system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
void printDeviceProperties(cudaDeviceProp prop) {
printf("Device name: %s\n", prop.name);
printf("Clock rate (KHz): %d\n", prop.clockRate);
printf("Compute: %d.%d\n", prop.major, prop.minor);
printf("Total number of SMs: %d\n", prop.multiProcessorCount);
printf("Device shares CPU ram directly: %d\n", prop.integrated);
printf("Device can map host memory into GPU virtual memory space: %d\n", prop.canMapHostMemory);
printf("Total global memory (bytes): %zu\n", prop.totalGlobalMem);
printf("Total constant memory (bytes): %zu\n", prop.totalConstMem);
for (int i = 0; i < 3; i++) printf("Blocks per dimension %d: %d\n", i, prop.maxGridSize[i]);
printf("Shared memory per block (bytes): %zu\n", prop.sharedMemPerBlock);
printf("Registers per block: %d\n", prop.regsPerBlock);
printf("Threads per block: %d\n", prop.maxThreadsPerBlock);
for (int i = 0; i < 3; i++) printf("Threads per dimension %d: %d\n", i, prop.maxThreadsDim[i]);
printf("Warp size (threads): %d\n", prop.warpSize);
}
int main() {
int num_devices = 0;
cudaGetDeviceCount(&num_devices);
printf("Number of GPUs: %d\n", num_devices);
printf("=======================================\n");
for (int i = 0; i < num_devices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printDeviceProperties(prop);
printf("=======================================\n");
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
void printDeviceProperties(cudaDeviceProp prop) {
printf("Device name: %s\n", prop.name);
printf("Clock rate (KHz): %d\n", prop.clockRate);
printf("Compute: %d.%d\n", prop.major, prop.minor);
printf("Total number of SMs: %d\n", prop.multiProcessorCount);
printf("Device shares CPU ram directly: %d\n", prop.integrated);
printf("Device can map host memory into GPU virtual memory space: %d\n", prop.canMapHostMemory);
printf("Total global memory (bytes): %zu\n", prop.totalGlobalMem);
printf("Total constant memory (bytes): %zu\n", prop.totalConstMem);
for (int i = 0; i < 3; i++) printf("Blocks per dimension %d: %d\n", i, prop.maxGridSize[i]);
printf("Shared memory per block (bytes): %zu\n", prop.sharedMemPerBlock);
printf("Registers per block: %d\n", prop.regsPerBlock);
printf("Threads per block: %d\n", prop.maxThreadsPerBlock);
for (int i = 0; i < 3; i++) printf("Threads per dimension %d: %d\n", i, prop.maxThreadsDim[i]);
printf("Warp size (threads): %d\n", prop.warpSize);
}
int main() {
int num_devices = 0;
cudaGetDeviceCount(&num_devices);
printf("Number of GPUs: %d\n", num_devices);
printf("=======================================\n");
for (int i = 0; i < num_devices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printDeviceProperties(prop);
printf("=======================================\n");
}
} | .file "tmpxft_00045ec0_00000000-6_device_prop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device name: %s\n"
.LC1:
.string "Clock rate (KHz): %d\n"
.LC2:
.string "Compute: %d.%d\n"
.LC3:
.string "Total number of SMs: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Device shares CPU ram directly: %d\n"
.align 8
.LC5:
.string "Device can map host memory into GPU virtual memory space: %d\n"
.align 8
.LC6:
.string "Total global memory (bytes): %zu\n"
.align 8
.LC7:
.string "Total constant memory (bytes): %zu\n"
.section .rodata.str1.1
.LC8:
.string "Blocks per dimension %d: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Shared memory per block (bytes): %zu\n"
.section .rodata.str1.1
.LC10:
.string "Registers per block: %d\n"
.LC11:
.string "Threads per block: %d\n"
.LC12:
.string "Threads per dimension %d: %d\n"
.LC13:
.string "Warp size (threads): %d\n"
.text
.globl _Z21printDeviceProperties14cudaDeviceProp
.type _Z21printDeviceProperties14cudaDeviceProp, @function
_Z21printDeviceProperties14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq 32(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %ecx
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 432(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L4:
movl 368(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L4
movq 328(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 356(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl 340(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z21printDeviceProperties14cudaDeviceProp, .-_Z21printDeviceProperties14cudaDeviceProp
.section .rodata.str1.1
.LC14:
.string "Number of GPUs: %d\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "=======================================\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L10
movl $0, %ebp
leaq .LC15(%rip), %r12
.L11:
leaq 16(%rsp), %rbx
movl %ebp, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep movsq
call _Z21printDeviceProperties14cudaDeviceProp
addq $1040, %rsp
.cfi_def_cfa_offset 1088
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jg .L11
.L10:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
void printDeviceProperties(cudaDeviceProp prop) {
printf("Device name: %s\n", prop.name);
printf("Clock rate (KHz): %d\n", prop.clockRate);
printf("Compute: %d.%d\n", prop.major, prop.minor);
printf("Total number of SMs: %d\n", prop.multiProcessorCount);
printf("Device shares CPU ram directly: %d\n", prop.integrated);
printf("Device can map host memory into GPU virtual memory space: %d\n", prop.canMapHostMemory);
printf("Total global memory (bytes): %zu\n", prop.totalGlobalMem);
printf("Total constant memory (bytes): %zu\n", prop.totalConstMem);
for (int i = 0; i < 3; i++) printf("Blocks per dimension %d: %d\n", i, prop.maxGridSize[i]);
printf("Shared memory per block (bytes): %zu\n", prop.sharedMemPerBlock);
printf("Registers per block: %d\n", prop.regsPerBlock);
printf("Threads per block: %d\n", prop.maxThreadsPerBlock);
for (int i = 0; i < 3; i++) printf("Threads per dimension %d: %d\n", i, prop.maxThreadsDim[i]);
printf("Warp size (threads): %d\n", prop.warpSize);
}
int main() {
int num_devices = 0;
cudaGetDeviceCount(&num_devices);
printf("Number of GPUs: %d\n", num_devices);
printf("=======================================\n");
for (int i = 0; i < num_devices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printDeviceProperties(prop);
printf("=======================================\n");
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
void printDeviceProperties(hipDeviceProp_t prop) {
printf("Device name: %s\n", prop.name);
printf("Clock rate (KHz): %d\n", prop.clockRate);
printf("Compute: %d.%d\n", prop.major, prop.minor);
printf("Total number of SMs: %d\n", prop.multiProcessorCount);
printf("Device shares CPU ram directly: %d\n", prop.integrated);
printf("Device can map host memory into GPU virtual memory space: %d\n", prop.canMapHostMemory);
printf("Total global memory (bytes): %zu\n", prop.totalGlobalMem);
printf("Total constant memory (bytes): %zu\n", prop.totalConstMem);
for (int i = 0; i < 3; i++) printf("Blocks per dimension %d: %d\n", i, prop.maxGridSize[i]);
printf("Shared memory per block (bytes): %zu\n", prop.sharedMemPerBlock);
printf("Registers per block: %d\n", prop.regsPerBlock);
printf("Threads per block: %d\n", prop.maxThreadsPerBlock);
for (int i = 0; i < 3; i++) printf("Threads per dimension %d: %d\n", i, prop.maxThreadsDim[i]);
printf("Warp size (threads): %d\n", prop.warpSize);
}
int main() {
int num_devices = 0;
hipGetDeviceCount(&num_devices);
printf("Number of GPUs: %d\n", num_devices);
printf("=======================================\n");
for (int i = 0; i < num_devices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printDeviceProperties(prop);
printf("=======================================\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void printDeviceProperties(hipDeviceProp_t prop) {
printf("Device name: %s\n", prop.name);
printf("Clock rate (KHz): %d\n", prop.clockRate);
printf("Compute: %d.%d\n", prop.major, prop.minor);
printf("Total number of SMs: %d\n", prop.multiProcessorCount);
printf("Device shares CPU ram directly: %d\n", prop.integrated);
printf("Device can map host memory into GPU virtual memory space: %d\n", prop.canMapHostMemory);
printf("Total global memory (bytes): %zu\n", prop.totalGlobalMem);
printf("Total constant memory (bytes): %zu\n", prop.totalConstMem);
for (int i = 0; i < 3; i++) printf("Blocks per dimension %d: %d\n", i, prop.maxGridSize[i]);
printf("Shared memory per block (bytes): %zu\n", prop.sharedMemPerBlock);
printf("Registers per block: %d\n", prop.regsPerBlock);
printf("Threads per block: %d\n", prop.maxThreadsPerBlock);
for (int i = 0; i < 3; i++) printf("Threads per dimension %d: %d\n", i, prop.maxThreadsDim[i]);
printf("Warp size (threads): %d\n", prop.warpSize);
}
int main() {
int num_devices = 0;
hipGetDeviceCount(&num_devices);
printf("Number of GPUs: %d\n", num_devices);
printf("=======================================\n");
for (int i = 0; i < num_devices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printDeviceProperties(prop);
printf("=======================================\n");
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void printDeviceProperties(hipDeviceProp_t prop) {
printf("Device name: %s\n", prop.name);
printf("Clock rate (KHz): %d\n", prop.clockRate);
printf("Compute: %d.%d\n", prop.major, prop.minor);
printf("Total number of SMs: %d\n", prop.multiProcessorCount);
printf("Device shares CPU ram directly: %d\n", prop.integrated);
printf("Device can map host memory into GPU virtual memory space: %d\n", prop.canMapHostMemory);
printf("Total global memory (bytes): %zu\n", prop.totalGlobalMem);
printf("Total constant memory (bytes): %zu\n", prop.totalConstMem);
for (int i = 0; i < 3; i++) printf("Blocks per dimension %d: %d\n", i, prop.maxGridSize[i]);
printf("Shared memory per block (bytes): %zu\n", prop.sharedMemPerBlock);
printf("Registers per block: %d\n", prop.regsPerBlock);
printf("Threads per block: %d\n", prop.maxThreadsPerBlock);
for (int i = 0; i < 3; i++) printf("Threads per dimension %d: %d\n", i, prop.maxThreadsDim[i]);
printf("Warp size (threads): %d\n", prop.warpSize);
}
int main() {
int num_devices = 0;
hipGetDeviceCount(&num_devices);
printf("Number of GPUs: %d\n", num_devices);
printf("=======================================\n");
for (int i = 0; i < num_devices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printDeviceProperties(prop);
printf("=======================================\n");
}
} | .text
.file "device_prop.hip"
.globl _Z21printDeviceProperties20hipDeviceProp_tR0600 # -- Begin function _Z21printDeviceProperties20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z21printDeviceProperties20hipDeviceProp_tR0600,@function
_Z21printDeviceProperties20hipDeviceProp_tR0600: # @_Z21printDeviceProperties20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 392(%rsp), %esi
movl 396(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 420(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 428(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
movl $.L.str.8, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_1
# %bb.2:
movq 296(%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
movl $.L.str.12, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4:
movl 308(%rbx), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21printDeviceProperties20hipDeviceProp_tR0600, .Lfunc_end0-_Z21printDeviceProperties20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 1476(%rsp)
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
movl 1476(%rsp), %esi
xorl %ebx, %ebx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 1476(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 1480(%rsp), %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %r14, %rsi
rep
callq _Z21printDeviceProperties20hipDeviceProp_tR0600
movl $.Lstr.1, %edi
callq puts@PLT
incl %ebx
cmpl 1476(%rsp), %ebx
jl .LBB1_2
.LBB1_3: # %._crit_edge
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device name: %s\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Clock rate (KHz): %d\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute: %d.%d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total number of SMs: %d\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device shares CPU ram directly: %d\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device can map host memory into GPU virtual memory space: %d\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total global memory (bytes): %zu\n"
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total constant memory (bytes): %zu\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Blocks per dimension %d: %d\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Shared memory per block (bytes): %zu\n"
.size .L.str.9, 38
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Registers per block: %d\n"
.size .L.str.10, 25
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Threads per block: %d\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Threads per dimension %d: %d\n"
.size .L.str.12, 30
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Warp size (threads): %d\n"
.size .L.str.13, 25
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Number of GPUs: %d\n"
.size .L.str.14, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "======================================="
.size .Lstr.1, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045ec0_00000000-6_device_prop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device name: %s\n"
.LC1:
.string "Clock rate (KHz): %d\n"
.LC2:
.string "Compute: %d.%d\n"
.LC3:
.string "Total number of SMs: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Device shares CPU ram directly: %d\n"
.align 8
.LC5:
.string "Device can map host memory into GPU virtual memory space: %d\n"
.align 8
.LC6:
.string "Total global memory (bytes): %zu\n"
.align 8
.LC7:
.string "Total constant memory (bytes): %zu\n"
.section .rodata.str1.1
.LC8:
.string "Blocks per dimension %d: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Shared memory per block (bytes): %zu\n"
.section .rodata.str1.1
.LC10:
.string "Registers per block: %d\n"
.LC11:
.string "Threads per block: %d\n"
.LC12:
.string "Threads per dimension %d: %d\n"
.LC13:
.string "Warp size (threads): %d\n"
.text
.globl _Z21printDeviceProperties14cudaDeviceProp
.type _Z21printDeviceProperties14cudaDeviceProp, @function
_Z21printDeviceProperties14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq 32(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %ecx
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 432(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L4:
movl 368(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L4
movq 328(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 356(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl 340(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z21printDeviceProperties14cudaDeviceProp, .-_Z21printDeviceProperties14cudaDeviceProp
.section .rodata.str1.1
.LC14:
.string "Number of GPUs: %d\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "=======================================\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L10
movl $0, %ebp
leaq .LC15(%rip), %r12
.L11:
leaq 16(%rsp), %rbx
movl %ebp, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep movsq
call _Z21printDeviceProperties14cudaDeviceProp
addq $1040, %rsp
.cfi_def_cfa_offset 1088
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jg .L11
.L10:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device_prop.hip"
.globl _Z21printDeviceProperties20hipDeviceProp_tR0600 # -- Begin function _Z21printDeviceProperties20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z21printDeviceProperties20hipDeviceProp_tR0600,@function
_Z21printDeviceProperties20hipDeviceProp_tR0600: # @_Z21printDeviceProperties20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 392(%rsp), %esi
movl 396(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 420(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 428(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 432(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
movl $.L.str.8, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_1
# %bb.2:
movq 296(%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
movl $.L.str.12, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4:
movl 308(%rbx), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21printDeviceProperties20hipDeviceProp_tR0600, .Lfunc_end0-_Z21printDeviceProperties20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 1476(%rsp)
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
movl 1476(%rsp), %esi
xorl %ebx, %ebx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 1476(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 1480(%rsp), %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %r14, %rsi
rep
callq _Z21printDeviceProperties20hipDeviceProp_tR0600
movl $.Lstr.1, %edi
callq puts@PLT
incl %ebx
cmpl 1476(%rsp), %ebx
jl .LBB1_2
.LBB1_3: # %._crit_edge
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device name: %s\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Clock rate (KHz): %d\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute: %d.%d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total number of SMs: %d\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device shares CPU ram directly: %d\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device can map host memory into GPU virtual memory space: %d\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total global memory (bytes): %zu\n"
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total constant memory (bytes): %zu\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Blocks per dimension %d: %d\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Shared memory per block (bytes): %zu\n"
.size .L.str.9, 38
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Registers per block: %d\n"
.size .L.str.10, 25
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Threads per block: %d\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Threads per dimension %d: %d\n"
.size .L.str.12, 30
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Warp size (threads): %d\n"
.size .L.str.13, 25
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Number of GPUs: %d\n"
.size .L.str.14, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "======================================="
.size .Lstr.1, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
const int digest_size = 256;
const int digest_size_bytes = digest_size / 8;
//cudaEvent_t start, stop;
#define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y))))
//__device__ __host__ inline const char* chars = "123abcABC";
__device__ const uint64_t RC[24] = {
0x0000000000000001, 0x0000000000008082, 0x800000000000808a,
0x8000000080008000, 0x000000000000808b, 0x0000000080000001,
0x8000000080008081, 0x8000000000008009, 0x000000000000008a,
0x0000000000000088, 0x0000000080008009, 0x000000008000000a,
0x000000008000808b, 0x800000000000008b, 0x8000000000008089,
0x8000000000008003, 0x8000000000008002, 0x8000000000000080,
0x000000000000800a, 0x800000008000000a, 0x8000000080008081,
0x8000000000008080, 0x0000000080000001, 0x8000000080008008
};
__device__ const int r[24] = {
1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14,
27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44
};
__device__ const int piln[24] = {
10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4,
15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1
};
//__device__ __host__ inline void generate_message(char* message, uint64_t tid, int* str_len) {
// int len = 0;
// const int num_chars = 94;
// char str[21];
// while (tid > 0) {
// str[len++] = chars[tid % num_chars];
// tid /= num_chars;
// }
//
// str[len] = '\0';
// memcpy(message, str, len + 1);
// *str_len = len;
//}
__device__ __host__ inline void keccak256(uint64_t state[25]) {
uint64_t temp, C[5];
int j;
for (int i = 0; i < 24; i++) {
// Theta
// for i = 0 to 5
// C[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ state[i + 15] ^ state[i + 20];
C[0] = state[0] ^ state[5] ^ state[10] ^ state[15] ^ state[20];
C[1] = state[1] ^ state[6] ^ state[11] ^ state[16] ^ state[21];
C[2] = state[2] ^ state[7] ^ state[12] ^ state[17] ^ state[22];
C[3] = state[3] ^ state[8] ^ state[13] ^ state[18] ^ state[23];
C[4] = state[4] ^ state[9] ^ state[14] ^ state[19] ^ state[24];
// for i = 0 to 5
// temp = C[(i + 4) % 5] ^ ROTL64(C[(i + 1) % 5], 1);
// for j = 0 to 25, j += 5
// state[j + i] ^= temp;
temp = C[4] ^ ROTL64(C[1], 1);
state[0] ^= temp;
state[5] ^= temp;
state[10] ^= temp;
state[15] ^= temp;
state[20] ^= temp;
temp = C[0] ^ ROTL64(C[2], 1);
state[1] ^= temp;
state[6] ^= temp;
state[11] ^= temp;
state[16] ^= temp;
state[21] ^= temp;
temp = C[1] ^ ROTL64(C[3], 1);
state[2] ^= temp;
state[7] ^= temp;
state[12] ^= temp;
state[17] ^= temp;
state[22] ^= temp;
temp = C[2] ^ ROTL64(C[4], 1);
state[3] ^= temp;
state[8] ^= temp;
state[13] ^= temp;
state[18] ^= temp;
state[23] ^= temp;
temp = C[3] ^ ROTL64(C[0], 1);
state[4] ^= temp;
state[9] ^= temp;
state[14] ^= temp;
state[19] ^= temp;
state[24] ^= temp;
// Rho Pi
// for i = 0 to 24
// j = piln[i];
// C[0] = state[j];
// state[j] = ROTL64(temp, r[i]);
// temp = C[0];
temp = state[1];
j = piln[0];
C[0] = state[j];
state[j] = ROTL64(temp, r[0]);
temp = C[0];
j = piln[1];
C[0] = state[j];
state[j] = ROTL64(temp, r[1]);
temp = C[0];
j = piln[2];
C[0] = state[j];
state[j] = ROTL64(temp, r[2]);
temp = C[0];
j = piln[3];
C[0] = state[j];
state[j] = ROTL64(temp, r[3]);
temp = C[0];
j = piln[4];
C[0] = state[j];
state[j] = ROTL64(temp, r[4]);
temp = C[0];
j = piln[5];
C[0] = state[j];
state[j] = ROTL64(temp, r[5]);
temp = C[0];
j = piln[6];
C[0] = state[j];
state[j] = ROTL64(temp, r[6]);
temp = C[0];
j = piln[7];
C[0] = state[j];
state[j] = ROTL64(temp, r[7]);
temp = C[0];
j = piln[8];
C[0] = state[j];
state[j] = ROTL64(temp, r[8]);
temp = C[0];
j = piln[9];
C[0] = state[j];
state[j] = ROTL64(temp, r[9]);
temp = C[0];
j = piln[10];
C[0] = state[j];
state[j] = ROTL64(temp, r[10]);
temp = C[0];
j = piln[11];
C[0] = state[j];
state[j] = ROTL64(temp, r[11]);
temp = C[0];
j = piln[12];
C[0] = state[j];
state[j] = ROTL64(temp, r[12]);
temp = C[0];
j = piln[13];
C[0] = state[j];
state[j] = ROTL64(temp, r[13]);
temp = C[0];
j = piln[14];
C[0] = state[j];
state[j] = ROTL64(temp, r[14]);
temp = C[0];
j = piln[15];
C[0] = state[j];
state[j] = ROTL64(temp, r[15]);
temp = C[0];
j = piln[16];
C[0] = state[j];
state[j] = ROTL64(temp, r[16]);
temp = C[0];
j = piln[17];
C[0] = state[j];
state[j] = ROTL64(temp, r[17]);
temp = C[0];
j = piln[18];
C[0] = state[j];
state[j] = ROTL64(temp, r[18]);
temp = C[0];
j = piln[19];
C[0] = state[j];
state[j] = ROTL64(temp, r[19]);
temp = C[0];
j = piln[20];
C[0] = state[j];
state[j] = ROTL64(temp, r[20]);
temp = C[0];
j = piln[21];
C[0] = state[j];
state[j] = ROTL64(temp, r[21]);
temp = C[0];
j = piln[22];
C[0] = state[j];
state[j] = ROTL64(temp, r[22]);
temp = C[0];
j = piln[23];
C[0] = state[j];
state[j] = ROTL64(temp, r[23]);
temp = C[0];
// Chi
// for j = 0 to 25, j += 5
// for i = 0 to 5
// C[i] = state[j + i];
// for i = 0 to 5
// state[j + 1] ^= (~C[(i + 1) % 5]) & C[(i + 2) % 5];
C[0] = state[0];
C[1] = state[1];
C[2] = state[2];
C[3] = state[3];
C[4] = state[4];
state[0] ^= (~C[1]) & C[2];
state[1] ^= (~C[2]) & C[3];
state[2] ^= (~C[3]) & C[4];
state[3] ^= (~C[4]) & C[0];
state[4] ^= (~C[0]) & C[1];
C[0] = state[5];
C[1] = state[6];
C[2] = state[7];
C[3] = state[8];
C[4] = state[9];
state[5] ^= (~C[1]) & C[2];
state[6] ^= (~C[2]) & C[3];
state[7] ^= (~C[3]) & C[4];
state[8] ^= (~C[4]) & C[0];
state[9] ^= (~C[0]) & C[1];
C[0] = state[10];
C[1] = state[11];
C[2] = state[12];
C[3] = state[13];
C[4] = state[14];
state[10] ^= (~C[1]) & C[2];
state[11] ^= (~C[2]) & C[3];
state[12] ^= (~C[3]) & C[4];
state[13] ^= (~C[4]) & C[0];
state[14] ^= (~C[0]) & C[1];
C[0] = state[15];
C[1] = state[16];
C[2] = state[17];
C[3] = state[18];
C[4] = state[19];
state[15] ^= (~C[1]) & C[2];
state[16] ^= (~C[2]) & C[3];
state[17] ^= (~C[3]) & C[4];
state[18] ^= (~C[4]) & C[0];
state[19] ^= (~C[0]) & C[1];
C[0] = state[20];
C[1] = state[21];
C[2] = state[22];
C[3] = state[23];
C[4] = state[24];
state[20] ^= (~C[1]) & C[2];
state[21] ^= (~C[2]) & C[3];
state[22] ^= (~C[3]) & C[4];
state[23] ^= (~C[4]) & C[0];
state[24] ^= (~C[0]) & C[1];
// Iota
state[0] ^= RC[i];
}
}
__device__ __host__ inline void keccak(const char* message, int message_len, unsigned char* output, int output_len) {
uint64_t state[25];
uint8_t temp[144];
int rsize = 136;
int rsize_byte = 17;
memset(state, 0, sizeof(state));
for (; message_len >= rsize; message_len -= rsize, message += rsize) {
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)message)[i];
}
keccak256(state);
}
// last block and padding
memcpy(temp, message, message_len);
temp[message_len++] = 1;
memset(temp + message_len, 0, rsize - message_len);
temp[rsize - 1] |= 0x80;
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)temp)[i];
}
keccak256(state);
memcpy(output, state, output_len);
}
//
//__global__ void benchmark(const char* messages, unsigned char* output, int num_messages) {
// const int str_len = 6;
// const int output_len = 32;
// int tid = threadIdx.x + (blockIdx.x * blockDim.x);
// int num_threads = blockDim.x * gridDim.x;
//
// for (; tid < num_messages; tid += num_threads)
// {
// keccak(&messages[tid * str_len], str_len, &output[tid * output_len], output_len);
// }
//}
//
//
//void gpu_init() {
// cudaDeviceProp device_prop;
// int device_count, block_size;
//
// cudaGetDeviceCount(&device_count);
// if (device_count != 1) {
// exit(EXIT_FAILURE);
// }
//
// if (cudaGetDeviceProperties(&device_prop, 0) != cudaSuccess) {
// exit(EXIT_FAILURE);
// }
//
// number_threads = device_prop.maxThreadsPerBlock;
// number_multi_processors = device_prop.multiProcessorCount;
// max_threads_per_mp = device_prop.maxThreadsPerMultiProcessor;
// block_size = (max_threads_per_mp / gcd(max_threads_per_mp, number_threads));
// number_threads = max_threads_per_mp / block_size;
// number_blocks = block_size * number_multi_processors;
// clock_speed = (int)(device_prop.memoryClockRate * 1000 * 1000);
//}
//int gcd(int a, int b) {
// return (a == 0) ? b : gcd(b % a, a);
//}
//char* read_in_messages(char* file_name) {
// FILE* f;
// if (!(f = fopen(file_name, "r")))
// {
// printf("Error opening file %s", file_name);
// exit(1);
// }
//
// char* messages = (char*)malloc(sizeof(char) * num_messages * str_length);
// if (messages == NULL)
// {
// perror("Error allocating memory for list of Strings.\n");
// exit(1);
// }
//
// int index = 0;
// char buf[10];
// while (1) {
// if (fgets(buf, str_length + 1, f) == NULL)
// break;
// buf[strlen(buf) - 1] = '\0';
// memcpy(&messages[index], buf, str_length);
// index += str_length - 1;
// }
//
// return messages;
//}
//
//
//
//
//void runBenchmarks(char* file_name, int num_messages) {
// float h_to_d_time = 0.0;
// float comp_time = 0.0;
// float d_to_h_time = 0.0;
// float total_time = 0.0;
// float elapsed_time;
// int hashes_per_sec;
//
// size_t array_size = sizeof(char) * str_length * num_messages;
// size_t output_size = digest_size_bytes * num_messages;
//
// // Allocate host arrays
// char* h_messages = read_in_messages(file_name);
// unsigned char* h_output = (unsigned char*)malloc(output_size);
//
// char* d_messages;
// unsigned char* d_output;
//
// // Allocate device arrays
// cudaMalloc((void**)&d_messages, array_size);
// cudaMalloc((void**)&d_output, output_size);
//
// int number_runs = 25;
// // Copy Strings from host to device arrays
// for (int j = 0; j < number_runs; j++) {
// benchmark << <number_blocks, number_threads >> > (d_messages, d_output, num_messages);
// }
//
// // Free arrays from memory
// free(h_messages);
// free(h_output);
// cudaFree(d_messages);
// cudaFree(d_output);
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
const int digest_size = 256;
const int digest_size_bytes = digest_size / 8;
//cudaEvent_t start, stop;
#define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y))))
//__device__ __host__ inline const char* chars = "123abcABC";
__device__ const uint64_t RC[24] = {
0x0000000000000001, 0x0000000000008082, 0x800000000000808a,
0x8000000080008000, 0x000000000000808b, 0x0000000080000001,
0x8000000080008081, 0x8000000000008009, 0x000000000000008a,
0x0000000000000088, 0x0000000080008009, 0x000000008000000a,
0x000000008000808b, 0x800000000000008b, 0x8000000000008089,
0x8000000000008003, 0x8000000000008002, 0x8000000000000080,
0x000000000000800a, 0x800000008000000a, 0x8000000080008081,
0x8000000000008080, 0x0000000080000001, 0x8000000080008008
};
__device__ const int r[24] = {
1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14,
27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44
};
__device__ const int piln[24] = {
10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4,
15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1
};
//__device__ __host__ inline void generate_message(char* message, uint64_t tid, int* str_len) {
// int len = 0;
// const int num_chars = 94;
// char str[21];
// while (tid > 0) {
// str[len++] = chars[tid % num_chars];
// tid /= num_chars;
// }
//
// str[len] = '\0';
// memcpy(message, str, len + 1);
// *str_len = len;
//}
__device__ __host__ inline void keccak256(uint64_t state[25]) {
uint64_t temp, C[5];
int j;
for (int i = 0; i < 24; i++) {
// Theta
// for i = 0 to 5
// C[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ state[i + 15] ^ state[i + 20];
C[0] = state[0] ^ state[5] ^ state[10] ^ state[15] ^ state[20];
C[1] = state[1] ^ state[6] ^ state[11] ^ state[16] ^ state[21];
C[2] = state[2] ^ state[7] ^ state[12] ^ state[17] ^ state[22];
C[3] = state[3] ^ state[8] ^ state[13] ^ state[18] ^ state[23];
C[4] = state[4] ^ state[9] ^ state[14] ^ state[19] ^ state[24];
// for i = 0 to 5
// temp = C[(i + 4) % 5] ^ ROTL64(C[(i + 1) % 5], 1);
// for j = 0 to 25, j += 5
// state[j + i] ^= temp;
temp = C[4] ^ ROTL64(C[1], 1);
state[0] ^= temp;
state[5] ^= temp;
state[10] ^= temp;
state[15] ^= temp;
state[20] ^= temp;
temp = C[0] ^ ROTL64(C[2], 1);
state[1] ^= temp;
state[6] ^= temp;
state[11] ^= temp;
state[16] ^= temp;
state[21] ^= temp;
temp = C[1] ^ ROTL64(C[3], 1);
state[2] ^= temp;
state[7] ^= temp;
state[12] ^= temp;
state[17] ^= temp;
state[22] ^= temp;
temp = C[2] ^ ROTL64(C[4], 1);
state[3] ^= temp;
state[8] ^= temp;
state[13] ^= temp;
state[18] ^= temp;
state[23] ^= temp;
temp = C[3] ^ ROTL64(C[0], 1);
state[4] ^= temp;
state[9] ^= temp;
state[14] ^= temp;
state[19] ^= temp;
state[24] ^= temp;
// Rho Pi
// for i = 0 to 24
// j = piln[i];
// C[0] = state[j];
// state[j] = ROTL64(temp, r[i]);
// temp = C[0];
temp = state[1];
j = piln[0];
C[0] = state[j];
state[j] = ROTL64(temp, r[0]);
temp = C[0];
j = piln[1];
C[0] = state[j];
state[j] = ROTL64(temp, r[1]);
temp = C[0];
j = piln[2];
C[0] = state[j];
state[j] = ROTL64(temp, r[2]);
temp = C[0];
j = piln[3];
C[0] = state[j];
state[j] = ROTL64(temp, r[3]);
temp = C[0];
j = piln[4];
C[0] = state[j];
state[j] = ROTL64(temp, r[4]);
temp = C[0];
j = piln[5];
C[0] = state[j];
state[j] = ROTL64(temp, r[5]);
temp = C[0];
j = piln[6];
C[0] = state[j];
state[j] = ROTL64(temp, r[6]);
temp = C[0];
j = piln[7];
C[0] = state[j];
state[j] = ROTL64(temp, r[7]);
temp = C[0];
j = piln[8];
C[0] = state[j];
state[j] = ROTL64(temp, r[8]);
temp = C[0];
j = piln[9];
C[0] = state[j];
state[j] = ROTL64(temp, r[9]);
temp = C[0];
j = piln[10];
C[0] = state[j];
state[j] = ROTL64(temp, r[10]);
temp = C[0];
j = piln[11];
C[0] = state[j];
state[j] = ROTL64(temp, r[11]);
temp = C[0];
j = piln[12];
C[0] = state[j];
state[j] = ROTL64(temp, r[12]);
temp = C[0];
j = piln[13];
C[0] = state[j];
state[j] = ROTL64(temp, r[13]);
temp = C[0];
j = piln[14];
C[0] = state[j];
state[j] = ROTL64(temp, r[14]);
temp = C[0];
j = piln[15];
C[0] = state[j];
state[j] = ROTL64(temp, r[15]);
temp = C[0];
j = piln[16];
C[0] = state[j];
state[j] = ROTL64(temp, r[16]);
temp = C[0];
j = piln[17];
C[0] = state[j];
state[j] = ROTL64(temp, r[17]);
temp = C[0];
j = piln[18];
C[0] = state[j];
state[j] = ROTL64(temp, r[18]);
temp = C[0];
j = piln[19];
C[0] = state[j];
state[j] = ROTL64(temp, r[19]);
temp = C[0];
j = piln[20];
C[0] = state[j];
state[j] = ROTL64(temp, r[20]);
temp = C[0];
j = piln[21];
C[0] = state[j];
state[j] = ROTL64(temp, r[21]);
temp = C[0];
j = piln[22];
C[0] = state[j];
state[j] = ROTL64(temp, r[22]);
temp = C[0];
j = piln[23];
C[0] = state[j];
state[j] = ROTL64(temp, r[23]);
temp = C[0];
// Chi
// for j = 0 to 25, j += 5
// for i = 0 to 5
// C[i] = state[j + i];
// for i = 0 to 5
// state[j + 1] ^= (~C[(i + 1) % 5]) & C[(i + 2) % 5];
C[0] = state[0];
C[1] = state[1];
C[2] = state[2];
C[3] = state[3];
C[4] = state[4];
state[0] ^= (~C[1]) & C[2];
state[1] ^= (~C[2]) & C[3];
state[2] ^= (~C[3]) & C[4];
state[3] ^= (~C[4]) & C[0];
state[4] ^= (~C[0]) & C[1];
C[0] = state[5];
C[1] = state[6];
C[2] = state[7];
C[3] = state[8];
C[4] = state[9];
state[5] ^= (~C[1]) & C[2];
state[6] ^= (~C[2]) & C[3];
state[7] ^= (~C[3]) & C[4];
state[8] ^= (~C[4]) & C[0];
state[9] ^= (~C[0]) & C[1];
C[0] = state[10];
C[1] = state[11];
C[2] = state[12];
C[3] = state[13];
C[4] = state[14];
state[10] ^= (~C[1]) & C[2];
state[11] ^= (~C[2]) & C[3];
state[12] ^= (~C[3]) & C[4];
state[13] ^= (~C[4]) & C[0];
state[14] ^= (~C[0]) & C[1];
C[0] = state[15];
C[1] = state[16];
C[2] = state[17];
C[3] = state[18];
C[4] = state[19];
state[15] ^= (~C[1]) & C[2];
state[16] ^= (~C[2]) & C[3];
state[17] ^= (~C[3]) & C[4];
state[18] ^= (~C[4]) & C[0];
state[19] ^= (~C[0]) & C[1];
C[0] = state[20];
C[1] = state[21];
C[2] = state[22];
C[3] = state[23];
C[4] = state[24];
state[20] ^= (~C[1]) & C[2];
state[21] ^= (~C[2]) & C[3];
state[22] ^= (~C[3]) & C[4];
state[23] ^= (~C[4]) & C[0];
state[24] ^= (~C[0]) & C[1];
// Iota
state[0] ^= RC[i];
}
}
__device__ __host__ inline void keccak(const char* message, int message_len, unsigned char* output, int output_len) {
uint64_t state[25];
uint8_t temp[144];
int rsize = 136;
int rsize_byte = 17;
memset(state, 0, sizeof(state));
for (; message_len >= rsize; message_len -= rsize, message += rsize) {
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)message)[i];
}
keccak256(state);
}
// last block and padding
memcpy(temp, message, message_len);
temp[message_len++] = 1;
memset(temp + message_len, 0, rsize - message_len);
temp[rsize - 1] |= 0x80;
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)temp)[i];
}
keccak256(state);
memcpy(output, state, output_len);
}
//
//__global__ void benchmark(const char* messages, unsigned char* output, int num_messages) {
// const int str_len = 6;
// const int output_len = 32;
// int tid = threadIdx.x + (blockIdx.x * blockDim.x);
// int num_threads = blockDim.x * gridDim.x;
//
// for (; tid < num_messages; tid += num_threads)
// {
// keccak(&messages[tid * str_len], str_len, &output[tid * output_len], output_len);
// }
//}
//
//
//void gpu_init() {
// cudaDeviceProp device_prop;
// int device_count, block_size;
//
// cudaGetDeviceCount(&device_count);
// if (device_count != 1) {
// exit(EXIT_FAILURE);
// }
//
// if (cudaGetDeviceProperties(&device_prop, 0) != cudaSuccess) {
// exit(EXIT_FAILURE);
// }
//
// number_threads = device_prop.maxThreadsPerBlock;
// number_multi_processors = device_prop.multiProcessorCount;
// max_threads_per_mp = device_prop.maxThreadsPerMultiProcessor;
// block_size = (max_threads_per_mp / gcd(max_threads_per_mp, number_threads));
// number_threads = max_threads_per_mp / block_size;
// number_blocks = block_size * number_multi_processors;
// clock_speed = (int)(device_prop.memoryClockRate * 1000 * 1000);
//}
//int gcd(int a, int b) {
// return (a == 0) ? b : gcd(b % a, a);
//}
//char* read_in_messages(char* file_name) {
// FILE* f;
// if (!(f = fopen(file_name, "r")))
// {
// printf("Error opening file %s", file_name);
// exit(1);
// }
//
// char* messages = (char*)malloc(sizeof(char) * num_messages * str_length);
// if (messages == NULL)
// {
// perror("Error allocating memory for list of Strings.\n");
// exit(1);
// }
//
// int index = 0;
// char buf[10];
// while (1) {
// if (fgets(buf, str_length + 1, f) == NULL)
// break;
// buf[strlen(buf) - 1] = '\0';
// memcpy(&messages[index], buf, str_length);
// index += str_length - 1;
// }
//
// return messages;
//}
//
//
//
//
//void runBenchmarks(char* file_name, int num_messages) {
// float h_to_d_time = 0.0;
// float comp_time = 0.0;
// float d_to_h_time = 0.0;
// float total_time = 0.0;
// float elapsed_time;
// int hashes_per_sec;
//
// size_t array_size = sizeof(char) * str_length * num_messages;
// size_t output_size = digest_size_bytes * num_messages;
//
// // Allocate host arrays
// char* h_messages = read_in_messages(file_name);
// unsigned char* h_output = (unsigned char*)malloc(output_size);
//
// char* d_messages;
// unsigned char* d_output;
//
// // Allocate device arrays
// cudaMalloc((void**)&d_messages, array_size);
// cudaMalloc((void**)&d_output, output_size);
//
// int number_runs = 25;
// // Copy Strings from host to device arrays
// for (int j = 0; j < number_runs; j++) {
// benchmark << <number_blocks, number_threads >> > (d_messages, d_output, num_messages);
// }
//
// // Free arrays from memory
// free(h_messages);
// free(h_output);
// cudaFree(d_messages);
// cudaFree(d_output);
//} | .file "tmpxft_0018e6c4_00000000-6_keccak.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "precalc_xorwow_matrix"
.LC1:
.string "precalc_xorwow_offset_matrix"
.LC2:
.string "mrg32k3aM1"
.LC3:
.string "mrg32k3aM2"
.LC4:
.string "mrg32k3aM1SubSeq"
.LC5:
.string "mrg32k3aM2SubSeq"
.LC6:
.string "mrg32k3aM1Seq"
.LC7:
.string "mrg32k3aM2Seq"
.LC8:
.string "__cr_lgamma_table"
.LC9:
.string "RC"
.LC10:
.string "r"
.LC11:
.string "piln"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $192, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2RC(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $96, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1r(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $96, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4piln(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 32
.type _ZL4piln, @object
.size _ZL4piln, 96
_ZL4piln:
.long 10
.long 7
.long 11
.long 17
.long 18
.long 3
.long 5
.long 16
.long 8
.long 21
.long 24
.long 4
.long 15
.long 23
.long 19
.long 13
.long 12
.long 2
.long 20
.long 14
.long 22
.long 9
.long 6
.long 1
.align 32
.type _ZL1r, @object
.size _ZL1r, 96
_ZL1r:
.long 1
.long 3
.long 6
.long 10
.long 15
.long 21
.long 28
.long 36
.long 45
.long 55
.long 2
.long 14
.long 27
.long 41
.long 56
.long 8
.long 25
.long 43
.long 62
.long 18
.long 39
.long 61
.long 20
.long 44
.align 32
.type _ZL2RC, @object
.size _ZL2RC, 192
_ZL2RC:
.quad 1
.quad 32898
.quad -9223372036854742902
.quad -9223372034707259392
.quad 32907
.quad 2147483649
.quad -9223372034707259263
.quad -9223372036854743031
.quad 138
.quad 136
.quad 2147516425
.quad 2147483658
.quad 2147516555
.quad -9223372036854775669
.quad -9223372036854742903
.quad -9223372036854743037
.quad -9223372036854743038
.quad -9223372036854775680
.quad 32778
.quad -9223372034707292150
.quad -9223372034707259263
.quad -9223372036854742912
.quad 2147483649
.quad -9223372034707259384
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
const int digest_size = 256;
const int digest_size_bytes = digest_size / 8;
//cudaEvent_t start, stop;
#define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y))))
//__device__ __host__ inline const char* chars = "123abcABC";
__device__ const uint64_t RC[24] = {
0x0000000000000001, 0x0000000000008082, 0x800000000000808a,
0x8000000080008000, 0x000000000000808b, 0x0000000080000001,
0x8000000080008081, 0x8000000000008009, 0x000000000000008a,
0x0000000000000088, 0x0000000080008009, 0x000000008000000a,
0x000000008000808b, 0x800000000000008b, 0x8000000000008089,
0x8000000000008003, 0x8000000000008002, 0x8000000000000080,
0x000000000000800a, 0x800000008000000a, 0x8000000080008081,
0x8000000000008080, 0x0000000080000001, 0x8000000080008008
};
__device__ const int r[24] = {
1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14,
27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44
};
__device__ const int piln[24] = {
10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4,
15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1
};
//__device__ __host__ inline void generate_message(char* message, uint64_t tid, int* str_len) {
// int len = 0;
// const int num_chars = 94;
// char str[21];
// while (tid > 0) {
// str[len++] = chars[tid % num_chars];
// tid /= num_chars;
// }
//
// str[len] = '\0';
// memcpy(message, str, len + 1);
// *str_len = len;
//}
__device__ __host__ inline void keccak256(uint64_t state[25]) {
uint64_t temp, C[5];
int j;
for (int i = 0; i < 24; i++) {
// Theta
// for i = 0 to 5
// C[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ state[i + 15] ^ state[i + 20];
C[0] = state[0] ^ state[5] ^ state[10] ^ state[15] ^ state[20];
C[1] = state[1] ^ state[6] ^ state[11] ^ state[16] ^ state[21];
C[2] = state[2] ^ state[7] ^ state[12] ^ state[17] ^ state[22];
C[3] = state[3] ^ state[8] ^ state[13] ^ state[18] ^ state[23];
C[4] = state[4] ^ state[9] ^ state[14] ^ state[19] ^ state[24];
// for i = 0 to 5
// temp = C[(i + 4) % 5] ^ ROTL64(C[(i + 1) % 5], 1);
// for j = 0 to 25, j += 5
// state[j + i] ^= temp;
temp = C[4] ^ ROTL64(C[1], 1);
state[0] ^= temp;
state[5] ^= temp;
state[10] ^= temp;
state[15] ^= temp;
state[20] ^= temp;
temp = C[0] ^ ROTL64(C[2], 1);
state[1] ^= temp;
state[6] ^= temp;
state[11] ^= temp;
state[16] ^= temp;
state[21] ^= temp;
temp = C[1] ^ ROTL64(C[3], 1);
state[2] ^= temp;
state[7] ^= temp;
state[12] ^= temp;
state[17] ^= temp;
state[22] ^= temp;
temp = C[2] ^ ROTL64(C[4], 1);
state[3] ^= temp;
state[8] ^= temp;
state[13] ^= temp;
state[18] ^= temp;
state[23] ^= temp;
temp = C[3] ^ ROTL64(C[0], 1);
state[4] ^= temp;
state[9] ^= temp;
state[14] ^= temp;
state[19] ^= temp;
state[24] ^= temp;
// Rho Pi
// for i = 0 to 24
// j = piln[i];
// C[0] = state[j];
// state[j] = ROTL64(temp, r[i]);
// temp = C[0];
temp = state[1];
j = piln[0];
C[0] = state[j];
state[j] = ROTL64(temp, r[0]);
temp = C[0];
j = piln[1];
C[0] = state[j];
state[j] = ROTL64(temp, r[1]);
temp = C[0];
j = piln[2];
C[0] = state[j];
state[j] = ROTL64(temp, r[2]);
temp = C[0];
j = piln[3];
C[0] = state[j];
state[j] = ROTL64(temp, r[3]);
temp = C[0];
j = piln[4];
C[0] = state[j];
state[j] = ROTL64(temp, r[4]);
temp = C[0];
j = piln[5];
C[0] = state[j];
state[j] = ROTL64(temp, r[5]);
temp = C[0];
j = piln[6];
C[0] = state[j];
state[j] = ROTL64(temp, r[6]);
temp = C[0];
j = piln[7];
C[0] = state[j];
state[j] = ROTL64(temp, r[7]);
temp = C[0];
j = piln[8];
C[0] = state[j];
state[j] = ROTL64(temp, r[8]);
temp = C[0];
j = piln[9];
C[0] = state[j];
state[j] = ROTL64(temp, r[9]);
temp = C[0];
j = piln[10];
C[0] = state[j];
state[j] = ROTL64(temp, r[10]);
temp = C[0];
j = piln[11];
C[0] = state[j];
state[j] = ROTL64(temp, r[11]);
temp = C[0];
j = piln[12];
C[0] = state[j];
state[j] = ROTL64(temp, r[12]);
temp = C[0];
j = piln[13];
C[0] = state[j];
state[j] = ROTL64(temp, r[13]);
temp = C[0];
j = piln[14];
C[0] = state[j];
state[j] = ROTL64(temp, r[14]);
temp = C[0];
j = piln[15];
C[0] = state[j];
state[j] = ROTL64(temp, r[15]);
temp = C[0];
j = piln[16];
C[0] = state[j];
state[j] = ROTL64(temp, r[16]);
temp = C[0];
j = piln[17];
C[0] = state[j];
state[j] = ROTL64(temp, r[17]);
temp = C[0];
j = piln[18];
C[0] = state[j];
state[j] = ROTL64(temp, r[18]);
temp = C[0];
j = piln[19];
C[0] = state[j];
state[j] = ROTL64(temp, r[19]);
temp = C[0];
j = piln[20];
C[0] = state[j];
state[j] = ROTL64(temp, r[20]);
temp = C[0];
j = piln[21];
C[0] = state[j];
state[j] = ROTL64(temp, r[21]);
temp = C[0];
j = piln[22];
C[0] = state[j];
state[j] = ROTL64(temp, r[22]);
temp = C[0];
j = piln[23];
C[0] = state[j];
state[j] = ROTL64(temp, r[23]);
temp = C[0];
// Chi
// for j = 0 to 25, j += 5
// for i = 0 to 5
// C[i] = state[j + i];
// for i = 0 to 5
// state[j + 1] ^= (~C[(i + 1) % 5]) & C[(i + 2) % 5];
C[0] = state[0];
C[1] = state[1];
C[2] = state[2];
C[3] = state[3];
C[4] = state[4];
state[0] ^= (~C[1]) & C[2];
state[1] ^= (~C[2]) & C[3];
state[2] ^= (~C[3]) & C[4];
state[3] ^= (~C[4]) & C[0];
state[4] ^= (~C[0]) & C[1];
C[0] = state[5];
C[1] = state[6];
C[2] = state[7];
C[3] = state[8];
C[4] = state[9];
state[5] ^= (~C[1]) & C[2];
state[6] ^= (~C[2]) & C[3];
state[7] ^= (~C[3]) & C[4];
state[8] ^= (~C[4]) & C[0];
state[9] ^= (~C[0]) & C[1];
C[0] = state[10];
C[1] = state[11];
C[2] = state[12];
C[3] = state[13];
C[4] = state[14];
state[10] ^= (~C[1]) & C[2];
state[11] ^= (~C[2]) & C[3];
state[12] ^= (~C[3]) & C[4];
state[13] ^= (~C[4]) & C[0];
state[14] ^= (~C[0]) & C[1];
C[0] = state[15];
C[1] = state[16];
C[2] = state[17];
C[3] = state[18];
C[4] = state[19];
state[15] ^= (~C[1]) & C[2];
state[16] ^= (~C[2]) & C[3];
state[17] ^= (~C[3]) & C[4];
state[18] ^= (~C[4]) & C[0];
state[19] ^= (~C[0]) & C[1];
C[0] = state[20];
C[1] = state[21];
C[2] = state[22];
C[3] = state[23];
C[4] = state[24];
state[20] ^= (~C[1]) & C[2];
state[21] ^= (~C[2]) & C[3];
state[22] ^= (~C[3]) & C[4];
state[23] ^= (~C[4]) & C[0];
state[24] ^= (~C[0]) & C[1];
// Iota
state[0] ^= RC[i];
}
}
__device__ __host__ inline void keccak(const char* message, int message_len, unsigned char* output, int output_len) {
uint64_t state[25];
uint8_t temp[144];
int rsize = 136;
int rsize_byte = 17;
memset(state, 0, sizeof(state));
for (; message_len >= rsize; message_len -= rsize, message += rsize) {
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)message)[i];
}
keccak256(state);
}
// last block and padding
memcpy(temp, message, message_len);
temp[message_len++] = 1;
memset(temp + message_len, 0, rsize - message_len);
temp[rsize - 1] |= 0x80;
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)temp)[i];
}
keccak256(state);
memcpy(output, state, output_len);
}
//
//__global__ void benchmark(const char* messages, unsigned char* output, int num_messages) {
// const int str_len = 6;
// const int output_len = 32;
// int tid = threadIdx.x + (blockIdx.x * blockDim.x);
// int num_threads = blockDim.x * gridDim.x;
//
// for (; tid < num_messages; tid += num_threads)
// {
// keccak(&messages[tid * str_len], str_len, &output[tid * output_len], output_len);
// }
//}
//
//
//void gpu_init() {
// cudaDeviceProp device_prop;
// int device_count, block_size;
//
// cudaGetDeviceCount(&device_count);
// if (device_count != 1) {
// exit(EXIT_FAILURE);
// }
//
// if (cudaGetDeviceProperties(&device_prop, 0) != cudaSuccess) {
// exit(EXIT_FAILURE);
// }
//
// number_threads = device_prop.maxThreadsPerBlock;
// number_multi_processors = device_prop.multiProcessorCount;
// max_threads_per_mp = device_prop.maxThreadsPerMultiProcessor;
// block_size = (max_threads_per_mp / gcd(max_threads_per_mp, number_threads));
// number_threads = max_threads_per_mp / block_size;
// number_blocks = block_size * number_multi_processors;
// clock_speed = (int)(device_prop.memoryClockRate * 1000 * 1000);
//}
//int gcd(int a, int b) {
// return (a == 0) ? b : gcd(b % a, a);
//}
//char* read_in_messages(char* file_name) {
// FILE* f;
// if (!(f = fopen(file_name, "r")))
// {
// printf("Error opening file %s", file_name);
// exit(1);
// }
//
// char* messages = (char*)malloc(sizeof(char) * num_messages * str_length);
// if (messages == NULL)
// {
// perror("Error allocating memory for list of Strings.\n");
// exit(1);
// }
//
// int index = 0;
// char buf[10];
// while (1) {
// if (fgets(buf, str_length + 1, f) == NULL)
// break;
// buf[strlen(buf) - 1] = '\0';
// memcpy(&messages[index], buf, str_length);
// index += str_length - 1;
// }
//
// return messages;
//}
//
//
//
//
//void runBenchmarks(char* file_name, int num_messages) {
// float h_to_d_time = 0.0;
// float comp_time = 0.0;
// float d_to_h_time = 0.0;
// float total_time = 0.0;
// float elapsed_time;
// int hashes_per_sec;
//
// size_t array_size = sizeof(char) * str_length * num_messages;
// size_t output_size = digest_size_bytes * num_messages;
//
// // Allocate host arrays
// char* h_messages = read_in_messages(file_name);
// unsigned char* h_output = (unsigned char*)malloc(output_size);
//
// char* d_messages;
// unsigned char* d_output;
//
// // Allocate device arrays
// cudaMalloc((void**)&d_messages, array_size);
// cudaMalloc((void**)&d_output, output_size);
//
// int number_runs = 25;
// // Copy Strings from host to device arrays
// for (int j = 0; j < number_runs; j++) {
// benchmark << <number_blocks, number_threads >> > (d_messages, d_output, num_messages);
// }
//
// // Free arrays from memory
// free(h_messages);
// free(h_output);
// cudaFree(d_messages);
// cudaFree(d_output);
//} | #include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
const int digest_size = 256;
const int digest_size_bytes = digest_size / 8;
//cudaEvent_t start, stop;
#define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y))))
//__device__ __host__ inline const char* chars = "123abcABC";
__device__ const uint64_t RC[24] = {
0x0000000000000001, 0x0000000000008082, 0x800000000000808a,
0x8000000080008000, 0x000000000000808b, 0x0000000080000001,
0x8000000080008081, 0x8000000000008009, 0x000000000000008a,
0x0000000000000088, 0x0000000080008009, 0x000000008000000a,
0x000000008000808b, 0x800000000000008b, 0x8000000000008089,
0x8000000000008003, 0x8000000000008002, 0x8000000000000080,
0x000000000000800a, 0x800000008000000a, 0x8000000080008081,
0x8000000000008080, 0x0000000080000001, 0x8000000080008008
};
__device__ const int r[24] = {
1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14,
27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44
};
__device__ const int piln[24] = {
10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4,
15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1
};
//__device__ __host__ inline void generate_message(char* message, uint64_t tid, int* str_len) {
// int len = 0;
// const int num_chars = 94;
// char str[21];
// while (tid > 0) {
// str[len++] = chars[tid % num_chars];
// tid /= num_chars;
// }
//
// str[len] = '\0';
// memcpy(message, str, len + 1);
// *str_len = len;
//}
__device__ __host__ inline void keccak256(uint64_t state[25]) {
uint64_t temp, C[5];
int j;
for (int i = 0; i < 24; i++) {
// Theta
// for i = 0 to 5
// C[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ state[i + 15] ^ state[i + 20];
C[0] = state[0] ^ state[5] ^ state[10] ^ state[15] ^ state[20];
C[1] = state[1] ^ state[6] ^ state[11] ^ state[16] ^ state[21];
C[2] = state[2] ^ state[7] ^ state[12] ^ state[17] ^ state[22];
C[3] = state[3] ^ state[8] ^ state[13] ^ state[18] ^ state[23];
C[4] = state[4] ^ state[9] ^ state[14] ^ state[19] ^ state[24];
// for i = 0 to 5
// temp = C[(i + 4) % 5] ^ ROTL64(C[(i + 1) % 5], 1);
// for j = 0 to 25, j += 5
// state[j + i] ^= temp;
temp = C[4] ^ ROTL64(C[1], 1);
state[0] ^= temp;
state[5] ^= temp;
state[10] ^= temp;
state[15] ^= temp;
state[20] ^= temp;
temp = C[0] ^ ROTL64(C[2], 1);
state[1] ^= temp;
state[6] ^= temp;
state[11] ^= temp;
state[16] ^= temp;
state[21] ^= temp;
temp = C[1] ^ ROTL64(C[3], 1);
state[2] ^= temp;
state[7] ^= temp;
state[12] ^= temp;
state[17] ^= temp;
state[22] ^= temp;
temp = C[2] ^ ROTL64(C[4], 1);
state[3] ^= temp;
state[8] ^= temp;
state[13] ^= temp;
state[18] ^= temp;
state[23] ^= temp;
temp = C[3] ^ ROTL64(C[0], 1);
state[4] ^= temp;
state[9] ^= temp;
state[14] ^= temp;
state[19] ^= temp;
state[24] ^= temp;
// Rho Pi
// for i = 0 to 24
// j = piln[i];
// C[0] = state[j];
// state[j] = ROTL64(temp, r[i]);
// temp = C[0];
temp = state[1];
j = piln[0];
C[0] = state[j];
state[j] = ROTL64(temp, r[0]);
temp = C[0];
j = piln[1];
C[0] = state[j];
state[j] = ROTL64(temp, r[1]);
temp = C[0];
j = piln[2];
C[0] = state[j];
state[j] = ROTL64(temp, r[2]);
temp = C[0];
j = piln[3];
C[0] = state[j];
state[j] = ROTL64(temp, r[3]);
temp = C[0];
j = piln[4];
C[0] = state[j];
state[j] = ROTL64(temp, r[4]);
temp = C[0];
j = piln[5];
C[0] = state[j];
state[j] = ROTL64(temp, r[5]);
temp = C[0];
j = piln[6];
C[0] = state[j];
state[j] = ROTL64(temp, r[6]);
temp = C[0];
j = piln[7];
C[0] = state[j];
state[j] = ROTL64(temp, r[7]);
temp = C[0];
j = piln[8];
C[0] = state[j];
state[j] = ROTL64(temp, r[8]);
temp = C[0];
j = piln[9];
C[0] = state[j];
state[j] = ROTL64(temp, r[9]);
temp = C[0];
j = piln[10];
C[0] = state[j];
state[j] = ROTL64(temp, r[10]);
temp = C[0];
j = piln[11];
C[0] = state[j];
state[j] = ROTL64(temp, r[11]);
temp = C[0];
j = piln[12];
C[0] = state[j];
state[j] = ROTL64(temp, r[12]);
temp = C[0];
j = piln[13];
C[0] = state[j];
state[j] = ROTL64(temp, r[13]);
temp = C[0];
j = piln[14];
C[0] = state[j];
state[j] = ROTL64(temp, r[14]);
temp = C[0];
j = piln[15];
C[0] = state[j];
state[j] = ROTL64(temp, r[15]);
temp = C[0];
j = piln[16];
C[0] = state[j];
state[j] = ROTL64(temp, r[16]);
temp = C[0];
j = piln[17];
C[0] = state[j];
state[j] = ROTL64(temp, r[17]);
temp = C[0];
j = piln[18];
C[0] = state[j];
state[j] = ROTL64(temp, r[18]);
temp = C[0];
j = piln[19];
C[0] = state[j];
state[j] = ROTL64(temp, r[19]);
temp = C[0];
j = piln[20];
C[0] = state[j];
state[j] = ROTL64(temp, r[20]);
temp = C[0];
j = piln[21];
C[0] = state[j];
state[j] = ROTL64(temp, r[21]);
temp = C[0];
j = piln[22];
C[0] = state[j];
state[j] = ROTL64(temp, r[22]);
temp = C[0];
j = piln[23];
C[0] = state[j];
state[j] = ROTL64(temp, r[23]);
temp = C[0];
// Chi
// for j = 0 to 25, j += 5
// for i = 0 to 5
// C[i] = state[j + i];
// for i = 0 to 5
// state[j + 1] ^= (~C[(i + 1) % 5]) & C[(i + 2) % 5];
C[0] = state[0];
C[1] = state[1];
C[2] = state[2];
C[3] = state[3];
C[4] = state[4];
state[0] ^= (~C[1]) & C[2];
state[1] ^= (~C[2]) & C[3];
state[2] ^= (~C[3]) & C[4];
state[3] ^= (~C[4]) & C[0];
state[4] ^= (~C[0]) & C[1];
C[0] = state[5];
C[1] = state[6];
C[2] = state[7];
C[3] = state[8];
C[4] = state[9];
state[5] ^= (~C[1]) & C[2];
state[6] ^= (~C[2]) & C[3];
state[7] ^= (~C[3]) & C[4];
state[8] ^= (~C[4]) & C[0];
state[9] ^= (~C[0]) & C[1];
C[0] = state[10];
C[1] = state[11];
C[2] = state[12];
C[3] = state[13];
C[4] = state[14];
state[10] ^= (~C[1]) & C[2];
state[11] ^= (~C[2]) & C[3];
state[12] ^= (~C[3]) & C[4];
state[13] ^= (~C[4]) & C[0];
state[14] ^= (~C[0]) & C[1];
C[0] = state[15];
C[1] = state[16];
C[2] = state[17];
C[3] = state[18];
C[4] = state[19];
state[15] ^= (~C[1]) & C[2];
state[16] ^= (~C[2]) & C[3];
state[17] ^= (~C[3]) & C[4];
state[18] ^= (~C[4]) & C[0];
state[19] ^= (~C[0]) & C[1];
C[0] = state[20];
C[1] = state[21];
C[2] = state[22];
C[3] = state[23];
C[4] = state[24];
state[20] ^= (~C[1]) & C[2];
state[21] ^= (~C[2]) & C[3];
state[22] ^= (~C[3]) & C[4];
state[23] ^= (~C[4]) & C[0];
state[24] ^= (~C[0]) & C[1];
// Iota
state[0] ^= RC[i];
}
}
__device__ __host__ inline void keccak(const char* message, int message_len, unsigned char* output, int output_len) {
uint64_t state[25];
uint8_t temp[144];
int rsize = 136;
int rsize_byte = 17;
memset(state, 0, sizeof(state));
for (; message_len >= rsize; message_len -= rsize, message += rsize) {
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)message)[i];
}
keccak256(state);
}
// last block and padding
memcpy(temp, message, message_len);
temp[message_len++] = 1;
memset(temp + message_len, 0, rsize - message_len);
temp[rsize - 1] |= 0x80;
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)temp)[i];
}
keccak256(state);
memcpy(output, state, output_len);
}
//
//__global__ void benchmark(const char* messages, unsigned char* output, int num_messages) {
// const int str_len = 6;
// const int output_len = 32;
// int tid = threadIdx.x + (blockIdx.x * blockDim.x);
// int num_threads = blockDim.x * gridDim.x;
//
// for (; tid < num_messages; tid += num_threads)
// {
// keccak(&messages[tid * str_len], str_len, &output[tid * output_len], output_len);
// }
//}
//
//
//void gpu_init() {
// cudaDeviceProp device_prop;
// int device_count, block_size;
//
// cudaGetDeviceCount(&device_count);
// if (device_count != 1) {
// exit(EXIT_FAILURE);
// }
//
// if (cudaGetDeviceProperties(&device_prop, 0) != cudaSuccess) {
// exit(EXIT_FAILURE);
// }
//
// number_threads = device_prop.maxThreadsPerBlock;
// number_multi_processors = device_prop.multiProcessorCount;
// max_threads_per_mp = device_prop.maxThreadsPerMultiProcessor;
// block_size = (max_threads_per_mp / gcd(max_threads_per_mp, number_threads));
// number_threads = max_threads_per_mp / block_size;
// number_blocks = block_size * number_multi_processors;
// clock_speed = (int)(device_prop.memoryClockRate * 1000 * 1000);
//}
//int gcd(int a, int b) {
// return (a == 0) ? b : gcd(b % a, a);
//}
//char* read_in_messages(char* file_name) {
// FILE* f;
// if (!(f = fopen(file_name, "r")))
// {
// printf("Error opening file %s", file_name);
// exit(1);
// }
//
// char* messages = (char*)malloc(sizeof(char) * num_messages * str_length);
// if (messages == NULL)
// {
// perror("Error allocating memory for list of Strings.\n");
// exit(1);
// }
//
// int index = 0;
// char buf[10];
// while (1) {
// if (fgets(buf, str_length + 1, f) == NULL)
// break;
// buf[strlen(buf) - 1] = '\0';
// memcpy(&messages[index], buf, str_length);
// index += str_length - 1;
// }
//
// return messages;
//}
//
//
//
//
//void runBenchmarks(char* file_name, int num_messages) {
// float h_to_d_time = 0.0;
// float comp_time = 0.0;
// float d_to_h_time = 0.0;
// float total_time = 0.0;
// float elapsed_time;
// int hashes_per_sec;
//
// size_t array_size = sizeof(char) * str_length * num_messages;
// size_t output_size = digest_size_bytes * num_messages;
//
// // Allocate host arrays
// char* h_messages = read_in_messages(file_name);
// unsigned char* h_output = (unsigned char*)malloc(output_size);
//
// char* d_messages;
// unsigned char* d_output;
//
// // Allocate device arrays
// cudaMalloc((void**)&d_messages, array_size);
// cudaMalloc((void**)&d_output, output_size);
//
// int number_runs = 25;
// // Copy Strings from host to device arrays
// for (int j = 0; j < number_runs; j++) {
// benchmark << <number_blocks, number_threads >> > (d_messages, d_output, num_messages);
// }
//
// // Free arrays from memory
// free(h_messages);
// free(h_output);
// cudaFree(d_messages);
// cudaFree(d_output);
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
const int digest_size = 256;
const int digest_size_bytes = digest_size / 8;
//cudaEvent_t start, stop;
#define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y))))
//__device__ __host__ inline const char* chars = "123abcABC";
__device__ const uint64_t RC[24] = {
0x0000000000000001, 0x0000000000008082, 0x800000000000808a,
0x8000000080008000, 0x000000000000808b, 0x0000000080000001,
0x8000000080008081, 0x8000000000008009, 0x000000000000008a,
0x0000000000000088, 0x0000000080008009, 0x000000008000000a,
0x000000008000808b, 0x800000000000008b, 0x8000000000008089,
0x8000000000008003, 0x8000000000008002, 0x8000000000000080,
0x000000000000800a, 0x800000008000000a, 0x8000000080008081,
0x8000000000008080, 0x0000000080000001, 0x8000000080008008
};
__device__ const int r[24] = {
1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14,
27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44
};
__device__ const int piln[24] = {
10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4,
15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1
};
//__device__ __host__ inline void generate_message(char* message, uint64_t tid, int* str_len) {
// int len = 0;
// const int num_chars = 94;
// char str[21];
// while (tid > 0) {
// str[len++] = chars[tid % num_chars];
// tid /= num_chars;
// }
//
// str[len] = '\0';
// memcpy(message, str, len + 1);
// *str_len = len;
//}
__device__ __host__ inline void keccak256(uint64_t state[25]) {
uint64_t temp, C[5];
int j;
for (int i = 0; i < 24; i++) {
// Theta
// for i = 0 to 5
// C[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ state[i + 15] ^ state[i + 20];
C[0] = state[0] ^ state[5] ^ state[10] ^ state[15] ^ state[20];
C[1] = state[1] ^ state[6] ^ state[11] ^ state[16] ^ state[21];
C[2] = state[2] ^ state[7] ^ state[12] ^ state[17] ^ state[22];
C[3] = state[3] ^ state[8] ^ state[13] ^ state[18] ^ state[23];
C[4] = state[4] ^ state[9] ^ state[14] ^ state[19] ^ state[24];
// for i = 0 to 5
// temp = C[(i + 4) % 5] ^ ROTL64(C[(i + 1) % 5], 1);
// for j = 0 to 25, j += 5
// state[j + i] ^= temp;
temp = C[4] ^ ROTL64(C[1], 1);
state[0] ^= temp;
state[5] ^= temp;
state[10] ^= temp;
state[15] ^= temp;
state[20] ^= temp;
temp = C[0] ^ ROTL64(C[2], 1);
state[1] ^= temp;
state[6] ^= temp;
state[11] ^= temp;
state[16] ^= temp;
state[21] ^= temp;
temp = C[1] ^ ROTL64(C[3], 1);
state[2] ^= temp;
state[7] ^= temp;
state[12] ^= temp;
state[17] ^= temp;
state[22] ^= temp;
temp = C[2] ^ ROTL64(C[4], 1);
state[3] ^= temp;
state[8] ^= temp;
state[13] ^= temp;
state[18] ^= temp;
state[23] ^= temp;
temp = C[3] ^ ROTL64(C[0], 1);
state[4] ^= temp;
state[9] ^= temp;
state[14] ^= temp;
state[19] ^= temp;
state[24] ^= temp;
// Rho Pi
// for i = 0 to 24
// j = piln[i];
// C[0] = state[j];
// state[j] = ROTL64(temp, r[i]);
// temp = C[0];
temp = state[1];
j = piln[0];
C[0] = state[j];
state[j] = ROTL64(temp, r[0]);
temp = C[0];
j = piln[1];
C[0] = state[j];
state[j] = ROTL64(temp, r[1]);
temp = C[0];
j = piln[2];
C[0] = state[j];
state[j] = ROTL64(temp, r[2]);
temp = C[0];
j = piln[3];
C[0] = state[j];
state[j] = ROTL64(temp, r[3]);
temp = C[0];
j = piln[4];
C[0] = state[j];
state[j] = ROTL64(temp, r[4]);
temp = C[0];
j = piln[5];
C[0] = state[j];
state[j] = ROTL64(temp, r[5]);
temp = C[0];
j = piln[6];
C[0] = state[j];
state[j] = ROTL64(temp, r[6]);
temp = C[0];
j = piln[7];
C[0] = state[j];
state[j] = ROTL64(temp, r[7]);
temp = C[0];
j = piln[8];
C[0] = state[j];
state[j] = ROTL64(temp, r[8]);
temp = C[0];
j = piln[9];
C[0] = state[j];
state[j] = ROTL64(temp, r[9]);
temp = C[0];
j = piln[10];
C[0] = state[j];
state[j] = ROTL64(temp, r[10]);
temp = C[0];
j = piln[11];
C[0] = state[j];
state[j] = ROTL64(temp, r[11]);
temp = C[0];
j = piln[12];
C[0] = state[j];
state[j] = ROTL64(temp, r[12]);
temp = C[0];
j = piln[13];
C[0] = state[j];
state[j] = ROTL64(temp, r[13]);
temp = C[0];
j = piln[14];
C[0] = state[j];
state[j] = ROTL64(temp, r[14]);
temp = C[0];
j = piln[15];
C[0] = state[j];
state[j] = ROTL64(temp, r[15]);
temp = C[0];
j = piln[16];
C[0] = state[j];
state[j] = ROTL64(temp, r[16]);
temp = C[0];
j = piln[17];
C[0] = state[j];
state[j] = ROTL64(temp, r[17]);
temp = C[0];
j = piln[18];
C[0] = state[j];
state[j] = ROTL64(temp, r[18]);
temp = C[0];
j = piln[19];
C[0] = state[j];
state[j] = ROTL64(temp, r[19]);
temp = C[0];
j = piln[20];
C[0] = state[j];
state[j] = ROTL64(temp, r[20]);
temp = C[0];
j = piln[21];
C[0] = state[j];
state[j] = ROTL64(temp, r[21]);
temp = C[0];
j = piln[22];
C[0] = state[j];
state[j] = ROTL64(temp, r[22]);
temp = C[0];
j = piln[23];
C[0] = state[j];
state[j] = ROTL64(temp, r[23]);
temp = C[0];
// Chi
// for j = 0 to 25, j += 5
// for i = 0 to 5
// C[i] = state[j + i];
// for i = 0 to 5
// state[j + 1] ^= (~C[(i + 1) % 5]) & C[(i + 2) % 5];
C[0] = state[0];
C[1] = state[1];
C[2] = state[2];
C[3] = state[3];
C[4] = state[4];
state[0] ^= (~C[1]) & C[2];
state[1] ^= (~C[2]) & C[3];
state[2] ^= (~C[3]) & C[4];
state[3] ^= (~C[4]) & C[0];
state[4] ^= (~C[0]) & C[1];
C[0] = state[5];
C[1] = state[6];
C[2] = state[7];
C[3] = state[8];
C[4] = state[9];
state[5] ^= (~C[1]) & C[2];
state[6] ^= (~C[2]) & C[3];
state[7] ^= (~C[3]) & C[4];
state[8] ^= (~C[4]) & C[0];
state[9] ^= (~C[0]) & C[1];
C[0] = state[10];
C[1] = state[11];
C[2] = state[12];
C[3] = state[13];
C[4] = state[14];
state[10] ^= (~C[1]) & C[2];
state[11] ^= (~C[2]) & C[3];
state[12] ^= (~C[3]) & C[4];
state[13] ^= (~C[4]) & C[0];
state[14] ^= (~C[0]) & C[1];
C[0] = state[15];
C[1] = state[16];
C[2] = state[17];
C[3] = state[18];
C[4] = state[19];
state[15] ^= (~C[1]) & C[2];
state[16] ^= (~C[2]) & C[3];
state[17] ^= (~C[3]) & C[4];
state[18] ^= (~C[4]) & C[0];
state[19] ^= (~C[0]) & C[1];
C[0] = state[20];
C[1] = state[21];
C[2] = state[22];
C[3] = state[23];
C[4] = state[24];
state[20] ^= (~C[1]) & C[2];
state[21] ^= (~C[2]) & C[3];
state[22] ^= (~C[3]) & C[4];
state[23] ^= (~C[4]) & C[0];
state[24] ^= (~C[0]) & C[1];
// Iota
state[0] ^= RC[i];
}
}
__device__ __host__ inline void keccak(const char* message, int message_len, unsigned char* output, int output_len) {
uint64_t state[25];
uint8_t temp[144];
int rsize = 136;
int rsize_byte = 17;
memset(state, 0, sizeof(state));
for (; message_len >= rsize; message_len -= rsize, message += rsize) {
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)message)[i];
}
keccak256(state);
}
// last block and padding
memcpy(temp, message, message_len);
temp[message_len++] = 1;
memset(temp + message_len, 0, rsize - message_len);
temp[rsize - 1] |= 0x80;
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)temp)[i];
}
keccak256(state);
memcpy(output, state, output_len);
}
//
//__global__ void benchmark(const char* messages, unsigned char* output, int num_messages) {
// const int str_len = 6;
// const int output_len = 32;
// int tid = threadIdx.x + (blockIdx.x * blockDim.x);
// int num_threads = blockDim.x * gridDim.x;
//
// for (; tid < num_messages; tid += num_threads)
// {
// keccak(&messages[tid * str_len], str_len, &output[tid * output_len], output_len);
// }
//}
//
//
//void gpu_init() {
// cudaDeviceProp device_prop;
// int device_count, block_size;
//
// cudaGetDeviceCount(&device_count);
// if (device_count != 1) {
// exit(EXIT_FAILURE);
// }
//
// if (cudaGetDeviceProperties(&device_prop, 0) != cudaSuccess) {
// exit(EXIT_FAILURE);
// }
//
// number_threads = device_prop.maxThreadsPerBlock;
// number_multi_processors = device_prop.multiProcessorCount;
// max_threads_per_mp = device_prop.maxThreadsPerMultiProcessor;
// block_size = (max_threads_per_mp / gcd(max_threads_per_mp, number_threads));
// number_threads = max_threads_per_mp / block_size;
// number_blocks = block_size * number_multi_processors;
// clock_speed = (int)(device_prop.memoryClockRate * 1000 * 1000);
//}
//int gcd(int a, int b) {
// return (a == 0) ? b : gcd(b % a, a);
//}
//char* read_in_messages(char* file_name) {
// FILE* f;
// if (!(f = fopen(file_name, "r")))
// {
// printf("Error opening file %s", file_name);
// exit(1);
// }
//
// char* messages = (char*)malloc(sizeof(char) * num_messages * str_length);
// if (messages == NULL)
// {
// perror("Error allocating memory for list of Strings.\n");
// exit(1);
// }
//
// int index = 0;
// char buf[10];
// while (1) {
// if (fgets(buf, str_length + 1, f) == NULL)
// break;
// buf[strlen(buf) - 1] = '\0';
// memcpy(&messages[index], buf, str_length);
// index += str_length - 1;
// }
//
// return messages;
//}
//
//
//
//
//void runBenchmarks(char* file_name, int num_messages) {
// float h_to_d_time = 0.0;
// float comp_time = 0.0;
// float d_to_h_time = 0.0;
// float total_time = 0.0;
// float elapsed_time;
// int hashes_per_sec;
//
// size_t array_size = sizeof(char) * str_length * num_messages;
// size_t output_size = digest_size_bytes * num_messages;
//
// // Allocate host arrays
// char* h_messages = read_in_messages(file_name);
// unsigned char* h_output = (unsigned char*)malloc(output_size);
//
// char* d_messages;
// unsigned char* d_output;
//
// // Allocate device arrays
// cudaMalloc((void**)&d_messages, array_size);
// cudaMalloc((void**)&d_output, output_size);
//
// int number_runs = 25;
// // Copy Strings from host to device arrays
// for (int j = 0; j < number_runs; j++) {
// benchmark << <number_blocks, number_threads >> > (d_messages, d_output, num_messages);
// }
//
// // Free arrays from memory
// free(h_messages);
// free(h_output);
// cudaFree(d_messages);
// cudaFree(d_output);
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
const int digest_size = 256;
const int digest_size_bytes = digest_size / 8;
//cudaEvent_t start, stop;
#define ROTL64(x, y) (((x) << (y)) | ((x) >> (64 - (y))))
//__device__ __host__ inline const char* chars = "123abcABC";
__device__ const uint64_t RC[24] = {
0x0000000000000001, 0x0000000000008082, 0x800000000000808a,
0x8000000080008000, 0x000000000000808b, 0x0000000080000001,
0x8000000080008081, 0x8000000000008009, 0x000000000000008a,
0x0000000000000088, 0x0000000080008009, 0x000000008000000a,
0x000000008000808b, 0x800000000000008b, 0x8000000000008089,
0x8000000000008003, 0x8000000000008002, 0x8000000000000080,
0x000000000000800a, 0x800000008000000a, 0x8000000080008081,
0x8000000000008080, 0x0000000080000001, 0x8000000080008008
};
__device__ const int r[24] = {
1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14,
27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44
};
__device__ const int piln[24] = {
10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4,
15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1
};
//__device__ __host__ inline void generate_message(char* message, uint64_t tid, int* str_len) {
// int len = 0;
// const int num_chars = 94;
// char str[21];
// while (tid > 0) {
// str[len++] = chars[tid % num_chars];
// tid /= num_chars;
// }
//
// str[len] = '\0';
// memcpy(message, str, len + 1);
// *str_len = len;
//}
__device__ __host__ inline void keccak256(uint64_t state[25]) {
uint64_t temp, C[5];
int j;
for (int i = 0; i < 24; i++) {
// Theta
// for i = 0 to 5
// C[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ state[i + 15] ^ state[i + 20];
C[0] = state[0] ^ state[5] ^ state[10] ^ state[15] ^ state[20];
C[1] = state[1] ^ state[6] ^ state[11] ^ state[16] ^ state[21];
C[2] = state[2] ^ state[7] ^ state[12] ^ state[17] ^ state[22];
C[3] = state[3] ^ state[8] ^ state[13] ^ state[18] ^ state[23];
C[4] = state[4] ^ state[9] ^ state[14] ^ state[19] ^ state[24];
// for i = 0 to 5
// temp = C[(i + 4) % 5] ^ ROTL64(C[(i + 1) % 5], 1);
// for j = 0 to 25, j += 5
// state[j + i] ^= temp;
temp = C[4] ^ ROTL64(C[1], 1);
state[0] ^= temp;
state[5] ^= temp;
state[10] ^= temp;
state[15] ^= temp;
state[20] ^= temp;
temp = C[0] ^ ROTL64(C[2], 1);
state[1] ^= temp;
state[6] ^= temp;
state[11] ^= temp;
state[16] ^= temp;
state[21] ^= temp;
temp = C[1] ^ ROTL64(C[3], 1);
state[2] ^= temp;
state[7] ^= temp;
state[12] ^= temp;
state[17] ^= temp;
state[22] ^= temp;
temp = C[2] ^ ROTL64(C[4], 1);
state[3] ^= temp;
state[8] ^= temp;
state[13] ^= temp;
state[18] ^= temp;
state[23] ^= temp;
temp = C[3] ^ ROTL64(C[0], 1);
state[4] ^= temp;
state[9] ^= temp;
state[14] ^= temp;
state[19] ^= temp;
state[24] ^= temp;
// Rho Pi
// for i = 0 to 24
// j = piln[i];
// C[0] = state[j];
// state[j] = ROTL64(temp, r[i]);
// temp = C[0];
temp = state[1];
j = piln[0];
C[0] = state[j];
state[j] = ROTL64(temp, r[0]);
temp = C[0];
j = piln[1];
C[0] = state[j];
state[j] = ROTL64(temp, r[1]);
temp = C[0];
j = piln[2];
C[0] = state[j];
state[j] = ROTL64(temp, r[2]);
temp = C[0];
j = piln[3];
C[0] = state[j];
state[j] = ROTL64(temp, r[3]);
temp = C[0];
j = piln[4];
C[0] = state[j];
state[j] = ROTL64(temp, r[4]);
temp = C[0];
j = piln[5];
C[0] = state[j];
state[j] = ROTL64(temp, r[5]);
temp = C[0];
j = piln[6];
C[0] = state[j];
state[j] = ROTL64(temp, r[6]);
temp = C[0];
j = piln[7];
C[0] = state[j];
state[j] = ROTL64(temp, r[7]);
temp = C[0];
j = piln[8];
C[0] = state[j];
state[j] = ROTL64(temp, r[8]);
temp = C[0];
j = piln[9];
C[0] = state[j];
state[j] = ROTL64(temp, r[9]);
temp = C[0];
j = piln[10];
C[0] = state[j];
state[j] = ROTL64(temp, r[10]);
temp = C[0];
j = piln[11];
C[0] = state[j];
state[j] = ROTL64(temp, r[11]);
temp = C[0];
j = piln[12];
C[0] = state[j];
state[j] = ROTL64(temp, r[12]);
temp = C[0];
j = piln[13];
C[0] = state[j];
state[j] = ROTL64(temp, r[13]);
temp = C[0];
j = piln[14];
C[0] = state[j];
state[j] = ROTL64(temp, r[14]);
temp = C[0];
j = piln[15];
C[0] = state[j];
state[j] = ROTL64(temp, r[15]);
temp = C[0];
j = piln[16];
C[0] = state[j];
state[j] = ROTL64(temp, r[16]);
temp = C[0];
j = piln[17];
C[0] = state[j];
state[j] = ROTL64(temp, r[17]);
temp = C[0];
j = piln[18];
C[0] = state[j];
state[j] = ROTL64(temp, r[18]);
temp = C[0];
j = piln[19];
C[0] = state[j];
state[j] = ROTL64(temp, r[19]);
temp = C[0];
j = piln[20];
C[0] = state[j];
state[j] = ROTL64(temp, r[20]);
temp = C[0];
j = piln[21];
C[0] = state[j];
state[j] = ROTL64(temp, r[21]);
temp = C[0];
j = piln[22];
C[0] = state[j];
state[j] = ROTL64(temp, r[22]);
temp = C[0];
j = piln[23];
C[0] = state[j];
state[j] = ROTL64(temp, r[23]);
temp = C[0];
// Chi
// for j = 0 to 25, j += 5
// for i = 0 to 5
// C[i] = state[j + i];
// for i = 0 to 5
// state[j + 1] ^= (~C[(i + 1) % 5]) & C[(i + 2) % 5];
C[0] = state[0];
C[1] = state[1];
C[2] = state[2];
C[3] = state[3];
C[4] = state[4];
state[0] ^= (~C[1]) & C[2];
state[1] ^= (~C[2]) & C[3];
state[2] ^= (~C[3]) & C[4];
state[3] ^= (~C[4]) & C[0];
state[4] ^= (~C[0]) & C[1];
C[0] = state[5];
C[1] = state[6];
C[2] = state[7];
C[3] = state[8];
C[4] = state[9];
state[5] ^= (~C[1]) & C[2];
state[6] ^= (~C[2]) & C[3];
state[7] ^= (~C[3]) & C[4];
state[8] ^= (~C[4]) & C[0];
state[9] ^= (~C[0]) & C[1];
C[0] = state[10];
C[1] = state[11];
C[2] = state[12];
C[3] = state[13];
C[4] = state[14];
state[10] ^= (~C[1]) & C[2];
state[11] ^= (~C[2]) & C[3];
state[12] ^= (~C[3]) & C[4];
state[13] ^= (~C[4]) & C[0];
state[14] ^= (~C[0]) & C[1];
C[0] = state[15];
C[1] = state[16];
C[2] = state[17];
C[3] = state[18];
C[4] = state[19];
state[15] ^= (~C[1]) & C[2];
state[16] ^= (~C[2]) & C[3];
state[17] ^= (~C[3]) & C[4];
state[18] ^= (~C[4]) & C[0];
state[19] ^= (~C[0]) & C[1];
C[0] = state[20];
C[1] = state[21];
C[2] = state[22];
C[3] = state[23];
C[4] = state[24];
state[20] ^= (~C[1]) & C[2];
state[21] ^= (~C[2]) & C[3];
state[22] ^= (~C[3]) & C[4];
state[23] ^= (~C[4]) & C[0];
state[24] ^= (~C[0]) & C[1];
// Iota
state[0] ^= RC[i];
}
}
__device__ __host__ inline void keccak(const char* message, int message_len, unsigned char* output, int output_len) {
uint64_t state[25];
uint8_t temp[144];
int rsize = 136;
int rsize_byte = 17;
memset(state, 0, sizeof(state));
for (; message_len >= rsize; message_len -= rsize, message += rsize) {
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)message)[i];
}
keccak256(state);
}
// last block and padding
memcpy(temp, message, message_len);
temp[message_len++] = 1;
memset(temp + message_len, 0, rsize - message_len);
temp[rsize - 1] |= 0x80;
for (int i = 0; i < rsize_byte; i++) {
state[i] ^= ((uint64_t*)temp)[i];
}
keccak256(state);
memcpy(output, state, output_len);
}
//
//__global__ void benchmark(const char* messages, unsigned char* output, int num_messages) {
// const int str_len = 6;
// const int output_len = 32;
// int tid = threadIdx.x + (blockIdx.x * blockDim.x);
// int num_threads = blockDim.x * gridDim.x;
//
// for (; tid < num_messages; tid += num_threads)
// {
// keccak(&messages[tid * str_len], str_len, &output[tid * output_len], output_len);
// }
//}
//
//
//void gpu_init() {
// cudaDeviceProp device_prop;
// int device_count, block_size;
//
// cudaGetDeviceCount(&device_count);
// if (device_count != 1) {
// exit(EXIT_FAILURE);
// }
//
// if (cudaGetDeviceProperties(&device_prop, 0) != cudaSuccess) {
// exit(EXIT_FAILURE);
// }
//
// number_threads = device_prop.maxThreadsPerBlock;
// number_multi_processors = device_prop.multiProcessorCount;
// max_threads_per_mp = device_prop.maxThreadsPerMultiProcessor;
// block_size = (max_threads_per_mp / gcd(max_threads_per_mp, number_threads));
// number_threads = max_threads_per_mp / block_size;
// number_blocks = block_size * number_multi_processors;
// clock_speed = (int)(device_prop.memoryClockRate * 1000 * 1000);
//}
//int gcd(int a, int b) {
// return (a == 0) ? b : gcd(b % a, a);
//}
//char* read_in_messages(char* file_name) {
// FILE* f;
// if (!(f = fopen(file_name, "r")))
// {
// printf("Error opening file %s", file_name);
// exit(1);
// }
//
// char* messages = (char*)malloc(sizeof(char) * num_messages * str_length);
// if (messages == NULL)
// {
// perror("Error allocating memory for list of Strings.\n");
// exit(1);
// }
//
// int index = 0;
// char buf[10];
// while (1) {
// if (fgets(buf, str_length + 1, f) == NULL)
// break;
// buf[strlen(buf) - 1] = '\0';
// memcpy(&messages[index], buf, str_length);
// index += str_length - 1;
// }
//
// return messages;
//}
//
//
//
//
//void runBenchmarks(char* file_name, int num_messages) {
// float h_to_d_time = 0.0;
// float comp_time = 0.0;
// float d_to_h_time = 0.0;
// float total_time = 0.0;
// float elapsed_time;
// int hashes_per_sec;
//
// size_t array_size = sizeof(char) * str_length * num_messages;
// size_t output_size = digest_size_bytes * num_messages;
//
// // Allocate host arrays
// char* h_messages = read_in_messages(file_name);
// unsigned char* h_output = (unsigned char*)malloc(output_size);
//
// char* d_messages;
// unsigned char* d_output;
//
// // Allocate device arrays
// cudaMalloc((void**)&d_messages, array_size);
// cudaMalloc((void**)&d_output, output_size);
//
// int number_runs = 25;
// // Copy Strings from host to device arrays
// for (int j = 0; j < number_runs; j++) {
// benchmark << <number_blocks, number_threads >> > (d_messages, d_output, num_messages);
// }
//
// // Free arrays from memory
// free(h_messages);
// free(h_output);
// cudaFree(d_messages);
// cudaFree(d_output);
//} | .text
.file "keccak.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018e6c4_00000000-6_keccak.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "precalc_xorwow_matrix"
.LC1:
.string "precalc_xorwow_offset_matrix"
.LC2:
.string "mrg32k3aM1"
.LC3:
.string "mrg32k3aM2"
.LC4:
.string "mrg32k3aM1SubSeq"
.LC5:
.string "mrg32k3aM2SubSeq"
.LC6:
.string "mrg32k3aM1Seq"
.LC7:
.string "mrg32k3aM2Seq"
.LC8:
.string "__cr_lgamma_table"
.LC9:
.string "RC"
.LC10:
.string "r"
.LC11:
.string "piln"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $192, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2RC(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $96, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1r(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $96, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4piln(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 32
.type _ZL4piln, @object
.size _ZL4piln, 96
_ZL4piln:
.long 10
.long 7
.long 11
.long 17
.long 18
.long 3
.long 5
.long 16
.long 8
.long 21
.long 24
.long 4
.long 15
.long 23
.long 19
.long 13
.long 12
.long 2
.long 20
.long 14
.long 22
.long 9
.long 6
.long 1
.align 32
.type _ZL1r, @object
.size _ZL1r, 96
_ZL1r:
.long 1
.long 3
.long 6
.long 10
.long 15
.long 21
.long 28
.long 36
.long 45
.long 55
.long 2
.long 14
.long 27
.long 41
.long 56
.long 8
.long 25
.long 43
.long 62
.long 18
.long 39
.long 61
.long 20
.long 44
.align 32
.type _ZL2RC, @object
.size _ZL2RC, 192
_ZL2RC:
.quad 1
.quad 32898
.quad -9223372036854742902
.quad -9223372034707259392
.quad 32907
.quad 2147483649
.quad -9223372034707259263
.quad -9223372036854743031
.quad 138
.quad 136
.quad 2147516425
.quad 2147483658
.quad 2147516555
.quad -9223372036854775669
.quad -9223372036854742903
.quad -9223372036854743037
.quad -9223372036854743038
.quad -9223372036854775680
.quad 32778
.quad -9223372034707292150
.quad -9223372034707259263
.quad -9223372036854742912
.quad 2147483649
.quad -9223372034707259384
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "keccak.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void kernelFindMax4(const int* dataArray, int arraySize, int* maxVal)
{
__shared__ extern int cache[];
int cacheIndex = threadIdx.x;
int arrayIndex1 = (int)(blockDim.x * blockIdx.x + threadIdx.x); // グローバルメモリの1つ目の要素番号
int arrayIndex2 = arrayIndex1 + gridDim.x * blockDim.x; // グローバルメモリの2つ目の要素番号
cache[cacheIndex] = INT_MIN;
if (arrayIndex1 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex1]); // シェアードメモリと比較
}
if (arrayIndex2 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex2]); // シェアードメモリと比較
}
__syncthreads();
int blockSize = blockDim.x;
for (int offset = blockSize >> 1; offset > 0; offset >>= 1)
{
if (cacheIndex < offset)
{
cache[cacheIndex] = max(cache[cacheIndex], cache[cacheIndex ^ offset]);
}
__syncthreads();
}
if (cacheIndex == 0)
{
atomicMax(maxVal, cache[0]);
}
} | code for sm_80
Function : _Z14kernelFindMax4PKiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, -0x80000000 ; /* 0x80000000ff007424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0207 */
/*0070*/ IMAD R4, R9, c[0x0][0xc], R2 ; /* 0x0000030009047a24 */
/* 0x000fe200078e0202 */
/*0080*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f26270 */
/*0090*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fd20003f46270 */
/*00a0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*00b0*/ @!P2 MOV R5, 0x4 ; /* 0x000000040005a802 */
/* 0x000fe20000000f00 */
/*00c0*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fc800078e0203 */
/*00d0*/ @!P2 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x000058000404a625 */
/* 0x000fe200078e0205 */
/*00e0*/ @!P1 LDG.E R0, [R2.64] ; /* 0x0000000402009981 */
/* 0x000eaa000c1e1900 */
/*00f0*/ @!P2 LDG.E R5, [R4.64] ; /* 0x000000040405a981 */
/* 0x000ee2000c1e1900 */
/*0100*/ ISETP.GE.AND P3, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f66270 */
/*0110*/ IMAD.MOV.U32 R8, RZ, RZ, -0x80000000 ; /* 0x80000000ff087424 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0130*/ STS [R7.X4], R8 ; /* 0x0000000807007388 */
/* 0x0001e80000004800 */
/*0140*/ @!P1 STS [R7.X4], R0 ; /* 0x0000000007009388 */
/* 0x0041e20000004800 */
/*0150*/ @!P2 IMNMX R6, R5, R0, !PT ; /* 0x000000000506a217 */
/* 0x008fca0007800200 */
/*0160*/ @!P2 STS [R7.X4], R6 ; /* 0x000000060700a388 */
/* 0x0001e80000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P3 BRA 0x250 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*0190*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x001fc80000000f00 */
/*01a0*/ SHF.R.S32.HI R4, RZ, 0x1, R0 ; /* 0x00000001ff047819 */
/* 0x000fc80000011400 */
/*01b0*/ ISETP.GE.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f26270 */
/*01c0*/ @!P1 LOP3.LUT R3, R4, R7, RZ, 0x3c, !PT ; /* 0x0000000704039212 */
/* 0x000fe200078e3cff */
/*01d0*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x000fea0000004800 */
/*01e0*/ @!P1 LDS R3, [R3.X4] ; /* 0x0000000003039984 */
/* 0x000e240000004800 */
/*01f0*/ @!P1 IMNMX R2, R2, R3, !PT ; /* 0x0000000302029217 */
/* 0x001fca0007800200 */
/*0200*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f24270 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fd800078e0004 */
/*0240*/ @P1 BRA 0x1a0 ; /* 0xffffff5000001947 */
/* 0x001fea000383ffff */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0260*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0280*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0290*/ RED.E.MAX.S32.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000d10e384 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void kernelFindMax4(const int* dataArray, int arraySize, int* maxVal)
{
__shared__ extern int cache[];
int cacheIndex = threadIdx.x;
int arrayIndex1 = (int)(blockDim.x * blockIdx.x + threadIdx.x); // グローバルメモリの1つ目の要素番号
int arrayIndex2 = arrayIndex1 + gridDim.x * blockDim.x; // グローバルメモリの2つ目の要素番号
cache[cacheIndex] = INT_MIN;
if (arrayIndex1 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex1]); // シェアードメモリと比較
}
if (arrayIndex2 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex2]); // シェアードメモリと比較
}
__syncthreads();
int blockSize = blockDim.x;
for (int offset = blockSize >> 1; offset > 0; offset >>= 1)
{
if (cacheIndex < offset)
{
cache[cacheIndex] = max(cache[cacheIndex], cache[cacheIndex ^ offset]);
}
__syncthreads();
}
if (cacheIndex == 0)
{
atomicMax(maxVal, cache[0]);
}
} | .file "tmpxft_000193cd_00000000-6_kernelFindMax4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL14kernelFindMax4PKiiPi, @function
_ZL14kernelFindMax4PKiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 24(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL14kernelFindMax4PKiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL14kernelFindMax4PKiiPi, .-_ZL14kernelFindMax4PKiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14kernelFindMax4PKiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14kernelFindMax4PKiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void kernelFindMax4(const int* dataArray, int arraySize, int* maxVal)
{
__shared__ extern int cache[];
int cacheIndex = threadIdx.x;
int arrayIndex1 = (int)(blockDim.x * blockIdx.x + threadIdx.x); // グローバルメモリの1つ目の要素番号
int arrayIndex2 = arrayIndex1 + gridDim.x * blockDim.x; // グローバルメモリの2つ目の要素番号
cache[cacheIndex] = INT_MIN;
if (arrayIndex1 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex1]); // シェアードメモリと比較
}
if (arrayIndex2 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex2]); // シェアードメモリと比較
}
__syncthreads();
int blockSize = blockDim.x;
for (int offset = blockSize >> 1; offset > 0; offset >>= 1)
{
if (cacheIndex < offset)
{
cache[cacheIndex] = max(cache[cacheIndex], cache[cacheIndex ^ offset]);
}
__syncthreads();
}
if (cacheIndex == 0)
{
atomicMax(maxVal, cache[0]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void kernelFindMax4(const int* dataArray, int arraySize, int* maxVal)
{
__shared__ extern int cache[];
int cacheIndex = threadIdx.x;
int arrayIndex1 = (int)(blockDim.x * blockIdx.x + threadIdx.x); // グローバルメモリの1つ目の要素番号
int arrayIndex2 = arrayIndex1 + gridDim.x * blockDim.x; // グローバルメモリの2つ目の要素番号
cache[cacheIndex] = INT_MIN;
if (arrayIndex1 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex1]); // シェアードメモリと比較
}
if (arrayIndex2 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex2]); // シェアードメモリと比較
}
__syncthreads();
int blockSize = blockDim.x;
for (int offset = blockSize >> 1; offset > 0; offset >>= 1)
{
if (cacheIndex < offset)
{
cache[cacheIndex] = max(cache[cacheIndex], cache[cacheIndex ^ offset]);
}
__syncthreads();
}
if (cacheIndex == 0)
{
atomicMax(maxVal, cache[0]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void kernelFindMax4(const int* dataArray, int arraySize, int* maxVal)
{
__shared__ extern int cache[];
int cacheIndex = threadIdx.x;
int arrayIndex1 = (int)(blockDim.x * blockIdx.x + threadIdx.x); // グローバルメモリの1つ目の要素番号
int arrayIndex2 = arrayIndex1 + gridDim.x * blockDim.x; // グローバルメモリの2つ目の要素番号
cache[cacheIndex] = INT_MIN;
if (arrayIndex1 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex1]); // シェアードメモリと比較
}
if (arrayIndex2 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex2]); // シェアードメモリと比較
}
__syncthreads();
int blockSize = blockDim.x;
for (int offset = blockSize >> 1; offset > 0; offset >>= 1)
{
if (cacheIndex < offset)
{
cache[cacheIndex] = max(cache[cacheIndex], cache[cacheIndex ^ offset]);
}
__syncthreads();
}
if (cacheIndex == 0)
{
atomicMax(maxVal, cache[0]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL14kernelFindMax4PKiiPi,"axG",@progbits,_ZL14kernelFindMax4PKiiPi,comdat
.globl _ZL14kernelFindMax4PKiiPi
.p2align 8
.type _ZL14kernelFindMax4PKiiPi,@function
_ZL14kernelFindMax4PKiiPi:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x18
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_bfrev_b32_e32 v2, 1
ds_store_b32 v4, v2
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v2
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
ds_load_b32 v2, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v1, v2, v1
ds_store_b32 v4, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s4, 2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s4, 4
s_mov_b32 s4, s2
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s2, s4, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_5
v_xor_b32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v2, v4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v1, v2, v1
ds_store_b32 v4, v1
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_atomic_max_i32 v1, v0, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL14kernelFindMax4PKiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL14kernelFindMax4PKiiPi,"axG",@progbits,_ZL14kernelFindMax4PKiiPi,comdat
.Lfunc_end0:
.size _ZL14kernelFindMax4PKiiPi, .Lfunc_end0-_ZL14kernelFindMax4PKiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL14kernelFindMax4PKiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL14kernelFindMax4PKiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void kernelFindMax4(const int* dataArray, int arraySize, int* maxVal)
{
__shared__ extern int cache[];
int cacheIndex = threadIdx.x;
int arrayIndex1 = (int)(blockDim.x * blockIdx.x + threadIdx.x); // グローバルメモリの1つ目の要素番号
int arrayIndex2 = arrayIndex1 + gridDim.x * blockDim.x; // グローバルメモリの2つ目の要素番号
cache[cacheIndex] = INT_MIN;
if (arrayIndex1 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex1]); // シェアードメモリと比較
}
if (arrayIndex2 < arraySize)
{
cache[cacheIndex] = max(cache[cacheIndex] , dataArray[arrayIndex2]); // シェアードメモリと比較
}
__syncthreads();
int blockSize = blockDim.x;
for (int offset = blockSize >> 1; offset > 0; offset >>= 1)
{
if (cacheIndex < offset)
{
cache[cacheIndex] = max(cache[cacheIndex], cache[cacheIndex ^ offset]);
}
__syncthreads();
}
if (cacheIndex == 0)
{
atomicMax(maxVal, cache[0]);
}
} | .text
.file "kernelFindMax4.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14kernelFindMax4PKiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, -0x80000000 ; /* 0x80000000ff007424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0207 */
/*0070*/ IMAD R4, R9, c[0x0][0xc], R2 ; /* 0x0000030009047a24 */
/* 0x000fe200078e0202 */
/*0080*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f26270 */
/*0090*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fd20003f46270 */
/*00a0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*00b0*/ @!P2 MOV R5, 0x4 ; /* 0x000000040005a802 */
/* 0x000fe20000000f00 */
/*00c0*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fc800078e0203 */
/*00d0*/ @!P2 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x000058000404a625 */
/* 0x000fe200078e0205 */
/*00e0*/ @!P1 LDG.E R0, [R2.64] ; /* 0x0000000402009981 */
/* 0x000eaa000c1e1900 */
/*00f0*/ @!P2 LDG.E R5, [R4.64] ; /* 0x000000040405a981 */
/* 0x000ee2000c1e1900 */
/*0100*/ ISETP.GE.AND P3, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f66270 */
/*0110*/ IMAD.MOV.U32 R8, RZ, RZ, -0x80000000 ; /* 0x80000000ff087424 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0130*/ STS [R7.X4], R8 ; /* 0x0000000807007388 */
/* 0x0001e80000004800 */
/*0140*/ @!P1 STS [R7.X4], R0 ; /* 0x0000000007009388 */
/* 0x0041e20000004800 */
/*0150*/ @!P2 IMNMX R6, R5, R0, !PT ; /* 0x000000000506a217 */
/* 0x008fca0007800200 */
/*0160*/ @!P2 STS [R7.X4], R6 ; /* 0x000000060700a388 */
/* 0x0001e80000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P3 BRA 0x250 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*0190*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x001fc80000000f00 */
/*01a0*/ SHF.R.S32.HI R4, RZ, 0x1, R0 ; /* 0x00000001ff047819 */
/* 0x000fc80000011400 */
/*01b0*/ ISETP.GE.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f26270 */
/*01c0*/ @!P1 LOP3.LUT R3, R4, R7, RZ, 0x3c, !PT ; /* 0x0000000704039212 */
/* 0x000fe200078e3cff */
/*01d0*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x000fea0000004800 */
/*01e0*/ @!P1 LDS R3, [R3.X4] ; /* 0x0000000003039984 */
/* 0x000e240000004800 */
/*01f0*/ @!P1 IMNMX R2, R2, R3, !PT ; /* 0x0000000302029217 */
/* 0x001fca0007800200 */
/*0200*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f24270 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fd800078e0004 */
/*0240*/ @P1 BRA 0x1a0 ; /* 0xffffff5000001947 */
/* 0x001fea000383ffff */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0260*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0280*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0290*/ RED.E.MAX.S32.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000d10e384 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL14kernelFindMax4PKiiPi,"axG",@progbits,_ZL14kernelFindMax4PKiiPi,comdat
.globl _ZL14kernelFindMax4PKiiPi
.p2align 8
.type _ZL14kernelFindMax4PKiiPi,@function
_ZL14kernelFindMax4PKiiPi:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x18
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_bfrev_b32_e32 v2, 1
ds_store_b32 v4, v2
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v2
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
ds_load_b32 v2, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v1, v2, v1
ds_store_b32 v4, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s4, 2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s4, 4
s_mov_b32 s4, s2
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s2, s4, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_5
v_xor_b32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v2, v4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v1, v2, v1
ds_store_b32 v4, v1
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_atomic_max_i32 v1, v0, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL14kernelFindMax4PKiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL14kernelFindMax4PKiiPi,"axG",@progbits,_ZL14kernelFindMax4PKiiPi,comdat
.Lfunc_end0:
.size _ZL14kernelFindMax4PKiiPi, .Lfunc_end0-_ZL14kernelFindMax4PKiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL14kernelFindMax4PKiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL14kernelFindMax4PKiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000193cd_00000000-6_kernelFindMax4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL14kernelFindMax4PKiiPi, @function
_ZL14kernelFindMax4PKiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 24(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL14kernelFindMax4PKiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL14kernelFindMax4PKiiPi, .-_ZL14kernelFindMax4PKiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14kernelFindMax4PKiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14kernelFindMax4PKiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelFindMax4.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/***********************************************************
tissueGPU1.cu
GPU kernel to accumulate contributions of tissue source
strengths qt to tissue solute levels pt.
TWS December 2011
Cuda 10.1 Version, August 2019
************************************************************/
__global__ void tissueGPU1Kernel(int *d_tisspoints, float *d_dtt000, float *d_pt000, float *d_qt000, int nnt)
{
int itp = blockDim.x * blockIdx.x + threadIdx.x;
int jtp,ixyz,ix,iy,iz,jx,jy,jz,nnt2=2*nnt;
float p = 0.;
if(itp < nnt){
ix = d_tisspoints[itp];
iy = d_tisspoints[itp+nnt];
iz = d_tisspoints[itp+nnt2];
for(jtp=0; jtp<nnt; jtp++){
jx = d_tisspoints[jtp];
jy = d_tisspoints[jtp+nnt];
jz = d_tisspoints[jtp+nnt2];
ixyz = abs(jx-ix) + abs(jy-iy) + abs(jz-iz);
p += d_qt000[jtp]*d_dtt000[ixyz];
}
d_pt000[itp] = p;
}
} | code for sm_80
Function : _Z16tissueGPU1KernelPiPfS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0e7624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ; /* 0x0000001fff0f7819 */
/* 0x000fe20000011400 */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0x9e0 ; /* 0x0000092000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R8, R14, -0x1, RZ ; /* 0xffffffff0e087810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe40000000f00 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f26070 */
/*0100*/ IMAD.WIDE R2, R0, R16, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0210 */
/*0110*/ IMAD R7, R7, 0x2, R0 ; /* 0x0000000207077824 */
/* 0x000fe200078e0200 */
/*0120*/ LOP3.LUT R21, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e157812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD.WIDE R4, R16, c[0x0][0x180], R2 ; /* 0x0000600010047a25 */
/* 0x000fe200078e0202 */
/*0140*/ LDG.E R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000166000c1e1900 */
/*0150*/ IMAD.WIDE R6, R7, R16, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0210 */
/*0160*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000162000c1e1900 */
/*0170*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003f05270 */
/*0180*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000162000c1e1900 */
/*0190*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*01a0*/ SHF.R.S32.HI R22, RZ, 0x1f, R14 ; /* 0x0000001fff167819 */
/* 0x000fe2000001140e */
/*01b0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*01c0*/ @!P1 BRA 0x720 ; /* 0x0000055000009947 */
/* 0x000fec0003800000 */
/*01d0*/ LEA R4, P1, R14.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000e047a11 */
/* 0x041fe200078210ff */
/*01e0*/ IMAD.SHL.U32 R3, R14, 0x2, RZ ; /* 0x000000020e037824 */
/* 0x000fe200078e00ff */
/*01f0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fe200000001ff */
/*0200*/ IADD3 R23, -R21, c[0x0][0x180], RZ ; /* 0x0000600015177a10 */
/* 0x000fe20007ffe1ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R4, P2, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007f5e0ff */
/*0230*/ IMAD.WIDE R2, R3, R16, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0210 */
/*0240*/ LEA.HI.X R5, R14, c[0x0][0x164], R22, 0x2, P1 ; /* 0x000059000e057a11 */
/* 0x000fc400008f1416 */
/*0250*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0605 */
/*02a0*/ LDG.E R25, [R6.64] ; /* 0x0000000406197981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R24, [R4.64+-0x8] ; /* 0xfffff80404187981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R27, [R2.64] ; /* 0x00000004021b7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R8, [R4.64+-0x4] ; /* 0xfffffc0404087981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040406097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R26, [R4.64+0x4] ; /* 0x00000404041a7981 */
/* 0x000f22000c1e1900 */
/*0310*/ IMAD.IADD R25, R25, 0x1, -R18 ; /* 0x0000000119197824 */
/* 0x024fc400078e0a12 */
/*0320*/ IMAD.IADD R24, R24, 0x1, -R19 ; /* 0x0000000118187824 */
/* 0x008fe400078e0a13 */
/*0330*/ IMAD.IADD R27, R27, 0x1, -R20.reuse ; /* 0x000000011b1b7824 */
/* 0x110fe200078e0a14 */
/*0340*/ IABS R25, R25 ; /* 0x0000001900197213 */
/* 0x000fe40000000000 */
/*0350*/ IABS R24, R24 ; /* 0x0000001800187213 */
/* 0x000fe40000000000 */
/*0360*/ IABS R29, R27 ; /* 0x0000001b001d7213 */
/* 0x000fe40000000000 */
/*0370*/ LDG.E R27, [R6.64+0x8] ; /* 0x00000804061b7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IADD3 R29, R29, R24, R25 ; /* 0x000000181d1d7210 */
/* 0x000fe20007ffe019 */
/*0390*/ IMAD.IADD R8, R8, 0x1, -R19 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a13 */
/*03a0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.IADD R11, R11, 0x1, -R20 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0a14 */
/*03c0*/ IADD3 R9, -R18, R9, RZ ; /* 0x0000000912097210 */
/* 0x000fc40007ffe1ff */
/*03d0*/ LDG.E R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000f22000c1e1900 */
/*03e0*/ IABS R8, R8 ; /* 0x0000000800087213 */
/* 0x000fe40000000000 */
/*03f0*/ IABS R9, R9 ; /* 0x0000000900097213 */
/* 0x000fe40000000000 */
/*0400*/ IABS R11, R11 ; /* 0x0000000b000b7213 */
/* 0x000fc80000000000 */
/*0410*/ IADD3 R11, R11, R8, R9 ; /* 0x000000080b0b7210 */
/* 0x000fe20007ffe009 */
/*0420*/ IMAD.WIDE R8, R29, R16, c[0x0][0x168] ; /* 0x00005a001d087625 */
/* 0x000fca00078e0210 */
/*0430*/ LDG.E R29, [R8.64] ; /* 0x00000004081d7981 */
/* 0x000124000c1e1900 */
/*0440*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe200078e000c */
/*0450*/ MOV R9, R13 ; /* 0x0000000d00097202 */
/* 0x000fca0000000f00 */
/*0460*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R28, [R8.64+0x4] ; /* 0x00000404081c7981 */
/* 0x000f22000c1e1900 */
/*0480*/ IMAD.IADD R27, R27, 0x1, -R18 ; /* 0x000000011b1b7824 */
/* 0x004fe400078e0a12 */
/*0490*/ IMAD.IADD R25, R25, 0x1, -R20 ; /* 0x0000000119197824 */
/* 0x008fc600078e0a14 */
/*04a0*/ IABS R27, R27 ; /* 0x0000001b001b7213 */
/* 0x000fe20000000000 */
/*04b0*/ IMAD.IADD R24, R24, 0x1, -R19 ; /* 0x0000000118187824 */
/* 0x010fe200078e0a13 */
/*04c0*/ IABS R13, R25 ; /* 0x00000019000d7213 */
/* 0x000fe40000000000 */
/*04d0*/ MOV R25, R27 ; /* 0x0000001b00197202 */
/* 0x000fe40000000f00 */
/*04e0*/ IABS R24, R24 ; /* 0x0000001800187213 */
/* 0x000fe20000000000 */
/*04f0*/ LDG.E R27, [R2.64+0xc] ; /* 0x00000c04021b7981 */
/* 0x000ea6000c1e1900 */
/*0500*/ IADD3 R13, R13, R24, R25 ; /* 0x000000180d0d7210 */
/* 0x000fc40007ffe019 */
/*0510*/ LDG.E R25, [R6.64+0xc] ; /* 0x00000c0406197981 */
/* 0x000ee2000c1e1900 */
/*0520*/ FFMA R24, R29, R12, R10 ; /* 0x0000000c1d187223 */
/* 0x000fe4000000000a */
/*0530*/ IMAD.WIDE R10, R11, R16, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e0210 */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000122000c1e1900 */
/*0550*/ IMAD.IADD R26, R26, 0x1, -R19 ; /* 0x000000011a1a7824 */
/* 0x000fe400078e0a13 */
/*0560*/ IMAD.WIDE R12, R13, R16, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fcc00078e0210 */
/*0570*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000922000c1e1900 */
/*0580*/ IABS R10, R26 ; /* 0x0000001a000a7213 */
/* 0x001fe20000000000 */
/*0590*/ IMAD.IADD R27, R27, 0x1, -R20 ; /* 0x000000011b1b7824 */
/* 0x004fe400078e0a14 */
/*05a0*/ IMAD.IADD R25, R25, 0x1, -R18 ; /* 0x0000000119197824 */
/* 0x008fca00078e0a12 */
/*05b0*/ IABS R29, R25 ; /* 0x00000019001d7213 */
/* 0x000fe40000000000 */
/*05c0*/ IABS R25, R27 ; /* 0x0000001b00197213 */
/* 0x000fe40000000000 */
/*05d0*/ MOV R26, R29 ; /* 0x0000001d001a7202 */
/* 0x000fc80000000f00 */
/*05e0*/ IADD3 R25, R25, R10, R26 ; /* 0x0000000a19197210 */
/* 0x000fe20007ffe01a */
/*05f0*/ FFMA R13, R11, R28, R24 ; /* 0x0000001c0b0d7223 */
/* 0x010fe40000000018 */
/*0600*/ LDG.E R24, [R8.64+0x8] ; /* 0x0000080408187981 */
/* 0x000ea4000c1e1900 */
/*0610*/ IMAD.WIDE R10, R25, R16, c[0x0][0x168] ; /* 0x00005a00190a7625 */
/* 0x000fe400078e0210 */
/*0620*/ LDG.E R25, [R8.64+0xc] ; /* 0x00000c0408197981 */
/* 0x000ee8000c1e1900 */
/*0630*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0640*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007f3e0ff */
/*0650*/ IADD3 R23, R23, -0x4, RZ ; /* 0xfffffffc17177810 */
/* 0x000fc60007ffe0ff */
/*0660*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0670*/ ISETP.NE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f25270 */
/*0680*/ IADD3 R4, P3, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f7e0ff */
/*0690*/ IADD3 R6, P4, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007f9e0ff */
/*06a0*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*06c0*/ IADD3.X R7, RZ, R7, RZ, P4, !PT ; /* 0x00000007ff077210 */
/* 0x000fe200027fe4ff */
/*06d0*/ FFMA R24, R12, R24, R13 ; /* 0x000000180c187223 */
/* 0x004fe2000000000d */
/*06e0*/ IADD3 R12, P2, R8, 0x10, RZ ; /* 0x00000010080c7810 */
/* 0x000fca0007f5e0ff */
/*06f0*/ IMAD.X R13, RZ, RZ, R9, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e0609 */
/*0700*/ FFMA R10, R10, R25, R24 ; /* 0x000000190a0a7223 */
/* 0x008fe20000000018 */
/*0710*/ @P1 BRA 0x2a0 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0720*/ @!P0 BRA 0x9e0 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R12, P0, R17.reuse, c[0x0][0x180], RZ ; /* 0x00006000110c7a10 */
/* 0x040fe20007f1e0ff */
/*0740*/ IMAD.WIDE R4, R17, R16, c[0x0][0x160] ; /* 0x0000580011047625 */
/* 0x001fc600078e0210 */
/*0750*/ LEA.HI.X.SX32 R23, R17.reuse, R22, 0x1, P0 ; /* 0x0000001611177211 */
/* 0x040fe200000f0eff */
/*0760*/ IMAD R7, R14, 0x2, R17 ; /* 0x000000020e077824 */
/* 0x000fe200078e0211 */
/*0770*/ LEA R9, P0, R12.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000c097a11 */
/* 0x040fe200078010ff */
/*0780*/ IMAD.WIDE R2, R17, R16, c[0x0][0x178] ; /* 0x00005e0011027625 */
/* 0x000fe200078e0210 */
/*0790*/ MOV R11, R4 ; /* 0x00000004000b7202 */
/* 0x000fe40000000f00 */
/*07a0*/ LEA.HI.X R12, R12, c[0x0][0x164], R23, 0x2, P0 ; /* 0x000059000c0c7a11 */
/* 0x000fe200000f1417 */
/*07b0*/ IMAD.WIDE R6, R7, R16, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0210 */
/*07c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*07d0*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0003 */
/*07e0*/ IMAD.MOV.U32 R14, RZ, RZ, R5 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0005 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000e */
/*0800*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000b */
/*0820*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ea2000c1e1900 */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000c */
/*0840*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee8000c1e1900 */
/*0850*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000124000c1e1900 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x001fe200078e000d */
/*0870*/ IADD3 R23, -R20, R23, RZ ; /* 0x0000001714177210 */
/* 0x024fe20007ffe1ff */
/*0880*/ IMAD.IADD R17, R3, 0x1, -R18 ; /* 0x0000000103117824 */
/* 0x008fe400078e0a12 */
/*0890*/ IMAD.IADD R22, R4, 0x1, -R19 ; /* 0x0000000104167824 */
/* 0x010fc600078e0a13 */
/*08a0*/ IABS R17, R17 ; /* 0x0000001100117213 */
/* 0x000fe40000000000 */
/*08b0*/ IABS R3, R23 ; /* 0x0000001700037213 */
/* 0x000fe40000000000 */
/*08c0*/ IABS R22, R22 ; /* 0x0000001600167213 */
/* 0x000fc80000000000 */
/*08d0*/ IADD3 R3, R3, R22, R17 ; /* 0x0000001603037210 */
/* 0x000fe20007ffe011 */
/*08e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0008 */
/*08f0*/ IMAD.WIDE R2, R3, R16, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe400078e0210 */
/*0900*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IADD3 R21, R21, -0x1, RZ ; /* 0xffffffff15157810 */
/* 0x000fc80007ffe0ff */
/*0930*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0950*/ IADD3 R9, P3, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f7e0ff */
/*0960*/ IADD3 R11, P4, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007f9e0ff */
/*0970*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f5e0ff */
/*0980*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0990*/ IMAD.X R12, RZ, RZ, R12, P3 ; /* 0x000000ffff0c7224 */
/* 0x000fe200018e060c */
/*09a0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*09b0*/ IMAD.X R14, RZ, RZ, R14, P4 ; /* 0x000000ffff0e7224 */
/* 0x000fc400020e060e */
/*09c0*/ FFMA R10, R3, R4, R10 ; /* 0x00000004030a7223 */
/* 0x004fe2000000000a */
/*09d0*/ @P0 BRA 0x7f0 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*09e0*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x001fc800078010ff */
/*09f0*/ LEA.HI.X R3, R0, c[0x0][0x174], R15, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f140f */
/*0a00*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/***********************************************************
tissueGPU1.cu
GPU kernel to accumulate contributions of tissue source
strengths qt to tissue solute levels pt.
TWS December 2011
Cuda 10.1 Version, August 2019
************************************************************/
__global__ void tissueGPU1Kernel(int *d_tisspoints, float *d_dtt000, float *d_pt000, float *d_qt000, int nnt)
{
int itp = blockDim.x * blockIdx.x + threadIdx.x;
int jtp,ixyz,ix,iy,iz,jx,jy,jz,nnt2=2*nnt;
float p = 0.;
if(itp < nnt){
ix = d_tisspoints[itp];
iy = d_tisspoints[itp+nnt];
iz = d_tisspoints[itp+nnt2];
for(jtp=0; jtp<nnt; jtp++){
jx = d_tisspoints[jtp];
jy = d_tisspoints[jtp+nnt];
jz = d_tisspoints[jtp+nnt2];
ixyz = abs(jx-ix) + abs(jy-iy) + abs(jz-iz);
p += d_qt000[jtp]*d_dtt000[ixyz];
}
d_pt000[itp] = p;
}
} | .file "tmpxft_0011ee95_00000000-6_tissueGPU1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i
.type _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i, @function
_Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16tissueGPU1KernelPiPfS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i, .-_Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i
.globl _Z16tissueGPU1KernelPiPfS0_S0_i
.type _Z16tissueGPU1KernelPiPfS0_S0_i, @function
_Z16tissueGPU1KernelPiPfS0_S0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16tissueGPU1KernelPiPfS0_S0_i, .-_Z16tissueGPU1KernelPiPfS0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16tissueGPU1KernelPiPfS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16tissueGPU1KernelPiPfS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/***********************************************************
tissueGPU1.cu
GPU kernel to accumulate contributions of tissue source
strengths qt to tissue solute levels pt.
TWS December 2011
Cuda 10.1 Version, August 2019
************************************************************/
__global__ void tissueGPU1Kernel(int *d_tisspoints, float *d_dtt000, float *d_pt000, float *d_qt000, int nnt)
{
int itp = blockDim.x * blockIdx.x + threadIdx.x;
int jtp,ixyz,ix,iy,iz,jx,jy,jz,nnt2=2*nnt;
float p = 0.;
if(itp < nnt){
ix = d_tisspoints[itp];
iy = d_tisspoints[itp+nnt];
iz = d_tisspoints[itp+nnt2];
for(jtp=0; jtp<nnt; jtp++){
jx = d_tisspoints[jtp];
jy = d_tisspoints[jtp+nnt];
jz = d_tisspoints[jtp+nnt2];
ixyz = abs(jx-ix) + abs(jy-iy) + abs(jz-iz);
p += d_qt000[jtp]*d_dtt000[ixyz];
}
d_pt000[itp] = p;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/***********************************************************
tissueGPU1.cu
GPU kernel to accumulate contributions of tissue source
strengths qt to tissue solute levels pt.
TWS December 2011
Cuda 10.1 Version, August 2019
************************************************************/
__global__ void tissueGPU1Kernel(int *d_tisspoints, float *d_dtt000, float *d_pt000, float *d_qt000, int nnt)
{
int itp = blockDim.x * blockIdx.x + threadIdx.x;
int jtp,ixyz,ix,iy,iz,jx,jy,jz,nnt2=2*nnt;
float p = 0.;
if(itp < nnt){
ix = d_tisspoints[itp];
iy = d_tisspoints[itp+nnt];
iz = d_tisspoints[itp+nnt2];
for(jtp=0; jtp<nnt; jtp++){
jx = d_tisspoints[jtp];
jy = d_tisspoints[jtp+nnt];
jz = d_tisspoints[jtp+nnt2];
ixyz = abs(jx-ix) + abs(jy-iy) + abs(jz-iz);
p += d_qt000[jtp]*d_dtt000[ixyz];
}
d_pt000[itp] = p;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/***********************************************************
tissueGPU1.cu
GPU kernel to accumulate contributions of tissue source
strengths qt to tissue solute levels pt.
TWS December 2011
Cuda 10.1 Version, August 2019
************************************************************/
__global__ void tissueGPU1Kernel(int *d_tisspoints, float *d_dtt000, float *d_pt000, float *d_qt000, int nnt)
{
int itp = blockDim.x * blockIdx.x + threadIdx.x;
int jtp,ixyz,ix,iy,iz,jx,jy,jz,nnt2=2*nnt;
float p = 0.;
if(itp < nnt){
ix = d_tisspoints[itp];
iy = d_tisspoints[itp+nnt];
iz = d_tisspoints[itp+nnt2];
for(jtp=0; jtp<nnt; jtp++){
jx = d_tisspoints[jtp];
jy = d_tisspoints[jtp+nnt];
jz = d_tisspoints[jtp+nnt2];
ixyz = abs(jx-ix) + abs(jy-iy) + abs(jz-iz);
p += d_qt000[jtp]*d_dtt000[ixyz];
}
d_pt000[itp] = p;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16tissueGPU1KernelPiPfS0_S0_i
.globl _Z16tissueGPU1KernelPiPfS0_S0_i
.p2align 8
.type _Z16tissueGPU1KernelPiPfS0_S0_i,@function
_Z16tissueGPU1KernelPiPfS0_S0_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
v_add_nc_u32_e32 v3, s2, v1
s_lshl_b32 s10, s2, 1
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_nc_u32_e32 v5, s10, v1
s_mov_b32 s11, 0
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s3, s11
s_lshl_b64 s[10:11], s[10:11], 2
v_ashrrev_i32_e32 v6, 31, v5
s_lshl_b64 s[12:13], s[2:3], 2
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b32 v0, v[7:8], off
global_load_b32 v5, v[3:4], off
global_load_b32 v7, v[9:10], off
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_add_u32 s14, s4, s12
s_addc_u32 s15, s5, s13
s_add_u32 s16, s4, s10
s_addc_u32 s17, s5, s11
s_clause 0x2
s_load_b32 s3, s[4:5], 0x0
s_load_b32 s14, s[14:15], 0x0
s_load_b32 s15, s[16:17], 0x0
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(2) lgkmcnt(0)
v_sub_nc_u32_e32 v3, s3, v0
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v8, s14, v5
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v9, s15, v7
s_load_b32 s3, s[8:9], 0x0
s_add_u32 s8, s8, 4
v_sub_nc_u32_e32 v10, 0, v3
v_sub_nc_u32_e32 v11, 0, v8
v_sub_nc_u32_e32 v12, 0, v9
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s2, 0
v_max_i32_e32 v3, v3, v10
v_max_i32_e32 v8, v8, v11
v_max_i32_e32 v9, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v8, v3, v9
v_lshlrev_b64 v[8:9], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v3, v[8:9], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v6, s3, v3
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16tissueGPU1KernelPiPfS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16tissueGPU1KernelPiPfS0_S0_i, .Lfunc_end0-_Z16tissueGPU1KernelPiPfS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16tissueGPU1KernelPiPfS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z16tissueGPU1KernelPiPfS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/***********************************************************
tissueGPU1.cu
GPU kernel to accumulate contributions of tissue source
strengths qt to tissue solute levels pt.
TWS December 2011
Cuda 10.1 Version, August 2019
************************************************************/
__global__ void tissueGPU1Kernel(int *d_tisspoints, float *d_dtt000, float *d_pt000, float *d_qt000, int nnt)
{
int itp = blockDim.x * blockIdx.x + threadIdx.x;
int jtp,ixyz,ix,iy,iz,jx,jy,jz,nnt2=2*nnt;
float p = 0.;
if(itp < nnt){
ix = d_tisspoints[itp];
iy = d_tisspoints[itp+nnt];
iz = d_tisspoints[itp+nnt2];
for(jtp=0; jtp<nnt; jtp++){
jx = d_tisspoints[jtp];
jy = d_tisspoints[jtp+nnt];
jz = d_tisspoints[jtp+nnt2];
ixyz = abs(jx-ix) + abs(jy-iy) + abs(jz-iz);
p += d_qt000[jtp]*d_dtt000[ixyz];
}
d_pt000[itp] = p;
}
} | .text
.file "tissueGPU1Kernel.hip"
.globl _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i # -- Begin function _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.p2align 4, 0x90
.type _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i,@function
_Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i: # @_Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16tissueGPU1KernelPiPfS0_S0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i, .Lfunc_end0-_Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16tissueGPU1KernelPiPfS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16tissueGPU1KernelPiPfS0_S0_i,@object # @_Z16tissueGPU1KernelPiPfS0_S0_i
.section .rodata,"a",@progbits
.globl _Z16tissueGPU1KernelPiPfS0_S0_i
.p2align 3, 0x0
_Z16tissueGPU1KernelPiPfS0_S0_i:
.quad _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.size _Z16tissueGPU1KernelPiPfS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16tissueGPU1KernelPiPfS0_S0_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16tissueGPU1KernelPiPfS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16tissueGPU1KernelPiPfS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0e7624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ; /* 0x0000001fff0f7819 */
/* 0x000fe20000011400 */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0x9e0 ; /* 0x0000092000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R8, R14, -0x1, RZ ; /* 0xffffffff0e087810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe40000000f00 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f26070 */
/*0100*/ IMAD.WIDE R2, R0, R16, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0210 */
/*0110*/ IMAD R7, R7, 0x2, R0 ; /* 0x0000000207077824 */
/* 0x000fe200078e0200 */
/*0120*/ LOP3.LUT R21, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e157812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD.WIDE R4, R16, c[0x0][0x180], R2 ; /* 0x0000600010047a25 */
/* 0x000fe200078e0202 */
/*0140*/ LDG.E R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000166000c1e1900 */
/*0150*/ IMAD.WIDE R6, R7, R16, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0210 */
/*0160*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000162000c1e1900 */
/*0170*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003f05270 */
/*0180*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000162000c1e1900 */
/*0190*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*01a0*/ SHF.R.S32.HI R22, RZ, 0x1f, R14 ; /* 0x0000001fff167819 */
/* 0x000fe2000001140e */
/*01b0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*01c0*/ @!P1 BRA 0x720 ; /* 0x0000055000009947 */
/* 0x000fec0003800000 */
/*01d0*/ LEA R4, P1, R14.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000e047a11 */
/* 0x041fe200078210ff */
/*01e0*/ IMAD.SHL.U32 R3, R14, 0x2, RZ ; /* 0x000000020e037824 */
/* 0x000fe200078e00ff */
/*01f0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fe200000001ff */
/*0200*/ IADD3 R23, -R21, c[0x0][0x180], RZ ; /* 0x0000600015177a10 */
/* 0x000fe20007ffe1ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R4, P2, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007f5e0ff */
/*0230*/ IMAD.WIDE R2, R3, R16, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0210 */
/*0240*/ LEA.HI.X R5, R14, c[0x0][0x164], R22, 0x2, P1 ; /* 0x000059000e057a11 */
/* 0x000fc400008f1416 */
/*0250*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0605 */
/*02a0*/ LDG.E R25, [R6.64] ; /* 0x0000000406197981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R24, [R4.64+-0x8] ; /* 0xfffff80404187981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R27, [R2.64] ; /* 0x00000004021b7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R8, [R4.64+-0x4] ; /* 0xfffffc0404087981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040406097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R26, [R4.64+0x4] ; /* 0x00000404041a7981 */
/* 0x000f22000c1e1900 */
/*0310*/ IMAD.IADD R25, R25, 0x1, -R18 ; /* 0x0000000119197824 */
/* 0x024fc400078e0a12 */
/*0320*/ IMAD.IADD R24, R24, 0x1, -R19 ; /* 0x0000000118187824 */
/* 0x008fe400078e0a13 */
/*0330*/ IMAD.IADD R27, R27, 0x1, -R20.reuse ; /* 0x000000011b1b7824 */
/* 0x110fe200078e0a14 */
/*0340*/ IABS R25, R25 ; /* 0x0000001900197213 */
/* 0x000fe40000000000 */
/*0350*/ IABS R24, R24 ; /* 0x0000001800187213 */
/* 0x000fe40000000000 */
/*0360*/ IABS R29, R27 ; /* 0x0000001b001d7213 */
/* 0x000fe40000000000 */
/*0370*/ LDG.E R27, [R6.64+0x8] ; /* 0x00000804061b7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IADD3 R29, R29, R24, R25 ; /* 0x000000181d1d7210 */
/* 0x000fe20007ffe019 */
/*0390*/ IMAD.IADD R8, R8, 0x1, -R19 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a13 */
/*03a0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.IADD R11, R11, 0x1, -R20 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0a14 */
/*03c0*/ IADD3 R9, -R18, R9, RZ ; /* 0x0000000912097210 */
/* 0x000fc40007ffe1ff */
/*03d0*/ LDG.E R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000f22000c1e1900 */
/*03e0*/ IABS R8, R8 ; /* 0x0000000800087213 */
/* 0x000fe40000000000 */
/*03f0*/ IABS R9, R9 ; /* 0x0000000900097213 */
/* 0x000fe40000000000 */
/*0400*/ IABS R11, R11 ; /* 0x0000000b000b7213 */
/* 0x000fc80000000000 */
/*0410*/ IADD3 R11, R11, R8, R9 ; /* 0x000000080b0b7210 */
/* 0x000fe20007ffe009 */
/*0420*/ IMAD.WIDE R8, R29, R16, c[0x0][0x168] ; /* 0x00005a001d087625 */
/* 0x000fca00078e0210 */
/*0430*/ LDG.E R29, [R8.64] ; /* 0x00000004081d7981 */
/* 0x000124000c1e1900 */
/*0440*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe200078e000c */
/*0450*/ MOV R9, R13 ; /* 0x0000000d00097202 */
/* 0x000fca0000000f00 */
/*0460*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R28, [R8.64+0x4] ; /* 0x00000404081c7981 */
/* 0x000f22000c1e1900 */
/*0480*/ IMAD.IADD R27, R27, 0x1, -R18 ; /* 0x000000011b1b7824 */
/* 0x004fe400078e0a12 */
/*0490*/ IMAD.IADD R25, R25, 0x1, -R20 ; /* 0x0000000119197824 */
/* 0x008fc600078e0a14 */
/*04a0*/ IABS R27, R27 ; /* 0x0000001b001b7213 */
/* 0x000fe20000000000 */
/*04b0*/ IMAD.IADD R24, R24, 0x1, -R19 ; /* 0x0000000118187824 */
/* 0x010fe200078e0a13 */
/*04c0*/ IABS R13, R25 ; /* 0x00000019000d7213 */
/* 0x000fe40000000000 */
/*04d0*/ MOV R25, R27 ; /* 0x0000001b00197202 */
/* 0x000fe40000000f00 */
/*04e0*/ IABS R24, R24 ; /* 0x0000001800187213 */
/* 0x000fe20000000000 */
/*04f0*/ LDG.E R27, [R2.64+0xc] ; /* 0x00000c04021b7981 */
/* 0x000ea6000c1e1900 */
/*0500*/ IADD3 R13, R13, R24, R25 ; /* 0x000000180d0d7210 */
/* 0x000fc40007ffe019 */
/*0510*/ LDG.E R25, [R6.64+0xc] ; /* 0x00000c0406197981 */
/* 0x000ee2000c1e1900 */
/*0520*/ FFMA R24, R29, R12, R10 ; /* 0x0000000c1d187223 */
/* 0x000fe4000000000a */
/*0530*/ IMAD.WIDE R10, R11, R16, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e0210 */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000122000c1e1900 */
/*0550*/ IMAD.IADD R26, R26, 0x1, -R19 ; /* 0x000000011a1a7824 */
/* 0x000fe400078e0a13 */
/*0560*/ IMAD.WIDE R12, R13, R16, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fcc00078e0210 */
/*0570*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000922000c1e1900 */
/*0580*/ IABS R10, R26 ; /* 0x0000001a000a7213 */
/* 0x001fe20000000000 */
/*0590*/ IMAD.IADD R27, R27, 0x1, -R20 ; /* 0x000000011b1b7824 */
/* 0x004fe400078e0a14 */
/*05a0*/ IMAD.IADD R25, R25, 0x1, -R18 ; /* 0x0000000119197824 */
/* 0x008fca00078e0a12 */
/*05b0*/ IABS R29, R25 ; /* 0x00000019001d7213 */
/* 0x000fe40000000000 */
/*05c0*/ IABS R25, R27 ; /* 0x0000001b00197213 */
/* 0x000fe40000000000 */
/*05d0*/ MOV R26, R29 ; /* 0x0000001d001a7202 */
/* 0x000fc80000000f00 */
/*05e0*/ IADD3 R25, R25, R10, R26 ; /* 0x0000000a19197210 */
/* 0x000fe20007ffe01a */
/*05f0*/ FFMA R13, R11, R28, R24 ; /* 0x0000001c0b0d7223 */
/* 0x010fe40000000018 */
/*0600*/ LDG.E R24, [R8.64+0x8] ; /* 0x0000080408187981 */
/* 0x000ea4000c1e1900 */
/*0610*/ IMAD.WIDE R10, R25, R16, c[0x0][0x168] ; /* 0x00005a00190a7625 */
/* 0x000fe400078e0210 */
/*0620*/ LDG.E R25, [R8.64+0xc] ; /* 0x00000c0408197981 */
/* 0x000ee8000c1e1900 */
/*0630*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0640*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007f3e0ff */
/*0650*/ IADD3 R23, R23, -0x4, RZ ; /* 0xfffffffc17177810 */
/* 0x000fc60007ffe0ff */
/*0660*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0670*/ ISETP.NE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f25270 */
/*0680*/ IADD3 R4, P3, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f7e0ff */
/*0690*/ IADD3 R6, P4, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007f9e0ff */
/*06a0*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*06c0*/ IADD3.X R7, RZ, R7, RZ, P4, !PT ; /* 0x00000007ff077210 */
/* 0x000fe200027fe4ff */
/*06d0*/ FFMA R24, R12, R24, R13 ; /* 0x000000180c187223 */
/* 0x004fe2000000000d */
/*06e0*/ IADD3 R12, P2, R8, 0x10, RZ ; /* 0x00000010080c7810 */
/* 0x000fca0007f5e0ff */
/*06f0*/ IMAD.X R13, RZ, RZ, R9, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e0609 */
/*0700*/ FFMA R10, R10, R25, R24 ; /* 0x000000190a0a7223 */
/* 0x008fe20000000018 */
/*0710*/ @P1 BRA 0x2a0 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0720*/ @!P0 BRA 0x9e0 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R12, P0, R17.reuse, c[0x0][0x180], RZ ; /* 0x00006000110c7a10 */
/* 0x040fe20007f1e0ff */
/*0740*/ IMAD.WIDE R4, R17, R16, c[0x0][0x160] ; /* 0x0000580011047625 */
/* 0x001fc600078e0210 */
/*0750*/ LEA.HI.X.SX32 R23, R17.reuse, R22, 0x1, P0 ; /* 0x0000001611177211 */
/* 0x040fe200000f0eff */
/*0760*/ IMAD R7, R14, 0x2, R17 ; /* 0x000000020e077824 */
/* 0x000fe200078e0211 */
/*0770*/ LEA R9, P0, R12.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000c097a11 */
/* 0x040fe200078010ff */
/*0780*/ IMAD.WIDE R2, R17, R16, c[0x0][0x178] ; /* 0x00005e0011027625 */
/* 0x000fe200078e0210 */
/*0790*/ MOV R11, R4 ; /* 0x00000004000b7202 */
/* 0x000fe40000000f00 */
/*07a0*/ LEA.HI.X R12, R12, c[0x0][0x164], R23, 0x2, P0 ; /* 0x000059000c0c7a11 */
/* 0x000fe200000f1417 */
/*07b0*/ IMAD.WIDE R6, R7, R16, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0210 */
/*07c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*07d0*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0003 */
/*07e0*/ IMAD.MOV.U32 R14, RZ, RZ, R5 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0005 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000e */
/*0800*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000b */
/*0820*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ea2000c1e1900 */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000c */
/*0840*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee8000c1e1900 */
/*0850*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000124000c1e1900 */
/*0860*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x001fe200078e000d */
/*0870*/ IADD3 R23, -R20, R23, RZ ; /* 0x0000001714177210 */
/* 0x024fe20007ffe1ff */
/*0880*/ IMAD.IADD R17, R3, 0x1, -R18 ; /* 0x0000000103117824 */
/* 0x008fe400078e0a12 */
/*0890*/ IMAD.IADD R22, R4, 0x1, -R19 ; /* 0x0000000104167824 */
/* 0x010fc600078e0a13 */
/*08a0*/ IABS R17, R17 ; /* 0x0000001100117213 */
/* 0x000fe40000000000 */
/*08b0*/ IABS R3, R23 ; /* 0x0000001700037213 */
/* 0x000fe40000000000 */
/*08c0*/ IABS R22, R22 ; /* 0x0000001600167213 */
/* 0x000fc80000000000 */
/*08d0*/ IADD3 R3, R3, R22, R17 ; /* 0x0000001603037210 */
/* 0x000fe20007ffe011 */
/*08e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0008 */
/*08f0*/ IMAD.WIDE R2, R3, R16, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe400078e0210 */
/*0900*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IADD3 R21, R21, -0x1, RZ ; /* 0xffffffff15157810 */
/* 0x000fc80007ffe0ff */
/*0930*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0950*/ IADD3 R9, P3, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f7e0ff */
/*0960*/ IADD3 R11, P4, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007f9e0ff */
/*0970*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f5e0ff */
/*0980*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0990*/ IMAD.X R12, RZ, RZ, R12, P3 ; /* 0x000000ffff0c7224 */
/* 0x000fe200018e060c */
/*09a0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*09b0*/ IMAD.X R14, RZ, RZ, R14, P4 ; /* 0x000000ffff0e7224 */
/* 0x000fc400020e060e */
/*09c0*/ FFMA R10, R3, R4, R10 ; /* 0x00000004030a7223 */
/* 0x004fe2000000000a */
/*09d0*/ @P0 BRA 0x7f0 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*09e0*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x001fc800078010ff */
/*09f0*/ LEA.HI.X R3, R0, c[0x0][0x174], R15, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f140f */
/*0a00*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16tissueGPU1KernelPiPfS0_S0_i
.globl _Z16tissueGPU1KernelPiPfS0_S0_i
.p2align 8
.type _Z16tissueGPU1KernelPiPfS0_S0_i,@function
_Z16tissueGPU1KernelPiPfS0_S0_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
v_add_nc_u32_e32 v3, s2, v1
s_lshl_b32 s10, s2, 1
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_nc_u32_e32 v5, s10, v1
s_mov_b32 s11, 0
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s3, s11
s_lshl_b64 s[10:11], s[10:11], 2
v_ashrrev_i32_e32 v6, 31, v5
s_lshl_b64 s[12:13], s[2:3], 2
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b32 v0, v[7:8], off
global_load_b32 v5, v[3:4], off
global_load_b32 v7, v[9:10], off
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_add_u32 s14, s4, s12
s_addc_u32 s15, s5, s13
s_add_u32 s16, s4, s10
s_addc_u32 s17, s5, s11
s_clause 0x2
s_load_b32 s3, s[4:5], 0x0
s_load_b32 s14, s[14:15], 0x0
s_load_b32 s15, s[16:17], 0x0
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(2) lgkmcnt(0)
v_sub_nc_u32_e32 v3, s3, v0
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v8, s14, v5
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v9, s15, v7
s_load_b32 s3, s[8:9], 0x0
s_add_u32 s8, s8, 4
v_sub_nc_u32_e32 v10, 0, v3
v_sub_nc_u32_e32 v11, 0, v8
v_sub_nc_u32_e32 v12, 0, v9
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s2, 0
v_max_i32_e32 v3, v3, v10
v_max_i32_e32 v8, v8, v11
v_max_i32_e32 v9, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v8, v3, v9
v_lshlrev_b64 v[8:9], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v3, v[8:9], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v6, s3, v3
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16tissueGPU1KernelPiPfS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16tissueGPU1KernelPiPfS0_S0_i, .Lfunc_end0-_Z16tissueGPU1KernelPiPfS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16tissueGPU1KernelPiPfS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z16tissueGPU1KernelPiPfS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011ee95_00000000-6_tissueGPU1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i
.type _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i, @function
_Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16tissueGPU1KernelPiPfS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i, .-_Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i
.globl _Z16tissueGPU1KernelPiPfS0_S0_i
.type _Z16tissueGPU1KernelPiPfS0_S0_i, @function
_Z16tissueGPU1KernelPiPfS0_S0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z16tissueGPU1KernelPiPfS0_S0_iPiPfS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16tissueGPU1KernelPiPfS0_S0_i, .-_Z16tissueGPU1KernelPiPfS0_S0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16tissueGPU1KernelPiPfS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16tissueGPU1KernelPiPfS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tissueGPU1Kernel.hip"
.globl _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i # -- Begin function _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.p2align 4, 0x90
.type _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i,@function
_Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i: # @_Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16tissueGPU1KernelPiPfS0_S0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i, .Lfunc_end0-_Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16tissueGPU1KernelPiPfS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16tissueGPU1KernelPiPfS0_S0_i,@object # @_Z16tissueGPU1KernelPiPfS0_S0_i
.section .rodata,"a",@progbits
.globl _Z16tissueGPU1KernelPiPfS0_S0_i
.p2align 3, 0x0
_Z16tissueGPU1KernelPiPfS0_S0_i:
.quad _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.size _Z16tissueGPU1KernelPiPfS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16tissueGPU1KernelPiPfS0_S0_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__tissueGPU1KernelPiPfS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16tissueGPU1KernelPiPfS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define NDIM 2
template <int8_t kNdim>
class IndexIterator {
public:
__host__ __device__ void Set(int64_t i) {
int8_t j = kNdim;
for (; --j >= 1;) {
index_[j] = i % shape_[j];
i /= shape_[j];
}
index_[j] = i % shape_[j];
}
__host__ __device__ int64_t* index() { return index_; }
private:
//const int64_t* shape_;
int64_t shape_[kNdim];
//int64_t total_size_{};
//int64_t raw_index_{};
//int64_t step_{};
int64_t index_[kNdim];
};
__global__ void test(IndexIterator<NDIM> i) {
i.Set(1);
printf("1\n", i.index()[0]);
}
int main() {
IndexIterator<NDIM> i{};
test<<<1,1>>>(i);
} | code for sm_80
Function : _Z4test13IndexIteratorILa2EE
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ IADD3 R0, P1, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007f3e0ff */
/*0040*/ IADD3 R6, P2, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f5e0ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0060*/ IMAD.X R0, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff007624 */
/* 0x000fe400008e06ff */
/*0070*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P2 ; /* 0x00000900ff077624 */
/* 0x000fc600010e06ff */
/*0080*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80003f06100 */
/*0090*/ SEL R5, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff057a07 */
/* 0x000fe40000000000 */
/*00a0*/ SEL R4, RZ, c[0x0][0x168], P0 ; /* 0x00005a00ff047a07 */
/* 0x000fe40000000000 */
/*00b0*/ LOP3.LUT R0, R5, c[0x0][0x164], RZ, 0xfc, !PT ; /* 0x0000590005007a12 */
/* 0x000fc800078efcff */
/*00c0*/ ISETP.NE.U32.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25070 */
/*00d0*/ @!P1 BRA 0x130 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R0, 0x100 ; /* 0x0000010000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x340 ; /* 0x0000024000007944 */
/* 0x000fea0003c00000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0120*/ BRA 0x260 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0130*/ I2F.U32.RP R0, c[0x0][0x160] ; /* 0x0000580000007b06 */
/* 0x000e220000209000 */
/*0140*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fce0003f25070 */
/*0150*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*01a0*/ IMAD R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a24 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01c0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01e0*/ IMAD R4, R3, c[0x0][0x160], R4 ; /* 0x0000580003047a24 */
/* 0x000fe400078e0204 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06070 */
/*0210*/ @P0 IADD3 R4, R4, -c[0x0][0x160], RZ ; /* 0x8000580004040a10 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06070 */
/*0230*/ @P0 IADD3 R4, R4, -c[0x0][0x160], RZ ; /* 0x8000580004040a10 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff049a12 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0260*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0270*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100a00 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0290*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*02a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*02b0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*02c0*/ MOV R11, 0x330 ; /* 0x00000330000b7802 */
/* 0x000fe40000000f00 */
/*02d0*/ MOV R20, 0x2b0 ; /* 0x000002b000147802 */
/* 0x000fe40000000f00 */
/*02e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*02f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0300*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0310*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0320*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R2, P1, RZ, -c[0x0][0x160], RZ ; /* 0x80005800ff027a10 */
/* 0x000fe40007f3e0ff */
/*0350*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fc60003f03270 */
/*0360*/ IMAD.X R3, RZ, RZ, ~c[0x0][0x164], P1 ; /* 0x80005900ff037624 */
/* 0x000fe200008e06ff */
/*0370*/ SEL R2, R2, c[0x0][0x160], !P0 ; /* 0x0000580002027a07 */
/* 0x000fc80004000000 */
/*0380*/ SEL R3, R3, c[0x0][0x164], !P0 ; /* 0x0000590003037a07 */
/* 0x000fc80004000000 */
/*0390*/ I2F.U64.RP R12, R2 ; /* 0x00000002000c7312 */
/* 0x000e300000309000 */
/*03a0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*03b0*/ IADD3 R8, R12, 0x1ffffffe, RZ ; /* 0x1ffffffe0c087810 */
/* 0x001fcc0007ffe0ff */
/*03c0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*03d0*/ IMAD.WIDE.U32 R10, R8, R2, RZ ; /* 0x00000002080a7225 */
/* 0x001fc800078e00ff */
/*03e0*/ IMAD R11, R8, R3, R11 ; /* 0x00000003080b7224 */
/* 0x000fe200078e020b */
/*03f0*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*0400*/ IMAD R11, R9, R2, R11 ; /* 0x00000002090b7224 */
/* 0x000fe400078e020b */
/*0410*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.X R15, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0e0b */
/*0430*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0440*/ IMAD R17, R9, R15.reuse, RZ ; /* 0x0000000f09117224 */
/* 0x080fe400078e02ff */
/*0450*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0460*/ IMAD.HI.U32 R15, R9, R15, RZ ; /* 0x0000000f090f7227 */
/* 0x000fc800078e00ff */
/*0470*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fca000782000a */
/*0480*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fe20007f5e0ff */
/*0490*/ IMAD.X R10, R15, 0x1, R9, P0 ; /* 0x000000010f0a7824 */
/* 0x000fc800000e0609 */
/*04a0*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fe200078e00ff */
/*04b0*/ IADD3.X R13, RZ, RZ, R10, P2, P1 ; /* 0x000000ffff0d7210 */
/* 0x000fe400017e240a */
/*04c0*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f26270 */
/*04d0*/ IMAD R9, R11, R3, R9 ; /* 0x000000030b097224 */
/* 0x000fe200078e0209 */
/*04e0*/ IADD3 R15, P0, RZ, -R8, RZ ; /* 0x80000008ff0f7210 */
/* 0x000fc60007f1e0ff */
/*04f0*/ IMAD R9, R13, R2, R9 ; /* 0x000000020d097224 */
/* 0x000fe400078e0209 */
/*0500*/ IMAD.HI.U32 R10, R11, R15, RZ ; /* 0x0000000f0b0a7227 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.X R8, RZ, RZ, ~R9, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e09 */
/*0520*/ IADD3 R9, P4, RZ, -R4, RZ ; /* 0x80000004ff097210 */
/* 0x000fc60007f9e0ff */
/*0530*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fe2000780000a */
/*0540*/ SEL R4, R9, R4, !P1 ; /* 0x0000000409047207 */
/* 0x000fc60004800000 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.HI.U32 R11, P2, R13, R15, R10 ; /* 0x0000000f0d0b7227 */
/* 0x000fc8000784000a */
/*0570*/ IMAD R10, R13.reuse, R8.reuse, RZ ; /* 0x000000080d0a7224 */
/* 0x0c0fe400078e02ff */
/*0580*/ IMAD.HI.U32 R8, R13, R8, RZ ; /* 0x000000080d087227 */
/* 0x000fc600078e00ff */
/*0590*/ IADD3 R11, P3, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x000fe20007f7e0ff */
/*05a0*/ IMAD.X R10, RZ, RZ, ~R5, P4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400020e0e05 */
/*05b0*/ IMAD.X R13, R8, 0x1, R13, P0 ; /* 0x00000001080d7824 */
/* 0x000fe400000e060d */
/*05c0*/ IMAD.HI.U32 R8, R11, R4, RZ ; /* 0x000000040b087227 */
/* 0x000fe200078e00ff */
/*05d0*/ SEL R10, R10, R5, !P1 ; /* 0x000000050a0a7207 */
/* 0x000fe40004800000 */
/*05e0*/ IADD3.X R13, RZ, RZ, R13, P3, P2 ; /* 0x000000ffff0d7210 */
/* 0x000fc60001fe440d */
/*05f0*/ IMAD.WIDE.U32 R8, R11, R10, R8 ; /* 0x0000000a0b087225 */
/* 0x000fc800078e0008 */
/*0600*/ IMAD R11, R13.reuse, R10, RZ ; /* 0x0000000a0d0b7224 */
/* 0x040fe400078e02ff */
/*0610*/ IMAD.HI.U32 R8, P0, R13, R4, R8 ; /* 0x000000040d087227 */
/* 0x000fc80007800008 */
/*0620*/ IMAD.HI.U32 R5, R13, R10, RZ ; /* 0x0000000a0d057227 */
/* 0x000fe200078e00ff */
/*0630*/ IADD3 R11, P2, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x000fc60007f5e0ff */
/*0640*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe400000e0605 */
/*0650*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0670*/ IADD3 R13, P2, -R8, R4, RZ ; /* 0x00000004080d7210 */
/* 0x000fe20007f5e1ff */
/*0680*/ IMAD R11, R11, R3, R9 ; /* 0x000000030b0b7224 */
/* 0x000fc600078e0209 */
/*0690*/ ISETP.GE.U32.AND P0, PT, R13, R2.reuse, PT ; /* 0x000000020d00720c */
/* 0x080fe20003f06070 */
/*06a0*/ IMAD R5, R5, R2, R11 ; /* 0x0000000205057224 */
/* 0x000fc800078e020b */
/*06b0*/ IMAD.X R5, R10, 0x1, ~R5, P2 ; /* 0x000000010a057824 */
/* 0x000fe200010e0e05 */
/*06c0*/ IADD3 R9, P2, R13, -R2, RZ ; /* 0x800000020d097210 */
/* 0x000fc80007f5e0ff */
/*06d0*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, R3, PT, P0 ; /* 0x000000030500720c */
/* 0x040fe20003f06100 */
/*06e0*/ IMAD.X R11, R5, 0x1, ~R3, P2 ; /* 0x00000001050b7824 */
/* 0x000fc600010e0e03 */
/*06f0*/ SEL R9, R9, R13, P0 ; /* 0x0000000d09097207 */
/* 0x000fe40000000000 */
/*0700*/ SEL R11, R11, R5, P0 ; /* 0x000000050b0b7207 */
/* 0x000fe40000000000 */
/*0710*/ ISETP.GE.U32.AND P0, PT, R9.reuse, R2.reuse, PT ; /* 0x000000020900720c */
/* 0x0c0fe40003f06070 */
/*0720*/ IADD3 R4, P2, R9, -R2, RZ ; /* 0x8000000209047210 */
/* 0x000fe40007f5e0ff */
/*0730*/ ISETP.GE.U32.AND.EX P0, PT, R11, R3, PT, P0 ; /* 0x000000030b00720c */
/* 0x000fc60003f06100 */
/*0740*/ IMAD.X R5, R11, 0x1, ~R3, P2 ; /* 0x000000010b057824 */
/* 0x000fe200010e0e03 */
/*0750*/ SEL R4, R4, R9, P0 ; /* 0x0000000904047207 */
/* 0x000fc80000000000 */
/*0760*/ SEL R5, R5, R11, P0 ; /* 0x0000000b05057207 */
/* 0x000fe40000000000 */
/*0770*/ IADD3 R3, P2, RZ, -R4.reuse, RZ ; /* 0x80000004ff037210 */
/* 0x080fe40007f5e0ff */
/*0780*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f05070 */
/*0790*/ SEL R4, R3, R4, !P1 ; /* 0x0000000403047207 */
/* 0x000fe20004800000 */
/*07a0*/ IMAD.X R2, RZ, RZ, ~R5, P2 ; /* 0x000000ffff027224 */
/* 0x000fe200010e0e05 */
/*07b0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fe20003f05300 */
/*07c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc600078e00ff */
/*07d0*/ SEL R5, R2, R5, !P1 ; /* 0x0000000502057207 */
/* 0x000fe20004800000 */
/*07e0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*07f0*/ SEL R4, R4, 0xffffffff, P0 ; /* 0xffffffff04047807 */
/* 0x000fe40000000000 */
/*0800*/ SEL R5, R5, 0xffffffff, P0 ; /* 0xffffffff05057807 */
/* 0x000fe20000000000 */
/*0810*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7e002007950 */
/* 0x000fec0003c3ffff */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define NDIM 2
template <int8_t kNdim>
class IndexIterator {
public:
__host__ __device__ void Set(int64_t i) {
int8_t j = kNdim;
for (; --j >= 1;) {
index_[j] = i % shape_[j];
i /= shape_[j];
}
index_[j] = i % shape_[j];
}
__host__ __device__ int64_t* index() { return index_; }
private:
//const int64_t* shape_;
int64_t shape_[kNdim];
//int64_t total_size_{};
//int64_t raw_index_{};
//int64_t step_{};
int64_t index_[kNdim];
};
__global__ void test(IndexIterator<NDIM> i) {
i.Set(1);
printf("1\n", i.index()[0]);
}
int main() {
IndexIterator<NDIM> i{};
test<<<1,1>>>(i);
} | .file "tmpxft_0017fb6f_00000000-6_indexer2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
.type _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE, @function
_Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4test13IndexIteratorILa2EE(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE, .-_Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
.globl _Z4test13IndexIteratorILa2EE
.type _Z4test13IndexIteratorILa2EE, @function
_Z4test13IndexIteratorILa2EE:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4test13IndexIteratorILa2EE, .-_Z4test13IndexIteratorILa2EE
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 64(%rsp)
movdqa 48(%rsp), %xmm1
movaps %xmm1, 80(%rsp)
leaq 64(%rsp), %rdi
call _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4test13IndexIteratorILa2EE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4test13IndexIteratorILa2EE(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define NDIM 2
template <int8_t kNdim>
class IndexIterator {
public:
__host__ __device__ void Set(int64_t i) {
int8_t j = kNdim;
for (; --j >= 1;) {
index_[j] = i % shape_[j];
i /= shape_[j];
}
index_[j] = i % shape_[j];
}
__host__ __device__ int64_t* index() { return index_; }
private:
//const int64_t* shape_;
int64_t shape_[kNdim];
//int64_t total_size_{};
//int64_t raw_index_{};
//int64_t step_{};
int64_t index_[kNdim];
};
__global__ void test(IndexIterator<NDIM> i) {
i.Set(1);
printf("1\n", i.index()[0]);
}
int main() {
IndexIterator<NDIM> i{};
test<<<1,1>>>(i);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NDIM 2
template <int8_t kNdim>
class IndexIterator {
public:
__host__ __device__ void Set(int64_t i) {
int8_t j = kNdim;
for (; --j >= 1;) {
index_[j] = i % shape_[j];
i /= shape_[j];
}
index_[j] = i % shape_[j];
}
__host__ __device__ int64_t* index() { return index_; }
private:
//const int64_t* shape_;
int64_t shape_[kNdim];
//int64_t total_size_{};
//int64_t raw_index_{};
//int64_t step_{};
int64_t index_[kNdim];
};
__global__ void test(IndexIterator<NDIM> i) {
i.Set(1);
printf("1\n", i.index()[0]);
}
int main() {
IndexIterator<NDIM> i{};
test<<<1,1>>>(i);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NDIM 2
template <int8_t kNdim>
class IndexIterator {
public:
__host__ __device__ void Set(int64_t i) {
int8_t j = kNdim;
for (; --j >= 1;) {
index_[j] = i % shape_[j];
i /= shape_[j];
}
index_[j] = i % shape_[j];
}
__host__ __device__ int64_t* index() { return index_; }
private:
//const int64_t* shape_;
int64_t shape_[kNdim];
//int64_t total_size_{};
//int64_t raw_index_{};
//int64_t step_{};
int64_t index_[kNdim];
};
__global__ void test(IndexIterator<NDIM> i) {
i.Set(1);
printf("1\n", i.index()[0]);
}
int main() {
IndexIterator<NDIM> i{};
test<<<1,1>>>(i);
} | .text
.file "indexer2.hip"
.globl _Z19__device_stub__test13IndexIteratorILa2EE # -- Begin function _Z19__device_stub__test13IndexIteratorILa2EE
.p2align 4, 0x90
.type _Z19__device_stub__test13IndexIteratorILa2EE,@function
_Z19__device_stub__test13IndexIteratorILa2EE: # @_Z19__device_stub__test13IndexIteratorILa2EE
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z4test13IndexIteratorILa2EE, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__test13IndexIteratorILa2EE, .Lfunc_end0-_Z19__device_stub__test13IndexIteratorILa2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4test13IndexIteratorILa2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4test13IndexIteratorILa2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4test13IndexIteratorILa2EE,@object # @_Z4test13IndexIteratorILa2EE
.section .rodata,"a",@progbits
.globl _Z4test13IndexIteratorILa2EE
.p2align 3, 0x0
_Z4test13IndexIteratorILa2EE:
.quad _Z19__device_stub__test13IndexIteratorILa2EE
.size _Z4test13IndexIteratorILa2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4test13IndexIteratorILa2EE"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__test13IndexIteratorILa2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4test13IndexIteratorILa2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017fb6f_00000000-6_indexer2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
.type _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE, @function
_Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4test13IndexIteratorILa2EE(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE, .-_Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
.globl _Z4test13IndexIteratorILa2EE
.type _Z4test13IndexIteratorILa2EE, @function
_Z4test13IndexIteratorILa2EE:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4test13IndexIteratorILa2EE, .-_Z4test13IndexIteratorILa2EE
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 64(%rsp)
movdqa 48(%rsp), %xmm1
movaps %xmm1, 80(%rsp)
leaq 64(%rsp), %rdi
call _Z42__device_stub__Z4test13IndexIteratorILa2EER13IndexIteratorILa2EE
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4test13IndexIteratorILa2EE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4test13IndexIteratorILa2EE(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "indexer2.hip"
.globl _Z19__device_stub__test13IndexIteratorILa2EE # -- Begin function _Z19__device_stub__test13IndexIteratorILa2EE
.p2align 4, 0x90
.type _Z19__device_stub__test13IndexIteratorILa2EE,@function
_Z19__device_stub__test13IndexIteratorILa2EE: # @_Z19__device_stub__test13IndexIteratorILa2EE
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z4test13IndexIteratorILa2EE, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__test13IndexIteratorILa2EE, .Lfunc_end0-_Z19__device_stub__test13IndexIteratorILa2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4test13IndexIteratorILa2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4test13IndexIteratorILa2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4test13IndexIteratorILa2EE,@object # @_Z4test13IndexIteratorILa2EE
.section .rodata,"a",@progbits
.globl _Z4test13IndexIteratorILa2EE
.p2align 3, 0x0
_Z4test13IndexIteratorILa2EE:
.quad _Z19__device_stub__test13IndexIteratorILa2EE
.size _Z4test13IndexIteratorILa2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4test13IndexIteratorILa2EE"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__test13IndexIteratorILa2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4test13IndexIteratorILa2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <cuda.h>
#define THREADS 128
#define BLOCKS 16
#define SIZE 2048
__global__ void add(int *array) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > SIZE) return;
int temp = 0;
int before = (idx + 1) % SIZE;
int after = idx - 1;
if (after < 0) after = SIZE - 1;
temp += array[idx];
temp += array[before];
temp += array[after];
__syncthreads(); // Barrera...
array[idx] = temp;
}
void init(int* h_v, int numb) {
for (int i = 0; i < SIZE; i++) {
h_v[i] = numb;
}
}
int main( void ) {
int *result, *h_a;
int *dev_a;
int size = SIZE * sizeof(int);
result = (int*) malloc( size );
h_a = (int*) malloc( size );
if (h_a == NULL || result == NULL) {
fprintf(stderr, "Error allocating memory... %s\n", strerror(errno));
exit(1);
}
memset(result, 0, size);
init(h_a, 3);
cudaMalloc(&dev_a, size);
// se transfieren los datos a memoria de dispositivo...
cudaMemcpy(dev_a, h_a, size, cudaMemcpyHostToDevice);
add<<<BLOCKS, THREADS>>>(dev_a);
// se transfieren los datos del dispositivo a memoria.
cudaMemcpy(result, dev_a, size, cudaMemcpyDeviceToHost);
fprintf(stdout, "Result %s\n", "");
for (int i = 0; i < SIZE; i++) {
fprintf(stderr, " %d ", result[i]);
if ((i + 1) % 10 == 0) fprintf(stdout, "%s\n", "");
}
fprintf(stdout, "%s\n", "");
free(h_a), free(result);
cudaFree(dev_a);
return 0;
} | code for sm_80
Function : _Z3addPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x800, PT ; /* 0x000008000200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R2.reuse, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f06270 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00b0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe40007ffe0ff */
/*00c0*/ LEA.HI R3, R3, R0, RZ, 0xb ; /* 0x0000000003037211 */
/* 0x000fe400078f58ff */
/*00d0*/ SEL R6, R4, 0x7ff, P0 ; /* 0x000007ff04067807 */
/* 0x000fc40000000000 */
/*00e0*/ LOP3.LUT R3, R3, 0xfffff800, RZ, 0xc0, !PT ; /* 0xfffff80003037812 */
/* 0x000fc600078ec0ff */
/*00f0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.IADD R4, R0, 0x1, -R3 ; /* 0x0000000100047824 */
/* 0x000fe400078e0a03 */
/*0110*/ IMAD.WIDE R2, R2, R5.reuse, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x080fe200078e0205 */
/*0120*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea6000c1e1900 */
/*0130*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0140*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000eaa000c1e1900 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ IADD3 R9, R6, R4, R9 ; /* 0x0000000406097210 */
/* 0x004fca0007ffe009 */
/*0180*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <cuda.h>
#define THREADS 128
#define BLOCKS 16
#define SIZE 2048
__global__ void add(int *array) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > SIZE) return;
int temp = 0;
int before = (idx + 1) % SIZE;
int after = idx - 1;
if (after < 0) after = SIZE - 1;
temp += array[idx];
temp += array[before];
temp += array[after];
__syncthreads(); // Barrera...
array[idx] = temp;
}
void init(int* h_v, int numb) {
for (int i = 0; i < SIZE; i++) {
h_v[i] = numb;
}
}
int main( void ) {
int *result, *h_a;
int *dev_a;
int size = SIZE * sizeof(int);
result = (int*) malloc( size );
h_a = (int*) malloc( size );
if (h_a == NULL || result == NULL) {
fprintf(stderr, "Error allocating memory... %s\n", strerror(errno));
exit(1);
}
memset(result, 0, size);
init(h_a, 3);
cudaMalloc(&dev_a, size);
// se transfieren los datos a memoria de dispositivo...
cudaMemcpy(dev_a, h_a, size, cudaMemcpyHostToDevice);
add<<<BLOCKS, THREADS>>>(dev_a);
// se transfieren los datos del dispositivo a memoria.
cudaMemcpy(result, dev_a, size, cudaMemcpyDeviceToHost);
fprintf(stdout, "Result %s\n", "");
for (int i = 0; i < SIZE; i++) {
fprintf(stderr, " %d ", result[i]);
if ((i + 1) % 10 == 0) fprintf(stdout, "%s\n", "");
}
fprintf(stdout, "%s\n", "");
free(h_a), free(result);
cudaFree(dev_a);
return 0;
} | .file "tmpxft_00002620_00000000-6_suma_afin.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %rax
leaq 8192(%rdi), %rdx
.L4:
movl %esi, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z4initPii, .-_Z4initPii
.globl _Z22__device_stub__Z3addPiPi
.type _Z22__device_stub__Z3addPiPi, @function
_Z22__device_stub__Z3addPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z3addPiPi, .-_Z22__device_stub__Z3addPiPi
.globl _Z3addPi
.type _Z3addPi, @function
_Z3addPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3addPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPi, .-_Z3addPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error allocating memory... %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string ""
.LC2:
.string "Result %s\n"
.LC3:
.string " %d "
.LC4:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
testq %rax, %rax
je .L21
movq %rax, %r15
testq %rbp, %rbp
je .L21
movl $1024, %ecx
movl $0, %eax
movq %rbp, %rdi
rep stosq
movl $3, %esi
movq %r15, %rdi
call _Z4initPii
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L17:
movl $2, %ecx
movl $8192, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %ebx
leaq .LC3(%rip), %r12
leaq .LC1(%rip), %r14
leaq .LC4(%rip), %r13
jmp .L19
.L21:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3addPiPi
jmp .L17
.L18:
addq $1, %rbx
cmpq $2049, %rbx
je .L25
.L19:
movl -4(%rbp,%rbx,4), %ecx
movq %r12, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L18
movq %r14, %rcx
movq %r13, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L25:
leaq .LC1(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <cuda.h>
#define THREADS 128
#define BLOCKS 16
#define SIZE 2048
__global__ void add(int *array) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > SIZE) return;
int temp = 0;
int before = (idx + 1) % SIZE;
int after = idx - 1;
if (after < 0) after = SIZE - 1;
temp += array[idx];
temp += array[before];
temp += array[after];
__syncthreads(); // Barrera...
array[idx] = temp;
}
void init(int* h_v, int numb) {
for (int i = 0; i < SIZE; i++) {
h_v[i] = numb;
}
}
int main( void ) {
int *result, *h_a;
int *dev_a;
int size = SIZE * sizeof(int);
result = (int*) malloc( size );
h_a = (int*) malloc( size );
if (h_a == NULL || result == NULL) {
fprintf(stderr, "Error allocating memory... %s\n", strerror(errno));
exit(1);
}
memset(result, 0, size);
init(h_a, 3);
cudaMalloc(&dev_a, size);
// se transfieren los datos a memoria de dispositivo...
cudaMemcpy(dev_a, h_a, size, cudaMemcpyHostToDevice);
add<<<BLOCKS, THREADS>>>(dev_a);
// se transfieren los datos del dispositivo a memoria.
cudaMemcpy(result, dev_a, size, cudaMemcpyDeviceToHost);
fprintf(stdout, "Result %s\n", "");
for (int i = 0; i < SIZE; i++) {
fprintf(stderr, " %d ", result[i]);
if ((i + 1) % 10 == 0) fprintf(stdout, "%s\n", "");
}
fprintf(stdout, "%s\n", "");
free(h_a), free(result);
cudaFree(dev_a);
return 0;
} | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <hip/hip_runtime.h>
#define THREADS 128
#define BLOCKS 16
#define SIZE 2048
__global__ void add(int *array) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > SIZE) return;
int temp = 0;
int before = (idx + 1) % SIZE;
int after = idx - 1;
if (after < 0) after = SIZE - 1;
temp += array[idx];
temp += array[before];
temp += array[after];
__syncthreads(); // Barrera...
array[idx] = temp;
}
void init(int* h_v, int numb) {
for (int i = 0; i < SIZE; i++) {
h_v[i] = numb;
}
}
int main( void ) {
int *result, *h_a;
int *dev_a;
int size = SIZE * sizeof(int);
result = (int*) malloc( size );
h_a = (int*) malloc( size );
if (h_a == NULL || result == NULL) {
fprintf(stderr, "Error allocating memory... %s\n", strerror(errno));
exit(1);
}
memset(result, 0, size);
init(h_a, 3);
hipMalloc(&dev_a, size);
// se transfieren los datos a memoria de dispositivo...
hipMemcpy(dev_a, h_a, size, hipMemcpyHostToDevice);
add<<<BLOCKS, THREADS>>>(dev_a);
// se transfieren los datos del dispositivo a memoria.
hipMemcpy(result, dev_a, size, hipMemcpyDeviceToHost);
fprintf(stdout, "Result %s\n", "");
for (int i = 0; i < SIZE; i++) {
fprintf(stderr, " %d ", result[i]);
if ((i + 1) % 10 == 0) fprintf(stdout, "%s\n", "");
}
fprintf(stdout, "%s\n", "");
free(h_a), free(result);
hipFree(dev_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <hip/hip_runtime.h>
#define THREADS 128
#define BLOCKS 16
#define SIZE 2048
__global__ void add(int *array) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > SIZE) return;
int temp = 0;
int before = (idx + 1) % SIZE;
int after = idx - 1;
if (after < 0) after = SIZE - 1;
temp += array[idx];
temp += array[before];
temp += array[after];
__syncthreads(); // Barrera...
array[idx] = temp;
}
void init(int* h_v, int numb) {
for (int i = 0; i < SIZE; i++) {
h_v[i] = numb;
}
}
int main( void ) {
int *result, *h_a;
int *dev_a;
int size = SIZE * sizeof(int);
result = (int*) malloc( size );
h_a = (int*) malloc( size );
if (h_a == NULL || result == NULL) {
fprintf(stderr, "Error allocating memory... %s\n", strerror(errno));
exit(1);
}
memset(result, 0, size);
init(h_a, 3);
hipMalloc(&dev_a, size);
// se transfieren los datos a memoria de dispositivo...
hipMemcpy(dev_a, h_a, size, hipMemcpyHostToDevice);
add<<<BLOCKS, THREADS>>>(dev_a);
// se transfieren los datos del dispositivo a memoria.
hipMemcpy(result, dev_a, size, hipMemcpyDeviceToHost);
fprintf(stdout, "Result %s\n", "");
for (int i = 0; i < SIZE; i++) {
fprintf(stderr, " %d ", result[i]);
if ((i + 1) % 10 == 0) fprintf(stdout, "%s\n", "");
}
fprintf(stdout, "%s\n", "");
free(h_a), free(result);
hipFree(dev_a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPi
.globl _Z3addPi
.p2align 8
.type _Z3addPi,@function
_Z3addPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x801, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v3, -1, v1
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_add_nc_u32_e32 v0, 1, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0x7ff, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshrrev_b32_e32 v2, 21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v0, v2
v_and_b32_e32 v2, 0xfffff800, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x2
global_load_b32 v6, v[0:1], off
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add3_u32 v2, v4, v6, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPi, .Lfunc_end0-_Z3addPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <hip/hip_runtime.h>
#define THREADS 128
#define BLOCKS 16
#define SIZE 2048
__global__ void add(int *array) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx > SIZE) return;
int temp = 0;
int before = (idx + 1) % SIZE;
int after = idx - 1;
if (after < 0) after = SIZE - 1;
temp += array[idx];
temp += array[before];
temp += array[after];
__syncthreads(); // Barrera...
array[idx] = temp;
}
void init(int* h_v, int numb) {
for (int i = 0; i < SIZE; i++) {
h_v[i] = numb;
}
}
int main( void ) {
int *result, *h_a;
int *dev_a;
int size = SIZE * sizeof(int);
result = (int*) malloc( size );
h_a = (int*) malloc( size );
if (h_a == NULL || result == NULL) {
fprintf(stderr, "Error allocating memory... %s\n", strerror(errno));
exit(1);
}
memset(result, 0, size);
init(h_a, 3);
hipMalloc(&dev_a, size);
// se transfieren los datos a memoria de dispositivo...
hipMemcpy(dev_a, h_a, size, hipMemcpyHostToDevice);
add<<<BLOCKS, THREADS>>>(dev_a);
// se transfieren los datos del dispositivo a memoria.
hipMemcpy(result, dev_a, size, hipMemcpyDeviceToHost);
fprintf(stdout, "Result %s\n", "");
for (int i = 0; i < SIZE; i++) {
fprintf(stderr, " %d ", result[i]);
if ((i + 1) % 10 == 0) fprintf(stdout, "%s\n", "");
}
fprintf(stdout, "%s\n", "");
free(h_a), free(result);
hipFree(dev_a);
return 0;
} | .text
.file "suma_afin.hip"
.globl _Z18__device_stub__addPi # -- Begin function _Z18__device_stub__addPi
.p2align 4, 0x90
.type _Z18__device_stub__addPi,@function
_Z18__device_stub__addPi: # @_Z18__device_stub__addPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3addPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__addPi, .Lfunc_end0-_Z18__device_stub__addPi
.cfi_endproc
# -- End function
.globl _Z4initPii # -- Begin function _Z4initPii
.p2align 4, 0x90
.type _Z4initPii,@function
_Z4initPii: # @_Z4initPii
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %esi, (%rdi,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z4initPii, .Lfunc_end1-_Z4initPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq malloc
testq %rbx, %rbx
je .LBB2_11
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB2_11
# %bb.2:
xorl %r15d, %r15d
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl $3, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z4initPii.exit
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 8(%rsp), %rdi
movl $1, %ebp
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq stdout(%rip), %rdi
movl $.L.str.1, %esi
movl $.L.str.2, %edx
xorl %eax, %eax
callq fprintf
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %r12d, %r12d
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %r13d
movq stderr(%rip), %rdi
movl (%rbx,%r12,4), %edx
movl $.L.str.3, %esi
xorl %eax, %eax
callq fprintf
cmpl %r12d, %r13d
jne .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.2, %edx
xorl %eax, %eax
callq fprintf
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r12
incl %ebp
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_7
# %bb.10:
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.2, %edx
xorl %eax, %eax
callq fprintf
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPi,@object # @_Z3addPi
.section .rodata,"a",@progbits
.globl _Z3addPi
.p2align 3, 0x0
_Z3addPi:
.quad _Z18__device_stub__addPi
.size _Z3addPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating memory... %s\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Result %s\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.zero 1
.size .L.str.2, 1
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %d "
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s\n"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x800, PT ; /* 0x000008000200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R2.reuse, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f06270 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00b0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe40007ffe0ff */
/*00c0*/ LEA.HI R3, R3, R0, RZ, 0xb ; /* 0x0000000003037211 */
/* 0x000fe400078f58ff */
/*00d0*/ SEL R6, R4, 0x7ff, P0 ; /* 0x000007ff04067807 */
/* 0x000fc40000000000 */
/*00e0*/ LOP3.LUT R3, R3, 0xfffff800, RZ, 0xc0, !PT ; /* 0xfffff80003037812 */
/* 0x000fc600078ec0ff */
/*00f0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.IADD R4, R0, 0x1, -R3 ; /* 0x0000000100047824 */
/* 0x000fe400078e0a03 */
/*0110*/ IMAD.WIDE R2, R2, R5.reuse, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x080fe200078e0205 */
/*0120*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea6000c1e1900 */
/*0130*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0140*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000eaa000c1e1900 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ IADD3 R9, R6, R4, R9 ; /* 0x0000000406097210 */
/* 0x004fca0007ffe009 */
/*0180*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPi
.globl _Z3addPi
.p2align 8
.type _Z3addPi,@function
_Z3addPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x801, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v3, -1, v1
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_add_nc_u32_e32 v0, 1, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0x7ff, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshrrev_b32_e32 v2, 21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v0, v2
v_and_b32_e32 v2, 0xfffff800, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x2
global_load_b32 v6, v[0:1], off
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add3_u32 v2, v4, v6, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPi, .Lfunc_end0-_Z3addPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00002620_00000000-6_suma_afin.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPii
.type _Z4initPii, @function
_Z4initPii:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %rax
leaq 8192(%rdi), %rdx
.L4:
movl %esi, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z4initPii, .-_Z4initPii
.globl _Z22__device_stub__Z3addPiPi
.type _Z22__device_stub__Z3addPiPi, @function
_Z22__device_stub__Z3addPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z3addPiPi, .-_Z22__device_stub__Z3addPiPi
.globl _Z3addPi
.type _Z3addPi, @function
_Z3addPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3addPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPi, .-_Z3addPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error allocating memory... %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string ""
.LC2:
.string "Result %s\n"
.LC3:
.string " %d "
.LC4:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
testq %rax, %rax
je .L21
movq %rax, %r15
testq %rbp, %rbp
je .L21
movl $1024, %ecx
movl $0, %eax
movq %rbp, %rdi
rep stosq
movl $3, %esi
movq %r15, %rdi
call _Z4initPii
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L17:
movl $2, %ecx
movl $8192, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %ebx
leaq .LC3(%rip), %r12
leaq .LC1(%rip), %r14
leaq .LC4(%rip), %r13
jmp .L19
.L21:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3addPiPi
jmp .L17
.L18:
addq $1, %rbx
cmpq $2049, %rbx
je .L25
.L19:
movl -4(%rbp,%rbx,4), %ecx
movq %r12, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L18
movq %r14, %rcx
movq %r13, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L25:
leaq .LC1(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "suma_afin.hip"
.globl _Z18__device_stub__addPi # -- Begin function _Z18__device_stub__addPi
.p2align 4, 0x90
.type _Z18__device_stub__addPi,@function
_Z18__device_stub__addPi: # @_Z18__device_stub__addPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3addPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__addPi, .Lfunc_end0-_Z18__device_stub__addPi
.cfi_endproc
# -- End function
.globl _Z4initPii # -- Begin function _Z4initPii
.p2align 4, 0x90
.type _Z4initPii,@function
_Z4initPii: # @_Z4initPii
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %esi, (%rdi,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z4initPii, .Lfunc_end1-_Z4initPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq malloc
testq %rbx, %rbx
je .LBB2_11
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB2_11
# %bb.2:
xorl %r15d, %r15d
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl $3, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z4initPii.exit
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 8(%rsp), %rdi
movl $1, %ebp
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq stdout(%rip), %rdi
movl $.L.str.1, %esi
movl $.L.str.2, %edx
xorl %eax, %eax
callq fprintf
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %r12d, %r12d
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %r13d
movq stderr(%rip), %rdi
movl (%rbx,%r12,4), %edx
movl $.L.str.3, %esi
xorl %eax, %eax
callq fprintf
cmpl %r12d, %r13d
jne .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.2, %edx
xorl %eax, %eax
callq fprintf
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r12
incl %ebp
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_7
# %bb.10:
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.2, %edx
xorl %eax, %eax
callq fprintf
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPi,@object # @_Z3addPi
.section .rodata,"a",@progbits
.globl _Z3addPi
.p2align 3, 0x0
_Z3addPi:
.quad _Z18__device_stub__addPi
.size _Z3addPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating memory... %s\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Result %s\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.zero 1
.size .L.str.2, 1
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %d "
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s\n"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define SIZE 1024
__global__ void VectorAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if(i<n)
c[i] = a[i] + b[i];
}
int main()
{
printf("\n------------------------------\nSUMA VECTORIAL\n------------------------------\n");
// ALLOCATE AND INITIALIZE DATA ON CPU
int *a, *b, *c;
int *d_a, *d_b, *d_c;
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
// ALOCATE DATA ON GPU
cudaMalloc( &d_a, SIZE*sizeof(int));
cudaMalloc( &d_b, SIZE*sizeof(int));
cudaMalloc( &d_c, SIZE*sizeof(int));
for( int i=0;i<SIZE;++i)
{
a[i] = i;
b[i] = i;
c[i] = 0;
}
printf("\n Vector A\n \n");
for( int i=0;i<3;++i)
printf("a[%d] = %d\n", i, a[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("a[%d] = %d\n", i, a[i]);
printf("\n Vector B\n \n");
for( int i=0;i<3;++i)
printf("b[%d] = %d\n", i, b[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("b[%d] = %d\n", i, b[i]);
// TRANSFER DATA FROM CPU TO GPU
cudaMemcpy( d_a, a, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, SIZE*sizeof(int), cudaMemcpyHostToDevice );
// RUN KERNEL
VectorAdd<<< 1, SIZE >>>(d_a, d_b, d_c, SIZE);
// TRANSFER DATA FROM GPU TO CPU
cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
printf("\n A[i] + B[i] = C[i] \n");
printf("\n Vector C\n \n");
for( int i=0;i<3;++i)
printf("c[%d] = %d\n", i, c[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("c[%d] = %d\n", i, c[i]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z9VectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define SIZE 1024
__global__ void VectorAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if(i<n)
c[i] = a[i] + b[i];
}
int main()
{
printf("\n------------------------------\nSUMA VECTORIAL\n------------------------------\n");
// ALLOCATE AND INITIALIZE DATA ON CPU
int *a, *b, *c;
int *d_a, *d_b, *d_c;
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
// ALOCATE DATA ON GPU
cudaMalloc( &d_a, SIZE*sizeof(int));
cudaMalloc( &d_b, SIZE*sizeof(int));
cudaMalloc( &d_c, SIZE*sizeof(int));
for( int i=0;i<SIZE;++i)
{
a[i] = i;
b[i] = i;
c[i] = 0;
}
printf("\n Vector A\n \n");
for( int i=0;i<3;++i)
printf("a[%d] = %d\n", i, a[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("a[%d] = %d\n", i, a[i]);
printf("\n Vector B\n \n");
for( int i=0;i<3;++i)
printf("b[%d] = %d\n", i, b[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("b[%d] = %d\n", i, b[i]);
// TRANSFER DATA FROM CPU TO GPU
cudaMemcpy( d_a, a, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, SIZE*sizeof(int), cudaMemcpyHostToDevice );
// RUN KERNEL
VectorAdd<<< 1, SIZE >>>(d_a, d_b, d_c, SIZE);
// TRANSFER DATA FROM GPU TO CPU
cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
printf("\n A[i] + B[i] = C[i] \n");
printf("\n Vector C\n \n");
for( int i=0;i<3;++i)
printf("c[%d] = %d\n", i, c[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("c[%d] = %d\n", i, c[i]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0018d03c_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.globl _Z9VectorAddPiS_S_i
.type _Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n------------------------------\nSUMA VECTORIAL\n------------------------------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n Vector A\n \n"
.LC2:
.string "a[%d] = %d\n"
.LC3:
.string ".\n.\n.\n"
.LC4:
.string "\n Vector B\n \n"
.LC5:
.string "b[%d] = %d\n"
.LC6:
.string "\n A[i] + B[i] = C[i] \n"
.LC7:
.string "\n Vector C\n \n"
.LC8:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC2(%rip), %r14
.L13:
movl (%r12,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $3, %r13
jne .L13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1021, %r13d
leaq .LC2(%rip), %r14
.L14:
movl (%r12,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $1024, %r13
jne .L14
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC5(%rip), %r14
.L15:
movl 0(%rbp,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $3, %r13
jne .L15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1021, %r13d
leaq .LC5(%rip), %r14
.L16:
movl 0(%rbp,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $1024, %r13
jne .L16
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC8(%rip), %r14
.L18:
movl (%rbx,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $3, %r13
jne .L18
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1021, %r13d
leaq .LC8(%rip), %r14
.L19:
movl (%rbx,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $1024, %r13
jne .L19
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
jmp .L17
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9VectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define SIZE 1024
__global__ void VectorAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if(i<n)
c[i] = a[i] + b[i];
}
int main()
{
printf("\n------------------------------\nSUMA VECTORIAL\n------------------------------\n");
// ALLOCATE AND INITIALIZE DATA ON CPU
int *a, *b, *c;
int *d_a, *d_b, *d_c;
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
// ALOCATE DATA ON GPU
cudaMalloc( &d_a, SIZE*sizeof(int));
cudaMalloc( &d_b, SIZE*sizeof(int));
cudaMalloc( &d_c, SIZE*sizeof(int));
for( int i=0;i<SIZE;++i)
{
a[i] = i;
b[i] = i;
c[i] = 0;
}
printf("\n Vector A\n \n");
for( int i=0;i<3;++i)
printf("a[%d] = %d\n", i, a[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("a[%d] = %d\n", i, a[i]);
printf("\n Vector B\n \n");
for( int i=0;i<3;++i)
printf("b[%d] = %d\n", i, b[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("b[%d] = %d\n", i, b[i]);
// TRANSFER DATA FROM CPU TO GPU
cudaMemcpy( d_a, a, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_b, b, SIZE*sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( d_c, c, SIZE*sizeof(int), cudaMemcpyHostToDevice );
// RUN KERNEL
VectorAdd<<< 1, SIZE >>>(d_a, d_b, d_c, SIZE);
// TRANSFER DATA FROM GPU TO CPU
cudaMemcpy( c, d_c, SIZE*sizeof(int), cudaMemcpyDeviceToHost );
printf("\n A[i] + B[i] = C[i] \n");
printf("\n Vector C\n \n");
for( int i=0;i<3;++i)
printf("c[%d] = %d\n", i, c[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("c[%d] = %d\n", i, c[i]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 1024
__global__ void VectorAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if(i<n)
c[i] = a[i] + b[i];
}
int main()
{
printf("\n------------------------------\nSUMA VECTORIAL\n------------------------------\n");
// ALLOCATE AND INITIALIZE DATA ON CPU
int *a, *b, *c;
int *d_a, *d_b, *d_c;
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
// ALOCATE DATA ON GPU
hipMalloc( &d_a, SIZE*sizeof(int));
hipMalloc( &d_b, SIZE*sizeof(int));
hipMalloc( &d_c, SIZE*sizeof(int));
for( int i=0;i<SIZE;++i)
{
a[i] = i;
b[i] = i;
c[i] = 0;
}
printf("\n Vector A\n \n");
for( int i=0;i<3;++i)
printf("a[%d] = %d\n", i, a[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("a[%d] = %d\n", i, a[i]);
printf("\n Vector B\n \n");
for( int i=0;i<3;++i)
printf("b[%d] = %d\n", i, b[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("b[%d] = %d\n", i, b[i]);
// TRANSFER DATA FROM CPU TO GPU
hipMemcpy( d_a, a, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_b, b, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, SIZE*sizeof(int), hipMemcpyHostToDevice );
// RUN KERNEL
VectorAdd<<< 1, SIZE >>>(d_a, d_b, d_c, SIZE);
// TRANSFER DATA FROM GPU TO CPU
hipMemcpy( c, d_c, SIZE*sizeof(int), hipMemcpyDeviceToHost );
printf("\n A[i] + B[i] = C[i] \n");
printf("\n Vector C\n \n");
for( int i=0;i<3;++i)
printf("c[%d] = %d\n", i, c[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("c[%d] = %d\n", i, c[i]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 1024
__global__ void VectorAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if(i<n)
c[i] = a[i] + b[i];
}
int main()
{
printf("\n------------------------------\nSUMA VECTORIAL\n------------------------------\n");
// ALLOCATE AND INITIALIZE DATA ON CPU
int *a, *b, *c;
int *d_a, *d_b, *d_c;
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
// ALOCATE DATA ON GPU
hipMalloc( &d_a, SIZE*sizeof(int));
hipMalloc( &d_b, SIZE*sizeof(int));
hipMalloc( &d_c, SIZE*sizeof(int));
for( int i=0;i<SIZE;++i)
{
a[i] = i;
b[i] = i;
c[i] = 0;
}
printf("\n Vector A\n \n");
for( int i=0;i<3;++i)
printf("a[%d] = %d\n", i, a[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("a[%d] = %d\n", i, a[i]);
printf("\n Vector B\n \n");
for( int i=0;i<3;++i)
printf("b[%d] = %d\n", i, b[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("b[%d] = %d\n", i, b[i]);
// TRANSFER DATA FROM CPU TO GPU
hipMemcpy( d_a, a, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_b, b, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, SIZE*sizeof(int), hipMemcpyHostToDevice );
// RUN KERNEL
VectorAdd<<< 1, SIZE >>>(d_a, d_b, d_c, SIZE);
// TRANSFER DATA FROM GPU TO CPU
hipMemcpy( c, d_c, SIZE*sizeof(int), hipMemcpyDeviceToHost );
printf("\n A[i] + B[i] = C[i] \n");
printf("\n Vector C\n \n");
for( int i=0;i<3;++i)
printf("c[%d] = %d\n", i, c[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("c[%d] = %d\n", i, c[i]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPiS_S_i
.globl _Z9VectorAddPiS_S_i
.p2align 8
.type _Z9VectorAddPiS_S_i,@function
_Z9VectorAddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPiS_S_i, .Lfunc_end0-_Z9VectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 1024
__global__ void VectorAdd(int *a, int *b, int *c, int n)
{
int i = threadIdx.x;
if(i<n)
c[i] = a[i] + b[i];
}
int main()
{
printf("\n------------------------------\nSUMA VECTORIAL\n------------------------------\n");
// ALLOCATE AND INITIALIZE DATA ON CPU
int *a, *b, *c;
int *d_a, *d_b, *d_c;
a = (int *)malloc(SIZE*sizeof(int));
b = (int *)malloc(SIZE*sizeof(int));
c = (int *)malloc(SIZE*sizeof(int));
// ALOCATE DATA ON GPU
hipMalloc( &d_a, SIZE*sizeof(int));
hipMalloc( &d_b, SIZE*sizeof(int));
hipMalloc( &d_c, SIZE*sizeof(int));
for( int i=0;i<SIZE;++i)
{
a[i] = i;
b[i] = i;
c[i] = 0;
}
printf("\n Vector A\n \n");
for( int i=0;i<3;++i)
printf("a[%d] = %d\n", i, a[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("a[%d] = %d\n", i, a[i]);
printf("\n Vector B\n \n");
for( int i=0;i<3;++i)
printf("b[%d] = %d\n", i, b[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("b[%d] = %d\n", i, b[i]);
// TRANSFER DATA FROM CPU TO GPU
hipMemcpy( d_a, a, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_b, b, SIZE*sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( d_c, c, SIZE*sizeof(int), hipMemcpyHostToDevice );
// RUN KERNEL
VectorAdd<<< 1, SIZE >>>(d_a, d_b, d_c, SIZE);
// TRANSFER DATA FROM GPU TO CPU
hipMemcpy( c, d_c, SIZE*sizeof(int), hipMemcpyDeviceToHost );
printf("\n A[i] + B[i] = C[i] \n");
printf("\n Vector C\n \n");
for( int i=0;i<3;++i)
printf("c[%d] = %d\n", i, c[i]);
printf(".\n.\n.\n");
for( int i=SIZE-3;i<SIZE;++i)
printf("c[%d] = %d\n", i, c[i]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "VectorAdd.hip"
.globl _Z24__device_stub__VectorAddPiS_S_i # -- Begin function _Z24__device_stub__VectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPiS_S_i,@function
_Z24__device_stub__VectorAddPiS_S_i: # @_Z24__device_stub__VectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%rbx,%r12,4)
movl %r12d, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_3
# %bb.4:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1021, %r12d # imm = 0x3FD
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_5
# %bb.6:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_7
# %bb.8:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1021, %r12d # imm = 0x3FD
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_9
# %bb.10:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.8, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_13
# %bb.14:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1021, %r12d # imm = 0x3FD
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.8, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_15
# %bb.16:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPiS_S_i,@object # @_Z9VectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPiS_S_i
.p2align 3, 0x0
_Z9VectorAddPiS_S_i:
.quad _Z24__device_stub__VectorAddPiS_S_i
.size _Z9VectorAddPiS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "a[%d] = %d\n"
.size .L.str.2, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "b[%d] = %d\n"
.size .L.str.5, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "c[%d] = %d\n"
.size .L.str.8, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9VectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n------------------------------\nSUMA VECTORIAL\n------------------------------"
.size .Lstr, 78
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n Vector A\n "
.size .Lstr.1, 13
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n Vector B\n "
.size .Lstr.3, 13
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\n A[i] + B[i] = C[i] "
.size .Lstr.5, 22
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\n Vector C\n "
.size .Lstr.6, 13
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz ".\n.\n."
.size .Lstr.7, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9VectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPiS_S_i
.globl _Z9VectorAddPiS_S_i
.p2align 8
.type _Z9VectorAddPiS_S_i,@function
_Z9VectorAddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPiS_S_i, .Lfunc_end0-_Z9VectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018d03c_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.globl _Z9VectorAddPiS_S_i
.type _Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n------------------------------\nSUMA VECTORIAL\n------------------------------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n Vector A\n \n"
.LC2:
.string "a[%d] = %d\n"
.LC3:
.string ".\n.\n.\n"
.LC4:
.string "\n Vector B\n \n"
.LC5:
.string "b[%d] = %d\n"
.LC6:
.string "\n A[i] + B[i] = C[i] \n"
.LC7:
.string "\n Vector C\n \n"
.LC8:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC2(%rip), %r14
.L13:
movl (%r12,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $3, %r13
jne .L13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1021, %r13d
leaq .LC2(%rip), %r14
.L14:
movl (%r12,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $1024, %r13
jne .L14
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC5(%rip), %r14
.L15:
movl 0(%rbp,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $3, %r13
jne .L15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1021, %r13d
leaq .LC5(%rip), %r14
.L16:
movl 0(%rbp,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $1024, %r13
jne .L16
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC8(%rip), %r14
.L18:
movl (%rbx,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $3, %r13
jne .L18
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1021, %r13d
leaq .LC8(%rip), %r14
.L19:
movl (%rbx,%r13,4), %ecx
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
cmpq $1024, %r13
jne .L19
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
jmp .L17
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9VectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorAdd.hip"
.globl _Z24__device_stub__VectorAddPiS_S_i # -- Begin function _Z24__device_stub__VectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPiS_S_i,@function
_Z24__device_stub__VectorAddPiS_S_i: # @_Z24__device_stub__VectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%rbx,%r12,4)
movl %r12d, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_3
# %bb.4:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1021, %r12d # imm = 0x3FD
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_5
# %bb.6:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_7
# %bb.8:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1021, %r12d # imm = 0x3FD
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %edx
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_9
# %bb.10:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9VectorAddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.8, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_13
# %bb.14:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1021, %r12d # imm = 0x3FD
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.8, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_15
# %bb.16:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPiS_S_i,@object # @_Z9VectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPiS_S_i
.p2align 3, 0x0
_Z9VectorAddPiS_S_i:
.quad _Z24__device_stub__VectorAddPiS_S_i
.size _Z9VectorAddPiS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "a[%d] = %d\n"
.size .L.str.2, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "b[%d] = %d\n"
.size .L.str.5, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "c[%d] = %d\n"
.size .L.str.8, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9VectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n------------------------------\nSUMA VECTORIAL\n------------------------------"
.size .Lstr, 78
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n Vector A\n "
.size .Lstr.1, 13
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n Vector B\n "
.size .Lstr.3, 13
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\n A[i] + B[i] = C[i] "
.size .Lstr.5, 22
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\n Vector C\n "
.size .Lstr.6, 13
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz ".\n.\n."
.size .Lstr.7, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<string.h>
#include<math.h>
//Cuda checks
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(cudaError_t ret, const char *file, int line){
if(ret != cudaSuccess) {
fprintf(stderr, "CudaError: %s %s %d\n", cudaGetErrorString(ret), file, line);
exit(1);
}
}
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
// Kernal Multiply Function
__global__ void matrix_multiply_kernel(unsigned char *temp, unsigned char *matrix, float *kernal, int order, int middle, int windowSizeX, int windowSizeY){
//Find place in the execution
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
//If out of bounds, do nothing
if(y >= windowSizeY || x >= windowSizeX){
return;
}
//Else do function
for(int y2 = 0; y2 < order; y2++){
for(int x2 = 0; x2 < order; x2++){
int tempX = x - middle + x2, tempY = y - middle + y2;
if(tempX < 0){
tempX = 0;
}else if(tempX >= windowSizeX){
tempX = windowSizeX - 1;
}
if(tempY < 0){
tempY = 0;
}else if(tempY >= windowSizeY){
tempY = windowSizeY - 1;
}
sum += temp[(windowSizeX * tempY) + tempX] * kernal[(order * x2) + y2];
}
}
//Clamp the sum value
if(sum < 0){
sum = 0;
}else if(sum > 255){
sum = 255;
}
//Add sum value to matrix
matrix[(windowSizeX * y) + x] = (unsigned char) sum;
}
///////////////////
//Multiply Kernal//
///////////////////
void multiplyKernal(unsigned char* matrix, float* kernal, int order, int windowSizeX, int windowSizeY){
//Find the middle of the kernal
int middle = ceil(order/2);
//Declare all the Kernal data
unsigned char *temp, *matrix_d;
float *kernal_d;
int kernal_size = order*order*sizeof(float);
int matrix_size = windowSizeX * windowSizeY * sizeof(char);
//Initialize Kernal Data
cuda_check(cudaMalloc(&temp, matrix_size));
cuda_check(cudaMalloc(&matrix_d, matrix_size));
cuda_check(cudaMalloc(&kernal_d, kernal_size));
// Copy Data to Kernal
cuda_check(cudaMemcpy(temp, matrix, matrix_size, cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(matrix_d, matrix, matrix_size, cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(kernal_d, kernal, kernal_size, cudaMemcpyHostToDevice));
//Kernal Functions
dim3 block_dim(32, 32);
dim3 grid_dim(DIV_ROUND_UP(windowSizeX, block_dim.x), DIV_ROUND_UP(windowSizeY, block_dim.y));
matrix_multiply_kernel<<<grid_dim, block_dim>>>(temp, matrix_d, kernal_d, order, middle, windowSizeX, windowSizeY);
cuda_check(cudaPeekAtLastError());
cuda_check(cudaDeviceSynchronize());
//Copy back to Host
cuda_check(cudaMemcpy(matrix, matrix_d, matrix_size, cudaMemcpyDeviceToHost));
//Free data
cuda_check(cudaFree(temp));
cuda_check(cudaFree(matrix_d));
cuda_check(cudaFree(kernal_d));
}
/////////////////
//Main Function//
/////////////////
int main(int argc, char **argv)
{
char firstLine[10];
int windowSizeX = 0, windowSizeY = 0, temp, order;
float sigma;
//Read in inputs, check if they are correct!
if(argc != 4){
fprintf(stderr, "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n");
exit(1);
}
FILE *fp;
//If file cannout open
if((fp = fopen(argv[1], "rb")) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
// if File is incorrect
if(fgets(firstLine, 4, fp) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
//if info is incorrect
if(strcmp(firstLine, "P5\n")){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &windowSizeX) || !fscanf(fp,"%d", &windowSizeY)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(windowSizeX == 0 && windowSizeY == 0){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &temp)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(temp != 255){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
getc(fp);
//Create matrix
unsigned char* matrix = (unsigned char*)malloc(sizeof(unsigned char) * windowSizeX * windowSizeY);
//Read in Matrix
if(fread(matrix, sizeof(unsigned char), windowSizeX*windowSizeY,fp) != (unsigned)(windowSizeX*windowSizeY)){
fprintf(stderr, "Error: invalid PGM pixels\n");
exit(1);
}
sigma = atof(argv[3]);
if(sigma == 0){
fprintf(stderr, "Error: invalid sigma value\n");
exit(1);
}
//Create the order, if order is even, add 1
order = ceil(sigma * 6);
if(order%2 == 0){
order++;
}
if(order > windowSizeX || order > windowSizeY){
fprintf(stderr, "Error: sigma value too big for image size\n");
exit(1);
}
int middle = ceil(order/2);
//Intialize the kernal
float sum = 0;
float kernal [order*order];
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
int x2 = x - middle, y2 = y - middle;
kernal[(order * y) + x] = (1/(2*M_PI*(pow(sigma,2)))) * (pow(M_E, -((pow(x2,2) + pow(y2,2))/(2*pow(sigma,2)))));
sum += kernal[(order * y) + x];
}
}
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
kernal[(order * y) + x] = kernal[(order * y) + x] / sum;
}
}
//Function Time
struct timespec before, after;
clock_gettime(CLOCK_MONOTONIC, &before);
multiplyKernal(matrix, kernal, order, windowSizeX, windowSizeY);
clock_gettime(CLOCK_MONOTONIC, &after);
//Function End
unsigned long elapsed_ns = (after.tv_sec - before.tv_sec)*(1E9) + after.tv_nsec - before.tv_nsec;
double seconds = elapsed_ns / (1E9);
printf("Running time: %f secs\n", seconds);
char name[255];
sprintf(name, "%s", argv[2]);
//Print back to output file
FILE *fd;
fd = fopen(name, "w+");
fprintf(fd, "P5\n");
fprintf(fd, "%d %d\n", windowSizeX, windowSizeY);
fprintf(fd, "255\n");
for(int y = 0; y < windowSizeY; y++) {
for(int x = 0; x < windowSizeX; x++) {
fprintf(fd, "%c", matrix[(windowSizeX * y) + x]);
}
}
fclose(fp);
fclose(fd);
free(matrix);
return 0;
} | code for sm_80
Function : _Z22matrix_multiply_kernelPhS_Pfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R19, SR_CTAID.X ; /* 0x0000000000137919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R19, R19, c[0x0][0x0], R2 ; /* 0x0000000013137a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x180], P0 ; /* 0x0000600013007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff147624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x970 ; /* 0x0000088000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R20.reuse, -0x1, RZ ; /* 0xffffffff14027810 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R21, R20.reuse, 0x4, RZ ; /* 0x0000000414157824 */
/* 0x040fe200078e00ff */
/*0110*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x000fe200078ec0ff */
/*0120*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0130*/ IADD3 R25, R19.reuse, 0x3, RZ ; /* 0x0000000313197810 */
/* 0x040fe20007ffe0ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0160*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R22, R19, -c[0x0][0x17c], RZ ; /* 0x80005f0013167a10 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R23, R0, -c[0x0][0x17c], RZ ; /* 0x80005f0000177a10 */
/* 0x000fe20007ffe0ff */
/*01a0*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe2000fffe13f */
/*01b0*/ IADD3 R25, R25, -c[0x0][0x17c], RZ ; /* 0x80005f0019197a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ UIADD3 UR5, -UR5, UR7, URZ ; /* 0x0000000705057290 */
/* 0x000fe2000fffe13f */
/*01d0*/ IADD3 R26, R20, -c[0x0][0x178], RZ ; /* 0x80005e00141a7a10 */
/* 0x000fc40007ffe0ff */
/*01e0*/ IMAD.IADD R2, R23, 0x1, R24 ; /* 0x0000000117027824 */
/* 0x000fe200078e0218 */
/*01f0*/ ISETP.NE.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f25270 */
/*0200*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*0210*/ ISETP.GE.AND P3, PT, R2.reuse, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x040fe40003f66270 */
/*0220*/ ISETP.GE.AND P2, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe40003f46270 */
/*0230*/ SEL R27, R2, UR5, !P3 ; /* 0x00000005021b7c07 */
/* 0x000fc8000d800000 */
/*0240*/ SEL R27, R27, RZ, P2 ; /* 0x000000ff1b1b7207 */
/* 0x000fe20001000000 */
/*0250*/ @!P0 BRA 0x650 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*0260*/ IADD3 R2, R24, c[0x0][0x178], RZ ; /* 0x00005e0018027a10 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.MOV.U32 R18, RZ, RZ, R25 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0019 */
/*02b0*/ IMAD.WIDE R4, R24, R5, c[0x0][0x170] ; /* 0x00005c0018047625 */
/* 0x000fc800078e0205 */
/*02c0*/ IADD3 R6, R18.reuse, -0x3, RZ ; /* 0xfffffffd12067810 */
/* 0x040fe40007ffe0ff */
/*02d0*/ IADD3 R7, R18, -0x2, RZ ; /* 0xfffffffe12077810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P5, PT, R6.reuse, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x040fe40003fa6270 */
/*02f0*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f66270 */
/*0300*/ IADD3 R8, R18, -0x1, RZ ; /* 0xffffffff12087810 */
/* 0x000fc40007ffe0ff */
/*0310*/ ISETP.GE.AND P4, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x040fe40003f86270 */
/*0320*/ SEL R6, R6, UR4, !P5 ; /* 0x0000000406067c07 */
/* 0x000fe4000e800000 */
/*0330*/ ISETP.GE.AND P5, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe40003fa6270 */
/*0340*/ ISETP.GE.AND P6, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003fc6270 */
/*0350*/ SEL R7, R7, UR4, !P4 ; /* 0x0000000407077c07 */
/* 0x000fe4000e000000 */
/*0360*/ SEL R6, R6, RZ, P3 ; /* 0x000000ff06067207 */
/* 0x000fc40001800000 */
/*0370*/ ISETP.GE.AND P2, PT, R18, c[0x0][0x180], PT ; /* 0x0000600012007a0c */
/* 0x000fe40003f46270 */
/*0380*/ ISETP.GE.AND P3, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f66270 */
/*0390*/ SEL R9, R8, UR4, !P6 ; /* 0x0000000408097c07 */
/* 0x000fe2000f000000 */
/*03a0*/ IMAD R8, R27, c[0x0][0x180], R6 ; /* 0x000060001b087a24 */
/* 0x000fe200078e0206 */
/*03b0*/ SEL R10, R7, RZ, P5 ; /* 0x000000ff070a7207 */
/* 0x000fe40002800000 */
/*03c0*/ ISETP.GE.AND P4, PT, R18.reuse, RZ, PT ; /* 0x000000ff1200720c */
/* 0x040fe40003f86270 */
/*03d0*/ SEL R11, R18, UR4, !P2 ; /* 0x00000004120b7c07 */
/* 0x000fe2000d000000 */
/*03e0*/ IMAD R7, R27, c[0x0][0x180], R10 ; /* 0x000060001b077a24 */
/* 0x000fe200078e020a */
/*03f0*/ SEL R6, R9, RZ, P3 ; /* 0x000000ff09067207 */
/* 0x000fc40001800000 */
/*0400*/ IADD3 R12, P2, R8.reuse, c[0x0][0x160], RZ ; /* 0x00005800080c7a10 */
/* 0x040fe40007f5e0ff */
/*0410*/ SEL R10, R11, RZ, P4 ; /* 0x000000ff0b0a7207 */
/* 0x000fe20002000000 */
/*0420*/ IMAD R9, R27, c[0x0][0x180], R6 ; /* 0x000060001b097a24 */
/* 0x000fe200078e0206 */
/*0430*/ IADD3 R6, P3, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fe40007f7e0ff */
/*0440*/ LEA.HI.X.SX32 R13, R8, c[0x0][0x164], 0x1, P2 ; /* 0x00005900080d7a11 */
/* 0x000fe200010f0eff */
/*0450*/ IMAD R11, R27, c[0x0][0x180], R10 ; /* 0x000060001b0b7a24 */
/* 0x000fe200078e020a */
/*0460*/ IADD3 R8, P2, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe40007f5e0ff */
/*0470*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P3 ; /* 0x0000590007077a11 */
/* 0x000fe200018f0eff */
/*0480*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x0000a2000c1e1100 */
/*0490*/ IADD3 R10, P3, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fc40007f7e0ff */
/*04a0*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P2 ; /* 0x0000590009097a11 */
/* 0x000fe200010f0eff */
/*04b0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x0002e2000c1e1100 */
/*04c0*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P3 ; /* 0x000059000b0b7a11 */
/* 0x000fe200018f0eff */
/*04d0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff117624 */
/* 0x000fe400078e00ff */
/*04e0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000964000c1e1100 */
/*04f0*/ IMAD.WIDE R14, R17.reuse, 0x4, R2 ; /* 0x00000004110e7825 */
/* 0x040fe400078e0202 */
/*0500*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000368000c1e1100 */
/*0510*/ LDG.E R13, [R4.64] ; /* 0x00000008040d7981 */
/* 0x001162000c1e1900 */
/*0520*/ IMAD.WIDE R16, R17, 0x4, R14 ; /* 0x0000000411107825 */
/* 0x000fc600078e020e */
/*0530*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x010968000c1e1900 */
/*0540*/ LDG.E R7, [R14.64] ; /* 0x000000080e077981 */
/* 0x002f68000c1e1900 */
/*0550*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f62000c1e1900 */
/*0560*/ IADD3 R29, R29, 0x4, RZ ; /* 0x000000041d1d7810 */
/* 0x000fca0007ffe0ff */
/*0570*/ IMAD.IADD R11, R26, 0x1, R29 ; /* 0x000000011a0b7824 */
/* 0x000fca00078e021d */
/*0580*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f45270 */
/*0590*/ IMAD.WIDE R4, R21, 0x4, R4 ; /* 0x0000000415047825 */
/* 0x001fe200078e0204 */
/*05a0*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fc60007ffe0ff */
/*05b0*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x010fe200078e0202 */
/*05c0*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x004e300000101000 */
/*05d0*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*05e0*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x020ea20000101000 */
/*05f0*/ FFMA R28, R12, R13, R28 ; /* 0x0000000d0c1c7223 */
/* 0x001fce000000001c */
/*0600*/ I2F.U16 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000101000 */
/*0610*/ FFMA R28, R6, R9, R28 ; /* 0x00000009061c7223 */
/* 0x002fc8000000001c */
/*0620*/ FFMA R7, R8, R7, R28 ; /* 0x0000000708077223 */
/* 0x004fc8000000001c */
/*0630*/ FFMA R28, R10, R16, R7 ; /* 0x000000100a1c7223 */
/* 0x001fe20000000007 */
/*0640*/ @P2 BRA 0x2c0 ; /* 0xfffffc7000002947 */
/* 0x000fea000383ffff */
/*0650*/ @!P1 BRA 0x940 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.IADD R8, R22, 0x1, R29 ; /* 0x0000000116087824 */
/* 0x000fca00078e021d */
/*0670*/ ISETP.GE.AND P2, PT, R8.reuse, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x040fe40003f46270 */
/*0680*/ ISETP.GE.AND P1, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f26270 */
/*0690*/ SEL R2, R8, UR4, !P2 ; /* 0x0000000408027c07 */
/* 0x000fc8000d000000 */
/*06a0*/ SEL R2, R2, RZ, P1 ; /* 0x000000ff02027207 */
/* 0x000fca0000800000 */
/*06b0*/ IMAD R2, R27, c[0x0][0x180], R2 ; /* 0x000060001b027a24 */
/* 0x000fca00078e0202 */
/*06c0*/ IADD3 R6, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fc80007f3e0ff */
/*06d0*/ LEA.HI.X.SX32 R7, R2, c[0x0][0x164], 0x1, P1 ; /* 0x0000590002077a11 */
/* 0x000fca00008f0eff */
/*06e0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ea2000c1e1100 */
/*06f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD R29, R29, c[0x0][0x178], R24 ; /* 0x00005e001d1d7a24 */
/* 0x000fc800078e0218 */
/*0710*/ IMAD.WIDE R2, R29, R4, c[0x0][0x170] ; /* 0x00005c001d027625 */
/* 0x000fcc00078e0204 */
/*0720*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ee2000c1e1900 */
/*0730*/ ISETP.NE.AND P1, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe20003f25270 */
/*0740*/ I2F.U16 R5, R6 ; /* 0x0000000600057306 */
/* 0x004ee40000101000 */
/*0750*/ FFMA R28, R5, R2, R28 ; /* 0x00000002051c7223 */
/* 0x008fd4000000001c */
/*0760*/ @!P1 BRA 0x940 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.NE.AND P1, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe40003f25270 */
/*0780*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fc80007ffe0ff */
/*0790*/ ISETP.GE.AND P3, PT, R2.reuse, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x040fe40003f66270 */
/*07a0*/ ISETP.GE.AND P2, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe40003f46270 */
/*07b0*/ SEL R2, R2, UR4, !P3 ; /* 0x0000000402027c07 */
/* 0x000fc6000d800000 */
/*07c0*/ @P1 IADD3 R3, R8, 0x2, RZ ; /* 0x0000000208031810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ SEL R2, R2, RZ, P2 ; /* 0x000000ff02027207 */
/* 0x000fe40001000000 */
/*07e0*/ @P1 ISETP.GE.AND P4, PT, R3.reuse, c[0x0][0x180], PT ; /* 0x0000600003001a0c */
/* 0x040fe40003f86270 */
/*07f0*/ @P1 ISETP.GE.AND P3, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300120c */
/* 0x040fe40003f66270 */
/*0800*/ @P1 SEL R3, R3, UR4, !P4 ; /* 0x0000000403031c07 */
/* 0x000fc8000e000000 */
/*0810*/ @P1 SEL R6, R3, RZ, P3 ; /* 0x000000ff03061207 */
/* 0x000fe20001800000 */
/*0820*/ IMAD R3, R27, c[0x0][0x180], R2 ; /* 0x000060001b037a24 */
/* 0x000fc800078e0202 */
/*0830*/ @P1 IMAD R27, R27, c[0x0][0x180], R6 ; /* 0x000060001b1b1a24 */
/* 0x000fe200078e0206 */
/*0840*/ IADD3 R2, P2, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f5e0ff */
/*0850*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P2 ; /* 0x0000590003037a11 */
/* 0x000fe400010f0eff */
/*0860*/ @P1 IADD3 R6, P2, R27, c[0x0][0x160], RZ ; /* 0x000058001b061a10 */
/* 0x000fc60007f5e0ff */
/*0870*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea2000c1e1100 */
/*0880*/ @P1 LEA.HI.X.SX32 R7, R27, c[0x0][0x164], 0x1, P2 ; /* 0x000059001b071a11 */
/* 0x000fe400010f0eff */
/*0890*/ IADD3 R9, R29, c[0x0][0x178], RZ ; /* 0x00005e001d097a10 */
/* 0x000fc60007ffe0ff */
/*08a0*/ @P1 LDG.E.U8 R6, [R6.64] ; /* 0x0000000806061981 */
/* 0x000ee2000c1e1100 */
/*08b0*/ @P1 IADD3 R5, R9.reuse, c[0x0][0x178], RZ ; /* 0x00005e0009051a10 */
/* 0x040fe20007ffe0ff */
/*08c0*/ IMAD.WIDE R8, R9, R4, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc800078e0204 */
/*08d0*/ @P1 IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005041625 */
/* 0x000fe400078e0204 */
/*08e0*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f28000c1e1900 */
/*08f0*/ @P1 LDG.E R4, [R4.64] ; /* 0x0000000804041981 */
/* 0x000f62000c1e1900 */
/*0900*/ I2F.U16 R11, R2 ; /* 0x00000002000b7306 */
/* 0x004f300000101000 */
/*0910*/ @P1 I2F.U16 R13, R6 ; /* 0x00000006000d1306 */
/* 0x008f620000101000 */
/*0920*/ FFMA R28, R11, R8, R28 ; /* 0x000000080b1c7223 */
/* 0x010fc8000000001c */
/*0930*/ @P1 FFMA R28, R13, R4, R28 ; /* 0x000000040d1c1223 */
/* 0x020fc6000000001c */
/*0940*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fc80007ffe0ff */
/*0950*/ ISETP.GE.AND P1, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fda0003f26270 */
/*0960*/ @!P1 BRA 0x1e0 ; /* 0xfffff87000009947 */
/* 0x000fea000383ffff */
/*0970*/ FSETP.GEU.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720b */
/* 0x000fe20003f0e000 */
/*0980*/ IMAD R0, R0, c[0x0][0x180], R19 ; /* 0x0000600000007a24 */
/* 0x000fe200078e0213 */
/*0990*/ FMNMX.NAN R28, R28, 255, PT ; /* 0x437f00001c1c7809 */
/* 0x000fc80003820000 */
/*09a0*/ FSEL R28, R28, RZ, P0 ; /* 0x000000ff1c1c7208 */
/* 0x000fe40000000000 */
/*09b0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x040fe40007f1e0ff */
/*09c0*/ F2I.U32.TRUNC.NTZ R5, R28 ; /* 0x0000001c00057305 */
/* 0x000e24000020f000 */
/*09d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f0eff */
/*09e0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101108 */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<string.h>
#include<math.h>
//Cuda checks
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(cudaError_t ret, const char *file, int line){
if(ret != cudaSuccess) {
fprintf(stderr, "CudaError: %s %s %d\n", cudaGetErrorString(ret), file, line);
exit(1);
}
}
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
// Kernal Multiply Function
__global__ void matrix_multiply_kernel(unsigned char *temp, unsigned char *matrix, float *kernal, int order, int middle, int windowSizeX, int windowSizeY){
//Find place in the execution
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
//If out of bounds, do nothing
if(y >= windowSizeY || x >= windowSizeX){
return;
}
//Else do function
for(int y2 = 0; y2 < order; y2++){
for(int x2 = 0; x2 < order; x2++){
int tempX = x - middle + x2, tempY = y - middle + y2;
if(tempX < 0){
tempX = 0;
}else if(tempX >= windowSizeX){
tempX = windowSizeX - 1;
}
if(tempY < 0){
tempY = 0;
}else if(tempY >= windowSizeY){
tempY = windowSizeY - 1;
}
sum += temp[(windowSizeX * tempY) + tempX] * kernal[(order * x2) + y2];
}
}
//Clamp the sum value
if(sum < 0){
sum = 0;
}else if(sum > 255){
sum = 255;
}
//Add sum value to matrix
matrix[(windowSizeX * y) + x] = (unsigned char) sum;
}
///////////////////
//Multiply Kernal//
///////////////////
void multiplyKernal(unsigned char* matrix, float* kernal, int order, int windowSizeX, int windowSizeY){
//Find the middle of the kernal
int middle = ceil(order/2);
//Declare all the Kernal data
unsigned char *temp, *matrix_d;
float *kernal_d;
int kernal_size = order*order*sizeof(float);
int matrix_size = windowSizeX * windowSizeY * sizeof(char);
//Initialize Kernal Data
cuda_check(cudaMalloc(&temp, matrix_size));
cuda_check(cudaMalloc(&matrix_d, matrix_size));
cuda_check(cudaMalloc(&kernal_d, kernal_size));
// Copy Data to Kernal
cuda_check(cudaMemcpy(temp, matrix, matrix_size, cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(matrix_d, matrix, matrix_size, cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(kernal_d, kernal, kernal_size, cudaMemcpyHostToDevice));
//Kernal Functions
dim3 block_dim(32, 32);
dim3 grid_dim(DIV_ROUND_UP(windowSizeX, block_dim.x), DIV_ROUND_UP(windowSizeY, block_dim.y));
matrix_multiply_kernel<<<grid_dim, block_dim>>>(temp, matrix_d, kernal_d, order, middle, windowSizeX, windowSizeY);
cuda_check(cudaPeekAtLastError());
cuda_check(cudaDeviceSynchronize());
//Copy back to Host
cuda_check(cudaMemcpy(matrix, matrix_d, matrix_size, cudaMemcpyDeviceToHost));
//Free data
cuda_check(cudaFree(temp));
cuda_check(cudaFree(matrix_d));
cuda_check(cudaFree(kernal_d));
}
/////////////////
//Main Function//
/////////////////
int main(int argc, char **argv)
{
char firstLine[10];
int windowSizeX = 0, windowSizeY = 0, temp, order;
float sigma;
//Read in inputs, check if they are correct!
if(argc != 4){
fprintf(stderr, "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n");
exit(1);
}
FILE *fp;
//If file cannout open
if((fp = fopen(argv[1], "rb")) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
// if File is incorrect
if(fgets(firstLine, 4, fp) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
//if info is incorrect
if(strcmp(firstLine, "P5\n")){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &windowSizeX) || !fscanf(fp,"%d", &windowSizeY)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(windowSizeX == 0 && windowSizeY == 0){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &temp)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(temp != 255){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
getc(fp);
//Create matrix
unsigned char* matrix = (unsigned char*)malloc(sizeof(unsigned char) * windowSizeX * windowSizeY);
//Read in Matrix
if(fread(matrix, sizeof(unsigned char), windowSizeX*windowSizeY,fp) != (unsigned)(windowSizeX*windowSizeY)){
fprintf(stderr, "Error: invalid PGM pixels\n");
exit(1);
}
sigma = atof(argv[3]);
if(sigma == 0){
fprintf(stderr, "Error: invalid sigma value\n");
exit(1);
}
//Create the order, if order is even, add 1
order = ceil(sigma * 6);
if(order%2 == 0){
order++;
}
if(order > windowSizeX || order > windowSizeY){
fprintf(stderr, "Error: sigma value too big for image size\n");
exit(1);
}
int middle = ceil(order/2);
//Intialize the kernal
float sum = 0;
float kernal [order*order];
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
int x2 = x - middle, y2 = y - middle;
kernal[(order * y) + x] = (1/(2*M_PI*(pow(sigma,2)))) * (pow(M_E, -((pow(x2,2) + pow(y2,2))/(2*pow(sigma,2)))));
sum += kernal[(order * y) + x];
}
}
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
kernal[(order * y) + x] = kernal[(order * y) + x] / sum;
}
}
//Function Time
struct timespec before, after;
clock_gettime(CLOCK_MONOTONIC, &before);
multiplyKernal(matrix, kernal, order, windowSizeX, windowSizeY);
clock_gettime(CLOCK_MONOTONIC, &after);
//Function End
unsigned long elapsed_ns = (after.tv_sec - before.tv_sec)*(1E9) + after.tv_nsec - before.tv_nsec;
double seconds = elapsed_ns / (1E9);
printf("Running time: %f secs\n", seconds);
char name[255];
sprintf(name, "%s", argv[2]);
//Print back to output file
FILE *fd;
fd = fopen(name, "w+");
fprintf(fd, "P5\n");
fprintf(fd, "%d %d\n", windowSizeX, windowSizeY);
fprintf(fd, "255\n");
for(int y = 0; y < windowSizeY; y++) {
for(int x = 0; x < windowSizeX; x++) {
fprintf(fd, "%c", matrix[(windowSizeX * y) + x]);
}
}
fclose(fp);
fclose(fd);
free(matrix);
return 0;
} | .file "tmpxft_000562ef_00000000-6_gaussian_blur_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
.type _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii, @function
_Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22matrix_multiply_kernelPhS_Pfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii, .-_Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
.globl _Z22matrix_multiply_kernelPhS_Pfiiii
.type _Z22matrix_multiply_kernelPhS_Pfiiii, @function
_Z22matrix_multiply_kernelPhS_Pfiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z22matrix_multiply_kernelPhS_Pfiiii, .-_Z22matrix_multiply_kernelPhS_Pfiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/seanjedi/ECS158Project4/master/gaussian_blur_cuda.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CudaError: %s %s %d\n"
.text
.globl _Z14multiplyKernalPhPfiii
.type _Z14multiplyKernalPhPfiii, @function
_Z14multiplyKernalPhPfiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edx, %ebp
imull %edx, %ebp
sall $2, %ebp
movl %ecx, %ebx
imull %r8d, %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movslq %ebp, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
leal 31(%r14), %eax
shrl $5, %eax
movl %eax, 60(%rsp)
leal 31(%r15), %eax
shrl $5, %eax
movl %eax, 64(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L18:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L34
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L35
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L37
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L38
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L39
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $68, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $69, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $70, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $72, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $73, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $74, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %r13d, %r8d
shrl $31, %r8d
addl %r13d, %r8d
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq %r15
.cfi_def_cfa_offset 160
movl %r14d, %r9d
sarl %r8d
movl %r13d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $80, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $81, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $84, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $86, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $87, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $88, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14multiplyKernalPhPfiii, .-_Z14multiplyKernalPhPfiii
.section .rodata.str1.8
.align 8
.LC3:
.string "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n"
.section .rodata.str1.1
.LC4:
.string "rb"
.LC5:
.string "Error: cannot open file %s\n"
.LC6:
.string "P5\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Error: invalid PGM information\n"
.section .rodata.str1.1
.LC8:
.string "%d"
.LC9:
.string "Error: invalid PGM pixels\n"
.LC10:
.string "Error: invalid sigma value\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Error: sigma value too big for image size\n"
.section .rodata.str1.1
.LC22:
.string "Running time: %f secs\n"
.LC23:
.string "%s"
.LC24:
.string "w+"
.LC25:
.string "%d %d\n"
.LC26:
.string "255\n"
.LC27:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $440, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, -456(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $0, -380(%rbp)
movl $0, -376(%rbp)
cmpl $4, %edi
jne .L85
movq -456(%rbp), %rax
movq 8(%rax), %rdi
leaq .LC4(%rip), %rsi
call fopen@PLT
movq %rax, -448(%rbp)
testq %rax, %rax
je .L86
leaq -330(%rbp), %rdi
movq -448(%rbp), %rcx
movl $4, %edx
movl $10, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L87
leaq -330(%rbp), %rdi
leaq .LC6(%rip), %rsi
call strcmp@PLT
movl %eax, -436(%rbp)
testl %eax, %eax
jne .L88
leaq -380(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq -448(%rbp), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L46
leaq -376(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L46
movl -380(%rbp), %eax
orl -376(%rbp), %eax
je .L89
leaq -372(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq -448(%rbp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L90
cmpl $255, -372(%rbp)
jne .L91
movq -448(%rbp), %r15
movq %r15, %rdi
call getc@PLT
movslq -380(%rbp), %rbx
movslq -376(%rbp), %rax
imulq %rax, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %r8
movq %rbx, %rcx
movl $1, %edx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rax, %rdx
movl -380(%rbp), %eax
imull -376(%rbp), %eax
cmpq %rdx, %rax
jne .L92
movq -456(%rbp), %rax
movq 24(%rax), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L52
je .L93
.L52:
movaps %xmm0, %xmm1
mulss .LC11(%rip), %xmm1
movaps %xmm1, %xmm4
movss .LC28(%rip), %xmm3
movaps %xmm1, %xmm2
andps %xmm3, %xmm2
movss .LC12(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L54
cvttss2sil %xmm1, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC14(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm1, %xmm3
orps %xmm3, %xmm4
.L54:
cvttss2sil %xmm4, %edi
movl %edi, %eax
andl $1, %eax
cmpl $1, %eax
adcl $0, %edi
movl %edi, -392(%rbp)
cmpl %edi, -380(%rbp)
jl .L56
cmpl %edi, -376(%rbp)
jl .L56
movl -392(%rbp), %esi
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
movl %esi, %edx
imull %esi, %edx
movslq %edx, %rdx
leaq 15(,%rdx,4), %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L58:
cmpq %rcx, %rsp
je .L59
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L58
.L85:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L60
orq $0, -8(%rsp,%rdx)
.L60:
movq %rsp, %rdx
movq %rdx, -464(%rbp)
movl -392(%rbp), %esi
testl %esi, %esi
jle .L61
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LC16(%rip), %xmm1
movsd .LC17(%rip), %xmm2
divsd %xmm1, %xmm2
movsd %xmm2, -408(%rbp)
addsd %xmm0, %xmm0
movsd %xmm0, -416(%rbp)
movl %eax, %r15d
negl %r15d
movl %r15d, -440(%rbp)
movslq %esi, %rdi
movq %rdi, -472(%rbp)
salq $2, %rdi
movq %rdi, -424(%rbp)
subl %eax, %esi
movl %esi, %r13d
movq %rdx, -432(%rbp)
movl $0x00000000, -388(%rbp)
.L62:
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, -400(%rbp)
movq -432(%rbp), %r12
movl -440(%rbp), %ebx
.L63:
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
mulsd %xmm1, %xmm1
addsd -400(%rbp), %xmm1
divsd -416(%rbp), %xmm1
xorpd .LC18(%rip), %xmm1
movsd .LC19(%rip), %xmm0
call pow@PLT
mulsd -408(%rbp), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12)
addss -388(%rbp), %xmm0
movss %xmm0, -388(%rbp)
addl $1, %ebx
addq $4, %r12
cmpl %r13d, %ebx
jne .L63
addl $1, %r15d
movq -424(%rbp), %rdi
addq %rdi, -432(%rbp)
cmpl %r13d, %r15d
jne .L62
movq -464(%rbp), %rax
movq -424(%rbp), %rdi
leaq (%rax,%rdi), %rdx
movq -472(%rbp), %rsi
negq %rsi
salq $2, %rsi
movl -436(%rbp), %ecx
.L65:
leaq (%rdx,%rsi), %rax
.L66:
movss (%rax), %xmm0
divss -388(%rbp), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L66
addl $1, %ecx
movq -424(%rbp), %rax
addq %rax, %rdx
cmpl %ecx, -392(%rbp)
jne .L65
.L61:
leaq -368(%rbp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl -376(%rbp), %r8d
movl -380(%rbp), %ecx
movl -392(%rbp), %edx
movq -464(%rbp), %rsi
movq %r14, %rdi
call _Z14multiplyKernalPhPfiii
leaq -352(%rbp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq -352(%rbp), %rax
subq -368(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC20(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -344(%rbp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -360(%rbp), %xmm1
subsd %xmm1, %xmm0
comisd .LC21(%rip), %xmm0
jnb .L67
cvttsd2siq %xmm0, %rax
.L68:
testq %rax, %rax
js .L69
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L70:
divsd .LC20(%rip), %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq -320(%rbp), %rbx
movq -456(%rbp), %rax
movq 16(%rax), %r8
leaq .LC23(%rip), %rcx
movl $255, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl -376(%rbp), %r8d
movl -380(%rbp), %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC26(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl -436(%rbp), %r12d
leaq .LC27(%rip), %r15
cmpl $0, -376(%rbp)
jg .L71
.L72:
movq -448(%rbp), %rdi
call fclose@PLT
movq %r13, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L67:
.cfi_restore_state
subsd .LC21(%rip), %xmm0
cvttsd2siq %xmm0, %rax
btcq $63, %rax
jmp .L68
.L69:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L70
.L73:
imull %r12d, %eax
addl %ebx, %eax
cltq
movzbl (%r14,%rax), %ecx
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl -380(%rbp), %eax
cmpl %ebx, %eax
jg .L73
.L74:
addl $1, %r12d
cmpl %r12d, -376(%rbp)
jle .L72
.L71:
movl -380(%rbp), %eax
movl -436(%rbp), %ebx
testl %eax, %eax
jg .L73
jmp .L74
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC29:
.string "_Z22matrix_multiply_kernelPhS_Pfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrix_multiply_kernelPhS_Pfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1086324736
.align 4
.LC12:
.long 1258291200
.align 4
.LC14:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC16:
.long 1413754136
.long 1075388923
.align 8
.LC17:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC18:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC19:
.long -1961601175
.long 1074118410
.align 8
.LC20:
.long 0
.long 1104006501
.align 8
.LC21:
.long 0
.long 1138753536
.section .rodata.cst4
.align 4
.LC28:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<string.h>
#include<math.h>
//Cuda checks
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(cudaError_t ret, const char *file, int line){
if(ret != cudaSuccess) {
fprintf(stderr, "CudaError: %s %s %d\n", cudaGetErrorString(ret), file, line);
exit(1);
}
}
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
// Kernal Multiply Function
__global__ void matrix_multiply_kernel(unsigned char *temp, unsigned char *matrix, float *kernal, int order, int middle, int windowSizeX, int windowSizeY){
//Find place in the execution
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
//If out of bounds, do nothing
if(y >= windowSizeY || x >= windowSizeX){
return;
}
//Else do function
for(int y2 = 0; y2 < order; y2++){
for(int x2 = 0; x2 < order; x2++){
int tempX = x - middle + x2, tempY = y - middle + y2;
if(tempX < 0){
tempX = 0;
}else if(tempX >= windowSizeX){
tempX = windowSizeX - 1;
}
if(tempY < 0){
tempY = 0;
}else if(tempY >= windowSizeY){
tempY = windowSizeY - 1;
}
sum += temp[(windowSizeX * tempY) + tempX] * kernal[(order * x2) + y2];
}
}
//Clamp the sum value
if(sum < 0){
sum = 0;
}else if(sum > 255){
sum = 255;
}
//Add sum value to matrix
matrix[(windowSizeX * y) + x] = (unsigned char) sum;
}
///////////////////
//Multiply Kernal//
///////////////////
void multiplyKernal(unsigned char* matrix, float* kernal, int order, int windowSizeX, int windowSizeY){
//Find the middle of the kernal
int middle = ceil(order/2);
//Declare all the Kernal data
unsigned char *temp, *matrix_d;
float *kernal_d;
int kernal_size = order*order*sizeof(float);
int matrix_size = windowSizeX * windowSizeY * sizeof(char);
//Initialize Kernal Data
cuda_check(cudaMalloc(&temp, matrix_size));
cuda_check(cudaMalloc(&matrix_d, matrix_size));
cuda_check(cudaMalloc(&kernal_d, kernal_size));
// Copy Data to Kernal
cuda_check(cudaMemcpy(temp, matrix, matrix_size, cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(matrix_d, matrix, matrix_size, cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(kernal_d, kernal, kernal_size, cudaMemcpyHostToDevice));
//Kernal Functions
dim3 block_dim(32, 32);
dim3 grid_dim(DIV_ROUND_UP(windowSizeX, block_dim.x), DIV_ROUND_UP(windowSizeY, block_dim.y));
matrix_multiply_kernel<<<grid_dim, block_dim>>>(temp, matrix_d, kernal_d, order, middle, windowSizeX, windowSizeY);
cuda_check(cudaPeekAtLastError());
cuda_check(cudaDeviceSynchronize());
//Copy back to Host
cuda_check(cudaMemcpy(matrix, matrix_d, matrix_size, cudaMemcpyDeviceToHost));
//Free data
cuda_check(cudaFree(temp));
cuda_check(cudaFree(matrix_d));
cuda_check(cudaFree(kernal_d));
}
/////////////////
//Main Function//
/////////////////
int main(int argc, char **argv)
{
char firstLine[10];
int windowSizeX = 0, windowSizeY = 0, temp, order;
float sigma;
//Read in inputs, check if they are correct!
if(argc != 4){
fprintf(stderr, "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n");
exit(1);
}
FILE *fp;
//If file cannout open
if((fp = fopen(argv[1], "rb")) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
// if File is incorrect
if(fgets(firstLine, 4, fp) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
//if info is incorrect
if(strcmp(firstLine, "P5\n")){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &windowSizeX) || !fscanf(fp,"%d", &windowSizeY)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(windowSizeX == 0 && windowSizeY == 0){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &temp)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(temp != 255){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
getc(fp);
//Create matrix
unsigned char* matrix = (unsigned char*)malloc(sizeof(unsigned char) * windowSizeX * windowSizeY);
//Read in Matrix
if(fread(matrix, sizeof(unsigned char), windowSizeX*windowSizeY,fp) != (unsigned)(windowSizeX*windowSizeY)){
fprintf(stderr, "Error: invalid PGM pixels\n");
exit(1);
}
sigma = atof(argv[3]);
if(sigma == 0){
fprintf(stderr, "Error: invalid sigma value\n");
exit(1);
}
//Create the order, if order is even, add 1
order = ceil(sigma * 6);
if(order%2 == 0){
order++;
}
if(order > windowSizeX || order > windowSizeY){
fprintf(stderr, "Error: sigma value too big for image size\n");
exit(1);
}
int middle = ceil(order/2);
//Intialize the kernal
float sum = 0;
float kernal [order*order];
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
int x2 = x - middle, y2 = y - middle;
kernal[(order * y) + x] = (1/(2*M_PI*(pow(sigma,2)))) * (pow(M_E, -((pow(x2,2) + pow(y2,2))/(2*pow(sigma,2)))));
sum += kernal[(order * y) + x];
}
}
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
kernal[(order * y) + x] = kernal[(order * y) + x] / sum;
}
}
//Function Time
struct timespec before, after;
clock_gettime(CLOCK_MONOTONIC, &before);
multiplyKernal(matrix, kernal, order, windowSizeX, windowSizeY);
clock_gettime(CLOCK_MONOTONIC, &after);
//Function End
unsigned long elapsed_ns = (after.tv_sec - before.tv_sec)*(1E9) + after.tv_nsec - before.tv_nsec;
double seconds = elapsed_ns / (1E9);
printf("Running time: %f secs\n", seconds);
char name[255];
sprintf(name, "%s", argv[2]);
//Print back to output file
FILE *fd;
fd = fopen(name, "w+");
fprintf(fd, "P5\n");
fprintf(fd, "%d %d\n", windowSizeX, windowSizeY);
fprintf(fd, "255\n");
for(int y = 0; y < windowSizeY; y++) {
for(int x = 0; x < windowSizeX; x++) {
fprintf(fd, "%c", matrix[(windowSizeX * y) + x]);
}
}
fclose(fp);
fclose(fd);
free(matrix);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<string.h>
#include<math.h>
//Cuda checks
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(hipError_t ret, const char *file, int line){
if(ret != hipSuccess) {
fprintf(stderr, "CudaError: %s %s %d\n", hipGetErrorString(ret), file, line);
exit(1);
}
}
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
// Kernal Multiply Function
__global__ void matrix_multiply_kernel(unsigned char *temp, unsigned char *matrix, float *kernal, int order, int middle, int windowSizeX, int windowSizeY){
//Find place in the execution
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
//If out of bounds, do nothing
if(y >= windowSizeY || x >= windowSizeX){
return;
}
//Else do function
for(int y2 = 0; y2 < order; y2++){
for(int x2 = 0; x2 < order; x2++){
int tempX = x - middle + x2, tempY = y - middle + y2;
if(tempX < 0){
tempX = 0;
}else if(tempX >= windowSizeX){
tempX = windowSizeX - 1;
}
if(tempY < 0){
tempY = 0;
}else if(tempY >= windowSizeY){
tempY = windowSizeY - 1;
}
sum += temp[(windowSizeX * tempY) + tempX] * kernal[(order * x2) + y2];
}
}
//Clamp the sum value
if(sum < 0){
sum = 0;
}else if(sum > 255){
sum = 255;
}
//Add sum value to matrix
matrix[(windowSizeX * y) + x] = (unsigned char) sum;
}
///////////////////
//Multiply Kernal//
///////////////////
void multiplyKernal(unsigned char* matrix, float* kernal, int order, int windowSizeX, int windowSizeY){
//Find the middle of the kernal
int middle = ceil(order/2);
//Declare all the Kernal data
unsigned char *temp, *matrix_d;
float *kernal_d;
int kernal_size = order*order*sizeof(float);
int matrix_size = windowSizeX * windowSizeY * sizeof(char);
//Initialize Kernal Data
cuda_check(hipMalloc(&temp, matrix_size));
cuda_check(hipMalloc(&matrix_d, matrix_size));
cuda_check(hipMalloc(&kernal_d, kernal_size));
// Copy Data to Kernal
cuda_check(hipMemcpy(temp, matrix, matrix_size, hipMemcpyHostToDevice));
cuda_check(hipMemcpy(matrix_d, matrix, matrix_size, hipMemcpyHostToDevice));
cuda_check(hipMemcpy(kernal_d, kernal, kernal_size, hipMemcpyHostToDevice));
//Kernal Functions
dim3 block_dim(32, 32);
dim3 grid_dim(DIV_ROUND_UP(windowSizeX, block_dim.x), DIV_ROUND_UP(windowSizeY, block_dim.y));
matrix_multiply_kernel<<<grid_dim, block_dim>>>(temp, matrix_d, kernal_d, order, middle, windowSizeX, windowSizeY);
cuda_check(hipPeekAtLastError());
cuda_check(hipDeviceSynchronize());
//Copy back to Host
cuda_check(hipMemcpy(matrix, matrix_d, matrix_size, hipMemcpyDeviceToHost));
//Free data
cuda_check(hipFree(temp));
cuda_check(hipFree(matrix_d));
cuda_check(hipFree(kernal_d));
}
/////////////////
//Main Function//
/////////////////
int main(int argc, char **argv)
{
char firstLine[10];
int windowSizeX = 0, windowSizeY = 0, temp, order;
float sigma;
//Read in inputs, check if they are correct!
if(argc != 4){
fprintf(stderr, "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n");
exit(1);
}
FILE *fp;
//If file cannout open
if((fp = fopen(argv[1], "rb")) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
// if File is incorrect
if(fgets(firstLine, 4, fp) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
//if info is incorrect
if(strcmp(firstLine, "P5\n")){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &windowSizeX) || !fscanf(fp,"%d", &windowSizeY)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(windowSizeX == 0 && windowSizeY == 0){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &temp)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(temp != 255){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
getc(fp);
//Create matrix
unsigned char* matrix = (unsigned char*)malloc(sizeof(unsigned char) * windowSizeX * windowSizeY);
//Read in Matrix
if(fread(matrix, sizeof(unsigned char), windowSizeX*windowSizeY,fp) != (unsigned)(windowSizeX*windowSizeY)){
fprintf(stderr, "Error: invalid PGM pixels\n");
exit(1);
}
sigma = atof(argv[3]);
if(sigma == 0){
fprintf(stderr, "Error: invalid sigma value\n");
exit(1);
}
//Create the order, if order is even, add 1
order = ceil(sigma * 6);
if(order%2 == 0){
order++;
}
if(order > windowSizeX || order > windowSizeY){
fprintf(stderr, "Error: sigma value too big for image size\n");
exit(1);
}
int middle = ceil(order/2);
//Intialize the kernal
float sum = 0;
float kernal [order*order];
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
int x2 = x - middle, y2 = y - middle;
kernal[(order * y) + x] = (1/(2*M_PI*(pow(sigma,2)))) * (pow(M_E, -((pow(x2,2) + pow(y2,2))/(2*pow(sigma,2)))));
sum += kernal[(order * y) + x];
}
}
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
kernal[(order * y) + x] = kernal[(order * y) + x] / sum;
}
}
//Function Time
struct timespec before, after;
clock_gettime(CLOCK_MONOTONIC, &before);
multiplyKernal(matrix, kernal, order, windowSizeX, windowSizeY);
clock_gettime(CLOCK_MONOTONIC, &after);
//Function End
unsigned long elapsed_ns = (after.tv_sec - before.tv_sec)*(1E9) + after.tv_nsec - before.tv_nsec;
double seconds = elapsed_ns / (1E9);
printf("Running time: %f secs\n", seconds);
char name[255];
sprintf(name, "%s", argv[2]);
//Print back to output file
FILE *fd;
fd = fopen(name, "w+");
fprintf(fd, "P5\n");
fprintf(fd, "%d %d\n", windowSizeX, windowSizeY);
fprintf(fd, "255\n");
for(int y = 0; y < windowSizeY; y++) {
for(int x = 0; x < windowSizeX; x++) {
fprintf(fd, "%c", matrix[(windowSizeX * y) + x]);
}
}
fclose(fp);
fclose(fd);
free(matrix);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<string.h>
#include<math.h>
//Cuda checks
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(hipError_t ret, const char *file, int line){
if(ret != hipSuccess) {
fprintf(stderr, "CudaError: %s %s %d\n", hipGetErrorString(ret), file, line);
exit(1);
}
}
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
// Kernal Multiply Function
__global__ void matrix_multiply_kernel(unsigned char *temp, unsigned char *matrix, float *kernal, int order, int middle, int windowSizeX, int windowSizeY){
//Find place in the execution
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
//If out of bounds, do nothing
if(y >= windowSizeY || x >= windowSizeX){
return;
}
//Else do function
for(int y2 = 0; y2 < order; y2++){
for(int x2 = 0; x2 < order; x2++){
int tempX = x - middle + x2, tempY = y - middle + y2;
if(tempX < 0){
tempX = 0;
}else if(tempX >= windowSizeX){
tempX = windowSizeX - 1;
}
if(tempY < 0){
tempY = 0;
}else if(tempY >= windowSizeY){
tempY = windowSizeY - 1;
}
sum += temp[(windowSizeX * tempY) + tempX] * kernal[(order * x2) + y2];
}
}
//Clamp the sum value
if(sum < 0){
sum = 0;
}else if(sum > 255){
sum = 255;
}
//Add sum value to matrix
matrix[(windowSizeX * y) + x] = (unsigned char) sum;
}
///////////////////
//Multiply Kernal//
///////////////////
void multiplyKernal(unsigned char* matrix, float* kernal, int order, int windowSizeX, int windowSizeY){
//Find the middle of the kernal
int middle = ceil(order/2);
//Declare all the Kernal data
unsigned char *temp, *matrix_d;
float *kernal_d;
int kernal_size = order*order*sizeof(float);
int matrix_size = windowSizeX * windowSizeY * sizeof(char);
//Initialize Kernal Data
cuda_check(hipMalloc(&temp, matrix_size));
cuda_check(hipMalloc(&matrix_d, matrix_size));
cuda_check(hipMalloc(&kernal_d, kernal_size));
// Copy Data to Kernal
cuda_check(hipMemcpy(temp, matrix, matrix_size, hipMemcpyHostToDevice));
cuda_check(hipMemcpy(matrix_d, matrix, matrix_size, hipMemcpyHostToDevice));
cuda_check(hipMemcpy(kernal_d, kernal, kernal_size, hipMemcpyHostToDevice));
//Kernal Functions
dim3 block_dim(32, 32);
dim3 grid_dim(DIV_ROUND_UP(windowSizeX, block_dim.x), DIV_ROUND_UP(windowSizeY, block_dim.y));
matrix_multiply_kernel<<<grid_dim, block_dim>>>(temp, matrix_d, kernal_d, order, middle, windowSizeX, windowSizeY);
cuda_check(hipPeekAtLastError());
cuda_check(hipDeviceSynchronize());
//Copy back to Host
cuda_check(hipMemcpy(matrix, matrix_d, matrix_size, hipMemcpyDeviceToHost));
//Free data
cuda_check(hipFree(temp));
cuda_check(hipFree(matrix_d));
cuda_check(hipFree(kernal_d));
}
/////////////////
//Main Function//
/////////////////
int main(int argc, char **argv)
{
char firstLine[10];
int windowSizeX = 0, windowSizeY = 0, temp, order;
float sigma;
//Read in inputs, check if they are correct!
if(argc != 4){
fprintf(stderr, "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n");
exit(1);
}
FILE *fp;
//If file cannout open
if((fp = fopen(argv[1], "rb")) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
// if File is incorrect
if(fgets(firstLine, 4, fp) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
//if info is incorrect
if(strcmp(firstLine, "P5\n")){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &windowSizeX) || !fscanf(fp,"%d", &windowSizeY)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(windowSizeX == 0 && windowSizeY == 0){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &temp)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(temp != 255){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
getc(fp);
//Create matrix
unsigned char* matrix = (unsigned char*)malloc(sizeof(unsigned char) * windowSizeX * windowSizeY);
//Read in Matrix
if(fread(matrix, sizeof(unsigned char), windowSizeX*windowSizeY,fp) != (unsigned)(windowSizeX*windowSizeY)){
fprintf(stderr, "Error: invalid PGM pixels\n");
exit(1);
}
sigma = atof(argv[3]);
if(sigma == 0){
fprintf(stderr, "Error: invalid sigma value\n");
exit(1);
}
//Create the order, if order is even, add 1
order = ceil(sigma * 6);
if(order%2 == 0){
order++;
}
if(order > windowSizeX || order > windowSizeY){
fprintf(stderr, "Error: sigma value too big for image size\n");
exit(1);
}
int middle = ceil(order/2);
//Intialize the kernal
float sum = 0;
float kernal [order*order];
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
int x2 = x - middle, y2 = y - middle;
kernal[(order * y) + x] = (1/(2*M_PI*(pow(sigma,2)))) * (pow(M_E, -((pow(x2,2) + pow(y2,2))/(2*pow(sigma,2)))));
sum += kernal[(order * y) + x];
}
}
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
kernal[(order * y) + x] = kernal[(order * y) + x] / sum;
}
}
//Function Time
struct timespec before, after;
clock_gettime(CLOCK_MONOTONIC, &before);
multiplyKernal(matrix, kernal, order, windowSizeX, windowSizeY);
clock_gettime(CLOCK_MONOTONIC, &after);
//Function End
unsigned long elapsed_ns = (after.tv_sec - before.tv_sec)*(1E9) + after.tv_nsec - before.tv_nsec;
double seconds = elapsed_ns / (1E9);
printf("Running time: %f secs\n", seconds);
char name[255];
sprintf(name, "%s", argv[2]);
//Print back to output file
FILE *fd;
fd = fopen(name, "w+");
fprintf(fd, "P5\n");
fprintf(fd, "%d %d\n", windowSizeX, windowSizeY);
fprintf(fd, "255\n");
for(int y = 0; y < windowSizeY; y++) {
for(int x = 0; x < windowSizeX; x++) {
fprintf(fd, "%c", matrix[(windowSizeX * y) + x]);
}
}
fclose(fp);
fclose(fd);
free(matrix);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22matrix_multiply_kernelPhS_Pfiiii
.globl _Z22matrix_multiply_kernelPhS_Pfiiii
.p2align 8
.type _Z22matrix_multiply_kernelPhS_Pfiiii,@function
_Z22matrix_multiply_kernelPhS_Pfiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x2
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_add_i32 s11, s4, -1
s_add_i32 s12, s5, -1
s_mov_b32 s9, 0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v3, s8, v1
v_subrev_nc_u32_e32 v4, s8, v0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s13, v4
s_mov_b32 s8, s13
s_mov_b32 s14, s9
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_cndmask_b32_e32 v6, s12, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0, v6, vcc_lo
v_mul_lo_u32 v5, v5, s4
.p2align 6
.LBB0_4:
v_add_nc_u32_e32 v6, s14, v3
s_lshl_b64 s[16:17], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
v_cmp_gt_i32_e32 vcc_lo, s4, v6
s_load_b32 s15, s[16:17], 0x0
s_add_i32 s14, s14, 1
s_add_i32 s8, s8, s10
s_cmp_eq_u32 s10, s14
v_cndmask_b32_e32 v7, s11, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, 0, v7, vcc_lo
v_add_nc_u32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s15, v6
s_cbranch_scc0 .LBB0_4
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s13, s10
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v2, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v3, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ngt_f32_e32 0, v2
s_cbranch_execz .LBB0_11
s_mov_b32 s3, exec_lo
v_cmpx_lt_f32_e32 0x437f0000, v2
v_mov_b32_e32 v2, 0x437f0000
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v2
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v2, v3
v_ashrrev_i32_e32 v1, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22matrix_multiply_kernelPhS_Pfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22matrix_multiply_kernelPhS_Pfiiii, .Lfunc_end0-_Z22matrix_multiply_kernelPhS_Pfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22matrix_multiply_kernelPhS_Pfiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z22matrix_multiply_kernelPhS_Pfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<string.h>
#include<math.h>
//Cuda checks
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(hipError_t ret, const char *file, int line){
if(ret != hipSuccess) {
fprintf(stderr, "CudaError: %s %s %d\n", hipGetErrorString(ret), file, line);
exit(1);
}
}
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
// Kernal Multiply Function
__global__ void matrix_multiply_kernel(unsigned char *temp, unsigned char *matrix, float *kernal, int order, int middle, int windowSizeX, int windowSizeY){
//Find place in the execution
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
//If out of bounds, do nothing
if(y >= windowSizeY || x >= windowSizeX){
return;
}
//Else do function
for(int y2 = 0; y2 < order; y2++){
for(int x2 = 0; x2 < order; x2++){
int tempX = x - middle + x2, tempY = y - middle + y2;
if(tempX < 0){
tempX = 0;
}else if(tempX >= windowSizeX){
tempX = windowSizeX - 1;
}
if(tempY < 0){
tempY = 0;
}else if(tempY >= windowSizeY){
tempY = windowSizeY - 1;
}
sum += temp[(windowSizeX * tempY) + tempX] * kernal[(order * x2) + y2];
}
}
//Clamp the sum value
if(sum < 0){
sum = 0;
}else if(sum > 255){
sum = 255;
}
//Add sum value to matrix
matrix[(windowSizeX * y) + x] = (unsigned char) sum;
}
///////////////////
//Multiply Kernal//
///////////////////
void multiplyKernal(unsigned char* matrix, float* kernal, int order, int windowSizeX, int windowSizeY){
//Find the middle of the kernal
int middle = ceil(order/2);
//Declare all the Kernal data
unsigned char *temp, *matrix_d;
float *kernal_d;
int kernal_size = order*order*sizeof(float);
int matrix_size = windowSizeX * windowSizeY * sizeof(char);
//Initialize Kernal Data
cuda_check(hipMalloc(&temp, matrix_size));
cuda_check(hipMalloc(&matrix_d, matrix_size));
cuda_check(hipMalloc(&kernal_d, kernal_size));
// Copy Data to Kernal
cuda_check(hipMemcpy(temp, matrix, matrix_size, hipMemcpyHostToDevice));
cuda_check(hipMemcpy(matrix_d, matrix, matrix_size, hipMemcpyHostToDevice));
cuda_check(hipMemcpy(kernal_d, kernal, kernal_size, hipMemcpyHostToDevice));
//Kernal Functions
dim3 block_dim(32, 32);
dim3 grid_dim(DIV_ROUND_UP(windowSizeX, block_dim.x), DIV_ROUND_UP(windowSizeY, block_dim.y));
matrix_multiply_kernel<<<grid_dim, block_dim>>>(temp, matrix_d, kernal_d, order, middle, windowSizeX, windowSizeY);
cuda_check(hipPeekAtLastError());
cuda_check(hipDeviceSynchronize());
//Copy back to Host
cuda_check(hipMemcpy(matrix, matrix_d, matrix_size, hipMemcpyDeviceToHost));
//Free data
cuda_check(hipFree(temp));
cuda_check(hipFree(matrix_d));
cuda_check(hipFree(kernal_d));
}
/////////////////
//Main Function//
/////////////////
int main(int argc, char **argv)
{
char firstLine[10];
int windowSizeX = 0, windowSizeY = 0, temp, order;
float sigma;
//Read in inputs, check if they are correct!
if(argc != 4){
fprintf(stderr, "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n");
exit(1);
}
FILE *fp;
//If file cannout open
if((fp = fopen(argv[1], "rb")) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
// if File is incorrect
if(fgets(firstLine, 4, fp) == NULL){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
//if info is incorrect
if(strcmp(firstLine, "P5\n")){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &windowSizeX) || !fscanf(fp,"%d", &windowSizeY)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(windowSizeX == 0 && windowSizeY == 0){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
if(!fscanf(fp,"%d", &temp)){
fprintf(stderr, "Error: cannot open file %s\n", argv[1]);
exit(1);
}
if(temp != 255){
fprintf(stderr, "Error: invalid PGM information\n");
exit(1);
}
getc(fp);
//Create matrix
unsigned char* matrix = (unsigned char*)malloc(sizeof(unsigned char) * windowSizeX * windowSizeY);
//Read in Matrix
if(fread(matrix, sizeof(unsigned char), windowSizeX*windowSizeY,fp) != (unsigned)(windowSizeX*windowSizeY)){
fprintf(stderr, "Error: invalid PGM pixels\n");
exit(1);
}
sigma = atof(argv[3]);
if(sigma == 0){
fprintf(stderr, "Error: invalid sigma value\n");
exit(1);
}
//Create the order, if order is even, add 1
order = ceil(sigma * 6);
if(order%2 == 0){
order++;
}
if(order > windowSizeX || order > windowSizeY){
fprintf(stderr, "Error: sigma value too big for image size\n");
exit(1);
}
int middle = ceil(order/2);
//Intialize the kernal
float sum = 0;
float kernal [order*order];
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
int x2 = x - middle, y2 = y - middle;
kernal[(order * y) + x] = (1/(2*M_PI*(pow(sigma,2)))) * (pow(M_E, -((pow(x2,2) + pow(y2,2))/(2*pow(sigma,2)))));
sum += kernal[(order * y) + x];
}
}
for(int y = 0; y < order; y++){
for(int x = 0; x < order; x++){
kernal[(order * y) + x] = kernal[(order * y) + x] / sum;
}
}
//Function Time
struct timespec before, after;
clock_gettime(CLOCK_MONOTONIC, &before);
multiplyKernal(matrix, kernal, order, windowSizeX, windowSizeY);
clock_gettime(CLOCK_MONOTONIC, &after);
//Function End
unsigned long elapsed_ns = (after.tv_sec - before.tv_sec)*(1E9) + after.tv_nsec - before.tv_nsec;
double seconds = elapsed_ns / (1E9);
printf("Running time: %f secs\n", seconds);
char name[255];
sprintf(name, "%s", argv[2]);
//Print back to output file
FILE *fd;
fd = fopen(name, "w+");
fprintf(fd, "P5\n");
fprintf(fd, "%d %d\n", windowSizeX, windowSizeY);
fprintf(fd, "255\n");
for(int y = 0; y < windowSizeY; y++) {
for(int x = 0; x < windowSizeX; x++) {
fprintf(fd, "%c", matrix[(windowSizeX * y) + x]);
}
}
fclose(fp);
fclose(fd);
free(matrix);
return 0;
} | .text
.file "gaussian_blur_cuda.hip"
.globl _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii # -- Begin function _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.p2align 4, 0x90
.type _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii,@function
_Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii: # @_Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22matrix_multiply_kernelPhS_Pfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii, .Lfunc_end0-_Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.cfi_endproc
# -- End function
.globl _Z14multiplyKernalPhPfiii # -- Begin function _Z14multiplyKernalPhPfiii
.p2align 4, 0x90
.type _Z14multiplyKernalPhPfiii,@function
_Z14multiplyKernalPhPfiii: # @_Z14multiplyKernalPhPfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
# kill: def $ecx killed $ecx def $rcx
movl %edx, %r13d
movq %rsi, %r12
movq %rdi, %rbp
movq %r8, 48(%rsp) # 8-byte Spill
movl %r8d, %eax
movq %rcx, 40(%rsp) # 8-byte Spill
imull %ecx, %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z11_cuda_check10hipError_tPKci.exit
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z11_cuda_check10hipError_tPKci.exit28
movl %r13d, %r15d
imull %r13d, %r13d
shll $2, %r13d
movslq %r13d, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z11_cuda_check10hipError_tPKci.exit30
movq 16(%rsp), %rdi
movq %rbp, %r13
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z11_cuda_check10hipError_tPKci.exit32
movq (%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z11_cuda_check10hipError_tPKci.exit34
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq 48(%rsp), %r13 # 8-byte Reload
jne .LBB1_12
# %bb.13: # %_Z11_cuda_check10hipError_tPKci.exit36
movq 40(%rsp), %r12 # 8-byte Reload
leal 31(%r12), %eax
shrl $5, %eax
leal 31(%r13), %edi
shrl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
movq 16(%rsp), %rcx
movq (%rsp), %rdx
movq 8(%rsp), %rsi
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movl %r15d, 36(%rsp)
movl %eax, 32(%rsp)
movl %r12d, 28(%rsp)
movl %r13d, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z22matrix_multiply_kernelPhS_Pfiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z11_cuda_check10hipError_tPKci.exit38
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z11_cuda_check10hipError_tPKci.exit40
movq (%rsp), %rsi
movq %rbp, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z11_cuda_check10hipError_tPKci.exit42
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z11_cuda_check10hipError_tPKci.exit44
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z11_cuda_check10hipError_tPKci.exit46
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z11_cuda_check10hipError_tPKci.exit48
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $70, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14multiplyKernalPhPfiii, .Lfunc_end1-_Z14multiplyKernalPhPfiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40c00000 # float 6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.LCPI2_2:
.quad 0x3ff0000000000000 # double 1
.LCPI2_4:
.quad 0x4005bf0a8b145769 # double 2.7182818284590451
.LCPI2_5:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_6:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_3:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.LCPI2_7:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_8:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $408, %rsp # imm = 0x198
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $0, -48(%rbp)
movl $0, -44(%rbp)
cmpl $4, %edi
jne .LBB2_1
# %bb.3:
movq %rsi, %r14
movq 8(%rsi), %rdi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_36
# %bb.4:
movq %rax, %rbx
leaq -154(%rbp), %rdi
movl $4, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB2_36
# %bb.5:
cmpl $669008, -154(%rbp) # imm = 0xA3550
jne .LBB2_6
# %bb.7:
leaq -48(%rbp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB2_36
# %bb.8:
leaq -44(%rbp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB2_36
# %bb.9:
movl -48(%rbp), %eax
orl -44(%rbp), %eax
je .LBB2_6
# %bb.10:
leaq -68(%rbp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB2_36
# %bb.11:
cmpl $255, -68(%rbp)
jne .LBB2_6
# %bb.12:
movq %rbx, %rdi
callq getc
movslq -48(%rbp), %rax
movslq -44(%rbp), %r12
imulq %rax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %rbx, %rcx
callq fread
movl -44(%rbp), %ecx
imull -48(%rbp), %ecx
cmpq %rcx, %rax
jne .LBB2_13
# %bb.14:
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
jne .LBB2_16
jnp .LBB2_15
.LBB2_16:
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm1, -52(%rbp) # 4-byte Spill
mulss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edx
movl %edx, %edi
orl $1, %edi
cmpl -48(%rbp), %edi
jg .LBB2_18
# %bb.17:
cmpl -44(%rbp), %edi
jg .LBB2_18
# %bb.19:
movq %r15, -88(%rbp) # 8-byte Spill
movq %r14, -96(%rbp) # 8-byte Spill
movq %rbx, -104(%rbp) # 8-byte Spill
movq %rsp, -80(%rbp) # 8-byte Spill
movl %edi, %eax
imull %eax, %eax
leaq 15(,%rax,4), %rax
movabsq $17179869168, %rcx # imm = 0x3FFFFFFF0
andq %rax, %rcx
movq %rsp, %r15
subq %rcx, %r15
movq %r15, %rsp
movl %edi, %r14d
testl %edx, %edx
movl %edx, -56(%rbp) # 4-byte Spill
js .LBB2_20
# %bb.32: # %.preheader101.lr.ph
shrl %edx
movss -52(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm2
mulsd %xmm2, %xmm2
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
movsd .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero
divsd %xmm0, %xmm3
addsd %xmm2, %xmm2
movl %edx, -60(%rbp) # 4-byte Spill
movl %edx, %ebx
negl %ebx
xorps %xmm1, %xmm1
xorl %eax, %eax
movapd .LCPI2_3(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0]
movsd .LCPI2_4(%rip), %xmm4 # xmm4 = mem[0],zero
xorl %r13d, %r13d
movl %edi, -64(%rbp) # 4-byte Spill
movq %r15, -112(%rbp) # 8-byte Spill
movsd %xmm2, -136(%rbp) # 8-byte Spill
movsd %xmm3, -128(%rbp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_33: # %.preheader101
# =>This Loop Header: Depth=1
# Child Loop BB2_34 Depth 2
movq %rax, -120(%rbp) # 8-byte Spill
movl %eax, %eax
leaq (%r15,%rax,4), %r15
movl %r13d, %eax
subl -60(%rbp), %eax # 4-byte Folded Reload
xorps %xmm5, %xmm5
cvtsi2sd %eax, %xmm5
mulsd %xmm5, %xmm5
movsd %xmm5, -144(%rbp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_34: # Parent Loop BB2_33 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, -52(%rbp) # 4-byte Spill
leal (%rbx,%r12), %eax
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm1, %xmm1
addsd -144(%rbp), %xmm1 # 8-byte Folded Reload
xorpd %xmm0, %xmm1
divsd %xmm2, %xmm1
movapd %xmm4, %xmm0
callq pow
movsd .LCPI2_4(%rip), %xmm4 # xmm4 = mem[0],zero
movsd -128(%rbp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd -136(%rbp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movss -52(%rbp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulsd %xmm3, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
addss %xmm0, %xmm1
movapd .LCPI2_3(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0]
incq %r12
cmpq %r12, %r14
jne .LBB2_34
# %bb.35: # %._crit_edge
# in Loop: Header=BB2_33 Depth=1
incq %r13
movl -64(%rbp), %edi # 4-byte Reload
movq -120(%rbp), %rax # 8-byte Reload
addl %edi, %eax
cmpq %r14, %r13
movq -112(%rbp), %r15 # 8-byte Reload
jne .LBB2_33
jmp .LBB2_21
.LBB2_20:
xorps %xmm1, %xmm1
.LBB2_21: # %.preheader100
cmpl $0, -56(%rbp) # 4-byte Folded Reload
movq -96(%rbp), %rbx # 8-byte Reload
movq -88(%rbp), %r12 # 8-byte Reload
js .LBB2_26
# %bb.22: # %.preheader99.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_23: # %.preheader99
# =>This Loop Header: Depth=1
# Child Loop BB2_24 Depth 2
movl %eax, %edx
leaq (%r15,%rdx,4), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_24: # Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
cmpq %rsi, %r14
jne .LBB2_24
# %bb.25: # %._crit_edge109
# in Loop: Header=BB2_23 Depth=1
incq %rcx
addl %edi, %eax
cmpq %r14, %rcx
jne .LBB2_23
.LBB2_26: # %._crit_edge111
leaq -192(%rbp), %rsi
movl %edi, %r14d
movl $1, %edi
callq clock_gettime
movl -48(%rbp), %ecx
movl -44(%rbp), %r8d
movq %r12, %rdi
movq %r15, %rsi
movl %r14d, %edx
callq _Z14multiplyKernalPhPfiii
leaq -176(%rbp), %rsi
movl $1, %edi
callq clock_gettime
movq -176(%rbp), %rax
subq -192(%rbp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI2_5(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm2, %xmm2
cvtsi2sdq -168(%rbp), %xmm2
mulsd %xmm1, %xmm0
addsd %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2sdq -184(%rbp), %xmm0
subsd %xmm0, %xmm2
cvttsd2si %xmm2, %rax
movq %rax, %rcx
subsd .LCPI2_6(%rip), %xmm2
cvttsd2si %xmm2, %rdx
sarq $63, %rcx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, %xmm2
punpckldq .LCPI2_7(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI2_8(%rip), %xmm2
movapd %xmm2, %xmm0
unpckhpd %xmm2, %xmm0 # xmm0 = xmm0[1],xmm2[1]
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 16(%rbx), %rsi
leaq -448(%rbp), %r14
movq %r14, %rdi
callq strcpy@PLT
movl $.L.str.12, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
movl $.L.str.4, %edi
movl $3, %esi
movl $1, %edx
movq %rax, %rcx
callq fwrite@PLT
movl -48(%rbp), %edx
movl -44(%rbp), %ecx
xorl %ebx, %ebx
movl $.L.str.13, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
movl $.L.str.14, %edi
movl $4, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite@PLT
cmpl $0, -44(%rbp)
jg .LBB2_27
.LBB2_31: # %._crit_edge116
movq -104(%rbp), %rdi # 8-byte Reload
callq fclose
movq %r14, %rdi
callq fclose
movq %r12, %rdi
callq free
movq -80(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.p2align 4, 0x90
.LBB2_30: # %._crit_edge114
# in Loop: Header=BB2_27 Depth=1
.cfi_def_cfa %rbp, 16
incl %ebx
cmpl -44(%rbp), %ebx
jge .LBB2_31
.LBB2_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_29 Depth 2
movl -48(%rbp), %eax
testl %eax, %eax
jle .LBB2_30
# %bb.28: # %.lr.ph113.preheader
# in Loop: Header=BB2_27 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_29: # %.lr.ph113
# Parent Loop BB2_27 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebx, %eax
cltq
addq %r12, %rax
movzbl (%r15,%rax), %edi
movq %r14, %rsi
callq fputc@PLT
movl -48(%rbp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB2_29
jmp .LBB2_30
.LBB2_36:
movq stderr(%rip), %rdi
movq 8(%r14), %rdx
movl $.L.str.3, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_6:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $31, %esi
jmp .LBB2_2
.LBB2_1:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $63, %esi
jmp .LBB2_2
.LBB2_13:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $26, %esi
jmp .LBB2_2
.LBB2_15:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $27, %esi
jmp .LBB2_2
.LBB2_18:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $42, %esi
.LBB2_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matrix_multiply_kernelPhS_Pfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22matrix_multiply_kernelPhS_Pfiiii,@object # @_Z22matrix_multiply_kernelPhS_Pfiiii
.section .rodata,"a",@progbits
.globl _Z22matrix_multiply_kernelPhS_Pfiiii
.p2align 3, 0x0
_Z22matrix_multiply_kernelPhS_Pfiiii:
.quad _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.size _Z22matrix_multiply_kernelPhS_Pfiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/seanjedi/ECS158Project4/master/gaussian_blur_cuda.hip"
.size .L.str, 111
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n"
.size .L.str.1, 64
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "rb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error: cannot open file %s\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P5\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error: invalid PGM information\n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error: invalid PGM pixels\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: invalid sigma value\n"
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error: sigma value too big for image size\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Running time: %f secs\n"
.size .L.str.10, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "w+"
.size .L.str.12, 3
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d %d\n"
.size .L.str.13, 7
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "255\n"
.size .L.str.14, 5
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "CudaError: %s %s %d\n"
.size .L.str.16, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22matrix_multiply_kernelPhS_Pfiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22matrix_multiply_kernelPhS_Pfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22matrix_multiply_kernelPhS_Pfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R19, SR_CTAID.X ; /* 0x0000000000137919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R19, R19, c[0x0][0x0], R2 ; /* 0x0000000013137a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x180], P0 ; /* 0x0000600013007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff147624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x970 ; /* 0x0000088000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R20.reuse, -0x1, RZ ; /* 0xffffffff14027810 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R21, R20.reuse, 0x4, RZ ; /* 0x0000000414157824 */
/* 0x040fe200078e00ff */
/*0110*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x000fe200078ec0ff */
/*0120*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0130*/ IADD3 R25, R19.reuse, 0x3, RZ ; /* 0x0000000313197810 */
/* 0x040fe20007ffe0ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0160*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R22, R19, -c[0x0][0x17c], RZ ; /* 0x80005f0013167a10 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R23, R0, -c[0x0][0x17c], RZ ; /* 0x80005f0000177a10 */
/* 0x000fe20007ffe0ff */
/*01a0*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe2000fffe13f */
/*01b0*/ IADD3 R25, R25, -c[0x0][0x17c], RZ ; /* 0x80005f0019197a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ UIADD3 UR5, -UR5, UR7, URZ ; /* 0x0000000705057290 */
/* 0x000fe2000fffe13f */
/*01d0*/ IADD3 R26, R20, -c[0x0][0x178], RZ ; /* 0x80005e00141a7a10 */
/* 0x000fc40007ffe0ff */
/*01e0*/ IMAD.IADD R2, R23, 0x1, R24 ; /* 0x0000000117027824 */
/* 0x000fe200078e0218 */
/*01f0*/ ISETP.NE.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f25270 */
/*0200*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*0210*/ ISETP.GE.AND P3, PT, R2.reuse, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x040fe40003f66270 */
/*0220*/ ISETP.GE.AND P2, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe40003f46270 */
/*0230*/ SEL R27, R2, UR5, !P3 ; /* 0x00000005021b7c07 */
/* 0x000fc8000d800000 */
/*0240*/ SEL R27, R27, RZ, P2 ; /* 0x000000ff1b1b7207 */
/* 0x000fe20001000000 */
/*0250*/ @!P0 BRA 0x650 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*0260*/ IADD3 R2, R24, c[0x0][0x178], RZ ; /* 0x00005e0018027a10 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.MOV.U32 R18, RZ, RZ, R25 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0019 */
/*02b0*/ IMAD.WIDE R4, R24, R5, c[0x0][0x170] ; /* 0x00005c0018047625 */
/* 0x000fc800078e0205 */
/*02c0*/ IADD3 R6, R18.reuse, -0x3, RZ ; /* 0xfffffffd12067810 */
/* 0x040fe40007ffe0ff */
/*02d0*/ IADD3 R7, R18, -0x2, RZ ; /* 0xfffffffe12077810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P5, PT, R6.reuse, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x040fe40003fa6270 */
/*02f0*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f66270 */
/*0300*/ IADD3 R8, R18, -0x1, RZ ; /* 0xffffffff12087810 */
/* 0x000fc40007ffe0ff */
/*0310*/ ISETP.GE.AND P4, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x040fe40003f86270 */
/*0320*/ SEL R6, R6, UR4, !P5 ; /* 0x0000000406067c07 */
/* 0x000fe4000e800000 */
/*0330*/ ISETP.GE.AND P5, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe40003fa6270 */
/*0340*/ ISETP.GE.AND P6, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003fc6270 */
/*0350*/ SEL R7, R7, UR4, !P4 ; /* 0x0000000407077c07 */
/* 0x000fe4000e000000 */
/*0360*/ SEL R6, R6, RZ, P3 ; /* 0x000000ff06067207 */
/* 0x000fc40001800000 */
/*0370*/ ISETP.GE.AND P2, PT, R18, c[0x0][0x180], PT ; /* 0x0000600012007a0c */
/* 0x000fe40003f46270 */
/*0380*/ ISETP.GE.AND P3, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f66270 */
/*0390*/ SEL R9, R8, UR4, !P6 ; /* 0x0000000408097c07 */
/* 0x000fe2000f000000 */
/*03a0*/ IMAD R8, R27, c[0x0][0x180], R6 ; /* 0x000060001b087a24 */
/* 0x000fe200078e0206 */
/*03b0*/ SEL R10, R7, RZ, P5 ; /* 0x000000ff070a7207 */
/* 0x000fe40002800000 */
/*03c0*/ ISETP.GE.AND P4, PT, R18.reuse, RZ, PT ; /* 0x000000ff1200720c */
/* 0x040fe40003f86270 */
/*03d0*/ SEL R11, R18, UR4, !P2 ; /* 0x00000004120b7c07 */
/* 0x000fe2000d000000 */
/*03e0*/ IMAD R7, R27, c[0x0][0x180], R10 ; /* 0x000060001b077a24 */
/* 0x000fe200078e020a */
/*03f0*/ SEL R6, R9, RZ, P3 ; /* 0x000000ff09067207 */
/* 0x000fc40001800000 */
/*0400*/ IADD3 R12, P2, R8.reuse, c[0x0][0x160], RZ ; /* 0x00005800080c7a10 */
/* 0x040fe40007f5e0ff */
/*0410*/ SEL R10, R11, RZ, P4 ; /* 0x000000ff0b0a7207 */
/* 0x000fe20002000000 */
/*0420*/ IMAD R9, R27, c[0x0][0x180], R6 ; /* 0x000060001b097a24 */
/* 0x000fe200078e0206 */
/*0430*/ IADD3 R6, P3, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fe40007f7e0ff */
/*0440*/ LEA.HI.X.SX32 R13, R8, c[0x0][0x164], 0x1, P2 ; /* 0x00005900080d7a11 */
/* 0x000fe200010f0eff */
/*0450*/ IMAD R11, R27, c[0x0][0x180], R10 ; /* 0x000060001b0b7a24 */
/* 0x000fe200078e020a */
/*0460*/ IADD3 R8, P2, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe40007f5e0ff */
/*0470*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P3 ; /* 0x0000590007077a11 */
/* 0x000fe200018f0eff */
/*0480*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x0000a2000c1e1100 */
/*0490*/ IADD3 R10, P3, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fc40007f7e0ff */
/*04a0*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P2 ; /* 0x0000590009097a11 */
/* 0x000fe200010f0eff */
/*04b0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x0002e2000c1e1100 */
/*04c0*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P3 ; /* 0x000059000b0b7a11 */
/* 0x000fe200018f0eff */
/*04d0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff117624 */
/* 0x000fe400078e00ff */
/*04e0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000964000c1e1100 */
/*04f0*/ IMAD.WIDE R14, R17.reuse, 0x4, R2 ; /* 0x00000004110e7825 */
/* 0x040fe400078e0202 */
/*0500*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000368000c1e1100 */
/*0510*/ LDG.E R13, [R4.64] ; /* 0x00000008040d7981 */
/* 0x001162000c1e1900 */
/*0520*/ IMAD.WIDE R16, R17, 0x4, R14 ; /* 0x0000000411107825 */
/* 0x000fc600078e020e */
/*0530*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x010968000c1e1900 */
/*0540*/ LDG.E R7, [R14.64] ; /* 0x000000080e077981 */
/* 0x002f68000c1e1900 */
/*0550*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f62000c1e1900 */
/*0560*/ IADD3 R29, R29, 0x4, RZ ; /* 0x000000041d1d7810 */
/* 0x000fca0007ffe0ff */
/*0570*/ IMAD.IADD R11, R26, 0x1, R29 ; /* 0x000000011a0b7824 */
/* 0x000fca00078e021d */
/*0580*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f45270 */
/*0590*/ IMAD.WIDE R4, R21, 0x4, R4 ; /* 0x0000000415047825 */
/* 0x001fe200078e0204 */
/*05a0*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fc60007ffe0ff */
/*05b0*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x010fe200078e0202 */
/*05c0*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x004e300000101000 */
/*05d0*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*05e0*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x020ea20000101000 */
/*05f0*/ FFMA R28, R12, R13, R28 ; /* 0x0000000d0c1c7223 */
/* 0x001fce000000001c */
/*0600*/ I2F.U16 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000101000 */
/*0610*/ FFMA R28, R6, R9, R28 ; /* 0x00000009061c7223 */
/* 0x002fc8000000001c */
/*0620*/ FFMA R7, R8, R7, R28 ; /* 0x0000000708077223 */
/* 0x004fc8000000001c */
/*0630*/ FFMA R28, R10, R16, R7 ; /* 0x000000100a1c7223 */
/* 0x001fe20000000007 */
/*0640*/ @P2 BRA 0x2c0 ; /* 0xfffffc7000002947 */
/* 0x000fea000383ffff */
/*0650*/ @!P1 BRA 0x940 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.IADD R8, R22, 0x1, R29 ; /* 0x0000000116087824 */
/* 0x000fca00078e021d */
/*0670*/ ISETP.GE.AND P2, PT, R8.reuse, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x040fe40003f46270 */
/*0680*/ ISETP.GE.AND P1, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f26270 */
/*0690*/ SEL R2, R8, UR4, !P2 ; /* 0x0000000408027c07 */
/* 0x000fc8000d000000 */
/*06a0*/ SEL R2, R2, RZ, P1 ; /* 0x000000ff02027207 */
/* 0x000fca0000800000 */
/*06b0*/ IMAD R2, R27, c[0x0][0x180], R2 ; /* 0x000060001b027a24 */
/* 0x000fca00078e0202 */
/*06c0*/ IADD3 R6, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fc80007f3e0ff */
/*06d0*/ LEA.HI.X.SX32 R7, R2, c[0x0][0x164], 0x1, P1 ; /* 0x0000590002077a11 */
/* 0x000fca00008f0eff */
/*06e0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ea2000c1e1100 */
/*06f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD R29, R29, c[0x0][0x178], R24 ; /* 0x00005e001d1d7a24 */
/* 0x000fc800078e0218 */
/*0710*/ IMAD.WIDE R2, R29, R4, c[0x0][0x170] ; /* 0x00005c001d027625 */
/* 0x000fcc00078e0204 */
/*0720*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ee2000c1e1900 */
/*0730*/ ISETP.NE.AND P1, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe20003f25270 */
/*0740*/ I2F.U16 R5, R6 ; /* 0x0000000600057306 */
/* 0x004ee40000101000 */
/*0750*/ FFMA R28, R5, R2, R28 ; /* 0x00000002051c7223 */
/* 0x008fd4000000001c */
/*0760*/ @!P1 BRA 0x940 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.NE.AND P1, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe40003f25270 */
/*0780*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x000fc80007ffe0ff */
/*0790*/ ISETP.GE.AND P3, PT, R2.reuse, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x040fe40003f66270 */
/*07a0*/ ISETP.GE.AND P2, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe40003f46270 */
/*07b0*/ SEL R2, R2, UR4, !P3 ; /* 0x0000000402027c07 */
/* 0x000fc6000d800000 */
/*07c0*/ @P1 IADD3 R3, R8, 0x2, RZ ; /* 0x0000000208031810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ SEL R2, R2, RZ, P2 ; /* 0x000000ff02027207 */
/* 0x000fe40001000000 */
/*07e0*/ @P1 ISETP.GE.AND P4, PT, R3.reuse, c[0x0][0x180], PT ; /* 0x0000600003001a0c */
/* 0x040fe40003f86270 */
/*07f0*/ @P1 ISETP.GE.AND P3, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300120c */
/* 0x040fe40003f66270 */
/*0800*/ @P1 SEL R3, R3, UR4, !P4 ; /* 0x0000000403031c07 */
/* 0x000fc8000e000000 */
/*0810*/ @P1 SEL R6, R3, RZ, P3 ; /* 0x000000ff03061207 */
/* 0x000fe20001800000 */
/*0820*/ IMAD R3, R27, c[0x0][0x180], R2 ; /* 0x000060001b037a24 */
/* 0x000fc800078e0202 */
/*0830*/ @P1 IMAD R27, R27, c[0x0][0x180], R6 ; /* 0x000060001b1b1a24 */
/* 0x000fe200078e0206 */
/*0840*/ IADD3 R2, P2, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f5e0ff */
/*0850*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P2 ; /* 0x0000590003037a11 */
/* 0x000fe400010f0eff */
/*0860*/ @P1 IADD3 R6, P2, R27, c[0x0][0x160], RZ ; /* 0x000058001b061a10 */
/* 0x000fc60007f5e0ff */
/*0870*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea2000c1e1100 */
/*0880*/ @P1 LEA.HI.X.SX32 R7, R27, c[0x0][0x164], 0x1, P2 ; /* 0x000059001b071a11 */
/* 0x000fe400010f0eff */
/*0890*/ IADD3 R9, R29, c[0x0][0x178], RZ ; /* 0x00005e001d097a10 */
/* 0x000fc60007ffe0ff */
/*08a0*/ @P1 LDG.E.U8 R6, [R6.64] ; /* 0x0000000806061981 */
/* 0x000ee2000c1e1100 */
/*08b0*/ @P1 IADD3 R5, R9.reuse, c[0x0][0x178], RZ ; /* 0x00005e0009051a10 */
/* 0x040fe20007ffe0ff */
/*08c0*/ IMAD.WIDE R8, R9, R4, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc800078e0204 */
/*08d0*/ @P1 IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005041625 */
/* 0x000fe400078e0204 */
/*08e0*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f28000c1e1900 */
/*08f0*/ @P1 LDG.E R4, [R4.64] ; /* 0x0000000804041981 */
/* 0x000f62000c1e1900 */
/*0900*/ I2F.U16 R11, R2 ; /* 0x00000002000b7306 */
/* 0x004f300000101000 */
/*0910*/ @P1 I2F.U16 R13, R6 ; /* 0x00000006000d1306 */
/* 0x008f620000101000 */
/*0920*/ FFMA R28, R11, R8, R28 ; /* 0x000000080b1c7223 */
/* 0x010fc8000000001c */
/*0930*/ @P1 FFMA R28, R13, R4, R28 ; /* 0x000000040d1c1223 */
/* 0x020fc6000000001c */
/*0940*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fc80007ffe0ff */
/*0950*/ ISETP.GE.AND P1, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fda0003f26270 */
/*0960*/ @!P1 BRA 0x1e0 ; /* 0xfffff87000009947 */
/* 0x000fea000383ffff */
/*0970*/ FSETP.GEU.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720b */
/* 0x000fe20003f0e000 */
/*0980*/ IMAD R0, R0, c[0x0][0x180], R19 ; /* 0x0000600000007a24 */
/* 0x000fe200078e0213 */
/*0990*/ FMNMX.NAN R28, R28, 255, PT ; /* 0x437f00001c1c7809 */
/* 0x000fc80003820000 */
/*09a0*/ FSEL R28, R28, RZ, P0 ; /* 0x000000ff1c1c7208 */
/* 0x000fe40000000000 */
/*09b0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x040fe40007f1e0ff */
/*09c0*/ F2I.U32.TRUNC.NTZ R5, R28 ; /* 0x0000001c00057305 */
/* 0x000e24000020f000 */
/*09d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f0eff */
/*09e0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101108 */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22matrix_multiply_kernelPhS_Pfiiii
.globl _Z22matrix_multiply_kernelPhS_Pfiiii
.p2align 8
.type _Z22matrix_multiply_kernelPhS_Pfiiii,@function
_Z22matrix_multiply_kernelPhS_Pfiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x2
s_load_b32 s8, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_add_i32 s11, s4, -1
s_add_i32 s12, s5, -1
s_mov_b32 s9, 0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v3, s8, v1
v_subrev_nc_u32_e32 v4, s8, v0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s13, v4
s_mov_b32 s8, s13
s_mov_b32 s14, s9
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_cndmask_b32_e32 v6, s12, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0, v6, vcc_lo
v_mul_lo_u32 v5, v5, s4
.p2align 6
.LBB0_4:
v_add_nc_u32_e32 v6, s14, v3
s_lshl_b64 s[16:17], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
v_cmp_gt_i32_e32 vcc_lo, s4, v6
s_load_b32 s15, s[16:17], 0x0
s_add_i32 s14, s14, 1
s_add_i32 s8, s8, s10
s_cmp_eq_u32 s10, s14
v_cndmask_b32_e32 v7, s11, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, 0, v7, vcc_lo
v_add_nc_u32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s15, v6
s_cbranch_scc0 .LBB0_4
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s13, s10
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v2, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v3, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ngt_f32_e32 0, v2
s_cbranch_execz .LBB0_11
s_mov_b32 s3, exec_lo
v_cmpx_lt_f32_e32 0x437f0000, v2
v_mov_b32_e32 v2, 0x437f0000
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v2
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v2, v3
v_ashrrev_i32_e32 v1, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22matrix_multiply_kernelPhS_Pfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22matrix_multiply_kernelPhS_Pfiiii, .Lfunc_end0-_Z22matrix_multiply_kernelPhS_Pfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22matrix_multiply_kernelPhS_Pfiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z22matrix_multiply_kernelPhS_Pfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000562ef_00000000-6_gaussian_blur_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
.type _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii, @function
_Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22matrix_multiply_kernelPhS_Pfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii, .-_Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
.globl _Z22matrix_multiply_kernelPhS_Pfiiii
.type _Z22matrix_multiply_kernelPhS_Pfiiii, @function
_Z22matrix_multiply_kernelPhS_Pfiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z22matrix_multiply_kernelPhS_Pfiiii, .-_Z22matrix_multiply_kernelPhS_Pfiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/seanjedi/ECS158Project4/master/gaussian_blur_cuda.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CudaError: %s %s %d\n"
.text
.globl _Z14multiplyKernalPhPfiii
.type _Z14multiplyKernalPhPfiii, @function
_Z14multiplyKernalPhPfiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edx, %ebp
imull %edx, %ebp
sall $2, %ebp
movl %ecx, %ebx
imull %r8d, %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movslq %ebp, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
leal 31(%r14), %eax
shrl $5, %eax
movl %eax, 60(%rsp)
leal 31(%r15), %eax
shrl $5, %eax
movl %eax, 64(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L18:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L34
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L35
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L37
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L38
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L39
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $68, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $69, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $70, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $72, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $73, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $74, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %r13d, %r8d
shrl $31, %r8d
addl %r13d, %r8d
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq %r15
.cfi_def_cfa_offset 160
movl %r14d, %r9d
sarl %r8d
movl %r13d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z50__device_stub__Z22matrix_multiply_kernelPhS_PfiiiiPhS_Pfiiii
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $80, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $81, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $84, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $86, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $87, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $88, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14multiplyKernalPhPfiii, .-_Z14multiplyKernalPhPfiii
.section .rodata.str1.8
.align 8
.LC3:
.string "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n"
.section .rodata.str1.1
.LC4:
.string "rb"
.LC5:
.string "Error: cannot open file %s\n"
.LC6:
.string "P5\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Error: invalid PGM information\n"
.section .rodata.str1.1
.LC8:
.string "%d"
.LC9:
.string "Error: invalid PGM pixels\n"
.LC10:
.string "Error: invalid sigma value\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Error: sigma value too big for image size\n"
.section .rodata.str1.1
.LC22:
.string "Running time: %f secs\n"
.LC23:
.string "%s"
.LC24:
.string "w+"
.LC25:
.string "%d %d\n"
.LC26:
.string "255\n"
.LC27:
.string "%c"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $440, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, -456(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $0, -380(%rbp)
movl $0, -376(%rbp)
cmpl $4, %edi
jne .L85
movq -456(%rbp), %rax
movq 8(%rax), %rdi
leaq .LC4(%rip), %rsi
call fopen@PLT
movq %rax, -448(%rbp)
testq %rax, %rax
je .L86
leaq -330(%rbp), %rdi
movq -448(%rbp), %rcx
movl $4, %edx
movl $10, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L87
leaq -330(%rbp), %rdi
leaq .LC6(%rip), %rsi
call strcmp@PLT
movl %eax, -436(%rbp)
testl %eax, %eax
jne .L88
leaq -380(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq -448(%rbp), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L46
leaq -376(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L46
movl -380(%rbp), %eax
orl -376(%rbp), %eax
je .L89
leaq -372(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq -448(%rbp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L90
cmpl $255, -372(%rbp)
jne .L91
movq -448(%rbp), %r15
movq %r15, %rdi
call getc@PLT
movslq -380(%rbp), %rbx
movslq -376(%rbp), %rax
imulq %rax, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %r8
movq %rbx, %rcx
movl $1, %edx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rax, %rdx
movl -380(%rbp), %eax
imull -376(%rbp), %eax
cmpq %rdx, %rax
jne .L92
movq -456(%rbp), %rax
movq 24(%rax), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L52
je .L93
.L52:
movaps %xmm0, %xmm1
mulss .LC11(%rip), %xmm1
movaps %xmm1, %xmm4
movss .LC28(%rip), %xmm3
movaps %xmm1, %xmm2
andps %xmm3, %xmm2
movss .LC12(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L54
cvttss2sil %xmm1, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC14(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm1, %xmm3
orps %xmm3, %xmm4
.L54:
cvttss2sil %xmm4, %edi
movl %edi, %eax
andl $1, %eax
cmpl $1, %eax
adcl $0, %edi
movl %edi, -392(%rbp)
cmpl %edi, -380(%rbp)
jl .L56
cmpl %edi, -376(%rbp)
jl .L56
movl -392(%rbp), %esi
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
movl %esi, %edx
imull %esi, %edx
movslq %edx, %rdx
leaq 15(,%rdx,4), %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L58:
cmpq %rcx, %rsp
je .L59
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L58
.L85:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movq -456(%rbp), %rax
movq 8(%rax), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L60
orq $0, -8(%rsp,%rdx)
.L60:
movq %rsp, %rdx
movq %rdx, -464(%rbp)
movl -392(%rbp), %esi
testl %esi, %esi
jle .L61
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LC16(%rip), %xmm1
movsd .LC17(%rip), %xmm2
divsd %xmm1, %xmm2
movsd %xmm2, -408(%rbp)
addsd %xmm0, %xmm0
movsd %xmm0, -416(%rbp)
movl %eax, %r15d
negl %r15d
movl %r15d, -440(%rbp)
movslq %esi, %rdi
movq %rdi, -472(%rbp)
salq $2, %rdi
movq %rdi, -424(%rbp)
subl %eax, %esi
movl %esi, %r13d
movq %rdx, -432(%rbp)
movl $0x00000000, -388(%rbp)
.L62:
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, -400(%rbp)
movq -432(%rbp), %r12
movl -440(%rbp), %ebx
.L63:
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
mulsd %xmm1, %xmm1
addsd -400(%rbp), %xmm1
divsd -416(%rbp), %xmm1
xorpd .LC18(%rip), %xmm1
movsd .LC19(%rip), %xmm0
call pow@PLT
mulsd -408(%rbp), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12)
addss -388(%rbp), %xmm0
movss %xmm0, -388(%rbp)
addl $1, %ebx
addq $4, %r12
cmpl %r13d, %ebx
jne .L63
addl $1, %r15d
movq -424(%rbp), %rdi
addq %rdi, -432(%rbp)
cmpl %r13d, %r15d
jne .L62
movq -464(%rbp), %rax
movq -424(%rbp), %rdi
leaq (%rax,%rdi), %rdx
movq -472(%rbp), %rsi
negq %rsi
salq $2, %rsi
movl -436(%rbp), %ecx
.L65:
leaq (%rdx,%rsi), %rax
.L66:
movss (%rax), %xmm0
divss -388(%rbp), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L66
addl $1, %ecx
movq -424(%rbp), %rax
addq %rax, %rdx
cmpl %ecx, -392(%rbp)
jne .L65
.L61:
leaq -368(%rbp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl -376(%rbp), %r8d
movl -380(%rbp), %ecx
movl -392(%rbp), %edx
movq -464(%rbp), %rsi
movq %r14, %rdi
call _Z14multiplyKernalPhPfiii
leaq -352(%rbp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq -352(%rbp), %rax
subq -368(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC20(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -344(%rbp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -360(%rbp), %xmm1
subsd %xmm1, %xmm0
comisd .LC21(%rip), %xmm0
jnb .L67
cvttsd2siq %xmm0, %rax
.L68:
testq %rax, %rax
js .L69
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L70:
divsd .LC20(%rip), %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq -320(%rbp), %rbx
movq -456(%rbp), %rax
movq 16(%rax), %r8
leaq .LC23(%rip), %rcx
movl $255, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl -376(%rbp), %r8d
movl -380(%rbp), %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC26(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl -436(%rbp), %r12d
leaq .LC27(%rip), %r15
cmpl $0, -376(%rbp)
jg .L71
.L72:
movq -448(%rbp), %rdi
call fclose@PLT
movq %r13, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L67:
.cfi_restore_state
subsd .LC21(%rip), %xmm0
cvttsd2siq %xmm0, %rax
btcq $63, %rax
jmp .L68
.L69:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L70
.L73:
imull %r12d, %eax
addl %ebx, %eax
cltq
movzbl (%r14,%rax), %ecx
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl -380(%rbp), %eax
cmpl %ebx, %eax
jg .L73
.L74:
addl $1, %r12d
cmpl %r12d, -376(%rbp)
jle .L72
.L71:
movl -380(%rbp), %eax
movl -436(%rbp), %ebx
testl %eax, %eax
jg .L73
jmp .L74
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC29:
.string "_Z22matrix_multiply_kernelPhS_Pfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrix_multiply_kernelPhS_Pfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1086324736
.align 4
.LC12:
.long 1258291200
.align 4
.LC14:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC16:
.long 1413754136
.long 1075388923
.align 8
.LC17:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC18:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC19:
.long -1961601175
.long 1074118410
.align 8
.LC20:
.long 0
.long 1104006501
.align 8
.LC21:
.long 0
.long 1138753536
.section .rodata.cst4
.align 4
.LC28:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gaussian_blur_cuda.hip"
.globl _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii # -- Begin function _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.p2align 4, 0x90
.type _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii,@function
_Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii: # @_Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22matrix_multiply_kernelPhS_Pfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii, .Lfunc_end0-_Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.cfi_endproc
# -- End function
.globl _Z14multiplyKernalPhPfiii # -- Begin function _Z14multiplyKernalPhPfiii
.p2align 4, 0x90
.type _Z14multiplyKernalPhPfiii,@function
_Z14multiplyKernalPhPfiii: # @_Z14multiplyKernalPhPfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
# kill: def $ecx killed $ecx def $rcx
movl %edx, %r13d
movq %rsi, %r12
movq %rdi, %rbp
movq %r8, 48(%rsp) # 8-byte Spill
movl %r8d, %eax
movq %rcx, 40(%rsp) # 8-byte Spill
imull %ecx, %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z11_cuda_check10hipError_tPKci.exit
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z11_cuda_check10hipError_tPKci.exit28
movl %r13d, %r15d
imull %r13d, %r13d
shll $2, %r13d
movslq %r13d, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z11_cuda_check10hipError_tPKci.exit30
movq 16(%rsp), %rdi
movq %rbp, %r13
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z11_cuda_check10hipError_tPKci.exit32
movq (%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z11_cuda_check10hipError_tPKci.exit34
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq 48(%rsp), %r13 # 8-byte Reload
jne .LBB1_12
# %bb.13: # %_Z11_cuda_check10hipError_tPKci.exit36
movq 40(%rsp), %r12 # 8-byte Reload
leal 31(%r12), %eax
shrl $5, %eax
leal 31(%r13), %edi
shrl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
movq 16(%rsp), %rcx
movq (%rsp), %rdx
movq 8(%rsp), %rsi
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movl %r15d, 36(%rsp)
movl %eax, 32(%rsp)
movl %r12d, 28(%rsp)
movl %r13d, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z22matrix_multiply_kernelPhS_Pfiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z11_cuda_check10hipError_tPKci.exit38
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z11_cuda_check10hipError_tPKci.exit40
movq (%rsp), %rsi
movq %rbp, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z11_cuda_check10hipError_tPKci.exit42
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z11_cuda_check10hipError_tPKci.exit44
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z11_cuda_check10hipError_tPKci.exit46
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z11_cuda_check10hipError_tPKci.exit48
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $70, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14multiplyKernalPhPfiii, .Lfunc_end1-_Z14multiplyKernalPhPfiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40c00000 # float 6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.LCPI2_2:
.quad 0x3ff0000000000000 # double 1
.LCPI2_4:
.quad 0x4005bf0a8b145769 # double 2.7182818284590451
.LCPI2_5:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_6:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_3:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.LCPI2_7:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_8:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $408, %rsp # imm = 0x198
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $0, -48(%rbp)
movl $0, -44(%rbp)
cmpl $4, %edi
jne .LBB2_1
# %bb.3:
movq %rsi, %r14
movq 8(%rsi), %rdi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_36
# %bb.4:
movq %rax, %rbx
leaq -154(%rbp), %rdi
movl $4, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB2_36
# %bb.5:
cmpl $669008, -154(%rbp) # imm = 0xA3550
jne .LBB2_6
# %bb.7:
leaq -48(%rbp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB2_36
# %bb.8:
leaq -44(%rbp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB2_36
# %bb.9:
movl -48(%rbp), %eax
orl -44(%rbp), %eax
je .LBB2_6
# %bb.10:
leaq -68(%rbp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
je .LBB2_36
# %bb.11:
cmpl $255, -68(%rbp)
jne .LBB2_6
# %bb.12:
movq %rbx, %rdi
callq getc
movslq -48(%rbp), %rax
movslq -44(%rbp), %r12
imulq %rax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %rbx, %rcx
callq fread
movl -44(%rbp), %ecx
imull -48(%rbp), %ecx
cmpq %rcx, %rax
jne .LBB2_13
# %bb.14:
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
jne .LBB2_16
jnp .LBB2_15
.LBB2_16:
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm1, -52(%rbp) # 4-byte Spill
mulss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edx
movl %edx, %edi
orl $1, %edi
cmpl -48(%rbp), %edi
jg .LBB2_18
# %bb.17:
cmpl -44(%rbp), %edi
jg .LBB2_18
# %bb.19:
movq %r15, -88(%rbp) # 8-byte Spill
movq %r14, -96(%rbp) # 8-byte Spill
movq %rbx, -104(%rbp) # 8-byte Spill
movq %rsp, -80(%rbp) # 8-byte Spill
movl %edi, %eax
imull %eax, %eax
leaq 15(,%rax,4), %rax
movabsq $17179869168, %rcx # imm = 0x3FFFFFFF0
andq %rax, %rcx
movq %rsp, %r15
subq %rcx, %r15
movq %r15, %rsp
movl %edi, %r14d
testl %edx, %edx
movl %edx, -56(%rbp) # 4-byte Spill
js .LBB2_20
# %bb.32: # %.preheader101.lr.ph
shrl %edx
movss -52(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm2
mulsd %xmm2, %xmm2
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
movsd .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero
divsd %xmm0, %xmm3
addsd %xmm2, %xmm2
movl %edx, -60(%rbp) # 4-byte Spill
movl %edx, %ebx
negl %ebx
xorps %xmm1, %xmm1
xorl %eax, %eax
movapd .LCPI2_3(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0]
movsd .LCPI2_4(%rip), %xmm4 # xmm4 = mem[0],zero
xorl %r13d, %r13d
movl %edi, -64(%rbp) # 4-byte Spill
movq %r15, -112(%rbp) # 8-byte Spill
movsd %xmm2, -136(%rbp) # 8-byte Spill
movsd %xmm3, -128(%rbp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_33: # %.preheader101
# =>This Loop Header: Depth=1
# Child Loop BB2_34 Depth 2
movq %rax, -120(%rbp) # 8-byte Spill
movl %eax, %eax
leaq (%r15,%rax,4), %r15
movl %r13d, %eax
subl -60(%rbp), %eax # 4-byte Folded Reload
xorps %xmm5, %xmm5
cvtsi2sd %eax, %xmm5
mulsd %xmm5, %xmm5
movsd %xmm5, -144(%rbp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_34: # Parent Loop BB2_33 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, -52(%rbp) # 4-byte Spill
leal (%rbx,%r12), %eax
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm1, %xmm1
addsd -144(%rbp), %xmm1 # 8-byte Folded Reload
xorpd %xmm0, %xmm1
divsd %xmm2, %xmm1
movapd %xmm4, %xmm0
callq pow
movsd .LCPI2_4(%rip), %xmm4 # xmm4 = mem[0],zero
movsd -128(%rbp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd -136(%rbp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movss -52(%rbp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulsd %xmm3, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
addss %xmm0, %xmm1
movapd .LCPI2_3(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0]
incq %r12
cmpq %r12, %r14
jne .LBB2_34
# %bb.35: # %._crit_edge
# in Loop: Header=BB2_33 Depth=1
incq %r13
movl -64(%rbp), %edi # 4-byte Reload
movq -120(%rbp), %rax # 8-byte Reload
addl %edi, %eax
cmpq %r14, %r13
movq -112(%rbp), %r15 # 8-byte Reload
jne .LBB2_33
jmp .LBB2_21
.LBB2_20:
xorps %xmm1, %xmm1
.LBB2_21: # %.preheader100
cmpl $0, -56(%rbp) # 4-byte Folded Reload
movq -96(%rbp), %rbx # 8-byte Reload
movq -88(%rbp), %r12 # 8-byte Reload
js .LBB2_26
# %bb.22: # %.preheader99.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_23: # %.preheader99
# =>This Loop Header: Depth=1
# Child Loop BB2_24 Depth 2
movl %eax, %edx
leaq (%r15,%rdx,4), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_24: # Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
cmpq %rsi, %r14
jne .LBB2_24
# %bb.25: # %._crit_edge109
# in Loop: Header=BB2_23 Depth=1
incq %rcx
addl %edi, %eax
cmpq %r14, %rcx
jne .LBB2_23
.LBB2_26: # %._crit_edge111
leaq -192(%rbp), %rsi
movl %edi, %r14d
movl $1, %edi
callq clock_gettime
movl -48(%rbp), %ecx
movl -44(%rbp), %r8d
movq %r12, %rdi
movq %r15, %rsi
movl %r14d, %edx
callq _Z14multiplyKernalPhPfiii
leaq -176(%rbp), %rsi
movl $1, %edi
callq clock_gettime
movq -176(%rbp), %rax
subq -192(%rbp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI2_5(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm2, %xmm2
cvtsi2sdq -168(%rbp), %xmm2
mulsd %xmm1, %xmm0
addsd %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2sdq -184(%rbp), %xmm0
subsd %xmm0, %xmm2
cvttsd2si %xmm2, %rax
movq %rax, %rcx
subsd .LCPI2_6(%rip), %xmm2
cvttsd2si %xmm2, %rdx
sarq $63, %rcx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, %xmm2
punpckldq .LCPI2_7(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI2_8(%rip), %xmm2
movapd %xmm2, %xmm0
unpckhpd %xmm2, %xmm0 # xmm0 = xmm0[1],xmm2[1]
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 16(%rbx), %rsi
leaq -448(%rbp), %r14
movq %r14, %rdi
callq strcpy@PLT
movl $.L.str.12, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
movl $.L.str.4, %edi
movl $3, %esi
movl $1, %edx
movq %rax, %rcx
callq fwrite@PLT
movl -48(%rbp), %edx
movl -44(%rbp), %ecx
xorl %ebx, %ebx
movl $.L.str.13, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
movl $.L.str.14, %edi
movl $4, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite@PLT
cmpl $0, -44(%rbp)
jg .LBB2_27
.LBB2_31: # %._crit_edge116
movq -104(%rbp), %rdi # 8-byte Reload
callq fclose
movq %r14, %rdi
callq fclose
movq %r12, %rdi
callq free
movq -80(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.p2align 4, 0x90
.LBB2_30: # %._crit_edge114
# in Loop: Header=BB2_27 Depth=1
.cfi_def_cfa %rbp, 16
incl %ebx
cmpl -44(%rbp), %ebx
jge .LBB2_31
.LBB2_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_29 Depth 2
movl -48(%rbp), %eax
testl %eax, %eax
jle .LBB2_30
# %bb.28: # %.lr.ph113.preheader
# in Loop: Header=BB2_27 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_29: # %.lr.ph113
# Parent Loop BB2_27 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebx, %eax
cltq
addq %r12, %rax
movzbl (%r15,%rax), %edi
movq %r14, %rsi
callq fputc@PLT
movl -48(%rbp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB2_29
jmp .LBB2_30
.LBB2_36:
movq stderr(%rip), %rdi
movq 8(%r14), %rdx
movl $.L.str.3, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_6:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $31, %esi
jmp .LBB2_2
.LBB2_1:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $63, %esi
jmp .LBB2_2
.LBB2_13:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $26, %esi
jmp .LBB2_2
.LBB2_15:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $27, %esi
jmp .LBB2_2
.LBB2_18:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $42, %esi
.LBB2_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matrix_multiply_kernelPhS_Pfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22matrix_multiply_kernelPhS_Pfiiii,@object # @_Z22matrix_multiply_kernelPhS_Pfiiii
.section .rodata,"a",@progbits
.globl _Z22matrix_multiply_kernelPhS_Pfiiii
.p2align 3, 0x0
_Z22matrix_multiply_kernelPhS_Pfiiii:
.quad _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.size _Z22matrix_multiply_kernelPhS_Pfiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/seanjedi/ECS158Project4/master/gaussian_blur_cuda.hip"
.size .L.str, 111
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: ./gaussian_blur_cuda <input_file> <output_file> <sigma>\n"
.size .L.str.1, 64
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "rb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error: cannot open file %s\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P5\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error: invalid PGM information\n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error: invalid PGM pixels\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: invalid sigma value\n"
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error: sigma value too big for image size\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Running time: %f secs\n"
.size .L.str.10, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "w+"
.size .L.str.12, 3
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d %d\n"
.size .L.str.13, 7
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "255\n"
.size .L.str.14, 5
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "CudaError: %s %s %d\n"
.size .L.str.16, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22matrix_multiply_kernelPhS_Pfiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__matrix_multiply_kernelPhS_Pfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22matrix_multiply_kernelPhS_Pfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void grayscaleVer2D(uchar3* input, uchar3* output, int imageWidth, int imageHeight){
int tid_x = threadIdx.x + blockIdx.x * blockDim.x;
int tid_y = threadIdx.y + blockIdx.y * blockDim.y;
if(tid_x > imageWidth || tid_y > imageHeight) return;
int tid = (int)(tid_x + tid_y * imageWidth);
output[tid].x = (input[tid].x + input[tid].y + input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | code for sm_80
Function : _Z14grayscaleVer2DP6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00e0*/ LDG.E.U8 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1100 */
/*00f0*/ LDG.E.U8 R5, [R2.64+0x1] ; /* 0x0000010402057981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea4000c1e1100 */
/*0110*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x004fe20007ffe004 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0207 */
/*0130*/ IMAD.WIDE.U32 R4, R4, -0x55555555, RZ ; /* 0xaaaaaaab04047825 */
/* 0x000fca00078e00ff */
/*0140*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011605 */
/*0150*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe8000c101104 */
/*0160*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*0170*/ STG.E.U8 [R6.64+0x2], R5 ; /* 0x0000020506007986 */
/* 0x000fe2000c101104 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void grayscaleVer2D(uchar3* input, uchar3* output, int imageWidth, int imageHeight){
int tid_x = threadIdx.x + blockIdx.x * blockDim.x;
int tid_y = threadIdx.y + blockIdx.y * blockDim.y;
if(tid_x > imageWidth || tid_y > imageHeight) return;
int tid = (int)(tid_x + tid_y * imageWidth);
output[tid].x = (input[tid].x + input[tid].y + input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | .file "tmpxft_00003a60_00000000-6_grayscaleVer2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii
.type _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii, @function
_Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14grayscaleVer2DP6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii, .-_Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii
.globl _Z14grayscaleVer2DP6uchar3S0_ii
.type _Z14grayscaleVer2DP6uchar3S0_ii, @function
_Z14grayscaleVer2DP6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14grayscaleVer2DP6uchar3S0_ii, .-_Z14grayscaleVer2DP6uchar3S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14grayscaleVer2DP6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14grayscaleVer2DP6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void grayscaleVer2D(uchar3* input, uchar3* output, int imageWidth, int imageHeight){
int tid_x = threadIdx.x + blockIdx.x * blockDim.x;
int tid_y = threadIdx.y + blockIdx.y * blockDim.y;
if(tid_x > imageWidth || tid_y > imageHeight) return;
int tid = (int)(tid_x + tid_y * imageWidth);
output[tid].x = (input[tid].x + input[tid].y + input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void grayscaleVer2D(uchar3* input, uchar3* output, int imageWidth, int imageHeight){
int tid_x = threadIdx.x + blockIdx.x * blockDim.x;
int tid_y = threadIdx.y + blockIdx.y * blockDim.y;
if(tid_x > imageWidth || tid_y > imageHeight) return;
int tid = (int)(tid_x + tid_y * imageWidth);
output[tid].x = (input[tid].x + input[tid].y + input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void grayscaleVer2D(uchar3* input, uchar3* output, int imageWidth, int imageHeight){
int tid_x = threadIdx.x + blockIdx.x * blockDim.x;
int tid_y = threadIdx.y + blockIdx.y * blockDim.y;
if(tid_x > imageWidth || tid_y > imageHeight) return;
int tid = (int)(tid_x + tid_y * imageWidth);
output[tid].x = (input[tid].x + input[tid].y + input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.globl _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii,@function
_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_ge_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[0:1], null, v2, 3, s[0:1]
s_clause 0x2
global_load_u8 v3, v[0:1], off
global_load_u8 v4, v[0:1], off offset:1
global_load_u8 v0, v[0:1], off offset:2
s_waitcnt vmcnt(1)
v_add_nc_u16 v1, v4, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v0, v1, v0
v_and_b32_e32 v0, 0xffff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v3, 0x5556, v0
v_mad_i64_i32 v[0:1], null, v2, 3, s[2:3]
v_lshrrev_b32_e32 v2, 16, v3
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v2, off offset:2
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void grayscaleVer2D(uchar3* input, uchar3* output, int imageWidth, int imageHeight){
int tid_x = threadIdx.x + blockIdx.x * blockDim.x;
int tid_y = threadIdx.y + blockIdx.y * blockDim.y;
if(tid_x > imageWidth || tid_y > imageHeight) return;
int tid = (int)(tid_x + tid_y * imageWidth);
output[tid].x = (input[tid].x + input[tid].y + input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | .text
.file "grayscaleVer2D.hip"
.globl _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.p2align 4, 0x90
.type _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii,@function
_Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii: # @_Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii:
.quad _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.size _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14grayscaleVer2DP6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00e0*/ LDG.E.U8 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1100 */
/*00f0*/ LDG.E.U8 R5, [R2.64+0x1] ; /* 0x0000010402057981 */
/* 0x000ea8000c1e1100 */
/*0100*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea4000c1e1100 */
/*0110*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x004fe20007ffe004 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0207 */
/*0130*/ IMAD.WIDE.U32 R4, R4, -0x55555555, RZ ; /* 0xaaaaaaab04047825 */
/* 0x000fca00078e00ff */
/*0140*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011605 */
/*0150*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe8000c101104 */
/*0160*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*0170*/ STG.E.U8 [R6.64+0x2], R5 ; /* 0x0000020506007986 */
/* 0x000fe2000c101104 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.globl _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii,@function
_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_ge_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[0:1], null, v2, 3, s[0:1]
s_clause 0x2
global_load_u8 v3, v[0:1], off
global_load_u8 v4, v[0:1], off offset:1
global_load_u8 v0, v[0:1], off offset:2
s_waitcnt vmcnt(1)
v_add_nc_u16 v1, v4, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v0, v1, v0
v_and_b32_e32 v0, 0xffff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v3, 0x5556, v0
v_mad_i64_i32 v[0:1], null, v2, 3, s[2:3]
v_lshrrev_b32_e32 v2, 16, v3
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v2, off offset:2
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003a60_00000000-6_grayscaleVer2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii
.type _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii, @function
_Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14grayscaleVer2DP6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii, .-_Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii
.globl _Z14grayscaleVer2DP6uchar3S0_ii
.type _Z14grayscaleVer2DP6uchar3S0_ii, @function
_Z14grayscaleVer2DP6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14grayscaleVer2DP6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14grayscaleVer2DP6uchar3S0_ii, .-_Z14grayscaleVer2DP6uchar3S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14grayscaleVer2DP6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14grayscaleVer2DP6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grayscaleVer2D.hip"
.globl _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.p2align 4, 0x90
.type _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii,@function
_Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii: # @_Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii:
.quad _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.size _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14grayscaleVer2DP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
/*Kernel for matrix outer product*/
__global__
void k_gemm_f32(float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c){
const int TILE_WIDTH=16;
const int VEC_SIZE=4; //multiplies TILE_WIDTH for the b row vectors. 4 means one thread calculated C's entries with a rowlength of 4*16=64 numbers in B. Must be multiple of TILE_WIDTH
float Cc[TILE_WIDTH]={0}; //initializes all elements to zero
__shared__ float Ac[TILE_WIDTH*TILE_WIDTH]; //buffer that holds columns of a
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int a_begin=by*TILE_WIDTH*stride_col_a;
int a_end=a_begin+stride_col_a;//check if correct
int b_begin=bx*TILE_WIDTH*VEC_SIZE*stride_row_b; //we multiply by VEC_SIZE because B's tiles have length TILEWIDTH*VEC_SIZE
for (;a_begin < a_end;a_begin+=TILE_WIDTH*stride_row_a){
//Load elements of A into shared memory
for (int i=0; i< 4;i++){
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
}
__syncthreads();
const float* ptrB=&B[b_begin+(TILE_WIDTH*ty+tx)*stride_row_b];
float* ptrA=Ac;
#pragma unroll
for (int i=0;i<TILE_WIDTH;i++){
float bv=alpha*ptrB[0];
//this loop could be unrolled
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]+=ptrA[j]*bv;
}
ptrA+=TILE_WIDTH; //next column of A (it is the next column because Ac is a transposed block of A)
ptrB+=stride_col_b;
}
b_begin+=TILE_WIDTH*stride_col_b;
__syncthreads();
}
int c=stride_col_c*TILE_WIDTH*by+(TILE_WIDTH*VEC_SIZE*bx+tx+TILE_WIDTH*ty)*stride_row_c;
for (int i=0;i<TILE_WIDTH;i++){
C[c]+=Cc[i];
c+=stride_col_c;
}
}
//Todo!!
/*Kernel for matrix outer product. This version does not require A,B,C to be multiples of the blocksizes*/
__global__
void k_gemm_f32_nonblockmultiple(const int m, const int n, const int k,float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c){
const int TILE_WIDTH=16;
const int VEC_SIZE=4; //multiplies TILE_WIDTH for the b row vectors. 4 means one thread calculated with a rowlength of 4*16=64 numbers in B. Must be multiple of TILE_WIDTH
float Cc[TILE_WIDTH]={0}; //initializes all elements to zero
__shared__ float Ac[TILE_WIDTH*TILE_WIDTH]; //buffer that holds columns of a
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int qm=m%TILE_WIDTH;
//int qn=(VEC_SIZE*TILE_WIDTH)%n;
int qk=k%TILE_WIDTH;
int rowA=by*TILE_WIDTH;
int colB=bx*TILE_WIDTH*VEC_SIZE+TILE_WIDTH*ty+tx;
int a_begin=by*TILE_WIDTH*stride_col_a;
int b_begin=bx*TILE_WIDTH*VEC_SIZE*stride_row_b; //we multiply by VEC_SIZE because B's tiles have length TILEWIDTH*VEC_SIZE
bool does_compute=false;
//printf("qk:%d\n",qk);
int rk=k/TILE_WIDTH;
for (int q=0;q<rk;q++){
//Load elements of A into shared memory
//printf("i: %d\n",a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a);
if ((tx<k)&&((rowA+TILE_WIDTH-1)<m)){
for (int i=0; i< 4;i++){
//printf("Aci: %d, i: %d and A:%f\n",i*4+ty+TILE_WIDTH*tx,a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a,A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a]);
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
}
}
else{
for (int i=0; i< 4;i++){
if((rowA+i*4+ty)<m && (tx<k)){
//printf("is: %f\n",A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a]);
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
// printf("is:Ac index: %d, index: %d and A:%f\n",i*4+ty+TILE_WIDTH*tx,a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a,A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a]);
}
else{
Ac[i*4+ty+TILE_WIDTH*tx]=0.0;
}
}
}
/*
for (int i=0;i<TILE_WIDTH*TILE_WIDTH;i++){
Ac[i]=-7;
}
*/
__syncthreads();
/*
if (tx==0 && ty==0){
for (int i=0;i<TILE_WIDTH*TILE_WIDTH;i++){
printf("%f\t",Ac[i]);
}
}
*/
if (colB>=n){
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]=0.0;
}
}
else{
//printf("Id: %d,%d,%d,%d\n",by,ty,bx,tx);
const float* ptrB=&B[b_begin+(TILE_WIDTH*ty+tx)*stride_row_b];
float* ptrA=Ac;
does_compute=true;
#pragma unroll
for (int i=0;i<TILE_WIDTH;i++){
float bv=alpha*ptrB[0];
//this loop could be unrolled
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]+=ptrA[j]*bv;
/* if (ptrA[j]!=0){
printf("%f vs. %f\n",ptrA[j],bv);
}
*/
}
ptrA+=TILE_WIDTH; //next column of A (it is the next column because Ac is a transposed block of A)
ptrB+=stride_col_b;
}
b_begin+=TILE_WIDTH*stride_col_b;
}
a_begin+=TILE_WIDTH*stride_row_a;
__syncthreads();
}
if (qk>0){
if (tx<qk){
//printf("rowA:%d, ty:%d\n",rowA,ty);
a_begin=(by*TILE_WIDTH*stride_col_a)+rk*TILE_WIDTH*stride_row_a;
for (int i=0; i< 4;i++){
if((rowA+i*4+ty)<m){
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
//printf("Ac index2: %d, index: %d and \n",i*4+ty+TILE_WIDTH*tx,a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a);
}
else{
Ac[i*4+ty+TILE_WIDTH*tx]=0.0;
}
}
}
else{
for (int i=0; i< 4;i++){
Ac[i*4+ty+TILE_WIDTH*tx]=0.0;
}
}
__syncthreads();
//return;
if (colB<n){
// printf("Id: %d,%d,%d,%d\n",by,ty,bx,tx);
const float* ptrB=&B[b_begin+(TILE_WIDTH*ty+tx)*stride_row_b];
float* ptrA=Ac;
does_compute=true;
for (int i=0;i<qk;i++){
float bv=alpha*ptrB[0];
//this loop could be unrolled
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]+=ptrA[j]*bv;
/*if (ptrA[j]!=0){
printf("%f vs2. %f\n",ptrA[j],bv);
}
*/
}
ptrA+=TILE_WIDTH; //next column of A (it is the next column because Ac is a transposed block of A)
ptrB+=stride_col_b;
}
}
}
__syncthreads(); //maybe redundant
if (does_compute){
int c=stride_col_c*TILE_WIDTH*by+(TILE_WIDTH*VEC_SIZE*bx+tx+TILE_WIDTH*ty)*stride_row_c;
int c_length=((rowA+TILE_WIDTH)<=m)?TILE_WIDTH:qm;
for (int i=0;i<c_length;i++){
C[c]+=Cc[i];
c+=stride_col_c;
}
}
}
__global__
void k_scal_f32(int m, int n, float beta, float* C, int stride_row_c, int stride_col_c){
const int BLOCK_WIDTH=256; //size of a block
const int TILE_WIDTH=64; //size of block per single thread
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
//printf("Bin drin mit : bx %d, tx %d, by %d, ty %d \n",bx,tx,by,ty);
float* c_begin=&C[(by*BLOCK_WIDTH+ty*TILE_WIDTH)*stride_col_c+(bx*BLOCK_WIDTH+tx*TILE_WIDTH)*stride_row_c];
if ((((by+1)*BLOCK_WIDTH)<=m) && (((bx+1)*BLOCK_WIDTH)<=n)){
for (int i=0;i<TILE_WIDTH;i++){
for (int j=0;j<TILE_WIDTH;j++){
c_begin[i*stride_col_c+j*stride_row_c]*=beta;
}
}
}
else{
int column=by*BLOCK_WIDTH+ty*TILE_WIDTH;
for (int i=0;i<TILE_WIDTH;i++){
if (column<m){
int row=bx*BLOCK_WIDTH+tx*TILE_WIDTH;
for (int j=0;j<TILE_WIDTH;j++){
if (row<n){
c_begin[i*stride_col_c+j*stride_row_c]*=beta;
//printf("Bin hier drin mit %d und %d mit by %d ty %d bx %d tx %d\n",i,j,by,ty,bx,tx);
}
row=row+1;
}
}
column=column+1;
}
}
}
//matrix matrix multiplication
__host__
void gemm_f32_blockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h){
float* A_d;
float* B_d;
float* C_d;
int sizeA=sizeof(float)*m*k;
int sizeB=sizeof(float)*n*k;
int sizeC=sizeof(float)*m*n;
float bsmx=16;
float bsmy=4;
dim3 threadLayout=dim3(bsmx,bsmy,1);
dim3 grid=dim3(ceil(n/(4.0*bsmx)),ceil(m/bsmx),1);
cudaMalloc((void**) &C_d,sizeC);
if (beta==0){
cudaMemset(C_d, 0, sizeC);
}
else{
cudaMemcpy((void*) C_d, (void*) C_h, sizeC,cudaMemcpyHostToDevice);
k_scal_f32<<<grid,threadLayout>>>(m,n,beta,C_d,1,n);
}
if (alpha!=0.0){
cudaMalloc((void**) &A_d,sizeA);
cudaMalloc((void**) &B_d,sizeB);
cudaError_t copy1=cudaMemcpy((void*) A_d, (void*) A_h, sizeA, cudaMemcpyHostToDevice);
cudaError_t copy2=cudaMemcpy((void*) B_d, (void*) B_h, sizeB, cudaMemcpyHostToDevice);
if ((copy1==cudaSuccess)&& (copy2==cudaSuccess)){
k_gemm_f32<<<grid,threadLayout>>> (alpha, A_d, 1, k,B_d,1,n,C_d,1,n);
cudaMemcpy((void*) C_h, (void*) C_d, sizeC, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
}
}
cudaFree(C_d);
}
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
__host__
void gemm_f32_nonblockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h){
float* A_d;
float* B_d;
float* C_d;
float bsmx=16; //blocksize x
float bsmy=4; //blocksize y
int mB=ceil(m/bsmx)*bsmx;
int nB=ceil(n/(4.0*bsmx))*(4.0*bsmx);
int kB=ceil(k/bsmx)*bsmx;
int sizeCb=sizeof(float)*mB*nB;
cudaMalloc((void**) &C_d, sizeCb);
dim3 threadLayout=dim3(bsmx,bsmy,1);
dim3 grid=dim3(ceil(nB/(4.0*bsmx)),ceil(mB/bsmx),1);
if (beta==0){
cudaMemset(C_d, 0, sizeCb);
}
else{
cudaError_t copy;
for (int i=0;i<m;i++){
copy=cudaMemcpy((void*) (C_d+i*nB), (void*) (C_h+i*n), sizeof(float)*n,cudaMemcpyHostToDevice);
}
if (copy!=cudaSuccess){
printf("Copy fehlgeschlagen\n");
}
// printf("Starte nun den Kernel\n");
dim3 threadsize=dim3(4,4,1);
dim3 blocksize=dim3(ceil(n/256.0),ceil(m/256.0),1);
k_scal_f32<<<blocksize,threadsize>>>(m,n,beta,C_d,1,nB);
//cudaDeviceSynchronize();
}
if (alpha!=0.0){
int sizeAb=sizeof(float)*mB*kB;
int sizeBb=sizeof(float)*kB*nB;
cudaMalloc((void**) &A_d,sizeAb);
cudaMalloc((void**) &B_d,sizeBb);
cudaMemset(A_d,0.0,sizeAb);
cudaMemset(B_d,0.0,sizeBb);
cudaError_t copy1;
cudaError_t copy2;
for (int i=0;i<m;i++){
copy1=cudaMemcpy((void*) (A_d+i*kB), (void*) (A_h+i*k), sizeof(float)*k,cudaMemcpyHostToDevice);
}
for (int i=0;i<k;i++){
copy2=cudaMemcpy((void*) (B_d+i*nB), (void*) (B_h+i*n), sizeof(float)*n, cudaMemcpyHostToDevice);
}
if ((copy1==cudaSuccess)&& (copy2==cudaSuccess)){
k_gemm_f32<<<grid,threadLayout>>> (alpha, A_d, 1, kB,B_d,1,nB,C_d,1,nB);
cudaFree(A_d);
cudaFree(B_d);
}
}
for (int i=0;i<m;i++){
cudaError_t copy=cudaMemcpy((void*) (C_h+i*n), (void*) (C_d+i*nB),sizeof(float)*n,cudaMemcpyDeviceToHost);
if (copy!=cudaSuccess){
printf("Copy fehlgeschlagen\n");
}
}
cudaFree(C_d);
}
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
__host__
void gemm_f32(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h){
if ((alpha==0.0) && (beta==1.0)){
return;
}
int res1=m%16;
int res2=n/(4*4);
if ((res1==0)&&(res2==0)){
gemm_f32_blockmultiple(m,n,k,alpha,A_h,B_h,beta,C_h);
}
else{
// printf("nonblockmultiple\n");
gemm_f32_nonblockmultiple(m,n,k,alpha,A_h,B_h,beta,C_h);
}
}
//General matrix-to-matrix multiplication for 32 bit floats. This assumes that the input parameters are already allocated in device memory
__host__
void gemm_f32_device(int m, int n, int k, float alpha, const float* A_d, int stride_row_a, int stride_col_a, const float* B_d, int stride_row_b, int stride_col_b, float beta, float* C_d,int stride_row_c, int stride_col_c){
if ((alpha==0.0) && (beta==1.0)){
return;
}
float bsmx=16;
float bsmy=4;
dim3 threadLayout=dim3(bsmx,bsmy,1);
dim3 grid=dim3(ceil(n/(4.0*bsmx)),ceil(m/bsmx),1);
k_scal_f32<<<grid,threadLayout>>>(m,n,beta,C_d,stride_row_c,stride_col_c);
if (alpha!=0){
int res1=m%(int)bsmx;
int res2=n%(int)bsmx;
if ((res1==0)&&(res2==0)){
// printf("gemm blockmultiple\n");
k_gemm_f32<<<grid,threadLayout>>>(alpha, A_d, stride_row_a, stride_col_a,B_d,stride_row_b,stride_col_b,C_d,stride_row_c,stride_col_c);
}
else{
//printf("gemm nonblockmultiple\n");
k_gemm_f32_nonblockmultiple<<<grid,threadLayout>>>(m,n,k,alpha, A_d, stride_row_a, stride_col_a,B_d,stride_row_b,stride_col_b,C_d,stride_row_c,stride_col_c);
}
}
} | .file "tmpxft_0004b365_00000000-6_gemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
.type _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii, @function
_Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movq %rdi, 32(%rsp)
movl %esi, 40(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 12(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10k_gemm_f32fPKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii, .-_Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
.globl _Z10k_gemm_f32fPKfiiS0_iiPfii
.type _Z10k_gemm_f32fPKfiiS0_iiPfii, @function
_Z10k_gemm_f32fPKfiiS0_iiPfii:
.LFB2086:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10k_gemm_f32fPKfiiS0_iiPfii, .-_Z10k_gemm_f32fPKfiiS0_iiPfii
.globl _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
.type _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii, @function
_Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii:
.LFB2087:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 248(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii, .-_Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
.globl _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii
.type _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii, @function
_Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii, .-_Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii
.globl _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
.type _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii, @function
_Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10k_scal_f32iifPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii, .-_Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
.globl _Z10k_scal_f32iifPfii
.type _Z10k_scal_f32iifPfii, @function
_Z10k_scal_f32iifPfii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z10k_scal_f32iifPfii, .-_Z10k_scal_f32iifPfii
.globl _Z15gemm_f32_deviceiiifPKfiiS0_iifPfii
.type _Z15gemm_f32_deviceiiifPKfiiS0_iifPfii, @function
_Z15gemm_f32_deviceiiifPKfiiS0_iifPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r15d
movaps %xmm0, %xmm6
movss %xmm0, 8(%rsp)
movq %rcx, %r12
movl %r8d, %r13d
movl %r9d, %r14d
movss %xmm1, 12(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm0, %xmm6
setnp %al
movl $0, %edx
cmovne %edx, %eax
testb %al, %al
je .L36
ucomiss .LC1(%rip), %xmm1
setnp %al
cmovne %edx, %eax
testb %al, %al
je .L36
.L27:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $16, 24(%rsp)
movl $4, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L30
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L30:
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L31
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L31:
cvttsd2siq %xmm4, %rax
movl %eax, 36(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
pxor %xmm0, %xmm0
movss 8(%rsp), %xmm7
ucomiss %xmm0, %xmm7
jp .L37
je .L27
.L37:
movl %ebx, %edx
sarl $31, %edx
shrl $28, %edx
leal (%rbx,%rdx), %eax
andl $15, %eax
subl %edx, %eax
movl %ebp, %ecx
sarl $31, %ecx
shrl $28, %ecx
leal 0(%rbp,%rcx), %edx
andl $15, %edx
subl %ecx, %edx
orl %edx, %eax
jne .L35
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
subq $8, %rsp
.cfi_def_cfa_offset 120
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
pushq 160(%rsp)
.cfi_def_cfa_offset 144
movl 160(%rsp), %r9d
movl 152(%rsp), %r8d
movq 144(%rsp), %rcx
movl %r14d, %edx
movl %r13d, %esi
movq %r12, %rdi
movss 40(%rsp), %xmm0
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $32, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L39:
movl 152(%rsp), %r8d
movl 144(%rsp), %ecx
movq 136(%rsp), %rdx
movss 12(%rsp), %xmm0
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
jmp .L32
.L35:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
pushq 152(%rsp)
.cfi_def_cfa_offset 136
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
pushq 152(%rsp)
.cfi_def_cfa_offset 160
movl %r14d, %r9d
movl %r13d, %r8d
movq %r12, %rcx
movss 56(%rsp), %xmm0
movl %r15d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
addq $48, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.cfi_endproc
.LFE2060:
.size _Z15gemm_f32_deviceiiifPKfiiS0_iifPfii, .-_Z15gemm_f32_deviceiiifPKfiiS0_iifPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "Copy fehlgeschlagen\n"
.text
.globl _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf
.type _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf, @function
_Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %r15d
movl %esi, 16(%rsp)
movl %edx, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 64(%rsp)
movss %xmm1, 36(%rsp)
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L41
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L41:
mulss .LC11(%rip), %xmm1
cvttss2sil %xmm1, %eax
movl %eax, 32(%rsp)
pxor %xmm6, %xmm6
cvtsi2sdl 16(%rsp), %xmm6
movsd %xmm6, 48(%rsp)
movapd %xmm6, %xmm2
mulsd .LC5(%rip), %xmm2
movapd %xmm2, %xmm0
movsd .LC10(%rip), %xmm3
movapd %xmm2, %xmm1
andpd %xmm3, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L42
cvttsd2siq %xmm2, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm0
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm0
addsd %xmm1, %xmm0
andnpd %xmm2, %xmm3
orpd %xmm3, %xmm0
.L42:
mulsd .LC12(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 20(%rsp)
movslq %eax, %rdx
movq %rdx, 8(%rsp)
movl 32(%rsp), %r14d
movl %r14d, %ebx
imull %eax, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $16, 96(%rsp)
movl $4, 100(%rsp)
movl $1, 104(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L43
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L43:
pxor %xmm0, %xmm0
cvtsi2sdl 20(%rsp), %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L44
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L44:
cvttsd2siq %xmm4, %rax
movl %eax, 108(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
pxor %xmm0, %xmm0
movss 36(%rsp), %xmm7
ucomiss %xmm0, %xmm7
jp .L67
je .L45
.L67:
testl %r15d, %r15d
jle .L48
movslq 16(%rsp), %r13
salq $2, %r13
movq 8(%rsp), %rax
leaq 0(,%rax,4), %r14
movq 24(%rsp), %r12
movl $0, %ebp
movl $0, %ebx
.L50:
movq %rbp, %rdi
addq 88(%rsp), %rdi
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
call cudaMemcpy@PLT
addl $1, %ebx
addq %r14, %rbp
addq %r13, %r12
cmpl %ebx, %r15d
jne .L50
movl %eax, %ebp
.L48:
testl %ebp, %ebp
jne .L74
.L51:
movl $4, 120(%rsp)
movl $4, 124(%rsp)
movl $1, 128(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC14(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L52
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L52:
movsd 48(%rsp), %xmm0
mulsd .LC14(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L53
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L53:
cvttsd2siq %xmm4, %rax
movl %eax, 136(%rsp)
cvttsd2siq %xmm1, %rax
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl 128(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 120(%rsp), %rdx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L49:
pxor %xmm0, %xmm0
movss 40(%rsp), %xmm5
ucomiss %xmm0, %xmm5
jp .L68
jne .L68
.L55:
testl %r15d, %r15d
jle .L63
movslq 16(%rsp), %r13
salq $2, %r13
movq 8(%rsp), %r14
salq $2, %r14
movq 24(%rsp), %rbx
movl $0, %r12d
movl $0, %ebp
jmp .L65
.L45:
movq %rbx, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
jmp .L49
.L74:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L75:
movl 20(%rsp), %r8d
movl $1, %ecx
movq 88(%rsp), %rdx
movss 36(%rsp), %xmm0
movl 16(%rsp), %esi
movl %r15d, %edi
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
jmp .L49
.L68:
pxor %xmm0, %xmm0
cvtsi2ssl 44(%rsp), %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L57
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L57:
mulss .LC11(%rip), %xmm1
cvttss2sil %xmm1, %r12d
movl %r12d, 36(%rsp)
movslq %r12d, %r14
movl 32(%rsp), %ebx
imull %r12d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 20(%rsp), %ebp
imull %r12d, %ebp
sall $2, %ebp
movslq %ebp, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq 120(%rsp), %rdi
call cudaMemset@PLT
movq %rbp, %rdx
movl $0, %esi
movq 136(%rsp), %rdi
call cudaMemset@PLT
testl %r15d, %r15d
jle .L58
movslq 44(%rsp), %r13
salq $2, %r13
salq $2, %r14
movq 56(%rsp), %rbx
movl $0, %r12d
movl $0, %ebp
.L59:
movq %r12, %rdi
addq 120(%rsp), %rdi
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
addl $1, %ebp
addq %r14, %r12
addq %r13, %rbx
cmpl %ebp, %r15d
jne .L59
movl %eax, 76(%rsp)
.L58:
movl 44(%rsp), %eax
testl %eax, %eax
jle .L60
movslq 16(%rsp), %r13
salq $2, %r13
movq 8(%rsp), %rcx
leaq 0(,%rcx,4), %r14
movq 64(%rsp), %rbx
movl $0, %r12d
movl $0, %ebp
movl %r15d, 32(%rsp)
movl %eax, %r15d
.L61:
movq %r12, %rdi
addq 136(%rsp), %rdi
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
addl $1, %ebp
addq %r14, %r12
addq %r13, %rbx
cmpl %ebp, %r15d
jne .L61
movl %eax, 72(%rsp)
movl 32(%rsp), %r15d
.L60:
movl 76(%rsp), %eax
orl 72(%rsp), %eax
jne .L55
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L62:
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
jmp .L55
.L76:
subq $8, %rsp
.cfi_def_cfa_offset 232
movl 28(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 240
pushq $1
.cfi_def_cfa_offset 248
pushq 112(%rsp)
.cfi_def_cfa_offset 256
movl %eax, %r9d
movl $1, %r8d
movq 168(%rsp), %rcx
movl 68(%rsp), %edx
movl $1, %esi
movq 152(%rsp), %rdi
movss 72(%rsp), %xmm0
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L62
.L64:
addl $1, %ebp
addq %r14, %r12
addq %r13, %rbx
cmpl %ebp, %r15d
je .L63
.L65:
movq %r12, %rsi
addq 88(%rsp), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L64
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L64
.L63:
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf, .-_Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf
.globl _Z22gemm_f32_blockmultipleiiifPKfS0_fPf
.type _Z22gemm_f32_blockmultipleiiifPKfS0_fPf, @function
_Z22gemm_f32_blockmultipleiiifPKfS0_fPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r14d
movss %xmm0, 12(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movss %xmm1, 8(%rsp)
movq %r9, %r15
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leal 0(,%rsi,4), %r13d
movl $16, 64(%rsp)
movl $4, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L79
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L79:
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L80
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L80:
cvttsd2siq %xmm4, %rax
movl %eax, 76(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl %ebx, %r12d
imull %r13d, %r12d
movslq %r12d, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
pxor %xmm0, %xmm0
movss 8(%rsp), %xmm7
ucomiss %xmm0, %xmm7
jp .L81
jne .L81
movq %r12, %rdx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
.L83:
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm6
ucomiss %xmm0, %xmm6
jp .L89
jne .L89
.L84:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L91
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L83
movl %ebp, %r8d
movl $1, %ecx
movq 56(%rsp), %rdx
movss 8(%rsp), %xmm0
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
jmp .L83
.L89:
imull %r14d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
imull %r14d, %r13d
movslq %r13d, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
orl %ebx, %eax
jne .L84
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L86:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
jmp .L84
.L92:
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
pushq $1
.cfi_def_cfa_offset 184
pushq 80(%rsp)
.cfi_def_cfa_offset 192
movl %ebp, %r9d
movl $1, %r8d
movq 80(%rsp), %rcx
movl %r14d, %edx
movl $1, %esi
movq 72(%rsp), %rdi
movss 44(%rsp), %xmm0
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $32, %rsp
.cfi_def_cfa_offset 160
jmp .L86
.L91:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z22gemm_f32_blockmultipleiiifPKfS0_fPf, .-_Z22gemm_f32_blockmultipleiiifPKfS0_fPf
.globl _Z8gemm_f32iiifPKfS0_fPf
.type _Z8gemm_f32iiifPKfS0_fPf, @function
_Z8gemm_f32iiifPKfS0_fPf:
.LFB2059:
.cfi_startproc
endbr64
movl %edx, %r10d
pxor %xmm2, %xmm2
ucomiss %xmm2, %xmm0
setnp %al
movl $0, %edx
cmovne %edx, %eax
testb %al, %al
je .L97
ucomiss .LC1(%rip), %xmm1
setnp %al
cmovne %edx, %eax
testb %al, %al
je .L97
ret
.L97:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
sarl $31, %edx
shrl $28, %edx
leal (%rdi,%rdx), %eax
andl $15, %eax
subl %edx, %eax
leal 15(%rsi), %edx
testl %esi, %esi
cmovns %esi, %edx
sarl $4, %edx
orl %edx, %eax
jne .L96
movl %r10d, %edx
call _Z22gemm_f32_blockmultipleiiifPKfS0_fPf
.L93:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
movl %r10d, %edx
call _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf
jmp .L93
.cfi_endproc
.LFE2059:
.size _Z8gemm_f32iiifPKfS0_fPf, .-_Z8gemm_f32iiifPKfS0_fPf
.section .rodata.str1.1
.LC15:
.string "_Z10k_scal_f32iifPfii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "_Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii"
.section .rodata.str1.1
.LC17:
.string "_Z10k_gemm_f32fPKfiiS0_iiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10k_scal_f32iifPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z10k_gemm_f32fPKfiiS0_iiPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1031798784
.align 4
.LC3:
.long 1258291200
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1066401792
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.set .LC9,.LC10+4
.align 8
.LC10:
.long -1
.long 2147483647
.section .rodata.cst4
.align 4
.LC11:
.long 1098907648
.section .rodata.cst8
.align 8
.LC12:
.long 0
.long 1078984704
.align 8
.LC14:
.long 0
.long 1064304640
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
/*Kernel for matrix outer product*/
__global__
void k_gemm_f32(float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c){
const int TILE_WIDTH=16;
const int VEC_SIZE=4; //multiplies TILE_WIDTH for the b row vectors. 4 means one thread calculated C's entries with a rowlength of 4*16=64 numbers in B. Must be multiple of TILE_WIDTH
float Cc[TILE_WIDTH]={0}; //initializes all elements to zero
__shared__ float Ac[TILE_WIDTH*TILE_WIDTH]; //buffer that holds columns of a
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int a_begin=by*TILE_WIDTH*stride_col_a;
int a_end=a_begin+stride_col_a;//check if correct
int b_begin=bx*TILE_WIDTH*VEC_SIZE*stride_row_b; //we multiply by VEC_SIZE because B's tiles have length TILEWIDTH*VEC_SIZE
for (;a_begin < a_end;a_begin+=TILE_WIDTH*stride_row_a){
//Load elements of A into shared memory
for (int i=0; i< 4;i++){
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
}
__syncthreads();
const float* ptrB=&B[b_begin+(TILE_WIDTH*ty+tx)*stride_row_b];
float* ptrA=Ac;
#pragma unroll
for (int i=0;i<TILE_WIDTH;i++){
float bv=alpha*ptrB[0];
//this loop could be unrolled
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]+=ptrA[j]*bv;
}
ptrA+=TILE_WIDTH; //next column of A (it is the next column because Ac is a transposed block of A)
ptrB+=stride_col_b;
}
b_begin+=TILE_WIDTH*stride_col_b;
__syncthreads();
}
int c=stride_col_c*TILE_WIDTH*by+(TILE_WIDTH*VEC_SIZE*bx+tx+TILE_WIDTH*ty)*stride_row_c;
for (int i=0;i<TILE_WIDTH;i++){
C[c]+=Cc[i];
c+=stride_col_c;
}
}
//Todo!!
/*Kernel for matrix outer product. This version does not require A,B,C to be multiples of the blocksizes*/
__global__
void k_gemm_f32_nonblockmultiple(const int m, const int n, const int k,float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c){
const int TILE_WIDTH=16;
const int VEC_SIZE=4; //multiplies TILE_WIDTH for the b row vectors. 4 means one thread calculated with a rowlength of 4*16=64 numbers in B. Must be multiple of TILE_WIDTH
float Cc[TILE_WIDTH]={0}; //initializes all elements to zero
__shared__ float Ac[TILE_WIDTH*TILE_WIDTH]; //buffer that holds columns of a
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
int qm=m%TILE_WIDTH;
//int qn=(VEC_SIZE*TILE_WIDTH)%n;
int qk=k%TILE_WIDTH;
int rowA=by*TILE_WIDTH;
int colB=bx*TILE_WIDTH*VEC_SIZE+TILE_WIDTH*ty+tx;
int a_begin=by*TILE_WIDTH*stride_col_a;
int b_begin=bx*TILE_WIDTH*VEC_SIZE*stride_row_b; //we multiply by VEC_SIZE because B's tiles have length TILEWIDTH*VEC_SIZE
bool does_compute=false;
//printf("qk:%d\n",qk);
int rk=k/TILE_WIDTH;
for (int q=0;q<rk;q++){
//Load elements of A into shared memory
//printf("i: %d\n",a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a);
if ((tx<k)&&((rowA+TILE_WIDTH-1)<m)){
for (int i=0; i< 4;i++){
//printf("Aci: %d, i: %d and A:%f\n",i*4+ty+TILE_WIDTH*tx,a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a,A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a]);
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
}
}
else{
for (int i=0; i< 4;i++){
if((rowA+i*4+ty)<m && (tx<k)){
//printf("is: %f\n",A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a]);
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
// printf("is:Ac index: %d, index: %d and A:%f\n",i*4+ty+TILE_WIDTH*tx,a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a,A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a]);
}
else{
Ac[i*4+ty+TILE_WIDTH*tx]=0.0;
}
}
}
/*
for (int i=0;i<TILE_WIDTH*TILE_WIDTH;i++){
Ac[i]=-7;
}
*/
__syncthreads();
/*
if (tx==0 && ty==0){
for (int i=0;i<TILE_WIDTH*TILE_WIDTH;i++){
printf("%f\t",Ac[i]);
}
}
*/
if (colB>=n){
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]=0.0;
}
}
else{
//printf("Id: %d,%d,%d,%d\n",by,ty,bx,tx);
const float* ptrB=&B[b_begin+(TILE_WIDTH*ty+tx)*stride_row_b];
float* ptrA=Ac;
does_compute=true;
#pragma unroll
for (int i=0;i<TILE_WIDTH;i++){
float bv=alpha*ptrB[0];
//this loop could be unrolled
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]+=ptrA[j]*bv;
/* if (ptrA[j]!=0){
printf("%f vs. %f\n",ptrA[j],bv);
}
*/
}
ptrA+=TILE_WIDTH; //next column of A (it is the next column because Ac is a transposed block of A)
ptrB+=stride_col_b;
}
b_begin+=TILE_WIDTH*stride_col_b;
}
a_begin+=TILE_WIDTH*stride_row_a;
__syncthreads();
}
if (qk>0){
if (tx<qk){
//printf("rowA:%d, ty:%d\n",rowA,ty);
a_begin=(by*TILE_WIDTH*stride_col_a)+rk*TILE_WIDTH*stride_row_a;
for (int i=0; i< 4;i++){
if((rowA+i*4+ty)<m){
Ac[i*4+ty+TILE_WIDTH*tx]=A[a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a];
//printf("Ac index2: %d, index: %d and \n",i*4+ty+TILE_WIDTH*tx,a_begin+stride_col_a*(i*4+ty)+tx*stride_row_a);
}
else{
Ac[i*4+ty+TILE_WIDTH*tx]=0.0;
}
}
}
else{
for (int i=0; i< 4;i++){
Ac[i*4+ty+TILE_WIDTH*tx]=0.0;
}
}
__syncthreads();
//return;
if (colB<n){
// printf("Id: %d,%d,%d,%d\n",by,ty,bx,tx);
const float* ptrB=&B[b_begin+(TILE_WIDTH*ty+tx)*stride_row_b];
float* ptrA=Ac;
does_compute=true;
for (int i=0;i<qk;i++){
float bv=alpha*ptrB[0];
//this loop could be unrolled
for (int j=0;j<TILE_WIDTH;j++){
Cc[j]+=ptrA[j]*bv;
/*if (ptrA[j]!=0){
printf("%f vs2. %f\n",ptrA[j],bv);
}
*/
}
ptrA+=TILE_WIDTH; //next column of A (it is the next column because Ac is a transposed block of A)
ptrB+=stride_col_b;
}
}
}
__syncthreads(); //maybe redundant
if (does_compute){
int c=stride_col_c*TILE_WIDTH*by+(TILE_WIDTH*VEC_SIZE*bx+tx+TILE_WIDTH*ty)*stride_row_c;
int c_length=((rowA+TILE_WIDTH)<=m)?TILE_WIDTH:qm;
for (int i=0;i<c_length;i++){
C[c]+=Cc[i];
c+=stride_col_c;
}
}
}
__global__
void k_scal_f32(int m, int n, float beta, float* C, int stride_row_c, int stride_col_c){
const int BLOCK_WIDTH=256; //size of a block
const int TILE_WIDTH=64; //size of block per single thread
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
//printf("Bin drin mit : bx %d, tx %d, by %d, ty %d \n",bx,tx,by,ty);
float* c_begin=&C[(by*BLOCK_WIDTH+ty*TILE_WIDTH)*stride_col_c+(bx*BLOCK_WIDTH+tx*TILE_WIDTH)*stride_row_c];
if ((((by+1)*BLOCK_WIDTH)<=m) && (((bx+1)*BLOCK_WIDTH)<=n)){
for (int i=0;i<TILE_WIDTH;i++){
for (int j=0;j<TILE_WIDTH;j++){
c_begin[i*stride_col_c+j*stride_row_c]*=beta;
}
}
}
else{
int column=by*BLOCK_WIDTH+ty*TILE_WIDTH;
for (int i=0;i<TILE_WIDTH;i++){
if (column<m){
int row=bx*BLOCK_WIDTH+tx*TILE_WIDTH;
for (int j=0;j<TILE_WIDTH;j++){
if (row<n){
c_begin[i*stride_col_c+j*stride_row_c]*=beta;
//printf("Bin hier drin mit %d und %d mit by %d ty %d bx %d tx %d\n",i,j,by,ty,bx,tx);
}
row=row+1;
}
}
column=column+1;
}
}
}
//matrix matrix multiplication
__host__
void gemm_f32_blockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h){
float* A_d;
float* B_d;
float* C_d;
int sizeA=sizeof(float)*m*k;
int sizeB=sizeof(float)*n*k;
int sizeC=sizeof(float)*m*n;
float bsmx=16;
float bsmy=4;
dim3 threadLayout=dim3(bsmx,bsmy,1);
dim3 grid=dim3(ceil(n/(4.0*bsmx)),ceil(m/bsmx),1);
cudaMalloc((void**) &C_d,sizeC);
if (beta==0){
cudaMemset(C_d, 0, sizeC);
}
else{
cudaMemcpy((void*) C_d, (void*) C_h, sizeC,cudaMemcpyHostToDevice);
k_scal_f32<<<grid,threadLayout>>>(m,n,beta,C_d,1,n);
}
if (alpha!=0.0){
cudaMalloc((void**) &A_d,sizeA);
cudaMalloc((void**) &B_d,sizeB);
cudaError_t copy1=cudaMemcpy((void*) A_d, (void*) A_h, sizeA, cudaMemcpyHostToDevice);
cudaError_t copy2=cudaMemcpy((void*) B_d, (void*) B_h, sizeB, cudaMemcpyHostToDevice);
if ((copy1==cudaSuccess)&& (copy2==cudaSuccess)){
k_gemm_f32<<<grid,threadLayout>>> (alpha, A_d, 1, k,B_d,1,n,C_d,1,n);
cudaMemcpy((void*) C_h, (void*) C_d, sizeC, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
}
}
cudaFree(C_d);
}
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
__host__
void gemm_f32_nonblockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h){
float* A_d;
float* B_d;
float* C_d;
float bsmx=16; //blocksize x
float bsmy=4; //blocksize y
int mB=ceil(m/bsmx)*bsmx;
int nB=ceil(n/(4.0*bsmx))*(4.0*bsmx);
int kB=ceil(k/bsmx)*bsmx;
int sizeCb=sizeof(float)*mB*nB;
cudaMalloc((void**) &C_d, sizeCb);
dim3 threadLayout=dim3(bsmx,bsmy,1);
dim3 grid=dim3(ceil(nB/(4.0*bsmx)),ceil(mB/bsmx),1);
if (beta==0){
cudaMemset(C_d, 0, sizeCb);
}
else{
cudaError_t copy;
for (int i=0;i<m;i++){
copy=cudaMemcpy((void*) (C_d+i*nB), (void*) (C_h+i*n), sizeof(float)*n,cudaMemcpyHostToDevice);
}
if (copy!=cudaSuccess){
printf("Copy fehlgeschlagen\n");
}
// printf("Starte nun den Kernel\n");
dim3 threadsize=dim3(4,4,1);
dim3 blocksize=dim3(ceil(n/256.0),ceil(m/256.0),1);
k_scal_f32<<<blocksize,threadsize>>>(m,n,beta,C_d,1,nB);
//cudaDeviceSynchronize();
}
if (alpha!=0.0){
int sizeAb=sizeof(float)*mB*kB;
int sizeBb=sizeof(float)*kB*nB;
cudaMalloc((void**) &A_d,sizeAb);
cudaMalloc((void**) &B_d,sizeBb);
cudaMemset(A_d,0.0,sizeAb);
cudaMemset(B_d,0.0,sizeBb);
cudaError_t copy1;
cudaError_t copy2;
for (int i=0;i<m;i++){
copy1=cudaMemcpy((void*) (A_d+i*kB), (void*) (A_h+i*k), sizeof(float)*k,cudaMemcpyHostToDevice);
}
for (int i=0;i<k;i++){
copy2=cudaMemcpy((void*) (B_d+i*nB), (void*) (B_h+i*n), sizeof(float)*n, cudaMemcpyHostToDevice);
}
if ((copy1==cudaSuccess)&& (copy2==cudaSuccess)){
k_gemm_f32<<<grid,threadLayout>>> (alpha, A_d, 1, kB,B_d,1,nB,C_d,1,nB);
cudaFree(A_d);
cudaFree(B_d);
}
}
for (int i=0;i<m;i++){
cudaError_t copy=cudaMemcpy((void*) (C_h+i*n), (void*) (C_d+i*nB),sizeof(float)*n,cudaMemcpyDeviceToHost);
if (copy!=cudaSuccess){
printf("Copy fehlgeschlagen\n");
}
}
cudaFree(C_d);
}
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
__host__
void gemm_f32(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h){
if ((alpha==0.0) && (beta==1.0)){
return;
}
int res1=m%16;
int res2=n/(4*4);
if ((res1==0)&&(res2==0)){
gemm_f32_blockmultiple(m,n,k,alpha,A_h,B_h,beta,C_h);
}
else{
// printf("nonblockmultiple\n");
gemm_f32_nonblockmultiple(m,n,k,alpha,A_h,B_h,beta,C_h);
}
}
//General matrix-to-matrix multiplication for 32 bit floats. This assumes that the input parameters are already allocated in device memory
__host__
void gemm_f32_device(int m, int n, int k, float alpha, const float* A_d, int stride_row_a, int stride_col_a, const float* B_d, int stride_row_b, int stride_col_b, float beta, float* C_d,int stride_row_c, int stride_col_c){
if ((alpha==0.0) && (beta==1.0)){
return;
}
float bsmx=16;
float bsmy=4;
dim3 threadLayout=dim3(bsmx,bsmy,1);
dim3 grid=dim3(ceil(n/(4.0*bsmx)),ceil(m/bsmx),1);
k_scal_f32<<<grid,threadLayout>>>(m,n,beta,C_d,stride_row_c,stride_col_c);
if (alpha!=0){
int res1=m%(int)bsmx;
int res2=n%(int)bsmx;
if ((res1==0)&&(res2==0)){
// printf("gemm blockmultiple\n");
k_gemm_f32<<<grid,threadLayout>>>(alpha, A_d, stride_row_a, stride_col_a,B_d,stride_row_b,stride_col_b,C_d,stride_row_c,stride_col_c);
}
else{
//printf("gemm nonblockmultiple\n");
k_gemm_f32_nonblockmultiple<<<grid,threadLayout>>>(m,n,k,alpha, A_d, stride_row_a, stride_col_a,B_d,stride_row_b,stride_col_b,C_d,stride_row_c,stride_col_c);
}
}
} | #pragma once
#include <hip/hip_runtime.h>
#ifdef __HIPCC__
__global__
#endif
void k_gemm_f32(float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c);
#ifdef __HIPCC__
__global__
#endif
void k_scal_f32(int m, int n, float beta, float* C, int stride_row_c, int stride_col_c);
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_blockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_nonblockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
#ifdef __HIPCC__
__host__
#endif
void gemm_f32(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
//General matrix-to-matrix multiplication for 32 bit floats. This assumes that the input parameters are already allocated in device memory
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_device(int m, int n, int k, float alpha, const float* A_d, int stride_row_a, int stride_col_a, const float* B_d, int stride_row_b, int stride_col_b, float beta, float* C_d,int stride_row_c, int stride_col_c); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifdef __HIPCC__
__global__
#endif
void k_gemm_f32(float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c);
#ifdef __HIPCC__
__global__
#endif
void k_scal_f32(int m, int n, float beta, float* C, int stride_row_c, int stride_col_c);
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_blockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_nonblockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
#ifdef __HIPCC__
__host__
#endif
void gemm_f32(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
//General matrix-to-matrix multiplication for 32 bit floats. This assumes that the input parameters are already allocated in device memory
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_device(int m, int n, int k, float alpha, const float* A_d, int stride_row_a, int stride_col_a, const float* B_d, int stride_row_b, int stride_col_b, float beta, float* C_d,int stride_row_c, int stride_col_c); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifdef __HIPCC__
__global__
#endif
void k_gemm_f32(float alpha, const float* A, int stride_row_a, int stride_col_a,const float* B, int stride_row_b, int stride_col_b,float* C, int stride_row_c, int stride_col_c);
#ifdef __HIPCC__
__global__
#endif
void k_scal_f32(int m, int n, float beta, float* C, int stride_row_c, int stride_col_c);
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_blockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_nonblockmultiple(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
//General matrix-to-matrix multiplication for 32 bit floats. Input matrices are padded if they are not a multiple of block size bsmx and bsmy
#ifdef __HIPCC__
__host__
#endif
void gemm_f32(int m, int n, int k, float alpha, const float* A_h, const float* B_h, float beta, float* C_h);
//General matrix-to-matrix multiplication for 32 bit floats. This assumes that the input parameters are already allocated in device memory
#ifdef __HIPCC__
__host__
#endif
void gemm_f32_device(int m, int n, int k, float alpha, const float* A_d, int stride_row_a, int stride_col_a, const float* B_d, int stride_row_b, int stride_col_b, float beta, float* C_d,int stride_row_c, int stride_col_c); | .text
.file "gemm.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b365_00000000-6_gemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
.type _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii, @function
_Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movq %rdi, 32(%rsp)
movl %esi, 40(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 12(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10k_gemm_f32fPKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii, .-_Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
.globl _Z10k_gemm_f32fPKfiiS0_iiPfii
.type _Z10k_gemm_f32fPKfiiS0_iiPfii, @function
_Z10k_gemm_f32fPKfiiS0_iiPfii:
.LFB2086:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10k_gemm_f32fPKfiiS0_iiPfii, .-_Z10k_gemm_f32fPKfiiS0_iiPfii
.globl _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
.type _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii, @function
_Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii:
.LFB2087:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 248(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii, .-_Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
.globl _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii
.type _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii, @function
_Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii, .-_Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii
.globl _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
.type _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii, @function
_Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii:
.LFB2089:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10k_scal_f32iifPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii, .-_Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
.globl _Z10k_scal_f32iifPfii
.type _Z10k_scal_f32iifPfii, @function
_Z10k_scal_f32iifPfii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z10k_scal_f32iifPfii, .-_Z10k_scal_f32iifPfii
.globl _Z15gemm_f32_deviceiiifPKfiiS0_iifPfii
.type _Z15gemm_f32_deviceiiifPKfiiS0_iifPfii, @function
_Z15gemm_f32_deviceiiifPKfiiS0_iifPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r15d
movaps %xmm0, %xmm6
movss %xmm0, 8(%rsp)
movq %rcx, %r12
movl %r8d, %r13d
movl %r9d, %r14d
movss %xmm1, 12(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm0, %xmm6
setnp %al
movl $0, %edx
cmovne %edx, %eax
testb %al, %al
je .L36
ucomiss .LC1(%rip), %xmm1
setnp %al
cmovne %edx, %eax
testb %al, %al
je .L36
.L27:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $16, 24(%rsp)
movl $4, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L30
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L30:
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L31
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L31:
cvttsd2siq %xmm4, %rax
movl %eax, 36(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
pxor %xmm0, %xmm0
movss 8(%rsp), %xmm7
ucomiss %xmm0, %xmm7
jp .L37
je .L27
.L37:
movl %ebx, %edx
sarl $31, %edx
shrl $28, %edx
leal (%rbx,%rdx), %eax
andl $15, %eax
subl %edx, %eax
movl %ebp, %ecx
sarl $31, %ecx
shrl $28, %ecx
leal 0(%rbp,%rcx), %edx
andl $15, %edx
subl %ecx, %edx
orl %edx, %eax
jne .L35
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
subq $8, %rsp
.cfi_def_cfa_offset 120
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
pushq 160(%rsp)
.cfi_def_cfa_offset 144
movl 160(%rsp), %r9d
movl 152(%rsp), %r8d
movq 144(%rsp), %rcx
movl %r14d, %edx
movl %r13d, %esi
movq %r12, %rdi
movss 40(%rsp), %xmm0
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $32, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L39:
movl 152(%rsp), %r8d
movl 144(%rsp), %ecx
movq 136(%rsp), %rdx
movss 12(%rsp), %xmm0
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
jmp .L32
.L35:
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
pushq 152(%rsp)
.cfi_def_cfa_offset 136
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
pushq 152(%rsp)
.cfi_def_cfa_offset 160
movl %r14d, %r9d
movl %r13d, %r8d
movq %r12, %rcx
movss 56(%rsp), %xmm0
movl %r15d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z63__device_stub__Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfiiiiifPKfiiS0_iiPfii
addq $48, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.cfi_endproc
.LFE2060:
.size _Z15gemm_f32_deviceiiifPKfiiS0_iifPfii, .-_Z15gemm_f32_deviceiiifPKfiiS0_iifPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "Copy fehlgeschlagen\n"
.text
.globl _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf
.type _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf, @function
_Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %r15d
movl %esi, 16(%rsp)
movl %edx, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 64(%rsp)
movss %xmm1, 36(%rsp)
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L41
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L41:
mulss .LC11(%rip), %xmm1
cvttss2sil %xmm1, %eax
movl %eax, 32(%rsp)
pxor %xmm6, %xmm6
cvtsi2sdl 16(%rsp), %xmm6
movsd %xmm6, 48(%rsp)
movapd %xmm6, %xmm2
mulsd .LC5(%rip), %xmm2
movapd %xmm2, %xmm0
movsd .LC10(%rip), %xmm3
movapd %xmm2, %xmm1
andpd %xmm3, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L42
cvttsd2siq %xmm2, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm0
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm0
addsd %xmm1, %xmm0
andnpd %xmm2, %xmm3
orpd %xmm3, %xmm0
.L42:
mulsd .LC12(%rip), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 20(%rsp)
movslq %eax, %rdx
movq %rdx, 8(%rsp)
movl 32(%rsp), %r14d
movl %r14d, %ebx
imull %eax, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $16, 96(%rsp)
movl $4, 100(%rsp)
movl $1, 104(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L43
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L43:
pxor %xmm0, %xmm0
cvtsi2sdl 20(%rsp), %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L44
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L44:
cvttsd2siq %xmm4, %rax
movl %eax, 108(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
pxor %xmm0, %xmm0
movss 36(%rsp), %xmm7
ucomiss %xmm0, %xmm7
jp .L67
je .L45
.L67:
testl %r15d, %r15d
jle .L48
movslq 16(%rsp), %r13
salq $2, %r13
movq 8(%rsp), %rax
leaq 0(,%rax,4), %r14
movq 24(%rsp), %r12
movl $0, %ebp
movl $0, %ebx
.L50:
movq %rbp, %rdi
addq 88(%rsp), %rdi
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
call cudaMemcpy@PLT
addl $1, %ebx
addq %r14, %rbp
addq %r13, %r12
cmpl %ebx, %r15d
jne .L50
movl %eax, %ebp
.L48:
testl %ebp, %ebp
jne .L74
.L51:
movl $4, 120(%rsp)
movl $4, 124(%rsp)
movl $1, 128(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC14(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L52
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L52:
movsd 48(%rsp), %xmm0
mulsd .LC14(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L53
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L53:
cvttsd2siq %xmm4, %rax
movl %eax, 136(%rsp)
cvttsd2siq %xmm1, %rax
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl 128(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 120(%rsp), %rdx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L49:
pxor %xmm0, %xmm0
movss 40(%rsp), %xmm5
ucomiss %xmm0, %xmm5
jp .L68
jne .L68
.L55:
testl %r15d, %r15d
jle .L63
movslq 16(%rsp), %r13
salq $2, %r13
movq 8(%rsp), %r14
salq $2, %r14
movq 24(%rsp), %rbx
movl $0, %r12d
movl $0, %ebp
jmp .L65
.L45:
movq %rbx, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
jmp .L49
.L74:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L75:
movl 20(%rsp), %r8d
movl $1, %ecx
movq 88(%rsp), %rdx
movss 36(%rsp), %xmm0
movl 16(%rsp), %esi
movl %r15d, %edi
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
jmp .L49
.L68:
pxor %xmm0, %xmm0
cvtsi2ssl 44(%rsp), %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L57
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L57:
mulss .LC11(%rip), %xmm1
cvttss2sil %xmm1, %r12d
movl %r12d, 36(%rsp)
movslq %r12d, %r14
movl 32(%rsp), %ebx
imull %r12d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 20(%rsp), %ebp
imull %r12d, %ebp
sall $2, %ebp
movslq %ebp, %rbp
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq 120(%rsp), %rdi
call cudaMemset@PLT
movq %rbp, %rdx
movl $0, %esi
movq 136(%rsp), %rdi
call cudaMemset@PLT
testl %r15d, %r15d
jle .L58
movslq 44(%rsp), %r13
salq $2, %r13
salq $2, %r14
movq 56(%rsp), %rbx
movl $0, %r12d
movl $0, %ebp
.L59:
movq %r12, %rdi
addq 120(%rsp), %rdi
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
addl $1, %ebp
addq %r14, %r12
addq %r13, %rbx
cmpl %ebp, %r15d
jne .L59
movl %eax, 76(%rsp)
.L58:
movl 44(%rsp), %eax
testl %eax, %eax
jle .L60
movslq 16(%rsp), %r13
salq $2, %r13
movq 8(%rsp), %rcx
leaq 0(,%rcx,4), %r14
movq 64(%rsp), %rbx
movl $0, %r12d
movl $0, %ebp
movl %r15d, 32(%rsp)
movl %eax, %r15d
.L61:
movq %r12, %rdi
addq 136(%rsp), %rdi
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
addl $1, %ebp
addq %r14, %r12
addq %r13, %rbx
cmpl %ebp, %r15d
jne .L61
movl %eax, 72(%rsp)
movl 32(%rsp), %r15d
.L60:
movl 76(%rsp), %eax
orl 72(%rsp), %eax
jne .L55
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L62:
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
jmp .L55
.L76:
subq $8, %rsp
.cfi_def_cfa_offset 232
movl 28(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 240
pushq $1
.cfi_def_cfa_offset 248
pushq 112(%rsp)
.cfi_def_cfa_offset 256
movl %eax, %r9d
movl $1, %r8d
movq 168(%rsp), %rcx
movl 68(%rsp), %edx
movl $1, %esi
movq 152(%rsp), %rdi
movss 72(%rsp), %xmm0
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L62
.L64:
addl $1, %ebp
addq %r14, %r12
addq %r13, %rbx
cmpl %ebp, %r15d
je .L63
.L65:
movq %r12, %rsi
addq 88(%rsp), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L64
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L64
.L63:
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf, .-_Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf
.globl _Z22gemm_f32_blockmultipleiiifPKfS0_fPf
.type _Z22gemm_f32_blockmultipleiiifPKfS0_fPf, @function
_Z22gemm_f32_blockmultipleiiifPKfS0_fPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r14d
movss %xmm0, 12(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movss %xmm1, 8(%rsp)
movq %r9, %r15
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leal 0(,%rsi,4), %r13d
movl $16, 64(%rsp)
movl $4, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC3(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L79
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L79:
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC10(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC6(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L80
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC8(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L80:
cvttsd2siq %xmm4, %rax
movl %eax, 76(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl %ebx, %r12d
imull %r13d, %r12d
movslq %r12d, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
pxor %xmm0, %xmm0
movss 8(%rsp), %xmm7
ucomiss %xmm0, %xmm7
jp .L81
jne .L81
movq %r12, %rdx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
.L83:
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm6
ucomiss %xmm0, %xmm6
jp .L89
jne .L89
.L84:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L91
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L83
movl %ebp, %r8d
movl $1, %ecx
movq 56(%rsp), %rdx
movss 8(%rsp), %xmm0
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z10k_scal_f32iifPfiiiifPfii
jmp .L83
.L89:
imull %r14d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
imull %r14d, %r13d
movslq %r13d, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
orl %ebx, %eax
jne .L84
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L86:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
jmp .L84
.L92:
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
pushq $1
.cfi_def_cfa_offset 184
pushq 80(%rsp)
.cfi_def_cfa_offset 192
movl %ebp, %r9d
movl $1, %r8d
movq 80(%rsp), %rcx
movl %r14d, %edx
movl $1, %esi
movq 72(%rsp), %rdi
movss 44(%rsp), %xmm0
call _Z43__device_stub__Z10k_gemm_f32fPKfiiS0_iiPfiifPKfiiS0_iiPfii
addq $32, %rsp
.cfi_def_cfa_offset 160
jmp .L86
.L91:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z22gemm_f32_blockmultipleiiifPKfS0_fPf, .-_Z22gemm_f32_blockmultipleiiifPKfS0_fPf
.globl _Z8gemm_f32iiifPKfS0_fPf
.type _Z8gemm_f32iiifPKfS0_fPf, @function
_Z8gemm_f32iiifPKfS0_fPf:
.LFB2059:
.cfi_startproc
endbr64
movl %edx, %r10d
pxor %xmm2, %xmm2
ucomiss %xmm2, %xmm0
setnp %al
movl $0, %edx
cmovne %edx, %eax
testb %al, %al
je .L97
ucomiss .LC1(%rip), %xmm1
setnp %al
cmovne %edx, %eax
testb %al, %al
je .L97
ret
.L97:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
sarl $31, %edx
shrl $28, %edx
leal (%rdi,%rdx), %eax
andl $15, %eax
subl %edx, %eax
leal 15(%rsi), %edx
testl %esi, %esi
cmovns %esi, %edx
sarl $4, %edx
orl %edx, %eax
jne .L96
movl %r10d, %edx
call _Z22gemm_f32_blockmultipleiiifPKfS0_fPf
.L93:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
movl %r10d, %edx
call _Z25gemm_f32_nonblockmultipleiiifPKfS0_fPf
jmp .L93
.cfi_endproc
.LFE2059:
.size _Z8gemm_f32iiifPKfS0_fPf, .-_Z8gemm_f32iiifPKfS0_fPf
.section .rodata.str1.1
.LC15:
.string "_Z10k_scal_f32iifPfii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "_Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii"
.section .rodata.str1.1
.LC17:
.string "_Z10k_gemm_f32fPKfiiS0_iiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10k_scal_f32iifPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z27k_gemm_f32_nonblockmultipleiiifPKfiiS0_iiPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z10k_gemm_f32fPKfiiS0_iiPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1031798784
.align 4
.LC3:
.long 1258291200
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1066401792
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.set .LC9,.LC10+4
.align 8
.LC10:
.long -1
.long 2147483647
.section .rodata.cst4
.align 4
.LC11:
.long 1098907648
.section .rodata.cst8
.align 8
.LC12:
.long 0
.long 1078984704
.align 8
.LC14:
.long 0
.long 1064304640
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gemm.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include <stdlib.h>
#include<malloc.h>
#include <time.h>
#include<cuda.h>
#include <iostream>
typedef char* string;
#define HILOSXBLOCK 32 //¿máximo depende de la memorio compartida de la gpu?
//d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C
__global__
void multGPUSHARE(float* A,int filA,int colA,float* B,int filB,int colB,float* C){//filC=filA,colC=colB
//Tamaño total de los elementos con que vamos a trabajar
__shared__ float A_s[HILOSXBLOCK][HILOSXBLOCK];
__shared__ float B_s[HILOSXBLOCK][HILOSXBLOCK];
//Para saber en qué bloque y qué hilo estamos
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = gridDim.x;
int gy = gridDim.y;
//Para el resultado de C
int row = by * HILOSXBLOCK + ty;
int col = bx * HILOSXBLOCK + tx;
float suma = 0;//para llevar la suma de las multiplicaciones
int n = 0, m = 0;
while(m < gx && n < gy){
/* De A queremos sacar las columnas, por eso:
* col = ( ( m * HILOSXBLOCK ) + tx )
* col = ( ( bx * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que m se mueve entre los bloques en el eje x (las columnas)
*/
if(( ( m * HILOSXBLOCK ) + tx ) < colA && row < filA) //Si no se pasa
A_s[ty][tx] = A[ (row * colA) + ( ( m * HILOSXBLOCK ) + tx )];//(Row*colA + k), donde k-> 0..filB (filB = colA)
else A_s[ty][tx] = 0;
/* De B queremos sacar las filas, por eso:
* row = ( ( m * HILOSXBLOCK ) + tx )
* row = ( ( by * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que n se mueve entre los bloques en el eje y (las filas)
*/
if(( n * HILOSXBLOCK + ty) < filB && col < colB)
B_s[ty][tx] = B[( ( n * HILOSXBLOCK + ty) * colB ) + col ];//(k*colB)+Col, donde k-> 0..filB
else B_s[ty][tx] = 0;
m++; n++;
__syncthreads();//espera a todos los hilos
for (int k=0; k < HILOSXBLOCK ; ++k) {
suma += A_s[ty][k] * B_s[k][tx];
}
__syncthreads();
}
if(row < filA && col < colB)
C[ (row * colB) + col] = suma; //C[filA][colB]
}
__global__
void multGPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((col < colsB)&&(row < rowsA)) {
for(int M = 0; M < rowsB; M++) {
C[row * colsB + col]+= A[row * colsA + M] * B[M * colsB + col];
}
}
}
__host__
void multCPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int i, j;
for(i = 0; i < rowsA; i++){
for(j = 0; j< colsB; j++){
for(int M = 0; M < rowsB; M++){
C[i * colsB + j] += A[i * colsA + M] * B[ M * colsB + j];
}
}
}
}
__host__
bool compare(float *A, float *B, int rows, int cols){
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (A[ i * cols + j] != B[i * cols + j]) return false;
}
}
return true;
}
__host__
void load(float *M, FILE *stream, int rows, int cols) {
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
fscanf(stream, "%f,", &M[i * cols + j]);
}
}
fclose(stream);
}
__host__
void save(float *M, int rows, int cols, string file_name) {
FILE *stream;
int i, j;
stream = fopen(file_name, "w");
fprintf(stream, "%d\n", rows);
fprintf(stream, "%d\n", cols);
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (j + 1 == cols) fprintf(stream, "%.2f", M[i * cols + j]);
else fprintf(stream, "%.2f,", M[i * cols + j]);
}
fprintf(stream, "%s\n","");
}
fclose(stream);
}
__host__
void print(float* M, int rows, int cols){
printf("---------------print matrix--------------\n");
for(int i = 0; i < rows; i++) {
for(int j = 0; j < cols; j++) {
printf("%f ", M[i * cols + j]);
}
printf("\n");
}
}
void guardar(float *resultado, int size, string file_name) {
FILE *f = fopen(file_name, "w");
fprintf(f, "%d\n", size);
if (f == NULL) {
printf("Error opening file!\n");
exit(1);
}
int i;
for (i = 0; i < size; i++) {
printf("resultado de %d :%f\n",i,resultado[i] );
if (i + 1 == size) {
fprintf(f, "%f\n", resultado[i]);
} else {
fprintf(f, "%f\n", resultado[i]);
}
}
fclose(f);
}
//asd
int main(int argc, char** argv){
if (argc != 3) {
printf("Must be called with the names of the files\n");
return 1;
}
//--------config gpu-------------------///
int numdiv;
int iddiv;
const int kb = 1024;
const int mb = kb * kb;
cudaGetDeviceCount(&numdiv);
printf("%d numero de GPUS\n",numdiv);
for (int i = 0; i < numdiv; i++) {
cudaDeviceProp propieties;
cudaGetDeviceProperties(&propieties, i);
printf("nombre %s\n",(char*)propieties.name);
std::wcout<<" Global memory: " << propieties.totalGlobalMem / mb << "mb" << std::endl;
std::wcout<<" Shared memory: " << propieties.sharedMemPerBlock / kb << "kb" << std::endl;
std::wcout<<" Constant memory: " << propieties.totalConstMem / kb << "kb" << std::endl;
std::wcout<<" Block registers: " << propieties.regsPerBlock << std::endl;
std::wcout<<" Warp size: " << propieties.warpSize << std::endl;
std::wcout<<" Threads per block: " << propieties.maxThreadsPerBlock << std::endl;
std::wcout<<" Max block dimensions: [ " << propieties.maxThreadsDim[0] << ", " << propieties.maxThreadsDim[1] << ", " << propieties.maxThreadsDim[2] << " ]" << std::endl;
std::wcout<<" Max grid dimensions: [ " << propieties.maxGridSize[0] << ", " << propieties.maxGridSize[1] << ", " << propieties.maxGridSize[2] << " ]" << std::endl;
}
printf("selecione dispositivo");
scanf("%d",&iddiv );
cudaSetDevice(iddiv);
//-------------------------------CPU--------------------------------------
clock_t time_start_cpu, time_end_cpu,time_start_gpu_ing, time_end_gpu_ing,time_start_gpu, time_end_gpu;
float *A, *B, *C, *times;
int rowsA, colsA, rowsB, colsB;
double timeCPU, timeGPU, timeGPUING;
FILE *arc1, *arc2;
arc1 = fopen(argv[1], "r");
arc2 = fopen(argv[2], "r");
fscanf(arc1, "%d", &rowsA);
fscanf(arc1, "%d", &colsA);
fscanf(arc2, "%d", &rowsB);
fscanf(arc2, "%d", &colsB);
//RESERVA MEMORIA EN CPU
times = (float*)malloc(10 * 3 * sizeof(float));
A = (float*)malloc(rowsA * colsA * sizeof(float));
B = (float*)malloc(rowsB * colsB * sizeof(float));
C = (float*)malloc(rowsA * colsB * sizeof(float));
load(A, arc1, rowsA, colsA);
// printf("rowsA: %d\n", rowsA);
// printf("colsA: %d\n", colsA);
// print(A, rowsA, colsA);
load(B, arc2, rowsB, colsB);
// printf("rowsA: %d\n", rowsB);
// printf("colsA: %d\n", colsB);
// print(B, rowsB, colsB);
// tiene que ser iguales filas M2 y col M1
if(colsA==rowsB){
for (int i = 0; i < 10; i++) {
/* code */
time_start_cpu = clock();
multCPU(A, rowsA, colsA, B, rowsB, colsB, C);
time_end_cpu = clock();
timeCPU = ((double)(time_end_cpu-time_start_cpu))/CLOCKS_PER_SEC;
printf ("El tiempo transcurrido en la CPU fue %lf segundos.\n", timeCPU);
times[i]=timeCPU;
}
//imprime(C,filA,colB);
}else{
printf("Error, no se pueden multiplicar");
return 0;
}
// print(C, rowsA, colsB);
// save(C, rowsA, colsB, "CPU.out"); ----------------------------
//-------------------------------GPU INGENUA--------------------------------------
cudaError_t error = cudaSuccess;
float *d_A, *d_B, *d_C, *h_C, *d_s_C;
h_C = (float*)malloc(rowsA * colsB * sizeof(float));
error = cudaMalloc((void**)&d_A,rowsA*colsA*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_A");
return 1;
}
error = cudaMalloc((void**)&d_B,rowsB*colsB*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_B");
return 1;
}
error = cudaMalloc((void**)&d_C,rowsA*colsB*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_C");
return 1;
}
error = cudaMalloc((void**)&d_s_C,rowsA*colsB*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_s_C");
return 1;
}
cudaMemcpy(d_A, A, rowsA * colsA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, rowsB * colsB * sizeof(float), cudaMemcpyHostToDevice); //se copia de origen b a destico d_b
int blockSize = 32;
dim3 dimblock(blockSize, blockSize, 1);
dim3 dimGrid(blockSize, blockSize, 1);
//dim3 dimGrid(ceil((colsB) / float(blockSize), ceil((rowsA) / float(blockSize)), 1);
for(int i=10;i<20;i++){
time_start_gpu_ing = clock();
multGPU<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_C);
cudaDeviceSynchronize();
time_end_gpu_ing = clock();
timeGPUING = ((double)(time_end_gpu_ing-time_start_gpu_ing))/CLOCKS_PER_SEC;
times[i]=timeGPUING;
printf ("Tiempo trasncurrido en GPU Algoritmo INGENUO: %lf seconds.\n", timeGPUING);
}
cudaMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), cudaMemcpyDeviceToHost);
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado: %lf\n", ((double)(timeCPU / timeGPUING)));
// save(h_C, rowsA, colsB, "GPU.out");
}
//-----------------------GPU SHARED --------------------------------------
for(int i=20;i<30;i++){
time_start_gpu = clock();
multGPUSHARE<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C);
cudaDeviceSynchronize();
time_end_gpu = clock();
timeGPU = ((double)(time_end_gpu-time_start_gpu))/CLOCKS_PER_SEC;
times[i]=timeGPU;
printf ("Tiempo trasncurrido en GPU_SHEAR: %lf seconds.\n", timeGPU);
}
cudaMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), cudaMemcpyDeviceToHost);
guardar(times,30,"tiempos.csv");
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado en la cpu vs gpu_shared: %lf\n", (double)(timeCPU / timeGPU));
// save(h_C, rowsA, colsB, "GPU.out");
}
free(A); free(B); free(C); free(h_C);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); cudaFree(d_s_C);
return 0;
} | .file "tmpxft_0012eb8d_00000000-6_matrizmultiallgraph.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7multCPUPfiiS_iiS_
.type _Z7multCPUPfiiS_iiS_, @function
_Z7multCPUPfiiS_iiS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %esi, -12(%rsp)
movq %rcx, -8(%rsp)
movq 56(%rsp), %r13
testl %esi, %esi
jle .L3
movq %rdi, %rbx
movl %edx, %r14d
movl %r8d, %ebp
movl %r9d, %r10d
movslq %r9d, %rdi
salq $2, %rdi
movl $0, %r11d
movl $0, %ecx
movl $0, %edx
movslq %r8d, %r15
movl %r14d, %esi
movq %r15, %r8
jmp .L5
.L8:
leal (%r12,%r11), %eax
cltq
leaq 0(%r13,%rax,4), %rcx
movq %r14, %rdx
movq %r15, %rax
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L6
.L9:
addl $1, %r12d
addq $4, %r14
cmpl %r12d, %r10d
je .L12
.L10:
testl %ebp, %ebp
jg .L8
jmp .L9
.L12:
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L7:
addl $1, %edx
addl %esi, %ecx
addl %r10d, %r11d
cmpl %edx, -12(%rsp)
je .L3
.L5:
testl %r10d, %r10d
jle .L7
movq -8(%rsp), %r14
movslq %ecx, %rax
leaq (%rbx,%rax,4), %r15
addq %r8, %rax
leaq (%rbx,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
jmp .L10
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7multCPUPfiiS_iiS_, .-_Z7multCPUPfiiS_iiS_
.globl _Z7comparePfS_ii
.type _Z7comparePfS_ii, @function
_Z7comparePfS_ii:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L21
movl $0, %r9d
movl $0, %r10d
movslq %ecx, %r11
.L16:
testl %ecx, %ecx
jle .L20
movslq %r9d, %r8
leaq 0(,%r8,4), %rax
addq %r11, %r8
salq $2, %r8
.L18:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L22
jne .L22
addq $4, %rax
cmpq %r8, %rax
jne .L18
.L20:
addl $1, %r10d
addl %ecx, %r9d
cmpl %r10d, %edx
jne .L16
movl $1, %eax
ret
.L21:
movl $1, %eax
ret
.L22:
movl $0, %eax
ret
.cfi_endproc
.LFE3670:
.size _Z7comparePfS_ii, .-_Z7comparePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f,"
.text
.globl _Z4loadPfP8_IO_FILEii
.type _Z4loadPfP8_IO_FILEii, @function
_Z4loadPfP8_IO_FILEii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
movq %rsi, %r12
movl %edx, 4(%rsp)
testl %edx, %edx
jle .L27
movl %ecx, %r14d
movl $0, (%rsp)
movl $0, %r15d
leaq .LC0(%rip), %r13
jmp .L28
.L30:
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L29:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
.L31:
addl $1, %r15d
addl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L27
.L28:
testl %r14d, %r14d
jg .L30
jmp .L31
.L27:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z4loadPfP8_IO_FILEii, .-_Z4loadPfP8_IO_FILEii
.section .rodata.str1.1
.LC1:
.string "w"
.LC2:
.string "%d\n"
.LC3:
.string "%.2f"
.LC4:
.string "%.2f,"
.LC5:
.string ""
.LC6:
.string "%s\n"
.text
.globl _Z4savePfiiPc
.type _Z4savePfiiPc, @function
_Z4savePfiiPc:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movl %esi, %r14d
movl %esi, 28(%rsp)
movl %edx, %r15d
movq %rcx, %rdi
leaq .LC1(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl %r14d, %ecx
leaq .LC2(%rip), %rbx
movq %rbx, %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %ecx
movq %rbx, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %r14d, %r14d
jle .L35
movl $0, 24(%rsp)
movl $0, 16(%rsp)
jmp .L36
.L37:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %r14, %rbx
je .L38
.L39:
cmpq %r12, %rbx
jne .L37
movl 20(%rsp), %eax
addl %ebx, %eax
cltq
movq 8(%rsp), %rcx
pxor %xmm0, %xmm0
cvtss2sd (%rcx,%rax,4), %xmm0
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L38:
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 16(%rsp)
movl 16(%rsp), %eax
addl %r15d, 24(%rsp)
cmpl %eax, 28(%rsp)
je .L35
.L36:
testl %r15d, %r15d
jle .L38
movl 24(%rsp), %eax
movl %eax, 20(%rsp)
leal -1(%r15), %r12d
movslq %r15d, %r14
cltq
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %r13
movl $0, %ebx
jmp .L39
.L35:
movq %rbp, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z4savePfiiPc, .-_Z4savePfiiPc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "---------------print matrix--------------\n"
.section .rodata.str1.1
.LC8:
.string "%f "
.LC9:
.string "\n"
.text
.globl _Z5printPfii
.type _Z5printPfii, @function
_Z5printPfii:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L44
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC8(%rip), %r12
jmp .L46
.L48:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L47:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
.L49:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L44
.L46:
testl %r15d, %r15d
jg .L48
jmp .L49
.L44:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z5printPfii, .-_Z5printPfii
.section .rodata.str1.1
.LC10:
.string "Error opening file!\n"
.LC11:
.string "resultado de %d :%f\n"
.LC12:
.string "%f\n"
.text
.globl _Z7guardarPfiPc
.type _Z7guardarPfiPc, @function
_Z7guardarPfiPc:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movl %esi, %r13d
movq %rdx, %rdi
leaq .LC1(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movl %r13d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
testq %r12, %r12
je .L53
movl $0, %ebp
leaq .LC11(%rip), %r14
leaq .LC12(%rip), %r15
testl %r13d, %r13d
jg .L57
jmp .L55
.L53:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
.L57:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %r13d, %ebp
jne .L56
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L55:
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _Z7guardarPfiPc, .-_Z7guardarPfiPc
.globl _Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_
.type _Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_, @function
_Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_:
.LFB3700:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12multGPUSHAREPfiiS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_, .-_Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_
.globl _Z12multGPUSHAREPfiiS_iiS_
.type _Z12multGPUSHAREPfiiS_iiS_, @function
_Z12multGPUSHAREPfiiS_iiS_:
.LFB3701:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z12multGPUSHAREPfiiS_iiS_, .-_Z12multGPUSHAREPfiiS_iiS_
.globl _Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_
.type _Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_, @function
_Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_:
.LFB3702:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7multGPUPfiiS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_, .-_Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_
.globl _Z7multGPUPfiiS_iiS_
.type _Z7multGPUPfiiS_iiS_, @function
_Z7multGPUPfiiS_iiS_:
.LFB3703:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z7multGPUPfiiS_iiS_, .-_Z7multGPUPfiiS_iiS_
.section .rodata.str1.8
.align 8
.LC13:
.string "Must be called with the names of the files\n"
.section .rodata.str1.1
.LC14:
.string "%d numero de GPUS\n"
.LC15:
.string "nombre %s\n"
.LC16:
.string " Global memory: "
.LC17:
.string "mb"
.LC18:
.string " Shared memory: "
.LC19:
.string "kb"
.LC20:
.string " Constant memory: "
.LC21:
.string " Block registers: "
.LC22:
.string " Warp size: "
.LC23:
.string " Threads per block: "
.LC24:
.string " Max block dimensions: [ "
.LC25:
.string ", "
.LC26:
.string " ]"
.LC27:
.string " Max grid dimensions: [ "
.LC28:
.string "selecione dispositivo"
.LC29:
.string "%d"
.LC30:
.string "r"
.section .rodata.str1.8
.align 8
.LC32:
.string "El tiempo transcurrido en la CPU fue %lf segundos.\n"
.align 8
.LC33:
.string "Error, no se pueden multiplicar"
.align 8
.LC34:
.string "Error al asignar memoria a d_A"
.align 8
.LC35:
.string "Error al asignar memoria a d_B"
.align 8
.LC36:
.string "Error al asignar memoria a d_C"
.align 8
.LC37:
.string "Error al asignar memoria a d_s_C"
.align 8
.LC38:
.string "Tiempo trasncurrido en GPU Algoritmo INGENUO: %lf seconds.\n"
.section .rodata.str1.1
.LC39:
.string "Error al multiplicar\n"
.LC40:
.string "tiempo acelerado: %lf\n"
.section .rodata.str1.8
.align 8
.LC41:
.string "Tiempo trasncurrido en GPU_SHEAR: %lf seconds.\n"
.section .rodata.str1.1
.LC42:
.string "tiempos.csv"
.section .rodata.str1.8
.align 8
.LC43:
.string "tiempo acelerado en la cpu vs gpu_shared: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB3675:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
cmpl $3, %edi
je .L77
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L76:
movq 1144(%rsp), %rdx
subq %fs:40, %rdx
jne .L119
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
leaq 32(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 32(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L79
movl $0, %r12d
leaq .LC15(%rip), %r15
leaq .LC16(%rip), %r14
leaq _ZSt5wcout(%rip), %rbx
leaq .LC17(%rip), %r13
.L96:
leaq 112(%rsp), %rbp
movl %r12d, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq 400(%rsp), %rsi
shrq $20, %rsi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L120
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq 408(%rsp), %rsi
shrq $10, %rsi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L121
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movq 464(%rsp), %rsi
shrq $10, %rsi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE9_M_insertImEERS2_T_@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L122
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 416(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L123
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC22(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 420(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L124
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 432(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L125
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 436(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC25(%rip), %rbp
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 440(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 444(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC26(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L126
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
leaq .LC27(%rip), %rsi
movq %rbx, %rdi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 448(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC25(%rip), %rbp
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 452(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rdi
movl 456(%rsp), %esi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEElsEi@PLT
movq %rax, %rdi
leaq .LC26(%rip), %rsi
call _ZStlsIwSt11char_traitsIwEERSt13basic_ostreamIT_T0_ES6_PKc@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rdi
testq %rdi, %rdi
je .L127
movq (%rdi), %rax
movl $10, %esi
call *80(%rax)
movl %eax, %esi
movq %rbp, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE3putEw@PLT
movq %rax, %rdi
call _ZNSt13basic_ostreamIwSt11char_traitsIwEE5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 32(%rsp)
jg .L96
.L79:
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rsi
leaq .LC29(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %edi
call cudaSetDevice@PLT
movq (%rsp), %r14
movq 8(%r14), %rdi
leaq .LC30(%rip), %rbp
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r15
movq 16(%r14), %rdi
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r14
leaq 40(%rsp), %rdx
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 44(%rsp), %rdx
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 48(%rsp), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 52(%rsp), %rdx
movq %rbx, %rsi
movq %r14, (%rsp)
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $120, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl %ebx, %ecx
imull %ebp, %ecx
movslq %ecx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movl 52(%rsp), %r14d
movl %r14d, %ecx
imull 48(%rsp), %ecx
movslq %ecx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
imull %ebx, %r14d
movslq %r14d, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movl %ebp, %ecx
movl %ebx, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z4loadPfP8_IO_FILEii
movl 52(%rsp), %ecx
movl 48(%rsp), %edx
movq (%rsp), %rsi
movq %r12, %rdi
call _Z4loadPfP8_IO_FILEii
movl 48(%rsp), %ecx
cmpl %ecx, 44(%rsp)
jne .L97
movq 8(%rsp), %rax
movq %rax, %rbx
leaq 40(%rax), %r15
.L98:
call clock@PLT
movq %rax, %rbp
subq $8, %rsp
.cfi_def_cfa_offset 1224
pushq %r14
.cfi_def_cfa_offset 1232
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq %r12, %rcx
movl 60(%rsp), %edx
movl 56(%rsp), %esi
movq %r13, %rdi
call _Z7multCPUPfiiS_iiS_
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC31(%rip), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 1216
movsd %xmm0, (%rsp)
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsd2ss (%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r15, %rbx
jne .L98
movl 40(%rsp), %ebx
movl %ebx, %edi
imull 52(%rsp), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
imull 44(%rsp), %ebx
movslq %ebx, %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L128
movl 48(%rsp), %esi
imull 52(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L129
movl 40(%rsp), %esi
imull 52(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L130
movl 40(%rsp), %esi
imull 52(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L131
movl 40(%rsp), %edx
imull 44(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 48(%rsp), %edx
imull 52(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 88(%rsp)
movl $32, 92(%rsp)
movl $1, 96(%rsp)
movl $32, 100(%rsp)
movl $32, 104(%rsp)
movl $1, 108(%rsp)
movl $10, %ebx
leaq .LC38(%rip), %r15
jmp .L105
.L120:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L132
call _ZSt16__throw_bad_castv@PLT
.L132:
call __stack_chk_fail@PLT
.L121:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L133
call _ZSt16__throw_bad_castv@PLT
.L133:
call __stack_chk_fail@PLT
.L122:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L134
call _ZSt16__throw_bad_castv@PLT
.L134:
call __stack_chk_fail@PLT
.L123:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L135
call _ZSt16__throw_bad_castv@PLT
.L135:
call __stack_chk_fail@PLT
.L124:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L136
call _ZSt16__throw_bad_castv@PLT
.L136:
call __stack_chk_fail@PLT
.L125:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L137
call _ZSt16__throw_bad_castv@PLT
.L137:
call __stack_chk_fail@PLT
.L126:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L138
call _ZSt16__throw_bad_castv@PLT
.L138:
call __stack_chk_fail@PLT
.L127:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L139
call _ZSt16__throw_bad_castv@PLT
.L139:
call __stack_chk_fail@PLT
.L97:
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L76
.L128:
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L76
.L129:
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L76
.L130:
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L76
.L131:
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L76
.L141:
subq $8, %rsp
.cfi_def_cfa_offset 1224
pushq 80(%rsp)
.cfi_def_cfa_offset 1232
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq 80(%rsp), %rcx
movl 60(%rsp), %edx
movl 56(%rsp), %esi
movq 72(%rsp), %rdi
call _Z34__device_stub__Z7multGPUPfiiS_iiS_PfiiS_iiS_
addq $16, %rsp
.cfi_def_cfa_offset 1216
.L104:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC31(%rip), %xmm0
movapd %xmm0, %xmm1
movsd %xmm0, 16(%rsp)
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
movapd %xmm1, %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L140
.L105:
call clock@PLT
movq %rax, %rbp
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L104
jmp .L141
.L140:
movl 40(%rsp), %edx
imull 52(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 72(%rsp), %rsi
movq 24(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl 40(%rsp), %edx
movq %r14, %rsi
movq %r15, %rdi
call _Z7comparePfS_ii
testb %al, %al
jne .L106
leaq .LC39(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L108:
leaq .LC41(%rip), %r15
jmp .L107
.L106:
movsd (%rsp), %xmm0
divsd 16(%rsp), %xmm0
leaq .LC40(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L108
.L143:
subq $8, %rsp
.cfi_def_cfa_offset 1224
pushq 88(%rsp)
.cfi_def_cfa_offset 1232
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq 80(%rsp), %rcx
movl 60(%rsp), %edx
movl 56(%rsp), %esi
movq 72(%rsp), %rdi
call _Z40__device_stub__Z12multGPUSHAREPfiiS_iiS_PfiiS_iiS_
addq $16, %rsp
.cfi_def_cfa_offset 1216
.L109:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC31(%rip), %xmm0
movapd %xmm0, %xmm2
movsd %xmm0, 16(%rsp)
cvtsd2ss %xmm0, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
movapd %xmm2, %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $30, %rbx
je .L142
.L107:
call clock@PLT
movq %rax, %rbp
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L109
jmp .L143
.L142:
movl 40(%rsp), %edx
imull 52(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 72(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC42(%rip), %rdx
movl $30, %esi
movq 8(%rsp), %rdi
call _Z7guardarPfiPc
movl 52(%rsp), %ecx
movl 40(%rsp), %edx
movq %r14, %rsi
movq %rbx, %rdi
call _Z7comparePfS_ii
testb %al, %al
jne .L110
leaq .LC39(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L111:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L76
.L110:
movsd (%rsp), %xmm0
divsd 16(%rsp), %xmm0
leaq .LC43(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L111
.L119:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3675:
.size main, .-main
.section .rodata.str1.1
.LC44:
.string "_Z7multGPUPfiiS_iiS_"
.LC45:
.string "_Z12multGPUSHAREPfiiS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC44(%rip), %rdx
movq %rdx, %rcx
leaq _Z7multGPUPfiiS_iiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC45(%rip), %rdx
movq %rdx, %rcx
leaq _Z12multGPUSHAREPfiiS_iiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC31:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include <stdlib.h>
#include<malloc.h>
#include <time.h>
#include<cuda.h>
#include <iostream>
typedef char* string;
#define HILOSXBLOCK 32 //¿máximo depende de la memorio compartida de la gpu?
//d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C
__global__
void multGPUSHARE(float* A,int filA,int colA,float* B,int filB,int colB,float* C){//filC=filA,colC=colB
//Tamaño total de los elementos con que vamos a trabajar
__shared__ float A_s[HILOSXBLOCK][HILOSXBLOCK];
__shared__ float B_s[HILOSXBLOCK][HILOSXBLOCK];
//Para saber en qué bloque y qué hilo estamos
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = gridDim.x;
int gy = gridDim.y;
//Para el resultado de C
int row = by * HILOSXBLOCK + ty;
int col = bx * HILOSXBLOCK + tx;
float suma = 0;//para llevar la suma de las multiplicaciones
int n = 0, m = 0;
while(m < gx && n < gy){
/* De A queremos sacar las columnas, por eso:
* col = ( ( m * HILOSXBLOCK ) + tx )
* col = ( ( bx * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que m se mueve entre los bloques en el eje x (las columnas)
*/
if(( ( m * HILOSXBLOCK ) + tx ) < colA && row < filA) //Si no se pasa
A_s[ty][tx] = A[ (row * colA) + ( ( m * HILOSXBLOCK ) + tx )];//(Row*colA + k), donde k-> 0..filB (filB = colA)
else A_s[ty][tx] = 0;
/* De B queremos sacar las filas, por eso:
* row = ( ( m * HILOSXBLOCK ) + tx )
* row = ( ( by * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que n se mueve entre los bloques en el eje y (las filas)
*/
if(( n * HILOSXBLOCK + ty) < filB && col < colB)
B_s[ty][tx] = B[( ( n * HILOSXBLOCK + ty) * colB ) + col ];//(k*colB)+Col, donde k-> 0..filB
else B_s[ty][tx] = 0;
m++; n++;
__syncthreads();//espera a todos los hilos
for (int k=0; k < HILOSXBLOCK ; ++k) {
suma += A_s[ty][k] * B_s[k][tx];
}
__syncthreads();
}
if(row < filA && col < colB)
C[ (row * colB) + col] = suma; //C[filA][colB]
}
__global__
void multGPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((col < colsB)&&(row < rowsA)) {
for(int M = 0; M < rowsB; M++) {
C[row * colsB + col]+= A[row * colsA + M] * B[M * colsB + col];
}
}
}
__host__
void multCPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int i, j;
for(i = 0; i < rowsA; i++){
for(j = 0; j< colsB; j++){
for(int M = 0; M < rowsB; M++){
C[i * colsB + j] += A[i * colsA + M] * B[ M * colsB + j];
}
}
}
}
__host__
bool compare(float *A, float *B, int rows, int cols){
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (A[ i * cols + j] != B[i * cols + j]) return false;
}
}
return true;
}
__host__
void load(float *M, FILE *stream, int rows, int cols) {
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
fscanf(stream, "%f,", &M[i * cols + j]);
}
}
fclose(stream);
}
__host__
void save(float *M, int rows, int cols, string file_name) {
FILE *stream;
int i, j;
stream = fopen(file_name, "w");
fprintf(stream, "%d\n", rows);
fprintf(stream, "%d\n", cols);
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (j + 1 == cols) fprintf(stream, "%.2f", M[i * cols + j]);
else fprintf(stream, "%.2f,", M[i * cols + j]);
}
fprintf(stream, "%s\n","");
}
fclose(stream);
}
__host__
void print(float* M, int rows, int cols){
printf("---------------print matrix--------------\n");
for(int i = 0; i < rows; i++) {
for(int j = 0; j < cols; j++) {
printf("%f ", M[i * cols + j]);
}
printf("\n");
}
}
void guardar(float *resultado, int size, string file_name) {
FILE *f = fopen(file_name, "w");
fprintf(f, "%d\n", size);
if (f == NULL) {
printf("Error opening file!\n");
exit(1);
}
int i;
for (i = 0; i < size; i++) {
printf("resultado de %d :%f\n",i,resultado[i] );
if (i + 1 == size) {
fprintf(f, "%f\n", resultado[i]);
} else {
fprintf(f, "%f\n", resultado[i]);
}
}
fclose(f);
}
//asd
int main(int argc, char** argv){
if (argc != 3) {
printf("Must be called with the names of the files\n");
return 1;
}
//--------config gpu-------------------///
int numdiv;
int iddiv;
const int kb = 1024;
const int mb = kb * kb;
cudaGetDeviceCount(&numdiv);
printf("%d numero de GPUS\n",numdiv);
for (int i = 0; i < numdiv; i++) {
cudaDeviceProp propieties;
cudaGetDeviceProperties(&propieties, i);
printf("nombre %s\n",(char*)propieties.name);
std::wcout<<" Global memory: " << propieties.totalGlobalMem / mb << "mb" << std::endl;
std::wcout<<" Shared memory: " << propieties.sharedMemPerBlock / kb << "kb" << std::endl;
std::wcout<<" Constant memory: " << propieties.totalConstMem / kb << "kb" << std::endl;
std::wcout<<" Block registers: " << propieties.regsPerBlock << std::endl;
std::wcout<<" Warp size: " << propieties.warpSize << std::endl;
std::wcout<<" Threads per block: " << propieties.maxThreadsPerBlock << std::endl;
std::wcout<<" Max block dimensions: [ " << propieties.maxThreadsDim[0] << ", " << propieties.maxThreadsDim[1] << ", " << propieties.maxThreadsDim[2] << " ]" << std::endl;
std::wcout<<" Max grid dimensions: [ " << propieties.maxGridSize[0] << ", " << propieties.maxGridSize[1] << ", " << propieties.maxGridSize[2] << " ]" << std::endl;
}
printf("selecione dispositivo");
scanf("%d",&iddiv );
cudaSetDevice(iddiv);
//-------------------------------CPU--------------------------------------
clock_t time_start_cpu, time_end_cpu,time_start_gpu_ing, time_end_gpu_ing,time_start_gpu, time_end_gpu;
float *A, *B, *C, *times;
int rowsA, colsA, rowsB, colsB;
double timeCPU, timeGPU, timeGPUING;
FILE *arc1, *arc2;
arc1 = fopen(argv[1], "r");
arc2 = fopen(argv[2], "r");
fscanf(arc1, "%d", &rowsA);
fscanf(arc1, "%d", &colsA);
fscanf(arc2, "%d", &rowsB);
fscanf(arc2, "%d", &colsB);
//RESERVA MEMORIA EN CPU
times = (float*)malloc(10 * 3 * sizeof(float));
A = (float*)malloc(rowsA * colsA * sizeof(float));
B = (float*)malloc(rowsB * colsB * sizeof(float));
C = (float*)malloc(rowsA * colsB * sizeof(float));
load(A, arc1, rowsA, colsA);
// printf("rowsA: %d\n", rowsA);
// printf("colsA: %d\n", colsA);
// print(A, rowsA, colsA);
load(B, arc2, rowsB, colsB);
// printf("rowsA: %d\n", rowsB);
// printf("colsA: %d\n", colsB);
// print(B, rowsB, colsB);
// tiene que ser iguales filas M2 y col M1
if(colsA==rowsB){
for (int i = 0; i < 10; i++) {
/* code */
time_start_cpu = clock();
multCPU(A, rowsA, colsA, B, rowsB, colsB, C);
time_end_cpu = clock();
timeCPU = ((double)(time_end_cpu-time_start_cpu))/CLOCKS_PER_SEC;
printf ("El tiempo transcurrido en la CPU fue %lf segundos.\n", timeCPU);
times[i]=timeCPU;
}
//imprime(C,filA,colB);
}else{
printf("Error, no se pueden multiplicar");
return 0;
}
// print(C, rowsA, colsB);
// save(C, rowsA, colsB, "CPU.out"); ----------------------------
//-------------------------------GPU INGENUA--------------------------------------
cudaError_t error = cudaSuccess;
float *d_A, *d_B, *d_C, *h_C, *d_s_C;
h_C = (float*)malloc(rowsA * colsB * sizeof(float));
error = cudaMalloc((void**)&d_A,rowsA*colsA*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_A");
return 1;
}
error = cudaMalloc((void**)&d_B,rowsB*colsB*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_B");
return 1;
}
error = cudaMalloc((void**)&d_C,rowsA*colsB*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_C");
return 1;
}
error = cudaMalloc((void**)&d_s_C,rowsA*colsB*sizeof(float));
if (error != cudaSuccess) {
printf("Error al asignar memoria a d_s_C");
return 1;
}
cudaMemcpy(d_A, A, rowsA * colsA * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, rowsB * colsB * sizeof(float), cudaMemcpyHostToDevice); //se copia de origen b a destico d_b
int blockSize = 32;
dim3 dimblock(blockSize, blockSize, 1);
dim3 dimGrid(blockSize, blockSize, 1);
//dim3 dimGrid(ceil((colsB) / float(blockSize), ceil((rowsA) / float(blockSize)), 1);
for(int i=10;i<20;i++){
time_start_gpu_ing = clock();
multGPU<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_C);
cudaDeviceSynchronize();
time_end_gpu_ing = clock();
timeGPUING = ((double)(time_end_gpu_ing-time_start_gpu_ing))/CLOCKS_PER_SEC;
times[i]=timeGPUING;
printf ("Tiempo trasncurrido en GPU Algoritmo INGENUO: %lf seconds.\n", timeGPUING);
}
cudaMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), cudaMemcpyDeviceToHost);
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado: %lf\n", ((double)(timeCPU / timeGPUING)));
// save(h_C, rowsA, colsB, "GPU.out");
}
//-----------------------GPU SHARED --------------------------------------
for(int i=20;i<30;i++){
time_start_gpu = clock();
multGPUSHARE<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C);
cudaDeviceSynchronize();
time_end_gpu = clock();
timeGPU = ((double)(time_end_gpu-time_start_gpu))/CLOCKS_PER_SEC;
times[i]=timeGPU;
printf ("Tiempo trasncurrido en GPU_SHEAR: %lf seconds.\n", timeGPU);
}
cudaMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), cudaMemcpyDeviceToHost);
guardar(times,30,"tiempos.csv");
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado en la cpu vs gpu_shared: %lf\n", (double)(timeCPU / timeGPU));
// save(h_C, rowsA, colsB, "GPU.out");
}
free(A); free(B); free(C); free(h_C);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); cudaFree(d_s_C);
return 0;
} | #include<stdio.h>
#include <stdlib.h>
#include<malloc.h>
#include <time.h>
#include<hip/hip_runtime.h>
#include <iostream>
typedef char* string;
#define HILOSXBLOCK 32 //¿máximo depende de la memorio compartida de la gpu?
//d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C
__global__
void multGPUSHARE(float* A,int filA,int colA,float* B,int filB,int colB,float* C){//filC=filA,colC=colB
//Tamaño total de los elementos con que vamos a trabajar
__shared__ float A_s[HILOSXBLOCK][HILOSXBLOCK];
__shared__ float B_s[HILOSXBLOCK][HILOSXBLOCK];
//Para saber en qué bloque y qué hilo estamos
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = gridDim.x;
int gy = gridDim.y;
//Para el resultado de C
int row = by * HILOSXBLOCK + ty;
int col = bx * HILOSXBLOCK + tx;
float suma = 0;//para llevar la suma de las multiplicaciones
int n = 0, m = 0;
while(m < gx && n < gy){
/* De A queremos sacar las columnas, por eso:
* col = ( ( m * HILOSXBLOCK ) + tx )
* col = ( ( bx * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que m se mueve entre los bloques en el eje x (las columnas)
*/
if(( ( m * HILOSXBLOCK ) + tx ) < colA && row < filA) //Si no se pasa
A_s[ty][tx] = A[ (row * colA) + ( ( m * HILOSXBLOCK ) + tx )];//(Row*colA + k), donde k-> 0..filB (filB = colA)
else A_s[ty][tx] = 0;
/* De B queremos sacar las filas, por eso:
* row = ( ( m * HILOSXBLOCK ) + tx )
* row = ( ( by * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que n se mueve entre los bloques en el eje y (las filas)
*/
if(( n * HILOSXBLOCK + ty) < filB && col < colB)
B_s[ty][tx] = B[( ( n * HILOSXBLOCK + ty) * colB ) + col ];//(k*colB)+Col, donde k-> 0..filB
else B_s[ty][tx] = 0;
m++; n++;
__syncthreads();//espera a todos los hilos
for (int k=0; k < HILOSXBLOCK ; ++k) {
suma += A_s[ty][k] * B_s[k][tx];
}
__syncthreads();
}
if(row < filA && col < colB)
C[ (row * colB) + col] = suma; //C[filA][colB]
}
__global__
void multGPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((col < colsB)&&(row < rowsA)) {
for(int M = 0; M < rowsB; M++) {
C[row * colsB + col]+= A[row * colsA + M] * B[M * colsB + col];
}
}
}
__host__
void multCPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int i, j;
for(i = 0; i < rowsA; i++){
for(j = 0; j< colsB; j++){
for(int M = 0; M < rowsB; M++){
C[i * colsB + j] += A[i * colsA + M] * B[ M * colsB + j];
}
}
}
}
__host__
bool compare(float *A, float *B, int rows, int cols){
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (A[ i * cols + j] != B[i * cols + j]) return false;
}
}
return true;
}
__host__
void load(float *M, FILE *stream, int rows, int cols) {
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
fscanf(stream, "%f,", &M[i * cols + j]);
}
}
fclose(stream);
}
__host__
void save(float *M, int rows, int cols, string file_name) {
FILE *stream;
int i, j;
stream = fopen(file_name, "w");
fprintf(stream, "%d\n", rows);
fprintf(stream, "%d\n", cols);
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (j + 1 == cols) fprintf(stream, "%.2f", M[i * cols + j]);
else fprintf(stream, "%.2f,", M[i * cols + j]);
}
fprintf(stream, "%s\n","");
}
fclose(stream);
}
__host__
void print(float* M, int rows, int cols){
printf("---------------print matrix--------------\n");
for(int i = 0; i < rows; i++) {
for(int j = 0; j < cols; j++) {
printf("%f ", M[i * cols + j]);
}
printf("\n");
}
}
void guardar(float *resultado, int size, string file_name) {
FILE *f = fopen(file_name, "w");
fprintf(f, "%d\n", size);
if (f == NULL) {
printf("Error opening file!\n");
exit(1);
}
int i;
for (i = 0; i < size; i++) {
printf("resultado de %d :%f\n",i,resultado[i] );
if (i + 1 == size) {
fprintf(f, "%f\n", resultado[i]);
} else {
fprintf(f, "%f\n", resultado[i]);
}
}
fclose(f);
}
//asd
int main(int argc, char** argv){
if (argc != 3) {
printf("Must be called with the names of the files\n");
return 1;
}
//--------config gpu-------------------///
int numdiv;
int iddiv;
const int kb = 1024;
const int mb = kb * kb;
hipGetDeviceCount(&numdiv);
printf("%d numero de GPUS\n",numdiv);
for (int i = 0; i < numdiv; i++) {
hipDeviceProp_t propieties;
hipGetDeviceProperties(&propieties, i);
printf("nombre %s\n",(char*)propieties.name);
std::wcout<<" Global memory: " << propieties.totalGlobalMem / mb << "mb" << std::endl;
std::wcout<<" Shared memory: " << propieties.sharedMemPerBlock / kb << "kb" << std::endl;
std::wcout<<" Constant memory: " << propieties.totalConstMem / kb << "kb" << std::endl;
std::wcout<<" Block registers: " << propieties.regsPerBlock << std::endl;
std::wcout<<" Warp size: " << propieties.warpSize << std::endl;
std::wcout<<" Threads per block: " << propieties.maxThreadsPerBlock << std::endl;
std::wcout<<" Max block dimensions: [ " << propieties.maxThreadsDim[0] << ", " << propieties.maxThreadsDim[1] << ", " << propieties.maxThreadsDim[2] << " ]" << std::endl;
std::wcout<<" Max grid dimensions: [ " << propieties.maxGridSize[0] << ", " << propieties.maxGridSize[1] << ", " << propieties.maxGridSize[2] << " ]" << std::endl;
}
printf("selecione dispositivo");
scanf("%d",&iddiv );
hipSetDevice(iddiv);
//-------------------------------CPU--------------------------------------
clock_t time_start_cpu, time_end_cpu,time_start_gpu_ing, time_end_gpu_ing,time_start_gpu, time_end_gpu;
float *A, *B, *C, *times;
int rowsA, colsA, rowsB, colsB;
double timeCPU, timeGPU, timeGPUING;
FILE *arc1, *arc2;
arc1 = fopen(argv[1], "r");
arc2 = fopen(argv[2], "r");
fscanf(arc1, "%d", &rowsA);
fscanf(arc1, "%d", &colsA);
fscanf(arc2, "%d", &rowsB);
fscanf(arc2, "%d", &colsB);
//RESERVA MEMORIA EN CPU
times = (float*)malloc(10 * 3 * sizeof(float));
A = (float*)malloc(rowsA * colsA * sizeof(float));
B = (float*)malloc(rowsB * colsB * sizeof(float));
C = (float*)malloc(rowsA * colsB * sizeof(float));
load(A, arc1, rowsA, colsA);
// printf("rowsA: %d\n", rowsA);
// printf("colsA: %d\n", colsA);
// print(A, rowsA, colsA);
load(B, arc2, rowsB, colsB);
// printf("rowsA: %d\n", rowsB);
// printf("colsA: %d\n", colsB);
// print(B, rowsB, colsB);
// tiene que ser iguales filas M2 y col M1
if(colsA==rowsB){
for (int i = 0; i < 10; i++) {
/* code */
time_start_cpu = clock();
multCPU(A, rowsA, colsA, B, rowsB, colsB, C);
time_end_cpu = clock();
timeCPU = ((double)(time_end_cpu-time_start_cpu))/CLOCKS_PER_SEC;
printf ("El tiempo transcurrido en la CPU fue %lf segundos.\n", timeCPU);
times[i]=timeCPU;
}
//imprime(C,filA,colB);
}else{
printf("Error, no se pueden multiplicar");
return 0;
}
// print(C, rowsA, colsB);
// save(C, rowsA, colsB, "CPU.out"); ----------------------------
//-------------------------------GPU INGENUA--------------------------------------
hipError_t error = hipSuccess;
float *d_A, *d_B, *d_C, *h_C, *d_s_C;
h_C = (float*)malloc(rowsA * colsB * sizeof(float));
error = hipMalloc((void**)&d_A,rowsA*colsA*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_A");
return 1;
}
error = hipMalloc((void**)&d_B,rowsB*colsB*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_B");
return 1;
}
error = hipMalloc((void**)&d_C,rowsA*colsB*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_C");
return 1;
}
error = hipMalloc((void**)&d_s_C,rowsA*colsB*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_s_C");
return 1;
}
hipMemcpy(d_A, A, rowsA * colsA * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, rowsB * colsB * sizeof(float), hipMemcpyHostToDevice); //se copia de origen b a destico d_b
int blockSize = 32;
dim3 dimblock(blockSize, blockSize, 1);
dim3 dimGrid(blockSize, blockSize, 1);
//dim3 dimGrid(ceil((colsB) / float(blockSize), ceil((rowsA) / float(blockSize)), 1);
for(int i=10;i<20;i++){
time_start_gpu_ing = clock();
multGPU<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_C);
hipDeviceSynchronize();
time_end_gpu_ing = clock();
timeGPUING = ((double)(time_end_gpu_ing-time_start_gpu_ing))/CLOCKS_PER_SEC;
times[i]=timeGPUING;
printf ("Tiempo trasncurrido en GPU Algoritmo INGENUO: %lf seconds.\n", timeGPUING);
}
hipMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), hipMemcpyDeviceToHost);
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado: %lf\n", ((double)(timeCPU / timeGPUING)));
// save(h_C, rowsA, colsB, "GPU.out");
}
//-----------------------GPU SHARED --------------------------------------
for(int i=20;i<30;i++){
time_start_gpu = clock();
multGPUSHARE<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C);
hipDeviceSynchronize();
time_end_gpu = clock();
timeGPU = ((double)(time_end_gpu-time_start_gpu))/CLOCKS_PER_SEC;
times[i]=timeGPU;
printf ("Tiempo trasncurrido en GPU_SHEAR: %lf seconds.\n", timeGPU);
}
hipMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), hipMemcpyDeviceToHost);
guardar(times,30,"tiempos.csv");
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado en la cpu vs gpu_shared: %lf\n", (double)(timeCPU / timeGPU));
// save(h_C, rowsA, colsB, "GPU.out");
}
free(A); free(B); free(C); free(h_C);
hipFree(d_A); hipFree(d_B); hipFree(d_C); hipFree(d_s_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include <stdlib.h>
#include<malloc.h>
#include <time.h>
#include<hip/hip_runtime.h>
#include <iostream>
typedef char* string;
#define HILOSXBLOCK 32 //¿máximo depende de la memorio compartida de la gpu?
//d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C
__global__
void multGPUSHARE(float* A,int filA,int colA,float* B,int filB,int colB,float* C){//filC=filA,colC=colB
//Tamaño total de los elementos con que vamos a trabajar
__shared__ float A_s[HILOSXBLOCK][HILOSXBLOCK];
__shared__ float B_s[HILOSXBLOCK][HILOSXBLOCK];
//Para saber en qué bloque y qué hilo estamos
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = gridDim.x;
int gy = gridDim.y;
//Para el resultado de C
int row = by * HILOSXBLOCK + ty;
int col = bx * HILOSXBLOCK + tx;
float suma = 0;//para llevar la suma de las multiplicaciones
int n = 0, m = 0;
while(m < gx && n < gy){
/* De A queremos sacar las columnas, por eso:
* col = ( ( m * HILOSXBLOCK ) + tx )
* col = ( ( bx * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que m se mueve entre los bloques en el eje x (las columnas)
*/
if(( ( m * HILOSXBLOCK ) + tx ) < colA && row < filA) //Si no se pasa
A_s[ty][tx] = A[ (row * colA) + ( ( m * HILOSXBLOCK ) + tx )];//(Row*colA + k), donde k-> 0..filB (filB = colA)
else A_s[ty][tx] = 0;
/* De B queremos sacar las filas, por eso:
* row = ( ( m * HILOSXBLOCK ) + tx )
* row = ( ( by * HILOSXBLOCK ) + tx )
* Hacemos la comparación entre ambas.
* Vemos que n se mueve entre los bloques en el eje y (las filas)
*/
if(( n * HILOSXBLOCK + ty) < filB && col < colB)
B_s[ty][tx] = B[( ( n * HILOSXBLOCK + ty) * colB ) + col ];//(k*colB)+Col, donde k-> 0..filB
else B_s[ty][tx] = 0;
m++; n++;
__syncthreads();//espera a todos los hilos
for (int k=0; k < HILOSXBLOCK ; ++k) {
suma += A_s[ty][k] * B_s[k][tx];
}
__syncthreads();
}
if(row < filA && col < colB)
C[ (row * colB) + col] = suma; //C[filA][colB]
}
__global__
void multGPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((col < colsB)&&(row < rowsA)) {
for(int M = 0; M < rowsB; M++) {
C[row * colsB + col]+= A[row * colsA + M] * B[M * colsB + col];
}
}
}
__host__
void multCPU(float* A, int rowsA, int colsA, float* B, int rowsB, int colsB, float* C){
int i, j;
for(i = 0; i < rowsA; i++){
for(j = 0; j< colsB; j++){
for(int M = 0; M < rowsB; M++){
C[i * colsB + j] += A[i * colsA + M] * B[ M * colsB + j];
}
}
}
}
__host__
bool compare(float *A, float *B, int rows, int cols){
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (A[ i * cols + j] != B[i * cols + j]) return false;
}
}
return true;
}
__host__
void load(float *M, FILE *stream, int rows, int cols) {
int i, j;
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
fscanf(stream, "%f,", &M[i * cols + j]);
}
}
fclose(stream);
}
__host__
void save(float *M, int rows, int cols, string file_name) {
FILE *stream;
int i, j;
stream = fopen(file_name, "w");
fprintf(stream, "%d\n", rows);
fprintf(stream, "%d\n", cols);
for(i = 0; i < rows; i++) {
for(j = 0; j < cols; j++) {
if (j + 1 == cols) fprintf(stream, "%.2f", M[i * cols + j]);
else fprintf(stream, "%.2f,", M[i * cols + j]);
}
fprintf(stream, "%s\n","");
}
fclose(stream);
}
__host__
void print(float* M, int rows, int cols){
printf("---------------print matrix--------------\n");
for(int i = 0; i < rows; i++) {
for(int j = 0; j < cols; j++) {
printf("%f ", M[i * cols + j]);
}
printf("\n");
}
}
void guardar(float *resultado, int size, string file_name) {
FILE *f = fopen(file_name, "w");
fprintf(f, "%d\n", size);
if (f == NULL) {
printf("Error opening file!\n");
exit(1);
}
int i;
for (i = 0; i < size; i++) {
printf("resultado de %d :%f\n",i,resultado[i] );
if (i + 1 == size) {
fprintf(f, "%f\n", resultado[i]);
} else {
fprintf(f, "%f\n", resultado[i]);
}
}
fclose(f);
}
//asd
int main(int argc, char** argv){
if (argc != 3) {
printf("Must be called with the names of the files\n");
return 1;
}
//--------config gpu-------------------///
int numdiv;
int iddiv;
const int kb = 1024;
const int mb = kb * kb;
hipGetDeviceCount(&numdiv);
printf("%d numero de GPUS\n",numdiv);
for (int i = 0; i < numdiv; i++) {
hipDeviceProp_t propieties;
hipGetDeviceProperties(&propieties, i);
printf("nombre %s\n",(char*)propieties.name);
std::wcout<<" Global memory: " << propieties.totalGlobalMem / mb << "mb" << std::endl;
std::wcout<<" Shared memory: " << propieties.sharedMemPerBlock / kb << "kb" << std::endl;
std::wcout<<" Constant memory: " << propieties.totalConstMem / kb << "kb" << std::endl;
std::wcout<<" Block registers: " << propieties.regsPerBlock << std::endl;
std::wcout<<" Warp size: " << propieties.warpSize << std::endl;
std::wcout<<" Threads per block: " << propieties.maxThreadsPerBlock << std::endl;
std::wcout<<" Max block dimensions: [ " << propieties.maxThreadsDim[0] << ", " << propieties.maxThreadsDim[1] << ", " << propieties.maxThreadsDim[2] << " ]" << std::endl;
std::wcout<<" Max grid dimensions: [ " << propieties.maxGridSize[0] << ", " << propieties.maxGridSize[1] << ", " << propieties.maxGridSize[2] << " ]" << std::endl;
}
printf("selecione dispositivo");
scanf("%d",&iddiv );
hipSetDevice(iddiv);
//-------------------------------CPU--------------------------------------
clock_t time_start_cpu, time_end_cpu,time_start_gpu_ing, time_end_gpu_ing,time_start_gpu, time_end_gpu;
float *A, *B, *C, *times;
int rowsA, colsA, rowsB, colsB;
double timeCPU, timeGPU, timeGPUING;
FILE *arc1, *arc2;
arc1 = fopen(argv[1], "r");
arc2 = fopen(argv[2], "r");
fscanf(arc1, "%d", &rowsA);
fscanf(arc1, "%d", &colsA);
fscanf(arc2, "%d", &rowsB);
fscanf(arc2, "%d", &colsB);
//RESERVA MEMORIA EN CPU
times = (float*)malloc(10 * 3 * sizeof(float));
A = (float*)malloc(rowsA * colsA * sizeof(float));
B = (float*)malloc(rowsB * colsB * sizeof(float));
C = (float*)malloc(rowsA * colsB * sizeof(float));
load(A, arc1, rowsA, colsA);
// printf("rowsA: %d\n", rowsA);
// printf("colsA: %d\n", colsA);
// print(A, rowsA, colsA);
load(B, arc2, rowsB, colsB);
// printf("rowsA: %d\n", rowsB);
// printf("colsA: %d\n", colsB);
// print(B, rowsB, colsB);
// tiene que ser iguales filas M2 y col M1
if(colsA==rowsB){
for (int i = 0; i < 10; i++) {
/* code */
time_start_cpu = clock();
multCPU(A, rowsA, colsA, B, rowsB, colsB, C);
time_end_cpu = clock();
timeCPU = ((double)(time_end_cpu-time_start_cpu))/CLOCKS_PER_SEC;
printf ("El tiempo transcurrido en la CPU fue %lf segundos.\n", timeCPU);
times[i]=timeCPU;
}
//imprime(C,filA,colB);
}else{
printf("Error, no se pueden multiplicar");
return 0;
}
// print(C, rowsA, colsB);
// save(C, rowsA, colsB, "CPU.out"); ----------------------------
//-------------------------------GPU INGENUA--------------------------------------
hipError_t error = hipSuccess;
float *d_A, *d_B, *d_C, *h_C, *d_s_C;
h_C = (float*)malloc(rowsA * colsB * sizeof(float));
error = hipMalloc((void**)&d_A,rowsA*colsA*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_A");
return 1;
}
error = hipMalloc((void**)&d_B,rowsB*colsB*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_B");
return 1;
}
error = hipMalloc((void**)&d_C,rowsA*colsB*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_C");
return 1;
}
error = hipMalloc((void**)&d_s_C,rowsA*colsB*sizeof(float));
if (error != hipSuccess) {
printf("Error al asignar memoria a d_s_C");
return 1;
}
hipMemcpy(d_A, A, rowsA * colsA * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, rowsB * colsB * sizeof(float), hipMemcpyHostToDevice); //se copia de origen b a destico d_b
int blockSize = 32;
dim3 dimblock(blockSize, blockSize, 1);
dim3 dimGrid(blockSize, blockSize, 1);
//dim3 dimGrid(ceil((colsB) / float(blockSize), ceil((rowsA) / float(blockSize)), 1);
for(int i=10;i<20;i++){
time_start_gpu_ing = clock();
multGPU<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_C);
hipDeviceSynchronize();
time_end_gpu_ing = clock();
timeGPUING = ((double)(time_end_gpu_ing-time_start_gpu_ing))/CLOCKS_PER_SEC;
times[i]=timeGPUING;
printf ("Tiempo trasncurrido en GPU Algoritmo INGENUO: %lf seconds.\n", timeGPUING);
}
hipMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), hipMemcpyDeviceToHost);
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado: %lf\n", ((double)(timeCPU / timeGPUING)));
// save(h_C, rowsA, colsB, "GPU.out");
}
//-----------------------GPU SHARED --------------------------------------
for(int i=20;i<30;i++){
time_start_gpu = clock();
multGPUSHARE<<<dimGrid,dimblock>>>(d_A, rowsA, colsA, d_B, rowsB, colsB, d_s_C);
hipDeviceSynchronize();
time_end_gpu = clock();
timeGPU = ((double)(time_end_gpu-time_start_gpu))/CLOCKS_PER_SEC;
times[i]=timeGPU;
printf ("Tiempo trasncurrido en GPU_SHEAR: %lf seconds.\n", timeGPU);
}
hipMemcpy(h_C, d_C, rowsA * colsB * sizeof(float), hipMemcpyDeviceToHost);
guardar(times,30,"tiempos.csv");
// print(h_C, rowsA, colsB);
if (!compare(h_C, C, rowsA, colsB)) {
printf("Error al multiplicar\n");
} else {
printf("tiempo acelerado en la cpu vs gpu_shared: %lf\n", (double)(timeCPU / timeGPU));
// save(h_C, rowsA, colsB, "GPU.out");
}
free(A); free(B); free(C); free(h_C);
hipFree(d_A); hipFree(d_B); hipFree(d_C); hipFree(d_s_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12multGPUSHAREPfiiS_iiS_
.globl _Z12multGPUSHAREPfiiS_iiS_
.p2align 8
.type _Z12multGPUSHAREPfiiS_iiS_,@function
_Z12multGPUSHAREPfiiS_iiS_:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s10, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 5, v2
v_lshl_add_u32 v0, s14, 5, v3
s_waitcnt lgkmcnt(0)
s_min_i32 s4, s8, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s10, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_13
s_clause 0x3
s_load_b32 s11, s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b32 s12, s[0:1], 0x18
v_lshlrev_b32_e32 v4, 2, v3
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v5, 7, v2
s_min_i32 s8, s8, s9
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v6, 0x1000, v4
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, v5, v4
s_xor_b32 s13, vcc_lo, -1
s_xor_b32 s2, s2, -1
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v9, v6, v5
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v8, v1, s11
.LBB0_2:
v_lshl_add_u32 v11, s9, 5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s11, v11
s_or_b32 s14, vcc_lo, s13
s_and_saveexec_b32 s15, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_4
ds_store_b32 v7, v10
.LBB0_4:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v11, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v11
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s14
v_lshl_add_u32 v11, s9, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v11
s_or_b32 s14, vcc_lo, s2
s_and_saveexec_b32 s15, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_8
ds_store_b32 v9, v10
.LBB0_8:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v11, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v11, v6
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s14, v5
s_add_i32 s14, s14, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 0x80, v11
s_cmpk_eq_i32 s14, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v12, v13
s_cbranch_scc0 .LBB0_11
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_13:
v_cmp_gt_i32_e32 vcc_lo, s10, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12multGPUSHAREPfiiS_iiS_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12multGPUSHAREPfiiS_iiS_, .Lfunc_end0-_Z12multGPUSHAREPfiiS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7multGPUPfiiS_iiS_
.globl _Z7multGPUPfiiS_iiS_
.p2align 8
.type _Z7multGPUPfiiS_iiS_,@function
_Z7multGPUPfiiS_iiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s6, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_cmp_gt_i32 s4, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_3
s_load_b64 s[2:3], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v6, v[2:3], off
s_clause 0x2
s_load_b32 s6, s[0:1], 0xc
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7multGPUPfiiS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7multGPUPfiiS_iiS_, .Lfunc_end1-_Z7multGPUPfiiS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12multGPUSHAREPfiiS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12multGPUSHAREPfiiS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7multGPUPfiiS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7multGPUPfiiS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
void check(cudaError_t e) {
if(e != cudaSuccess) {
printf(cudaGetErrorString(e));
}
}
__global__ void addArrayGPU(int* a, int* b, int* c) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
int ha[] = { 1, 2, 3, 4, 5 };
int hb[] = { 10, 20, 30, 40, 50};
int hc[count];
int *da, *db, *dc;
int size = sizeof(int)*count;
cudaMalloc(&da, size);
cudaMalloc(&db, size);
cudaMalloc(&dc, size);
cudaMemcpy(da, ha, size, cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, size, cudaMemcpyHostToDevice);
addArrayGPU<<<1, count>>>(da, db, dc);
cudaMemcpy(hc, dc, size, cudaMemcpyDeviceToHost);
printf("%d %d %d %d %d",
hc[0],
hc[1],
hc[2],
hc[3],
hc[4]);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | code for sm_80
Function : _Z11addArrayGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
void check(cudaError_t e) {
if(e != cudaSuccess) {
printf(cudaGetErrorString(e));
}
}
__global__ void addArrayGPU(int* a, int* b, int* c) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
int ha[] = { 1, 2, 3, 4, 5 };
int hb[] = { 10, 20, 30, 40, 50};
int hc[count];
int *da, *db, *dc;
int size = sizeof(int)*count;
cudaMalloc(&da, size);
cudaMalloc(&db, size);
cudaMalloc(&dc, size);
cudaMemcpy(da, ha, size, cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, size, cudaMemcpyHostToDevice);
addArrayGPU<<<1, count>>>(da, db, dc);
cudaMemcpy(hc, dc, size, cudaMemcpyDeviceToHost);
printf("%d %d %d %d %d",
hc[0],
hc[1],
hc[2],
hc[3],
hc[4]);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | .file "tmpxft_00063aff_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5check9cudaError
.type _Z5check9cudaError, @function
_Z5check9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5check9cudaError, .-_Z5check9cudaError
.globl _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
.type _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_, @function
_Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11addArrayGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_, .-_Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
.globl _Z11addArrayGPUPiS_S_
.type _Z11addArrayGPUPiS_S_, @function
_Z11addArrayGPUPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11addArrayGPUPiS_S_, .-_Z11addArrayGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d %d %d %d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
movl 136(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 140(%rsp), %r9d
movl 136(%rsp), %r8d
movl 132(%rsp), %ecx
movl 128(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
jmp .L19
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11addArrayGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11addArrayGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
void check(cudaError_t e) {
if(e != cudaSuccess) {
printf(cudaGetErrorString(e));
}
}
__global__ void addArrayGPU(int* a, int* b, int* c) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
int ha[] = { 1, 2, 3, 4, 5 };
int hb[] = { 10, 20, 30, 40, 50};
int hc[count];
int *da, *db, *dc;
int size = sizeof(int)*count;
cudaMalloc(&da, size);
cudaMalloc(&db, size);
cudaMalloc(&dc, size);
cudaMemcpy(da, ha, size, cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, size, cudaMemcpyHostToDevice);
addArrayGPU<<<1, count>>>(da, db, dc);
cudaMemcpy(hc, dc, size, cudaMemcpyDeviceToHost);
printf("%d %d %d %d %d",
hc[0],
hc[1],
hc[2],
hc[3],
hc[4]);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
void check(hipError_t e) {
if(e != hipSuccess) {
printf(hipGetErrorString(e));
}
}
__global__ void addArrayGPU(int* a, int* b, int* c) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
int ha[] = { 1, 2, 3, 4, 5 };
int hb[] = { 10, 20, 30, 40, 50};
int hc[count];
int *da, *db, *dc;
int size = sizeof(int)*count;
hipMalloc(&da, size);
hipMalloc(&db, size);
hipMalloc(&dc, size);
hipMemcpy(da, ha, size, hipMemcpyHostToDevice);
hipMemcpy(db, hb, size, hipMemcpyHostToDevice);
addArrayGPU<<<1, count>>>(da, db, dc);
hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);
printf("%d %d %d %d %d",
hc[0],
hc[1],
hc[2],
hc[3],
hc[4]);
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
void check(hipError_t e) {
if(e != hipSuccess) {
printf(hipGetErrorString(e));
}
}
__global__ void addArrayGPU(int* a, int* b, int* c) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
int ha[] = { 1, 2, 3, 4, 5 };
int hb[] = { 10, 20, 30, 40, 50};
int hc[count];
int *da, *db, *dc;
int size = sizeof(int)*count;
hipMalloc(&da, size);
hipMalloc(&db, size);
hipMalloc(&dc, size);
hipMemcpy(da, ha, size, hipMemcpyHostToDevice);
hipMemcpy(db, hb, size, hipMemcpyHostToDevice);
addArrayGPU<<<1, count>>>(da, db, dc);
hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);
printf("%d %d %d %d %d",
hc[0],
hc[1],
hc[2],
hc[3],
hc[4]);
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11addArrayGPUPiS_S_
.globl _Z11addArrayGPUPiS_S_
.p2align 8
.type _Z11addArrayGPUPiS_S_,@function
_Z11addArrayGPUPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11addArrayGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11addArrayGPUPiS_S_, .Lfunc_end0-_Z11addArrayGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11addArrayGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11addArrayGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
void check(hipError_t e) {
if(e != hipSuccess) {
printf(hipGetErrorString(e));
}
}
__global__ void addArrayGPU(int* a, int* b, int* c) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
int ha[] = { 1, 2, 3, 4, 5 };
int hb[] = { 10, 20, 30, 40, 50};
int hc[count];
int *da, *db, *dc;
int size = sizeof(int)*count;
hipMalloc(&da, size);
hipMalloc(&db, size);
hipMalloc(&dc, size);
hipMemcpy(da, ha, size, hipMemcpyHostToDevice);
hipMemcpy(db, hb, size, hipMemcpyHostToDevice);
addArrayGPU<<<1, count>>>(da, db, dc);
hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);
printf("%d %d %d %d %d",
hc[0],
hc[1],
hc[2],
hc[3],
hc[4]);
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} | .text
.file "main.hip"
.globl _Z5check10hipError_t # -- Begin function _Z5check10hipError_t
.p2align 4, 0x90
.type _Z5check10hipError_t,@function
_Z5check10hipError_t: # @_Z5check10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB0_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_1:
retq
.Lfunc_end0:
.size _Z5check10hipError_t, .Lfunc_end0-_Z5check10hipError_t
.cfi_endproc
# -- End function
.globl _Z26__device_stub__addArrayGPUPiS_S_ # -- Begin function _Z26__device_stub__addArrayGPUPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__addArrayGPUPiS_S_,@function
_Z26__device_stub__addArrayGPUPiS_S_: # @_Z26__device_stub__addArrayGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11addArrayGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__addArrayGPUPiS_S_, .Lfunc_end1-_Z26__device_stub__addArrayGPUPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 160(%rsp)
movl $5, 176(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 128(%rsp)
movl $50, 144(%rsp)
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z11addArrayGPUPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl 36(%rsp), %edx
movl 40(%rsp), %ecx
movl 44(%rsp), %r8d
movl 48(%rsp), %r9d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11addArrayGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11addArrayGPUPiS_S_,@object # @_Z11addArrayGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z11addArrayGPUPiS_S_
.p2align 3, 0x0
_Z11addArrayGPUPiS_S_:
.quad _Z26__device_stub__addArrayGPUPiS_S_
.size _Z11addArrayGPUPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d %d %d %d"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11addArrayGPUPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__addArrayGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11addArrayGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11addArrayGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11addArrayGPUPiS_S_
.globl _Z11addArrayGPUPiS_S_
.p2align 8
.type _Z11addArrayGPUPiS_S_,@function
_Z11addArrayGPUPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11addArrayGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11addArrayGPUPiS_S_, .Lfunc_end0-_Z11addArrayGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11addArrayGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11addArrayGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00063aff_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5check9cudaError
.type _Z5check9cudaError, @function
_Z5check9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5check9cudaError, .-_Z5check9cudaError
.globl _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
.type _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_, @function
_Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11addArrayGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_, .-_Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
.globl _Z11addArrayGPUPiS_S_
.type _Z11addArrayGPUPiS_S_, @function
_Z11addArrayGPUPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11addArrayGPUPiS_S_, .-_Z11addArrayGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d %d %d %d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
movl 136(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 140(%rsp), %r9d
movl 136(%rsp), %r8d
movl 132(%rsp), %ecx
movl 128(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
jmp .L19
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11addArrayGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11addArrayGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z5check10hipError_t # -- Begin function _Z5check10hipError_t
.p2align 4, 0x90
.type _Z5check10hipError_t,@function
_Z5check10hipError_t: # @_Z5check10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB0_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_1:
retq
.Lfunc_end0:
.size _Z5check10hipError_t, .Lfunc_end0-_Z5check10hipError_t
.cfi_endproc
# -- End function
.globl _Z26__device_stub__addArrayGPUPiS_S_ # -- Begin function _Z26__device_stub__addArrayGPUPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__addArrayGPUPiS_S_,@function
_Z26__device_stub__addArrayGPUPiS_S_: # @_Z26__device_stub__addArrayGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11addArrayGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__addArrayGPUPiS_S_, .Lfunc_end1-_Z26__device_stub__addArrayGPUPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 160(%rsp)
movl $5, 176(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 128(%rsp)
movl $50, 144(%rsp)
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z11addArrayGPUPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl 36(%rsp), %edx
movl 40(%rsp), %ecx
movl 44(%rsp), %r8d
movl 48(%rsp), %r9d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11addArrayGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11addArrayGPUPiS_S_,@object # @_Z11addArrayGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z11addArrayGPUPiS_S_
.p2align 3, 0x0
_Z11addArrayGPUPiS_S_:
.quad _Z26__device_stub__addArrayGPUPiS_S_
.size _Z11addArrayGPUPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d %d %d %d"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11addArrayGPUPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__addArrayGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11addArrayGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <vector>
#include <string>
#include <fstream>
using namespace std;
#define N 1024
#define BLOCK_SIZE 16
__global__ void arrMin(int *min, int *A, int *size)
{
__shared__ int sharedMin;
int tid = threadIdx.x;
if (tid == 0)
{
sharedMin = 1000;
}
__syncthreads();
int localMin = 1000;
for (int i = blockIdx.x * blockDim.x + tid; i < *size; i += blockDim.x)
{
int val = A[i];
if (localMin > val)
{
localMin = val;
}
}
atomicMin(&sharedMin, localMin);
__syncthreads();
if (tid == 0)
{
min[blockIdx.x] = sharedMin;
}
}
__global__ void makeB(int *A, int *B, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
{
B[i] = A[i] % 10;
}
}
int main()
{
vector<int> data;
int *A, *B, *min;
int *d_min, *d_A, *d_B, *d_size;
int size;
ifstream infile;
infile.open("inp.txt");
// Read file input and push to vector
if (infile.is_open())
{
while (infile.good())
{
char cNum[10];
infile.getline(cNum, 256, ',');
int num = atoi(cNum);
data.push_back(num);
}
size = data.size() * sizeof(int);
infile.close();
}
else
{
cout << "Error opening file";
}
// Alloc space for host copies
min = (int *)malloc(size);
A = (int *)malloc(size);
B = (int *)malloc(size);
// Alloc space for device copies
cudaMalloc((void **)&d_min, sizeof(int));
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_size, sizeof(int));
// Copy inputs to device
cudaMemcpy(d_A, data.data(), size, cudaMemcpyHostToDevice);
int temp = data.size();
cudaMemcpy(d_size, &temp, sizeof(int), cudaMemcpyHostToDevice);
arrMin<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_min, d_A, d_size);
makeB<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_A, d_B, temp);
cudaDeviceSynchronize();
// Copy result back to host
cudaMemcpy(min, d_min, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_B, size, cudaMemcpyDeviceToHost);
ofstream outfile;
outfile.open("q1a.txt");
if (outfile.is_open())
{
outfile << "The min is " << min[0] << '\n';
outfile.close();
}
else
{
cout << "Error opening file";
}
outfile.open("q1b.txt");
if (outfile.is_open())
{
for (int i = 0; i < data.size(); ++i)
{
outfile << B[i] << ' ';
}
outfile.close();
}
else
{
cout << "Error opening file";
}
cout << '\n';
// Cleanup
free(min);
free(A);
cudaFree(d_min);
cudaFree(d_A);
return 0;
} | code for sm_80
Function : _Z5makeBPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.HI R0, R2, 0x66666667, RZ ; /* 0x6666666702007827 */
/* 0x004fca00078e02ff */
/*00b0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*00c0*/ LEA.HI.SX32 R7, R0, R5, 0x1e ; /* 0x0000000500077211 */
/* 0x000fe200078ff2ff */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R7, R7, -0xa, R2 ; /* 0xfffffff607077824 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6arrMinPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0060*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x3e8 ; /* 0x000003e8ff088424 */
/* 0x000fca00078e00ff */
/*0070*/ @!P0 STS [RZ], R8 ; /* 0x00000008ff008388 */
/* 0x0001e80000000800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x1a0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 5.9604644775390625e-05 ; /* 0x000003e8ff047435 */
/* 0x000fc400000001ff */
/*00c0*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*00d0*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000ee20000000000 */
/*00e0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x002fca00078e0200 */
/*00f0*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f26270 */
/*0100*/ @P1 BRA 0x190 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3e8 ; /* 0x000003e8ff047424 */
/* 0x009fe400078e00ff */
/*0120*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f26270 */
/*0170*/ IMNMX R4, R3, R4, PT ; /* 0x0000000403047217 */
/* 0x004fd60003800200 */
/*0180*/ @!P1 BRA 0x120 ; /* 0xffffff9000009947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x009fea0003800000 */
/*01a0*/ REDUX.MIN.S32 UR5, R4 ; /* 0x00000000040573c4 */
/* 0x000e220000010200 */
/*01b0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*01c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*01d0*/ ISETP.EQ.U32.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf22070 */
/*01e0*/ IMAD.U32 R0, RZ, RZ, UR5 ; /* 0x00000005ff007e24 */
/* 0x001fd8000f8e00ff */
/*01f0*/ @P1 ATOMS.MIN.S32 RZ, [RZ], R0 ; /* 0x00000000ffff138c */
/* 0x0001e80000800200 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0230*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0240*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0002 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
#include <string>
#include <fstream>
using namespace std;
#define N 1024
#define BLOCK_SIZE 16
__global__ void arrMin(int *min, int *A, int *size)
{
__shared__ int sharedMin;
int tid = threadIdx.x;
if (tid == 0)
{
sharedMin = 1000;
}
__syncthreads();
int localMin = 1000;
for (int i = blockIdx.x * blockDim.x + tid; i < *size; i += blockDim.x)
{
int val = A[i];
if (localMin > val)
{
localMin = val;
}
}
atomicMin(&sharedMin, localMin);
__syncthreads();
if (tid == 0)
{
min[blockIdx.x] = sharedMin;
}
}
__global__ void makeB(int *A, int *B, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
{
B[i] = A[i] % 10;
}
}
int main()
{
vector<int> data;
int *A, *B, *min;
int *d_min, *d_A, *d_B, *d_size;
int size;
ifstream infile;
infile.open("inp.txt");
// Read file input and push to vector
if (infile.is_open())
{
while (infile.good())
{
char cNum[10];
infile.getline(cNum, 256, ',');
int num = atoi(cNum);
data.push_back(num);
}
size = data.size() * sizeof(int);
infile.close();
}
else
{
cout << "Error opening file";
}
// Alloc space for host copies
min = (int *)malloc(size);
A = (int *)malloc(size);
B = (int *)malloc(size);
// Alloc space for device copies
cudaMalloc((void **)&d_min, sizeof(int));
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_size, sizeof(int));
// Copy inputs to device
cudaMemcpy(d_A, data.data(), size, cudaMemcpyHostToDevice);
int temp = data.size();
cudaMemcpy(d_size, &temp, sizeof(int), cudaMemcpyHostToDevice);
arrMin<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_min, d_A, d_size);
makeB<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_A, d_B, temp);
cudaDeviceSynchronize();
// Copy result back to host
cudaMemcpy(min, d_min, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_B, size, cudaMemcpyDeviceToHost);
ofstream outfile;
outfile.open("q1a.txt");
if (outfile.is_open())
{
outfile << "The min is " << min[0] << '\n';
outfile.close();
}
else
{
cout << "Error opening file";
}
outfile.open("q1b.txt");
if (outfile.is_open())
{
for (int i = 0; i < data.size(); ++i)
{
outfile << B[i] << ' ';
}
outfile.close();
}
else
{
cout << "Error opening file";
}
cout << '\n';
// Cleanup
free(min);
free(A);
cudaFree(d_min);
cudaFree(d_A);
return 0;
} | .file "tmpxft_001b53e8_00000000-6_q1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4176:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4176:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6arrMinPiS_S_PiS_S_
.type _Z29__device_stub__Z6arrMinPiS_S_PiS_S_, @function
_Z29__device_stub__Z6arrMinPiS_S_PiS_S_:
.LFB4198:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6arrMinPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4198:
.size _Z29__device_stub__Z6arrMinPiS_S_PiS_S_, .-_Z29__device_stub__Z6arrMinPiS_S_PiS_S_
.globl _Z6arrMinPiS_S_
.type _Z6arrMinPiS_S_, @function
_Z6arrMinPiS_S_:
.LFB4199:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6arrMinPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4199:
.size _Z6arrMinPiS_S_, .-_Z6arrMinPiS_S_
.globl _Z27__device_stub__Z5makeBPiS_iPiS_i
.type _Z27__device_stub__Z5makeBPiS_iPiS_i, @function
_Z27__device_stub__Z5makeBPiS_iPiS_i:
.LFB4200:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5makeBPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4200:
.size _Z27__device_stub__Z5makeBPiS_iPiS_i, .-_Z27__device_stub__Z5makeBPiS_iPiS_i
.globl _Z5makeBPiS_i
.type _Z5makeBPiS_i, @function
_Z5makeBPiS_i:
.LFB4201:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5makeBPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4201:
.size _Z5makeBPiS_i, .-_Z5makeBPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5makeBPiS_i"
.LC1:
.string "_Z6arrMinPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4203:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5makeBPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6arrMinPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4203:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4529:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L24
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L24:
ret
.cfi_endproc
.LFE4529:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4735:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L44
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L30
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L31
jmp .L38
.L44:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L45:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L33
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L37
.L30:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L38:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L31:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L45
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L35
.L33:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L35:
addq %rbp, %r15
testq %r13, %r13
je .L36
movq 16(%rbx), %rsi
subq %r13, %rsi
.L37:
movq %r13, %rdi
call _ZdlPvm@PLT
.L36:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4735:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC3:
.string "inp.txt"
.LC4:
.string "Error opening file"
.LC5:
.string "q1a.txt"
.LC6:
.string "The min is "
.LC7:
.string "q1b.txt"
.text
.globl main
.type main, @function
main:
.LFB4163:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4163
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1176, %rsp
.cfi_def_cfa_offset 1232
movq %fs:40, %rax
movq %rax, 1160(%rsp)
xorl %eax, %eax
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
leaq 624(%rsp), %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
leaq 624(%rsp), %rdi
movl $8, %edx
leaq .LC3(%rip), %rsi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 744(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L47
cmpl $0, 912(%rsp)
jne .L48
leaq 1150(%rsp), %rbx
jmp .L51
.L75:
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, 68(%rsp)
movq 88(%rsp), %rsi
cmpq 96(%rsp), %rsi
je .L49
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 88(%rsp)
.L50:
cmpl $0, 912(%rsp)
jne .L48
.L51:
leaq 624(%rsp), %rdi
movl $44, %ecx
movl $256, %edx
movq %rbx, %rsi
call _ZNSi7getlineEPclc@PLT
jmp .L75
.L49:
leaq 68(%rsp), %rdx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L50
.L48:
movq 88(%rsp), %rbp
subl 80(%rsp), %ebp
leaq 624(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L52
.L47:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L52:
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq 80(%rsp), %r14
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %r15
movq %r15, %rbx
subq %r14, %rbx
sarq $2, %rbx
movl %ebx, 20(%rsp)
leaq 20(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movq %rbx, %r13
shrq $4, %r13
addl $1, %r13d
movl %r13d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6arrMinPiS_S_PiS_S_
.L53:
movl $16, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r13d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L54
movl 20(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z27__device_stub__Z5makeBPiS_iPiS_i
.L54:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %r13
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 112(%rsp), %rdi
movl $16, %edx
leaq .LC5(%rip), %rsi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 224(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L55
leaq 112(%rsp), %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 0(%r13), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L56
.L55:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L56:
leaq 112(%rsp), %rdi
movl $16, %edx
leaq .LC7(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 224(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L57
cmpq %r15, %r14
je .L58
movl $0, %ebp
leaq 112(%rsp), %r13
jmp .L61
.L76:
movq %rax, %rdi
movb $32, 68(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L59
leaq 68(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L60
.L59:
movl $32, %esi
call _ZNSo3putEc@PLT
.L60:
addq $1, %rbp
cmpq %rbx, %rbp
jnb .L58
.L61:
movl (%r12,%rbp,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
jmp .L76
.L58:
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L62
.L57:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L62:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 624(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L77
movl $0, %eax
addq $1176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L64:
leaq 624(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L65:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 1160(%rsp), %rax
subq %fs:40, %rax
je .L66
call __stack_chk_fail@PLT
.L69:
endbr64
movq %rax, %rbx
jmp .L64
.L68:
endbr64
movq %rax, %rbx
jmp .L65
.L66:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4163:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4163-.LLSDACSB4163
.LLSDACSB4163:
.uleb128 .LEHB0-.LFB4163
.uleb128 .LEHE0-.LEHB0
.uleb128 .L68-.LFB4163
.uleb128 0
.uleb128 .LEHB1-.LFB4163
.uleb128 .LEHE1-.LEHB1
.uleb128 .L69-.LFB4163
.uleb128 0
.uleb128 .LEHB2-.LFB4163
.uleb128 .LEHE2-.LEHB2
.uleb128 .L70-.LFB4163
.uleb128 0
.uleb128 .LEHB3-.LFB4163
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4163:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
#include <string>
#include <fstream>
using namespace std;
#define N 1024
#define BLOCK_SIZE 16
__global__ void arrMin(int *min, int *A, int *size)
{
__shared__ int sharedMin;
int tid = threadIdx.x;
if (tid == 0)
{
sharedMin = 1000;
}
__syncthreads();
int localMin = 1000;
for (int i = blockIdx.x * blockDim.x + tid; i < *size; i += blockDim.x)
{
int val = A[i];
if (localMin > val)
{
localMin = val;
}
}
atomicMin(&sharedMin, localMin);
__syncthreads();
if (tid == 0)
{
min[blockIdx.x] = sharedMin;
}
}
__global__ void makeB(int *A, int *B, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
{
B[i] = A[i] % 10;
}
}
int main()
{
vector<int> data;
int *A, *B, *min;
int *d_min, *d_A, *d_B, *d_size;
int size;
ifstream infile;
infile.open("inp.txt");
// Read file input and push to vector
if (infile.is_open())
{
while (infile.good())
{
char cNum[10];
infile.getline(cNum, 256, ',');
int num = atoi(cNum);
data.push_back(num);
}
size = data.size() * sizeof(int);
infile.close();
}
else
{
cout << "Error opening file";
}
// Alloc space for host copies
min = (int *)malloc(size);
A = (int *)malloc(size);
B = (int *)malloc(size);
// Alloc space for device copies
cudaMalloc((void **)&d_min, sizeof(int));
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_size, sizeof(int));
// Copy inputs to device
cudaMemcpy(d_A, data.data(), size, cudaMemcpyHostToDevice);
int temp = data.size();
cudaMemcpy(d_size, &temp, sizeof(int), cudaMemcpyHostToDevice);
arrMin<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_min, d_A, d_size);
makeB<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_A, d_B, temp);
cudaDeviceSynchronize();
// Copy result back to host
cudaMemcpy(min, d_min, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_B, size, cudaMemcpyDeviceToHost);
ofstream outfile;
outfile.open("q1a.txt");
if (outfile.is_open())
{
outfile << "The min is " << min[0] << '\n';
outfile.close();
}
else
{
cout << "Error opening file";
}
outfile.open("q1b.txt");
if (outfile.is_open())
{
for (int i = 0; i < data.size(); ++i)
{
outfile << B[i] << ' ';
}
outfile.close();
}
else
{
cout << "Error opening file";
}
cout << '\n';
// Cleanup
free(min);
free(A);
cudaFree(d_min);
cudaFree(d_A);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <string>
#include <fstream>
using namespace std;
#define N 1024
#define BLOCK_SIZE 16
__global__ void arrMin(int *min, int *A, int *size)
{
__shared__ int sharedMin;
int tid = threadIdx.x;
if (tid == 0)
{
sharedMin = 1000;
}
__syncthreads();
int localMin = 1000;
for (int i = blockIdx.x * blockDim.x + tid; i < *size; i += blockDim.x)
{
int val = A[i];
if (localMin > val)
{
localMin = val;
}
}
atomicMin(&sharedMin, localMin);
__syncthreads();
if (tid == 0)
{
min[blockIdx.x] = sharedMin;
}
}
__global__ void makeB(int *A, int *B, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
{
B[i] = A[i] % 10;
}
}
int main()
{
vector<int> data;
int *A, *B, *min;
int *d_min, *d_A, *d_B, *d_size;
int size;
ifstream infile;
infile.open("inp.txt");
// Read file input and push to vector
if (infile.is_open())
{
while (infile.good())
{
char cNum[10];
infile.getline(cNum, 256, ',');
int num = atoi(cNum);
data.push_back(num);
}
size = data.size() * sizeof(int);
infile.close();
}
else
{
cout << "Error opening file";
}
// Alloc space for host copies
min = (int *)malloc(size);
A = (int *)malloc(size);
B = (int *)malloc(size);
// Alloc space for device copies
hipMalloc((void **)&d_min, sizeof(int));
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_size, sizeof(int));
// Copy inputs to device
hipMemcpy(d_A, data.data(), size, hipMemcpyHostToDevice);
int temp = data.size();
hipMemcpy(d_size, &temp, sizeof(int), hipMemcpyHostToDevice);
arrMin<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_min, d_A, d_size);
makeB<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_A, d_B, temp);
hipDeviceSynchronize();
// Copy result back to host
hipMemcpy(min, d_min, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(B, d_B, size, hipMemcpyDeviceToHost);
ofstream outfile;
outfile.open("q1a.txt");
if (outfile.is_open())
{
outfile << "The min is " << min[0] << '\n';
outfile.close();
}
else
{
cout << "Error opening file";
}
outfile.open("q1b.txt");
if (outfile.is_open())
{
for (int i = 0; i < data.size(); ++i)
{
outfile << B[i] << ' ';
}
outfile.close();
}
else
{
cout << "Error opening file";
}
cout << '\n';
// Cleanup
free(min);
free(A);
hipFree(d_min);
hipFree(d_A);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <string>
#include <fstream>
using namespace std;
#define N 1024
#define BLOCK_SIZE 16
__global__ void arrMin(int *min, int *A, int *size)
{
__shared__ int sharedMin;
int tid = threadIdx.x;
if (tid == 0)
{
sharedMin = 1000;
}
__syncthreads();
int localMin = 1000;
for (int i = blockIdx.x * blockDim.x + tid; i < *size; i += blockDim.x)
{
int val = A[i];
if (localMin > val)
{
localMin = val;
}
}
atomicMin(&sharedMin, localMin);
__syncthreads();
if (tid == 0)
{
min[blockIdx.x] = sharedMin;
}
}
__global__ void makeB(int *A, int *B, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
{
B[i] = A[i] % 10;
}
}
int main()
{
vector<int> data;
int *A, *B, *min;
int *d_min, *d_A, *d_B, *d_size;
int size;
ifstream infile;
infile.open("inp.txt");
// Read file input and push to vector
if (infile.is_open())
{
while (infile.good())
{
char cNum[10];
infile.getline(cNum, 256, ',');
int num = atoi(cNum);
data.push_back(num);
}
size = data.size() * sizeof(int);
infile.close();
}
else
{
cout << "Error opening file";
}
// Alloc space for host copies
min = (int *)malloc(size);
A = (int *)malloc(size);
B = (int *)malloc(size);
// Alloc space for device copies
hipMalloc((void **)&d_min, sizeof(int));
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_size, sizeof(int));
// Copy inputs to device
hipMemcpy(d_A, data.data(), size, hipMemcpyHostToDevice);
int temp = data.size();
hipMemcpy(d_size, &temp, sizeof(int), hipMemcpyHostToDevice);
arrMin<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_min, d_A, d_size);
makeB<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_A, d_B, temp);
hipDeviceSynchronize();
// Copy result back to host
hipMemcpy(min, d_min, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(B, d_B, size, hipMemcpyDeviceToHost);
ofstream outfile;
outfile.open("q1a.txt");
if (outfile.is_open())
{
outfile << "The min is " << min[0] << '\n';
outfile.close();
}
else
{
cout << "Error opening file";
}
outfile.open("q1b.txt");
if (outfile.is_open())
{
for (int i = 0; i < data.size(); ++i)
{
outfile << B[i] << ' ';
}
outfile.close();
}
else
{
cout << "Error opening file";
}
cout << '\n';
// Cleanup
free(min);
free(A);
hipFree(d_min);
hipFree(d_A);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6arrMinPiS_S_
.globl _Z6arrMinPiS_S_
.p2align 8
.type _Z6arrMinPiS_S_,@function
_Z6arrMinPiS_S_:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s4, s15
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v1, 0x3e8 :: v_dual_mov_b32 v2, 0
ds_store_b32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s3, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s8, v[0:1]
v_mov_b32_e32 v0, 0x3e8
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v0, 0x3e8
s_mov_b32 s9, 0
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_le_i32_e64 s2, s3, v1
global_load_b32 v2, v[2:3], off
s_or_b32 s9, s2, s9
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v0, v2
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s9
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s2, exec_lo
s_brev_b32 s3, -2
.LBB0_7:
s_ctz_i32_b32 s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s6, v0, s5
s_lshl_b32 s5, 1, s5
s_and_not1_b32 s2, s2, s5
s_delay_alu instid0(VALU_DEP_1)
s_min_i32 s3, s3, s6
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_and_saveexec_b32 s5, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s5
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
ds_min_i32 v0, v1
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6arrMinPiS_S_
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6arrMinPiS_S_, .Lfunc_end0-_Z6arrMinPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5makeBPiS_i
.globl _Z5makeBPiS_i
.p2align 8
.type _Z5makeBPiS_i,@function
_Z5makeBPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v3, v2, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 10
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5makeBPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5makeBPiS_i, .Lfunc_end1-_Z5makeBPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6arrMinPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6arrMinPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5makeBPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5makeBPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <string>
#include <fstream>
using namespace std;
#define N 1024
#define BLOCK_SIZE 16
__global__ void arrMin(int *min, int *A, int *size)
{
__shared__ int sharedMin;
int tid = threadIdx.x;
if (tid == 0)
{
sharedMin = 1000;
}
__syncthreads();
int localMin = 1000;
for (int i = blockIdx.x * blockDim.x + tid; i < *size; i += blockDim.x)
{
int val = A[i];
if (localMin > val)
{
localMin = val;
}
}
atomicMin(&sharedMin, localMin);
__syncthreads();
if (tid == 0)
{
min[blockIdx.x] = sharedMin;
}
}
__global__ void makeB(int *A, int *B, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
{
B[i] = A[i] % 10;
}
}
int main()
{
vector<int> data;
int *A, *B, *min;
int *d_min, *d_A, *d_B, *d_size;
int size;
ifstream infile;
infile.open("inp.txt");
// Read file input and push to vector
if (infile.is_open())
{
while (infile.good())
{
char cNum[10];
infile.getline(cNum, 256, ',');
int num = atoi(cNum);
data.push_back(num);
}
size = data.size() * sizeof(int);
infile.close();
}
else
{
cout << "Error opening file";
}
// Alloc space for host copies
min = (int *)malloc(size);
A = (int *)malloc(size);
B = (int *)malloc(size);
// Alloc space for device copies
hipMalloc((void **)&d_min, sizeof(int));
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_size, sizeof(int));
// Copy inputs to device
hipMemcpy(d_A, data.data(), size, hipMemcpyHostToDevice);
int temp = data.size();
hipMemcpy(d_size, &temp, sizeof(int), hipMemcpyHostToDevice);
arrMin<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_min, d_A, d_size);
makeB<<<data.size() / BLOCK_SIZE + 1, BLOCK_SIZE>>>(d_A, d_B, temp);
hipDeviceSynchronize();
// Copy result back to host
hipMemcpy(min, d_min, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(B, d_B, size, hipMemcpyDeviceToHost);
ofstream outfile;
outfile.open("q1a.txt");
if (outfile.is_open())
{
outfile << "The min is " << min[0] << '\n';
outfile.close();
}
else
{
cout << "Error opening file";
}
outfile.open("q1b.txt");
if (outfile.is_open())
{
for (int i = 0; i < data.size(); ++i)
{
outfile << B[i] << ' ';
}
outfile.close();
}
else
{
cout << "Error opening file";
}
cout << '\n';
// Cleanup
free(min);
free(A);
hipFree(d_min);
hipFree(d_A);
return 0;
} | .text
.file "q1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__arrMinPiS_S_ # -- Begin function _Z21__device_stub__arrMinPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__arrMinPiS_S_,@function
_Z21__device_stub__arrMinPiS_S_: # @_Z21__device_stub__arrMinPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6arrMinPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__arrMinPiS_S_, .Lfunc_end0-_Z21__device_stub__arrMinPiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__makeBPiS_i # -- Begin function _Z20__device_stub__makeBPiS_i
.p2align 4, 0x90
.type _Z20__device_stub__makeBPiS_i,@function
_Z20__device_stub__makeBPiS_i: # @_Z20__device_stub__makeBPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5makeBPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__makeBPiS_i, .Lfunc_end1-_Z20__device_stub__makeBPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1160, %rsp # imm = 0x488
.cfi_def_cfa_offset 1216
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 640(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
.Ltmp1:
# %bb.1:
leaq 656(%rsp), %rdi
xorl %r15d, %r15d
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp4:
# %bb.2: # %.noexc
movq 640(%rsp), %rcx
addq -24(%rcx), %r14
testq %rax, %rax
jne .LBB2_4
# %bb.3:
movl 32(%r14), %r15d
orl $4, %r15d
.LBB2_4: # %.invoke
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.Ltmp5:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl %r15d, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp6:
# %bb.5: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 760(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_38
# %bb.6: # %.preheader123
movq 640(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 672(%rsp,%rax)
je .LBB2_8
# %bb.7:
xorl %r12d, %r12d
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.LBB2_29: # %._crit_edge
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 656(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp16:
# %bb.30: # %.noexc47
movl %r12d, %ebx
subl (%rsp), %ebx # 4-byte Folded Reload
andl $-4, %ebx
testq %rax, %rax
jne .LBB2_39
# %bb.31:
movq 640(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $640, %rdi # imm = 0x280
movl 672(%rsp,%rax), %esi
orl $4, %esi
.Ltmp17:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp18:
jmp .LBB2_39
.LBB2_38:
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.Ltmp7:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp8:
xorl %r12d, %r12d
# implicit-def: $ebx
.LBB2_39: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
movslq %ebx, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp20:
# %bb.40:
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp22:
# %bb.41:
.Ltmp23:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp24:
# %bb.42:
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp26:
# %bb.43:
movq 24(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq (%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp28:
# %bb.44:
movq %r12, %r13
movq (%rsp), %rbx # 8-byte Reload
subq %rbx, %r13
sarq $2, %r13
movl %r13d, 20(%rsp)
movq 112(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 20(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.45:
movq %r13, %rax
shrq $4, %rax
incl %eax
movabsq $4294967296, %r15 # imm = 0x100000000
orq %rax, %r15
.Ltmp32:
.cfi_escape 0x2e, 0x00
movabsq $4294967312, %rdx # imm = 0x100000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp33:
# %bb.46:
testl %eax, %eax
jne .LBB2_49
# %bb.47:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 64(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
.Ltmp34:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp35:
# %bb.48: # %.noexc50
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp36:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z6arrMinPiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp37:
.LBB2_49:
.Ltmp38:
.cfi_escape 0x2e, 0x00
movabsq $4294967312, %rdx # imm = 0x100000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp39:
# %bb.50:
testl %eax, %eax
jne .LBB2_53
# %bb.51:
movq 24(%rsp), %rax
movq 120(%rsp), %rcx
movl 20(%rsp), %edx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl %edx, 48(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
.Ltmp40:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp41:
# %bb.52: # %.noexc58
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp42:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z5makeBPiS_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp43:
.LBB2_53:
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp45:
# %bb.54:
movq 40(%rsp), %rsi
.Ltmp46:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq 32(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.Ltmp47:
# %bb.55:
movq 120(%rsp), %rsi
.Ltmp48:
.cfi_escape 0x2e, 0x00
movq 104(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp49:
# %bb.56:
.Ltmp51:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rbp
movq %rbp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp52:
# %bb.57:
leaq 136(%rsp), %r14
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movq %r14, %rdi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp55:
# %bb.58: # %.noexc61
movq 128(%rsp), %rcx
movq -24(%rcx), %rdi
addq %rbp, %rdi
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_60
# %bb.59:
movl 32(%rdi), %esi
orl $4, %esi
.LBB2_60: # %.invoke151
.Ltmp56:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp57:
# %bb.61: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 240(%rsp), %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_71
# %bb.62:
.Ltmp60:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
movq 32(%rsp), %rax # 8-byte Reload
movl (%rax), %esi
.Ltmp62:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _ZNSolsEi
.Ltmp63:
# %bb.64:
movb $10, 8(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_66
# %bb.65:
.Ltmp64:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp65:
jmp .LBB2_67
.LBB2_71:
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
jmp .LBB2_72
.LBB2_8: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 640(%rsp), %r14
leaq 128(%rsp), %rbp
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
movl %r15d, (%r12)
movq %rbx, (%rsp) # 8-byte Spill
.LBB2_28: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit
# in Loop: Header=BB2_9 Depth=1
addq $4, %r12
movq 640(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 672(%rsp,%rax)
jne .LBB2_29
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movq %rbp, %rsi
movl $44, %ecx
callq _ZNSi7getlineEPclc
.Ltmp10:
# %bb.10: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
cmpq %r13, %r12
jne .LBB2_11
# %bb.12: # in Loop: Header=BB2_9 Depth=1
subq %rbx, %r12
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r12
je .LBB2_13
# %bb.15: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %r12, %r14
sarq $2, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rcx
movabsq $2305843009213693951, %r13 # imm = 0x1FFFFFFFFFFFFFFF
cmpq %r13, %rcx
jae .LBB2_16
# %bb.17: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
addq %r14, %rax
jae .LBB2_18
.LBB2_19: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
testq %r13, %r13
je .LBB2_20
.LBB2_21: # in Loop: Header=BB2_9 Depth=1
leaq (,%r13,4), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp13:
# %bb.22: # in Loop: Header=BB2_9 Depth=1
movq %rax, %rbp
jmp .LBB2_23
.LBB2_16: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %r13, %rcx
addq %r14, %rax
jb .LBB2_19
.LBB2_18: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %rcx, %r13
testq %r13, %r13
jne .LBB2_21
.LBB2_20: # in Loop: Header=BB2_9 Depth=1
xorl %ebp, %ebp
.LBB2_23: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movl %r15d, (%rbp,%r14,4)
testq %r12, %r12
jle .LBB2_25
# %bb.24: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movq %rbx, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB2_25: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %rbp, (%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB2_27
# %bb.26: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB2_27: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i
# in Loop: Header=BB2_9 Depth=1
movq (%rsp), %rbx # 8-byte Reload
addq %rbx, %r12
leaq (%rbx,%r13,4), %r13
leaq 640(%rsp), %r14
leaq 128(%rsp), %rbp
jmp .LBB2_28
.LBB2_66:
.Ltmp66:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp67:
.LBB2_67: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
.Ltmp68:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp69:
# %bb.68: # %.noexc70
testq %rax, %rax
jne .LBB2_72
# %bb.69:
movq 128(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $128, %rdi
movl 160(%rsp,%rax), %esi
orl $4, %esi
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp71:
.LBB2_72: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp72:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movq %r14, %rdi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp73:
# %bb.73: # %.noexc75
movq 128(%rsp), %rcx
addq -24(%rcx), %rbp
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_75
# %bb.74:
movl 32(%rbp), %esi
orl $4, %esi
.LBB2_75: # %.invoke150
.Ltmp74:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp75:
# %bb.76: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit78
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_88
# %bb.77: # %.preheader
cmpq %rbx, %r12
movq 104(%rsp), %r12 # 8-byte Reload
je .LBB2_82
# %bb.78: # %.lr.ph138.preheader
cmpq $1, %r13
adcq $0, %r13
xorl %ebp, %ebp
leaq 128(%rsp), %r14
leaq 8(%rsp), %r15
jmp .LBB2_79
.p2align 4, 0x90
.LBB2_85: # in Loop: Header=BB2_79 Depth=1
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.Ltmp83:
.LBB2_86: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit87
# in Loop: Header=BB2_79 Depth=1
incq %rbp
cmpq %rbp, %r13
je .LBB2_82
.LBB2_79: # %.lr.ph138
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbp,4), %esi
.Ltmp78:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp79:
# %bb.80: # in Loop: Header=BB2_79 Depth=1
movb $32, 8(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_85
# %bb.81: # in Loop: Header=BB2_79 Depth=1
.Ltmp80:
.cfi_escape 0x2e, 0x00
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp81:
jmp .LBB2_86
.LBB2_88:
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp77:
jmp .LBB2_89
.LBB2_82: # %._crit_edge139
.Ltmp85:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp86:
# %bb.83: # %.noexc80
testq %rax, %rax
jne .LBB2_89
# %bb.84:
movq 128(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $128, %rdi
movl 160(%rsp,%rax), %esi
orl $4, %esi
.Ltmp87:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp88:
.LBB2_89: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit82
movb $10, 8(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB2_91
# %bb.90:
.Ltmp89:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp90:
jmp .LBB2_92
.LBB2_91:
.Ltmp91:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp92:
.LBB2_92: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit94
.cfi_escape 0x2e, 0x00
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi
.Ltmp93:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp94:
# %bb.93:
movq 24(%rsp), %rdi
.Ltmp95:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp96:
# %bb.94:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
leaq 640(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 896(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
testq %rbx, %rbx
je .LBB2_96
# %bb.95:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB2_96: # %_ZNSt6vectorIiSaIiEED2Ev.exit
xorl %eax, %eax
addq $1160, %rsp # imm = 0x488
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 1216
.Ltmp98:
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp99:
# %bb.14: # %.noexc44
.LBB2_70:
.Ltmp53:
movq %rax, %r14
jmp .LBB2_99
.LBB2_32:
.Ltmp2:
movq %rax, %r14
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB2_100
.LBB2_36: # %.loopexit
.Ltmp14:
jmp .LBB2_35
.LBB2_37: # %.loopexit.split-lp
.Ltmp100:
jmp .LBB2_35
.LBB2_34:
.Ltmp11:
.LBB2_35:
movq %rax, %r14
movq %rbx, (%rsp) # 8-byte Spill
jmp .LBB2_99
.LBB2_103:
.Ltmp50:
movq %rax, %r14
jmp .LBB2_99
.LBB2_33:
.Ltmp29:
movq %rax, %r14
jmp .LBB2_99
.LBB2_97:
.Ltmp97:
jmp .LBB2_98
.LBB2_87:
.Ltmp84:
.LBB2_98:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB2_99:
.cfi_escape 0x2e, 0x00
leaq 640(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 896(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB2_100:
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB2_102
# %bb.101:
.cfi_escape 0x2e, 0x00
movq (%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB2_102: # %_ZNSt6vectorIiSaIiEED2Ev.exit97
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp28-.Ltmp3 # Call between .Ltmp3 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp49-.Ltmp30 # Call between .Ltmp30 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin0 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp52-.Ltmp51 # Call between .Ltmp51 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp59-.Ltmp54 # Call between .Ltmp54 and .Ltmp59
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp66-.Ltmp13 # Call between .Ltmp13 and .Ltmp66
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp75-.Ltmp66 # Call between .Ltmp66 and .Ltmp75
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp81-.Ltmp82 # Call between .Ltmp82 and .Ltmp81
.uleb128 .Ltmp84-.Lfunc_begin0 # jumps to .Ltmp84
.byte 0 # On action: cleanup
.uleb128 .Ltmp76-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp96-.Ltmp76 # Call between .Ltmp76 and .Ltmp96
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp98-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp99-.Ltmp98 # Call between .Ltmp98 and .Ltmp99
.uleb128 .Ltmp100-.Lfunc_begin0 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Lfunc_end2-.Ltmp99 # Call between .Ltmp99 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6arrMinPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5makeBPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6arrMinPiS_S_,@object # @_Z6arrMinPiS_S_
.section .rodata,"a",@progbits
.globl _Z6arrMinPiS_S_
.p2align 3, 0x0
_Z6arrMinPiS_S_:
.quad _Z21__device_stub__arrMinPiS_S_
.size _Z6arrMinPiS_S_, 8
.type _Z5makeBPiS_i,@object # @_Z5makeBPiS_i
.globl _Z5makeBPiS_i
.p2align 3, 0x0
_Z5makeBPiS_i:
.quad _Z20__device_stub__makeBPiS_i
.size _Z5makeBPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inp.txt"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error opening file"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "q1a.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The min is "
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "q1b.txt"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "vector::_M_realloc_insert"
.size .L.str.5, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6arrMinPiS_S_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5makeBPiS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__arrMinPiS_S_
.addrsig_sym _Z20__device_stub__makeBPiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6arrMinPiS_S_
.addrsig_sym _Z5makeBPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5makeBPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.HI R0, R2, 0x66666667, RZ ; /* 0x6666666702007827 */
/* 0x004fca00078e02ff */
/*00b0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*00c0*/ LEA.HI.SX32 R7, R0, R5, 0x1e ; /* 0x0000000500077211 */
/* 0x000fe200078ff2ff */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R7, R7, -0xa, R2 ; /* 0xfffffff607077824 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6arrMinPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0060*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x3e8 ; /* 0x000003e8ff088424 */
/* 0x000fca00078e00ff */
/*0070*/ @!P0 STS [RZ], R8 ; /* 0x00000008ff008388 */
/* 0x0001e80000000800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x1a0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 5.9604644775390625e-05 ; /* 0x000003e8ff047435 */
/* 0x000fc400000001ff */
/*00c0*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*00d0*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000ee20000000000 */
/*00e0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x002fca00078e0200 */
/*00f0*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f26270 */
/*0100*/ @P1 BRA 0x190 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3e8 ; /* 0x000003e8ff047424 */
/* 0x009fe400078e00ff */
/*0120*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f26270 */
/*0170*/ IMNMX R4, R3, R4, PT ; /* 0x0000000403047217 */
/* 0x004fd60003800200 */
/*0180*/ @!P1 BRA 0x120 ; /* 0xffffff9000009947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x009fea0003800000 */
/*01a0*/ REDUX.MIN.S32 UR5, R4 ; /* 0x00000000040573c4 */
/* 0x000e220000010200 */
/*01b0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*01c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*01d0*/ ISETP.EQ.U32.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf22070 */
/*01e0*/ IMAD.U32 R0, RZ, RZ, UR5 ; /* 0x00000005ff007e24 */
/* 0x001fd8000f8e00ff */
/*01f0*/ @P1 ATOMS.MIN.S32 RZ, [RZ], R0 ; /* 0x00000000ffff138c */
/* 0x0001e80000800200 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0230*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0240*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0002 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6arrMinPiS_S_
.globl _Z6arrMinPiS_S_
.p2align 8
.type _Z6arrMinPiS_S_,@function
_Z6arrMinPiS_S_:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s4, s15
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v1, 0x3e8 :: v_dual_mov_b32 v2, 0
ds_store_b32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s3, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s4, s8, v[0:1]
v_mov_b32_e32 v0, 0x3e8
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v0, 0x3e8
s_mov_b32 s9, 0
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_le_i32_e64 s2, s3, v1
global_load_b32 v2, v[2:3], off
s_or_b32 s9, s2, s9
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v0, v2
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s9
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s2, exec_lo
s_brev_b32 s3, -2
.LBB0_7:
s_ctz_i32_b32 s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s6, v0, s5
s_lshl_b32 s5, 1, s5
s_and_not1_b32 s2, s2, s5
s_delay_alu instid0(VALU_DEP_1)
s_min_i32 s3, s3, s6
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_and_saveexec_b32 s5, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s5
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
ds_min_i32 v0, v1
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6arrMinPiS_S_
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6arrMinPiS_S_, .Lfunc_end0-_Z6arrMinPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5makeBPiS_i
.globl _Z5makeBPiS_i
.p2align 8
.type _Z5makeBPiS_i,@function
_Z5makeBPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v3, v2, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 10
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5makeBPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5makeBPiS_i, .Lfunc_end1-_Z5makeBPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6arrMinPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6arrMinPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5makeBPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5makeBPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b53e8_00000000-6_q1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4176:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4176:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6arrMinPiS_S_PiS_S_
.type _Z29__device_stub__Z6arrMinPiS_S_PiS_S_, @function
_Z29__device_stub__Z6arrMinPiS_S_PiS_S_:
.LFB4198:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6arrMinPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4198:
.size _Z29__device_stub__Z6arrMinPiS_S_PiS_S_, .-_Z29__device_stub__Z6arrMinPiS_S_PiS_S_
.globl _Z6arrMinPiS_S_
.type _Z6arrMinPiS_S_, @function
_Z6arrMinPiS_S_:
.LFB4199:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6arrMinPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4199:
.size _Z6arrMinPiS_S_, .-_Z6arrMinPiS_S_
.globl _Z27__device_stub__Z5makeBPiS_iPiS_i
.type _Z27__device_stub__Z5makeBPiS_iPiS_i, @function
_Z27__device_stub__Z5makeBPiS_iPiS_i:
.LFB4200:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5makeBPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4200:
.size _Z27__device_stub__Z5makeBPiS_iPiS_i, .-_Z27__device_stub__Z5makeBPiS_iPiS_i
.globl _Z5makeBPiS_i
.type _Z5makeBPiS_i, @function
_Z5makeBPiS_i:
.LFB4201:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5makeBPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4201:
.size _Z5makeBPiS_i, .-_Z5makeBPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5makeBPiS_i"
.LC1:
.string "_Z6arrMinPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4203:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5makeBPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6arrMinPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4203:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4529:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L24
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L24:
ret
.cfi_endproc
.LFE4529:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4735:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L44
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L30
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L31
jmp .L38
.L44:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L45:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L33
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L37
.L30:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L38:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L31:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L45
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L35
.L33:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L35:
addq %rbp, %r15
testq %r13, %r13
je .L36
movq 16(%rbx), %rsi
subq %r13, %rsi
.L37:
movq %r13, %rdi
call _ZdlPvm@PLT
.L36:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4735:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC3:
.string "inp.txt"
.LC4:
.string "Error opening file"
.LC5:
.string "q1a.txt"
.LC6:
.string "The min is "
.LC7:
.string "q1b.txt"
.text
.globl main
.type main, @function
main:
.LFB4163:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4163
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1176, %rsp
.cfi_def_cfa_offset 1232
movq %fs:40, %rax
movq %rax, 1160(%rsp)
xorl %eax, %eax
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
leaq 624(%rsp), %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
leaq 624(%rsp), %rdi
movl $8, %edx
leaq .LC3(%rip), %rsi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 744(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L47
cmpl $0, 912(%rsp)
jne .L48
leaq 1150(%rsp), %rbx
jmp .L51
.L75:
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, 68(%rsp)
movq 88(%rsp), %rsi
cmpq 96(%rsp), %rsi
je .L49
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 88(%rsp)
.L50:
cmpl $0, 912(%rsp)
jne .L48
.L51:
leaq 624(%rsp), %rdi
movl $44, %ecx
movl $256, %edx
movq %rbx, %rsi
call _ZNSi7getlineEPclc@PLT
jmp .L75
.L49:
leaq 68(%rsp), %rdx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L50
.L48:
movq 88(%rsp), %rbp
subl 80(%rsp), %ebp
leaq 624(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L52
.L47:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L52:
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq 80(%rsp), %r14
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %r15
movq %r15, %rbx
subq %r14, %rbx
sarq $2, %rbx
movl %ebx, 20(%rsp)
leaq 20(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movq %rbx, %r13
shrq $4, %r13
addl $1, %r13d
movl %r13d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6arrMinPiS_S_PiS_S_
.L53:
movl $16, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r13d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L54
movl 20(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z27__device_stub__Z5makeBPiS_iPiS_i
.L54:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %r13
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 112(%rsp), %rdi
movl $16, %edx
leaq .LC5(%rip), %rsi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 224(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L55
leaq 112(%rsp), %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 0(%r13), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L56
.L55:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L56:
leaq 112(%rsp), %rdi
movl $16, %edx
leaq .LC7(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 224(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L57
cmpq %r15, %r14
je .L58
movl $0, %ebp
leaq 112(%rsp), %r13
jmp .L61
.L76:
movq %rax, %rdi
movb $32, 68(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L59
leaq 68(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L60
.L59:
movl $32, %esi
call _ZNSo3putEc@PLT
.L60:
addq $1, %rbp
cmpq %rbx, %rbp
jnb .L58
.L61:
movl (%r12,%rbp,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
jmp .L76
.L58:
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L62
.L57:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L62:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 624(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L77
movl $0, %eax
addq $1176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L64:
leaq 624(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L65:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 1160(%rsp), %rax
subq %fs:40, %rax
je .L66
call __stack_chk_fail@PLT
.L69:
endbr64
movq %rax, %rbx
jmp .L64
.L68:
endbr64
movq %rax, %rbx
jmp .L65
.L66:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4163:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4163-.LLSDACSB4163
.LLSDACSB4163:
.uleb128 .LEHB0-.LFB4163
.uleb128 .LEHE0-.LEHB0
.uleb128 .L68-.LFB4163
.uleb128 0
.uleb128 .LEHB1-.LFB4163
.uleb128 .LEHE1-.LEHB1
.uleb128 .L69-.LFB4163
.uleb128 0
.uleb128 .LEHB2-.LFB4163
.uleb128 .LEHE2-.LEHB2
.uleb128 .L70-.LFB4163
.uleb128 0
.uleb128 .LEHB3-.LFB4163
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4163:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__arrMinPiS_S_ # -- Begin function _Z21__device_stub__arrMinPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__arrMinPiS_S_,@function
_Z21__device_stub__arrMinPiS_S_: # @_Z21__device_stub__arrMinPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6arrMinPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__arrMinPiS_S_, .Lfunc_end0-_Z21__device_stub__arrMinPiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__makeBPiS_i # -- Begin function _Z20__device_stub__makeBPiS_i
.p2align 4, 0x90
.type _Z20__device_stub__makeBPiS_i,@function
_Z20__device_stub__makeBPiS_i: # @_Z20__device_stub__makeBPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5makeBPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__makeBPiS_i, .Lfunc_end1-_Z20__device_stub__makeBPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1160, %rsp # imm = 0x488
.cfi_def_cfa_offset 1216
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 640(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
.Ltmp1:
# %bb.1:
leaq 656(%rsp), %rdi
xorl %r15d, %r15d
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp4:
# %bb.2: # %.noexc
movq 640(%rsp), %rcx
addq -24(%rcx), %r14
testq %rax, %rax
jne .LBB2_4
# %bb.3:
movl 32(%r14), %r15d
orl $4, %r15d
.LBB2_4: # %.invoke
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.Ltmp5:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl %r15d, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp6:
# %bb.5: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 760(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_38
# %bb.6: # %.preheader123
movq 640(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 672(%rsp,%rax)
je .LBB2_8
# %bb.7:
xorl %r12d, %r12d
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.LBB2_29: # %._crit_edge
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 656(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp16:
# %bb.30: # %.noexc47
movl %r12d, %ebx
subl (%rsp), %ebx # 4-byte Folded Reload
andl $-4, %ebx
testq %rax, %rax
jne .LBB2_39
# %bb.31:
movq 640(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $640, %rdi # imm = 0x280
movl 672(%rsp,%rax), %esi
orl $4, %esi
.Ltmp17:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp18:
jmp .LBB2_39
.LBB2_38:
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.Ltmp7:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp8:
xorl %r12d, %r12d
# implicit-def: $ebx
.LBB2_39: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
movslq %ebx, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp20:
# %bb.40:
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp22:
# %bb.41:
.Ltmp23:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp24:
# %bb.42:
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp26:
# %bb.43:
movq 24(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq (%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp28:
# %bb.44:
movq %r12, %r13
movq (%rsp), %rbx # 8-byte Reload
subq %rbx, %r13
sarq $2, %r13
movl %r13d, 20(%rsp)
movq 112(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 20(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.45:
movq %r13, %rax
shrq $4, %rax
incl %eax
movabsq $4294967296, %r15 # imm = 0x100000000
orq %rax, %r15
.Ltmp32:
.cfi_escape 0x2e, 0x00
movabsq $4294967312, %rdx # imm = 0x100000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp33:
# %bb.46:
testl %eax, %eax
jne .LBB2_49
# %bb.47:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 64(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
.Ltmp34:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp35:
# %bb.48: # %.noexc50
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp36:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z6arrMinPiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp37:
.LBB2_49:
.Ltmp38:
.cfi_escape 0x2e, 0x00
movabsq $4294967312, %rdx # imm = 0x100000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp39:
# %bb.50:
testl %eax, %eax
jne .LBB2_53
# %bb.51:
movq 24(%rsp), %rax
movq 120(%rsp), %rcx
movl 20(%rsp), %edx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl %edx, 48(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
.Ltmp40:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp41:
# %bb.52: # %.noexc58
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp42:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z5makeBPiS_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp43:
.LBB2_53:
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp45:
# %bb.54:
movq 40(%rsp), %rsi
.Ltmp46:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq 32(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.Ltmp47:
# %bb.55:
movq 120(%rsp), %rsi
.Ltmp48:
.cfi_escape 0x2e, 0x00
movq 104(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp49:
# %bb.56:
.Ltmp51:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rbp
movq %rbp, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp52:
# %bb.57:
leaq 136(%rsp), %r14
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movq %r14, %rdi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp55:
# %bb.58: # %.noexc61
movq 128(%rsp), %rcx
movq -24(%rcx), %rdi
addq %rbp, %rdi
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_60
# %bb.59:
movl 32(%rdi), %esi
orl $4, %esi
.LBB2_60: # %.invoke151
.Ltmp56:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp57:
# %bb.61: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
leaq 240(%rsp), %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_71
# %bb.62:
.Ltmp60:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
movq 32(%rsp), %rax # 8-byte Reload
movl (%rax), %esi
.Ltmp62:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _ZNSolsEi
.Ltmp63:
# %bb.64:
movb $10, 8(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_66
# %bb.65:
.Ltmp64:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp65:
jmp .LBB2_67
.LBB2_71:
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
jmp .LBB2_72
.LBB2_8: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 640(%rsp), %r14
leaq 128(%rsp), %rbp
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
movl %r15d, (%r12)
movq %rbx, (%rsp) # 8-byte Spill
.LBB2_28: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit
# in Loop: Header=BB2_9 Depth=1
addq $4, %r12
movq 640(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 672(%rsp,%rax)
jne .LBB2_29
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movq %rbp, %rsi
movl $44, %ecx
callq _ZNSi7getlineEPclc
.Ltmp10:
# %bb.10: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
cmpq %r13, %r12
jne .LBB2_11
# %bb.12: # in Loop: Header=BB2_9 Depth=1
subq %rbx, %r12
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r12
je .LBB2_13
# %bb.15: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %r12, %r14
sarq $2, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rcx
movabsq $2305843009213693951, %r13 # imm = 0x1FFFFFFFFFFFFFFF
cmpq %r13, %rcx
jae .LBB2_16
# %bb.17: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
addq %r14, %rax
jae .LBB2_18
.LBB2_19: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
testq %r13, %r13
je .LBB2_20
.LBB2_21: # in Loop: Header=BB2_9 Depth=1
leaq (,%r13,4), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp13:
# %bb.22: # in Loop: Header=BB2_9 Depth=1
movq %rax, %rbp
jmp .LBB2_23
.LBB2_16: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %r13, %rcx
addq %r14, %rax
jb .LBB2_19
.LBB2_18: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %rcx, %r13
testq %r13, %r13
jne .LBB2_21
.LBB2_20: # in Loop: Header=BB2_9 Depth=1
xorl %ebp, %ebp
.LBB2_23: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movl %r15d, (%rbp,%r14,4)
testq %r12, %r12
jle .LBB2_25
# %bb.24: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movq %rbx, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB2_25: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i
# in Loop: Header=BB2_9 Depth=1
movq %rbp, (%rsp) # 8-byte Spill
testq %rbx, %rbx
je .LBB2_27
# %bb.26: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB2_27: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i
# in Loop: Header=BB2_9 Depth=1
movq (%rsp), %rbx # 8-byte Reload
addq %rbx, %r12
leaq (%rbx,%r13,4), %r13
leaq 640(%rsp), %r14
leaq 128(%rsp), %rbp
jmp .LBB2_28
.LBB2_66:
.Ltmp66:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp67:
.LBB2_67: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
.Ltmp68:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp69:
# %bb.68: # %.noexc70
testq %rax, %rax
jne .LBB2_72
# %bb.69:
movq 128(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $128, %rdi
movl 160(%rsp,%rax), %esi
orl $4, %esi
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp71:
.LBB2_72: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp72:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movq %r14, %rdi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp73:
# %bb.73: # %.noexc75
movq 128(%rsp), %rcx
addq -24(%rcx), %rbp
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_75
# %bb.74:
movl 32(%rbp), %esi
orl $4, %esi
.LBB2_75: # %.invoke150
.Ltmp74:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp75:
# %bb.76: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit78
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_88
# %bb.77: # %.preheader
cmpq %rbx, %r12
movq 104(%rsp), %r12 # 8-byte Reload
je .LBB2_82
# %bb.78: # %.lr.ph138.preheader
cmpq $1, %r13
adcq $0, %r13
xorl %ebp, %ebp
leaq 128(%rsp), %r14
leaq 8(%rsp), %r15
jmp .LBB2_79
.p2align 4, 0x90
.LBB2_85: # in Loop: Header=BB2_79 Depth=1
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.Ltmp83:
.LBB2_86: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit87
# in Loop: Header=BB2_79 Depth=1
incq %rbp
cmpq %rbp, %r13
je .LBB2_82
.LBB2_79: # %.lr.ph138
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbp,4), %esi
.Ltmp78:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp79:
# %bb.80: # in Loop: Header=BB2_79 Depth=1
movb $32, 8(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_85
# %bb.81: # in Loop: Header=BB2_79 Depth=1
.Ltmp80:
.cfi_escape 0x2e, 0x00
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp81:
jmp .LBB2_86
.LBB2_88:
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp77:
jmp .LBB2_89
.LBB2_82: # %._crit_edge139
.Ltmp85:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp86:
# %bb.83: # %.noexc80
testq %rax, %rax
jne .LBB2_89
# %bb.84:
movq 128(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $128, %rdi
movl 160(%rsp,%rax), %esi
orl $4, %esi
.Ltmp87:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp88:
.LBB2_89: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit82
movb $10, 8(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB2_91
# %bb.90:
.Ltmp89:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp90:
jmp .LBB2_92
.LBB2_91:
.Ltmp91:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp92:
.LBB2_92: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit94
.cfi_escape 0x2e, 0x00
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi
.Ltmp93:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp94:
# %bb.93:
movq 24(%rsp), %rdi
.Ltmp95:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp96:
# %bb.94:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
leaq 640(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 896(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
testq %rbx, %rbx
je .LBB2_96
# %bb.95:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB2_96: # %_ZNSt6vectorIiSaIiEED2Ev.exit
xorl %eax, %eax
addq $1160, %rsp # imm = 0x488
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 1216
.Ltmp98:
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp99:
# %bb.14: # %.noexc44
.LBB2_70:
.Ltmp53:
movq %rax, %r14
jmp .LBB2_99
.LBB2_32:
.Ltmp2:
movq %rax, %r14
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB2_100
.LBB2_36: # %.loopexit
.Ltmp14:
jmp .LBB2_35
.LBB2_37: # %.loopexit.split-lp
.Ltmp100:
jmp .LBB2_35
.LBB2_34:
.Ltmp11:
.LBB2_35:
movq %rax, %r14
movq %rbx, (%rsp) # 8-byte Spill
jmp .LBB2_99
.LBB2_103:
.Ltmp50:
movq %rax, %r14
jmp .LBB2_99
.LBB2_33:
.Ltmp29:
movq %rax, %r14
jmp .LBB2_99
.LBB2_97:
.Ltmp97:
jmp .LBB2_98
.LBB2_87:
.Ltmp84:
.LBB2_98:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB2_99:
.cfi_escape 0x2e, 0x00
leaq 640(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 896(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB2_100:
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB2_102
# %bb.101:
.cfi_escape 0x2e, 0x00
movq (%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB2_102: # %_ZNSt6vectorIiSaIiEED2Ev.exit97
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp28-.Ltmp3 # Call between .Ltmp3 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp49-.Ltmp30 # Call between .Ltmp30 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin0 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp52-.Ltmp51 # Call between .Ltmp51 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp59-.Ltmp54 # Call between .Ltmp54 and .Ltmp59
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp66-.Ltmp13 # Call between .Ltmp13 and .Ltmp66
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp75-.Ltmp66 # Call between .Ltmp66 and .Ltmp75
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp81-.Ltmp82 # Call between .Ltmp82 and .Ltmp81
.uleb128 .Ltmp84-.Lfunc_begin0 # jumps to .Ltmp84
.byte 0 # On action: cleanup
.uleb128 .Ltmp76-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp96-.Ltmp76 # Call between .Ltmp76 and .Ltmp96
.uleb128 .Ltmp97-.Lfunc_begin0 # jumps to .Ltmp97
.byte 0 # On action: cleanup
.uleb128 .Ltmp98-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp99-.Ltmp98 # Call between .Ltmp98 and .Ltmp99
.uleb128 .Ltmp100-.Lfunc_begin0 # jumps to .Ltmp100
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Lfunc_end2-.Ltmp99 # Call between .Ltmp99 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6arrMinPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5makeBPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6arrMinPiS_S_,@object # @_Z6arrMinPiS_S_
.section .rodata,"a",@progbits
.globl _Z6arrMinPiS_S_
.p2align 3, 0x0
_Z6arrMinPiS_S_:
.quad _Z21__device_stub__arrMinPiS_S_
.size _Z6arrMinPiS_S_, 8
.type _Z5makeBPiS_i,@object # @_Z5makeBPiS_i
.globl _Z5makeBPiS_i
.p2align 3, 0x0
_Z5makeBPiS_i:
.quad _Z20__device_stub__makeBPiS_i
.size _Z5makeBPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inp.txt"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error opening file"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "q1a.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The min is "
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "q1b.txt"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "vector::_M_realloc_insert"
.size .L.str.5, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6arrMinPiS_S_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5makeBPiS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__arrMinPiS_S_
.addrsig_sym _Z20__device_stub__makeBPiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6arrMinPiS_S_
.addrsig_sym _Z5makeBPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
/****************************************************normalize²Ù×÷*************************************************************/
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
} | code for sm_80
Function : _Z9normalizePfS_ffm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R2, R0.reuse, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f3e0ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000037a10 */
/* 0x000fe40000ffe4ff */
/*0100*/ FSETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0b */
/* 0x004fda0003f06000 */
/*0110*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff070424 */
/* 0x000fca00078e00ff */
/*0120*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FSETP.GEU.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0b */
/* 0x004fda0003f0e000 */
/*0160*/ @!P0 BRA 0x280 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0180*/ BSSY B0, 0x260 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0190*/ FADD R4, R4, -c[0x0][0x170] ; /* 0x80005c0004047621 */
/* 0x000fe40000000000 */
/*01a0*/ FADD R5, R5, -c[0x0][0x170] ; /* 0x80005c0005057621 */
/* 0x000fc80000000000 */
/*01b0*/ MUFU.RCP R0, R5 ; /* 0x0000000500007308 */
/* 0x000e700000001000 */
/*01c0*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000ea20000000000 */
/*01d0*/ FFMA R7, -R5, R0, 1 ; /* 0x3f80000005077423 */
/* 0x003fc80000000100 */
/*01e0*/ FFMA R7, R0, R7, R0 ; /* 0x0000000700077223 */
/* 0x000fc80000000000 */
/*01f0*/ FFMA R0, R4, R7, RZ ; /* 0x0000000704007223 */
/* 0x000fc800000000ff */
/*0200*/ FFMA R6, -R5, R0, R4 ; /* 0x0000000005067223 */
/* 0x000fc80000000104 */
/*0210*/ FFMA R7, R7, R6, R0 ; /* 0x0000000607077223 */
/* 0x000fe20000000000 */
/*0220*/ @!P0 BRA 0x250 ; /* 0x0000002000008947 */
/* 0x004fea0003800000 */
/*0230*/ MOV R0, 0x250 ; /* 0x0000025000007802 */
/* 0x000fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011605 */
/*02b0*/ BSSY B1, 0x900 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*02c0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*02d0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*02e0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0300*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0310*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0340*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0350*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0360*/ @!P0 BRA 0x4e0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0380*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03a0*/ @P0 BRA 0x8e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03b0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*03c0*/ @!P0 BRA 0x8c0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03d0*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*03e0*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*03f0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0400*/ @!P1 BRA !P2, 0x8c0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0410*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0420*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0430*/ @P1 BRA 0x8a0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0450*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0460*/ @P0 BRA 0x870 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0470*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0480*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0490*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*04a0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*04b0*/ @!P0 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004088823 */
/* 0x000fe400000000ff */
/*04c0*/ @!P1 FFMA R9, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005099823 */
/* 0x000fe200000000ff */
/*04d0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*04f0*/ BSSY B2, 0x860 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0500*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0510*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0520*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0530*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*0540*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0550*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*0560*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0570*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*0580*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0590*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*05a0*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*05b0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*05c0*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*05d0*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*05e0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*05f0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0600*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0610*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0620*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0630*/ @!P0 BRA 0x840 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0650*/ @P0 BRA 0x810 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0670*/ @P0 BRA 0x850 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0690*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*06a0*/ @!P0 BRA 0x850 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06b0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*06c0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*06d0*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*06e0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*06f0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0700*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0710*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0730*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0740*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0750*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0760*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0770*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0780*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0790*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07a0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*07b0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*07c0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07d0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07e0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*07f0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x850 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0820*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0830*/ BRA 0x850 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0840*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0850*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0860*/ BRA 0x8f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0880*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0890*/ BRA 0x8f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08a0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*08b0*/ BRA 0x8f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08c0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*08d0*/ BRA 0x8f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08e0*/ FADD.FTZ R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fe40000010000 */
/*08f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0900*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0910*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0920*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0930*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6c004007950 */
/* 0x000fea0003c3ffff */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
/****************************************************normalize²Ù×÷*************************************************************/
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
} | .file "tmpxft_0005d7e8_00000000-6_normalize.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.type _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, @function
_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizePfS_ffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, .-_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.globl _Z9normalizePfS_ffm
.type _Z9normalizePfS_ffm, @function
_Z9normalizePfS_ffm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9normalizePfS_ffm, .-_Z9normalizePfS_ffm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9normalizePfS_ffm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizePfS_ffm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
/****************************************************normalize²Ù×÷*************************************************************/
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
/****************************************************normalize²Ù×÷*************************************************************/
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
/****************************************************normalize²Ù×÷*************************************************************/
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9normalizePfS_ffm
.globl _Z9normalizePfS_ffm
.p2align 8
.type _Z9normalizePfS_ffm,@function
_Z9normalizePfS_ffm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x14
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v3, 1.0
s_waitcnt vmcnt(0)
v_cmpx_nle_f32_e32 s3, v2
s_cbranch_execz .LBB0_5
global_load_b32 v3, v[0:1], off
s_load_b32 s1, s[0:1], 0x10
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, s1, v3
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_subrev_f32_e32 v2, s1, v2
v_sub_f32_e64 v3, s3, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v4, v3, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9normalizePfS_ffm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9normalizePfS_ffm, .Lfunc_end0-_Z9normalizePfS_ffm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9normalizePfS_ffm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9normalizePfS_ffm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
/****************************************************normalize²Ù×÷*************************************************************/
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
} | .text
.file "normalize.hip"
.globl _Z24__device_stub__normalizePfS_ffm # -- Begin function _Z24__device_stub__normalizePfS_ffm
.p2align 4, 0x90
.type _Z24__device_stub__normalizePfS_ffm,@function
_Z24__device_stub__normalizePfS_ffm: # @_Z24__device_stub__normalizePfS_ffm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizePfS_ffm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__normalizePfS_ffm, .Lfunc_end0-_Z24__device_stub__normalizePfS_ffm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizePfS_ffm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9normalizePfS_ffm,@object # @_Z9normalizePfS_ffm
.section .rodata,"a",@progbits
.globl _Z9normalizePfS_ffm
.p2align 3, 0x0
_Z9normalizePfS_ffm:
.quad _Z24__device_stub__normalizePfS_ffm
.size _Z9normalizePfS_ffm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9normalizePfS_ffm"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__normalizePfS_ffm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9normalizePfS_ffm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9normalizePfS_ffm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R2, R0.reuse, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f3e0ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000037a10 */
/* 0x000fe40000ffe4ff */
/*0100*/ FSETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0b */
/* 0x004fda0003f06000 */
/*0110*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff070424 */
/* 0x000fca00078e00ff */
/*0120*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FSETP.GEU.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0b */
/* 0x004fda0003f0e000 */
/*0160*/ @!P0 BRA 0x280 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0180*/ BSSY B0, 0x260 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0190*/ FADD R4, R4, -c[0x0][0x170] ; /* 0x80005c0004047621 */
/* 0x000fe40000000000 */
/*01a0*/ FADD R5, R5, -c[0x0][0x170] ; /* 0x80005c0005057621 */
/* 0x000fc80000000000 */
/*01b0*/ MUFU.RCP R0, R5 ; /* 0x0000000500007308 */
/* 0x000e700000001000 */
/*01c0*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000ea20000000000 */
/*01d0*/ FFMA R7, -R5, R0, 1 ; /* 0x3f80000005077423 */
/* 0x003fc80000000100 */
/*01e0*/ FFMA R7, R0, R7, R0 ; /* 0x0000000700077223 */
/* 0x000fc80000000000 */
/*01f0*/ FFMA R0, R4, R7, RZ ; /* 0x0000000704007223 */
/* 0x000fc800000000ff */
/*0200*/ FFMA R6, -R5, R0, R4 ; /* 0x0000000005067223 */
/* 0x000fc80000000104 */
/*0210*/ FFMA R7, R7, R6, R0 ; /* 0x0000000607077223 */
/* 0x000fe20000000000 */
/*0220*/ @!P0 BRA 0x250 ; /* 0x0000002000008947 */
/* 0x004fea0003800000 */
/*0230*/ MOV R0, 0x250 ; /* 0x0000025000007802 */
/* 0x000fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011605 */
/*02b0*/ BSSY B1, 0x900 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*02c0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*02d0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*02e0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0300*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0310*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0320*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0340*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0350*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0360*/ @!P0 BRA 0x4e0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0380*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03a0*/ @P0 BRA 0x8e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03b0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*03c0*/ @!P0 BRA 0x8c0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03d0*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*03e0*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*03f0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0400*/ @!P1 BRA !P2, 0x8c0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0410*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0420*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0430*/ @P1 BRA 0x8a0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0450*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0460*/ @P0 BRA 0x870 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0470*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0480*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0490*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*04a0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*04b0*/ @!P0 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004088823 */
/* 0x000fe400000000ff */
/*04c0*/ @!P1 FFMA R9, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005099823 */
/* 0x000fe200000000ff */
/*04d0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*04f0*/ BSSY B2, 0x860 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0500*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0510*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0520*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0530*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*0540*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0550*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*0560*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0570*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*0580*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0590*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*05a0*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*05b0*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*05c0*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*05d0*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*05e0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*05f0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0600*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0610*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0620*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0630*/ @!P0 BRA 0x840 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0650*/ @P0 BRA 0x810 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0670*/ @P0 BRA 0x850 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0690*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*06a0*/ @!P0 BRA 0x850 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06b0*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*06c0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*06d0*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*06e0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*06f0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0700*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0710*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0730*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0740*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0750*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0760*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0770*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0780*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0790*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07a0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*07b0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*07c0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07d0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07e0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*07f0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x850 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0820*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0830*/ BRA 0x850 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0840*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0850*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0860*/ BRA 0x8f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0880*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0890*/ BRA 0x8f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08a0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*08b0*/ BRA 0x8f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08c0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*08d0*/ BRA 0x8f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08e0*/ FADD.FTZ R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fe40000010000 */
/*08f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0900*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0910*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0920*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0930*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6c004007950 */
/* 0x000fea0003c3ffff */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9normalizePfS_ffm
.globl _Z9normalizePfS_ffm
.p2align 8
.type _Z9normalizePfS_ffm,@function
_Z9normalizePfS_ffm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x14
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v3, 1.0
s_waitcnt vmcnt(0)
v_cmpx_nle_f32_e32 s3, v2
s_cbranch_execz .LBB0_5
global_load_b32 v3, v[0:1], off
s_load_b32 s1, s[0:1], 0x10
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, s1, v3
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_subrev_f32_e32 v2, s1, v2
v_sub_f32_e64 v3, s3, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v4, v3, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9normalizePfS_ffm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9normalizePfS_ffm, .Lfunc_end0-_Z9normalizePfS_ffm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9normalizePfS_ffm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9normalizePfS_ffm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005d7e8_00000000-6_normalize.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.type _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, @function
_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizePfS_ffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, .-_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.globl _Z9normalizePfS_ffm
.type _Z9normalizePfS_ffm, @function
_Z9normalizePfS_ffm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9normalizePfS_ffm, .-_Z9normalizePfS_ffm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9normalizePfS_ffm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizePfS_ffm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "normalize.hip"
.globl _Z24__device_stub__normalizePfS_ffm # -- Begin function _Z24__device_stub__normalizePfS_ffm
.p2align 4, 0x90
.type _Z24__device_stub__normalizePfS_ffm,@function
_Z24__device_stub__normalizePfS_ffm: # @_Z24__device_stub__normalizePfS_ffm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizePfS_ffm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__normalizePfS_ffm, .Lfunc_end0-_Z24__device_stub__normalizePfS_ffm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizePfS_ffm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9normalizePfS_ffm,@object # @_Z9normalizePfS_ffm
.section .rodata,"a",@progbits
.globl _Z9normalizePfS_ffm
.p2align 3, 0x0
_Z9normalizePfS_ffm:
.quad _Z24__device_stub__normalizePfS_ffm
.size _Z9normalizePfS_ffm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9normalizePfS_ffm"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__normalizePfS_ffm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9normalizePfS_ffm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
__global__ void print()
{
printf("hello from gpu thread %d\n",threadIdx.x);
}
int main()
{
printf("hello from cpu \n");
print<<<1,10>>>();
} | code for sm_80
Function : _Z5printv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
__global__ void print()
{
printf("hello from gpu thread %d\n",threadIdx.x);
}
int main()
{
printf("hello from cpu \n");
print<<<1,10>>>();
} | .file "tmpxft_001281bd_00000000-6_hellworld.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5printvv
.type _Z23__device_stub__Z5printvv, @function
_Z23__device_stub__Z5printvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5printv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z5printvv, .-_Z23__device_stub__Z5printvv
.globl _Z5printv
.type _Z5printv, @function
_Z5printv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5printvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5printv, .-_Z5printv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello from cpu \n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5printvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5printv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5printv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
__global__ void print()
{
printf("hello from gpu thread %d\n",threadIdx.x);
}
int main()
{
printf("hello from cpu \n");
print<<<1,10>>>();
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void print()
{
printf("hello from gpu thread %d\n",threadIdx.x);
}
int main()
{
printf("hello from cpu \n");
print<<<1,10>>>();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void print()
{
printf("hello from gpu thread %d\n",threadIdx.x);
}
int main()
{
printf("hello from cpu \n");
print<<<1,10>>>();
} | .text
.file "hellworld.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__printv # -- Begin function _Z20__device_stub__printv
.p2align 4, 0x90
.type _Z20__device_stub__printv,@function
_Z20__device_stub__printv: # @_Z20__device_stub__printv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5printv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__printv, .Lfunc_end0-_Z20__device_stub__printv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5printv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5printv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5printv,@object # @_Z5printv
.section .rodata,"a",@progbits
.globl _Z5printv
.p2align 3, 0x0
_Z5printv:
.quad _Z20__device_stub__printv
.size _Z5printv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5printv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hello from cpu "
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__printv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5printv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001281bd_00000000-6_hellworld.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5printvv
.type _Z23__device_stub__Z5printvv, @function
_Z23__device_stub__Z5printvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5printv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z5printvv, .-_Z23__device_stub__Z5printvv
.globl _Z5printv
.type _Z5printv, @function
_Z5printv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5printvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5printv, .-_Z5printv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello from cpu \n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5printvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5printv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5printv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hellworld.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__printv # -- Begin function _Z20__device_stub__printv
.p2align 4, 0x90
.type _Z20__device_stub__printv,@function
_Z20__device_stub__printv: # @_Z20__device_stub__printv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5printv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__printv, .Lfunc_end0-_Z20__device_stub__printv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5printv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5printv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5printv,@object # @_Z5printv
.section .rodata,"a",@progbits
.globl _Z5printv
.p2align 3, 0x0
_Z5printv:
.quad _Z20__device_stub__printv
.size _Z5printv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5printv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hello from cpu "
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__printv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5printv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#define __CUDACC_RTC__
#define __CUDACC__
#include <device_functions.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
typedef struct {
int width;
int height;
float* elements;
int step;
} Matrix;
using namespace std;
#define BLOCK_SIZE 4
__global__ void MatrixMulKernel(const Matrix, const Matrix, Matrix);
void MatrixMul(const Matrix A, const Matrix B, Matrix C) {
Matrix d_A;
d_A.width = d_A.step = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaError_t err = cudaMalloc(&d_A.elements, size);
cout << "CUDA malloc A: " << cudaGetErrorString(err) << endl;
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.step = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
err = cudaMalloc(&d_B.elements, size);
cout << "CUDA malloc B: " << cudaGetErrorString(err) << endl;
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.step = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
err = cudaMalloc(&d_C.elements, size);
cout << "CUDA malloc C: " << cudaGetErrorString(err) << endl;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatrixMulKernel <<<dimGrid, dimBlock>>> (d_A, d_B, d_C);
err = cudaThreadSynchronize();
cout << "Run kernel: " << cudaGetErrorString(err) << endl;
err = cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
cout << "Copy C off of device: " << cudaGetErrorString(err) << endl;
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
__device__ float GetElement(const Matrix A, int row, int col) {
return A.elements[row * A.step + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) {
A.elements[row * A.step + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.step = A.step;
Asub.elements = &A.elements[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatrixMulKernel(Matrix A, Matrix B, Matrix C) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0.0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
int main() {
Matrix A, B, C;
int a1, a2, b1, b2;
a1 = BLOCK_SIZE;
a2 = BLOCK_SIZE;
b1 = a2;
b2 = BLOCK_SIZE;
A.height = a1;
A.width = a2;
A.elements = (float*)malloc(A.width * A.height * sizeof(float));
B.height = b1;
B.width = b2;
B.elements = (float*)malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*)malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = rand() % 10;
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = rand() % 10;
MatrixMul(A, B, C);
cout << "---Result of calculating:" << endl;
cout << "Martix A: " << endl;
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
cout << A.elements[i * A.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix B: " << endl;
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
cout << B.elements[i * B.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix C: " << endl;
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
cout << C.elements[i * C.width + j] << " ";
cout << endl;
}
cout << endl;
return 0;
} | code for sm_80
Function : _Z15MatrixMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e640000002500 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000ea20000002200 */
/*0080*/ SHF.R.S32.HI R0, RZ, 0x1f, R0 ; /* 0x0000001fff007819 */
/* 0x000fc60000011400 */
/*0090*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ee20000002100 */
/*00a0*/ LEA.HI R0, R0, c[0x0][0x160], RZ, 0x2 ; /* 0x0000580000007a11 */
/* 0x000fcc00078f10ff */
/*00b0*/ @!P0 BRA 0x900 ; /* 0x0000084000008947 */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R21, RZ, 0x2, R0 ; /* 0x00000002ff157819 */
/* 0x000fe20000011400 */
/*00d0*/ IMAD R18, R3.reuse, c[0x0][0x170], R2.reuse ; /* 0x00005c0003127a24 */
/* 0x14cfe200078e0202 */
/*00e0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.SHL.U32 R7, R3, 0x10, RZ ; /* 0x0000001003077824 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R6, R21.reuse, -0x1, RZ ; /* 0xffffffff15067810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0120*/ LOP3.LUT R0, R21, 0x3, RZ, 0xc0, !PT ; /* 0x0000000315007812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD R7, R2, 0x4, R7 ; /* 0x0000000402077824 */
/* 0x000fe200078e0207 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f26070 */
/*0150*/ IMAD R6, R3, c[0x0][0x188], R2 ; /* 0x0000620003067a24 */
/* 0x000fe200078e0202 */
/*0160*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003f05270 */
/*0170*/ SHF.R.S32.HI R16, RZ, 0x1f, R18 ; /* 0x0000001fff107819 */
/* 0x000fe40000011412 */
/*0180*/ SHF.R.S32.HI R17, RZ, 0x1f, R6 ; /* 0x0000001fff117819 */
/* 0x000fce0000011406 */
/*0190*/ @!P1 BRA 0x6e0 ; /* 0x0000054000009947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff147624 */
/* 0x000fe200078e00ff */
/*01b0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*01c0*/ IADD3 R21, R21, -R0, RZ ; /* 0x8000000015157210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.SHL.U32 R20, R20, 0x4, RZ ; /* 0x0000000414147824 */
/* 0x000fcc00078e00ff */
/*01f0*/ IMAD R8, R5, c[0x0][0x170], R19 ; /* 0x00005c0005087a24 */
/* 0x001fe400078e0213 */
/*0200*/ IMAD R10, R19, c[0x0][0x188], R4 ; /* 0x00006200130a7a24 */
/* 0x002fc600078e0204 */
/*0210*/ SHF.L.U32 R9, R8, 0x2, RZ ; /* 0x0000000208097819 */
/* 0x000fe200000006ff */
/*0220*/ IMAD.SHL.U32 R10, R10, 0x4, RZ ; /* 0x000000040a0a7824 */
/* 0x000fc600078e00ff */
/*0230*/ IADD3 R11, P1, R18, R9, RZ ; /* 0x00000009120b7210 */
/* 0x000fe40007f3e0ff */
/*0240*/ IADD3 R8, P2, R6, R10, RZ ; /* 0x0000000a06087210 */
/* 0x000fe40007f5e0ff */
/*0250*/ LEA.HI.X.SX32 R14, R9, R16, 0x1, P1 ; /* 0x00000010090e7211 */
/* 0x000fe400008f0eff */
/*0260*/ LEA.HI.X.SX32 R9, R10, R17, 0x1, P2 ; /* 0x000000110a097211 */
/* 0x000fe400010f0eff */
/*0270*/ LEA R22, P1, R11, c[0x0][0x168], 0x2 ; /* 0x00005a000b167a11 */
/* 0x000fe400078210ff */
/*0280*/ LEA R12, P2, R8, c[0x0][0x180], 0x2 ; /* 0x00006000080c7a11 */
/* 0x000fc400078410ff */
/*0290*/ LEA.HI.X R23, R11, c[0x0][0x16c], R14, 0x2, P1 ; /* 0x00005b000b177a11 */
/* 0x000fe400008f140e */
/*02a0*/ LEA.HI.X R13, R8, c[0x0][0x184], R9, 0x2, P2 ; /* 0x00006100080d7a11 */
/* 0x000fc600010f1409 */
/*02b0*/ LDG.E R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000ee2000c1e1900 */
/*02d0*/ IMAD.WIDE R24, R20, 0x4, R12 ; /* 0x0000000414187825 */
/* 0x000fc600078e020c */
/*02e0*/ STS [R7], R14 ; /* 0x0000000e07007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R7+0x40], R26 ; /* 0x0000401a07007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R27, [R2.X4+0x40] ; /* 0x00004000021b7984 */
/* 0x000fe80000004800 */
/*0320*/ LDS.128 R8, [R3.X16] ; /* 0x0000000003087984 */
/* 0x000e28000000cc00 */
/*0330*/ LDS R29, [R2.X4+0x50] ; /* 0x00005000021d7984 */
/* 0x000e620000004800 */
/*0340*/ FFMA R28, R27, R8, R15 ; /* 0x000000081b1c7223 */
/* 0x001fc6000000000f */
/*0350*/ LDS R15, [R2.X4+0x60] ; /* 0x00006000020f7984 */
/* 0x000e280000004800 */
/*0360*/ LDS R8, [R2.X4+0x70] ; /* 0x0000700002087984 */
/* 0x000ea80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ LDG.E R27, [R22.64+0x10] ; /* 0x00001004161b7981 */
/* 0x000ee8000c1e1900 */
/*0390*/ LDG.E R26, [R24.64] ; /* 0x00000004181a7981 */
/* 0x000f22000c1e1900 */
/*03a0*/ FFMA R9, R29, R9, R28 ; /* 0x000000091d097223 */
/* 0x002fc8000000001c */
/*03b0*/ FFMA R9, R15, R10, R9 ; /* 0x0000000a0f097223 */
/* 0x001fc80000000009 */
/*03c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x004fe40000000009 */
/*03d0*/ IMAD.WIDE R8, R20, 0x4, R24 ; /* 0x0000000414087825 */
/* 0x000fe200078e0218 */
/*03e0*/ STS [R7], R27 ; /* 0x0000001b07007388 */
/* 0x008fe80000000800 */
/*03f0*/ STS [R7+0x40], R26 ; /* 0x0000401a07007388 */
/* 0x010fe80000000800 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0410*/ LDS R10, [R2.X4+0x40] ; /* 0x00004000020a7984 */
/* 0x000fe80000004800 */
/*0420*/ LDS.128 R12, [R3.X16] ; /* 0x00000000030c7984 */
/* 0x000e28000000cc00 */
/*0430*/ LDS R28, [R2.X4+0x50] ; /* 0x00005000021c7984 */
/* 0x000e620000004800 */
/*0440*/ FFMA R10, R10, R12, R11 ; /* 0x0000000c0a0a7223 */
/* 0x001fc6000000000b */
/*0450*/ LDS R11, [R2.X4+0x60] ; /* 0x00006000020b7984 */
/* 0x000e280000004800 */
/*0460*/ LDS R12, [R2.X4+0x70] ; /* 0x00007000020c7984 */
/* 0x000ea80000004800 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ LDG.E R29, [R22.64+0x20] ; /* 0x00002004161d7981 */
/* 0x000ee8000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R13, R28, R13, R10 ; /* 0x0000000d1c0d7223 */
/* 0x002fc8000000000a */
/*04b0*/ FFMA R14, R11, R14, R13 ; /* 0x0000000e0b0e7223 */
/* 0x001fc8000000000d */
/*04c0*/ FFMA R15, R12, R15, R14 ; /* 0x0000000f0c0f7223 */
/* 0x004fe2000000000e */
/*04d0*/ STS [R7], R29 ; /* 0x0000001d07007388 */
/* 0x008fe80000000800 */
/*04e0*/ STS [R7+0x40], R24 ; /* 0x0000401807007388 */
/* 0x0101e80000000800 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0500*/ IMAD.WIDE R24, R20, 0x4, R8 ; /* 0x0000000414187825 */
/* 0x001fca00078e0208 */
/*0510*/ LDS R12, [R2.X4+0x40] ; /* 0x00004000020c7984 */
/* 0x000fe80000004800 */
/*0520*/ LDS R26, [R2.X4+0x50] ; /* 0x00005000021a7984 */
/* 0x000fe80000004800 */
/*0530*/ LDS R27, [R2.X4+0x60] ; /* 0x00006000021b7984 */
/* 0x000fe80000004800 */
/*0540*/ LDS R28, [R2.X4+0x70] ; /* 0x00007000021c7984 */
/* 0x000fe80000004800 */
/*0550*/ LDS.128 R8, [R3.X16] ; /* 0x0000000003087984 */
/* 0x000e28000000cc00 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0570*/ LDG.E R22, [R22.64+0x30] ; /* 0x0000300416167981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1900 */
/*0590*/ IADD3 R21, R21, -0x4, RZ ; /* 0xfffffffc15157810 */
/* 0x000fc40007ffe0ff */
/*05a0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ ISETP.NE.AND P1, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe20003f25270 */
/*05c0*/ FFMA R8, R12, R8, R15 ; /* 0x000000080c087223 */
/* 0x001fc8000000000f */
/*05d0*/ FFMA R26, R26, R9, R8 ; /* 0x000000091a1a7223 */
/* 0x000fc80000000008 */
/*05e0*/ FFMA R10, R27, R10, R26 ; /* 0x0000000a1b0a7223 */
/* 0x000fc8000000001a */
/*05f0*/ FFMA R10, R28, R11, R10 ; /* 0x0000000b1c0a7223 */
/* 0x000fe2000000000a */
/*0600*/ STS [R7], R22 ; /* 0x0000001607007388 */
/* 0x004fe80000000800 */
/*0610*/ STS [R7+0x40], R24 ; /* 0x0000401807007388 */
/* 0x008fe80000000800 */
/*0620*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0630*/ LDS R29, [R2.X4+0x40] ; /* 0x00004000021d7984 */
/* 0x000fe80000004800 */
/*0640*/ LDS.128 R12, [R3.X16] ; /* 0x00000000030c7984 */
/* 0x000e28000000cc00 */
/*0650*/ LDS R23, [R2.X4+0x50] ; /* 0x0000500002177984 */
/* 0x000e680000004800 */
/*0660*/ LDS R9, [R2.X4+0x60] ; /* 0x0000600002097984 */
/* 0x000ea80000004800 */
/*0670*/ LDS R8, [R2.X4+0x70] ; /* 0x0000700002087984 */
/* 0x000ee20000004800 */
/*0680*/ FFMA R10, R29, R12, R10 ; /* 0x0000000c1d0a7223 */
/* 0x001fc8000000000a */
/*0690*/ FFMA R10, R23, R13, R10 ; /* 0x0000000d170a7223 */
/* 0x002fc8000000000a */
/*06a0*/ FFMA R9, R9, R14, R10 ; /* 0x0000000e09097223 */
/* 0x004fc8000000000a */
/*06b0*/ FFMA R15, R8, R15, R9 ; /* 0x0000000f080f7223 */
/* 0x008fe20000000009 */
/*06c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06d0*/ @P1 BRA 0x1f0 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*06e0*/ @!P0 BRA 0x900 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD R14, R19, c[0x0][0x188], R4 ; /* 0x00006200130e7a24 */
/* 0x002fe400078e0204 */
/*0700*/ IMAD R19, R5, c[0x0][0x170], R19 ; /* 0x00005c0005137a24 */
/* 0x001fc600078e0213 */
/*0710*/ SHF.L.U32 R14, R14, 0x2, RZ ; /* 0x000000020e0e7819 */
/* 0x000fe200000006ff */
/*0720*/ IMAD.SHL.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137824 */
/* 0x000fca00078e00ff */
/*0730*/ IADD3 R10, P0, R18, R19, RZ ; /* 0x00000013120a7210 */
/* 0x000fe40007f1e0ff */
/*0740*/ IADD3 R8, P1, R6, R14, RZ ; /* 0x0000000e06087210 */
/* 0x000fe40007f3e0ff */
/*0750*/ LEA.HI.X.SX32 R11, R19, R16, 0x1, P0 ; /* 0x00000010130b7211 */
/* 0x000fe400000f0eff */
/*0760*/ LEA.HI.X.SX32 R9, R14, R17, 0x1, P1 ; /* 0x000000110e097211 */
/* 0x000fe400008f0eff */
/*0770*/ LEA R12, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a0c7a11 */
/* 0x000fe400078010ff */
/*0780*/ LEA R20, P1, R8, c[0x0][0x180], 0x2 ; /* 0x0000600008147a11 */
/* 0x000fc400078210ff */
/*0790*/ LEA.HI.X R13, R10, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b000a0d7a11 */
/* 0x000fe400000f140b */
/*07a0*/ LEA.HI.X R21, R8, c[0x0][0x184], R9, 0x2, P1 ; /* 0x0000610008157a11 */
/* 0x000fc600008f1409 */
/*07b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0000a8000c1e1900 */
/*07c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee2000c1e1900 */
/*07d0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*07e0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0800*/ MOV R13, c[0x0][0x188] ; /* 0x00006200000d7a02 */
/* 0x001fca0000000f00 */
/*0810*/ IMAD R14, R13, 0x4, R14 ; /* 0x000000040d0e7824 */
/* 0x000fe200078e020e */
/*0820*/ STS [R7], R12 ; /* 0x0000000c07007388 */
/* 0x004fe80000000800 */
/*0830*/ STS [R7+0x40], R20 ; /* 0x0000401407007388 */
/* 0x008fe80000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0850*/ LDS R22, [R2.X4+0x40] ; /* 0x0000400002167984 */
/* 0x000fe80000004800 */
/*0860*/ LDS.128 R8, [R3.X16] ; /* 0x0000000003087984 */
/* 0x000e28000000cc00 */
/*0870*/ LDS R23, [R2.X4+0x50] ; /* 0x0000500002177984 */
/* 0x000e680000004800 */
/*0880*/ LDS R24, [R2.X4+0x60] ; /* 0x0000600002187984 */
/* 0x000ea80000004800 */
/*0890*/ LDS R25, [R2.X4+0x70] ; /* 0x0000700002197984 */
/* 0x000ee20000004800 */
/*08a0*/ FFMA R8, R22, R8, R15 ; /* 0x0000000816087223 */
/* 0x001fc8000000000f */
/*08b0*/ FFMA R9, R23, R9, R8 ; /* 0x0000000917097223 */
/* 0x002fc80000000008 */
/*08c0*/ FFMA R10, R24, R10, R9 ; /* 0x0000000a180a7223 */
/* 0x004fc80000000009 */
/*08d0*/ FFMA R15, R25, R11, R10 ; /* 0x0000000b190f7223 */
/* 0x008fe2000000000a */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ @P0 BRA 0x730 ; /* 0xfffffe3000000947 */
/* 0x000fea000383ffff */
/*0900*/ IMAD R4, R5, c[0x0][0x1a0], R4 ; /* 0x0000680005047a24 */
/* 0x003fe400078e0204 */
/*0910*/ IMAD R2, R3, c[0x0][0x1a0], R2 ; /* 0x0000680003027a24 */
/* 0x00cfc600078e0202 */
/*0920*/ SHF.L.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037819 */
/* 0x000fc800000006ff */
/*0930*/ SHF.R.S32.HI R5, RZ, 0x1f, R3 ; /* 0x0000001fff057819 */
/* 0x000fe40000011403 */
/*0940*/ IADD3 R3, P0, R2, R3, RZ ; /* 0x0000000302037210 */
/* 0x000fc80007f1e0ff */
/*0950*/ LEA.HI.X.SX32 R0, R2, R5, 0x1, P0 ; /* 0x0000000502007211 */
/* 0x000fe400000f0eff */
/*0960*/ LEA R2, P0, R3, c[0x0][0x198], 0x2 ; /* 0x0000660003027a11 */
/* 0x000fc800078010ff */
/*0970*/ LEA.HI.X R3, R3, c[0x0][0x19c], R0, 0x2, P0 ; /* 0x0000670003037a11 */
/* 0x000fca00000f1400 */
/*0980*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#define __CUDACC_RTC__
#define __CUDACC__
#include <device_functions.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
typedef struct {
int width;
int height;
float* elements;
int step;
} Matrix;
using namespace std;
#define BLOCK_SIZE 4
__global__ void MatrixMulKernel(const Matrix, const Matrix, Matrix);
void MatrixMul(const Matrix A, const Matrix B, Matrix C) {
Matrix d_A;
d_A.width = d_A.step = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaError_t err = cudaMalloc(&d_A.elements, size);
cout << "CUDA malloc A: " << cudaGetErrorString(err) << endl;
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.step = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
err = cudaMalloc(&d_B.elements, size);
cout << "CUDA malloc B: " << cudaGetErrorString(err) << endl;
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.step = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
err = cudaMalloc(&d_C.elements, size);
cout << "CUDA malloc C: " << cudaGetErrorString(err) << endl;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatrixMulKernel <<<dimGrid, dimBlock>>> (d_A, d_B, d_C);
err = cudaThreadSynchronize();
cout << "Run kernel: " << cudaGetErrorString(err) << endl;
err = cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
cout << "Copy C off of device: " << cudaGetErrorString(err) << endl;
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
__device__ float GetElement(const Matrix A, int row, int col) {
return A.elements[row * A.step + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) {
A.elements[row * A.step + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.step = A.step;
Asub.elements = &A.elements[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatrixMulKernel(Matrix A, Matrix B, Matrix C) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0.0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
int main() {
Matrix A, B, C;
int a1, a2, b1, b2;
a1 = BLOCK_SIZE;
a2 = BLOCK_SIZE;
b1 = a2;
b2 = BLOCK_SIZE;
A.height = a1;
A.width = a2;
A.elements = (float*)malloc(A.width * A.height * sizeof(float));
B.height = b1;
B.width = b2;
B.elements = (float*)malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*)malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = rand() % 10;
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = rand() % 10;
MatrixMul(A, B, C);
cout << "---Result of calculating:" << endl;
cout << "Martix A: " << endl;
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
cout << A.elements[i * A.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix B: " << endl;
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
cout << B.elements[i * B.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix C: " << endl;
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
cout << C.elements[i * C.width + j] << " ";
cout << endl;
}
cout << endl;
return 0;
} | .file "tmpxft_00058f5c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB3924:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3924:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z10SetElement6Matrixiif
.type _Z10SetElement6Matrixiif, @function
_Z10SetElement6Matrixiif:
.LFB3925:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3925:
.size _Z10SetElement6Matrixiif, .-_Z10SetElement6Matrixiif
.globl _Z12GetSubMatrix6Matrixii
.type _Z12GetSubMatrix6Matrixii, @function
_Z12GetSubMatrix6Matrixii:
.LFB3926:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3926:
.size _Z12GetSubMatrix6Matrixii, .-_Z12GetSubMatrix6Matrixii
.globl _Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB3952:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z15MatrixMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3952:
.size _Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z15MatrixMulKernel6MatrixS_S_
.type _Z15MatrixMulKernel6MatrixS_S_, @function
_Z15MatrixMulKernel6MatrixS_S_:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _Z15MatrixMulKernel6MatrixS_S_, .-_Z15MatrixMulKernel6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA malloc A: "
.LC1:
.string "CUDA malloc B: "
.LC2:
.string "CUDA malloc C: "
.LC3:
.string "Run kernel: "
.LC4:
.string "Copy C off of device: "
.text
.globl _Z9MatrixMul6MatrixS_S_
.type _Z9MatrixMul6MatrixS_S_, @function
_Z9MatrixMul6MatrixS_S_:
.LFB3923:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movl 304(%rsp), %eax
movl 308(%rsp), %r13d
movl 328(%rsp), %r12d
movl 332(%rsp), %ebp
movl 352(%rsp), %ebx
movl 356(%rsp), %r15d
movl %eax, 64(%rsp)
movl %eax, 48(%rsp)
movl %r13d, 52(%rsp)
imull %r13d, %eax
cltq
salq $2, %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
movl %eax, %r14d
movl $15, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
testq %rax, %rax
je .L51
movq %rax, %r14
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L19:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %r14
testq %r14, %r14
je .L52
cmpb $0, 56(%r14)
je .L22
movzbl 67(%r14), %esi
.L23:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq 8(%rsp), %rdx
movq 312(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 96(%rsp)
movl %r12d, 80(%rsp)
movl %ebp, 84(%rsp)
imull %r12d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, 8(%rsp)
movl $15, %edx
leaq .LC1(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rsp), %edi
call cudaGetErrorString@PLT
movq %rax, %r14
testq %rax, %rax
je .L53
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L25:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %r14
testq %r14, %r14
je .L54
cmpb $0, 56(%r14)
je .L28
movzbl 67(%r14), %esi
.L29:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 336(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 128(%rsp)
movl %ebx, 112(%rsp)
movl %r15d, 116(%rsp)
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
movl $15, %edx
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
testq %rax, %rax
je .L55
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L31:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbp
testq %rbp, %rbp
je .L56
cmpb $0, 56(%rbp)
je .L34
movzbl 67(%rbp), %esi
.L35:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, 32(%rsp)
shrl $2, %r12d
movl %r12d, 36(%rsp)
shrl $2, %r13d
movl %r13d, 40(%rsp)
movl $1, 44(%rsp)
movl $4, 24(%rsp)
movl $4, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L36:
call cudaThreadSynchronize@PLT
movl %eax, %ebp
movl $12, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
testq %rax, %rax
je .L58
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L38:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbp
testq %rbp, %rbp
je .L59
cmpb $0, 56(%rbp)
je .L41
movzbl 67(%rbp), %esi
.L42:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 120(%rsp), %rsi
movq 360(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
movl $22, %edx
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L60
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L44:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L61
cmpb $0, 56(%rbx)
je .L47
movzbl 67(%rbx), %esi
.L48:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L19
.L52:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L63
call _ZSt16__throw_bad_castv@PLT
.L63:
call __stack_chk_fail@PLT
.L22:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L53:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L25
.L54:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L64
call _ZSt16__throw_bad_castv@PLT
.L64:
call __stack_chk_fail@PLT
.L28:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L29
.L55:
movq %r14, %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L31
.L56:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L65:
call __stack_chk_fail@PLT
.L34:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L57:
movdqa 48(%rsp), %xmm0
movaps %xmm0, 144(%rsp)
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 176(%rsp)
movq 96(%rsp), %rax
movq %rax, 192(%rsp)
movdqa 112(%rsp), %xmm2
movaps %xmm2, 208(%rsp)
movq 128(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 144(%rsp), %rdi
call _Z44__device_stub__Z15MatrixMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L36
.L58:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L38
.L59:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L41:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L60:
movq %rbp, %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L44
.L61:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L48
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size _Z9MatrixMul6MatrixS_S_, .-_Z9MatrixMul6MatrixS_S_
.section .rodata.str1.1
.LC5:
.string "---Result of calculating:"
.LC6:
.string "Martix A: "
.LC7:
.string " "
.LC8:
.string "Martix B: "
.LC9:
.string "Martix C: "
.text
.globl main
.type main, @function
main:
.LFB3927:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl $64, %edi
call malloc@PLT
movq %rax, %r15
movl $64, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, (%rsp)
leaq 16(%r15), %rbp
movq %rbp, %r12
movl $0, %r13d
.L69:
leaq -16(%r12), %rbx
.L70:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L70
addl $4, %r13d
addq $16, %r12
cmpl $16, %r13d
jne .L69
movq 8(%rsp), %rax
leaq 16(%rax), %r12
movq %r12, %r13
movl $0, %r14d
.L71:
leaq -16(%r13), %rbx
.L72:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L72
addl $4, %r14d
addq $16, %r13
cmpl $16, %r14d
jne .L71
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movq %r15, 24(%rsp)
movl $4, 48(%rsp)
movl $4, 52(%rsp)
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
movl $4, 80(%rsp)
movl $4, 84(%rsp)
movq (%rsp), %rax
movq %rax, 88(%rsp)
subq $80, %rsp
.cfi_def_cfa_offset 256
movdqa 160(%rsp), %xmm1
movups %xmm1, 48(%rsp)
movq 176(%rsp), %rax
movq %rax, 64(%rsp)
movdqa 128(%rsp), %xmm2
movups %xmm2, 24(%rsp)
movq 144(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 96(%rsp), %xmm3
movups %xmm3, (%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
call _Z9MatrixMul6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 176
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r15d
movq %rbx, %r13
leaq .LC7(%rip), %r14
jmp .L74
.L99:
call _ZSt16__throw_bad_castv@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L78:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $4, %r15d
addq $16, %rbp
cmpl $16, %r15d
je .L79
.L74:
leaq -16(%rbp), %rbx
.L75:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L75
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbx
testq %rbx, %rbx
je .L99
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
jmp .L78
.L79:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r14d
movq %rbx, %rbp
leaq .LC7(%rip), %r13
jmp .L80
.L100:
call _ZSt16__throw_bad_castv@PLT
.L83:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L84:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $4, %r14d
addq $16, %r12
cmpl $16, %r14d
je .L85
.L80:
leaq -16(%r12), %rbx
.L81:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L81
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L100
cmpb $0, 56(%rbx)
je .L83
movzbl 67(%rbx), %esi
jmp .L84
.L85:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %r12
addq $16, %r12
movl $0, %r14d
movq %rbx, %rbp
leaq .LC7(%rip), %r13
jmp .L86
.L101:
call _ZSt16__throw_bad_castv@PLT
.L89:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L90:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $4, %r14d
addq $16, %r12
cmpl $16, %r14d
je .L91
.L86:
leaq -16(%r12), %rbx
.L87:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L87
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L101
cmpb $0, 56(%rbx)
je .L89
movzbl 67(%rbx), %esi
jmp .L90
.L91:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3927:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z15MatrixMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#define __CUDACC_RTC__
#define __CUDACC__
#include <device_functions.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
typedef struct {
int width;
int height;
float* elements;
int step;
} Matrix;
using namespace std;
#define BLOCK_SIZE 4
__global__ void MatrixMulKernel(const Matrix, const Matrix, Matrix);
void MatrixMul(const Matrix A, const Matrix B, Matrix C) {
Matrix d_A;
d_A.width = d_A.step = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaError_t err = cudaMalloc(&d_A.elements, size);
cout << "CUDA malloc A: " << cudaGetErrorString(err) << endl;
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.step = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
err = cudaMalloc(&d_B.elements, size);
cout << "CUDA malloc B: " << cudaGetErrorString(err) << endl;
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.step = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
err = cudaMalloc(&d_C.elements, size);
cout << "CUDA malloc C: " << cudaGetErrorString(err) << endl;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatrixMulKernel <<<dimGrid, dimBlock>>> (d_A, d_B, d_C);
err = cudaThreadSynchronize();
cout << "Run kernel: " << cudaGetErrorString(err) << endl;
err = cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
cout << "Copy C off of device: " << cudaGetErrorString(err) << endl;
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
__device__ float GetElement(const Matrix A, int row, int col) {
return A.elements[row * A.step + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) {
A.elements[row * A.step + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.step = A.step;
Asub.elements = &A.elements[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatrixMulKernel(Matrix A, Matrix B, Matrix C) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0.0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
int main() {
Matrix A, B, C;
int a1, a2, b1, b2;
a1 = BLOCK_SIZE;
a2 = BLOCK_SIZE;
b1 = a2;
b2 = BLOCK_SIZE;
A.height = a1;
A.width = a2;
A.elements = (float*)malloc(A.width * A.height * sizeof(float));
B.height = b1;
B.width = b2;
B.elements = (float*)malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*)malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = rand() % 10;
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = rand() % 10;
MatrixMul(A, B, C);
cout << "---Result of calculating:" << endl;
cout << "Martix A: " << endl;
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
cout << A.elements[i * A.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix B: " << endl;
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
cout << B.elements[i * B.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix C: " << endl;
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
cout << C.elements[i * C.width + j] << " ";
cout << endl;
}
cout << endl;
return 0;
} | #include "hip/hip_runtime.h"
#define __CUDACC_RTC__
#define __HIPCC__
#include <hip/device_functions.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
typedef struct {
int width;
int height;
float* elements;
int step;
} Matrix;
using namespace std;
#define BLOCK_SIZE 4
__global__ void MatrixMulKernel(const Matrix, const Matrix, Matrix);
void MatrixMul(const Matrix A, const Matrix B, Matrix C) {
Matrix d_A;
d_A.width = d_A.step = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipError_t err = hipMalloc(&d_A.elements, size);
cout << "CUDA malloc A: " << hipGetErrorString(err) << endl;
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.step = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
err = hipMalloc(&d_B.elements, size);
cout << "CUDA malloc B: " << hipGetErrorString(err) << endl;
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.step = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
err = hipMalloc(&d_C.elements, size);
cout << "CUDA malloc C: " << hipGetErrorString(err) << endl;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatrixMulKernel <<<dimGrid, dimBlock>>> (d_A, d_B, d_C);
err = hipDeviceSynchronize();
cout << "Run kernel: " << hipGetErrorString(err) << endl;
err = hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
cout << "Copy C off of device: " << hipGetErrorString(err) << endl;
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
__device__ float GetElement(const Matrix A, int row, int col) {
return A.elements[row * A.step + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) {
A.elements[row * A.step + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.step = A.step;
Asub.elements = &A.elements[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatrixMulKernel(Matrix A, Matrix B, Matrix C) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0.0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
int main() {
Matrix A, B, C;
int a1, a2, b1, b2;
a1 = BLOCK_SIZE;
a2 = BLOCK_SIZE;
b1 = a2;
b2 = BLOCK_SIZE;
A.height = a1;
A.width = a2;
A.elements = (float*)malloc(A.width * A.height * sizeof(float));
B.height = b1;
B.width = b2;
B.elements = (float*)malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*)malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = rand() % 10;
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = rand() % 10;
MatrixMul(A, B, C);
cout << "---Result of calculating:" << endl;
cout << "Martix A: " << endl;
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
cout << A.elements[i * A.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix B: " << endl;
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
cout << B.elements[i * B.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix C: " << endl;
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
cout << C.elements[i * C.width + j] << " ";
cout << endl;
}
cout << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#define __CUDACC_RTC__
#define __HIPCC__
#include <hip/device_functions.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
typedef struct {
int width;
int height;
float* elements;
int step;
} Matrix;
using namespace std;
#define BLOCK_SIZE 4
__global__ void MatrixMulKernel(const Matrix, const Matrix, Matrix);
void MatrixMul(const Matrix A, const Matrix B, Matrix C) {
Matrix d_A;
d_A.width = d_A.step = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipError_t err = hipMalloc(&d_A.elements, size);
cout << "CUDA malloc A: " << hipGetErrorString(err) << endl;
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.step = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
err = hipMalloc(&d_B.elements, size);
cout << "CUDA malloc B: " << hipGetErrorString(err) << endl;
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.step = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
err = hipMalloc(&d_C.elements, size);
cout << "CUDA malloc C: " << hipGetErrorString(err) << endl;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatrixMulKernel <<<dimGrid, dimBlock>>> (d_A, d_B, d_C);
err = hipDeviceSynchronize();
cout << "Run kernel: " << hipGetErrorString(err) << endl;
err = hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
cout << "Copy C off of device: " << hipGetErrorString(err) << endl;
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
__device__ float GetElement(const Matrix A, int row, int col) {
return A.elements[row * A.step + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) {
A.elements[row * A.step + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.step = A.step;
Asub.elements = &A.elements[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatrixMulKernel(Matrix A, Matrix B, Matrix C) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0.0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
int main() {
Matrix A, B, C;
int a1, a2, b1, b2;
a1 = BLOCK_SIZE;
a2 = BLOCK_SIZE;
b1 = a2;
b2 = BLOCK_SIZE;
A.height = a1;
A.width = a2;
A.elements = (float*)malloc(A.width * A.height * sizeof(float));
B.height = b1;
B.width = b2;
B.elements = (float*)malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*)malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = rand() % 10;
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = rand() % 10;
MatrixMul(A, B, C);
cout << "---Result of calculating:" << endl;
cout << "Martix A: " << endl;
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
cout << A.elements[i * A.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix B: " << endl;
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
cout << B.elements[i * B.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix C: " << endl;
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
cout << C.elements[i * C.width + j] << " ";
cout << endl;
}
cout << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernel6MatrixS_S_
.globl _Z15MatrixMulKernel6MatrixS_S_
.p2align 8
.type _Z15MatrixMulKernel6MatrixS_S_,@function
_Z15MatrixMulKernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x38
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 4
s_cbranch_scc1 .LBB0_5
s_clause 0x3
s_load_b32 s10, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x20
v_lshlrev_b32_e32 v2, 2, v0
v_lshlrev_b32_e32 v3, 4, v1
s_ashr_i32 s11, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s11, s11, 30
v_add_nc_u32_e32 v4, 64, v2
s_add_i32 s5, s5, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_ashr_i32 s5, s5, 2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s10, v1, v[0:1]
v_mad_u64_u32 v[7:8], null, s4, v1, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_add_nc_u32_e32 v6, v4, v3
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
s_mul_i32 s6, s10, s15
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 2
s_lshl_b32 s10, s10, 2
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v9, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v10, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v4
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v5, v12
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v3
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 16, v11
s_cmp_eq_u32 s8, 16
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v4, 31, v3
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernel6MatrixS_S_, .Lfunc_end0-_Z15MatrixMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#define __CUDACC_RTC__
#define __HIPCC__
#include <hip/device_functions.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
typedef struct {
int width;
int height;
float* elements;
int step;
} Matrix;
using namespace std;
#define BLOCK_SIZE 4
__global__ void MatrixMulKernel(const Matrix, const Matrix, Matrix);
void MatrixMul(const Matrix A, const Matrix B, Matrix C) {
Matrix d_A;
d_A.width = d_A.step = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipError_t err = hipMalloc(&d_A.elements, size);
cout << "CUDA malloc A: " << hipGetErrorString(err) << endl;
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.step = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
err = hipMalloc(&d_B.elements, size);
cout << "CUDA malloc B: " << hipGetErrorString(err) << endl;
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.step = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
err = hipMalloc(&d_C.elements, size);
cout << "CUDA malloc C: " << hipGetErrorString(err) << endl;
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatrixMulKernel <<<dimGrid, dimBlock>>> (d_A, d_B, d_C);
err = hipDeviceSynchronize();
cout << "Run kernel: " << hipGetErrorString(err) << endl;
err = hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
cout << "Copy C off of device: " << hipGetErrorString(err) << endl;
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
__device__ float GetElement(const Matrix A, int row, int col) {
return A.elements[row * A.step + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) {
A.elements[row * A.step + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) {
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.step = A.step;
Asub.elements = &A.elements[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatrixMulKernel(Matrix A, Matrix B, Matrix C) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0.0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
int main() {
Matrix A, B, C;
int a1, a2, b1, b2;
a1 = BLOCK_SIZE;
a2 = BLOCK_SIZE;
b1 = a2;
b2 = BLOCK_SIZE;
A.height = a1;
A.width = a2;
A.elements = (float*)malloc(A.width * A.height * sizeof(float));
B.height = b1;
B.width = b2;
B.elements = (float*)malloc(B.width * B.height * sizeof(float));
C.height = A.height;
C.width = B.width;
C.elements = (float*)malloc(C.width * C.height * sizeof(float));
for (int i = 0; i < A.height; i++)
for (int j = 0; j < A.width; j++)
A.elements[i * A.width + j] = rand() % 10;
for (int i = 0; i < B.height; i++)
for (int j = 0; j < B.width; j++)
B.elements[i * B.width + j] = rand() % 10;
MatrixMul(A, B, C);
cout << "---Result of calculating:" << endl;
cout << "Martix A: " << endl;
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < A.width; j++)
cout << A.elements[i * A.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix B: " << endl;
for (int i = 0; i < B.height; i++) {
for (int j = 0; j < B.width; j++)
cout << B.elements[i * B.width + j] << " ";
cout << endl;
}
cout << endl;
cout << "Martix C: " << endl;
for (int i = 0; i < C.height; i++) {
for (int j = 0; j < C.width; j++)
cout << C.elements[i * C.width + j] << " ";
cout << endl;
}
cout << endl;
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9MatrixMul6MatrixS_S_ # -- Begin function _Z9MatrixMul6MatrixS_S_
.p2align 4, 0x90
.type _Z9MatrixMul6MatrixS_S_,@function
_Z9MatrixMul6MatrixS_S_: # @_Z9MatrixMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 304(%rsp), %eax
movl 308(%rsp), %ebx
movl %eax, 72(%rsp)
movl %eax, 56(%rsp)
movl %ebx, 60(%rsp)
imull %ebx, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cout, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_3
.LBB0_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_38
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
leaq 328(%rsp), %r12
leaq 304(%rsp), %r13
cmpb $0, 56(%r15)
je .LBB0_6
# %bb.5:
movzbl 67(%r15), %eax
jmp .LBB0_7
.LBB0_6:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 64(%rsp), %rdi
movq 8(%r13), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl (%r12), %r13d
movl %r13d, 48(%rsp)
movl %r13d, 32(%rsp)
movl 4(%r12), %eax
movl %eax, 36(%rsp)
imull %r13d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_8
# %bb.9:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cout, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_10
.LBB0_8:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_38
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
leaq 352(%rsp), %rbp
cmpb $0, 56(%r15)
je .LBB0_13
# %bb.12:
movzbl 67(%r15), %eax
jmp .LBB0_14
.LBB0_13:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi
movq 8(%r12), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %r12
movl (%rbp), %eax
movl %eax, 24(%rsp)
movl %eax, 8(%rsp)
movl 4(%rbp), %ecx
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_15
# %bb.16:
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cout, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_17
.LBB0_15:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit20
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_38
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%r15)
je .LBB0_20
# %bb.19:
movzbl 67(%r15), %eax
jmp .LBB0_21
.LBB0_20:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
shrl $2, %r13d
shrl $2, %ebx
shlq $32, %rbx
orq %r13, %rbx
movabsq $17179869188, %rdx # imm = 0x400000004
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_23
# %bb.22:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulKernel6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_23:
callq hipDeviceSynchronize
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_24
# %bb.25:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_26
.LBB0_24:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_26: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit22
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_38
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%rbx)
je .LBB0_29
# %bb.28:
movzbl 67(%rbx), %eax
jmp .LBB0_30
.LBB0_29:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%r12), %rdi
movq 16(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_31
# %bb.32:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_33
.LBB0_31:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_38
# %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%rbx)
je .LBB0_36
# %bb.35:
movzbl 67(%rbx), %eax
jmp .LBB0_37
.LBB0_36:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_37: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_38:
.cfi_def_cfa_offset 304
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z9MatrixMul6MatrixS_S_, .Lfunc_end0-_Z9MatrixMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MatrixMulKernel6MatrixS_S_ # -- Begin function _Z30__device_stub__MatrixMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernel6MatrixS_S_,@function
_Z30__device_stub__MatrixMulKernel6MatrixS_S_: # @_Z30__device_stub__MatrixMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15MatrixMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__MatrixMulKernel6MatrixS_S_, .Lfunc_end1-_Z30__device_stub__MatrixMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64, %edi
callq malloc
movq %rax, %r15
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB2_1: # %.preheader118
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $4, %rbp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %r12
addq $16, %r13
cmpq $4, %r12
jne .LBB2_1
# %bb.4: # %.preheader116.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB2_5: # %.preheader116
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $4, %rbp
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %r12
addq $16, %r13
cmpq $4, %r12
jne .LBB2_5
# %bb.8:
movabsq $17179869188, %rax # imm = 0x400000004
movq %rax, 128(%rsp)
movq %r15, 136(%rsp)
movq %rax, 104(%rsp)
movq %r14, 112(%rsp)
movq %rax, 80(%rsp)
movq %rbx, 88(%rsp)
movq 96(%rsp), %rax
movq %rax, 64(%rsp)
movups 80(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 120(%rsp), %rax
movq %rax, 40(%rsp)
movups 104(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 144(%rsp), %rax
movq %rax, 16(%rsp)
movups 128(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z9MatrixMul6MatrixS_S_
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_61
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_11
# %bb.10:
movzbl 67(%r12), %eax
jmp .LBB2_12
.LBB2_11:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_61
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i70
cmpb $0, 56(%r12)
je .LBB2_15
# %bb.14:
movzbl 67(%r12), %eax
jmp .LBB2_16
.LBB2_15:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit73
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r13d, %r13d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_36: # in Loop: Header=BB2_17 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_37: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit88
# in Loop: Header=BB2_17 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
addq $16, %r15
cmpq $4, %r13
je .LBB2_22
.LBB2_17: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $4, %r12
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_61
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i85
# in Loop: Header=BB2_17 Depth=1
cmpb $0, 56(%r12)
je .LBB2_36
# %bb.21: # in Loop: Header=BB2_17 Depth=1
movzbl 67(%r12), %eax
jmp .LBB2_37
.LBB2_22:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_61
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i75
cmpb $0, 56(%r15)
je .LBB2_25
# %bb.24:
movzbl 67(%r15), %eax
jmp .LBB2_26
.LBB2_25:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit78
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_61
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i80
cmpb $0, 56(%r15)
je .LBB2_29
# %bb.28:
movzbl 67(%r15), %eax
jmp .LBB2_30
.LBB2_29:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit83
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB2_31
.p2align 4, 0x90
.LBB2_35: # in Loop: Header=BB2_31 Depth=1
movzbl 67(%r15), %eax
.LBB2_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit103
# in Loop: Header=BB2_31 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $16, %r14
cmpq $4, %r12
je .LBB2_38
.LBB2_31: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB2_32 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_32: # Parent Loop BB2_31 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $4, %r15
jne .LBB2_32
# %bb.33: # in Loop: Header=BB2_31 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_61
# %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100
# in Loop: Header=BB2_31 Depth=1
cmpb $0, 56(%r15)
jne .LBB2_35
# %bb.52: # in Loop: Header=BB2_31 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_53
.LBB2_38:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_61
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i90
cmpb $0, 56(%r14)
je .LBB2_41
# %bb.40:
movzbl 67(%r14), %eax
jmp .LBB2_42
.LBB2_41:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit93
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_61
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
cmpb $0, 56(%r14)
je .LBB2_45
# %bb.44:
movzbl 67(%r14), %eax
jmp .LBB2_46
.LBB2_45:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit98
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB2_47
.p2align 4, 0x90
.LBB2_59: # in Loop: Header=BB2_47 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit113
# in Loop: Header=BB2_47 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $16, %rbx
cmpq $4, %r15
je .LBB2_54
.LBB2_47: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_48 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_48: # Parent Loop BB2_47 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $4, %r14
jne .LBB2_48
# %bb.49: # in Loop: Header=BB2_47 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_61
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i110
# in Loop: Header=BB2_47 Depth=1
cmpb $0, 56(%r14)
je .LBB2_59
# %bb.51: # in Loop: Header=BB2_47 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_60
.LBB2_54:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_61
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
cmpb $0, 56(%rbx)
je .LBB2_57
# %bb.56:
movzbl 67(%rbx), %eax
jmp .LBB2_58
.LBB2_57:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit108
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_61:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA malloc A: "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA malloc B: "
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA malloc C: "
.size .L.str.2, 16
.type _Z15MatrixMulKernel6MatrixS_S_,@object # @_Z15MatrixMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z15MatrixMulKernel6MatrixS_S_:
.quad _Z30__device_stub__MatrixMulKernel6MatrixS_S_
.size _Z15MatrixMulKernel6MatrixS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Run kernel: "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Copy C off of device: "
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "---Result of calculating:"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Martix A: "
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " "
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Martix B: "
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Martix C: "
.size .L.str.9, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernel6MatrixS_S_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15MatrixMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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