system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
matrix(float *A, int numElements, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
float a;
if (i < n && j< n && i!= (n-1) && i%2==0)
{
a = A[j*n + i];
A[j*n + i] = A[j*n + i + 1];
A[j*n + i +1] = a;
}
if (i<n&& j<n && i<j){
A[i*n+j] = A[j*n + i];
}
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__matrixPfii # -- Begin function _Z21__device_stub__matrixPfii
.p2align 4, 0x90
.type _Z21__device_stub__matrixPfii,@function
_Z21__device_stub__matrixPfii: # @_Z21__device_stub__matrixPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6matrixPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__matrixPfii, .Lfunc_end0-_Z21__device_stub__matrixPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matrixPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matrixPfii,@object # @_Z6matrixPfii
.section .rodata,"a",@progbits
.globl _Z6matrixPfii
.p2align 3, 0x0
_Z6matrixPfii:
.quad _Z21__device_stub__matrixPfii
.size _Z6matrixPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matrixPfii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matrixPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matrixPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matrixPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ BSSY B0, 0x1a0 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*00c0*/ ISETP.LT.AND P0, PT, R0.reuse, c[0x0][0x16c], !P0 ; /* 0x00005b0000007a0c */
/* 0x040fe40004701270 */
/*00d0*/ LOP3.LUT R2, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x040fe400078ec0ff */
/*00e0*/ ISETP.EQ.OR P1, PT, R0.reuse, UR4, !P0 ; /* 0x0000000400007c0c */
/* 0x040fe2000c722670 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.OR P0, PT, R0, R5, !P0 ; /* 0x000000050000720c */
/* 0x000fe40004706670 */
/*0110*/ ISETP.EQ.U32.OR P1, PT, R2, 0x1, P1 ; /* 0x000000010200780c */
/* 0x000fe20000f22470 */
/*0120*/ IMAD R2, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005027a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd000078e0204 */
/*0140*/ @P1 BRA 0x190 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*0170*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0041e8000c101904 */
/*0180*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0081e4000c101904 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ IMAD R5, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000057a24 */
/* 0x000fc800078e0205 */
/*01d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0204 */
/*01e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matrixPfii
.globl _Z6matrixPfii
.p2align 8
.type _Z6matrixPfii,@function
_Z6matrixPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0xc
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s0, s4, -1
v_and_b32_e32 v3, 1, v0
v_cmp_ne_u32_e64 s0, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_max_i32_e32 v2, v0, v1
v_cmp_eq_u32_e64 s1, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
global_load_b64 v[4:5], v[2:3], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v6, v4
global_store_b64 v[2:3], v[5:6], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_lt_i32_e64 s0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matrixPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matrixPfii, .Lfunc_end0-_Z6matrixPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matrixPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matrixPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d7537_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6matrixPfiiPfii
.type _Z27__device_stub__Z6matrixPfiiPfii, @function
_Z27__device_stub__Z6matrixPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6matrixPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6matrixPfiiPfii, .-_Z27__device_stub__Z6matrixPfiiPfii
.globl _Z6matrixPfii
.type _Z6matrixPfii, @function
_Z6matrixPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6matrixPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matrixPfii, .-_Z6matrixPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matrixPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matrixPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__matrixPfii # -- Begin function _Z21__device_stub__matrixPfii
.p2align 4, 0x90
.type _Z21__device_stub__matrixPfii,@function
_Z21__device_stub__matrixPfii: # @_Z21__device_stub__matrixPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6matrixPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__matrixPfii, .Lfunc_end0-_Z21__device_stub__matrixPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matrixPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matrixPfii,@object # @_Z6matrixPfii
.section .rodata,"a",@progbits
.globl _Z6matrixPfii
.p2align 3, 0x0
_Z6matrixPfii:
.quad _Z21__device_stub__matrixPfii
.size _Z6matrixPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matrixPfii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matrixPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matrixPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Check that types, widths, __GCC_ATOMIC* macros, etc. match on the host and
// device sides of CUDA compilations. Note that we filter out long double, as
// this is intentionally different on host and device.
//
// FIXME: We really should make __GCC_HAVE_SYNC_COMPARE_AND_SWAP identical on
// host and device, but architecturally this is difficult at the moment.
// RUN: mkdir -p %t
// RUN: %clang --cuda-host-only -nocudainc -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-device-defines-filtered
// RUN: diff %t/i386-host-defines-filtered %t/i386-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-device-defines-filtered
// RUN: diff %t/x86_64-host-defines-filtered %t/x86_64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-device-defines-filtered
// RUN: diff %t/powerpc64-host-defines-filtered %t/powerpc64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-device-defines-filtered
// RUN: diff %t/i386-msvc-host-defines-filtered %t/i386-msvc-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-device-defines-filtered
// RUN: diff %t/x86_64-msvc-host-defines-filtered %t/x86_64-msvc-device-defines-filtered | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Check that types, widths, __GCC_ATOMIC* macros, etc. match on the host and
// device sides of CUDA compilations. Note that we filter out long double, as
// this is intentionally different on host and device.
//
// FIXME: We really should make __GCC_HAVE_SYNC_COMPARE_AND_SWAP identical on
// host and device, but architecturally this is difficult at the moment.
// RUN: mkdir -p %t
// RUN: %clang --cuda-host-only -nocudainc -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-device-defines-filtered
// RUN: diff %t/i386-host-defines-filtered %t/i386-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-device-defines-filtered
// RUN: diff %t/x86_64-host-defines-filtered %t/x86_64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-device-defines-filtered
// RUN: diff %t/powerpc64-host-defines-filtered %t/powerpc64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-device-defines-filtered
// RUN: diff %t/i386-msvc-host-defines-filtered %t/i386-msvc-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-device-defines-filtered
// RUN: diff %t/x86_64-msvc-host-defines-filtered %t/x86_64-msvc-device-defines-filtered | .file "tmpxft_00114ab8_00000000-6_cuda-types.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Check that types, widths, __GCC_ATOMIC* macros, etc. match on the host and
// device sides of CUDA compilations. Note that we filter out long double, as
// this is intentionally different on host and device.
//
// FIXME: We really should make __GCC_HAVE_SYNC_COMPARE_AND_SWAP identical on
// host and device, but architecturally this is difficult at the moment.
// RUN: mkdir -p %t
// RUN: %clang --cuda-host-only -nocudainc -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-device-defines-filtered
// RUN: diff %t/i386-host-defines-filtered %t/i386-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-device-defines-filtered
// RUN: diff %t/x86_64-host-defines-filtered %t/x86_64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-device-defines-filtered
// RUN: diff %t/powerpc64-host-defines-filtered %t/powerpc64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-device-defines-filtered
// RUN: diff %t/i386-msvc-host-defines-filtered %t/i386-msvc-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-device-defines-filtered
// RUN: diff %t/x86_64-msvc-host-defines-filtered %t/x86_64-msvc-device-defines-filtered | #include <hip/hip_runtime.h>
// Check that types, widths, __GCC_ATOMIC* macros, etc. match on the host and
// device sides of CUDA compilations. Note that we filter out long double, as
// this is intentionally different on host and device.
//
// FIXME: We really should make __GCC_HAVE_SYNC_COMPARE_AND_SWAP identical on
// host and device, but architecturally this is difficult at the moment.
// RUN: mkdir -p %t
// RUN: %clang --cuda-host-only -nocudainc -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-device-defines-filtered
// RUN: diff %t/i386-host-defines-filtered %t/i386-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-device-defines-filtered
// RUN: diff %t/x86_64-host-defines-filtered %t/x86_64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-device-defines-filtered
// RUN: diff %t/powerpc64-host-defines-filtered %t/powerpc64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-device-defines-filtered
// RUN: diff %t/i386-msvc-host-defines-filtered %t/i386-msvc-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-device-defines-filtered
// RUN: diff %t/x86_64-msvc-host-defines-filtered %t/x86_64-msvc-device-defines-filtered |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Check that types, widths, __GCC_ATOMIC* macros, etc. match on the host and
// device sides of CUDA compilations. Note that we filter out long double, as
// this is intentionally different on host and device.
//
// FIXME: We really should make __GCC_HAVE_SYNC_COMPARE_AND_SWAP identical on
// host and device, but architecturally this is difficult at the moment.
// RUN: mkdir -p %t
// RUN: %clang --cuda-host-only -nocudainc -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-device-defines-filtered
// RUN: diff %t/i386-host-defines-filtered %t/i386-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-device-defines-filtered
// RUN: diff %t/x86_64-host-defines-filtered %t/x86_64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-device-defines-filtered
// RUN: diff %t/powerpc64-host-defines-filtered %t/powerpc64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-device-defines-filtered
// RUN: diff %t/i386-msvc-host-defines-filtered %t/i386-msvc-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-device-defines-filtered
// RUN: diff %t/x86_64-msvc-host-defines-filtered %t/x86_64-msvc-device-defines-filtered | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Check that types, widths, __GCC_ATOMIC* macros, etc. match on the host and
// device sides of CUDA compilations. Note that we filter out long double, as
// this is intentionally different on host and device.
//
// FIXME: We really should make __GCC_HAVE_SYNC_COMPARE_AND_SWAP identical on
// host and device, but architecturally this is difficult at the moment.
// RUN: mkdir -p %t
// RUN: %clang --cuda-host-only -nocudainc -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-device-defines-filtered
// RUN: diff %t/i386-host-defines-filtered %t/i386-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-device-defines-filtered
// RUN: diff %t/x86_64-host-defines-filtered %t/x86_64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target powerpc64-unknown-linux-gnu -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/powerpc64-device-defines-filtered
// RUN: diff %t/powerpc64-host-defines-filtered %t/powerpc64-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target i386-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/i386-msvc-device-defines-filtered
// RUN: diff %t/i386-msvc-host-defines-filtered %t/i386-msvc-device-defines-filtered
// RUN: %clang --cuda-host-only -nocudainc -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-host-defines-filtered
// RUN: %clang --cuda-device-only -nocudainc -nocudalib -target x86_64-windows-msvc -x cuda -E -dM -o - /dev/null \
// RUN: | grep -E 'define __[^ ]*(TYPE|MAX|SIZEOF|WIDTH)|define __GCC_ATOMIC' \
// RUN: | grep -Ev '__LDBL|_LONG_DOUBLE' > %t/x86_64-msvc-device-defines-filtered
// RUN: diff %t/x86_64-msvc-host-defines-filtered %t/x86_64-msvc-device-defines-filtered | .text
.file "cuda-types.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00114ab8_00000000-6_cuda-types.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-types.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void kernel_add(float *proj1, float *proj, int iv, int na, int nb, float weight){
int ia = 16 * blockIdx.x + threadIdx.x;
int ib = 16 * blockIdx.y + threadIdx.y;
if (ia >= na || ib >= nb)
return;
proj1[ia + ib * na] += proj[ia + ib * na + iv * na * nb] * weight;
}
// __global__ void kernel_add(cudaArray *proj1, cudaArray *proj, int iv, int na, int nb, float weight){
// int ia = 16 * blockIdx.x + threadIdx.x;
// int ib = 16 * blockIdx.y + threadIdx.y;
// if (ia >= na || ib >= nb)
// return;
// proj1[ia + ib * na] += proj[ia + ib * na + iv * na * nb] * weight;
// } | code for sm_80
Function : _Z10kernel_addPfS_iiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R0, R0, R5, 0x4 ; /* 0x0000000500007211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R3, R2, c[0x0][0x170], RZ ; /* 0x00005c0002037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*00f0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fce00078e0200 */
/*0100*/ IMAD.WIDE R4, R0, R2, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0202 */
/*0110*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0202 */
/*0120*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000eaa000c1e1900 */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FFMA R7, R2, c[0x0][0x17c], R7 ; /* 0x00005f0002077a23 */
/* 0x004fca0000000007 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kernel_add(float *proj1, float *proj, int iv, int na, int nb, float weight){
int ia = 16 * blockIdx.x + threadIdx.x;
int ib = 16 * blockIdx.y + threadIdx.y;
if (ia >= na || ib >= nb)
return;
proj1[ia + ib * na] += proj[ia + ib * na + iv * na * nb] * weight;
}
// __global__ void kernel_add(cudaArray *proj1, cudaArray *proj, int iv, int na, int nb, float weight){
// int ia = 16 * blockIdx.x + threadIdx.x;
// int ib = 16 * blockIdx.y + threadIdx.y;
// if (ia >= na || ib >= nb)
// return;
// proj1[ia + ib * na] += proj[ia + ib * na + iv * na * nb] * weight;
// } | .file "tmpxft_0009d49f_00000000-6_kernel_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif
.type _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif, @function
_Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_addPfS_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif, .-_Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif
.globl _Z10kernel_addPfS_iiif
.type _Z10kernel_addPfS_iiif, @function
_Z10kernel_addPfS_iiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_addPfS_iiif, .-_Z10kernel_addPfS_iiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_addPfS_iiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_addPfS_iiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kernel_add(float *proj1, float *proj, int iv, int na, int nb, float weight){
int ia = 16 * blockIdx.x + threadIdx.x;
int ib = 16 * blockIdx.y + threadIdx.y;
if (ia >= na || ib >= nb)
return;
proj1[ia + ib * na] += proj[ia + ib * na + iv * na * nb] * weight;
}
// __global__ void kernel_add(cudaArray *proj1, cudaArray *proj, int iv, int na, int nb, float weight){
// int ia = 16 * blockIdx.x + threadIdx.x;
// int ib = 16 * blockIdx.y + threadIdx.y;
// if (ia >= na || ib >= nb)
// return;
// proj1[ia + ib * na] += proj[ia + ib * na + iv * na * nb] * weight;
// } | #include <hip/hip_runtime.h>
__global__ void kernel_add(float *proj1, float *proj, int iv, int na, int nb, float weight); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kernel_add(float *proj1, float *proj, int iv, int na, int nb, float weight); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kernel_add(float *proj1, float *proj, int iv, int na, int nb, float weight); | .text
.file "kernel_add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_addPfS_iiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R0, R0, R5, 0x4 ; /* 0x0000000500007211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R3, R2, c[0x0][0x170], RZ ; /* 0x00005c0002037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*00f0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fce00078e0200 */
/*0100*/ IMAD.WIDE R4, R0, R2, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0202 */
/*0110*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0202 */
/*0120*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000eaa000c1e1900 */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0140*/ FFMA R7, R2, c[0x0][0x17c], R7 ; /* 0x00005f0002077a23 */
/* 0x004fca0000000007 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d49f_00000000-6_kernel_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif
.type _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif, @function
_Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_addPfS_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif, .-_Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif
.globl _Z10kernel_addPfS_iiif
.type _Z10kernel_addPfS_iiif, @function
_Z10kernel_addPfS_iiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10kernel_addPfS_iiifPfS_iiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_addPfS_iiif, .-_Z10kernel_addPfS_iiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_addPfS_iiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_addPfS_iiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ConvolutionRowGPU(double *d_Dst, double *d_Src, double *d_Filter, int imageW, int imageH, int filterR){
int k;
double sum=0;
int row=blockDim.y*blockIdx.y+threadIdx.y;
int col=blockDim.x*blockIdx.x+threadIdx.x;
for (k = -filterR; k <= filterR; k++) {
int d = col+ k;
if (d >= 0 && d < imageW) {
sum += d_Src[row * imageW + d] * d_Filter[filterR - k];
}
d_Dst[row * imageW + col] = sum;
}
} | .file "tmpxft_000963a0_00000000-6_ConvolutionRowGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii
.type _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii, @function
_Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17ConvolutionRowGPUPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii, .-_Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii
.globl _Z17ConvolutionRowGPUPdS_S_iii
.type _Z17ConvolutionRowGPUPdS_S_iii, @function
_Z17ConvolutionRowGPUPdS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17ConvolutionRowGPUPdS_S_iii, .-_Z17ConvolutionRowGPUPdS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17ConvolutionRowGPUPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17ConvolutionRowGPUPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ConvolutionRowGPU(double *d_Dst, double *d_Src, double *d_Filter, int imageW, int imageH, int filterR){
int k;
double sum=0;
int row=blockDim.y*blockIdx.y+threadIdx.y;
int col=blockDim.x*blockIdx.x+threadIdx.x;
for (k = -filterR; k <= filterR; k++) {
int d = col+ k;
if (d >= 0 && d < imageW) {
sum += d_Src[row * imageW + d] * d_Filter[filterR - k];
}
d_Dst[row * imageW + col] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ConvolutionRowGPU(double *d_Dst, double *d_Src, double *d_Filter, int imageW, int imageH, int filterR){
int k;
double sum=0;
int row=blockDim.y*blockIdx.y+threadIdx.y;
int col=blockDim.x*blockIdx.x+threadIdx.x;
for (k = -filterR; k <= filterR; k++) {
int d = col+ k;
if (d >= 0 && d < imageW) {
sum += d_Src[row * imageW + d] * d_Filter[filterR - k];
}
d_Dst[row * imageW + col] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ConvolutionRowGPU(double *d_Dst, double *d_Src, double *d_Filter, int imageW, int imageH, int filterR){
int k;
double sum=0;
int row=blockDim.y*blockIdx.y+threadIdx.y;
int col=blockDim.x*blockIdx.x+threadIdx.x;
for (k = -filterR; k <= filterR; k++) {
int d = col+ k;
if (d >= 0 && d < imageW) {
sum += d_Src[row * imageW + d] * d_Filter[filterR - k];
}
d_Dst[row * imageW + col] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17ConvolutionRowGPUPdS_S_iii
.globl _Z17ConvolutionRowGPUPdS_S_iii
.p2align 8
.type _Z17ConvolutionRowGPUPdS_S_iii,@function
_Z17ConvolutionRowGPUPdS_S_iii:
s_load_b32 s9, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 0
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v2, s8
v_subrev_nc_u32_e32 v5, s9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v4, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_add_co_u32 v2, vcc_lo, s4, v6
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
s_lshl_b32 s4, s9, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s4, s4, -1
global_store_b64 v[2:3], v[0:1], off
s_cmp_lg_u32 s4, -1
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s0, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v7, v4, v5
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_lshl_b64 s[10:11], s[4:5], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s2, s10
v_ashrrev_i32_e32 v8, 31, v7
s_addc_u32 s11, s3, s11
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v6, s[10:11]
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[7:8], v[9:10], v[0:1]
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17ConvolutionRowGPUPdS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17ConvolutionRowGPUPdS_S_iii, .Lfunc_end0-_Z17ConvolutionRowGPUPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17ConvolutionRowGPUPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17ConvolutionRowGPUPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ConvolutionRowGPU(double *d_Dst, double *d_Src, double *d_Filter, int imageW, int imageH, int filterR){
int k;
double sum=0;
int row=blockDim.y*blockIdx.y+threadIdx.y;
int col=blockDim.x*blockIdx.x+threadIdx.x;
for (k = -filterR; k <= filterR; k++) {
int d = col+ k;
if (d >= 0 && d < imageW) {
sum += d_Src[row * imageW + d] * d_Filter[filterR - k];
}
d_Dst[row * imageW + col] = sum;
}
} | .text
.file "ConvolutionRowGPU.hip"
.globl _Z32__device_stub__ConvolutionRowGPUPdS_S_iii # -- Begin function _Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__ConvolutionRowGPUPdS_S_iii,@function
_Z32__device_stub__ConvolutionRowGPUPdS_S_iii: # @_Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17ConvolutionRowGPUPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__ConvolutionRowGPUPdS_S_iii, .Lfunc_end0-_Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17ConvolutionRowGPUPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17ConvolutionRowGPUPdS_S_iii,@object # @_Z17ConvolutionRowGPUPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z17ConvolutionRowGPUPdS_S_iii
.p2align 3, 0x0
_Z17ConvolutionRowGPUPdS_S_iii:
.quad _Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.size _Z17ConvolutionRowGPUPdS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17ConvolutionRowGPUPdS_S_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17ConvolutionRowGPUPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000963a0_00000000-6_ConvolutionRowGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii
.type _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii, @function
_Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17ConvolutionRowGPUPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii, .-_Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii
.globl _Z17ConvolutionRowGPUPdS_S_iii
.type _Z17ConvolutionRowGPUPdS_S_iii, @function
_Z17ConvolutionRowGPUPdS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17ConvolutionRowGPUPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17ConvolutionRowGPUPdS_S_iii, .-_Z17ConvolutionRowGPUPdS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17ConvolutionRowGPUPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17ConvolutionRowGPUPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ConvolutionRowGPU.hip"
.globl _Z32__device_stub__ConvolutionRowGPUPdS_S_iii # -- Begin function _Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__ConvolutionRowGPUPdS_S_iii,@function
_Z32__device_stub__ConvolutionRowGPUPdS_S_iii: # @_Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17ConvolutionRowGPUPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__ConvolutionRowGPUPdS_S_iii, .Lfunc_end0-_Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17ConvolutionRowGPUPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17ConvolutionRowGPUPdS_S_iii,@object # @_Z17ConvolutionRowGPUPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z17ConvolutionRowGPUPdS_S_iii
.p2align 3, 0x0
_Z17ConvolutionRowGPUPdS_S_iii:
.quad _Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.size _Z17ConvolutionRowGPUPdS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17ConvolutionRowGPUPdS_S_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__ConvolutionRowGPUPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17ConvolutionRowGPUPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__
void add(int *a, int *b, int *c, int *n)
{
int index = blockIdx.x;
if( index < *n)
{
c[index] = a[index] + b[index] ;
}
} | code for sm_80
Function : _Z3addPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea40000002500 */
/*0060*/ ISETP.GE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0206 */
/*00a0*/ IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x0c0fe400078e0206 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e0206 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__
void add(int *a, int *b, int *c, int *n)
{
int index = blockIdx.x;
if( index < *n)
{
c[index] = a[index] + b[index] ;
}
} | .file "tmpxft_000ee78c_00000000-6_kernel_add_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_
.type _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_, @function
_Z28__device_stub__Z3addPiS_S_S_PiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_, .-_Z28__device_stub__Z3addPiS_S_S_PiS_S_S_
.globl _Z3addPiS_S_S_
.type _Z3addPiS_S_S_, @function
_Z3addPiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_S_, .-_Z3addPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__
void add(int *a, int *b, int *c, int *n)
{
int index = blockIdx.x;
if( index < *n)
{
c[index] = a[index] + b[index] ;
}
} | #include <hip/hip_runtime.h>
__global__
void add(int *a, int *b, int *c, int *n)
{
int index = blockIdx.x;
if( index < *n)
{
c[index] = a[index] + b[index] ;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__
void add(int *a, int *b, int *c, int *n)
{
int index = blockIdx.x;
if( index < *n)
{
c[index] = a[index] + b[index] ;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_S_
.globl _Z3addPiS_S_S_
.p2align 8
.type _Z3addPiS_S_S_,@function
_Z3addPiS_S_S_:
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_S_, .Lfunc_end0-_Z3addPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__
void add(int *a, int *b, int *c, int *n)
{
int index = blockIdx.x;
if( index < *n)
{
c[index] = a[index] + b[index] ;
}
} | .text
.file "kernel_add_vector.hip"
.globl _Z18__device_stub__addPiS_S_S_ # -- Begin function _Z18__device_stub__addPiS_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_S_,@function
_Z18__device_stub__addPiS_S_S_: # @_Z18__device_stub__addPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_S_,@object # @_Z3addPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_S_
.p2align 3, 0x0
_Z3addPiS_S_S_:
.quad _Z18__device_stub__addPiS_S_S_
.size _Z3addPiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_S_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea40000002500 */
/*0060*/ ISETP.GE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x004fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0206 */
/*00a0*/ IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x0c0fe400078e0206 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e0206 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_S_
.globl _Z3addPiS_S_S_
.p2align 8
.type _Z3addPiS_S_S_,@function
_Z3addPiS_S_S_:
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_S_, .Lfunc_end0-_Z3addPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ee78c_00000000-6_kernel_add_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_
.type _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_, @function
_Z28__device_stub__Z3addPiS_S_S_PiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_, .-_Z28__device_stub__Z3addPiS_S_S_PiS_S_S_
.globl _Z3addPiS_S_S_
.type _Z3addPiS_S_S_, @function
_Z3addPiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_S_, .-_Z3addPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_add_vector.hip"
.globl _Z18__device_stub__addPiS_S_S_ # -- Begin function _Z18__device_stub__addPiS_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_S_,@function
_Z18__device_stub__addPiS_S_S_: # @_Z18__device_stub__addPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_S_,@object # @_Z3addPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_S_
.p2align 3, 0x0
_Z3addPiS_S_S_:
.quad _Z18__device_stub__addPiS_S_S_
.size _Z3addPiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_S_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void testKernel(
float **inputPointers,
float **outputPointers,
int numPointers)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
if (tid < numPointers)
{
outputPointers[tid] = inputPointers[tid];
}
} | code for sm_80
Function : testKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void testKernel(
float **inputPointers,
float **outputPointers,
int numPointers)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
if (tid < numPointers)
{
outputPointers[tid] = inputPointers[tid];
}
} | .file "tmpxft_00052256_00000000-6_JCudaKernelParamsTestKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i
.type _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i, @function
_Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq testKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i, .-_Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i
.globl testKernel
.type testKernel, @function
testKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size testKernel, .-testKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "testKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq testKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void testKernel(
float **inputPointers,
float **outputPointers,
int numPointers)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
if (tid < numPointers)
{
outputPointers[tid] = inputPointers[tid];
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void testKernel(
float **inputPointers,
float **outputPointers,
int numPointers)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
if (tid < numPointers)
{
outputPointers[tid] = inputPointers[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void testKernel(
float **inputPointers,
float **outputPointers,
int numPointers)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
if (tid < numPointers)
{
outputPointers[tid] = inputPointers[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected testKernel
.globl testKernel
.p2align 8
.type testKernel,@function
testKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel testKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size testKernel, .Lfunc_end0-testKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: testKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: testKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void testKernel(
float **inputPointers,
float **outputPointers,
int numPointers)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
if (tid < numPointers)
{
outputPointers[tid] = inputPointers[tid];
}
} | .text
.file "JCudaKernelParamsTestKernel.hip"
.globl __device_stub__testKernel # -- Begin function __device_stub__testKernel
.p2align 4, 0x90
.type __device_stub__testKernel,@function
__device_stub__testKernel: # @__device_stub__testKernel
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $testKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__testKernel, .Lfunc_end0-__device_stub__testKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $testKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type testKernel,@object # @testKernel
.section .rodata,"a",@progbits
.globl testKernel
.p2align 3, 0x0
testKernel:
.quad __device_stub__testKernel
.size testKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "testKernel"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__testKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym testKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : testKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected testKernel
.globl testKernel
.p2align 8
.type testKernel,@function
testKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel testKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size testKernel, .Lfunc_end0-testKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: testKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: testKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00052256_00000000-6_JCudaKernelParamsTestKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i
.type _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i, @function
_Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq testKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i, .-_Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i
.globl testKernel
.type testKernel, @function
testKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10testKernelPPfS0_iPPfS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size testKernel, .-testKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "testKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq testKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "JCudaKernelParamsTestKernel.hip"
.globl __device_stub__testKernel # -- Begin function __device_stub__testKernel
.p2align 4, 0x90
.type __device_stub__testKernel,@function
__device_stub__testKernel: # @__device_stub__testKernel
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $testKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__testKernel, .Lfunc_end0-__device_stub__testKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $testKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type testKernel,@object # @testKernel
.section .rodata,"a",@progbits
.globl testKernel
.p2align 3, 0x0
testKernel:
.quad __device_stub__testKernel
.size testKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "testKernel"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__testKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym testKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void holaCUDA(float e){
printf("Hola, soy el hilo %d del bloque %d con valor pi -> %f\n", threadIdx.x, blockIdx.x,e);
}
int main (int argc, char **argv)
{
holaCUDA<<<3,4>>>(3.1416);
cudaDeviceReset(); //Reinicializa el device
return 0;
} | code for sm_80
Function : _Z8holaCUDAf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ F2F.F64.F32 R2, c[0x0][0x160] ; /* 0x0000580000027b10 */
/* 0x000e620000201800 */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0090*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0004e60000000a00 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00b0*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0025e80000100a00 */
/*00c0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0015e60000100a00 */
/*00d0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x004fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0130*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0140*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x008fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void holaCUDA(float e){
printf("Hola, soy el hilo %d del bloque %d con valor pi -> %f\n", threadIdx.x, blockIdx.x,e);
}
int main (int argc, char **argv)
{
holaCUDA<<<3,4>>>(3.1416);
cudaDeviceReset(); //Reinicializa el device
return 0;
} | .file "tmpxft_000129da_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8holaCUDAff
.type _Z26__device_stub__Z8holaCUDAff, @function
_Z26__device_stub__Z8holaCUDAff:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8holaCUDAf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8holaCUDAff, .-_Z26__device_stub__Z8holaCUDAff
.globl _Z8holaCUDAf
.type _Z8holaCUDAf, @function
_Z8holaCUDAf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8holaCUDAff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8holaCUDAf, .-_Z8holaCUDAf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss .LC0(%rip), %xmm0
call _Z26__device_stub__Z8holaCUDAff
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z8holaCUDAf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8holaCUDAf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1078530041
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void holaCUDA(float e){
printf("Hola, soy el hilo %d del bloque %d con valor pi -> %f\n", threadIdx.x, blockIdx.x,e);
}
int main (int argc, char **argv)
{
holaCUDA<<<3,4>>>(3.1416);
cudaDeviceReset(); //Reinicializa el device
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void holaCUDA(float e){
printf("Hola, soy el hilo %d del bloque %d con valor pi -> %f\n", threadIdx.x, blockIdx.x,e);
}
int main (int argc, char **argv)
{
holaCUDA<<<3,4>>>(3.1416);
hipDeviceReset(); //Reinicializa el device
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void holaCUDA(float e){
printf("Hola, soy el hilo %d del bloque %d con valor pi -> %f\n", threadIdx.x, blockIdx.x,e);
}
int main (int argc, char **argv)
{
holaCUDA<<<3,4>>>(3.1416);
hipDeviceReset(); //Reinicializa el device
return 0;
} | .text
.file "hello_world.hip"
.globl _Z23__device_stub__holaCUDAf # -- Begin function _Z23__device_stub__holaCUDAf
.p2align 4, 0x90
.type _Z23__device_stub__holaCUDAf,@function
_Z23__device_stub__holaCUDAf: # @_Z23__device_stub__holaCUDAf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8holaCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__holaCUDAf, .Lfunc_end0-_Z23__device_stub__holaCUDAf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $1078530041, 12(%rsp) # imm = 0x40490FF9
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8holaCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8holaCUDAf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8holaCUDAf,@object # @_Z8holaCUDAf
.section .rodata,"a",@progbits
.globl _Z8holaCUDAf
.p2align 3, 0x0
_Z8holaCUDAf:
.quad _Z23__device_stub__holaCUDAf
.size _Z8holaCUDAf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8holaCUDAf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__holaCUDAf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8holaCUDAf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000129da_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8holaCUDAff
.type _Z26__device_stub__Z8holaCUDAff, @function
_Z26__device_stub__Z8holaCUDAff:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8holaCUDAf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8holaCUDAff, .-_Z26__device_stub__Z8holaCUDAff
.globl _Z8holaCUDAf
.type _Z8holaCUDAf, @function
_Z8holaCUDAf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8holaCUDAff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8holaCUDAf, .-_Z8holaCUDAf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss .LC0(%rip), %xmm0
call _Z26__device_stub__Z8holaCUDAff
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z8holaCUDAf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8holaCUDAf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1078530041
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z23__device_stub__holaCUDAf # -- Begin function _Z23__device_stub__holaCUDAf
.p2align 4, 0x90
.type _Z23__device_stub__holaCUDAf,@function
_Z23__device_stub__holaCUDAf: # @_Z23__device_stub__holaCUDAf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8holaCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__holaCUDAf, .Lfunc_end0-_Z23__device_stub__holaCUDAf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $1078530041, 12(%rsp) # imm = 0x40490FF9
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8holaCUDAf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8holaCUDAf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8holaCUDAf,@object # @_Z8holaCUDAf
.section .rodata,"a",@progbits
.globl _Z8holaCUDAf
.p2align 3, 0x0
_Z8holaCUDAf:
.quad _Z23__device_stub__holaCUDAf
.size _Z8holaCUDAf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8holaCUDAf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__holaCUDAf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8holaCUDAf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
#include <stdio.h>
#include <cuda.h>
// declaration of function to check for errors
void checkCudaError(const char* msg);
// kernel
__global__ void reverseArrayBlock(int *d_out, int *d_in) {
int inOffset = blockDim.x * blockIdx.x;
int outOffset = blockDim.x * (gridDim.x - 1 - blockIdx.x);
int in = inOffset + threadIdx.x;
int out = outOffset + (blockDim.x - 1 - threadIdx.x);
d_out[out] = d_in[in];
}
// main thread
int main(int argc, char** argv) {
int *h_a;
int dimA = 256 * 1024;
int *d_b, *d_a;
int numThreadsPerBlock = 256;
// compute number of blocks needed
int numBlocks = dimA / numThreadsPerBlock;
// allocate memory
size_t memSize = numBlocks * numThreadsPerBlock*sizeof(int);
h_a = (int *)malloc(memSize);
cudaMalloc((void **) &d_a, memSize);
cudaMalloc((void **) &d_b, memSize);
// init array on host
for (int i=0; i<dimA; i++) {
h_a[i] = i;
}
cudaMemcpy( d_a, h_a, memSize, cudaMemcpyHostToDevice);
dim3 dimGrid(numBlocks);
dim3 dimBlock(numThreadsPerBlock);
reverseArrayBlock <<< dimGrid, dimBlock >>> (d_b, d_a);
// block until synced
cudaThreadSynchronize();
checkCudaError("kernel invocation");
cudaMemcpy(h_a, d_b, memSize, cudaMemcpyDeviceToHost);
checkCudaError("memcpy");
for (int i=0; i<dimA; i++) {
assert( h_a[i] == dimA - 1 - i);
}
cudaFree(d_a); cudaFree(d_b);
free(h_a);
return 0;
}
void checkCudaError(const char* msg) {
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "Cuda error: %s : %s .\n", msg, cudaGetErrorString(err) );
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z17reverseArrayBlockPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R0, c[0x0][0x0], R5 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE R2, R2, R6, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0206 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fe400078e33ff */
/*0090*/ LOP3.LUT R4, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff047212 */
/* 0x000fe400078e33ff */
/*00a0*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ IADD3 R5, R4, c[0x0][0x0], RZ ; /* 0x0000000004057a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD R5, R0, c[0x0][0x0], R5 ; /* 0x0000000000057a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0206 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <stdio.h>
#include <cuda.h>
// declaration of function to check for errors
void checkCudaError(const char* msg);
// kernel
__global__ void reverseArrayBlock(int *d_out, int *d_in) {
int inOffset = blockDim.x * blockIdx.x;
int outOffset = blockDim.x * (gridDim.x - 1 - blockIdx.x);
int in = inOffset + threadIdx.x;
int out = outOffset + (blockDim.x - 1 - threadIdx.x);
d_out[out] = d_in[in];
}
// main thread
int main(int argc, char** argv) {
int *h_a;
int dimA = 256 * 1024;
int *d_b, *d_a;
int numThreadsPerBlock = 256;
// compute number of blocks needed
int numBlocks = dimA / numThreadsPerBlock;
// allocate memory
size_t memSize = numBlocks * numThreadsPerBlock*sizeof(int);
h_a = (int *)malloc(memSize);
cudaMalloc((void **) &d_a, memSize);
cudaMalloc((void **) &d_b, memSize);
// init array on host
for (int i=0; i<dimA; i++) {
h_a[i] = i;
}
cudaMemcpy( d_a, h_a, memSize, cudaMemcpyHostToDevice);
dim3 dimGrid(numBlocks);
dim3 dimBlock(numThreadsPerBlock);
reverseArrayBlock <<< dimGrid, dimBlock >>> (d_b, d_a);
// block until synced
cudaThreadSynchronize();
checkCudaError("kernel invocation");
cudaMemcpy(h_a, d_b, memSize, cudaMemcpyDeviceToHost);
checkCudaError("memcpy");
for (int i=0; i<dimA; i++) {
assert( h_a[i] == dimA - 1 - i);
}
cudaFree(d_a); cudaFree(d_b);
free(h_a);
return 0;
}
void checkCudaError(const char* msg) {
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "Cuda error: %s : %s .\n", msg, cudaGetErrorString(err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_00161aeb_00000000-6_reverseArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s : %s .\n"
.text
.globl _Z14checkCudaErrorPKc
.type _Z14checkCudaErrorPKc, @function
_Z14checkCudaErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCudaErrorPKc, .-_Z14checkCudaErrorPKc
.globl _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
.type _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_, @function
_Z39__device_stub__Z17reverseArrayBlockPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17reverseArrayBlockPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_, .-_Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
.globl _Z17reverseArrayBlockPiS_
.type _Z17reverseArrayBlockPiS_, @function
_Z17reverseArrayBlockPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17reverseArrayBlockPiS_, .-_Z17reverseArrayBlockPiS_
.section .rodata.str1.1
.LC1:
.string "kernel invocation"
.LC2:
.string "memcpy"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movl $0, %eax
.L16:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L16
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call cudaThreadSynchronize@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCudaErrorPKc
movl $2, %ecx
movl $1048576, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCudaErrorPKc
movl $262144, %eax
.L18:
subl $1, %eax
jne .L18
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z17reverseArrayBlockPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reverseArrayBlockPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <stdio.h>
#include <cuda.h>
// declaration of function to check for errors
void checkCudaError(const char* msg);
// kernel
__global__ void reverseArrayBlock(int *d_out, int *d_in) {
int inOffset = blockDim.x * blockIdx.x;
int outOffset = blockDim.x * (gridDim.x - 1 - blockIdx.x);
int in = inOffset + threadIdx.x;
int out = outOffset + (blockDim.x - 1 - threadIdx.x);
d_out[out] = d_in[in];
}
// main thread
int main(int argc, char** argv) {
int *h_a;
int dimA = 256 * 1024;
int *d_b, *d_a;
int numThreadsPerBlock = 256;
// compute number of blocks needed
int numBlocks = dimA / numThreadsPerBlock;
// allocate memory
size_t memSize = numBlocks * numThreadsPerBlock*sizeof(int);
h_a = (int *)malloc(memSize);
cudaMalloc((void **) &d_a, memSize);
cudaMalloc((void **) &d_b, memSize);
// init array on host
for (int i=0; i<dimA; i++) {
h_a[i] = i;
}
cudaMemcpy( d_a, h_a, memSize, cudaMemcpyHostToDevice);
dim3 dimGrid(numBlocks);
dim3 dimBlock(numThreadsPerBlock);
reverseArrayBlock <<< dimGrid, dimBlock >>> (d_b, d_a);
// block until synced
cudaThreadSynchronize();
checkCudaError("kernel invocation");
cudaMemcpy(h_a, d_b, memSize, cudaMemcpyDeviceToHost);
checkCudaError("memcpy");
for (int i=0; i<dimA; i++) {
assert( h_a[i] == dimA - 1 - i);
}
cudaFree(d_a); cudaFree(d_b);
free(h_a);
return 0;
}
void checkCudaError(const char* msg) {
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "Cuda error: %s : %s .\n", msg, cudaGetErrorString(err) );
exit(EXIT_FAILURE);
}
} | #include <assert.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
// declaration of function to check for errors
void checkCudaError(const char* msg);
// kernel
__global__ void reverseArrayBlock(int *d_out, int *d_in) {
int inOffset = blockDim.x * blockIdx.x;
int outOffset = blockDim.x * (gridDim.x - 1 - blockIdx.x);
int in = inOffset + threadIdx.x;
int out = outOffset + (blockDim.x - 1 - threadIdx.x);
d_out[out] = d_in[in];
}
// main thread
int main(int argc, char** argv) {
int *h_a;
int dimA = 256 * 1024;
int *d_b, *d_a;
int numThreadsPerBlock = 256;
// compute number of blocks needed
int numBlocks = dimA / numThreadsPerBlock;
// allocate memory
size_t memSize = numBlocks * numThreadsPerBlock*sizeof(int);
h_a = (int *)malloc(memSize);
hipMalloc((void **) &d_a, memSize);
hipMalloc((void **) &d_b, memSize);
// init array on host
for (int i=0; i<dimA; i++) {
h_a[i] = i;
}
hipMemcpy( d_a, h_a, memSize, hipMemcpyHostToDevice);
dim3 dimGrid(numBlocks);
dim3 dimBlock(numThreadsPerBlock);
reverseArrayBlock <<< dimGrid, dimBlock >>> (d_b, d_a);
// block until synced
hipDeviceSynchronize();
checkCudaError("kernel invocation");
hipMemcpy(h_a, d_b, memSize, hipMemcpyDeviceToHost);
checkCudaError("memcpy");
for (int i=0; i<dimA; i++) {
assert( h_a[i] == dimA - 1 - i);
}
hipFree(d_a); hipFree(d_b);
free(h_a);
return 0;
}
void checkCudaError(const char* msg) {
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "Cuda error: %s : %s .\n", msg, hipGetErrorString(err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
// declaration of function to check for errors
void checkCudaError(const char* msg);
// kernel
__global__ void reverseArrayBlock(int *d_out, int *d_in) {
int inOffset = blockDim.x * blockIdx.x;
int outOffset = blockDim.x * (gridDim.x - 1 - blockIdx.x);
int in = inOffset + threadIdx.x;
int out = outOffset + (blockDim.x - 1 - threadIdx.x);
d_out[out] = d_in[in];
}
// main thread
int main(int argc, char** argv) {
int *h_a;
int dimA = 256 * 1024;
int *d_b, *d_a;
int numThreadsPerBlock = 256;
// compute number of blocks needed
int numBlocks = dimA / numThreadsPerBlock;
// allocate memory
size_t memSize = numBlocks * numThreadsPerBlock*sizeof(int);
h_a = (int *)malloc(memSize);
hipMalloc((void **) &d_a, memSize);
hipMalloc((void **) &d_b, memSize);
// init array on host
for (int i=0; i<dimA; i++) {
h_a[i] = i;
}
hipMemcpy( d_a, h_a, memSize, hipMemcpyHostToDevice);
dim3 dimGrid(numBlocks);
dim3 dimBlock(numThreadsPerBlock);
reverseArrayBlock <<< dimGrid, dimBlock >>> (d_b, d_a);
// block until synced
hipDeviceSynchronize();
checkCudaError("kernel invocation");
hipMemcpy(h_a, d_b, memSize, hipMemcpyDeviceToHost);
checkCudaError("memcpy");
for (int i=0; i<dimA; i++) {
assert( h_a[i] == dimA - 1 - i);
}
hipFree(d_a); hipFree(d_b);
free(h_a);
return 0;
}
void checkCudaError(const char* msg) {
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "Cuda error: %s : %s .\n", msg, hipGetErrorString(err) );
exit(EXIT_FAILURE);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17reverseArrayBlockPiS_
.globl _Z17reverseArrayBlockPiS_
.p2align 8
.type _Z17reverseArrayBlockPiS_,@function
_Z17reverseArrayBlockPiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_not_b32 s1, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s0, s0, s1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_not_b32_e32 v0, v0
s_mul_i32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17reverseArrayBlockPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17reverseArrayBlockPiS_, .Lfunc_end0-_Z17reverseArrayBlockPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17reverseArrayBlockPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17reverseArrayBlockPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
// declaration of function to check for errors
void checkCudaError(const char* msg);
// kernel
__global__ void reverseArrayBlock(int *d_out, int *d_in) {
int inOffset = blockDim.x * blockIdx.x;
int outOffset = blockDim.x * (gridDim.x - 1 - blockIdx.x);
int in = inOffset + threadIdx.x;
int out = outOffset + (blockDim.x - 1 - threadIdx.x);
d_out[out] = d_in[in];
}
// main thread
int main(int argc, char** argv) {
int *h_a;
int dimA = 256 * 1024;
int *d_b, *d_a;
int numThreadsPerBlock = 256;
// compute number of blocks needed
int numBlocks = dimA / numThreadsPerBlock;
// allocate memory
size_t memSize = numBlocks * numThreadsPerBlock*sizeof(int);
h_a = (int *)malloc(memSize);
hipMalloc((void **) &d_a, memSize);
hipMalloc((void **) &d_b, memSize);
// init array on host
for (int i=0; i<dimA; i++) {
h_a[i] = i;
}
hipMemcpy( d_a, h_a, memSize, hipMemcpyHostToDevice);
dim3 dimGrid(numBlocks);
dim3 dimBlock(numThreadsPerBlock);
reverseArrayBlock <<< dimGrid, dimBlock >>> (d_b, d_a);
// block until synced
hipDeviceSynchronize();
checkCudaError("kernel invocation");
hipMemcpy(h_a, d_b, memSize, hipMemcpyDeviceToHost);
checkCudaError("memcpy");
for (int i=0; i<dimA; i++) {
assert( h_a[i] == dimA - 1 - i);
}
hipFree(d_a); hipFree(d_b);
free(h_a);
return 0;
}
void checkCudaError(const char* msg) {
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "Cuda error: %s : %s .\n", msg, hipGetErrorString(err) );
exit(EXIT_FAILURE);
}
} | .text
.file "reverseArray.hip"
.globl _Z32__device_stub__reverseArrayBlockPiS_ # -- Begin function _Z32__device_stub__reverseArrayBlockPiS_
.p2align 4, 0x90
.type _Z32__device_stub__reverseArrayBlockPiS_,@function
_Z32__device_stub__reverseArrayBlockPiS_: # @_Z32__device_stub__reverseArrayBlockPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17reverseArrayBlockPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__reverseArrayBlockPiS_, .Lfunc_end0-_Z32__device_stub__reverseArrayBlockPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB1_1
# %bb.2:
movq (%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 768(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17reverseArrayBlockPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_5
# %bb.7: # %_Z14checkCudaErrorPKc.exit
movq 8(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z14checkCudaErrorPKc.exit30.preheader
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
jmp .LBB1_6
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %edx
.LBB1_6:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCudaErrorPKc # -- Begin function _Z14checkCudaErrorPKc
.p2align 4, 0x90
.type _Z14checkCudaErrorPKc,@function
_Z14checkCudaErrorPKc: # @_Z14checkCudaErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCudaErrorPKc, .Lfunc_end2-_Z14checkCudaErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17reverseArrayBlockPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17reverseArrayBlockPiS_,@object # @_Z17reverseArrayBlockPiS_
.section .rodata,"a",@progbits
.globl _Z17reverseArrayBlockPiS_
.p2align 3, 0x0
_Z17reverseArrayBlockPiS_:
.quad _Z32__device_stub__reverseArrayBlockPiS_
.size _Z17reverseArrayBlockPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel invocation"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cuda error: %s : %s .\n"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17reverseArrayBlockPiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__reverseArrayBlockPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17reverseArrayBlockPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17reverseArrayBlockPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R0, c[0x0][0x0], R5 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE R2, R2, R6, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0206 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fe400078e33ff */
/*0090*/ LOP3.LUT R4, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff047212 */
/* 0x000fe400078e33ff */
/*00a0*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ IADD3 R5, R4, c[0x0][0x0], RZ ; /* 0x0000000004057a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD R5, R0, c[0x0][0x0], R5 ; /* 0x0000000000057a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0206 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17reverseArrayBlockPiS_
.globl _Z17reverseArrayBlockPiS_
.p2align 8
.type _Z17reverseArrayBlockPiS_,@function
_Z17reverseArrayBlockPiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_not_b32 s1, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s0, s0, s1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_not_b32_e32 v0, v0
s_mul_i32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17reverseArrayBlockPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17reverseArrayBlockPiS_, .Lfunc_end0-_Z17reverseArrayBlockPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17reverseArrayBlockPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17reverseArrayBlockPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00161aeb_00000000-6_reverseArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s : %s .\n"
.text
.globl _Z14checkCudaErrorPKc
.type _Z14checkCudaErrorPKc, @function
_Z14checkCudaErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCudaErrorPKc, .-_Z14checkCudaErrorPKc
.globl _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
.type _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_, @function
_Z39__device_stub__Z17reverseArrayBlockPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17reverseArrayBlockPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_, .-_Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
.globl _Z17reverseArrayBlockPiS_
.type _Z17reverseArrayBlockPiS_, @function
_Z17reverseArrayBlockPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17reverseArrayBlockPiS_, .-_Z17reverseArrayBlockPiS_
.section .rodata.str1.1
.LC1:
.string "kernel invocation"
.LC2:
.string "memcpy"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movl $0, %eax
.L16:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L16
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call cudaThreadSynchronize@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCudaErrorPKc
movl $2, %ecx
movl $1048576, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCudaErrorPKc
movl $262144, %eax
.L18:
subl $1, %eax
jne .L18
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z17reverseArrayBlockPiS_PiS_
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z17reverseArrayBlockPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reverseArrayBlockPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reverseArray.hip"
.globl _Z32__device_stub__reverseArrayBlockPiS_ # -- Begin function _Z32__device_stub__reverseArrayBlockPiS_
.p2align 4, 0x90
.type _Z32__device_stub__reverseArrayBlockPiS_,@function
_Z32__device_stub__reverseArrayBlockPiS_: # @_Z32__device_stub__reverseArrayBlockPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17reverseArrayBlockPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__reverseArrayBlockPiS_, .Lfunc_end0-_Z32__device_stub__reverseArrayBlockPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB1_1
# %bb.2:
movq (%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 768(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17reverseArrayBlockPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_5
# %bb.7: # %_Z14checkCudaErrorPKc.exit
movq 8(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z14checkCudaErrorPKc.exit30.preheader
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
jmp .LBB1_6
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %edx
.LBB1_6:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCudaErrorPKc # -- Begin function _Z14checkCudaErrorPKc
.p2align 4, 0x90
.type _Z14checkCudaErrorPKc,@function
_Z14checkCudaErrorPKc: # @_Z14checkCudaErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCudaErrorPKc, .Lfunc_end2-_Z14checkCudaErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17reverseArrayBlockPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17reverseArrayBlockPiS_,@object # @_Z17reverseArrayBlockPiS_
.section .rodata,"a",@progbits
.globl _Z17reverseArrayBlockPiS_
.p2align 3, 0x0
_Z17reverseArrayBlockPiS_:
.quad _Z32__device_stub__reverseArrayBlockPiS_
.size _Z17reverseArrayBlockPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel invocation"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cuda error: %s : %s .\n"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17reverseArrayBlockPiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__reverseArrayBlockPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17reverseArrayBlockPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void hello(){
printf("Hello from block: %u, thread: %u\n", blockIdx.x, threadIdx.x);
}
int main(){
hello<<<2,2>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void hello(){
printf("Hello from block: %u, thread: %u\n", blockIdx.x, threadIdx.x);
}
int main(){
hello<<<2,2>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_00125a7d_00000000-6_hello_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void hello(){
printf("Hello from block: %u, thread: %u\n", blockIdx.x, threadIdx.x);
}
int main(){
hello<<<2,2>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello(){
printf("Hello from block: %u, thread: %u\n", blockIdx.x, threadIdx.x);
}
int main(){
hello<<<2,2>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello(){
printf("Hello from block: %u, thread: %u\n", blockIdx.x, threadIdx.x);
}
int main(){
hello<<<2,2>>>();
hipDeviceSynchronize();
} | .text
.file "hello_solution.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00125a7d_00000000-6_hello_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_solution.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* @file microbenchmarking_transfers.cu
* @detail This file describes the implementation of the functions involved in the
* PCIe bandwidth and latency.
* @author Antonio Jose Lazaro Munoz.
* @date 20/02/2016
*/
#include <stdio.h>
void swap(float & v1, float & v2){
float tmp = v1;
v1 = v2;
v2 = tmp;
}
int partition(float *array, int left, int right){
int part = right;
swap(array[part],array[(right+left) / 2]);
--right;
while(true){
while(array[left] < array[part]){
++left;
}
while(right >= left && array[part] <= array[right]){
--right;
}
if(right < left) break;
swap(array[left],array[right]);
++left;
--right;
}
swap(array[part],array[left]);
return left;
}
void qs(float * array, const int left, const int right){
if(left < right){
const int part = partition(array, left, right);
qs(array, part + 1,right);
qs(array, left,part - 1);
}
}
/**
* @brief Quicksort
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details Quicksort
*
* @param array elements array
* @param size array size
*/
void serialQuickSort(float *array, const int size){
qs(array, 0,size-1);
}
/**
* @brief Calculate times median
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the median from a set of times.
*
* @param h_times times array.
* @param N array size.
*
* @return time median.
*/
float getMedianTime(float *h_times, int N)
{
float median = 0;
float * h_sorted_times = (float *)malloc(N * sizeof(float));
for(int n = 0; n < N; n++)
h_sorted_times[n] = h_times[n];
//Sort execution times
serialQuickSort(h_sorted_times, N);
//Calculate median
if(N%2 == 0)
{
median = (h_sorted_times[N/2] + h_sorted_times[(N/2)+1])/2;
}
else
{
int p = N/2;
median = h_sorted_times[p];
}
free(h_sorted_times);
return median;
}
/**
* @brief Calculate PCIe HTD latency.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for HTD memory transfers.
*
* @param d_data device data.
* @param h_data host data.
* @param nreps iterations.
* @return HTD PCIe latency (ms).
*/
float getLoHTD(char *d_data, char *h_data, int nreps)
{
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
float LoHTD = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
cudaEventRecord(start_event, 0);
//we only transfer 1 byte.
cudaMemcpy(d_data, h_data, sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&LoHTD, start_event, stop_event);
h_times[k] = LoHTD;
}
LoHTD = getMedianTime(h_times, nreps);
free(h_times);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return LoHTD;
}
/**
* @brief Calculate PCIe DTH latency
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param nreps iterations
* @return DTH PCIe latency (ms).
*/
float getLoDTH(char *d_data, char *h_data, int nreps)
{
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
float LoDTH = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
cudaEventRecord(start_event, 0);
//we only transfer 1 byte.
cudaMemcpy(h_data, d_data, sizeof(char), cudaMemcpyDeviceToHost);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&LoDTH, start_event, stop_event);
h_times[k] = LoDTH;
}
LoDTH = getMedianTime(h_times, nreps);
free(h_times);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return LoDTH;
}
/**
* @brief DTH PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return DTH PCIe bandwidth (ms/byte).
*/
float getGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, 0);
cudaMemcpy(h_data, d_data, size * 1024 * 1024* sizeof(char), cudaMemcpyDeviceToHost);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GDTH;
}
/**
* @brief HTD PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return HTD PCIe bandwidth (ms/byte).
*/
float getGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, 0);
cudaMemcpy(d_data, h_data, size * 1024 * 1024* sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GHTD;
}
/**
* @brief Overlap DTH PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers, when a DTH memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return Overlap DTH PCIe bandwidth (byte/ms).
*/
float getOverlappedGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
cudaStream_t *stream_benchmark = (cudaStream_t *)malloc(2 * sizeof(cudaStream_t));
for(int i = 0; i < 2; i++)
cudaStreamCreate(&(stream_benchmark[i]));
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, stream_benchmark[0]);
//DTH
cudaMemcpyAsync(h_data,
d_data,
size * 1024 * 1024* sizeof(char),
cudaMemcpyDeviceToHost, stream_benchmark[0]);
cudaEventRecord(stop_event, stream_benchmark[0]);
//HTD
cudaMemcpyAsync(d_data + (size * 1024 * 1024),
h_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
cudaMemcpyHostToDevice, stream_benchmark[1]);
cudaDeviceSynchronize();
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
for(int i = 0; i < 2; i++)
cudaStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GDTH;
}
/**
* @brief Overlap HTD PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers, when a HTD memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return Overlap HTD PCIe bandwidth (byte/ms).
*/
float getOverlappedGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
cudaStream_t *stream_benchmark = (cudaStream_t *)malloc(2 * sizeof(cudaStream_t));
for(int i = 0; i < 2; i++)
cudaStreamCreate(&(stream_benchmark[i]));
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, stream_benchmark[0]);
cudaMemcpyAsync(d_data,
h_data,
size * 1024 * 1024* sizeof(char),
cudaMemcpyHostToDevice, stream_benchmark[0]);
cudaEventRecord(stop_event, stream_benchmark[0]);
cudaMemcpyAsync(h_data + (size * 1024 * 1024),
d_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
cudaMemcpyDeviceToHost, stream_benchmark[1]);
cudaDeviceSynchronize();
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
for(int i = 0; i < 2; i++)
cudaStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GHTD;
}
/**
* @brief PCIe microbenchmarking.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function calculates the values of PCIe latency and bandwidth
* for HTD and DTH memory transfers.
*
* @param gpu GPU id.
* @param LoHTD PCIe HTD latency (pointer).
* @param LoDTH PCIe DTH latency (pointer).
* @param GHTD HTD PCIe bandwidth (pointer).
* @param overlappedGHTD Overlap HTD PCIe bandwidth (pointer).
* @param GDTH DTH PCIe bandwidth (pointer).
* @param overlappedGDTH Overlap DTH PCIe bandwidth (pointer).
* @param nIter Iterations.
*/
void microbenchmarkingPCI(int gpu, float *LoHTD, float *LoDTH, float *GHTD, float *overlappedGHTD,
float *GDTH, float *overlappedGDTH, int nIter)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, gpu);
cudaSetDevice(gpu);
int tam = 1024*1024*1024; // 1GB
char *h_data_benchmark; cudaMallocHost((void**)&h_data_benchmark, tam * sizeof(char));
memset(h_data_benchmark, 0, tam * sizeof(char));
char *d_data_benchmark; cudaMalloc((void **)&d_data_benchmark, tam * sizeof(char));
cudaMemset(d_data_benchmark, 0, tam * sizeof(char));
*LoHTD = getLoHTD(d_data_benchmark, h_data_benchmark, nIter);
*GHTD = getGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
if(props.asyncEngineCount == 2)
*overlappedGHTD = getOverlappedGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
*LoDTH = getLoDTH(d_data_benchmark, h_data_benchmark, nIter);
*GDTH = getGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
if(props.asyncEngineCount == 2)
*overlappedGDTH = getOverlappedGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
cudaFreeHost(h_data_benchmark);
cudaFree(d_data_benchmark);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* @file microbenchmarking_transfers.cu
* @detail This file describes the implementation of the functions involved in the
* PCIe bandwidth and latency.
* @author Antonio Jose Lazaro Munoz.
* @date 20/02/2016
*/
#include <stdio.h>
void swap(float & v1, float & v2){
float tmp = v1;
v1 = v2;
v2 = tmp;
}
int partition(float *array, int left, int right){
int part = right;
swap(array[part],array[(right+left) / 2]);
--right;
while(true){
while(array[left] < array[part]){
++left;
}
while(right >= left && array[part] <= array[right]){
--right;
}
if(right < left) break;
swap(array[left],array[right]);
++left;
--right;
}
swap(array[part],array[left]);
return left;
}
void qs(float * array, const int left, const int right){
if(left < right){
const int part = partition(array, left, right);
qs(array, part + 1,right);
qs(array, left,part - 1);
}
}
/**
* @brief Quicksort
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details Quicksort
*
* @param array elements array
* @param size array size
*/
void serialQuickSort(float *array, const int size){
qs(array, 0,size-1);
}
/**
* @brief Calculate times median
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the median from a set of times.
*
* @param h_times times array.
* @param N array size.
*
* @return time median.
*/
float getMedianTime(float *h_times, int N)
{
float median = 0;
float * h_sorted_times = (float *)malloc(N * sizeof(float));
for(int n = 0; n < N; n++)
h_sorted_times[n] = h_times[n];
//Sort execution times
serialQuickSort(h_sorted_times, N);
//Calculate median
if(N%2 == 0)
{
median = (h_sorted_times[N/2] + h_sorted_times[(N/2)+1])/2;
}
else
{
int p = N/2;
median = h_sorted_times[p];
}
free(h_sorted_times);
return median;
}
/**
* @brief Calculate PCIe HTD latency.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for HTD memory transfers.
*
* @param d_data device data.
* @param h_data host data.
* @param nreps iterations.
* @return HTD PCIe latency (ms).
*/
float getLoHTD(char *d_data, char *h_data, int nreps)
{
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
float LoHTD = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
cudaEventRecord(start_event, 0);
//we only transfer 1 byte.
cudaMemcpy(d_data, h_data, sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&LoHTD, start_event, stop_event);
h_times[k] = LoHTD;
}
LoHTD = getMedianTime(h_times, nreps);
free(h_times);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return LoHTD;
}
/**
* @brief Calculate PCIe DTH latency
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param nreps iterations
* @return DTH PCIe latency (ms).
*/
float getLoDTH(char *d_data, char *h_data, int nreps)
{
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
float LoDTH = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
cudaEventRecord(start_event, 0);
//we only transfer 1 byte.
cudaMemcpy(h_data, d_data, sizeof(char), cudaMemcpyDeviceToHost);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&LoDTH, start_event, stop_event);
h_times[k] = LoDTH;
}
LoDTH = getMedianTime(h_times, nreps);
free(h_times);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return LoDTH;
}
/**
* @brief DTH PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return DTH PCIe bandwidth (ms/byte).
*/
float getGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, 0);
cudaMemcpy(h_data, d_data, size * 1024 * 1024* sizeof(char), cudaMemcpyDeviceToHost);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GDTH;
}
/**
* @brief HTD PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return HTD PCIe bandwidth (ms/byte).
*/
float getGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, 0);
cudaMemcpy(d_data, h_data, size * 1024 * 1024* sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GHTD;
}
/**
* @brief Overlap DTH PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers, when a DTH memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return Overlap DTH PCIe bandwidth (byte/ms).
*/
float getOverlappedGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
cudaStream_t *stream_benchmark = (cudaStream_t *)malloc(2 * sizeof(cudaStream_t));
for(int i = 0; i < 2; i++)
cudaStreamCreate(&(stream_benchmark[i]));
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, stream_benchmark[0]);
//DTH
cudaMemcpyAsync(h_data,
d_data,
size * 1024 * 1024* sizeof(char),
cudaMemcpyDeviceToHost, stream_benchmark[0]);
cudaEventRecord(stop_event, stream_benchmark[0]);
//HTD
cudaMemcpyAsync(d_data + (size * 1024 * 1024),
h_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
cudaMemcpyHostToDevice, stream_benchmark[1]);
cudaDeviceSynchronize();
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
for(int i = 0; i < 2; i++)
cudaStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GDTH;
}
/**
* @brief Overlap HTD PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers, when a HTD memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return Overlap HTD PCIe bandwidth (byte/ms).
*/
float getOverlappedGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
cudaStream_t *stream_benchmark = (cudaStream_t *)malloc(2 * sizeof(cudaStream_t));
for(int i = 0; i < 2; i++)
cudaStreamCreate(&(stream_benchmark[i]));
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, stream_benchmark[0]);
cudaMemcpyAsync(d_data,
h_data,
size * 1024 * 1024* sizeof(char),
cudaMemcpyHostToDevice, stream_benchmark[0]);
cudaEventRecord(stop_event, stream_benchmark[0]);
cudaMemcpyAsync(h_data + (size * 1024 * 1024),
d_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
cudaMemcpyDeviceToHost, stream_benchmark[1]);
cudaDeviceSynchronize();
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
for(int i = 0; i < 2; i++)
cudaStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GHTD;
}
/**
* @brief PCIe microbenchmarking.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function calculates the values of PCIe latency and bandwidth
* for HTD and DTH memory transfers.
*
* @param gpu GPU id.
* @param LoHTD PCIe HTD latency (pointer).
* @param LoDTH PCIe DTH latency (pointer).
* @param GHTD HTD PCIe bandwidth (pointer).
* @param overlappedGHTD Overlap HTD PCIe bandwidth (pointer).
* @param GDTH DTH PCIe bandwidth (pointer).
* @param overlappedGDTH Overlap DTH PCIe bandwidth (pointer).
* @param nIter Iterations.
*/
void microbenchmarkingPCI(int gpu, float *LoHTD, float *LoDTH, float *GHTD, float *overlappedGHTD,
float *GDTH, float *overlappedGDTH, int nIter)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, gpu);
cudaSetDevice(gpu);
int tam = 1024*1024*1024; // 1GB
char *h_data_benchmark; cudaMallocHost((void**)&h_data_benchmark, tam * sizeof(char));
memset(h_data_benchmark, 0, tam * sizeof(char));
char *d_data_benchmark; cudaMalloc((void **)&d_data_benchmark, tam * sizeof(char));
cudaMemset(d_data_benchmark, 0, tam * sizeof(char));
*LoHTD = getLoHTD(d_data_benchmark, h_data_benchmark, nIter);
*GHTD = getGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
if(props.asyncEngineCount == 2)
*overlappedGHTD = getOverlappedGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
*LoDTH = getLoDTH(d_data_benchmark, h_data_benchmark, nIter);
*GDTH = getGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
if(props.asyncEngineCount == 2)
*overlappedGDTH = getOverlappedGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
cudaFreeHost(h_data_benchmark);
cudaFree(d_data_benchmark);
} | .file "tmpxft_0000eb66_00000000-6_microbenchmarking_transfers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapRfS_
.type _Z4swapRfS_, @function
_Z4swapRfS_:
.LFB2057:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
movss (%rsi), %xmm1
movss %xmm1, (%rdi)
movss %xmm0, (%rsi)
ret
.cfi_endproc
.LFE2057:
.size _Z4swapRfS_, .-_Z4swapRfS_
.globl _Z9partitionPfii
.type _Z9partitionPfii, @function
_Z9partitionPfii:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %rcx
movl %esi, %edi
movl %edx, %eax
leal (%rdx,%rsi), %esi
movl %esi, %edx
shrl $31, %edx
addl %esi, %edx
sarl %edx
movslq %edx, %rdx
leaq (%rcx,%rdx,4), %rdx
movslq %eax, %rsi
leaq (%rcx,%rsi,4), %r9
movss (%r9), %xmm0
movss (%rdx), %xmm1
movss %xmm1, (%r9)
movss %xmm0, (%rdx)
subl $1, %eax
movslq %edi, %rdx
leaq (%rcx,%rdx,4), %rsi
jmp .L5
.L10:
cmpl %eax, %edx
jg .L7
movslq %eax, %rdx
leaq (%rcx,%rdx,4), %rdx
movss (%rdx), %xmm0
movss %xmm0, (%r8)
movss %xmm2, (%rdx)
subl $1, %eax
.L6:
addq $4, %rsi
addl $1, %edi
.L5:
movq %rsi, %r8
movss (%rsi), %xmm2
movss (%r9), %xmm1
comiss %xmm2, %xmm1
ja .L6
movl %edi, %edx
cmpl %eax, %edi
jg .L7
cltq
.L8:
movss (%rcx,%rax,4), %xmm0
comiss %xmm1, %xmm0
jb .L10
subq $1, %rax
cmpl %eax, %edx
jle .L8
.L7:
movss %xmm2, (%r9)
movss %xmm1, (%r8)
movl %edx, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z9partitionPfii, .-_Z9partitionPfii
.globl _Z2qsPfii
.type _Z2qsPfii, @function
_Z2qsPfii:
.LFB2059:
.cfi_startproc
endbr64
cmpl %edx, %esi
jl .L17
ret
.L17:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %ebp
call _Z9partitionPfii
movl %eax, %r13d
leal 1(%rax), %esi
movl %ebp, %edx
movq %r12, %rdi
call _Z2qsPfii
leal -1(%r13), %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z2qsPfii
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z2qsPfii, .-_Z2qsPfii
.globl _Z15serialQuickSortPfi
.type _Z15serialQuickSortPfi, @function
_Z15serialQuickSortPfi:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leal -1(%rsi), %edx
movl $0, %esi
call _Z2qsPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z15serialQuickSortPfi, .-_Z15serialQuickSortPfi
.globl _Z13getMedianTimePfi
.type _Z13getMedianTimePfi, @function
_Z13getMedianTimePfi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %r13d
movslq %esi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r13d, %r13d
jle .L21
movl $0, %eax
.L22:
movss (%r12,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rax, %rbp
jne .L22
.L21:
movl %r13d, %esi
movq %rbx, %rdi
call _Z15serialQuickSortPfi
testb $1, %r13b
jne .L23
movl %r13d, %eax
shrl $31, %eax
addl %r13d, %eax
sarl %eax
cltq
movss 4(%rbx,%rax,4), %xmm0
addss (%rbx,%rax,4), %xmm0
mulss .LC0(%rip), %xmm0
movd %xmm0, %ebp
.L24:
movq %rbx, %rdi
call free@PLT
movd %ebp, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %r13d, %eax
shrl $31, %eax
addl %r13d, %eax
sarl %eax
cltq
movl (%rbx,%rax,4), %ebp
jmp .L24
.cfi_endproc
.LFE2061:
.size _Z13getMedianTimePfi, .-_Z13getMedianTimePfi
.globl _Z8getLoHTDPcS_i
.type _Z8getLoHTDPcS_i, @function
_Z8getLoHTDPcS_i:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 20(%rsp)
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
testl %ebx, %ebx
jle .L28
movq %r15, %rbx
addq %r15, %rbp
leaq 20(%rsp), %r14
.L29:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $1, %edx
movq %r13, %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movss 20(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
.L28:
movl 12(%rsp), %esi
movq %r15, %rdi
call _Z13getMedianTimePfi
movss %xmm0, 20(%rsp)
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movss 20(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z8getLoHTDPcS_i, .-_Z8getLoHTDPcS_i
.globl _Z8getLoDTHPcS_i
.type _Z8getLoDTHPcS_i, @function
_Z8getLoDTHPcS_i:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 20(%rsp)
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
testl %ebx, %ebx
jle .L35
movq %r15, %rbx
addq %r15, %rbp
leaq 20(%rsp), %r14
.L36:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $1, %edx
movq %r12, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movss 20(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L36
.L35:
movl 12(%rsp), %esi
movq %r15, %rdi
call _Z13getMedianTimePfi
movss %xmm0, 20(%rsp)
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movss 20(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z8getLoDTHPcS_i, .-_Z8getLoDTHPcS_i
.globl _Z7getGDTHPcS_fi
.type _Z7getGDTHPcS_fi, @function
_Z7getGDTHPcS_fi:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, (%rsp)
movq %rsi, %r13
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, %ebp
movl $0, %r14d
movl $0, %ebx
movl $0x00000000, 8(%rsp)
leaq 20(%rsp), %r15
.L42:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebp, %r12d
sall $20, %r12d
movslq %r12d, %rdx
movl $2, %ecx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaEventElapsedTime@PLT
movss 8(%rsp), %xmm2
addss 20(%rsp), %xmm2
movss %xmm2, 8(%rsp)
addl %r12d, %r14d
addl $1, %ebx
addl %ebp, %ebp
cmpl $6, %ebx
jne .L42
movss 12(%rsp), %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
divss %xmm0, %xmm1
movd %xmm1, %r13d
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L46
movd %r13d, %xmm0
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z7getGDTHPcS_fi, .-_Z7getGDTHPcS_fi
.globl _Z7getGHTDPcS_fi
.type _Z7getGHTDPcS_fi, @function
_Z7getGHTDPcS_fi:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, (%rsp)
movq %rsi, %r13
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, %ebp
movl $0, %r14d
movl $0, %ebx
movl $0x00000000, 8(%rsp)
leaq 20(%rsp), %r15
.L48:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebp, %r12d
sall $20, %r12d
movslq %r12d, %rdx
movl $1, %ecx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaEventElapsedTime@PLT
movss 8(%rsp), %xmm2
addss 20(%rsp), %xmm2
movss %xmm2, 8(%rsp)
addl %r12d, %r14d
addl $1, %ebx
addl %ebp, %ebp
cmpl $6, %ebx
jne .L48
movss 12(%rsp), %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
divss %xmm0, %xmm1
movd %xmm1, %r13d
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
movd %r13d, %xmm0
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z7getGHTDPcS_fi, .-_Z7getGHTDPcS_fi
.globl _Z17getOverlappedGDTHPcS_fi
.type _Z17getOverlappedGDTHPcS_fi, @function
_Z17getOverlappedGDTHPcS_fi:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movss %xmm0, 28(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0x00000000, 36(%rsp)
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, %rdi
call cudaStreamCreate@PLT
leaq 8(%rbx), %rdi
call cudaStreamCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, %r13d
movl $0, %r15d
movl $0, %r12d
movl $0x00000000, 24(%rsp)
leaq 36(%rsp), %rax
movq %rax, 16(%rsp)
.L54:
movq (%rbx), %rsi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r14d
sall $20, %r14d
movslq %r14d, %rbp
movq (%rbx), %r8
movl $2, %ecx
movq %rbp, %rdx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq (%rbx), %rsi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rax
leaq (%rax,%rbp), %rsi
movq (%rsp), %rax
leaq (%rax,%rbp), %rdi
movq 8(%rbx), %r8
movl $1, %ecx
movq %rbp, %rdx
call cudaMemcpyAsync@PLT
call cudaDeviceSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaEventElapsedTime@PLT
movss 24(%rsp), %xmm2
addss 36(%rsp), %xmm2
movss %xmm2, 24(%rsp)
addl %r14d, %r15d
addl $1, %r12d
addl %r13d, %r13d
cmpl $6, %r12d
jne .L54
movss 28(%rsp), %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
divss %xmm0, %xmm1
movd %xmm1, %r15d
movq (%rbx), %rdi
call cudaStreamDestroy@PLT
movq 8(%rbx), %rdi
call cudaStreamDestroy@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L58
movd %r15d, %xmm0
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z17getOverlappedGDTHPcS_fi, .-_Z17getOverlappedGDTHPcS_fi
.globl _Z17getOverlappedGHTDPcS_fi
.type _Z17getOverlappedGHTDPcS_fi, @function
_Z17getOverlappedGHTDPcS_fi:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movss %xmm0, 28(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0x00000000, 36(%rsp)
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, %rdi
call cudaStreamCreate@PLT
leaq 8(%rbx), %rdi
call cudaStreamCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, %r13d
movl $0, %r15d
movl $0, %r12d
movl $0x00000000, 24(%rsp)
leaq 36(%rsp), %rax
movq %rax, 16(%rsp)
.L60:
movq (%rbx), %rsi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r14d
sall $20, %r14d
movslq %r14d, %rbp
movq (%rbx), %r8
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpyAsync@PLT
movq (%rbx), %rsi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq (%rsp), %rax
leaq (%rax,%rbp), %rsi
movq 8(%rsp), %rax
leaq (%rax,%rbp), %rdi
movq 8(%rbx), %r8
movl $2, %ecx
movq %rbp, %rdx
call cudaMemcpyAsync@PLT
call cudaDeviceSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaEventElapsedTime@PLT
movss 24(%rsp), %xmm2
addss 36(%rsp), %xmm2
movss %xmm2, 24(%rsp)
addl %r14d, %r15d
addl $1, %r12d
addl %r13d, %r13d
cmpl $6, %r12d
jne .L60
movss 28(%rsp), %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
divss %xmm0, %xmm1
movd %xmm1, %r15d
movq (%rbx), %rdi
call cudaStreamDestroy@PLT
movq 8(%rbx), %rdi
call cudaStreamDestroy@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L64
movd %r15d, %xmm0
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z17getOverlappedGHTDPcS_fi, .-_Z17getOverlappedGHTDPcS_fi
.globl _Z20microbenchmarkingPCIiPfS_S_S_S_S_i
.type _Z20microbenchmarkingPCIiPfS_S_S_S_S_i, @function
_Z20microbenchmarkingPCIiPfS_S_S_S_S_i:
.LFB2068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1080, %rsp
.cfi_def_cfa_offset 1136
movl %edi, %ebp
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %r14
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq 1136(%rsp), %r15
movl 1144(%rsp), %ebx
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl %ebp, %esi
call cudaGetDeviceProperties_v2@PLT
movl %ebp, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMallocHost@PLT
movl $1073741824, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call memset@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1073741824, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z8getLoHTDPcS_i
movss %xmm0, 0(%r13)
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z7getGHTDPcS_fi
movss %xmm0, (%r14)
cmpl $2, 632(%rsp)
je .L70
.L66:
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z8getLoDTHPcS_i
movss %xmm0, (%r12)
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z7getGDTHPcS_fi
movq (%rsp), %rax
movss %xmm0, (%rax)
cmpl $2, 632(%rsp)
je .L71
.L67:
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
movss 0(%r13), %xmm0
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z17getOverlappedGHTDPcS_fi
movq 8(%rsp), %rax
movss %xmm0, (%rax)
jmp .L66
.L71:
movss (%r12), %xmm0
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z17getOverlappedGDTHPcS_fi
movss %xmm0, (%r15)
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z20microbenchmarkingPCIiPfS_S_S_S_S_i, .-_Z20microbenchmarkingPCIiPfS_S_S_S_S_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.align 4
.LC2:
.long 1086324736
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* @file microbenchmarking_transfers.cu
* @detail This file describes the implementation of the functions involved in the
* PCIe bandwidth and latency.
* @author Antonio Jose Lazaro Munoz.
* @date 20/02/2016
*/
#include <stdio.h>
void swap(float & v1, float & v2){
float tmp = v1;
v1 = v2;
v2 = tmp;
}
int partition(float *array, int left, int right){
int part = right;
swap(array[part],array[(right+left) / 2]);
--right;
while(true){
while(array[left] < array[part]){
++left;
}
while(right >= left && array[part] <= array[right]){
--right;
}
if(right < left) break;
swap(array[left],array[right]);
++left;
--right;
}
swap(array[part],array[left]);
return left;
}
void qs(float * array, const int left, const int right){
if(left < right){
const int part = partition(array, left, right);
qs(array, part + 1,right);
qs(array, left,part - 1);
}
}
/**
* @brief Quicksort
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details Quicksort
*
* @param array elements array
* @param size array size
*/
void serialQuickSort(float *array, const int size){
qs(array, 0,size-1);
}
/**
* @brief Calculate times median
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the median from a set of times.
*
* @param h_times times array.
* @param N array size.
*
* @return time median.
*/
float getMedianTime(float *h_times, int N)
{
float median = 0;
float * h_sorted_times = (float *)malloc(N * sizeof(float));
for(int n = 0; n < N; n++)
h_sorted_times[n] = h_times[n];
//Sort execution times
serialQuickSort(h_sorted_times, N);
//Calculate median
if(N%2 == 0)
{
median = (h_sorted_times[N/2] + h_sorted_times[(N/2)+1])/2;
}
else
{
int p = N/2;
median = h_sorted_times[p];
}
free(h_sorted_times);
return median;
}
/**
* @brief Calculate PCIe HTD latency.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for HTD memory transfers.
*
* @param d_data device data.
* @param h_data host data.
* @param nreps iterations.
* @return HTD PCIe latency (ms).
*/
float getLoHTD(char *d_data, char *h_data, int nreps)
{
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
float LoHTD = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
cudaEventRecord(start_event, 0);
//we only transfer 1 byte.
cudaMemcpy(d_data, h_data, sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&LoHTD, start_event, stop_event);
h_times[k] = LoHTD;
}
LoHTD = getMedianTime(h_times, nreps);
free(h_times);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return LoHTD;
}
/**
* @brief Calculate PCIe DTH latency
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param nreps iterations
* @return DTH PCIe latency (ms).
*/
float getLoDTH(char *d_data, char *h_data, int nreps)
{
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
float LoDTH = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
cudaEventRecord(start_event, 0);
//we only transfer 1 byte.
cudaMemcpy(h_data, d_data, sizeof(char), cudaMemcpyDeviceToHost);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&LoDTH, start_event, stop_event);
h_times[k] = LoDTH;
}
LoDTH = getMedianTime(h_times, nreps);
free(h_times);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return LoDTH;
}
/**
* @brief DTH PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return DTH PCIe bandwidth (ms/byte).
*/
float getGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, 0);
cudaMemcpy(h_data, d_data, size * 1024 * 1024* sizeof(char), cudaMemcpyDeviceToHost);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GDTH;
}
/**
* @brief HTD PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return HTD PCIe bandwidth (ms/byte).
*/
float getGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, 0);
cudaMemcpy(d_data, h_data, size * 1024 * 1024* sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GHTD;
}
/**
* @brief Overlap DTH PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers, when a DTH memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return Overlap DTH PCIe bandwidth (byte/ms).
*/
float getOverlappedGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
cudaStream_t *stream_benchmark = (cudaStream_t *)malloc(2 * sizeof(cudaStream_t));
for(int i = 0; i < 2; i++)
cudaStreamCreate(&(stream_benchmark[i]));
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, stream_benchmark[0]);
//DTH
cudaMemcpyAsync(h_data,
d_data,
size * 1024 * 1024* sizeof(char),
cudaMemcpyDeviceToHost, stream_benchmark[0]);
cudaEventRecord(stop_event, stream_benchmark[0]);
//HTD
cudaMemcpyAsync(d_data + (size * 1024 * 1024),
h_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
cudaMemcpyHostToDevice, stream_benchmark[1]);
cudaDeviceSynchronize();
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
for(int i = 0; i < 2; i++)
cudaStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GDTH;
}
/**
* @brief Overlap HTD PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers, when a HTD memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return Overlap HTD PCIe bandwidth (byte/ms).
*/
float getOverlappedGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
cudaStream_t *stream_benchmark = (cudaStream_t *)malloc(2 * sizeof(cudaStream_t));
for(int i = 0; i < 2; i++)
cudaStreamCreate(&(stream_benchmark[i]));
cudaEvent_t start_event, stop_event;
cudaEventCreate(&start_event);
cudaEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
cudaEventRecord(start_event, stream_benchmark[0]);
cudaMemcpyAsync(d_data,
h_data,
size * 1024 * 1024* sizeof(char),
cudaMemcpyHostToDevice, stream_benchmark[0]);
cudaEventRecord(stop_event, stream_benchmark[0]);
cudaMemcpyAsync(h_data + (size * 1024 * 1024),
d_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
cudaMemcpyDeviceToHost, stream_benchmark[1]);
cudaDeviceSynchronize();
cudaEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
for(int i = 0; i < 2; i++)
cudaStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
cudaEventDestroy(start_event);
cudaEventDestroy(stop_event);
return GHTD;
}
/**
* @brief PCIe microbenchmarking.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function calculates the values of PCIe latency and bandwidth
* for HTD and DTH memory transfers.
*
* @param gpu GPU id.
* @param LoHTD PCIe HTD latency (pointer).
* @param LoDTH PCIe DTH latency (pointer).
* @param GHTD HTD PCIe bandwidth (pointer).
* @param overlappedGHTD Overlap HTD PCIe bandwidth (pointer).
* @param GDTH DTH PCIe bandwidth (pointer).
* @param overlappedGDTH Overlap DTH PCIe bandwidth (pointer).
* @param nIter Iterations.
*/
void microbenchmarkingPCI(int gpu, float *LoHTD, float *LoDTH, float *GHTD, float *overlappedGHTD,
float *GDTH, float *overlappedGDTH, int nIter)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, gpu);
cudaSetDevice(gpu);
int tam = 1024*1024*1024; // 1GB
char *h_data_benchmark; cudaMallocHost((void**)&h_data_benchmark, tam * sizeof(char));
memset(h_data_benchmark, 0, tam * sizeof(char));
char *d_data_benchmark; cudaMalloc((void **)&d_data_benchmark, tam * sizeof(char));
cudaMemset(d_data_benchmark, 0, tam * sizeof(char));
*LoHTD = getLoHTD(d_data_benchmark, h_data_benchmark, nIter);
*GHTD = getGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
if(props.asyncEngineCount == 2)
*overlappedGHTD = getOverlappedGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
*LoDTH = getLoDTH(d_data_benchmark, h_data_benchmark, nIter);
*GDTH = getGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
if(props.asyncEngineCount == 2)
*overlappedGDTH = getOverlappedGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
cudaFreeHost(h_data_benchmark);
cudaFree(d_data_benchmark);
} | /**
* @file microbenchmarking_transfers.cu
* @detail This file describes the implementation of the functions involved in the
* PCIe bandwidth and latency.
* @author Antonio Jose Lazaro Munoz.
* @date 20/02/2016
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void swap(float & v1, float & v2){
float tmp = v1;
v1 = v2;
v2 = tmp;
}
int partition(float *array, int left, int right){
int part = right;
swap(array[part],array[(right+left) / 2]);
--right;
while(true){
while(array[left] < array[part]){
++left;
}
while(right >= left && array[part] <= array[right]){
--right;
}
if(right < left) break;
swap(array[left],array[right]);
++left;
--right;
}
swap(array[part],array[left]);
return left;
}
void qs(float * array, const int left, const int right){
if(left < right){
const int part = partition(array, left, right);
qs(array, part + 1,right);
qs(array, left,part - 1);
}
}
/**
* @brief Quicksort
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details Quicksort
*
* @param array elements array
* @param size array size
*/
void serialQuickSort(float *array, const int size){
qs(array, 0,size-1);
}
/**
* @brief Calculate times median
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the median from a set of times.
*
* @param h_times times array.
* @param N array size.
*
* @return time median.
*/
float getMedianTime(float *h_times, int N)
{
float median = 0;
float * h_sorted_times = (float *)malloc(N * sizeof(float));
for(int n = 0; n < N; n++)
h_sorted_times[n] = h_times[n];
//Sort execution times
serialQuickSort(h_sorted_times, N);
//Calculate median
if(N%2 == 0)
{
median = (h_sorted_times[N/2] + h_sorted_times[(N/2)+1])/2;
}
else
{
int p = N/2;
median = h_sorted_times[p];
}
free(h_sorted_times);
return median;
}
/**
* @brief Calculate PCIe HTD latency.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for HTD memory transfers.
*
* @param d_data device data.
* @param h_data host data.
* @param nreps iterations.
* @return HTD PCIe latency (ms).
*/
float getLoHTD(char *d_data, char *h_data, int nreps)
{
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
float LoHTD = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
hipEventRecord(start_event, 0);
//we only transfer 1 byte.
hipMemcpy(d_data, h_data, sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&LoHTD, start_event, stop_event);
h_times[k] = LoHTD;
}
LoHTD = getMedianTime(h_times, nreps);
free(h_times);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return LoHTD;
}
/**
* @brief Calculate PCIe DTH latency
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param nreps iterations
* @return DTH PCIe latency (ms).
*/
float getLoDTH(char *d_data, char *h_data, int nreps)
{
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
float LoDTH = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
hipEventRecord(start_event, 0);
//we only transfer 1 byte.
hipMemcpy(h_data, d_data, sizeof(char), hipMemcpyDeviceToHost);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&LoDTH, start_event, stop_event);
h_times[k] = LoDTH;
}
LoDTH = getMedianTime(h_times, nreps);
free(h_times);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return LoDTH;
}
/**
* @brief DTH PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return DTH PCIe bandwidth (ms/byte).
*/
float getGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, 0);
hipMemcpy(h_data, d_data, size * 1024 * 1024* sizeof(char), hipMemcpyDeviceToHost);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GDTH;
}
/**
* @brief HTD PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return HTD PCIe bandwidth (ms/byte).
*/
float getGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, 0);
hipMemcpy(d_data, h_data, size * 1024 * 1024* sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GHTD;
}
/**
* @brief Overlap DTH PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers, when a DTH memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return Overlap DTH PCIe bandwidth (byte/ms).
*/
float getOverlappedGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
hipStream_t *stream_benchmark = (hipStream_t *)malloc(2 * sizeof(hipStream_t));
for(int i = 0; i < 2; i++)
hipStreamCreate(&(stream_benchmark[i]));
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, stream_benchmark[0]);
//DTH
hipMemcpyAsync(h_data,
d_data,
size * 1024 * 1024* sizeof(char),
hipMemcpyDeviceToHost, stream_benchmark[0]);
hipEventRecord(stop_event, stream_benchmark[0]);
//HTD
hipMemcpyAsync(d_data + (size * 1024 * 1024),
h_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
hipMemcpyHostToDevice, stream_benchmark[1]);
hipDeviceSynchronize();
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
for(int i = 0; i < 2; i++)
hipStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GDTH;
}
/**
* @brief Overlap HTD PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers, when a HTD memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return Overlap HTD PCIe bandwidth (byte/ms).
*/
float getOverlappedGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
hipStream_t *stream_benchmark = (hipStream_t *)malloc(2 * sizeof(hipStream_t));
for(int i = 0; i < 2; i++)
hipStreamCreate(&(stream_benchmark[i]));
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, stream_benchmark[0]);
hipMemcpyAsync(d_data,
h_data,
size * 1024 * 1024* sizeof(char),
hipMemcpyHostToDevice, stream_benchmark[0]);
hipEventRecord(stop_event, stream_benchmark[0]);
hipMemcpyAsync(h_data + (size * 1024 * 1024),
d_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
hipMemcpyDeviceToHost, stream_benchmark[1]);
hipDeviceSynchronize();
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
for(int i = 0; i < 2; i++)
hipStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GHTD;
}
/**
* @brief PCIe microbenchmarking.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function calculates the values of PCIe latency and bandwidth
* for HTD and DTH memory transfers.
*
* @param gpu GPU id.
* @param LoHTD PCIe HTD latency (pointer).
* @param LoDTH PCIe DTH latency (pointer).
* @param GHTD HTD PCIe bandwidth (pointer).
* @param overlappedGHTD Overlap HTD PCIe bandwidth (pointer).
* @param GDTH DTH PCIe bandwidth (pointer).
* @param overlappedGDTH Overlap DTH PCIe bandwidth (pointer).
* @param nIter Iterations.
*/
void microbenchmarkingPCI(int gpu, float *LoHTD, float *LoDTH, float *GHTD, float *overlappedGHTD,
float *GDTH, float *overlappedGDTH, int nIter)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, gpu);
hipSetDevice(gpu);
int tam = 1024*1024*1024; // 1GB
char *h_data_benchmark; hipHostMalloc((void**)&h_data_benchmark, tam * sizeof(char), hipHostMallocDefault);
memset(h_data_benchmark, 0, tam * sizeof(char));
char *d_data_benchmark; hipMalloc((void **)&d_data_benchmark, tam * sizeof(char));
hipMemset(d_data_benchmark, 0, tam * sizeof(char));
*LoHTD = getLoHTD(d_data_benchmark, h_data_benchmark, nIter);
*GHTD = getGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
if(props.asyncEngineCount == 2)
*overlappedGHTD = getOverlappedGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
*LoDTH = getLoDTH(d_data_benchmark, h_data_benchmark, nIter);
*GDTH = getGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
if(props.asyncEngineCount == 2)
*overlappedGDTH = getOverlappedGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
hipHostFree(h_data_benchmark);
hipFree(d_data_benchmark);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* @file microbenchmarking_transfers.cu
* @detail This file describes the implementation of the functions involved in the
* PCIe bandwidth and latency.
* @author Antonio Jose Lazaro Munoz.
* @date 20/02/2016
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void swap(float & v1, float & v2){
float tmp = v1;
v1 = v2;
v2 = tmp;
}
int partition(float *array, int left, int right){
int part = right;
swap(array[part],array[(right+left) / 2]);
--right;
while(true){
while(array[left] < array[part]){
++left;
}
while(right >= left && array[part] <= array[right]){
--right;
}
if(right < left) break;
swap(array[left],array[right]);
++left;
--right;
}
swap(array[part],array[left]);
return left;
}
void qs(float * array, const int left, const int right){
if(left < right){
const int part = partition(array, left, right);
qs(array, part + 1,right);
qs(array, left,part - 1);
}
}
/**
* @brief Quicksort
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details Quicksort
*
* @param array elements array
* @param size array size
*/
void serialQuickSort(float *array, const int size){
qs(array, 0,size-1);
}
/**
* @brief Calculate times median
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the median from a set of times.
*
* @param h_times times array.
* @param N array size.
*
* @return time median.
*/
float getMedianTime(float *h_times, int N)
{
float median = 0;
float * h_sorted_times = (float *)malloc(N * sizeof(float));
for(int n = 0; n < N; n++)
h_sorted_times[n] = h_times[n];
//Sort execution times
serialQuickSort(h_sorted_times, N);
//Calculate median
if(N%2 == 0)
{
median = (h_sorted_times[N/2] + h_sorted_times[(N/2)+1])/2;
}
else
{
int p = N/2;
median = h_sorted_times[p];
}
free(h_sorted_times);
return median;
}
/**
* @brief Calculate PCIe HTD latency.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for HTD memory transfers.
*
* @param d_data device data.
* @param h_data host data.
* @param nreps iterations.
* @return HTD PCIe latency (ms).
*/
float getLoHTD(char *d_data, char *h_data, int nreps)
{
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
float LoHTD = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
hipEventRecord(start_event, 0);
//we only transfer 1 byte.
hipMemcpy(d_data, h_data, sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&LoHTD, start_event, stop_event);
h_times[k] = LoHTD;
}
LoHTD = getMedianTime(h_times, nreps);
free(h_times);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return LoHTD;
}
/**
* @brief Calculate PCIe DTH latency
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param nreps iterations
* @return DTH PCIe latency (ms).
*/
float getLoDTH(char *d_data, char *h_data, int nreps)
{
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
float LoDTH = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
hipEventRecord(start_event, 0);
//we only transfer 1 byte.
hipMemcpy(h_data, d_data, sizeof(char), hipMemcpyDeviceToHost);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&LoDTH, start_event, stop_event);
h_times[k] = LoDTH;
}
LoDTH = getMedianTime(h_times, nreps);
free(h_times);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return LoDTH;
}
/**
* @brief DTH PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return DTH PCIe bandwidth (ms/byte).
*/
float getGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, 0);
hipMemcpy(h_data, d_data, size * 1024 * 1024* sizeof(char), hipMemcpyDeviceToHost);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GDTH;
}
/**
* @brief HTD PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return HTD PCIe bandwidth (ms/byte).
*/
float getGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, 0);
hipMemcpy(d_data, h_data, size * 1024 * 1024* sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GHTD;
}
/**
* @brief Overlap DTH PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers, when a DTH memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return Overlap DTH PCIe bandwidth (byte/ms).
*/
float getOverlappedGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
hipStream_t *stream_benchmark = (hipStream_t *)malloc(2 * sizeof(hipStream_t));
for(int i = 0; i < 2; i++)
hipStreamCreate(&(stream_benchmark[i]));
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, stream_benchmark[0]);
//DTH
hipMemcpyAsync(h_data,
d_data,
size * 1024 * 1024* sizeof(char),
hipMemcpyDeviceToHost, stream_benchmark[0]);
hipEventRecord(stop_event, stream_benchmark[0]);
//HTD
hipMemcpyAsync(d_data + (size * 1024 * 1024),
h_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
hipMemcpyHostToDevice, stream_benchmark[1]);
hipDeviceSynchronize();
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
for(int i = 0; i < 2; i++)
hipStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GDTH;
}
/**
* @brief Overlap HTD PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers, when a HTD memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return Overlap HTD PCIe bandwidth (byte/ms).
*/
float getOverlappedGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
hipStream_t *stream_benchmark = (hipStream_t *)malloc(2 * sizeof(hipStream_t));
for(int i = 0; i < 2; i++)
hipStreamCreate(&(stream_benchmark[i]));
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, stream_benchmark[0]);
hipMemcpyAsync(d_data,
h_data,
size * 1024 * 1024* sizeof(char),
hipMemcpyHostToDevice, stream_benchmark[0]);
hipEventRecord(stop_event, stream_benchmark[0]);
hipMemcpyAsync(h_data + (size * 1024 * 1024),
d_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
hipMemcpyDeviceToHost, stream_benchmark[1]);
hipDeviceSynchronize();
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
for(int i = 0; i < 2; i++)
hipStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GHTD;
}
/**
* @brief PCIe microbenchmarking.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function calculates the values of PCIe latency and bandwidth
* for HTD and DTH memory transfers.
*
* @param gpu GPU id.
* @param LoHTD PCIe HTD latency (pointer).
* @param LoDTH PCIe DTH latency (pointer).
* @param GHTD HTD PCIe bandwidth (pointer).
* @param overlappedGHTD Overlap HTD PCIe bandwidth (pointer).
* @param GDTH DTH PCIe bandwidth (pointer).
* @param overlappedGDTH Overlap DTH PCIe bandwidth (pointer).
* @param nIter Iterations.
*/
void microbenchmarkingPCI(int gpu, float *LoHTD, float *LoDTH, float *GHTD, float *overlappedGHTD,
float *GDTH, float *overlappedGDTH, int nIter)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, gpu);
hipSetDevice(gpu);
int tam = 1024*1024*1024; // 1GB
char *h_data_benchmark; hipHostMalloc((void**)&h_data_benchmark, tam * sizeof(char), hipHostMallocDefault);
memset(h_data_benchmark, 0, tam * sizeof(char));
char *d_data_benchmark; hipMalloc((void **)&d_data_benchmark, tam * sizeof(char));
hipMemset(d_data_benchmark, 0, tam * sizeof(char));
*LoHTD = getLoHTD(d_data_benchmark, h_data_benchmark, nIter);
*GHTD = getGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
if(props.asyncEngineCount == 2)
*overlappedGHTD = getOverlappedGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
*LoDTH = getLoDTH(d_data_benchmark, h_data_benchmark, nIter);
*GDTH = getGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
if(props.asyncEngineCount == 2)
*overlappedGDTH = getOverlappedGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
hipHostFree(h_data_benchmark);
hipFree(d_data_benchmark);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* @file microbenchmarking_transfers.cu
* @detail This file describes the implementation of the functions involved in the
* PCIe bandwidth and latency.
* @author Antonio Jose Lazaro Munoz.
* @date 20/02/2016
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
void swap(float & v1, float & v2){
float tmp = v1;
v1 = v2;
v2 = tmp;
}
int partition(float *array, int left, int right){
int part = right;
swap(array[part],array[(right+left) / 2]);
--right;
while(true){
while(array[left] < array[part]){
++left;
}
while(right >= left && array[part] <= array[right]){
--right;
}
if(right < left) break;
swap(array[left],array[right]);
++left;
--right;
}
swap(array[part],array[left]);
return left;
}
void qs(float * array, const int left, const int right){
if(left < right){
const int part = partition(array, left, right);
qs(array, part + 1,right);
qs(array, left,part - 1);
}
}
/**
* @brief Quicksort
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details Quicksort
*
* @param array elements array
* @param size array size
*/
void serialQuickSort(float *array, const int size){
qs(array, 0,size-1);
}
/**
* @brief Calculate times median
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the median from a set of times.
*
* @param h_times times array.
* @param N array size.
*
* @return time median.
*/
float getMedianTime(float *h_times, int N)
{
float median = 0;
float * h_sorted_times = (float *)malloc(N * sizeof(float));
for(int n = 0; n < N; n++)
h_sorted_times[n] = h_times[n];
//Sort execution times
serialQuickSort(h_sorted_times, N);
//Calculate median
if(N%2 == 0)
{
median = (h_sorted_times[N/2] + h_sorted_times[(N/2)+1])/2;
}
else
{
int p = N/2;
median = h_sorted_times[p];
}
free(h_sorted_times);
return median;
}
/**
* @brief Calculate PCIe HTD latency.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for HTD memory transfers.
*
* @param d_data device data.
* @param h_data host data.
* @param nreps iterations.
* @return HTD PCIe latency (ms).
*/
float getLoHTD(char *d_data, char *h_data, int nreps)
{
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
float LoHTD = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
hipEventRecord(start_event, 0);
//we only transfer 1 byte.
hipMemcpy(d_data, h_data, sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&LoHTD, start_event, stop_event);
h_times[k] = LoHTD;
}
LoHTD = getMedianTime(h_times, nreps);
free(h_times);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return LoHTD;
}
/**
* @brief Calculate PCIe DTH latency
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the latency of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param nreps iterations
* @return DTH PCIe latency (ms).
*/
float getLoDTH(char *d_data, char *h_data, int nreps)
{
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
float LoDTH = 0.0;
float *h_times = (float *)malloc(nreps * sizeof(float));
memset(h_times, 0, nreps * sizeof(float));
for(int k = 0; k < nreps; k++)
{
hipEventRecord(start_event, 0);
//we only transfer 1 byte.
hipMemcpy(h_data, d_data, sizeof(char), hipMemcpyDeviceToHost);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&LoDTH, start_event, stop_event);
h_times[k] = LoDTH;
}
LoDTH = getMedianTime(h_times, nreps);
free(h_times);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return LoDTH;
}
/**
* @brief DTH PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return DTH PCIe bandwidth (ms/byte).
*/
float getGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, 0);
hipMemcpy(h_data, d_data, size * 1024 * 1024* sizeof(char), hipMemcpyDeviceToHost);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GDTH;
}
/**
* @brief HTD PCIe bandwidth (ms/byte).
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return HTD PCIe bandwidth (ms/byte).
*/
float getGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, 0);
hipMemcpy(d_data, h_data, size * 1024 * 1024* sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GHTD;
}
/**
* @brief Overlap DTH PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for HTD memory transfers, when a DTH memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoDTH DTH PCIe latency.
* @param nreps Iterations.
* @return Overlap DTH PCIe bandwidth (byte/ms).
*/
float getOverlappedGDTH(char *d_data, char *h_data, float LoDTH, int nreps)
{
float time = 0;
float GDTH = 0.0;
float timeSumGDTH = 0.0;
hipStream_t *stream_benchmark = (hipStream_t *)malloc(2 * sizeof(hipStream_t));
for(int i = 0; i < 2; i++)
hipStreamCreate(&(stream_benchmark[i]));
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, stream_benchmark[0]);
//DTH
hipMemcpyAsync(h_data,
d_data,
size * 1024 * 1024* sizeof(char),
hipMemcpyDeviceToHost, stream_benchmark[0]);
hipEventRecord(stop_event, stream_benchmark[0]);
//HTD
hipMemcpyAsync(d_data + (size * 1024 * 1024),
h_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
hipMemcpyHostToDevice, stream_benchmark[1]);
hipDeviceSynchronize();
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGDTH += time;
total_bytes += size * 1024 * 1024;
n++;
}
GDTH = (timeSumGDTH - n*LoDTH)/total_bytes;
for(int i = 0; i < 2; i++)
hipStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GDTH;
}
/**
* @brief Overlap HTD PCIe bandwidth.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function returns the bandwidth of the PCIe for DTH memory transfers, when a HTD memory transfer
* is concurrently executed.
*
* @param d_data Device data.
* @param h_data Host data.
* @param LoHTD HTD PCIe latency.
* @param nreps Iterations.
* @return Overlap HTD PCIe bandwidth (byte/ms).
*/
float getOverlappedGHTD(char *d_data, char *h_data, float LoHTD, int nreps)
{
float time = 0;
float GHTD = 0.0;
float timeSumGHTD = 0.0;
hipStream_t *stream_benchmark = (hipStream_t *)malloc(2 * sizeof(hipStream_t));
for(int i = 0; i < 2; i++)
hipStreamCreate(&(stream_benchmark[i]));
hipEvent_t start_event, stop_event;
hipEventCreate(&start_event);
hipEventCreate(&stop_event);
int n = 0;
int total_bytes = 0;
//From 16 MB to 512 MB
for(int size = 16; size <= 512; size=size*2)
{
hipEventRecord(start_event, stream_benchmark[0]);
hipMemcpyAsync(d_data,
h_data,
size * 1024 * 1024* sizeof(char),
hipMemcpyHostToDevice, stream_benchmark[0]);
hipEventRecord(stop_event, stream_benchmark[0]);
hipMemcpyAsync(h_data + (size * 1024 * 1024),
d_data + (size * 1024 * 1024),
size * 1024 * 1024* sizeof(char),
hipMemcpyDeviceToHost, stream_benchmark[1]);
hipDeviceSynchronize();
hipEventElapsedTime(&time, start_event, stop_event);
timeSumGHTD += time;
total_bytes += size * 1024 * 1024;
n++;
}
GHTD = (timeSumGHTD - n*LoHTD)/total_bytes;
for(int i = 0; i < 2; i++)
hipStreamDestroy(stream_benchmark[i]);
free(stream_benchmark);
hipEventDestroy(start_event);
hipEventDestroy(stop_event);
return GHTD;
}
/**
* @brief PCIe microbenchmarking.
* @author Antonio Jose Lazaro Munoz
* @date 17/02/2016
* @details This function calculates the values of PCIe latency and bandwidth
* for HTD and DTH memory transfers.
*
* @param gpu GPU id.
* @param LoHTD PCIe HTD latency (pointer).
* @param LoDTH PCIe DTH latency (pointer).
* @param GHTD HTD PCIe bandwidth (pointer).
* @param overlappedGHTD Overlap HTD PCIe bandwidth (pointer).
* @param GDTH DTH PCIe bandwidth (pointer).
* @param overlappedGDTH Overlap DTH PCIe bandwidth (pointer).
* @param nIter Iterations.
*/
void microbenchmarkingPCI(int gpu, float *LoHTD, float *LoDTH, float *GHTD, float *overlappedGHTD,
float *GDTH, float *overlappedGDTH, int nIter)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, gpu);
hipSetDevice(gpu);
int tam = 1024*1024*1024; // 1GB
char *h_data_benchmark; hipHostMalloc((void**)&h_data_benchmark, tam * sizeof(char), hipHostMallocDefault);
memset(h_data_benchmark, 0, tam * sizeof(char));
char *d_data_benchmark; hipMalloc((void **)&d_data_benchmark, tam * sizeof(char));
hipMemset(d_data_benchmark, 0, tam * sizeof(char));
*LoHTD = getLoHTD(d_data_benchmark, h_data_benchmark, nIter);
*GHTD = getGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
if(props.asyncEngineCount == 2)
*overlappedGHTD = getOverlappedGHTD(d_data_benchmark, h_data_benchmark, *LoHTD, nIter);
*LoDTH = getLoDTH(d_data_benchmark, h_data_benchmark, nIter);
*GDTH = getGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
if(props.asyncEngineCount == 2)
*overlappedGDTH = getOverlappedGDTH(d_data_benchmark, h_data_benchmark, *LoDTH, nIter);
hipHostFree(h_data_benchmark);
hipFree(d_data_benchmark);
} | .text
.file "microbenchmarking_transfers.hip"
.globl _Z4swapRfS_ # -- Begin function _Z4swapRfS_
.p2align 4, 0x90
.type _Z4swapRfS_,@function
_Z4swapRfS_: # @_Z4swapRfS_
.cfi_startproc
# %bb.0:
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rdi)
movss %xmm0, (%rsi)
retq
.Lfunc_end0:
.size _Z4swapRfS_, .Lfunc_end0-_Z4swapRfS_
.cfi_endproc
# -- End function
.globl _Z9partitionPfii # -- Begin function _Z9partitionPfii
.p2align 4, 0x90
.type _Z9partitionPfii,@function
_Z9partitionPfii: # @_Z9partitionPfii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
# kill: def $edx killed $edx def $rdx
movl %esi, %eax
movabsq $-4294967296, %rsi # imm = 0xFFFFFFFF00000000
movslq %edx, %rcx
leal (%rcx,%rax), %r8d
movl %r8d, %r9d
shrl $31, %r9d
addl %r8d, %r9d
sarl %r9d
movslq %r9d, %r8
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rdi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%rdi,%rcx,4)
movss %xmm0, (%rdi,%r8,4)
leaq -4(%rdi), %r8
movabsq $4294967296, %r9 # imm = 0x100000000
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_4 Depth 2
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq %eax, %r11
leaq (%r8,%r11,4), %r10
shlq $32, %r11
addq %rsi, %r11
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
addq %r9, %r11
movss 4(%r10), %xmm1 # xmm1 = mem[0],zero,zero,zero
addq $4, %r10
incl %eax
ucomiss %xmm1, %xmm0
ja .LBB1_2
# %bb.3: # %.preheader
# in Loop: Header=BB1_1 Depth=1
movslq %edx, %rdx
sarq $32, %r11
movq %rdx, %rbx
shlq $32, %rbx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r11, %rdx
jle .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq %rdx, %r14
decq %rdx
movss (%r8,%r14,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addq %rsi, %rbx
ucomiss %xmm0, %xmm2
jae .LBB1_4
# %bb.6: # %.critedge
# in Loop: Header=BB1_1 Depth=1
cmpq %r11, %r14
jle .LBB1_8
# %bb.7: # in Loop: Header=BB1_1 Depth=1
sarq $30, %rbx
movss (%rdi,%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r10)
movss %xmm1, (%rdi,%rbx)
jmp .LBB1_1
.LBB1_8: # %.critedge33
movss %xmm1, (%rdi,%rcx,4)
movss %xmm0, (%r10)
decl %eax
# kill: def $eax killed $eax killed $rax
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9partitionPfii, .Lfunc_end1-_Z9partitionPfii
.cfi_endproc
# -- End function
.globl _Z2qsPfii # -- Begin function _Z2qsPfii
.p2align 4, 0x90
.type _Z2qsPfii,@function
_Z2qsPfii: # @_Z2qsPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movl %esi, %ebx
movq %rdi, %r14
movabsq $-4294967296, %r15 # imm = 0xFFFFFFFF00000000
leaq -4(%rdi), %r12
movabsq $4294967296, %r13 # imm = 0x100000000
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_9: # %_Z9partitionPfii.exit
# in Loop: Header=BB2_1 Depth=1
movss %xmm1, (%r14,%rax,4)
movss %xmm0, (%rsi)
movq %r14, %rdi
movl %ebp, %esi
# kill: def $edx killed $edx killed $rdx
callq _Z2qsPfii
addl $-2, %ebp
movl %ebp, %edx
.LBB2_1: # %tailrecurse
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
# Child Loop BB2_6 Depth 3
cmpl %edx, %ebx
jge .LBB2_10
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movslq %edx, %rax
leal (%rdx,%rbx), %ecx
movl %ecx, %esi
shrl $31, %esi
addl %ecx, %esi
sarl %esi
movslq %esi, %rcx
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%r14,%rax,4)
movss %xmm0, (%r14,%rcx,4)
movl %edx, %ecx
movl %ebx, %ebp
.LBB2_3: # Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
# Child Loop BB2_6 Depth 3
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq %ebp, %rdi
leaq (%r12,%rdi,4), %rsi
shlq $32, %rdi
addq %r15, %rdi
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
addq %r13, %rdi
movss 4(%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
addq $4, %rsi
incl %ebp
ucomiss %xmm1, %xmm0
ja .LBB2_4
# %bb.5: # %.preheader.i
# in Loop: Header=BB2_3 Depth=2
movslq %ecx, %rcx
sarq $32, %rdi
movq %rcx, %r8
shlq $32, %r8
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
cmpq %rdi, %rcx
jle .LBB2_9
# %bb.7: # in Loop: Header=BB2_6 Depth=3
movss -4(%r14,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
decq %rcx
addq %r15, %r8
ucomiss %xmm0, %xmm2
jae .LBB2_6
# %bb.8: # %.critedge.i
# in Loop: Header=BB2_3 Depth=2
sarq $30, %r8
movss (%r14,%r8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi)
movss %xmm1, (%r14,%r8)
jmp .LBB2_3
.LBB2_10:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z2qsPfii, .Lfunc_end2-_Z2qsPfii
.cfi_endproc
# -- End function
.globl _Z15serialQuickSortPfi # -- Begin function _Z15serialQuickSortPfi
.p2align 4, 0x90
.type _Z15serialQuickSortPfi,@function
_Z15serialQuickSortPfi: # @_Z15serialQuickSortPfi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
leal -1(%rsi), %edx
xorl %esi, %esi
jmp _Z2qsPfii # TAILCALL
.Lfunc_end3:
.size _Z15serialQuickSortPfi, .Lfunc_end3-_Z15serialQuickSortPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13getMedianTimePfi
.LCPI4_0:
.long 0x3f000000 # float 0.5
.text
.globl _Z13getMedianTimePfi
.p2align 4, 0x90
.type _Z13getMedianTimePfi,@function
_Z13getMedianTimePfi: # @_Z13getMedianTimePfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r14d
movq %rdi, %r15
movslq %esi, %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB4_2
# %bb.1: # %.lr.ph.preheader
movl %r14d, %edx
shlq $2, %rdx
movq %rbx, %rdi
movq %r15, %rsi
callq memcpy@PLT
.LBB4_2: # %._crit_edge
leal -1(%r14), %edx
movq %rbx, %rdi
xorl %esi, %esi
callq _Z2qsPfii
testb $1, %r14b
jne .LBB4_4
# %bb.3:
sarl %r14d
movslq %r14d, %rax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 4(%rbx,%rax,4), %xmm0
mulss .LCPI4_0(%rip), %xmm0
jmp .LBB4_5
.LBB4_4:
movl %r14d, %eax
shrl $31, %eax
addl %r14d, %eax
sarl %eax
cltq
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB4_5:
movss %xmm0, 4(%rsp) # 4-byte Spill
movq %rbx, %rdi
callq free
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z13getMedianTimePfi, .Lfunc_end4-_Z13getMedianTimePfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8getLoHTDPcS_i
.LCPI5_0:
.long 0x3f000000 # float 0.5
.text
.globl _Z8getLoHTDPcS_i
.p2align 4, 0x90
.type _Z8getLoHTDPcS_i,@function
_Z8getLoHTDPcS_i: # @_Z8getLoHTDPcS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r13d
movq %rsi, %r15
movq %rdi, %r12
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
movslq %r13d, %r14
leaq (,%r14,4), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %rbp, 32(%rsp) # 8-byte Spill
movq %rbp, %rdx
callq memset@PLT
movq %r13, 8(%rsp) # 8-byte Spill
movl %r13d, %ebp
testl %r14d, %r14d
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
leaq 4(%rsp), %r13
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1, %edx
movq %r12, %rdi
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r15
movq 8(%rsp), %r14 # 8-byte Reload
testl %r14d, %r14d
jle .LBB5_5
# %bb.4: # %.lr.ph.preheader.i
shlq $2, %rbp
movq %r15, %rdi
movq %rbx, %rsi
movq %rbp, %rdx
callq memcpy@PLT
.LBB5_5: # %._crit_edge.i
leal -1(%r14), %edx
movq %r15, %rdi
xorl %esi, %esi
callq _Z2qsPfii
testb $1, %r14b
jne .LBB5_7
# %bb.6:
sarl %r14d
movslq %r14d, %rax
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 4(%r15,%rax,4), %xmm0
mulss .LCPI5_0(%rip), %xmm0
jmp .LBB5_8
.LBB5_7:
movl %r14d, %eax
shrl $31, %eax
addl %r14d, %eax
sarl %eax
cltq
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB5_8: # %_Z13getMedianTimePfi.exit
movss %xmm0, 8(%rsp) # 4-byte Spill
movq %r15, %rdi
callq free
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8getLoHTDPcS_i, .Lfunc_end5-_Z8getLoHTDPcS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8getLoDTHPcS_i
.LCPI6_0:
.long 0x3f000000 # float 0.5
.text
.globl _Z8getLoDTHPcS_i
.p2align 4, 0x90
.type _Z8getLoDTHPcS_i,@function
_Z8getLoDTHPcS_i: # @_Z8getLoDTHPcS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r13d
movq %rsi, %r15
movq %rdi, %r12
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
movslq %r13d, %r14
leaq (,%r14,4), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %rbp, 32(%rsp) # 8-byte Spill
movq %rbp, %rdx
callq memset@PLT
movq %r13, 8(%rsp) # 8-byte Spill
movl %r13d, %ebp
testl %r14d, %r14d
jle .LBB6_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
leaq 4(%rsp), %r13
.p2align 4, 0x90
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1, %edx
movq %r15, %rdi
movq %r12, %rsi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB6_2
.LBB6_3: # %._crit_edge
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r15
movq 8(%rsp), %r14 # 8-byte Reload
testl %r14d, %r14d
jle .LBB6_5
# %bb.4: # %.lr.ph.preheader.i
shlq $2, %rbp
movq %r15, %rdi
movq %rbx, %rsi
movq %rbp, %rdx
callq memcpy@PLT
.LBB6_5: # %._crit_edge.i
leal -1(%r14), %edx
movq %r15, %rdi
xorl %esi, %esi
callq _Z2qsPfii
testb $1, %r14b
jne .LBB6_7
# %bb.6:
sarl %r14d
movslq %r14d, %rax
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 4(%r15,%rax,4), %xmm0
mulss .LCPI6_0(%rip), %xmm0
jmp .LBB6_8
.LBB6_7:
movl %r14d, %eax
shrl $31, %eax
addl %r14d, %eax
sarl %eax
cltq
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB6_8: # %_Z13getMedianTimePfi.exit
movss %xmm0, 8(%rsp) # 4-byte Spill
movq %r15, %rdi
callq free
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8getLoDTHPcS_i, .Lfunc_end6-_Z8getLoDTHPcS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7getGDTHPcS_fi
.LCPI7_0:
.long 0xc0c00000 # float -6
.LCPI7_1:
.long 0x4e7c0000 # float 1.05696461E+9
.text
.globl _Z7getGDTHPcS_fi
.p2align 4, 0x90
.type _Z7getGDTHPcS_fi,@function
_Z7getGDTHPcS_fi: # @_Z7getGDTHPcS_fi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 28(%rsp) # 4-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorps %xmm1, %xmm1
movl $16, %ebp
movl $6, %r12d
leaq 4(%rsp), %r15
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
movss %xmm1, (%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %ebp, %edx
shll $20, %edx
movq %rbx, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movss (%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss 4(%rsp), %xmm1
addl %ebp, %ebp
decl %r12d
jne .LBB7_1
# %bb.2:
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI7_0(%rip), %xmm0
addss %xmm0, %xmm1
divss .LCPI7_1(%rip), %xmm1
movss %xmm1, (%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z7getGDTHPcS_fi, .Lfunc_end7-_Z7getGDTHPcS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7getGHTDPcS_fi
.LCPI8_0:
.long 0xc0c00000 # float -6
.LCPI8_1:
.long 0x4e7c0000 # float 1.05696461E+9
.text
.globl _Z7getGHTDPcS_fi
.p2align 4, 0x90
.type _Z7getGHTDPcS_fi,@function
_Z7getGHTDPcS_fi: # @_Z7getGHTDPcS_fi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 28(%rsp) # 4-byte Spill
movq %rsi, %rbx
movq %rdi, %r14
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorps %xmm1, %xmm1
movl $16, %ebp
movl $6, %r12d
leaq 4(%rsp), %r15
.p2align 4, 0x90
.LBB8_1: # =>This Inner Loop Header: Depth=1
movss %xmm1, (%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %ebp, %edx
shll $20, %edx
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movss (%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss 4(%rsp), %xmm1
addl %ebp, %ebp
decl %r12d
jne .LBB8_1
# %bb.2:
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI8_0(%rip), %xmm0
addss %xmm0, %xmm1
divss .LCPI8_1(%rip), %xmm1
movss %xmm1, (%rsp) # 4-byte Spill
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z7getGHTDPcS_fi, .Lfunc_end8-_Z7getGHTDPcS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17getOverlappedGDTHPcS_fi
.LCPI9_0:
.long 0xc0c00000 # float -6
.LCPI9_1:
.long 0x4e7c0000 # float 1.05696461E+9
.text
.globl _Z17getOverlappedGDTHPcS_fi
.p2align 4, 0x90
.type _Z17getOverlappedGDTHPcS_fi,@function
_Z17getOverlappedGDTHPcS_fi: # @_Z17getOverlappedGDTHPcS_fi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 36(%rsp) # 4-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl $0, 12(%rsp)
movl $16, %edi
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r12), %rdi
callq hipStreamCreate
addq $8, %r12
cmpq $8, %r12
je .LBB9_1
# %bb.2:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
xorps %xmm0, %xmm0
movl $16, %ebp
movl $6, %r12d
.p2align 4, 0x90
.LBB9_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, 8(%rsp) # 4-byte Spill
movq 24(%rsp), %rdi
movq (%rbx), %rsi
callq hipEventRecord
movl %ebp, %r13d
shll $20, %r13d
movq (%rbx), %r8
movq %r14, %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
movq (%rbx), %rsi
callq hipEventRecord
leaq (%r15,%r13), %rdi
leaq (%r14,%r13), %rsi
movq 8(%rbx), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 12(%rsp), %xmm0
addl %ebp, %ebp
decl %r12d
jne .LBB9_3
# %bb.4: # %.preheader.preheader
movss %xmm0, 8(%rsp) # 4-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdi
callq hipStreamDestroy
incq %r14
cmpq $1, %r14
je .LBB9_5
# %bb.6:
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI9_0(%rip), %xmm0
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
divss .LCPI9_1(%rip), %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z17getOverlappedGDTHPcS_fi, .Lfunc_end9-_Z17getOverlappedGDTHPcS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17getOverlappedGHTDPcS_fi
.LCPI10_0:
.long 0xc0c00000 # float -6
.LCPI10_1:
.long 0x4e7c0000 # float 1.05696461E+9
.text
.globl _Z17getOverlappedGHTDPcS_fi
.p2align 4, 0x90
.type _Z17getOverlappedGHTDPcS_fi,@function
_Z17getOverlappedGHTDPcS_fi: # @_Z17getOverlappedGHTDPcS_fi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 36(%rsp) # 4-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl $0, 12(%rsp)
movl $16, %edi
callq malloc
movq %rax, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB10_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r12), %rdi
callq hipStreamCreate
addq $8, %r12
cmpq $8, %r12
je .LBB10_1
# %bb.2:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
xorps %xmm0, %xmm0
movl $16, %ebp
movl $6, %r12d
.p2align 4, 0x90
.LBB10_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, 8(%rsp) # 4-byte Spill
movq 24(%rsp), %rdi
movq (%rbx), %rsi
callq hipEventRecord
movl %ebp, %r13d
shll $20, %r13d
movq (%rbx), %r8
movq %r15, %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
movq (%rbx), %rsi
callq hipEventRecord
leaq (%r14,%r13), %rdi
leaq (%r15,%r13), %rsi
movq 8(%rbx), %r8
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpyAsync
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 12(%rsp), %xmm0
addl %ebp, %ebp
decl %r12d
jne .LBB10_3
# %bb.4: # %.preheader.preheader
movss %xmm0, 8(%rsp) # 4-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB10_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdi
callq hipStreamDestroy
incq %r14
cmpq $1, %r14
je .LBB10_5
# %bb.6:
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI10_0(%rip), %xmm0
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
divss .LCPI10_1(%rip), %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z17getOverlappedGHTDPcS_fi, .Lfunc_end10-_Z17getOverlappedGHTDPcS_fi
.cfi_endproc
# -- End function
.globl _Z20microbenchmarkingPCIiPfS_S_S_S_S_i # -- Begin function _Z20microbenchmarkingPCIiPfS_S_S_S_S_i
.p2align 4, 0x90
.type _Z20microbenchmarkingPCIiPfS_S_S_S_S_i,@function
_Z20microbenchmarkingPCIiPfS_S_S_S_S_i: # @_Z20microbenchmarkingPCIiPfS_S_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r14
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, %r13
movq %rdx, %rbx
movq %rsi, %r12
movl %edi, %ebp
movl 1560(%rsp), %r15d
leaq 24(%rsp), %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl %ebp, %edi
callq hipSetDevice
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
xorl %edx, %edx
callq hipHostMalloc
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
xorl %esi, %esi
callq memset@PLT
movq %rsp, %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq (%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl %r15d, %edx
callq _Z8getLoHTDPcS_i
movss %xmm0, (%r12)
movq (%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z7getGHTDPcS_fi
movss %xmm0, (%r13)
cmpl $2, 624(%rsp)
jne .LBB11_2
# %bb.1:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq _Z17getOverlappedGHTDPcS_fi
movq 16(%rsp), %rax # 8-byte Reload
movss %xmm0, (%rax)
.LBB11_2:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl %r15d, %edx
callq _Z8getLoDTHPcS_i
movss %xmm0, (%rbx)
movq (%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z7getGDTHPcS_fi
movss %xmm0, (%r14)
cmpl $2, 624(%rsp)
jne .LBB11_4
# %bb.3:
movq 1552(%rsp), %r14
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq _Z17getOverlappedGDTHPcS_fi
movss %xmm0, (%r14)
.LBB11_4:
movq 8(%rsp), %rdi
callq hipHostFree
movq (%rsp), %rdi
callq hipFree
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _Z20microbenchmarkingPCIiPfS_S_S_S_S_i, .Lfunc_end11-_Z20microbenchmarkingPCIiPfS_S_S_S_S_i
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define TILE_DIM 1024
template<typename T>
__device__ void sum(const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int index = threadIdx.x;
int length = rows * cols;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
T sum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
T value = matrix[valueIndex];
sum += value;
}
}
tile[index] = sum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
T value = tile[valueIndex];
sum += value;
tile[index] = sum;
}
}
}
if (index == 0) {
result[0] = sum;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define TILE_DIM 1024
template<typename T>
__device__ void sum(const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int index = threadIdx.x;
int length = rows * cols;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
T sum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
T value = matrix[valueIndex];
sum += value;
}
}
tile[index] = sum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
T value = tile[valueIndex];
sum += value;
tile[index] = sum;
}
}
}
if (index == 0) {
result[0] = sum;
}
} | .file "tmpxft_0010f6a9_00000000-6_Sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define TILE_DIM 1024
template<typename T>
__device__ void sum(const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int index = threadIdx.x;
int length = rows * cols;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
T sum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
T value = matrix[valueIndex];
sum += value;
}
}
tile[index] = sum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
T value = tile[valueIndex];
sum += value;
tile[index] = sum;
}
}
}
if (index == 0) {
result[0] = sum;
}
} | #include <hip/hip_runtime.h>
#define TILE_DIM 1024
template<typename T>
__device__ void sum(const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int index = threadIdx.x;
int length = rows * cols;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
T sum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
T value = matrix[valueIndex];
sum += value;
}
}
tile[index] = sum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
T value = tile[valueIndex];
sum += value;
tile[index] = sum;
}
}
}
if (index == 0) {
result[0] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define TILE_DIM 1024
template<typename T>
__device__ void sum(const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int index = threadIdx.x;
int length = rows * cols;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
T sum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
T value = matrix[valueIndex];
sum += value;
}
}
tile[index] = sum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
T value = tile[valueIndex];
sum += value;
tile[index] = sum;
}
}
}
if (index == 0) {
result[0] = sum;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define TILE_DIM 1024
template<typename T>
__device__ void sum(const T* matrix, T* result,
const int rows, const int cols) {
__shared__ T tile[TILE_DIM];
int index = threadIdx.x;
int length = rows * cols;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
T sum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
T value = matrix[valueIndex];
sum += value;
}
}
tile[index] = sum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
T value = tile[valueIndex];
sum += value;
tile[index] = sum;
}
}
}
if (index == 0) {
result[0] = sum;
}
} | .text
.file "Sum.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010f6a9_00000000-6_Sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sum.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void SineKernel(float *A)
{{
// Block index
const uint bx = blockIdx.x;
const uint bw = blockDim.x;
// Thread index
const uint tx = threadIdx.x;
// Stride access locations
const uint aBegin = bw*bx;
const uint idx = aBegin+tx;
// Grab a value from global memory
float this_val = A[idx];
float sinval = sin(this_val);
A[idx] = sinval;
// printf("Sin(%f) = %f\n", this_val, sinval);
}} | code for sm_80
Function : _Z10SineKernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x7f0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0090*/ FMUL R4, R0.reuse, 0.63661974668502807617 ; /* 0x3f22f98300047820 */
/* 0x044fe20000400000 */
/*00a0*/ FSETP.GE.AND P0, PT, |R0|, 105615, PT ; /* 0x47ce47800000780b */
/* 0x000fca0003f06200 */
/*00b0*/ F2I.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e300000203100 */
/*00c0*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x001e240000201400 */
/*00d0*/ FFMA R6, R5, -1.5707962512969970703, R0 ; /* 0xbfc90fda05067823 */
/* 0x001fc80000000000 */
/*00e0*/ FFMA R6, R5, -7.5497894158615963534e-08, R6 ; /* 0xb3a2216805067823 */
/* 0x000fc80000000006 */
/*00f0*/ FFMA R5, R5, -5.3903029534742383927e-15, R6 ; /* 0xa7c234c505057823 */
/* 0x000fe20000000006 */
/*0100*/ @!P0 BRA 0x7e0 ; /* 0x000006d000008947 */
/* 0x000fea0003800000 */
/*0110*/ FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0d200 */
/*0120*/ @!P0 BRA 0x7c0 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*0130*/ SHF.R.U32.HI R4, RZ, 0x17, R0 ; /* 0x00000017ff047819 */
/* 0x000fe20000011600 */
/*0140*/ IMAD.SHL.U32 R6, R0, 0x100, RZ ; /* 0x0000010000067824 */
/* 0x000fe200078e00ff */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0170*/ LOP3.LUT R5, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04057812 */
/* 0x000fe200078ec0ff */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0190*/ LOP3.LUT R9, R6, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000006097812 */
/* 0x000fe200078efcff */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R5, R5, -0x80, RZ ; /* 0xffffff8005057810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01d0*/ SHF.R.U32.HI R12, RZ, 0x5, R5 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011605 */
/*01e0*/ IMAD.U32 R10, RZ, RZ, UR8 ; /* 0x00000008ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*01f0*/ IMAD.U32 R11, RZ, RZ, UR9 ; /* 0x00000009ff0b7e24 */
/* 0x000fca000f8e00ff */
/*0200*/ LDG.E.CONSTANT R6, [R10.64] ; /* 0x000000060a067981 */
/* 0x000ea2000c1e9900 */
/*0210*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0220*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0230*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0240*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0250*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0260*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0270*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0280*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*0290*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02a0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.WIDE.U32 R6, R6, R9, RZ ; /* 0x0000000906067225 */
/* 0x004fca00078e00ff */
/*02c0*/ IADD3 R6, P6, R6, R4, RZ ; /* 0x0000000406067210 */
/* 0x000fc80007fde0ff */
/*02d0*/ IADD3.X R4, R7, UR4, RZ, P6, !PT ; /* 0x0000000407047c10 */
/* 0x000fe2000b7fe4ff */
/*02e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R6.reuse ; /* 0x000000ffff080224 */
/* 0x100fe200078e0006 */
/*02f0*/ ISETP.NE.AND P6, PT, R13, 0x6, PT ; /* 0x000000060d00780c */
/* 0x000fe20003fc5270 */
/*0300*/ @P4 IMAD.MOV.U32 R16, RZ, RZ, R6.reuse ; /* 0x000000ffff104224 */
/* 0x100fe200078e0006 */
/*0310*/ @P5 MOV R15, R6 ; /* 0x00000006000f5202 */
/* 0x000fe20000000f00 */
/*0320*/ @P3 IMAD.MOV.U32 R17, RZ, RZ, R6.reuse ; /* 0x000000ffff113224 */
/* 0x100fe400078e0006 */
/*0330*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R6.reuse ; /* 0x000000ffff122224 */
/* 0x100fe400078e0006 */
/*0340*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e1224 */
/* 0x000fcc00078e0006 */
/*0350*/ @P6 BRA 0x1e0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0360*/ IADD3 R6, -R12, 0x6, RZ ; /* 0x000000060c067810 */
/* 0x000fe20007ffe1ff */
/*0370*/ BSSY B1, 0x6a0 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0380*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*0390*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03a0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03b0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03c0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03d0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03e0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R8.reuse ; /* 0x000000ffff070224 */
/* 0x100fe200078e0008 */
/*03f0*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0400*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff093224 */
/* 0x000fe400078e0008 */
/*0410*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff073224 */
/* 0x000fe200078e000f */
/*0420*/ @P4 MOV R9, R15 ; /* 0x0000000f00094202 */
/* 0x000fe20000000f00 */
/*0430*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R16.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e0010 */
/*0440*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0450*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R16 ; /* 0x000000ffff092224 */
/* 0x000fe200078e0010 */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff072224 */
/* 0x000fc400078e0011 */
/*0480*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff091224 */
/* 0x000fe400078e0011 */
/*0490*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0012 */
/*04a0*/ LOP3.LUT P1, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fe2000782c0ff */
/*04b0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fe400078e000e */
/*04c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff090224 */
/* 0x000fe400078e0012 */
/*04d0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R4.reuse ; /* 0x000000ffff073224 */
/* 0x100fe200078e0004 */
/*04e0*/ @P3 MOV R9, R14 ; /* 0x0000000e00093202 */
/* 0x000fe20000000f00 */
/*04f0*/ @P4 IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff094224 */
/* 0x000fc400078e0004 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0007 */
/*0510*/ @!P1 BRA 0x690 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R12, -R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fca0007ffe1ff */
/*0530*/ IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0c7824 */
/* 0x000fca00078e00ff */
/*0540*/ ISETP.EQ.AND P0, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f02270 */
/*0550*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x4, PT ; /* 0x000000040c00780c */
/* 0x040fe40003f22270 */
/*0560*/ ISETP.EQ.AND P2, PT, R12.reuse, 0x8, PT ; /* 0x000000080c00780c */
/* 0x040fe40003f42270 */
/*0570*/ ISETP.EQ.AND P3, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fce0003f62270 */
/*0580*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0008 */
/*0590*/ ISETP.EQ.AND P0, PT, R12.reuse, 0x10, PT ; /* 0x000000100c00780c */
/* 0x040fe20003f02270 */
/*05a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff071224 */
/* 0x000fe200078e000f */
/*05b0*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x14, PT ; /* 0x000000140c00780c */
/* 0x040fe20003f22270 */
/*05c0*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff072224 */
/* 0x000fe200078e0010 */
/*05d0*/ ISETP.EQ.AND P2, PT, R12, 0x18, PT ; /* 0x000000180c00780c */
/* 0x000fe40003f42270 */
/*05e0*/ @P3 MOV R7, R17 ; /* 0x0000001100073202 */
/* 0x000fe40000000f00 */
/*05f0*/ IADD3 R8, -R6, 0x20, RZ ; /* 0x0000002006087810 */
/* 0x000fca0007ffe1ff */
/*0600*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff070224 */
/* 0x000fe400078e0012 */
/*0610*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff071224 */
/* 0x000fe400078e000e */
/*0620*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff072224 */
/* 0x000fe200078e0004 */
/*0630*/ SHF.L.U32 R4, R5, R6.reuse, RZ ; /* 0x0000000605047219 */
/* 0x080fe400000006ff */
/*0640*/ SHF.L.U32 R6, R9, R6, RZ ; /* 0x0000000609067219 */
/* 0x000fe400000006ff */
/*0650*/ SHF.R.U32.HI R5, RZ, R8.reuse, R9 ; /* 0x00000008ff057219 */
/* 0x080fe40000011609 */
/*0660*/ SHF.R.U32.HI R7, RZ, R8, R7 ; /* 0x00000008ff077219 */
/* 0x000fc60000011607 */
/*0670*/ IMAD.IADD R5, R5, 0x1, R4 ; /* 0x0000000105057824 */
/* 0x000fe400078e0204 */
/*0680*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x000fe400078e0206 */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U32.HI R4, R9.reuse, 0x2, R5 ; /* 0x0000000209047819 */
/* 0x040fe20000010605 */
/*06b0*/ IMAD.SHL.U32 R8, R9, 0x4, RZ ; /* 0x0000000409087824 */
/* 0x000fe200078e00ff */
/*06c0*/ LOP3.LUT P1, R0, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000007812 */
/* 0x000fe4000782c0ff */
/*06d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R4 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011604 */
/*06e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*06f0*/ @P0 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff040212 */
/* 0x000fe400078e33ff */
/*0700*/ @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff080212 */
/* 0x000fe400078e33ff */
/*0710*/ @P0 LOP3.LUT R0, R0, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000000000812 */
/* 0x000fe200078e3cff */
/*0720*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0730*/ LEA.HI R4, R5, R10, RZ, 0x2 ; /* 0x0000000a05047211 */
/* 0x000fe400078f10ff */
/*0740*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0750*/ I2F.F64.S64 R6, R8 ; /* 0x0000000800067312 */
/* 0x000e220000301c00 */
/*0760*/ IADD3 R0, -R4, RZ, RZ ; /* 0x000000ff04007210 */
/* 0x000fca0007ffe1ff */
/*0770*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0000 */
/*0780*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0790*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000301000 */
/*07a0*/ FSEL R5, R6, -R6, !P0 ; /* 0x8000000606057208 */
/* 0x001fe20004000000 */
/*07b0*/ BRA 0x7e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07c0*/ FMUL R5, RZ, R0 ; /* 0x00000000ff057220 */
/* 0x000fe40000400000 */
/*07d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT P1, RZ, R4.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104ff7812 */
/* 0x040fe2000782c0ff */
/*0800*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff077424 */
/* 0x000fe200078e00ff */
/*0810*/ LOP3.LUT P0, RZ, R4, 0x2, RZ, 0xc0, !PT ; /* 0x0000000204ff7812 */
/* 0x000fe2000780c0ff */
/*0820*/ FMUL R9, R5.reuse, R5 ; /* 0x0000000505097220 */
/* 0x040fe20000400000 */
/*0830*/ FSEL R4, R5, 1, !P1 ; /* 0x3f80000005047808 */
/* 0x000fe20004800000 */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff087424 */
/* 0x000fe200078e00ff */
/*0850*/ FSEL R7, R7, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb07077808 */
/* 0x000fe20004800000 */
/*0860*/ IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff007424 */
/* 0x000fc600078e00ff */
/*0870*/ FSEL R5, -R8, -0.4999999701976776123, !P1 ; /* 0xbeffffff08057808 */
/* 0x000fc60004800100 */
/*0880*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff061424 */
/* 0x000fc800078e00ff */
/*0890*/ @P1 FFMA R0, R9, R6, -0.0013887860113754868507 ; /* 0xbab607ed09001423 */
/* 0x000fc80000000006 */
/*08a0*/ FFMA R0, R9.reuse, R0, R7 ; /* 0x0000000009007223 */
/* 0x040fe40000000007 */
/*08b0*/ FFMA R7, R4, R9, RZ ; /* 0x0000000904077223 */
/* 0x000fe400000000ff */
/*08c0*/ FFMA R0, R9, R0, R5 ; /* 0x0000000009007223 */
/* 0x000fc80000000005 */
/*08d0*/ FFMA R7, R0, R7, R4 ; /* 0x0000000700077223 */
/* 0x000fc80000000004 */
/*08e0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fca00000000ff */
/*08f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0900*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x910; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void SineKernel(float *A)
{{
// Block index
const uint bx = blockIdx.x;
const uint bw = blockDim.x;
// Thread index
const uint tx = threadIdx.x;
// Stride access locations
const uint aBegin = bw*bx;
const uint idx = aBegin+tx;
// Grab a value from global memory
float this_val = A[idx];
float sinval = sin(this_val);
A[idx] = sinval;
// printf("Sin(%f) = %f\n", this_val, sinval);
}} | .file "tmpxft_000dde16_00000000-6_sine_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10SineKernelPfPf
.type _Z30__device_stub__Z10SineKernelPfPf, @function
_Z30__device_stub__Z10SineKernelPfPf:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10SineKernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z30__device_stub__Z10SineKernelPfPf, .-_Z30__device_stub__Z10SineKernelPfPf
.globl _Z10SineKernelPf
.type _Z10SineKernelPf, @function
_Z10SineKernelPf:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10SineKernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10SineKernelPf, .-_Z10SineKernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10SineKernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10SineKernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void SineKernel(float *A)
{{
// Block index
const uint bx = blockIdx.x;
const uint bw = blockDim.x;
// Thread index
const uint tx = threadIdx.x;
// Stride access locations
const uint aBegin = bw*bx;
const uint idx = aBegin+tx;
// Grab a value from global memory
float this_val = A[idx];
float sinval = sin(this_val);
A[idx] = sinval;
// printf("Sin(%f) = %f\n", this_val, sinval);
}} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void SineKernel(float *A)
{{
// Block index
const uint bx = blockIdx.x;
const uint bw = blockDim.x;
// Thread index
const uint tx = threadIdx.x;
// Stride access locations
const uint aBegin = bw*bx;
const uint idx = aBegin+tx;
// Grab a value from global memory
float this_val = A[idx];
float sinval = sin(this_val);
A[idx] = sinval;
// printf("Sin(%f) = %f\n", this_val, sinval);
}} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void SineKernel(float *A)
{{
// Block index
const uint bx = blockIdx.x;
const uint bw = blockDim.x;
// Thread index
const uint tx = threadIdx.x;
// Stride access locations
const uint aBegin = bw*bx;
const uint idx = aBegin+tx;
// Grab a value from global memory
float this_val = A[idx];
float sinval = sin(this_val);
A[idx] = sinval;
// printf("Sin(%f) = %f\n", this_val, sinval);
}} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10SineKernelPf
.globl _Z10SineKernelPf
.p2align 8
.type _Z10SineKernelPf,@function
_Z10SineKernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, exec_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v2
v_cmpx_ngt_f32_e64 0x48000000, |v2|
s_xor_b32 s2, exec_lo, s1
s_cbranch_execz .LBB0_2
s_mov_b32 s0, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s0, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s0, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s0
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s0
v_cndmask_b32_e64 v11, v11, v12, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s0
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s0
v_cndmask_b32_e64 v11, v11, v9, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s1
v_cndmask_b32_e64 v6, v6, v10, s1
v_cndmask_b32_e64 v4, v10, v4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_2:
s_and_not1_saveexec_b32 s0, s2
v_mul_f32_e64 v4, 0x3f22f983, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_mov_b32 s0, 0xb94c1982
s_mov_b32 s1, 0x37d75334
v_xor_b32_e32 v3, v3, v2
v_fmaak_f32 v7, s0, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_lshlrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_fmaak_f32 v8, s1, v6, 0xbab64f3b
v_and_b32_e32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v7, v6, v7
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, v4, v7
v_fmaak_f32 v8, v6, v8, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v6, v8, 1.0
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v3, v3, v5, v4
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10SineKernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10SineKernelPf, .Lfunc_end0-_Z10SineKernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10SineKernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10SineKernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void SineKernel(float *A)
{{
// Block index
const uint bx = blockIdx.x;
const uint bw = blockDim.x;
// Thread index
const uint tx = threadIdx.x;
// Stride access locations
const uint aBegin = bw*bx;
const uint idx = aBegin+tx;
// Grab a value from global memory
float this_val = A[idx];
float sinval = sin(this_val);
A[idx] = sinval;
// printf("Sin(%f) = %f\n", this_val, sinval);
}} | .text
.file "sine_kernel.hip"
.globl _Z25__device_stub__SineKernelPf # -- Begin function _Z25__device_stub__SineKernelPf
.p2align 4, 0x90
.type _Z25__device_stub__SineKernelPf,@function
_Z25__device_stub__SineKernelPf: # @_Z25__device_stub__SineKernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10SineKernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__SineKernelPf, .Lfunc_end0-_Z25__device_stub__SineKernelPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10SineKernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10SineKernelPf,@object # @_Z10SineKernelPf
.section .rodata,"a",@progbits
.globl _Z10SineKernelPf
.p2align 3, 0x0
_Z10SineKernelPf:
.quad _Z25__device_stub__SineKernelPf
.size _Z10SineKernelPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10SineKernelPf"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__SineKernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10SineKernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10SineKernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x7f0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0090*/ FMUL R4, R0.reuse, 0.63661974668502807617 ; /* 0x3f22f98300047820 */
/* 0x044fe20000400000 */
/*00a0*/ FSETP.GE.AND P0, PT, |R0|, 105615, PT ; /* 0x47ce47800000780b */
/* 0x000fca0003f06200 */
/*00b0*/ F2I.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e300000203100 */
/*00c0*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x001e240000201400 */
/*00d0*/ FFMA R6, R5, -1.5707962512969970703, R0 ; /* 0xbfc90fda05067823 */
/* 0x001fc80000000000 */
/*00e0*/ FFMA R6, R5, -7.5497894158615963534e-08, R6 ; /* 0xb3a2216805067823 */
/* 0x000fc80000000006 */
/*00f0*/ FFMA R5, R5, -5.3903029534742383927e-15, R6 ; /* 0xa7c234c505057823 */
/* 0x000fe20000000006 */
/*0100*/ @!P0 BRA 0x7e0 ; /* 0x000006d000008947 */
/* 0x000fea0003800000 */
/*0110*/ FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0d200 */
/*0120*/ @!P0 BRA 0x7c0 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*0130*/ SHF.R.U32.HI R4, RZ, 0x17, R0 ; /* 0x00000017ff047819 */
/* 0x000fe20000011600 */
/*0140*/ IMAD.SHL.U32 R6, R0, 0x100, RZ ; /* 0x0000010000067824 */
/* 0x000fe200078e00ff */
/*0150*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0170*/ LOP3.LUT R5, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04057812 */
/* 0x000fe200078ec0ff */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0190*/ LOP3.LUT R9, R6, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000006097812 */
/* 0x000fe200078efcff */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R5, R5, -0x80, RZ ; /* 0xffffff8005057810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01d0*/ SHF.R.U32.HI R12, RZ, 0x5, R5 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011605 */
/*01e0*/ IMAD.U32 R10, RZ, RZ, UR8 ; /* 0x00000008ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*01f0*/ IMAD.U32 R11, RZ, RZ, UR9 ; /* 0x00000009ff0b7e24 */
/* 0x000fca000f8e00ff */
/*0200*/ LDG.E.CONSTANT R6, [R10.64] ; /* 0x000000060a067981 */
/* 0x000ea2000c1e9900 */
/*0210*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0220*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0230*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0240*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0250*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0260*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0270*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0280*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*0290*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02a0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.WIDE.U32 R6, R6, R9, RZ ; /* 0x0000000906067225 */
/* 0x004fca00078e00ff */
/*02c0*/ IADD3 R6, P6, R6, R4, RZ ; /* 0x0000000406067210 */
/* 0x000fc80007fde0ff */
/*02d0*/ IADD3.X R4, R7, UR4, RZ, P6, !PT ; /* 0x0000000407047c10 */
/* 0x000fe2000b7fe4ff */
/*02e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R6.reuse ; /* 0x000000ffff080224 */
/* 0x100fe200078e0006 */
/*02f0*/ ISETP.NE.AND P6, PT, R13, 0x6, PT ; /* 0x000000060d00780c */
/* 0x000fe20003fc5270 */
/*0300*/ @P4 IMAD.MOV.U32 R16, RZ, RZ, R6.reuse ; /* 0x000000ffff104224 */
/* 0x100fe200078e0006 */
/*0310*/ @P5 MOV R15, R6 ; /* 0x00000006000f5202 */
/* 0x000fe20000000f00 */
/*0320*/ @P3 IMAD.MOV.U32 R17, RZ, RZ, R6.reuse ; /* 0x000000ffff113224 */
/* 0x100fe400078e0006 */
/*0330*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R6.reuse ; /* 0x000000ffff122224 */
/* 0x100fe400078e0006 */
/*0340*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e1224 */
/* 0x000fcc00078e0006 */
/*0350*/ @P6 BRA 0x1e0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0360*/ IADD3 R6, -R12, 0x6, RZ ; /* 0x000000060c067810 */
/* 0x000fe20007ffe1ff */
/*0370*/ BSSY B1, 0x6a0 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0380*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*0390*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03a0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03b0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03c0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03d0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03e0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R8.reuse ; /* 0x000000ffff070224 */
/* 0x100fe200078e0008 */
/*03f0*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0400*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff093224 */
/* 0x000fe400078e0008 */
/*0410*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff073224 */
/* 0x000fe200078e000f */
/*0420*/ @P4 MOV R9, R15 ; /* 0x0000000f00094202 */
/* 0x000fe20000000f00 */
/*0430*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R16.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e0010 */
/*0440*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0450*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R16 ; /* 0x000000ffff092224 */
/* 0x000fe200078e0010 */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff072224 */
/* 0x000fc400078e0011 */
/*0480*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff091224 */
/* 0x000fe400078e0011 */
/*0490*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0012 */
/*04a0*/ LOP3.LUT P1, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fe2000782c0ff */
/*04b0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fe400078e000e */
/*04c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff090224 */
/* 0x000fe400078e0012 */
/*04d0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R4.reuse ; /* 0x000000ffff073224 */
/* 0x100fe200078e0004 */
/*04e0*/ @P3 MOV R9, R14 ; /* 0x0000000e00093202 */
/* 0x000fe20000000f00 */
/*04f0*/ @P4 IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff094224 */
/* 0x000fc400078e0004 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0007 */
/*0510*/ @!P1 BRA 0x690 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R12, -R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fca0007ffe1ff */
/*0530*/ IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0c7824 */
/* 0x000fca00078e00ff */
/*0540*/ ISETP.EQ.AND P0, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f02270 */
/*0550*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x4, PT ; /* 0x000000040c00780c */
/* 0x040fe40003f22270 */
/*0560*/ ISETP.EQ.AND P2, PT, R12.reuse, 0x8, PT ; /* 0x000000080c00780c */
/* 0x040fe40003f42270 */
/*0570*/ ISETP.EQ.AND P3, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fce0003f62270 */
/*0580*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0008 */
/*0590*/ ISETP.EQ.AND P0, PT, R12.reuse, 0x10, PT ; /* 0x000000100c00780c */
/* 0x040fe20003f02270 */
/*05a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff071224 */
/* 0x000fe200078e000f */
/*05b0*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x14, PT ; /* 0x000000140c00780c */
/* 0x040fe20003f22270 */
/*05c0*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff072224 */
/* 0x000fe200078e0010 */
/*05d0*/ ISETP.EQ.AND P2, PT, R12, 0x18, PT ; /* 0x000000180c00780c */
/* 0x000fe40003f42270 */
/*05e0*/ @P3 MOV R7, R17 ; /* 0x0000001100073202 */
/* 0x000fe40000000f00 */
/*05f0*/ IADD3 R8, -R6, 0x20, RZ ; /* 0x0000002006087810 */
/* 0x000fca0007ffe1ff */
/*0600*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff070224 */
/* 0x000fe400078e0012 */
/*0610*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff071224 */
/* 0x000fe400078e000e */
/*0620*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff072224 */
/* 0x000fe200078e0004 */
/*0630*/ SHF.L.U32 R4, R5, R6.reuse, RZ ; /* 0x0000000605047219 */
/* 0x080fe400000006ff */
/*0640*/ SHF.L.U32 R6, R9, R6, RZ ; /* 0x0000000609067219 */
/* 0x000fe400000006ff */
/*0650*/ SHF.R.U32.HI R5, RZ, R8.reuse, R9 ; /* 0x00000008ff057219 */
/* 0x080fe40000011609 */
/*0660*/ SHF.R.U32.HI R7, RZ, R8, R7 ; /* 0x00000008ff077219 */
/* 0x000fc60000011607 */
/*0670*/ IMAD.IADD R5, R5, 0x1, R4 ; /* 0x0000000105057824 */
/* 0x000fe400078e0204 */
/*0680*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x000fe400078e0206 */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U32.HI R4, R9.reuse, 0x2, R5 ; /* 0x0000000209047819 */
/* 0x040fe20000010605 */
/*06b0*/ IMAD.SHL.U32 R8, R9, 0x4, RZ ; /* 0x0000000409087824 */
/* 0x000fe200078e00ff */
/*06c0*/ LOP3.LUT P1, R0, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000007812 */
/* 0x000fe4000782c0ff */
/*06d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R4 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011604 */
/*06e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*06f0*/ @P0 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff040212 */
/* 0x000fe400078e33ff */
/*0700*/ @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff080212 */
/* 0x000fe400078e33ff */
/*0710*/ @P0 LOP3.LUT R0, R0, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000000000812 */
/* 0x000fe200078e3cff */
/*0720*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0730*/ LEA.HI R4, R5, R10, RZ, 0x2 ; /* 0x0000000a05047211 */
/* 0x000fe400078f10ff */
/*0740*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0750*/ I2F.F64.S64 R6, R8 ; /* 0x0000000800067312 */
/* 0x000e220000301c00 */
/*0760*/ IADD3 R0, -R4, RZ, RZ ; /* 0x000000ff04007210 */
/* 0x000fca0007ffe1ff */
/*0770*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0000 */
/*0780*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0790*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000301000 */
/*07a0*/ FSEL R5, R6, -R6, !P0 ; /* 0x8000000606057208 */
/* 0x001fe20004000000 */
/*07b0*/ BRA 0x7e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07c0*/ FMUL R5, RZ, R0 ; /* 0x00000000ff057220 */
/* 0x000fe40000400000 */
/*07d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT P1, RZ, R4.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104ff7812 */
/* 0x040fe2000782c0ff */
/*0800*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff077424 */
/* 0x000fe200078e00ff */
/*0810*/ LOP3.LUT P0, RZ, R4, 0x2, RZ, 0xc0, !PT ; /* 0x0000000204ff7812 */
/* 0x000fe2000780c0ff */
/*0820*/ FMUL R9, R5.reuse, R5 ; /* 0x0000000505097220 */
/* 0x040fe20000400000 */
/*0830*/ FSEL R4, R5, 1, !P1 ; /* 0x3f80000005047808 */
/* 0x000fe20004800000 */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff087424 */
/* 0x000fe200078e00ff */
/*0850*/ FSEL R7, R7, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb07077808 */
/* 0x000fe20004800000 */
/*0860*/ IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff007424 */
/* 0x000fc600078e00ff */
/*0870*/ FSEL R5, -R8, -0.4999999701976776123, !P1 ; /* 0xbeffffff08057808 */
/* 0x000fc60004800100 */
/*0880*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff061424 */
/* 0x000fc800078e00ff */
/*0890*/ @P1 FFMA R0, R9, R6, -0.0013887860113754868507 ; /* 0xbab607ed09001423 */
/* 0x000fc80000000006 */
/*08a0*/ FFMA R0, R9.reuse, R0, R7 ; /* 0x0000000009007223 */
/* 0x040fe40000000007 */
/*08b0*/ FFMA R7, R4, R9, RZ ; /* 0x0000000904077223 */
/* 0x000fe400000000ff */
/*08c0*/ FFMA R0, R9, R0, R5 ; /* 0x0000000009007223 */
/* 0x000fc80000000005 */
/*08d0*/ FFMA R7, R0, R7, R4 ; /* 0x0000000700077223 */
/* 0x000fc80000000004 */
/*08e0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fca00000000ff */
/*08f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0900*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0910*/ BRA 0x910; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10SineKernelPf
.globl _Z10SineKernelPf
.p2align 8
.type _Z10SineKernelPf,@function
_Z10SineKernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, exec_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v2
v_cmpx_ngt_f32_e64 0x48000000, |v2|
s_xor_b32 s2, exec_lo, s1
s_cbranch_execz .LBB0_2
s_mov_b32 s0, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s0, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s0, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s0
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s0
v_cndmask_b32_e64 v11, v11, v12, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s0
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s0
v_cndmask_b32_e64 v11, v11, v9, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s1
v_cndmask_b32_e64 v6, v6, v10, s1
v_cndmask_b32_e64 v4, v10, v4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_2:
s_and_not1_saveexec_b32 s0, s2
v_mul_f32_e64 v4, 0x3f22f983, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_mov_b32 s0, 0xb94c1982
s_mov_b32 s1, 0x37d75334
v_xor_b32_e32 v3, v3, v2
v_fmaak_f32 v7, s0, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_lshlrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_fmaak_f32 v8, s1, v6, 0xbab64f3b
v_and_b32_e32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v7, v6, v7
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, v4, v7
v_fmaak_f32 v8, v6, v8, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v6, v8, 1.0
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v3, v3, v5, v4
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10SineKernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10SineKernelPf, .Lfunc_end0-_Z10SineKernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10SineKernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10SineKernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dde16_00000000-6_sine_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10SineKernelPfPf
.type _Z30__device_stub__Z10SineKernelPfPf, @function
_Z30__device_stub__Z10SineKernelPfPf:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10SineKernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z30__device_stub__Z10SineKernelPfPf, .-_Z30__device_stub__Z10SineKernelPfPf
.globl _Z10SineKernelPf
.type _Z10SineKernelPf, @function
_Z10SineKernelPf:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10SineKernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10SineKernelPf, .-_Z10SineKernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10SineKernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10SineKernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sine_kernel.hip"
.globl _Z25__device_stub__SineKernelPf # -- Begin function _Z25__device_stub__SineKernelPf
.p2align 4, 0x90
.type _Z25__device_stub__SineKernelPf,@function
_Z25__device_stub__SineKernelPf: # @_Z25__device_stub__SineKernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10SineKernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__SineKernelPf, .Lfunc_end0-_Z25__device_stub__SineKernelPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10SineKernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10SineKernelPf,@object # @_Z10SineKernelPf
.section .rodata,"a",@progbits
.globl _Z10SineKernelPf
.p2align 3, 0x0
_Z10SineKernelPf:
.quad _Z25__device_stub__SineKernelPf
.size _Z10SineKernelPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10SineKernelPf"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__SineKernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10SineKernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <chrono>
int main() {
int N = 2518;
thrust::host_vector<double> host(N);
double tmp;
for(int i = 0; i < N; i++){
std::cin >> tmp;
host[i] = tmp;
}
/* na linha abaixo os dados são copiados
para GPU */
auto start_time = std::chrono::high_resolution_clock::now();
thrust::device_vector<double> dev(host);
auto end_time = std::chrono::high_resolution_clock::now();
auto runtime = std::chrono::duration_cast<std::chrono::milliseconds>(end_time - start_time);
std::cerr << "Alocação e cópia para GPU: " << runtime.count() << "ms\n";
double mediaAnual = thrust::reduce(dev.end() -365, dev.end(), 0.0, thrust::plus<double>()) /N;
std::cout << "Media Anual: " << mediaAnual << "\n";
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <chrono>
int main() {
int N = 2518;
thrust::host_vector<double> host(N);
double tmp;
for(int i = 0; i < N; i++){
std::cin >> tmp;
host[i] = tmp;
}
/* na linha abaixo os dados são copiados
para GPU */
auto start_time = std::chrono::high_resolution_clock::now();
thrust::device_vector<double> dev(host);
auto end_time = std::chrono::high_resolution_clock::now();
auto runtime = std::chrono::duration_cast<std::chrono::milliseconds>(end_time - start_time);
std::cerr << "Alocação e cópia para GPU: " << runtime.count() << "ms\n";
double mediaAnual = thrust::reduce(dev.end() -365, dev.end(), 0.0, thrust::plus<double>()) /N;
std::cout << "Media Anual: " << mediaAnual << "\n";
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void mergePartialHistogramsKernel(uint *d_Histogram, uint *d_PartialHistograms, uint histogramCount, uint binCount)
{
for (uint bin = blockIdx.x; bin < binCount; bin += gridDim.x)
{
uint sum = 0;
for (uint histogramIndex = threadIdx.x; histogramIndex < histogramCount; histogramIndex += MERGE_THREADBLOCK_SIZE)
{
sum += d_PartialHistograms[bin + histogramIndex * binCount];
}
__shared__ uint data[MERGE_THREADBLOCK_SIZE];
data[threadIdx.x] = sum;
for (uint stride = MERGE_THREADBLOCK_SIZE / 2; stride > 0; stride >>= 1)
{
__syncthreads();
if (threadIdx.x < stride)
{
data[threadIdx.x] += data[threadIdx.x + stride];
}
}
if (threadIdx.x == 0)
{
d_Histogram[bin] = data[0];
}
}
} | code for sm_80
Function : _Z28mergePartialHistogramsKernelPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fe20003f06070 */
/*0070*/ BSSY B0, 0x4a0 ; /* 0x0000042000007945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd600078e00ff */
/*0090*/ @P0 BRA 0x490 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe20003f26070 */
/*00b0*/ IMAD R4, R0, c[0x0][0x174], R3 ; /* 0x00005d0000047a24 */
/* 0x000fd800078e0203 */
/*00c0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff071424 */
/* 0x000fc800078e00ff */
/*00d0*/ @P1 IMAD.WIDE.U32 R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004061625 */
/* 0x000fcc00078e0007 */
/*00e0*/ @P1 LDG.E R6, [R6.64] ; /* 0x0000000406061981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fe20000000f00 */
/*0100*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, 0x80 ; /* 0x00000080ff091424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B1, 0x320 ; /* 0x0000020000017945 */
/* 0x000fe40003800000 */
/*0120*/ @P1 IADD3 R2, R2, 0x80, RZ ; /* 0x0000008002021810 */
/* 0x000fe20007ffe0ff */
/*0130*/ @P1 IMAD R4, R9, c[0x0][0x174], R4 ; /* 0x00005d0009041a24 */
/* 0x000fc600078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe40003f06070 */
/*0150*/ IADD3 R5, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a10 */
/* 0x000fc80007ffe1ff */
/*0160*/ ISETP.LE.U32.OR P0, PT, R5, 0x180, P0 ; /* 0x000001800500780c */
/* 0x000fe20000703470 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*0180*/ @P1 IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105051824 */
/* 0x004fe200078e0206 */
/*0190*/ PLOP3.LUT P1, PT, P1, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fce0000f2e170 */
/*01a0*/ @P0 BRA 0x310 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*01b0*/ MOV R15, c[0x0][0x170] ; /* 0x00005c00000f7a02 */
/* 0x000fe40000000f00 */
/*01c0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2e170 */
/*01d0*/ IADD3 R15, R15, -0x180, RZ ; /* 0xfffffe800f0f7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x80 ; /* 0x00000080ff117424 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD R8, R17, c[0x0][0x174], R4 ; /* 0x00005d0011087a24 */
/* 0x000fe400078e0204 */
/*0210*/ IMAD.WIDE.U32 R6, R4, R13, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e000d */
/*0220*/ IMAD R10, R17.reuse, c[0x0][0x174], R8 ; /* 0x00005d00110a7a24 */
/* 0x040fe400078e0208 */
/*0230*/ IMAD.WIDE.U32 R8, R8, R13.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe200078e000d */
/*0240*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea6000c1e1900 */
/*0250*/ IMAD R4, R17, c[0x0][0x174], R10 ; /* 0x00005d0011047a24 */
/* 0x000fe400078e020a */
/*0260*/ IMAD.WIDE.U32 R10, R10, R13.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe200078e000d */
/*0270*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea6000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fc400078e000d */
/*0290*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*02b0*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fe20003f06070 */
/*02d0*/ IMAD R4, R17, c[0x0][0x174], R4 ; /* 0x00005d0011047a24 */
/* 0x000fe200078e0204 */
/*02e0*/ IADD3 R5, R8, R6, R5 ; /* 0x0000000608057210 */
/* 0x004fc80007ffe005 */
/*02f0*/ IADD3 R5, R12, R10, R5 ; /* 0x0000000a0c057210 */
/* 0x008fce0007ffe005 */
/*0300*/ @!P0 BRA 0x1e0 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe20003f06070 */
/*0330*/ BSSY B1, 0x430 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R6, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc80007ffe1ff */
/*0350*/ ISETP.LE.U32.OR P0, PT, R6, 0x80, P0 ; /* 0x000000800600780c */
/* 0x000fda0000703470 */
/*0360*/ @P0 BRA 0x420 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0370*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0380*/ IMAD.MOV.U32 R11, RZ, RZ, 0x80 ; /* 0x00000080ff0b7424 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD R10, R11, c[0x0][0x174], R4 ; /* 0x00005d000b0a7a24 */
/* 0x000fca00078e0204 */
/*03a0*/ IMAD.WIDE.U32 R8, R4, R7, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0007 */
/*03b0*/ IMAD.WIDE.U32 R6, R10, R7, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x000fe400078e0007 */
/*03c0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*03f0*/ IMAD R4, R11, c[0x0][0x174], R10 ; /* 0x00005d000b047a24 */
/* 0x000fe200078e020a */
/*0400*/ IADD3 R2, R2, 0x100, RZ ; /* 0x0000010002027810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R5, R6, R8, R5 ; /* 0x0000000806057210 */
/* 0x004fc80007ffe005 */
/*0420*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.LT.U32.OR P1, PT, R2, c[0x0][0x170], P1 ; /* 0x00005c0002007a0c */
/* 0x000fda0000f21470 */
/*0440*/ @!P1 BRA 0x490 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0460*/ IMAD.WIDE.U32 R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fcc00078e0007 */
/*0470*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105057824 */
/* 0x004fe400078e0206 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x000fe80000004800 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ ISETP.GT.U32.AND P1, PT, R0.reuse, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x040fe40003f24070 */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x000fd60003f04070 */
/*04e0*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*04f0*/ @!P1 LDS R7, [R0.X4+0x100] ; /* 0x0001000000079984 */
/* 0x000e240000004800 */
/*0500*/ @!P1 IADD3 R7, R2, R7, RZ ; /* 0x0000000702079210 */
/* 0x001fca0007ffe0ff */
/*0510*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x000fe80000004800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0530*/ ISETP.GT.U32.AND P1, PT, R0, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x000fca0003f24070 */
/*0540*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0550*/ @!P0 LDS R9, [R0.X4+0x80] ; /* 0x0000800000098984 */
/* 0x000e240000004800 */
/*0560*/ @!P0 IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102098824 */
/* 0x001fca00078e0209 */
/*0570*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x000fe80000004800 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0590*/ ISETP.GT.U32.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fca0003f04070 */
/*05a0*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*05b0*/ @!P1 LDS R5, [R0.X4+0x40] ; /* 0x0000400000059984 */
/* 0x000e240000004800 */
/*05c0*/ @!P1 IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102059824 */
/* 0x001fca00078e0205 */
/*05d0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ ISETP.GT.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fca0003f24070 */
/*0600*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0610*/ @!P0 LDS R7, [R0.X4+0x20] ; /* 0x0000200000078984 */
/* 0x000e240000004800 */
/*0620*/ @!P0 IADD3 R7, R2, R7, RZ ; /* 0x0000000702078210 */
/* 0x001fca0007ffe0ff */
/*0630*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0650*/ ISETP.GT.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fca0003f04070 */
/*0660*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*0670*/ @!P1 LDS R9, [R0.X4+0x10] ; /* 0x0000100000099984 */
/* 0x000e240000004800 */
/*0680*/ @!P1 IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102099824 */
/* 0x001fca00078e0209 */
/*0690*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x000fe80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*06c0*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff049424 */
/* 0x000fe200078e00ff */
/*06d0*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*06e0*/ @!P0 LDS R5, [R0.X4+0x8] ; /* 0x0000080000058984 */
/* 0x000e240000004800 */
/*06f0*/ @!P0 IMAD.IADD R7, R2, 0x1, R5 ; /* 0x0000000102078824 */
/* 0x001fca00078e0205 */
/*0700*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @!P1 LDS R2, [0x4] ; /* 0x00000400ff029984 */
/* 0x000fe80000000800 */
/*0730*/ @!P1 LDS R5, [R0.X4] ; /* 0x0000000000059984 */
/* 0x000e240000004800 */
/*0740*/ @!P1 IADD3 R11, R2, R5, RZ ; /* 0x00000005020b9210 */
/* 0x001fe20007ffe0ff */
/*0750*/ @!P1 IMAD.WIDE.U32 R4, R3.reuse, R4, c[0x0][0x160] ; /* 0x0000580003049625 */
/* 0x040fe200078e0004 */
/*0760*/ IADD3 R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a10 */
/* 0x000fc60007ffe0ff */
/*0770*/ @!P1 STS [R0.X4], R11 ; /* 0x0000000b00009388 */
/* 0x000fe20000004800 */
/*0780*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fc60003f06070 */
/*0790*/ @!P1 LDS R9, [RZ] ; /* 0x00000000ff099984 */
/* 0x000e280000000800 */
/*07a0*/ @!P1 STG.E [R4.64], R9 ; /* 0x0000000904009986 */
/* 0x0011ec000c101904 */
/*07b0*/ @!P0 BRA 0x60 ; /* 0xfffff8a000008947 */
/* 0x000fea000383ffff */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void mergePartialHistogramsKernel(uint *d_Histogram, uint *d_PartialHistograms, uint histogramCount, uint binCount)
{
for (uint bin = blockIdx.x; bin < binCount; bin += gridDim.x)
{
uint sum = 0;
for (uint histogramIndex = threadIdx.x; histogramIndex < histogramCount; histogramIndex += MERGE_THREADBLOCK_SIZE)
{
sum += d_PartialHistograms[bin + histogramIndex * binCount];
}
__shared__ uint data[MERGE_THREADBLOCK_SIZE];
data[threadIdx.x] = sum;
for (uint stride = MERGE_THREADBLOCK_SIZE / 2; stride > 0; stride >>= 1)
{
__syncthreads();
if (threadIdx.x < stride)
{
data[threadIdx.x] += data[threadIdx.x + stride];
}
}
if (threadIdx.x == 0)
{
d_Histogram[bin] = data[0];
}
}
} | .file "tmpxft_00096cea_00000000-6_mergePartialHistogramsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj
.type _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj, @function
_Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28mergePartialHistogramsKernelPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj, .-_Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj
.globl _Z28mergePartialHistogramsKernelPjS_jj
.type _Z28mergePartialHistogramsKernelPjS_jj, @function
_Z28mergePartialHistogramsKernelPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28mergePartialHistogramsKernelPjS_jj, .-_Z28mergePartialHistogramsKernelPjS_jj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28mergePartialHistogramsKernelPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28mergePartialHistogramsKernelPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void mergePartialHistogramsKernel(uint *d_Histogram, uint *d_PartialHistograms, uint histogramCount, uint binCount)
{
for (uint bin = blockIdx.x; bin < binCount; bin += gridDim.x)
{
uint sum = 0;
for (uint histogramIndex = threadIdx.x; histogramIndex < histogramCount; histogramIndex += MERGE_THREADBLOCK_SIZE)
{
sum += d_PartialHistograms[bin + histogramIndex * binCount];
}
__shared__ uint data[MERGE_THREADBLOCK_SIZE];
data[threadIdx.x] = sum;
for (uint stride = MERGE_THREADBLOCK_SIZE / 2; stride > 0; stride >>= 1)
{
__syncthreads();
if (threadIdx.x < stride)
{
data[threadIdx.x] += data[threadIdx.x + stride];
}
}
if (threadIdx.x == 0)
{
d_Histogram[bin] = data[0];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void mergePartialHistogramsKernel(uint *d_Histogram, uint *d_PartialHistograms, uint histogramCount, uint binCount)
{
for (uint bin = blockIdx.x; bin < binCount; bin += gridDim.x)
{
uint sum = 0;
for (uint histogramIndex = threadIdx.x; histogramIndex < histogramCount; histogramIndex += MERGE_THREADBLOCK_SIZE)
{
sum += d_PartialHistograms[bin + histogramIndex * binCount];
}
__shared__ uint data[MERGE_THREADBLOCK_SIZE];
data[threadIdx.x] = sum;
for (uint stride = MERGE_THREADBLOCK_SIZE / 2; stride > 0; stride >>= 1)
{
__syncthreads();
if (threadIdx.x < stride)
{
data[threadIdx.x] += data[threadIdx.x + stride];
}
}
if (threadIdx.x == 0)
{
d_Histogram[bin] = data[0];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void mergePartialHistogramsKernel(uint *d_Histogram, uint *d_PartialHistograms, uint histogramCount, uint binCount)
{
for (uint bin = blockIdx.x; bin < binCount; bin += gridDim.x)
{
uint sum = 0;
for (uint histogramIndex = threadIdx.x; histogramIndex < histogramCount; histogramIndex += MERGE_THREADBLOCK_SIZE)
{
sum += d_PartialHistograms[bin + histogramIndex * binCount];
}
__shared__ uint data[MERGE_THREADBLOCK_SIZE];
data[threadIdx.x] = sum;
for (uint stride = MERGE_THREADBLOCK_SIZE / 2; stride > 0; stride >>= 1)
{
__syncthreads();
if (threadIdx.x < stride)
{
data[threadIdx.x] += data[threadIdx.x + stride];
}
}
if (threadIdx.x == 0)
{
d_Histogram[bin] = data[0];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28mergePartialHistogramsKernelPjS_jj
.globl _Z28mergePartialHistogramsKernelPjS_jj
.p2align 8
.type _Z28mergePartialHistogramsKernelPjS_jj,@function
_Z28mergePartialHistogramsKernelPjS_jj:
s_load_b32 s8, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s8
s_cbranch_scc1 .LBB0_13
s_clause 0x2
s_load_b32 s9, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x18
s_mov_b32 s2, s15
s_mov_b32 s3, 0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v4, 2, v0
v_mad_u64_u32 v[1:2], null, v0, s8, s[2:3]
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_lshl_b32 s11, s8, 7
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e64 s0, s9, v0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s10, v1
s_add_i32 s2, s10, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_13
.LBB0_3:
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, v1
v_mov_b32_e32 v6, v0
s_mov_b32 s13, 0
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v6, 0x80, v6
v_add_nc_u32_e32 v2, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s1, s6, v7
v_add_co_ci_u32_e64 v8, s1, s7, v8, s1
s_delay_alu instid0(VALU_DEP_4)
v_cmp_le_u32_e64 s1, s9, v6
global_load_b32 v7, v[7:8], off
s_or_b32 s13, s1, s13
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v7, v5
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s13
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s12
s_mov_b32 s12, 64
ds_store_b32 v4, v5
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
s_lshr_b32 s1, s12, 1
s_cmp_lt_u32 s12, 2
s_mov_b32 s12, s1
s_cbranch_scc1 .LBB0_11
.LBB0_9:
s_mov_b32 s13, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s12, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
ds_store_b32 v4, v2
s_branch .LBB0_8
.LBB0_11:
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
ds_load_b32 v2, v3
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v2, s[12:13]
s_branch .LBB0_2
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28mergePartialHistogramsKernelPjS_jj
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28mergePartialHistogramsKernelPjS_jj, .Lfunc_end0-_Z28mergePartialHistogramsKernelPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28mergePartialHistogramsKernelPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28mergePartialHistogramsKernelPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define UMUL(a, b) ( (a) * (b) )
#define UMAD(a, b, c) ( UMUL((a), (b)) + (c) )
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#define SHARED_MEMORY_SIZE 49152
#define MERGE_THREADBLOCK_SIZE 128
static uint *d_PartialHistograms;
/*
* Function that maps value to bin in range 0 inclusive to binCOunt exclusive
*/
__global__ void mergePartialHistogramsKernel(uint *d_Histogram, uint *d_PartialHistograms, uint histogramCount, uint binCount)
{
for (uint bin = blockIdx.x; bin < binCount; bin += gridDim.x)
{
uint sum = 0;
for (uint histogramIndex = threadIdx.x; histogramIndex < histogramCount; histogramIndex += MERGE_THREADBLOCK_SIZE)
{
sum += d_PartialHistograms[bin + histogramIndex * binCount];
}
__shared__ uint data[MERGE_THREADBLOCK_SIZE];
data[threadIdx.x] = sum;
for (uint stride = MERGE_THREADBLOCK_SIZE / 2; stride > 0; stride >>= 1)
{
__syncthreads();
if (threadIdx.x < stride)
{
data[threadIdx.x] += data[threadIdx.x + stride];
}
}
if (threadIdx.x == 0)
{
d_Histogram[bin] = data[0];
}
}
} | .text
.file "mergePartialHistogramsKernel.hip"
.globl _Z43__device_stub__mergePartialHistogramsKernelPjS_jj # -- Begin function _Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.p2align 4, 0x90
.type _Z43__device_stub__mergePartialHistogramsKernelPjS_jj,@function
_Z43__device_stub__mergePartialHistogramsKernelPjS_jj: # @_Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28mergePartialHistogramsKernelPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z43__device_stub__mergePartialHistogramsKernelPjS_jj, .Lfunc_end0-_Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28mergePartialHistogramsKernelPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28mergePartialHistogramsKernelPjS_jj,@object # @_Z28mergePartialHistogramsKernelPjS_jj
.section .rodata,"a",@progbits
.globl _Z28mergePartialHistogramsKernelPjS_jj
.p2align 3, 0x0
_Z28mergePartialHistogramsKernelPjS_jj:
.quad _Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.size _Z28mergePartialHistogramsKernelPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28mergePartialHistogramsKernelPjS_jj"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28mergePartialHistogramsKernelPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28mergePartialHistogramsKernelPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fe20003f06070 */
/*0070*/ BSSY B0, 0x4a0 ; /* 0x0000042000007945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd600078e00ff */
/*0090*/ @P0 BRA 0x490 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe20003f26070 */
/*00b0*/ IMAD R4, R0, c[0x0][0x174], R3 ; /* 0x00005d0000047a24 */
/* 0x000fd800078e0203 */
/*00c0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff071424 */
/* 0x000fc800078e00ff */
/*00d0*/ @P1 IMAD.WIDE.U32 R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004061625 */
/* 0x000fcc00078e0007 */
/*00e0*/ @P1 LDG.E R6, [R6.64] ; /* 0x0000000406061981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fe20000000f00 */
/*0100*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, 0x80 ; /* 0x00000080ff091424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B1, 0x320 ; /* 0x0000020000017945 */
/* 0x000fe40003800000 */
/*0120*/ @P1 IADD3 R2, R2, 0x80, RZ ; /* 0x0000008002021810 */
/* 0x000fe20007ffe0ff */
/*0130*/ @P1 IMAD R4, R9, c[0x0][0x174], R4 ; /* 0x00005d0009041a24 */
/* 0x000fc600078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe40003f06070 */
/*0150*/ IADD3 R5, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a10 */
/* 0x000fc80007ffe1ff */
/*0160*/ ISETP.LE.U32.OR P0, PT, R5, 0x180, P0 ; /* 0x000001800500780c */
/* 0x000fe20000703470 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*0180*/ @P1 IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105051824 */
/* 0x004fe200078e0206 */
/*0190*/ PLOP3.LUT P1, PT, P1, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fce0000f2e170 */
/*01a0*/ @P0 BRA 0x310 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*01b0*/ MOV R15, c[0x0][0x170] ; /* 0x00005c00000f7a02 */
/* 0x000fe40000000f00 */
/*01c0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2e170 */
/*01d0*/ IADD3 R15, R15, -0x180, RZ ; /* 0xfffffe800f0f7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x80 ; /* 0x00000080ff117424 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD R8, R17, c[0x0][0x174], R4 ; /* 0x00005d0011087a24 */
/* 0x000fe400078e0204 */
/*0210*/ IMAD.WIDE.U32 R6, R4, R13, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e000d */
/*0220*/ IMAD R10, R17.reuse, c[0x0][0x174], R8 ; /* 0x00005d00110a7a24 */
/* 0x040fe400078e0208 */
/*0230*/ IMAD.WIDE.U32 R8, R8, R13.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe200078e000d */
/*0240*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea6000c1e1900 */
/*0250*/ IMAD R4, R17, c[0x0][0x174], R10 ; /* 0x00005d0011047a24 */
/* 0x000fe400078e020a */
/*0260*/ IMAD.WIDE.U32 R10, R10, R13.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe200078e000d */
/*0270*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea6000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R12, R4, R13, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fc400078e000d */
/*0290*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*02b0*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fe20003f06070 */
/*02d0*/ IMAD R4, R17, c[0x0][0x174], R4 ; /* 0x00005d0011047a24 */
/* 0x000fe200078e0204 */
/*02e0*/ IADD3 R5, R8, R6, R5 ; /* 0x0000000608057210 */
/* 0x004fc80007ffe005 */
/*02f0*/ IADD3 R5, R12, R10, R5 ; /* 0x0000000a0c057210 */
/* 0x008fce0007ffe005 */
/*0300*/ @!P0 BRA 0x1e0 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe20003f06070 */
/*0330*/ BSSY B1, 0x430 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R6, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc80007ffe1ff */
/*0350*/ ISETP.LE.U32.OR P0, PT, R6, 0x80, P0 ; /* 0x000000800600780c */
/* 0x000fda0000703470 */
/*0360*/ @P0 BRA 0x420 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0370*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0380*/ IMAD.MOV.U32 R11, RZ, RZ, 0x80 ; /* 0x00000080ff0b7424 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD R10, R11, c[0x0][0x174], R4 ; /* 0x00005d000b0a7a24 */
/* 0x000fca00078e0204 */
/*03a0*/ IMAD.WIDE.U32 R8, R4, R7, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0007 */
/*03b0*/ IMAD.WIDE.U32 R6, R10, R7, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x000fe400078e0007 */
/*03c0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*03f0*/ IMAD R4, R11, c[0x0][0x174], R10 ; /* 0x00005d000b047a24 */
/* 0x000fe200078e020a */
/*0400*/ IADD3 R2, R2, 0x100, RZ ; /* 0x0000010002027810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R5, R6, R8, R5 ; /* 0x0000000806057210 */
/* 0x004fc80007ffe005 */
/*0420*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.LT.U32.OR P1, PT, R2, c[0x0][0x170], P1 ; /* 0x00005c0002007a0c */
/* 0x000fda0000f21470 */
/*0440*/ @!P1 BRA 0x490 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0460*/ IMAD.WIDE.U32 R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fcc00078e0007 */
/*0470*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105057824 */
/* 0x004fe400078e0206 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x000fe80000004800 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ ISETP.GT.U32.AND P1, PT, R0.reuse, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x040fe40003f24070 */
/*04d0*/ ISETP.GT.U32.AND P0, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x000fd60003f04070 */
/*04e0*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*04f0*/ @!P1 LDS R7, [R0.X4+0x100] ; /* 0x0001000000079984 */
/* 0x000e240000004800 */
/*0500*/ @!P1 IADD3 R7, R2, R7, RZ ; /* 0x0000000702079210 */
/* 0x001fca0007ffe0ff */
/*0510*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x000fe80000004800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0530*/ ISETP.GT.U32.AND P1, PT, R0, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x000fca0003f24070 */
/*0540*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0550*/ @!P0 LDS R9, [R0.X4+0x80] ; /* 0x0000800000098984 */
/* 0x000e240000004800 */
/*0560*/ @!P0 IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102098824 */
/* 0x001fca00078e0209 */
/*0570*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x000fe80000004800 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0590*/ ISETP.GT.U32.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fca0003f04070 */
/*05a0*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*05b0*/ @!P1 LDS R5, [R0.X4+0x40] ; /* 0x0000400000059984 */
/* 0x000e240000004800 */
/*05c0*/ @!P1 IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102059824 */
/* 0x001fca00078e0205 */
/*05d0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ ISETP.GT.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fca0003f24070 */
/*0600*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0610*/ @!P0 LDS R7, [R0.X4+0x20] ; /* 0x0000200000078984 */
/* 0x000e240000004800 */
/*0620*/ @!P0 IADD3 R7, R2, R7, RZ ; /* 0x0000000702078210 */
/* 0x001fca0007ffe0ff */
/*0630*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0650*/ ISETP.GT.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fca0003f04070 */
/*0660*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*0670*/ @!P1 LDS R9, [R0.X4+0x10] ; /* 0x0000100000099984 */
/* 0x000e240000004800 */
/*0680*/ @!P1 IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102099824 */
/* 0x001fca00078e0209 */
/*0690*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x000fe80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*06c0*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff049424 */
/* 0x000fe200078e00ff */
/*06d0*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*06e0*/ @!P0 LDS R5, [R0.X4+0x8] ; /* 0x0000080000058984 */
/* 0x000e240000004800 */
/*06f0*/ @!P0 IMAD.IADD R7, R2, 0x1, R5 ; /* 0x0000000102078824 */
/* 0x001fca00078e0205 */
/*0700*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @!P1 LDS R2, [0x4] ; /* 0x00000400ff029984 */
/* 0x000fe80000000800 */
/*0730*/ @!P1 LDS R5, [R0.X4] ; /* 0x0000000000059984 */
/* 0x000e240000004800 */
/*0740*/ @!P1 IADD3 R11, R2, R5, RZ ; /* 0x00000005020b9210 */
/* 0x001fe20007ffe0ff */
/*0750*/ @!P1 IMAD.WIDE.U32 R4, R3.reuse, R4, c[0x0][0x160] ; /* 0x0000580003049625 */
/* 0x040fe200078e0004 */
/*0760*/ IADD3 R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a10 */
/* 0x000fc60007ffe0ff */
/*0770*/ @!P1 STS [R0.X4], R11 ; /* 0x0000000b00009388 */
/* 0x000fe20000004800 */
/*0780*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fc60003f06070 */
/*0790*/ @!P1 LDS R9, [RZ] ; /* 0x00000000ff099984 */
/* 0x000e280000000800 */
/*07a0*/ @!P1 STG.E [R4.64], R9 ; /* 0x0000000904009986 */
/* 0x0011ec000c101904 */
/*07b0*/ @!P0 BRA 0x60 ; /* 0xfffff8a000008947 */
/* 0x000fea000383ffff */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28mergePartialHistogramsKernelPjS_jj
.globl _Z28mergePartialHistogramsKernelPjS_jj
.p2align 8
.type _Z28mergePartialHistogramsKernelPjS_jj,@function
_Z28mergePartialHistogramsKernelPjS_jj:
s_load_b32 s8, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s8
s_cbranch_scc1 .LBB0_13
s_clause 0x2
s_load_b32 s9, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x18
s_mov_b32 s2, s15
s_mov_b32 s3, 0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v4, 2, v0
v_mad_u64_u32 v[1:2], null, v0, s8, s[2:3]
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_lshl_b32 s11, s8, 7
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e64 s0, s9, v0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s10, v1
s_add_i32 s2, s10, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_13
.LBB0_3:
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, v1
v_mov_b32_e32 v6, v0
s_mov_b32 s13, 0
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v6, 0x80, v6
v_add_nc_u32_e32 v2, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s1, s6, v7
v_add_co_ci_u32_e64 v8, s1, s7, v8, s1
s_delay_alu instid0(VALU_DEP_4)
v_cmp_le_u32_e64 s1, s9, v6
global_load_b32 v7, v[7:8], off
s_or_b32 s13, s1, s13
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v7, v5
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s13
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s12
s_mov_b32 s12, 64
ds_store_b32 v4, v5
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
s_lshr_b32 s1, s12, 1
s_cmp_lt_u32 s12, 2
s_mov_b32 s12, s1
s_cbranch_scc1 .LBB0_11
.LBB0_9:
s_mov_b32 s13, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB0_8
v_add_lshl_u32 v2, s12, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
ds_store_b32 v4, v2
s_branch .LBB0_8
.LBB0_11:
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
ds_load_b32 v2, v3
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v2, s[12:13]
s_branch .LBB0_2
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28mergePartialHistogramsKernelPjS_jj
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28mergePartialHistogramsKernelPjS_jj, .Lfunc_end0-_Z28mergePartialHistogramsKernelPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28mergePartialHistogramsKernelPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28mergePartialHistogramsKernelPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00096cea_00000000-6_mergePartialHistogramsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj
.type _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj, @function
_Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28mergePartialHistogramsKernelPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj, .-_Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj
.globl _Z28mergePartialHistogramsKernelPjS_jj
.type _Z28mergePartialHistogramsKernelPjS_jj, @function
_Z28mergePartialHistogramsKernelPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28mergePartialHistogramsKernelPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28mergePartialHistogramsKernelPjS_jj, .-_Z28mergePartialHistogramsKernelPjS_jj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28mergePartialHistogramsKernelPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28mergePartialHistogramsKernelPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mergePartialHistogramsKernel.hip"
.globl _Z43__device_stub__mergePartialHistogramsKernelPjS_jj # -- Begin function _Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.p2align 4, 0x90
.type _Z43__device_stub__mergePartialHistogramsKernelPjS_jj,@function
_Z43__device_stub__mergePartialHistogramsKernelPjS_jj: # @_Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28mergePartialHistogramsKernelPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z43__device_stub__mergePartialHistogramsKernelPjS_jj, .Lfunc_end0-_Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28mergePartialHistogramsKernelPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28mergePartialHistogramsKernelPjS_jj,@object # @_Z28mergePartialHistogramsKernelPjS_jj
.section .rodata,"a",@progbits
.globl _Z28mergePartialHistogramsKernelPjS_jj
.p2align 3, 0x0
_Z28mergePartialHistogramsKernelPjS_jj:
.quad _Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.size _Z28mergePartialHistogramsKernelPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28mergePartialHistogramsKernelPjS_jj"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__mergePartialHistogramsKernelPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28mergePartialHistogramsKernelPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <sys/types.h>
#define BLOCK_SIZE 256
#define STR_SIZE 256
#define HALO 1 // halo width along one direction when advancing to the next iteration
#define BENCH_PRINT
void run(int argc, char** argv);
long rows, cols;
int* data;
#define M_SEED 9
void init(int argc, char** argv)
{
char *folder;
char *filepath;
if (argc == 4)
{
cols = atol(argv[1]);
rows = atol(argv[2]);
folder = argv[3];
}
else
{
printf("Usage: %s row_len col_len folder\n", argv[0]);
exit(0);
}
filepath = (char *)malloc(sizeof(char) * (strlen(folder) + 128));
if (!filepath)
{
fprintf(stderr, "Cannot allocate filepath");
exit(EXIT_FAILURE);
}
sprintf(filepath, "%s/data.mem", folder);
FILE *fp;
if ((fp = fopen(filepath, "w+")) == 0)
{
fprintf(stderr, "%s was not opened\n", filepath);
exit(EXIT_FAILURE);
}
if (ftruncate(fileno(fp), sizeof(int) * rows * cols) != 0)
{
fprintf(stderr, "error: can not truncate %s\n", filepath);
perror("ftruncate");
exit(EXIT_FAILURE);
}
data = (int *)mmap(NULL, sizeof(int) * rows * cols, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, fileno(fp), 0);
if (!data)
{
fprintf(stderr, "Cannot mmap %s.\n", filepath);
exit(EXIT_FAILURE);
}
int seed = M_SEED;
srand(seed);
for (long i = 0; i < rows; i++)
{
for (long j = 0; j < cols; j++)
{
data[i * cols + j] = rand() % 10;
}
}
fflush(fp);
fclose(fp);
free(filepath);
}
int main(int argc, char** argv)
{
init(argc, argv);
return EXIT_SUCCESS;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <sys/types.h>
#define BLOCK_SIZE 256
#define STR_SIZE 256
#define HALO 1 // halo width along one direction when advancing to the next iteration
#define BENCH_PRINT
void run(int argc, char** argv);
long rows, cols;
int* data;
#define M_SEED 9
void init(int argc, char** argv)
{
char *folder;
char *filepath;
if (argc == 4)
{
cols = atol(argv[1]);
rows = atol(argv[2]);
folder = argv[3];
}
else
{
printf("Usage: %s row_len col_len folder\n", argv[0]);
exit(0);
}
filepath = (char *)malloc(sizeof(char) * (strlen(folder) + 128));
if (!filepath)
{
fprintf(stderr, "Cannot allocate filepath");
exit(EXIT_FAILURE);
}
sprintf(filepath, "%s/data.mem", folder);
FILE *fp;
if ((fp = fopen(filepath, "w+")) == 0)
{
fprintf(stderr, "%s was not opened\n", filepath);
exit(EXIT_FAILURE);
}
if (ftruncate(fileno(fp), sizeof(int) * rows * cols) != 0)
{
fprintf(stderr, "error: can not truncate %s\n", filepath);
perror("ftruncate");
exit(EXIT_FAILURE);
}
data = (int *)mmap(NULL, sizeof(int) * rows * cols, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, fileno(fp), 0);
if (!data)
{
fprintf(stderr, "Cannot mmap %s.\n", filepath);
exit(EXIT_FAILURE);
}
int seed = M_SEED;
srand(seed);
for (long i = 0; i < rows; i++)
{
for (long j = 0; j < cols; j++)
{
data[i * cols + j] = rand() % 10;
}
}
fflush(fp);
fclose(fp);
free(filepath);
}
int main(int argc, char** argv)
{
init(argc, argv);
return EXIT_SUCCESS;
} | .file "tmpxft_0004c39b_00000000-6_generator.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: %s row_len col_len folder\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Cannot allocate filepath"
.LC2:
.string "%s/data.mem"
.LC3:
.string "w+"
.LC4:
.string "%s was not opened\n"
.LC5:
.string "error: can not truncate %s\n"
.LC6:
.string "ftruncate"
.LC7:
.string "Cannot mmap %s.\n"
.text
.globl _Z4initiPPc
.type _Z4initiPPc, @function
_Z4initiPPc:
.LFB2070:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
cmpl $4, %edi
je .L21
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L21:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, cols(%rip)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, rows(%rip)
movq 24(%rbx), %rbp
movq %rbp, %rdi
call strlen@PLT
leaq 128(%rax), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L22
movq %rbp, %r8
leaq .LC2(%rip), %rcx
movq %rbx, %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L23
movq rows(%rip), %rbx
imulq cols(%rip), %rbx
salq $2, %rbx
movq %rax, %rdi
call fileno@PLT
movl %eax, %edi
movq %rbx, %rsi
call ftruncate@PLT
testl %eax, %eax
jne .L24
movq %r12, %rdi
call fileno@PLT
movl %eax, %r8d
movq rows(%rip), %rsi
imulq cols(%rip), %rsi
salq $2, %rsi
movl $0, %r9d
movl $16385, %ecx
movl $3, %edx
movl $0, %edi
call mmap@PLT
movq %rax, data(%rip)
testq %rax, %rax
je .L25
movl $9, %edi
call srand@PLT
movl $0, %ebp
cmpq $0, rows(%rip)
jg .L10
.L11:
movq %r12, %rdi
call fflush@PLT
movq %r12, %rdi
call fclose@PLT
movq %r13, %rdi
call free@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movq %r13, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %r13, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L25:
movq %r13, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
call rand@PLT
movq %rbp, %rcx
imulq cols(%rip), %rcx
addq %rbx, %rcx
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movq data(%rip), %rdx
movl %eax, (%rdx,%rcx,4)
addq $1, %rbx
cmpq %rbx, cols(%rip)
jg .L12
.L13:
addq $1, %rbp
cmpq %rbp, rows(%rip)
jle .L11
.L10:
movl $0, %ebx
cmpq $0, cols(%rip)
jg .L12
jmp .L13
.cfi_endproc
.LFE2070:
.size _Z4initiPPc, .-_Z4initiPPc
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z4initiPPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl data
.bss
.align 8
.type data, @object
.size data, 8
data:
.zero 8
.globl cols
.align 8
.type cols, @object
.size cols, 8
cols:
.zero 8
.globl rows
.align 8
.type rows, @object
.size rows, 8
rows:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <sys/types.h>
#define BLOCK_SIZE 256
#define STR_SIZE 256
#define HALO 1 // halo width along one direction when advancing to the next iteration
#define BENCH_PRINT
void run(int argc, char** argv);
long rows, cols;
int* data;
#define M_SEED 9
void init(int argc, char** argv)
{
char *folder;
char *filepath;
if (argc == 4)
{
cols = atol(argv[1]);
rows = atol(argv[2]);
folder = argv[3];
}
else
{
printf("Usage: %s row_len col_len folder\n", argv[0]);
exit(0);
}
filepath = (char *)malloc(sizeof(char) * (strlen(folder) + 128));
if (!filepath)
{
fprintf(stderr, "Cannot allocate filepath");
exit(EXIT_FAILURE);
}
sprintf(filepath, "%s/data.mem", folder);
FILE *fp;
if ((fp = fopen(filepath, "w+")) == 0)
{
fprintf(stderr, "%s was not opened\n", filepath);
exit(EXIT_FAILURE);
}
if (ftruncate(fileno(fp), sizeof(int) * rows * cols) != 0)
{
fprintf(stderr, "error: can not truncate %s\n", filepath);
perror("ftruncate");
exit(EXIT_FAILURE);
}
data = (int *)mmap(NULL, sizeof(int) * rows * cols, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, fileno(fp), 0);
if (!data)
{
fprintf(stderr, "Cannot mmap %s.\n", filepath);
exit(EXIT_FAILURE);
}
int seed = M_SEED;
srand(seed);
for (long i = 0; i < rows; i++)
{
for (long j = 0; j < cols; j++)
{
data[i * cols + j] = rand() % 10;
}
}
fflush(fp);
fclose(fp);
free(filepath);
}
int main(int argc, char** argv)
{
init(argc, argv);
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <sys/types.h>
#define BLOCK_SIZE 256
#define STR_SIZE 256
#define HALO 1 // halo width along one direction when advancing to the next iteration
#define BENCH_PRINT
void run(int argc, char** argv);
long rows, cols;
int* data;
#define M_SEED 9
void init(int argc, char** argv)
{
char *folder;
char *filepath;
if (argc == 4)
{
cols = atol(argv[1]);
rows = atol(argv[2]);
folder = argv[3];
}
else
{
printf("Usage: %s row_len col_len folder\n", argv[0]);
exit(0);
}
filepath = (char *)malloc(sizeof(char) * (strlen(folder) + 128));
if (!filepath)
{
fprintf(stderr, "Cannot allocate filepath");
exit(EXIT_FAILURE);
}
sprintf(filepath, "%s/data.mem", folder);
FILE *fp;
if ((fp = fopen(filepath, "w+")) == 0)
{
fprintf(stderr, "%s was not opened\n", filepath);
exit(EXIT_FAILURE);
}
if (ftruncate(fileno(fp), sizeof(int) * rows * cols) != 0)
{
fprintf(stderr, "error: can not truncate %s\n", filepath);
perror("ftruncate");
exit(EXIT_FAILURE);
}
data = (int *)mmap(NULL, sizeof(int) * rows * cols, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, fileno(fp), 0);
if (!data)
{
fprintf(stderr, "Cannot mmap %s.\n", filepath);
exit(EXIT_FAILURE);
}
int seed = M_SEED;
srand(seed);
for (long i = 0; i < rows; i++)
{
for (long j = 0; j < cols; j++)
{
data[i * cols + j] = rand() % 10;
}
}
fflush(fp);
fclose(fp);
free(filepath);
}
int main(int argc, char** argv)
{
init(argc, argv);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <sys/types.h>
#define BLOCK_SIZE 256
#define STR_SIZE 256
#define HALO 1 // halo width along one direction when advancing to the next iteration
#define BENCH_PRINT
void run(int argc, char** argv);
long rows, cols;
int* data;
#define M_SEED 9
void init(int argc, char** argv)
{
char *folder;
char *filepath;
if (argc == 4)
{
cols = atol(argv[1]);
rows = atol(argv[2]);
folder = argv[3];
}
else
{
printf("Usage: %s row_len col_len folder\n", argv[0]);
exit(0);
}
filepath = (char *)malloc(sizeof(char) * (strlen(folder) + 128));
if (!filepath)
{
fprintf(stderr, "Cannot allocate filepath");
exit(EXIT_FAILURE);
}
sprintf(filepath, "%s/data.mem", folder);
FILE *fp;
if ((fp = fopen(filepath, "w+")) == 0)
{
fprintf(stderr, "%s was not opened\n", filepath);
exit(EXIT_FAILURE);
}
if (ftruncate(fileno(fp), sizeof(int) * rows * cols) != 0)
{
fprintf(stderr, "error: can not truncate %s\n", filepath);
perror("ftruncate");
exit(EXIT_FAILURE);
}
data = (int *)mmap(NULL, sizeof(int) * rows * cols, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, fileno(fp), 0);
if (!data)
{
fprintf(stderr, "Cannot mmap %s.\n", filepath);
exit(EXIT_FAILURE);
}
int seed = M_SEED;
srand(seed);
for (long i = 0; i < rows; i++)
{
for (long j = 0; j < cols; j++)
{
data[i * cols + j] = rand() % 10;
}
}
fflush(fp);
fclose(fp);
free(filepath);
}
int main(int argc, char** argv)
{
init(argc, argv);
return EXIT_SUCCESS;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <sys/types.h>
#define BLOCK_SIZE 256
#define STR_SIZE 256
#define HALO 1 // halo width along one direction when advancing to the next iteration
#define BENCH_PRINT
void run(int argc, char** argv);
long rows, cols;
int* data;
#define M_SEED 9
void init(int argc, char** argv)
{
char *folder;
char *filepath;
if (argc == 4)
{
cols = atol(argv[1]);
rows = atol(argv[2]);
folder = argv[3];
}
else
{
printf("Usage: %s row_len col_len folder\n", argv[0]);
exit(0);
}
filepath = (char *)malloc(sizeof(char) * (strlen(folder) + 128));
if (!filepath)
{
fprintf(stderr, "Cannot allocate filepath");
exit(EXIT_FAILURE);
}
sprintf(filepath, "%s/data.mem", folder);
FILE *fp;
if ((fp = fopen(filepath, "w+")) == 0)
{
fprintf(stderr, "%s was not opened\n", filepath);
exit(EXIT_FAILURE);
}
if (ftruncate(fileno(fp), sizeof(int) * rows * cols) != 0)
{
fprintf(stderr, "error: can not truncate %s\n", filepath);
perror("ftruncate");
exit(EXIT_FAILURE);
}
data = (int *)mmap(NULL, sizeof(int) * rows * cols, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_NORESERVE, fileno(fp), 0);
if (!data)
{
fprintf(stderr, "Cannot mmap %s.\n", filepath);
exit(EXIT_FAILURE);
}
int seed = M_SEED;
srand(seed);
for (long i = 0; i < rows; i++)
{
for (long j = 0; j < cols; j++)
{
data[i * cols + j] = rand() % 10;
}
}
fflush(fp);
fclose(fp);
free(filepath);
}
int main(int argc, char** argv)
{
init(argc, argv);
return EXIT_SUCCESS;
} | .text
.file "generator.hip"
.globl _Z4initiPPc # -- Begin function _Z4initiPPc
.p2align 4, 0x90
.type _Z4initiPPc,@function
_Z4initiPPc: # @_Z4initiPPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $4, %edi
jne .LBB0_15
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, cols(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, rows(%rip)
movq 24(%rbx), %r14
movq %r14, %rdi
callq strlen
leaq 128(%rax), %rdi
callq malloc
testq %rax, %rax
je .LBB0_16
# %bb.2:
movq %rax, %rbx
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB0_3
# %bb.5:
movq %rax, %r14
movq %rax, %rdi
callq fileno
movq rows(%rip), %rsi
imulq cols(%rip), %rsi
shlq $2, %rsi
movl %eax, %edi
callq ftruncate
testl %eax, %eax
jne .LBB0_17
# %bb.6:
movq rows(%rip), %r15
imulq cols(%rip), %r15
shlq $2, %r15
movq %r14, %rdi
callq fileno
xorl %edi, %edi
movq %r15, %rsi
movl $3, %edx
movl $16385, %ecx # imm = 0x4001
movl %eax, %r8d
xorl %r9d, %r9d
callq mmap
movq %rax, data(%rip)
testq %rax, %rax
je .LBB0_7
# %bb.8:
movl $9, %edi
callq srand
cmpq $0, rows(%rip)
jle .LBB0_14
# %bb.9: # %.preheader.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_13: # %._crit_edge
# in Loop: Header=BB0_10 Depth=1
incq %r12
addq $4, %r15
cmpq rows(%rip), %r12
jge .LBB0_14
.LBB0_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
cmpq $0, cols(%rip)
jle .LBB0_13
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB0_10 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_12: # %.lr.ph
# Parent Loop BB0_10 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
movq cols(%rip), %rdx
movq %r15, %rsi
imulq %rdx, %rsi
addq data(%rip), %rsi
subl %ecx, %eax
movl %eax, (%rsi,%r13,4)
incq %r13
cmpq %rdx, %r13
jl .LBB0_12
jmp .LBB0_13
.LBB0_14: # %._crit_edge31
movq %r14, %rdi
callq fflush
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.LBB0_15:
.cfi_def_cfa_offset 48
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB0_16:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB0_3:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
jmp .LBB0_4
.LBB0_17:
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $.L.str.6, %edi
callq perror
movl $1, %edi
callq exit
.LBB0_7:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
.LBB0_4:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z4initiPPc, .Lfunc_end0-_Z4initiPPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z4initiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type rows,@object # @rows
.bss
.globl rows
.p2align 3, 0x0
rows:
.quad 0 # 0x0
.size rows, 8
.type cols,@object # @cols
.globl cols
.p2align 3, 0x0
cols:
.quad 0 # 0x0
.size cols, 8
.type data,@object # @data
.globl data
.p2align 3, 0x0
data:
.quad 0
.size data, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s row_len col_len folder\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot allocate filepath"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s/data.mem"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w+"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s was not opened\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error: can not truncate %s\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ftruncate"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cannot mmap %s.\n"
.size .L.str.7, 17
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c39b_00000000-6_generator.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: %s row_len col_len folder\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Cannot allocate filepath"
.LC2:
.string "%s/data.mem"
.LC3:
.string "w+"
.LC4:
.string "%s was not opened\n"
.LC5:
.string "error: can not truncate %s\n"
.LC6:
.string "ftruncate"
.LC7:
.string "Cannot mmap %s.\n"
.text
.globl _Z4initiPPc
.type _Z4initiPPc, @function
_Z4initiPPc:
.LFB2070:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
cmpl $4, %edi
je .L21
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L21:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, cols(%rip)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, rows(%rip)
movq 24(%rbx), %rbp
movq %rbp, %rdi
call strlen@PLT
leaq 128(%rax), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L22
movq %rbp, %r8
leaq .LC2(%rip), %rcx
movq %rbx, %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L23
movq rows(%rip), %rbx
imulq cols(%rip), %rbx
salq $2, %rbx
movq %rax, %rdi
call fileno@PLT
movl %eax, %edi
movq %rbx, %rsi
call ftruncate@PLT
testl %eax, %eax
jne .L24
movq %r12, %rdi
call fileno@PLT
movl %eax, %r8d
movq rows(%rip), %rsi
imulq cols(%rip), %rsi
salq $2, %rsi
movl $0, %r9d
movl $16385, %ecx
movl $3, %edx
movl $0, %edi
call mmap@PLT
movq %rax, data(%rip)
testq %rax, %rax
je .L25
movl $9, %edi
call srand@PLT
movl $0, %ebp
cmpq $0, rows(%rip)
jg .L10
.L11:
movq %r12, %rdi
call fflush@PLT
movq %r12, %rdi
call fclose@PLT
movq %r13, %rdi
call free@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movq %r13, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %r13, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L25:
movq %r13, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
call rand@PLT
movq %rbp, %rcx
imulq cols(%rip), %rcx
addq %rbx, %rcx
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movq data(%rip), %rdx
movl %eax, (%rdx,%rcx,4)
addq $1, %rbx
cmpq %rbx, cols(%rip)
jg .L12
.L13:
addq $1, %rbp
cmpq %rbp, rows(%rip)
jle .L11
.L10:
movl $0, %ebx
cmpq $0, cols(%rip)
jg .L12
jmp .L13
.cfi_endproc
.LFE2070:
.size _Z4initiPPc, .-_Z4initiPPc
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z4initiPPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl data
.bss
.align 8
.type data, @object
.size data, 8
data:
.zero 8
.globl cols
.align 8
.type cols, @object
.size cols, 8
cols:
.zero 8
.globl rows
.align 8
.type rows, @object
.size rows, 8
rows:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "generator.hip"
.globl _Z4initiPPc # -- Begin function _Z4initiPPc
.p2align 4, 0x90
.type _Z4initiPPc,@function
_Z4initiPPc: # @_Z4initiPPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $4, %edi
jne .LBB0_15
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, cols(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, rows(%rip)
movq 24(%rbx), %r14
movq %r14, %rdi
callq strlen
leaq 128(%rax), %rdi
callq malloc
testq %rax, %rax
je .LBB0_16
# %bb.2:
movq %rax, %rbx
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB0_3
# %bb.5:
movq %rax, %r14
movq %rax, %rdi
callq fileno
movq rows(%rip), %rsi
imulq cols(%rip), %rsi
shlq $2, %rsi
movl %eax, %edi
callq ftruncate
testl %eax, %eax
jne .LBB0_17
# %bb.6:
movq rows(%rip), %r15
imulq cols(%rip), %r15
shlq $2, %r15
movq %r14, %rdi
callq fileno
xorl %edi, %edi
movq %r15, %rsi
movl $3, %edx
movl $16385, %ecx # imm = 0x4001
movl %eax, %r8d
xorl %r9d, %r9d
callq mmap
movq %rax, data(%rip)
testq %rax, %rax
je .LBB0_7
# %bb.8:
movl $9, %edi
callq srand
cmpq $0, rows(%rip)
jle .LBB0_14
# %bb.9: # %.preheader.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_13: # %._crit_edge
# in Loop: Header=BB0_10 Depth=1
incq %r12
addq $4, %r15
cmpq rows(%rip), %r12
jge .LBB0_14
.LBB0_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
cmpq $0, cols(%rip)
jle .LBB0_13
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB0_10 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_12: # %.lr.ph
# Parent Loop BB0_10 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
movq cols(%rip), %rdx
movq %r15, %rsi
imulq %rdx, %rsi
addq data(%rip), %rsi
subl %ecx, %eax
movl %eax, (%rsi,%r13,4)
incq %r13
cmpq %rdx, %r13
jl .LBB0_12
jmp .LBB0_13
.LBB0_14: # %._crit_edge31
movq %r14, %rdi
callq fflush
movq %r14, %rdi
callq fclose
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.LBB0_15:
.cfi_def_cfa_offset 48
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB0_16:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB0_3:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
jmp .LBB0_4
.LBB0_17:
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $.L.str.6, %edi
callq perror
movl $1, %edi
callq exit
.LBB0_7:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
.LBB0_4:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z4initiPPc, .Lfunc_end0-_Z4initiPPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z4initiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type rows,@object # @rows
.bss
.globl rows
.p2align 3, 0x0
rows:
.quad 0 # 0x0
.size rows, 8
.type cols,@object # @cols
.globl cols
.p2align 3, 0x0
cols:
.quad 0 # 0x0
.size cols, 8
.type data,@object # @data
.globl data
.p2align 3, 0x0
data:
.quad 0
.size data, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s row_len col_len folder\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot allocate filepath"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s/data.mem"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w+"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s was not opened\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error: can not truncate %s\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ftruncate"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cannot mmap %s.\n"
.size .L.str.7, 17
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define cudaErrorCheck(call) \
do { \
cudaError_t cuErr = call; \
if (cudaSuccess != cuErr) { \
printf("CUDA Error - %s:%d: '%s'\n", __FILE__, __LINE__, \
cudaGetErrorString(cuErr)); \
exit(0); \
} \
} while (0)
#define BLOCK_NUM 100
#define BLOCK_DIM 512
__device__ int count = 0;
__global__ void getThreadNum() {
int oldVal, returnVal;
do {
oldVal = count;
returnVal = atomicCAS(&count, oldVal, oldVal + 1);
} while (oldVal != returnVal);
}
int main() {
int result = -1;
getThreadNum<<<BLOCK_NUM, BLOCK_DIM>>>();
cudaErrorCheck(cudaGetLastError());
cudaDeviceSynchronize();
int *count_addr;
cudaErrorCheck(cudaGetSymbolAddress((void**)&count_addr, count));
cudaErrorCheck(cudaMemcpy(&result, count_addr, sizeof(int), cudaMemcpyDeviceToHost));
printf("thread num, expected = %d, actual = %d\n", BLOCK_NUM * BLOCK_DIM, result);
return 0;
} | code for sm_80
Function : _Z12getThreadNumv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0050*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0060*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x004fcc0007ffe0ff */
/*0070*/ ATOMG.E.CAS.STRONG.GPU PT, R5, [R2], R4, R5 ; /* 0x00000004020573a9 */
/* 0x000ea400001ee105 */
/*0080*/ ISETP.NE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 BRA 0x40 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define cudaErrorCheck(call) \
do { \
cudaError_t cuErr = call; \
if (cudaSuccess != cuErr) { \
printf("CUDA Error - %s:%d: '%s'\n", __FILE__, __LINE__, \
cudaGetErrorString(cuErr)); \
exit(0); \
} \
} while (0)
#define BLOCK_NUM 100
#define BLOCK_DIM 512
__device__ int count = 0;
__global__ void getThreadNum() {
int oldVal, returnVal;
do {
oldVal = count;
returnVal = atomicCAS(&count, oldVal, oldVal + 1);
} while (oldVal != returnVal);
}
int main() {
int result = -1;
getThreadNum<<<BLOCK_NUM, BLOCK_DIM>>>();
cudaErrorCheck(cudaGetLastError());
cudaDeviceSynchronize();
int *count_addr;
cudaErrorCheck(cudaGetSymbolAddress((void**)&count_addr, count));
cudaErrorCheck(cudaMemcpy(&result, count_addr, sizeof(int), cudaMemcpyDeviceToHost));
printf("thread num, expected = %d, actual = %d\n", BLOCK_NUM * BLOCK_DIM, result);
return 0;
} | .file "tmpxft_00052755_00000000-6_testAtomic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12getThreadNumvv
.type _Z31__device_stub__Z12getThreadNumvv, @function
_Z31__device_stub__Z12getThreadNumvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12getThreadNumv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12getThreadNumvv, .-_Z31__device_stub__Z12getThreadNumvv
.globl _Z12getThreadNumv
.type _Z12getThreadNumv, @function
_Z12getThreadNumv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12getThreadNumvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12getThreadNumv, .-_Z12getThreadNumv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/FuriousBerserker/ConcurrencyError/master/CUDA/testAtomic/testAtomic.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Error - %s:%d: '%s'\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "thread num, expected = %d, actual = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $-1, 8(%rsp)
movl $512, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $100, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
je .L13
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $30, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L18:
call _Z31__device_stub__Z12getThreadNumvv
jmp .L12
.L13:
call cudaDeviceSynchronize@PLT
leaq 24(%rsp), %rdi
leaq _ZL5count(%rip), %rsi
call cudaGetSymbolAddress@PLT
testl %eax, %eax
je .L14
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $33, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
je .L15
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $34, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L15:
movl 8(%rsp), %ecx
movl $51200, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z12getThreadNumv"
.LC4:
.string "count"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12getThreadNumv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5count(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5count
.comm _ZL5count,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define cudaErrorCheck(call) \
do { \
cudaError_t cuErr = call; \
if (cudaSuccess != cuErr) { \
printf("CUDA Error - %s:%d: '%s'\n", __FILE__, __LINE__, \
cudaGetErrorString(cuErr)); \
exit(0); \
} \
} while (0)
#define BLOCK_NUM 100
#define BLOCK_DIM 512
__device__ int count = 0;
__global__ void getThreadNum() {
int oldVal, returnVal;
do {
oldVal = count;
returnVal = atomicCAS(&count, oldVal, oldVal + 1);
} while (oldVal != returnVal);
}
int main() {
int result = -1;
getThreadNum<<<BLOCK_NUM, BLOCK_DIM>>>();
cudaErrorCheck(cudaGetLastError());
cudaDeviceSynchronize();
int *count_addr;
cudaErrorCheck(cudaGetSymbolAddress((void**)&count_addr, count));
cudaErrorCheck(cudaMemcpy(&result, count_addr, sizeof(int), cudaMemcpyDeviceToHost));
printf("thread num, expected = %d, actual = %d\n", BLOCK_NUM * BLOCK_DIM, result);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define cudaErrorCheck(call) \
do { \
hipError_t cuErr = call; \
if (hipSuccess != cuErr) { \
printf("CUDA Error - %s:%d: '%s'\n", __FILE__, __LINE__, \
hipGetErrorString(cuErr)); \
exit(0); \
} \
} while (0)
#define BLOCK_NUM 100
#define BLOCK_DIM 512
__device__ int count = 0;
__global__ void getThreadNum() {
int oldVal, returnVal;
do {
oldVal = count;
returnVal = atomicCAS(&count, oldVal, oldVal + 1);
} while (oldVal != returnVal);
}
int main() {
int result = -1;
getThreadNum<<<BLOCK_NUM, BLOCK_DIM>>>();
cudaErrorCheck(hipGetLastError());
hipDeviceSynchronize();
int *count_addr;
cudaErrorCheck(hipGetSymbolAddress((void**)&count_addr, HIP_SYMBOL(count)));
cudaErrorCheck(hipMemcpy(&result, count_addr, sizeof(int), hipMemcpyDeviceToHost));
printf("thread num, expected = %d, actual = %d\n", BLOCK_NUM * BLOCK_DIM, result);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define cudaErrorCheck(call) \
do { \
hipError_t cuErr = call; \
if (hipSuccess != cuErr) { \
printf("CUDA Error - %s:%d: '%s'\n", __FILE__, __LINE__, \
hipGetErrorString(cuErr)); \
exit(0); \
} \
} while (0)
#define BLOCK_NUM 100
#define BLOCK_DIM 512
__device__ int count = 0;
__global__ void getThreadNum() {
int oldVal, returnVal;
do {
oldVal = count;
returnVal = atomicCAS(&count, oldVal, oldVal + 1);
} while (oldVal != returnVal);
}
int main() {
int result = -1;
getThreadNum<<<BLOCK_NUM, BLOCK_DIM>>>();
cudaErrorCheck(hipGetLastError());
hipDeviceSynchronize();
int *count_addr;
cudaErrorCheck(hipGetSymbolAddress((void**)&count_addr, HIP_SYMBOL(count)));
cudaErrorCheck(hipMemcpy(&result, count_addr, sizeof(int), hipMemcpyDeviceToHost));
printf("thread num, expected = %d, actual = %d\n", BLOCK_NUM * BLOCK_DIM, result);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12getThreadNumv
.globl _Z12getThreadNumv
.p2align 8
.type _Z12getThreadNumv,@function
_Z12getThreadNumv:
v_mov_b32_e32 v0, 0
s_mov_b32 s0, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, count@rel32@lo+4
s_addc_u32 s3, s3, count@rel32@hi+12
.LBB0_1:
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 1, v2
global_atomic_cmpswap_b32 v1, v0, v[1:2], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v1
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_1
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12getThreadNumv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12getThreadNumv, .Lfunc_end0-_Z12getThreadNumv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected count
.type count,@object
.section .bss,"aw",@nobits
.globl count
.p2align 2, 0x0
count:
.long 0
.size count, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym count
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12getThreadNumv
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z12getThreadNumv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define cudaErrorCheck(call) \
do { \
hipError_t cuErr = call; \
if (hipSuccess != cuErr) { \
printf("CUDA Error - %s:%d: '%s'\n", __FILE__, __LINE__, \
hipGetErrorString(cuErr)); \
exit(0); \
} \
} while (0)
#define BLOCK_NUM 100
#define BLOCK_DIM 512
__device__ int count = 0;
__global__ void getThreadNum() {
int oldVal, returnVal;
do {
oldVal = count;
returnVal = atomicCAS(&count, oldVal, oldVal + 1);
} while (oldVal != returnVal);
}
int main() {
int result = -1;
getThreadNum<<<BLOCK_NUM, BLOCK_DIM>>>();
cudaErrorCheck(hipGetLastError());
hipDeviceSynchronize();
int *count_addr;
cudaErrorCheck(hipGetSymbolAddress((void**)&count_addr, HIP_SYMBOL(count)));
cudaErrorCheck(hipMemcpy(&result, count_addr, sizeof(int), hipMemcpyDeviceToHost));
printf("thread num, expected = %d, actual = %d\n", BLOCK_NUM * BLOCK_DIM, result);
return 0;
} | .text
.file "testAtomic.hip"
.globl _Z27__device_stub__getThreadNumv # -- Begin function _Z27__device_stub__getThreadNumv
.p2align 4, 0x90
.type _Z27__device_stub__getThreadNumv,@function
_Z27__device_stub__getThreadNumv: # @_Z27__device_stub__getThreadNumv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12getThreadNumv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__getThreadNumv, .Lfunc_end0-_Z27__device_stub__getThreadNumv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $-1, 12(%rsp)
movabsq $4294967396, %rdi # imm = 0x100000064
leaq 412(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12getThreadNumv, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
movl $count, %esi
callq hipGetSymbolAddress
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movl 12(%rsp), %edx
movl $.L.str.2, %edi
movl $51200, %esi # imm = 0xC800
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 80
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $32, %edx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $35, %edx
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $36, %edx
.LBB1_4:
movq %rax, %rcx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12getThreadNumv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $count, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type count,@object # @count
.local count
.comm count,4,4
.type _Z12getThreadNumv,@object # @_Z12getThreadNumv
.section .rodata,"a",@progbits
.globl _Z12getThreadNumv
.p2align 3, 0x0
_Z12getThreadNumv:
.quad _Z27__device_stub__getThreadNumv
.size _Z12getThreadNumv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error - %s:%d: '%s'\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/FuriousBerserker/ConcurrencyError/master/CUDA/testAtomic/testAtomic.hip"
.size .L.str.1, 129
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "thread num, expected = %d, actual = %d\n"
.size .L.str.2, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12getThreadNumv"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "count"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__getThreadNumv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym count
.addrsig_sym _Z12getThreadNumv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12getThreadNumv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0050*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0060*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x004fcc0007ffe0ff */
/*0070*/ ATOMG.E.CAS.STRONG.GPU PT, R5, [R2], R4, R5 ; /* 0x00000004020573a9 */
/* 0x000ea400001ee105 */
/*0080*/ ISETP.NE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 BRA 0x40 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12getThreadNumv
.globl _Z12getThreadNumv
.p2align 8
.type _Z12getThreadNumv,@function
_Z12getThreadNumv:
v_mov_b32_e32 v0, 0
s_mov_b32 s0, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, count@rel32@lo+4
s_addc_u32 s3, s3, count@rel32@hi+12
.LBB0_1:
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 1, v2
global_atomic_cmpswap_b32 v1, v0, v[1:2], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v1
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_1
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12getThreadNumv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12getThreadNumv, .Lfunc_end0-_Z12getThreadNumv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected count
.type count,@object
.section .bss,"aw",@nobits
.globl count
.p2align 2, 0x0
count:
.long 0
.size count, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym count
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12getThreadNumv
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z12getThreadNumv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00052755_00000000-6_testAtomic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12getThreadNumvv
.type _Z31__device_stub__Z12getThreadNumvv, @function
_Z31__device_stub__Z12getThreadNumvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12getThreadNumv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12getThreadNumvv, .-_Z31__device_stub__Z12getThreadNumvv
.globl _Z12getThreadNumv
.type _Z12getThreadNumv, @function
_Z12getThreadNumv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12getThreadNumvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12getThreadNumv, .-_Z12getThreadNumv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/FuriousBerserker/ConcurrencyError/master/CUDA/testAtomic/testAtomic.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Error - %s:%d: '%s'\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "thread num, expected = %d, actual = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $-1, 8(%rsp)
movl $512, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $100, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
je .L13
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $30, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L18:
call _Z31__device_stub__Z12getThreadNumvv
jmp .L12
.L13:
call cudaDeviceSynchronize@PLT
leaq 24(%rsp), %rdi
leaq _ZL5count(%rip), %rsi
call cudaGetSymbolAddress@PLT
testl %eax, %eax
je .L14
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $33, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
je .L15
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $34, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L15:
movl 8(%rsp), %ecx
movl $51200, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z12getThreadNumv"
.LC4:
.string "count"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12getThreadNumv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5count(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5count
.comm _ZL5count,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testAtomic.hip"
.globl _Z27__device_stub__getThreadNumv # -- Begin function _Z27__device_stub__getThreadNumv
.p2align 4, 0x90
.type _Z27__device_stub__getThreadNumv,@function
_Z27__device_stub__getThreadNumv: # @_Z27__device_stub__getThreadNumv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12getThreadNumv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__getThreadNumv, .Lfunc_end0-_Z27__device_stub__getThreadNumv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $-1, 12(%rsp)
movabsq $4294967396, %rdi # imm = 0x100000064
leaq 412(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12getThreadNumv, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
movl $count, %esi
callq hipGetSymbolAddress
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movl 12(%rsp), %edx
movl $.L.str.2, %edi
movl $51200, %esi # imm = 0xC800
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 80
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $32, %edx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $35, %edx
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $36, %edx
.LBB1_4:
movq %rax, %rcx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12getThreadNumv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $count, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type count,@object # @count
.local count
.comm count,4,4
.type _Z12getThreadNumv,@object # @_Z12getThreadNumv
.section .rodata,"a",@progbits
.globl _Z12getThreadNumv
.p2align 3, 0x0
_Z12getThreadNumv:
.quad _Z27__device_stub__getThreadNumv
.size _Z12getThreadNumv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error - %s:%d: '%s'\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/FuriousBerserker/ConcurrencyError/master/CUDA/testAtomic/testAtomic.hip"
.size .L.str.1, 129
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "thread num, expected = %d, actual = %d\n"
.size .L.str.2, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12getThreadNumv"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "count"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__getThreadNumv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym count
.addrsig_sym _Z12getThreadNumv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ int get(int x, int y,int width){
return y * width +x;
}
extern "C"
__global__ void EVAPORATION( int width, int height, float *values, float evapCoef)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < width && j < height ){//TODO + alone
int k = get(i,j,width);
values[k] -= values[k] * evapCoef;
}
} | code for sm_80
Function : EVAPORATION
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FFMA R5, -R0, c[0x0][0x170], R0 ; /* 0x00005c0000057a23 */
/* 0x004fca0000000100 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ int get(int x, int y,int width){
return y * width +x;
}
extern "C"
__global__ void EVAPORATION( int width, int height, float *values, float evapCoef)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < width && j < height ){//TODO + alone
int k = get(i,j,width);
values[k] -= values[k] * evapCoef;
}
} | .file "tmpxft_000a65b1_00000000-6_Evaporation_2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3getiii
.type _Z3getiii, @function
_Z3getiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3getiii, .-_Z3getiii
.globl _Z34__device_stub__Z11EVAPORATIONiiPffiiPff
.type _Z34__device_stub__Z11EVAPORATIONiiPffiiPff, @function
_Z34__device_stub__Z11EVAPORATIONiiPffiiPff:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq EVAPORATION(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z34__device_stub__Z11EVAPORATIONiiPffiiPff, .-_Z34__device_stub__Z11EVAPORATIONiiPffiiPff
.globl EVAPORATION
.type EVAPORATION, @function
EVAPORATION:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11EVAPORATIONiiPffiiPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size EVAPORATION, .-EVAPORATION
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "EVAPORATION"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq EVAPORATION(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ int get(int x, int y,int width){
return y * width +x;
}
extern "C"
__global__ void EVAPORATION( int width, int height, float *values, float evapCoef)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < width && j < height ){//TODO + alone
int k = get(i,j,width);
values[k] -= values[k] * evapCoef;
}
} | #include <hip/hip_runtime.h>
__device__ int get(int x, int y,int width){
return y * width +x;
}
extern "C"
__global__ void EVAPORATION( int width, int height, float *values, float evapCoef)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < width && j < height ){//TODO + alone
int k = get(i,j,width);
values[k] -= values[k] * evapCoef;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ int get(int x, int y,int width){
return y * width +x;
}
extern "C"
__global__ void EVAPORATION( int width, int height, float *values, float evapCoef)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < width && j < height ){//TODO + alone
int k = get(i,j,width);
values[k] -= values[k] * evapCoef;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected EVAPORATION
.globl EVAPORATION
.p2align 8
.type EVAPORATION,@function
EVAPORATION:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel EVAPORATION
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size EVAPORATION, .Lfunc_end0-EVAPORATION
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: EVAPORATION
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: EVAPORATION.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ int get(int x, int y,int width){
return y * width +x;
}
extern "C"
__global__ void EVAPORATION( int width, int height, float *values, float evapCoef)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < width && j < height ){//TODO + alone
int k = get(i,j,width);
values[k] -= values[k] * evapCoef;
}
} | .text
.file "Evaporation_2D.hip"
.globl __device_stub__EVAPORATION # -- Begin function __device_stub__EVAPORATION
.p2align 4, 0x90
.type __device_stub__EVAPORATION,@function
__device_stub__EVAPORATION: # @__device_stub__EVAPORATION
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $EVAPORATION, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__EVAPORATION, .Lfunc_end0-__device_stub__EVAPORATION
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $EVAPORATION, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type EVAPORATION,@object # @EVAPORATION
.section .rodata,"a",@progbits
.globl EVAPORATION
.p2align 3, 0x0
EVAPORATION:
.quad __device_stub__EVAPORATION
.size EVAPORATION, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "EVAPORATION"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__EVAPORATION
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym EVAPORATION
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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