system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : EVAPORATION
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FFMA R5, -R0, c[0x0][0x170], R0 ; /* 0x00005c0000057a23 */
/* 0x004fca0000000100 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected EVAPORATION
.globl EVAPORATION
.p2align 8
.type EVAPORATION,@function
EVAPORATION:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel EVAPORATION
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size EVAPORATION, .Lfunc_end0-EVAPORATION
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: EVAPORATION
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: EVAPORATION.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a65b1_00000000-6_Evaporation_2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3getiii
.type _Z3getiii, @function
_Z3getiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3getiii, .-_Z3getiii
.globl _Z34__device_stub__Z11EVAPORATIONiiPffiiPff
.type _Z34__device_stub__Z11EVAPORATIONiiPffiiPff, @function
_Z34__device_stub__Z11EVAPORATIONiiPffiiPff:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq EVAPORATION(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z34__device_stub__Z11EVAPORATIONiiPffiiPff, .-_Z34__device_stub__Z11EVAPORATIONiiPffiiPff
.globl EVAPORATION
.type EVAPORATION, @function
EVAPORATION:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11EVAPORATIONiiPffiiPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size EVAPORATION, .-EVAPORATION
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "EVAPORATION"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq EVAPORATION(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Evaporation_2D.hip"
.globl __device_stub__EVAPORATION # -- Begin function __device_stub__EVAPORATION
.p2align 4, 0x90
.type __device_stub__EVAPORATION,@function
__device_stub__EVAPORATION: # @__device_stub__EVAPORATION
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $EVAPORATION, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__EVAPORATION, .Lfunc_end0-__device_stub__EVAPORATION
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $EVAPORATION, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type EVAPORATION,@object # @EVAPORATION
.section .rodata,"a",@progbits
.globl EVAPORATION
.p2align 3, 0x0
EVAPORATION:
.quad __device_stub__EVAPORATION
.size EVAPORATION, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "EVAPORATION"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__EVAPORATION
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym EVAPORATION
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkDimension(){
printf("threadIdx:(%d,%d,%d), blockIdx:(%d,%d,%d),blockDim:(%d,%d,%d),gridDim:(%d,%d,%d)\n",
threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
int main(){
// 数据总量
int nElem = 6;
dim3 block(3);
dim3 grid((nElem + block.x - 1)/block.x);
printf("grid:(%d,%d,%d)\n",grid.x,grid.y,grid.z);
printf("block:(%d,%d,%d)\n",block.x,block.y,block.z);
checkDimension<<<grid,block>>>();
// reset device before exit;
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z14checkDimensionv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000ee40000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ee80000002600 */
/*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100c00 */
/*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0083e40000100c00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkDimension(){
printf("threadIdx:(%d,%d,%d), blockIdx:(%d,%d,%d),blockDim:(%d,%d,%d),gridDim:(%d,%d,%d)\n",
threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
int main(){
// 数据总量
int nElem = 6;
dim3 block(3);
dim3 grid((nElem + block.x - 1)/block.x);
printf("grid:(%d,%d,%d)\n",grid.x,grid.y,grid.z);
printf("block:(%d,%d,%d)\n",block.x,block.y,block.z);
checkDimension<<<grid,block>>>();
// reset device before exit;
cudaDeviceReset();
return 0;
} | .file "tmpxft_0014a5b7_00000000-6_checkDimension.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14checkDimensionvv
.type _Z33__device_stub__Z14checkDimensionvv, @function
_Z33__device_stub__Z14checkDimensionvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14checkDimensionv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14checkDimensionvv, .-_Z33__device_stub__Z14checkDimensionvv
.globl _Z14checkDimensionv
.type _Z14checkDimensionv, @function
_Z14checkDimensionv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14checkDimensionvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14checkDimensionv, .-_Z14checkDimensionv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grid:(%d,%d,%d)\n"
.LC1:
.string "block:(%d,%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %r8d
movl $1, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $3, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z33__device_stub__Z14checkDimensionvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14checkDimensionv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14checkDimensionv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkDimension(){
printf("threadIdx:(%d,%d,%d), blockIdx:(%d,%d,%d),blockDim:(%d,%d,%d),gridDim:(%d,%d,%d)\n",
threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
int main(){
// 数据总量
int nElem = 6;
dim3 block(3);
dim3 grid((nElem + block.x - 1)/block.x);
printf("grid:(%d,%d,%d)\n",grid.x,grid.y,grid.z);
printf("block:(%d,%d,%d)\n",block.x,block.y,block.z);
checkDimension<<<grid,block>>>();
// reset device before exit;
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkDimension(){
printf("threadIdx:(%d,%d,%d), blockIdx:(%d,%d,%d),blockDim:(%d,%d,%d),gridDim:(%d,%d,%d)\n",
threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
int main(){
// 数据总量
int nElem = 6;
dim3 block(3);
dim3 grid((nElem + block.x - 1)/block.x);
printf("grid:(%d,%d,%d)\n",grid.x,grid.y,grid.z);
printf("block:(%d,%d,%d)\n",block.x,block.y,block.z);
checkDimension<<<grid,block>>>();
// reset device before exit;
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkDimension(){
printf("threadIdx:(%d,%d,%d), blockIdx:(%d,%d,%d),blockDim:(%d,%d,%d),gridDim:(%d,%d,%d)\n",
threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,
gridDim.x,gridDim.y,gridDim.z);
}
int main(){
// 数据总量
int nElem = 6;
dim3 block(3);
dim3 grid((nElem + block.x - 1)/block.x);
printf("grid:(%d,%d,%d)\n",grid.x,grid.y,grid.z);
printf("block:(%d,%d,%d)\n",block.x,block.y,block.z);
checkDimension<<<grid,block>>>();
// reset device before exit;
hipDeviceReset();
return 0;
} | .text
.file "checkDimension.hip"
.globl _Z29__device_stub__checkDimensionv # -- Begin function _Z29__device_stub__checkDimensionv
.p2align 4, 0x90
.type _Z29__device_stub__checkDimensionv,@function
_Z29__device_stub__checkDimensionv: # @_Z29__device_stub__checkDimensionv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14checkDimensionv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__checkDimensionv, .Lfunc_end0-_Z29__device_stub__checkDimensionv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $2, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14checkDimensionv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14checkDimensionv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14checkDimensionv,@object # @_Z14checkDimensionv
.section .rodata,"a",@progbits
.globl _Z14checkDimensionv
.p2align 3, 0x0
_Z14checkDimensionv:
.quad _Z29__device_stub__checkDimensionv
.size _Z14checkDimensionv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid:(%d,%d,%d)\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block:(%d,%d,%d)\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14checkDimensionv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__checkDimensionv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14checkDimensionv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014a5b7_00000000-6_checkDimension.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14checkDimensionvv
.type _Z33__device_stub__Z14checkDimensionvv, @function
_Z33__device_stub__Z14checkDimensionvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14checkDimensionv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14checkDimensionvv, .-_Z33__device_stub__Z14checkDimensionvv
.globl _Z14checkDimensionv
.type _Z14checkDimensionv, @function
_Z14checkDimensionv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14checkDimensionvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14checkDimensionv, .-_Z14checkDimensionv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grid:(%d,%d,%d)\n"
.LC1:
.string "block:(%d,%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %r8d
movl $1, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $3, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z33__device_stub__Z14checkDimensionvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14checkDimensionv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14checkDimensionv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "checkDimension.hip"
.globl _Z29__device_stub__checkDimensionv # -- Begin function _Z29__device_stub__checkDimensionv
.p2align 4, 0x90
.type _Z29__device_stub__checkDimensionv,@function
_Z29__device_stub__checkDimensionv: # @_Z29__device_stub__checkDimensionv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14checkDimensionv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__checkDimensionv, .Lfunc_end0-_Z29__device_stub__checkDimensionv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $2, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14checkDimensionv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14checkDimensionv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14checkDimensionv,@object # @_Z14checkDimensionv
.section .rodata,"a",@progbits
.globl _Z14checkDimensionv
.p2align 3, 0x0
_Z14checkDimensionv:
.quad _Z29__device_stub__checkDimensionv
.size _Z14checkDimensionv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid:(%d,%d,%d)\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block:(%d,%d,%d)\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14checkDimensionv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__checkDimensionv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14checkDimensionv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sleepKernel(double* cycles, int64_t waitCycles) {
extern __shared__ int s[];
long long int start = clock64();
for (;;) {
auto total = clock64() - start;
if (total >= waitCycles) { break; }
}
*cycles = (double(clock64() - start));
} | code for sm_80
Function : _Z11sleepKernelPdl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0020*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fe40000015000 */
/*0030*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*0040*/ IADD3 R0, P0, -R2, R4, RZ ; /* 0x0000000402007210 */
/* 0x000fca0007f1e1ff */
/*0050*/ IMAD.X R4, R5, 0x1, ~R3, P0 ; /* 0x0000000105047824 */
/* 0x000fe200000e0e03 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.AND.EX P0, PT, R4, c[0x0][0x16c], PT, P0 ; /* 0x00005b0004007a0c */
/* 0x000fda0003f06300 */
/*0080*/ @!P0 BRA 0x30 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0090*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*00a0*/ IADD3 R2, P0, -R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe20007f1e1ff */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3.X R3, ~R3, R5, RZ, P0, !PT ; /* 0x0000000503037210 */
/* 0x000fe400007fe5ff */
/*00d0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fc80000000f00 */
/*00e0*/ I2F.F64.S64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e240000301c00 */
/*00f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sleepKernel(double* cycles, int64_t waitCycles) {
extern __shared__ int s[];
long long int start = clock64();
for (;;) {
auto total = clock64() - start;
if (total >= waitCycles) { break; }
}
*cycles = (double(clock64() - start));
} | .file "tmpxft_001410e5_00000000-6_sleepKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11sleepKernelPdlPdl
.type _Z32__device_stub__Z11sleepKernelPdlPdl, @function
_Z32__device_stub__Z11sleepKernelPdlPdl:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11sleepKernelPdl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11sleepKernelPdlPdl, .-_Z32__device_stub__Z11sleepKernelPdlPdl
.globl _Z11sleepKernelPdl
.type _Z11sleepKernelPdl, @function
_Z11sleepKernelPdl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11sleepKernelPdlPdl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11sleepKernelPdl, .-_Z11sleepKernelPdl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sleepKernelPdl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sleepKernelPdl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sleepKernel(double* cycles, int64_t waitCycles) {
extern __shared__ int s[];
long long int start = clock64();
for (;;) {
auto total = clock64() - start;
if (total >= waitCycles) { break; }
}
*cycles = (double(clock64() - start));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sleepKernel(double* cycles, int64_t waitCycles) {
extern __shared__ int s[];
long long int start = clock64();
for (;;) {
auto total = clock64() - start;
if (total >= waitCycles) { break; }
}
*cycles = (double(clock64() - start));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sleepKernel(double* cycles, int64_t waitCycles) {
extern __shared__ int s[];
long long int start = clock64();
for (;;) {
auto total = clock64() - start;
if (total >= waitCycles) { break; }
}
*cycles = (double(clock64() - start));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sleepKernelPdl
.globl _Z11sleepKernelPdl
.p2align 8
.type _Z11sleepKernelPdl,@function
_Z11sleepKernelPdl:
s_load_b64 s[2:3], s[0:1], 0x8
s_getreg_b32 s4, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s5, 0
.LBB0_1:
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_u32 s6, s6, s4
s_subb_u32 s7, 0, s5
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s6, s[6:7], s[2:3]
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_1
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_load_b64 s[0:1], s[0:1], 0x0
s_sub_u32 s2, s2, s4
s_subb_u32 s3, 0, s5
v_cvt_f64_u32_e32 v[2:3], s2
v_cvt_f64_i32_e32 v[0:1], s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[0:1], v[0:1], 32
v_add_f64 v[0:1], v[0:1], v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sleepKernelPdl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sleepKernelPdl, .Lfunc_end0-_Z11sleepKernelPdl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sleepKernelPdl
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11sleepKernelPdl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sleepKernel(double* cycles, int64_t waitCycles) {
extern __shared__ int s[];
long long int start = clock64();
for (;;) {
auto total = clock64() - start;
if (total >= waitCycles) { break; }
}
*cycles = (double(clock64() - start));
} | .text
.file "sleepKernel.hip"
.globl _Z26__device_stub__sleepKernelPdl # -- Begin function _Z26__device_stub__sleepKernelPdl
.p2align 4, 0x90
.type _Z26__device_stub__sleepKernelPdl,@function
_Z26__device_stub__sleepKernelPdl: # @_Z26__device_stub__sleepKernelPdl
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11sleepKernelPdl, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__sleepKernelPdl, .Lfunc_end0-_Z26__device_stub__sleepKernelPdl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sleepKernelPdl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sleepKernelPdl,@object # @_Z11sleepKernelPdl
.section .rodata,"a",@progbits
.globl _Z11sleepKernelPdl
.p2align 3, 0x0
_Z11sleepKernelPdl:
.quad _Z26__device_stub__sleepKernelPdl
.size _Z11sleepKernelPdl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sleepKernelPdl"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sleepKernelPdl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sleepKernelPdl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11sleepKernelPdl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0020*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fe40000015000 */
/*0030*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*0040*/ IADD3 R0, P0, -R2, R4, RZ ; /* 0x0000000402007210 */
/* 0x000fca0007f1e1ff */
/*0050*/ IMAD.X R4, R5, 0x1, ~R3, P0 ; /* 0x0000000105047824 */
/* 0x000fe200000e0e03 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.AND.EX P0, PT, R4, c[0x0][0x16c], PT, P0 ; /* 0x00005b0004007a0c */
/* 0x000fda0003f06300 */
/*0080*/ @!P0 BRA 0x30 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0090*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*00a0*/ IADD3 R2, P0, -R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe20007f1e1ff */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3.X R3, ~R3, R5, RZ, P0, !PT ; /* 0x0000000503037210 */
/* 0x000fe400007fe5ff */
/*00d0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fc80000000f00 */
/*00e0*/ I2F.F64.S64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e240000301c00 */
/*00f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sleepKernelPdl
.globl _Z11sleepKernelPdl
.p2align 8
.type _Z11sleepKernelPdl,@function
_Z11sleepKernelPdl:
s_load_b64 s[2:3], s[0:1], 0x8
s_getreg_b32 s4, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s5, 0
.LBB0_1:
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_u32 s6, s6, s4
s_subb_u32 s7, 0, s5
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s6, s[6:7], s[2:3]
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_1
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_load_b64 s[0:1], s[0:1], 0x0
s_sub_u32 s2, s2, s4
s_subb_u32 s3, 0, s5
v_cvt_f64_u32_e32 v[2:3], s2
v_cvt_f64_i32_e32 v[0:1], s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[0:1], v[0:1], 32
v_add_f64 v[0:1], v[0:1], v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sleepKernelPdl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sleepKernelPdl, .Lfunc_end0-_Z11sleepKernelPdl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sleepKernelPdl
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11sleepKernelPdl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001410e5_00000000-6_sleepKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11sleepKernelPdlPdl
.type _Z32__device_stub__Z11sleepKernelPdlPdl, @function
_Z32__device_stub__Z11sleepKernelPdlPdl:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11sleepKernelPdl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11sleepKernelPdlPdl, .-_Z32__device_stub__Z11sleepKernelPdlPdl
.globl _Z11sleepKernelPdl
.type _Z11sleepKernelPdl, @function
_Z11sleepKernelPdl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11sleepKernelPdlPdl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11sleepKernelPdl, .-_Z11sleepKernelPdl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sleepKernelPdl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sleepKernelPdl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sleepKernel.hip"
.globl _Z26__device_stub__sleepKernelPdl # -- Begin function _Z26__device_stub__sleepKernelPdl
.p2align 4, 0x90
.type _Z26__device_stub__sleepKernelPdl,@function
_Z26__device_stub__sleepKernelPdl: # @_Z26__device_stub__sleepKernelPdl
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11sleepKernelPdl, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__sleepKernelPdl, .Lfunc_end0-_Z26__device_stub__sleepKernelPdl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sleepKernelPdl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sleepKernelPdl,@object # @_Z11sleepKernelPdl
.section .rodata,"a",@progbits
.globl _Z11sleepKernelPdl
.p2align 3, 0x0
_Z11sleepKernelPdl:
.quad _Z26__device_stub__sleepKernelPdl
.size _Z11sleepKernelPdl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sleepKernelPdl"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sleepKernelPdl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sleepKernelPdl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include <math.h>
#include<sys/time.h>
__global__ void MatrixTranspose(float *a,float *b,int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
int odx= iy*nx + ix;
if((ix<nx)&&(iy<ny)){
b[odx]=a[idx];
}
}
__global__ void MatrixMul(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int sum = 0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void MatAdd(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]+B[idx];
}
}
__global__ void Mul(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]*B[idx];
}
}
__global__ void div(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]/B[idx];
}
}
__global__ void MatSub(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]-B[idx];
}
}
double getTimeStamp(){
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) tv.tv_usec/1000000+ tv.tv_sec;
}
struct matStruct{
float *m;
int x;
int y;
};
typedef struct matStruct matrix;
matrix setup_matrix(int x,int y)
{
matrix p;
p.m= (float *)malloc(x*y*sizeof(float *));
p.x=x;
p.y=y;
return p;
}
matrix transpose(matrix A){
matrix C;
C=setup_matrix(A.y,A.x);
float *d_A, *d_C;
cudaMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
cudaMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
cudaMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), cudaMemcpyHostToDevice );
dim3 block(32,32);
dim3 grid(1,1);
MatrixTranspose<<<grid,block>>>(d_A,d_C,A.x,A.y);
cudaMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), cudaMemcpyDeviceToHost);
return C;
}
matrix matmul(matrix A, matrix B){
if ((A.y==B.x))
{ matrix C;
C=setup_matrix(A.x,B.y);
float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
cudaMalloc((void **) &d_B, ((B.x*B.y)*sizeof(float)));
cudaMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
cudaMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, (B.x*B.y)*sizeof(float), cudaMemcpyHostToDevice );
printf("%d %d\n",C.x,C.y);
dim3 block(32,32);
dim3 grid(1,1);
MatrixMul<<<grid,block>>>(d_A,d_B,d_C,A.x,A.y,B.y);
cudaMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix add_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatAdd<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix multiply(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
Mul<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix sub_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatSub<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix divide(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
div<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
int main( int argc, char *argv[])
{
if (argc !=3){
printf("Error: wrong number of args\n");
exit(0);
}
int nx= atoi(argv[1]);
int ny = atoi( argv[2]);
matrix a1,b1,c1;
a1=setup_matrix(3,3);
b1=setup_matrix(3,6);
for(int i=0; i<a1.x; i++)
{for(int j=0;j<a1.y;j++)
{a1.m[a1.y*i+j]=2;
printf("%f ",a1.m[a1.y*i+j]);
}
printf("\n");
}
for(int i=0; i<b1.x; i++)
{for(int j=0;j<b1.y;j++)
{b1.m[b1.y*i+j]=1;
printf("%f ",b1.m[b1.y*i+j]);
}
printf("\n");
}
c1=matmul(a1,b1);
for(int i=0; i<c1.x; i++)
{for(int j=0;j<c1.y;j++)
{printf("%f ",c1.m[c1.y*i+j]);
}
printf("\n");
}
} | .file "tmpxft_0001cf5e_00000000-6_phase1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12getTimeStampv
.type _Z12getTimeStampv, @function
_Z12getTimeStampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12getTimeStampv, .-_Z12getTimeStampv
.globl _Z12setup_matrixii
.type _Z12setup_matrixii, @function
_Z12setup_matrixii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
imull %esi, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
salq $32, %rbp
movl %ebx, %edx
orq %rbp, %rdx
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12setup_matrixii, .-_Z12setup_matrixii
.globl _Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii
.type _Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii, @function
_Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixTransposePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii, .-_Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii
.globl _Z15MatrixTransposePfS_ii
.type _Z15MatrixTransposePfS_ii, @function
_Z15MatrixTransposePfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z15MatrixTransposePfS_ii, .-_Z15MatrixTransposePfS_ii
.globl _Z9transpose9matStruct
.type _Z9transpose9matStruct, @function
_Z9transpose9matStruct:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, (%rsp)
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, 12(%rsp)
movq %rsi, %rbx
sarq $32, %rbx
movl %ebx, %r14d
movl %ebx, %edi
call _Z12setup_matrixii
movq %rax, %r13
movq %rdx, %rbp
movq %rdx, %r12
sarq $32, %r12
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %r12d, %r15d
imull %ebp, %r15d
movslq %r15d, %r15
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
salq $32, %r12
movl %ebp, %edx
orq %r12, %rdx
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movq %r13, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %r14d, %ecx
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z39__device_stub__Z15MatrixTransposePfS_iiPfS_ii
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9transpose9matStruct, .-_Z9transpose9matStruct
.globl _Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii
.type _Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii, @function
_Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii:
.LFB2092:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9MatrixMulPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii, .-_Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii
.globl _Z9MatrixMulPfS_S_iii
.type _Z9MatrixMulPfS_S_iii, @function
_Z9MatrixMulPfS_S_iii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z9MatrixMulPfS_S_iii, .-_Z9MatrixMulPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Error:Vector Sum failed incompatible sizes"
.text
.globl _Z6matmul9matStructS_
.type _Z6matmul9matStructS_, @function
_Z6matmul9matStructS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, (%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %esi, %r14d
movq %rsi, %r12
sarq $32, %r12
movq %rcx, %r13
sarq $32, %r13
cmpl %ecx, %r12d
je .L37
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movl %r14d, %edi
call _Z12setup_matrixii
.L34:
movq 104(%rsp), %rcx
subq %fs:40, %rcx
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq %rsi, %rbp
movq %rcx, %rbx
movl %r13d, %esi
movl %r14d, %edi
call _Z12setup_matrixii
movq %rax, 40(%rsp)
movl %edx, 32(%rsp)
movq %rdx, 16(%rsp)
movq %rdx, %r15
sarq $32, %r15
movl %r15d, 36(%rsp)
imull %r12d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 16(%rsp), %eax
imull %r15d, %eax
cltq
salq $2, %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl 32(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
movl $2, %ecx
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq 40(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
salq $32, %r15
movl 16(%rsp), %edx
orq %r15, %rdx
jmp .L34
.L39:
movl %r13d, %r9d
movl %r12d, %r8d
movl %r14d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z9MatrixMulPfS_S_iiiPfS_S_iii
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z6matmul9matStructS_, .-_Z6matmul9matStructS_
.section .rodata.str1.1
.LC3:
.string "Error: wrong number of args\n"
.LC6:
.string "%f "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
cmpl $3, %edi
je .L41
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L41:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $3, %esi
movl $3, %edi
call _Z12setup_matrixii
movq %rax, 16(%rsp)
movq %rdx, %r15
movq %rdx, 48(%rsp)
movl %edx, 8(%rsp)
movq %rdx, %rbx
sarq $32, %rbx
movl %ebx, (%rsp)
movl $6, %esi
movl $3, %edi
call _Z12setup_matrixii
movq %rax, 24(%rsp)
movq %rdx, %rax
movq %rdx, 40(%rsp)
movl %edx, 32(%rsp)
sarq $32, %rax
movq %rax, 56(%rsp)
movl %eax, 4(%rsp)
testl %r15d, %r15d
jle .L42
movl %ebx, 36(%rsp)
movl $0, %r15d
movl $0, %r14d
movl .LC4(%rip), %r13d
leaq .LC6(%rip), %r12
jmp .L43
.L45:
movslq %r15d, %rdx
movq 16(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq (%rsp), %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L44:
movl %r13d, (%rbx)
movsd .LC5(%rip), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L44
.L46:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
movl 36(%rsp), %eax
addl %eax, %r15d
movl 8(%rsp), %eax
cmpl %eax, %r14d
je .L42
.L43:
cmpl $0, (%rsp)
jg .L45
jmp .L46
.L42:
cmpl $0, 40(%rsp)
jle .L47
movl 56(%rsp), %eax
movl %eax, (%rsp)
movl $0, %r15d
movl $0, %r14d
movl .LC8(%rip), %r13d
leaq .LC6(%rip), %r12
jmp .L48
.L50:
movslq %r15d, %rdx
movq 24(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq 4(%rsp), %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L49:
movl %r13d, (%rbx)
movsd .LC9(%rip), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L49
.L51:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
movl (%rsp), %eax
addl %eax, %r15d
movl 32(%rsp), %eax
cmpl %eax, %r14d
je .L47
.L48:
cmpl $0, 4(%rsp)
jg .L50
jmp .L51
.L47:
movq 24(%rsp), %rdx
movq 40(%rsp), %rcx
movq 16(%rsp), %rdi
movq 48(%rsp), %rsi
call _Z6matmul9matStructS_
movq %rax, %r12
movl %edx, (%rsp)
movq %rdx, %rax
sarq $32, %rax
movl %eax, 4(%rsp)
testl %edx, %edx
jle .L52
movl %eax, 32(%rsp)
movl $0, %r15d
movl $0, %r14d
cltq
movq %rax, 8(%rsp)
leaq .LC6(%rip), %r13
jmp .L53
.L55:
movslq %r15d, %rbp
leaq 0(,%rbp,4), %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
salq $2, %rbp
.L54:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L54
.L56:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
movl 32(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, (%rsp)
je .L52
.L53:
cmpl $0, 4(%rsp)
jg .L55
jmp .L56
.L52:
movl $0, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size main, .-main
.globl _Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii
.type _Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatAddPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii
.globl _Z6MatAddPfS_S_ii
.type _Z6MatAddPfS_S_ii, @function
_Z6MatAddPfS_S_ii:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z6MatAddPfS_S_ii, .-_Z6MatAddPfS_S_ii
.globl _Z7add_mat9matStructS_
.type _Z7add_mat9matStructS_, @function
_Z7add_mat9matStructS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %esi, %r15d
movq %rsi, %r14
sarq $32, %r14
cmpq %rcx, %rsi
je .L75
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
.L72:
movq 72(%rsp), %rcx
subq %fs:40, %rcx
jne .L76
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
movq %rdi, %r13
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
movq %rax, %rbp
movq %rdx, 8(%rsp)
movl %r15d, %r12d
imull %r14d, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 48(%rsp)
movl %r14d, 52(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L71:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rax
movq 8(%rsp), %rdx
jmp .L72
.L77:
movl %r14d, %r8d
movl %r15d, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z6MatAddPfS_S_iiPfS_S_ii
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7add_mat9matStructS_, .-_Z7add_mat9matStructS_
.globl _Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii
.type _Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii, @function
_Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L82
.L78:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L83
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3MulPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L78
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii, .-_Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii
.globl _Z3MulPfS_S_ii
.type _Z3MulPfS_S_ii, @function
_Z3MulPfS_S_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z3MulPfS_S_ii, .-_Z3MulPfS_S_ii
.globl _Z8multiply9matStructS_
.type _Z8multiply9matStructS_, @function
_Z8multiply9matStructS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %esi, %r15d
movq %rsi, %r14
sarq $32, %r14
cmpq %rcx, %rsi
je .L92
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
.L89:
movq 72(%rsp), %rcx
subq %fs:40, %rcx
jne .L93
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
movq %rdi, %r13
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
movq %rax, %rbp
movq %rdx, 8(%rsp)
movl %r15d, %r12d
imull %r14d, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 48(%rsp)
movl %r14d, 52(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L88:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rax
movq 8(%rsp), %rdx
jmp .L89
.L94:
movl %r14d, %r8d
movl %r15d, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z3MulPfS_S_iiPfS_S_ii
jmp .L88
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z8multiply9matStructS_, .-_Z8multiply9matStructS_
.globl _Z28__device_stub__Z3divPfS_S_iiPfS_S_ii
.type _Z28__device_stub__Z3divPfS_S_iiPfS_S_ii, @function
_Z28__device_stub__Z3divPfS_S_iiPfS_S_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L99
.L95:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L100
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L99:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3divPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L95
.L100:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z28__device_stub__Z3divPfS_S_iiPfS_S_ii, .-_Z28__device_stub__Z3divPfS_S_iiPfS_S_ii
.globl _Z3divPfS_S_ii
.type _Z3divPfS_S_ii, @function
_Z3divPfS_S_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3divPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z3divPfS_S_ii, .-_Z3divPfS_S_ii
.globl _Z6divide9matStructS_
.type _Z6divide9matStructS_, @function
_Z6divide9matStructS_:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %esi, %r15d
movq %rsi, %r14
sarq $32, %r14
cmpq %rcx, %rsi
je .L109
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
.L106:
movq 72(%rsp), %rcx
subq %fs:40, %rcx
jne .L110
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
movq %rdi, %r13
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
movq %rax, %rbp
movq %rdx, 8(%rsp)
movl %r15d, %r12d
imull %r14d, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 48(%rsp)
movl %r14d, 52(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L111
.L105:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rax
movq 8(%rsp), %rdx
jmp .L106
.L111:
movl %r14d, %r8d
movl %r15d, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z3divPfS_S_iiPfS_S_ii
jmp .L105
.L110:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z6divide9matStructS_, .-_Z6divide9matStructS_
.globl _Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii
.type _Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L116
.L112:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L117
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L116:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatSubPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L112
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii
.globl _Z6MatSubPfS_S_ii
.type _Z6MatSubPfS_S_ii, @function
_Z6MatSubPfS_S_ii:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z6MatSubPfS_S_ii, .-_Z6MatSubPfS_S_ii
.globl _Z7sub_mat9matStructS_
.type _Z7sub_mat9matStructS_, @function
_Z7sub_mat9matStructS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %esi, %r15d
movq %rsi, %r14
sarq $32, %r14
cmpq %rcx, %rsi
je .L126
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
.L123:
movq 72(%rsp), %rcx
subq %fs:40, %rcx
jne .L127
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L126:
.cfi_restore_state
movq %rdi, %r13
movl %r14d, %esi
movl %r15d, %edi
call _Z12setup_matrixii
movq %rax, %rbp
movq %rdx, 8(%rsp)
movl %r15d, %r12d
imull %r14d, %r12d
sall $2, %r12d
movslq %r12d, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 48(%rsp)
movl %r14d, 52(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L128
.L122:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rax
movq 8(%rsp), %rdx
jmp .L123
.L128:
movl %r14d, %r8d
movl %r15d, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z6MatSubPfS_S_iiPfS_S_ii
jmp .L122
.L127:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z7sub_mat9matStructS_, .-_Z7sub_mat9matStructS_
.section .rodata.str1.1
.LC10:
.string "_Z6MatSubPfS_S_ii"
.LC11:
.string "_Z3divPfS_S_ii"
.LC12:
.string "_Z3MulPfS_S_ii"
.LC13:
.string "_Z6MatAddPfS_S_ii"
.LC14:
.string "_Z9MatrixMulPfS_S_iii"
.LC15:
.string "_Z15MatrixTransposePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatSubPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z3divPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3MulPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MatrixMulPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixTransposePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.set .LC4,.LC5+4
.align 8
.LC5:
.long 0
.long 1073741824
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1065353216
.section .rodata.cst8
.align 8
.LC9:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include <math.h>
#include<sys/time.h>
__global__ void MatrixTranspose(float *a,float *b,int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
int odx= iy*nx + ix;
if((ix<nx)&&(iy<ny)){
b[odx]=a[idx];
}
}
__global__ void MatrixMul(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int sum = 0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void MatAdd(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]+B[idx];
}
}
__global__ void Mul(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]*B[idx];
}
}
__global__ void div(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]/B[idx];
}
}
__global__ void MatSub(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]-B[idx];
}
}
double getTimeStamp(){
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) tv.tv_usec/1000000+ tv.tv_sec;
}
struct matStruct{
float *m;
int x;
int y;
};
typedef struct matStruct matrix;
matrix setup_matrix(int x,int y)
{
matrix p;
p.m= (float *)malloc(x*y*sizeof(float *));
p.x=x;
p.y=y;
return p;
}
matrix transpose(matrix A){
matrix C;
C=setup_matrix(A.y,A.x);
float *d_A, *d_C;
cudaMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
cudaMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
cudaMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), cudaMemcpyHostToDevice );
dim3 block(32,32);
dim3 grid(1,1);
MatrixTranspose<<<grid,block>>>(d_A,d_C,A.x,A.y);
cudaMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), cudaMemcpyDeviceToHost);
return C;
}
matrix matmul(matrix A, matrix B){
if ((A.y==B.x))
{ matrix C;
C=setup_matrix(A.x,B.y);
float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
cudaMalloc((void **) &d_B, ((B.x*B.y)*sizeof(float)));
cudaMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
cudaMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, (B.x*B.y)*sizeof(float), cudaMemcpyHostToDevice );
printf("%d %d\n",C.x,C.y);
dim3 block(32,32);
dim3 grid(1,1);
MatrixMul<<<grid,block>>>(d_A,d_B,d_C,A.x,A.y,B.y);
cudaMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix add_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatAdd<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix multiply(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
Mul<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix sub_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatSub<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix divide(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
cudaError_t status3 = cudaMallocHost((void**)&h_dC, bytes);
cudaMalloc((void **) &d_A, bytes);
cudaMalloc((void **) &d_B, bytes);
cudaMalloc((void **) &d_C,bytes);
cudaMemcpy(d_A,A.m, bytes, cudaMemcpyHostToDevice );
cudaMemcpy(d_B,B.m, bytes, cudaMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
div<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
cudaDeviceSynchronize();
cudaMemcpy(C.m,d_C,bytes, cudaMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
int main( int argc, char *argv[])
{
if (argc !=3){
printf("Error: wrong number of args\n");
exit(0);
}
int nx= atoi(argv[1]);
int ny = atoi( argv[2]);
matrix a1,b1,c1;
a1=setup_matrix(3,3);
b1=setup_matrix(3,6);
for(int i=0; i<a1.x; i++)
{for(int j=0;j<a1.y;j++)
{a1.m[a1.y*i+j]=2;
printf("%f ",a1.m[a1.y*i+j]);
}
printf("\n");
}
for(int i=0; i<b1.x; i++)
{for(int j=0;j<b1.y;j++)
{b1.m[b1.y*i+j]=1;
printf("%f ",b1.m[b1.y*i+j]);
}
printf("\n");
}
c1=matmul(a1,b1);
for(int i=0; i<c1.x; i++)
{for(int j=0;j<c1.y;j++)
{printf("%f ",c1.m[c1.y*i+j]);
}
printf("\n");
}
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include <math.h>
#include<sys/time.h>
__global__ void MatrixTranspose(float *a,float *b,int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
int odx= iy*nx + ix;
if((ix<nx)&&(iy<ny)){
b[odx]=a[idx];
}
}
__global__ void MatrixMul(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int sum = 0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void MatAdd(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]+B[idx];
}
}
__global__ void Mul(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]*B[idx];
}
}
__global__ void div(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]/B[idx];
}
}
__global__ void MatSub(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]-B[idx];
}
}
double getTimeStamp(){
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) tv.tv_usec/1000000+ tv.tv_sec;
}
struct matStruct{
float *m;
int x;
int y;
};
typedef struct matStruct matrix;
matrix setup_matrix(int x,int y)
{
matrix p;
p.m= (float *)malloc(x*y*sizeof(float *));
p.x=x;
p.y=y;
return p;
}
matrix transpose(matrix A){
matrix C;
C=setup_matrix(A.y,A.x);
float *d_A, *d_C;
hipMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
hipMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
hipMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), hipMemcpyHostToDevice );
dim3 block(32,32);
dim3 grid(1,1);
MatrixTranspose<<<grid,block>>>(d_A,d_C,A.x,A.y);
hipMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), hipMemcpyDeviceToHost);
return C;
}
matrix matmul(matrix A, matrix B){
if ((A.y==B.x))
{ matrix C;
C=setup_matrix(A.x,B.y);
float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
hipMalloc((void **) &d_B, ((B.x*B.y)*sizeof(float)));
hipMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
hipMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, (B.x*B.y)*sizeof(float), hipMemcpyHostToDevice );
printf("%d %d\n",C.x,C.y);
dim3 block(32,32);
dim3 grid(1,1);
MatrixMul<<<grid,block>>>(d_A,d_B,d_C,A.x,A.y,B.y);
hipMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix add_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatAdd<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix multiply(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
Mul<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix sub_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatSub<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix divide(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
div<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
int main( int argc, char *argv[])
{
if (argc !=3){
printf("Error: wrong number of args\n");
exit(0);
}
int nx= atoi(argv[1]);
int ny = atoi( argv[2]);
matrix a1,b1,c1;
a1=setup_matrix(3,3);
b1=setup_matrix(3,6);
for(int i=0; i<a1.x; i++)
{for(int j=0;j<a1.y;j++)
{a1.m[a1.y*i+j]=2;
printf("%f ",a1.m[a1.y*i+j]);
}
printf("\n");
}
for(int i=0; i<b1.x; i++)
{for(int j=0;j<b1.y;j++)
{b1.m[b1.y*i+j]=1;
printf("%f ",b1.m[b1.y*i+j]);
}
printf("\n");
}
c1=matmul(a1,b1);
for(int i=0; i<c1.x; i++)
{for(int j=0;j<c1.y;j++)
{printf("%f ",c1.m[c1.y*i+j]);
}
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include <math.h>
#include<sys/time.h>
__global__ void MatrixTranspose(float *a,float *b,int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
int odx= iy*nx + ix;
if((ix<nx)&&(iy<ny)){
b[odx]=a[idx];
}
}
__global__ void MatrixMul(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int sum = 0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void MatAdd(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]+B[idx];
}
}
__global__ void Mul(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]*B[idx];
}
}
__global__ void div(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]/B[idx];
}
}
__global__ void MatSub(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]-B[idx];
}
}
double getTimeStamp(){
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) tv.tv_usec/1000000+ tv.tv_sec;
}
struct matStruct{
float *m;
int x;
int y;
};
typedef struct matStruct matrix;
matrix setup_matrix(int x,int y)
{
matrix p;
p.m= (float *)malloc(x*y*sizeof(float *));
p.x=x;
p.y=y;
return p;
}
matrix transpose(matrix A){
matrix C;
C=setup_matrix(A.y,A.x);
float *d_A, *d_C;
hipMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
hipMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
hipMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), hipMemcpyHostToDevice );
dim3 block(32,32);
dim3 grid(1,1);
MatrixTranspose<<<grid,block>>>(d_A,d_C,A.x,A.y);
hipMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), hipMemcpyDeviceToHost);
return C;
}
matrix matmul(matrix A, matrix B){
if ((A.y==B.x))
{ matrix C;
C=setup_matrix(A.x,B.y);
float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
hipMalloc((void **) &d_B, ((B.x*B.y)*sizeof(float)));
hipMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
hipMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, (B.x*B.y)*sizeof(float), hipMemcpyHostToDevice );
printf("%d %d\n",C.x,C.y);
dim3 block(32,32);
dim3 grid(1,1);
MatrixMul<<<grid,block>>>(d_A,d_B,d_C,A.x,A.y,B.y);
hipMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix add_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatAdd<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix multiply(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
Mul<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix sub_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatSub<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix divide(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
div<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
int main( int argc, char *argv[])
{
if (argc !=3){
printf("Error: wrong number of args\n");
exit(0);
}
int nx= atoi(argv[1]);
int ny = atoi( argv[2]);
matrix a1,b1,c1;
a1=setup_matrix(3,3);
b1=setup_matrix(3,6);
for(int i=0; i<a1.x; i++)
{for(int j=0;j<a1.y;j++)
{a1.m[a1.y*i+j]=2;
printf("%f ",a1.m[a1.y*i+j]);
}
printf("\n");
}
for(int i=0; i<b1.x; i++)
{for(int j=0;j<b1.y;j++)
{b1.m[b1.y*i+j]=1;
printf("%f ",b1.m[b1.y*i+j]);
}
printf("\n");
}
c1=matmul(a1,b1);
for(int i=0; i<c1.x; i++)
{for(int j=0;j<c1.y;j++)
{printf("%f ",c1.m[c1.y*i+j]);
}
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixTransposePfS_ii
.globl _Z15MatrixTransposePfS_ii
.p2align 8
.type _Z15MatrixTransposePfS_ii,@function
_Z15MatrixTransposePfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixTransposePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixTransposePfS_ii, .Lfunc_end0-_Z15MatrixTransposePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9MatrixMulPfS_S_iii
.globl _Z9MatrixMulPfS_S_iii
.p2align 8
.type _Z9MatrixMulPfS_S_iii,@function
_Z9MatrixMulPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_7
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v6, v6
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
s_cbranch_scc0 .LBB1_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v6
s_branch .LBB1_6
.LBB1_5:
v_mov_b32_e32 v2, 0
.LBB1_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MatrixMulPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9MatrixMulPfS_S_iii, .Lfunc_end1-_Z9MatrixMulPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6MatAddPfS_S_ii
.globl _Z6MatAddPfS_S_ii
.p2align 8
.type _Z6MatAddPfS_S_ii,@function
_Z6MatAddPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatAddPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6MatAddPfS_S_ii, .Lfunc_end2-_Z6MatAddPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3MulPfS_S_ii
.globl _Z3MulPfS_S_ii
.p2align 8
.type _Z3MulPfS_S_ii,@function
_Z3MulPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3MulPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3MulPfS_S_ii, .Lfunc_end3-_Z3MulPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3divPfS_S_ii
.globl _Z3divPfS_S_ii
.p2align 8
.type _Z3divPfS_S_ii,@function
_Z3divPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB4_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3divPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z3divPfS_S_ii, .Lfunc_end4-_Z3divPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6MatSubPfS_S_ii
.globl _Z6MatSubPfS_S_ii
.p2align 8
.type _Z6MatSubPfS_S_ii,@function
_Z6MatSubPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB5_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatSubPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z6MatSubPfS_S_ii, .Lfunc_end5-_Z6MatSubPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixTransposePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixTransposePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MatrixMulPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MatrixMulPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include <math.h>
#include<sys/time.h>
__global__ void MatrixTranspose(float *a,float *b,int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
int odx= iy*nx + ix;
if((ix<nx)&&(iy<ny)){
b[odx]=a[idx];
}
}
__global__ void MatrixMul(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int sum = 0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
__global__ void MatAdd(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]+B[idx];
}
}
__global__ void Mul(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]*B[idx];
}
}
__global__ void div(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]/B[idx];
}
}
__global__ void MatSub(float *A, float *B, float *C, int nx, int ny){
int ix = threadIdx.x+ blockIdx.x*blockDim.x;
int iy = threadIdx.y+ blockIdx.y*blockDim.y;
int idx = ix*ny + iy;
if((ix<nx)&&(iy<ny)){
C[idx]=A[idx]-B[idx];
}
}
double getTimeStamp(){
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) tv.tv_usec/1000000+ tv.tv_sec;
}
struct matStruct{
float *m;
int x;
int y;
};
typedef struct matStruct matrix;
matrix setup_matrix(int x,int y)
{
matrix p;
p.m= (float *)malloc(x*y*sizeof(float *));
p.x=x;
p.y=y;
return p;
}
matrix transpose(matrix A){
matrix C;
C=setup_matrix(A.y,A.x);
float *d_A, *d_C;
hipMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
hipMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
hipMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), hipMemcpyHostToDevice );
dim3 block(32,32);
dim3 grid(1,1);
MatrixTranspose<<<grid,block>>>(d_A,d_C,A.x,A.y);
hipMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), hipMemcpyDeviceToHost);
return C;
}
matrix matmul(matrix A, matrix B){
if ((A.y==B.x))
{ matrix C;
C=setup_matrix(A.x,B.y);
float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, ((A.x*A.y)*sizeof(float)));
hipMalloc((void **) &d_B, ((B.x*B.y)*sizeof(float)));
hipMalloc((void **) &d_C, ((C.x*C.y)*sizeof(float)));
hipMemcpy(d_A,A.m, (A.x*A.y)*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, (B.x*B.y)*sizeof(float), hipMemcpyHostToDevice );
printf("%d %d\n",C.x,C.y);
dim3 block(32,32);
dim3 grid(1,1);
MatrixMul<<<grid,block>>>(d_A,d_B,d_C,A.x,A.y,B.y);
hipMemcpy(C.m,d_C,(C.x*C.y)*sizeof(float), hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix add_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatAdd<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix multiply(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
Mul<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix sub_mat(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
MatSub<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
matrix divide(matrix A, matrix B){
if ((A.x==B.x)&&(A.y==B.y))
{ matrix C;
C=setup_matrix(A.x,A.y);
float *d_A, *d_B, *d_C;
float *h_dC;
int bytes=(A.x*A.y)*sizeof(float);
hipError_t status3 = hipHostMalloc((void**)&h_dC, bytes, hipHostMallocDefault);
hipMalloc((void **) &d_A, bytes);
hipMalloc((void **) &d_B, bytes);
hipMalloc((void **) &d_C,bytes);
hipMemcpy(d_A,A.m, bytes, hipMemcpyHostToDevice );
hipMemcpy(d_B,B.m, bytes, hipMemcpyHostToDevice );
dim3 block(A.x,A.y);
dim3 grid(1,1);
div<<<grid,block>>>(d_A,d_B,d_C, A.x,A.y);
hipDeviceSynchronize();
hipMemcpy(C.m,d_C,bytes, hipMemcpyDeviceToHost);
return C;
}
else{
printf("Error:Vector Sum failed incompatible sizes");
matrix C;
C=setup_matrix(A.x,A.y);
return C;
}
}
int main( int argc, char *argv[])
{
if (argc !=3){
printf("Error: wrong number of args\n");
exit(0);
}
int nx= atoi(argv[1]);
int ny = atoi( argv[2]);
matrix a1,b1,c1;
a1=setup_matrix(3,3);
b1=setup_matrix(3,6);
for(int i=0; i<a1.x; i++)
{for(int j=0;j<a1.y;j++)
{a1.m[a1.y*i+j]=2;
printf("%f ",a1.m[a1.y*i+j]);
}
printf("\n");
}
for(int i=0; i<b1.x; i++)
{for(int j=0;j<b1.y;j++)
{b1.m[b1.y*i+j]=1;
printf("%f ",b1.m[b1.y*i+j]);
}
printf("\n");
}
c1=matmul(a1,b1);
for(int i=0; i<c1.x; i++)
{for(int j=0;j<c1.y;j++)
{printf("%f ",c1.m[c1.y*i+j]);
}
printf("\n");
}
} | .text
.file "phase1.hip"
.globl _Z30__device_stub__MatrixTransposePfS_ii # -- Begin function _Z30__device_stub__MatrixTransposePfS_ii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixTransposePfS_ii,@function
_Z30__device_stub__MatrixTransposePfS_ii: # @_Z30__device_stub__MatrixTransposePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixTransposePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixTransposePfS_ii, .Lfunc_end0-_Z30__device_stub__MatrixTransposePfS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__MatrixMulPfS_S_iii # -- Begin function _Z24__device_stub__MatrixMulPfS_S_iii
.p2align 4, 0x90
.type _Z24__device_stub__MatrixMulPfS_S_iii,@function
_Z24__device_stub__MatrixMulPfS_S_iii: # @_Z24__device_stub__MatrixMulPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9MatrixMulPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z24__device_stub__MatrixMulPfS_S_iii, .Lfunc_end1-_Z24__device_stub__MatrixMulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__MatAddPfS_S_ii # -- Begin function _Z21__device_stub__MatAddPfS_S_ii
.p2align 4, 0x90
.type _Z21__device_stub__MatAddPfS_S_ii,@function
_Z21__device_stub__MatAddPfS_S_ii: # @_Z21__device_stub__MatAddPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatAddPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z21__device_stub__MatAddPfS_S_ii, .Lfunc_end2-_Z21__device_stub__MatAddPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__MulPfS_S_ii # -- Begin function _Z18__device_stub__MulPfS_S_ii
.p2align 4, 0x90
.type _Z18__device_stub__MulPfS_S_ii,@function
_Z18__device_stub__MulPfS_S_ii: # @_Z18__device_stub__MulPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3MulPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z18__device_stub__MulPfS_S_ii, .Lfunc_end3-_Z18__device_stub__MulPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__divPfS_S_ii # -- Begin function _Z18__device_stub__divPfS_S_ii
.p2align 4, 0x90
.type _Z18__device_stub__divPfS_S_ii,@function
_Z18__device_stub__divPfS_S_ii: # @_Z18__device_stub__divPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3divPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z18__device_stub__divPfS_S_ii, .Lfunc_end4-_Z18__device_stub__divPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__MatSubPfS_S_ii # -- Begin function _Z21__device_stub__MatSubPfS_S_ii
.p2align 4, 0x90
.type _Z21__device_stub__MatSubPfS_S_ii,@function
_Z21__device_stub__MatSubPfS_S_ii: # @_Z21__device_stub__MatSubPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatSubPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z21__device_stub__MatSubPfS_S_ii, .Lfunc_end5-_Z21__device_stub__MatSubPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12getTimeStampv
.LCPI6_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z12getTimeStampv
.p2align 4, 0x90
.type _Z12getTimeStampv,@function
_Z12getTimeStampv: # @_Z12getTimeStampv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI6_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z12getTimeStampv, .Lfunc_end6-_Z12getTimeStampv
.cfi_endproc
# -- End function
.globl _Z12setup_matrixii # -- Begin function _Z12setup_matrixii
.p2align 4, 0x90
.type _Z12setup_matrixii,@function
_Z12setup_matrixii: # @_Z12setup_matrixii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movl %esi, %eax
imull %edi, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
shlq $32, %rbx
movl %ebp, %edx
orq %rbx, %rdx
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z12setup_matrixii, .Lfunc_end7-_Z12setup_matrixii
.cfi_endproc
# -- End function
.globl _Z9transpose9matStruct # -- Begin function _Z9transpose9matStruct
.p2align 4, 0x90
.type _Z9transpose9matStruct,@function
_Z9transpose9matStruct: # @_Z9transpose9matStruct
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r12
movq %rsi, %r13
shrq $32, %r13
movl %r13d, %r14d
imull %ebx, %r14d
shlq $32, %r14
movq %r14, %rdi
sarq $29, %rdi
callq malloc
movq %rax, %r15
sarq $30, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebx, 12(%rsp)
movl %r13d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixTransposePfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_2:
shlq $32, %rbx
orq %r13, %rbx
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r15, %rax
movq %rbx, %rdx
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z9transpose9matStruct, .Lfunc_end8-_Z9transpose9matStruct
.cfi_endproc
# -- End function
.globl _Z6matmul9matStructS_ # -- Begin function _Z6matmul9matStructS_
.p2align 4, 0x90
.type _Z6matmul9matStructS_,@function
_Z6matmul9matStructS_: # @_Z6matmul9matStructS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r14
movq %rsi, %rbp
movq %rsi, %rbx
shrq $32, %rbx
cmpl %r14d, %ebx
jne .LBB9_4
# %bb.1:
movq %r14, %r12
shrq $32, %r12
movl %r12d, %r15d
imull %ebp, %r15d
shlq $32, %r15
movq %rdi, 48(%rsp) # 8-byte Spill
movq %r15, %rdi
sarq $29, %rdi
movq %rdx, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
imull %r12d, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
sarq $30, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl %ebp, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_3
# %bb.2:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebp, 20(%rsp)
movl %ebx, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9MatrixMulPfS_S_iii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_3:
movq 24(%rsp), %rsi
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rax
jmp .LBB9_5
.LBB9_4:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rbx, %r12
.LBB9_5:
movl %ebp, %ecx
shlq $32, %r12
orq %rcx, %r12
movq %r12, %rdx
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z6matmul9matStructS_, .Lfunc_end9-_Z6matmul9matStructS_
.cfi_endproc
# -- End function
.globl _Z7add_mat9matStructS_ # -- Begin function _Z7add_mat9matStructS_
.p2align 4, 0x90
.type _Z7add_mat9matStructS_,@function
_Z7add_mat9matStructS_: # @_Z7add_mat9matStructS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rsi, %rbp
shrq $32, %rbp
cmpl %ecx, %ebx
jne .LBB10_5
# %bb.1:
shrq $32, %rcx
cmpq %rcx, %rbp
jne .LBB10_5
# %bb.2:
movq %rdx, %r12
movq %rdi, %r13
movq %rbp, %rax
imulq %rbx, %rax
movslq %eax, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
shll $2, %r15d
movslq %r15d, %r15
leaq 160(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6MatAddPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
jmp .LBB10_6
.LBB10_5:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
imull %ebx, %ebp
movslq %ebp, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %r14
.LBB10_6:
movq %r14, %rax
movq %rbx, %rdx
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z7add_mat9matStructS_, .Lfunc_end10-_Z7add_mat9matStructS_
.cfi_endproc
# -- End function
.globl _Z8multiply9matStructS_ # -- Begin function _Z8multiply9matStructS_
.p2align 4, 0x90
.type _Z8multiply9matStructS_,@function
_Z8multiply9matStructS_: # @_Z8multiply9matStructS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rsi, %rbp
shrq $32, %rbp
cmpl %ecx, %ebx
jne .LBB11_5
# %bb.1:
shrq $32, %rcx
cmpq %rcx, %rbp
jne .LBB11_5
# %bb.2:
movq %rdx, %r12
movq %rdi, %r13
movq %rbp, %rax
imulq %rbx, %rax
movslq %eax, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
shll $2, %r15d
movslq %r15d, %r15
leaq 160(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3MulPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB11_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
jmp .LBB11_6
.LBB11_5:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
imull %ebx, %ebp
movslq %ebp, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %r14
.LBB11_6:
movq %r14, %rax
movq %rbx, %rdx
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _Z8multiply9matStructS_, .Lfunc_end11-_Z8multiply9matStructS_
.cfi_endproc
# -- End function
.globl _Z7sub_mat9matStructS_ # -- Begin function _Z7sub_mat9matStructS_
.p2align 4, 0x90
.type _Z7sub_mat9matStructS_,@function
_Z7sub_mat9matStructS_: # @_Z7sub_mat9matStructS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rsi, %rbp
shrq $32, %rbp
cmpl %ecx, %ebx
jne .LBB12_5
# %bb.1:
shrq $32, %rcx
cmpq %rcx, %rbp
jne .LBB12_5
# %bb.2:
movq %rdx, %r12
movq %rdi, %r13
movq %rbp, %rax
imulq %rbx, %rax
movslq %eax, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
shll $2, %r15d
movslq %r15d, %r15
leaq 160(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB12_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6MatSubPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB12_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
jmp .LBB12_6
.LBB12_5:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
imull %ebx, %ebp
movslq %ebp, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %r14
.LBB12_6:
movq %r14, %rax
movq %rbx, %rdx
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size _Z7sub_mat9matStructS_, .Lfunc_end12-_Z7sub_mat9matStructS_
.cfi_endproc
# -- End function
.globl _Z6divide9matStructS_ # -- Begin function _Z6divide9matStructS_
.p2align 4, 0x90
.type _Z6divide9matStructS_,@function
_Z6divide9matStructS_: # @_Z6divide9matStructS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rsi, %rbp
shrq $32, %rbp
cmpl %ecx, %ebx
jne .LBB13_5
# %bb.1:
shrq $32, %rcx
cmpq %rcx, %rbp
jne .LBB13_5
# %bb.2:
movq %rdx, %r12
movq %rdi, %r13
movq %rbp, %rax
imulq %rbx, %rax
movslq %eax, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
shll $2, %r15d
movslq %r15d, %r15
leaq 160(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebx, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3divPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
jmp .LBB13_6
.LBB13_5:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
imull %ebx, %ebp
movslq %ebp, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %r14
.LBB13_6:
movq %r14, %rax
movq %rbx, %rdx
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end13:
.size _Z6divide9matStructS_, .Lfunc_end13-_Z6divide9matStructS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI14_0:
.quad 0x4000000000000000 # double 2
.LCPI14_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB14_16
# %bb.1:
movl $72, %edi
callq malloc
movq %rax, %rbx
movl $144, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB14_2: # %.preheader67
# =>This Loop Header: Depth=1
# Child Loop BB14_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB14_3: # Parent Loop BB14_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%r12,%r13,4) # imm = 0x40000000
movl $.L.str.3, %edi
movsd .LCPI14_0(%rip), %xmm0 # xmm0 = mem[0],zero
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB14_3
# %bb.4: # in Loop: Header=BB14_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r12
cmpq $3, %r15
jne .LBB14_2
# %bb.5: # %.preheader65.preheader
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB14_6: # %.preheader65
# =>This Loop Header: Depth=1
# Child Loop BB14_7 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB14_7: # Parent Loop BB14_6 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%r12,%r13,4) # imm = 0x3F800000
movl $.L.str.3, %edi
movsd .LCPI14_1(%rip), %xmm0 # xmm0 = mem[0],zero
movb $1, %al
callq printf
incq %r13
cmpq $6, %r13
jne .LBB14_7
# %bb.8: # in Loop: Header=BB14_6 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $24, %r12
cmpq $3, %r15
jne .LBB14_6
# %bb.9:
movabsq $12884901891, %rsi # imm = 0x300000003
movabsq $25769803779, %rcx # imm = 0x600000003
movq %rbx, %rdi
movq %r14, %rdx
callq _Z6matmul9matStructS_
movq %rax, (%rsp) # 8-byte Spill
movq %rdx, %r14
testl %r14d, %r14d
jle .LBB14_15
# %bb.10: # %.preheader.lr.ph
movq %r14, %rax
shrq $32, %r14
movl %eax, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB14_11
.p2align 4, 0x90
.LBB14_14: # %._crit_edge
# in Loop: Header=BB14_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %r14d, %r12d
cmpq %r15, %r13
je .LBB14_15
.LBB14_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB14_13 Depth 2
testl %r14d, %r14d
jle .LBB14_14
# %bb.12: # %.lr.ph
# in Loop: Header=BB14_11 Depth=1
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB14_13: # Parent Loop BB14_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB14_13
jmp .LBB14_14
.LBB14_15: # %._crit_edge74
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB14_16:
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end14:
.size main, .Lfunc_end14-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB15_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB15_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixTransposePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MatrixMulPfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddPfS_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3MulPfS_S_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3divPfS_S_ii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatSubPfS_S_ii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end15:
.size __hip_module_ctor, .Lfunc_end15-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB16_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB16_2:
retq
.Lfunc_end16:
.size __hip_module_dtor, .Lfunc_end16-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixTransposePfS_ii,@object # @_Z15MatrixTransposePfS_ii
.section .rodata,"a",@progbits
.globl _Z15MatrixTransposePfS_ii
.p2align 3, 0x0
_Z15MatrixTransposePfS_ii:
.quad _Z30__device_stub__MatrixTransposePfS_ii
.size _Z15MatrixTransposePfS_ii, 8
.type _Z9MatrixMulPfS_S_iii,@object # @_Z9MatrixMulPfS_S_iii
.globl _Z9MatrixMulPfS_S_iii
.p2align 3, 0x0
_Z9MatrixMulPfS_S_iii:
.quad _Z24__device_stub__MatrixMulPfS_S_iii
.size _Z9MatrixMulPfS_S_iii, 8
.type _Z6MatAddPfS_S_ii,@object # @_Z6MatAddPfS_S_ii
.globl _Z6MatAddPfS_S_ii
.p2align 3, 0x0
_Z6MatAddPfS_S_ii:
.quad _Z21__device_stub__MatAddPfS_S_ii
.size _Z6MatAddPfS_S_ii, 8
.type _Z3MulPfS_S_ii,@object # @_Z3MulPfS_S_ii
.globl _Z3MulPfS_S_ii
.p2align 3, 0x0
_Z3MulPfS_S_ii:
.quad _Z18__device_stub__MulPfS_S_ii
.size _Z3MulPfS_S_ii, 8
.type _Z3divPfS_S_ii,@object # @_Z3divPfS_S_ii
.globl _Z3divPfS_S_ii
.p2align 3, 0x0
_Z3divPfS_S_ii:
.quad _Z18__device_stub__divPfS_S_ii
.size _Z3divPfS_S_ii, 8
.type _Z6MatSubPfS_S_ii,@object # @_Z6MatSubPfS_S_ii
.globl _Z6MatSubPfS_S_ii
.p2align 3, 0x0
_Z6MatSubPfS_S_ii:
.quad _Z21__device_stub__MatSubPfS_S_ii
.size _Z6MatSubPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error:Vector Sum failed incompatible sizes"
.size .L.str.1, 43
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixTransposePfS_ii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9MatrixMulPfS_S_iii"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6MatAddPfS_S_ii"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3MulPfS_S_ii"
.size .L__unnamed_4, 15
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z3divPfS_S_ii"
.size .L__unnamed_5, 15
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z6MatSubPfS_S_ii"
.size .L__unnamed_6, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error: wrong number of args"
.size .Lstr, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixTransposePfS_ii
.addrsig_sym _Z24__device_stub__MatrixMulPfS_S_iii
.addrsig_sym _Z21__device_stub__MatAddPfS_S_ii
.addrsig_sym _Z18__device_stub__MulPfS_S_ii
.addrsig_sym _Z18__device_stub__divPfS_S_ii
.addrsig_sym _Z21__device_stub__MatSubPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixTransposePfS_ii
.addrsig_sym _Z9MatrixMulPfS_S_iii
.addrsig_sym _Z6MatAddPfS_S_ii
.addrsig_sym _Z3MulPfS_S_ii
.addrsig_sym _Z3divPfS_S_ii
.addrsig_sym _Z6MatSubPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Checks that cuda compilation does the right thing when passed
// -fcuda-flush-denormals-to-zero. This should be translated to
// -fdenormal-fp-math-f32=preserve-sign
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// CPUFTZ-NOT: -fdenormal-fp-math
// FTZ: "-fdenormal-fp-math-f32=preserve-sign,preserve-sign"
// NOFTZ: "-fdenormal-fp-math=ieee,ieee" | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Checks that cuda compilation does the right thing when passed
// -fcuda-flush-denormals-to-zero. This should be translated to
// -fdenormal-fp-math-f32=preserve-sign
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// CPUFTZ-NOT: -fdenormal-fp-math
// FTZ: "-fdenormal-fp-math-f32=preserve-sign,preserve-sign"
// NOFTZ: "-fdenormal-fp-math=ieee,ieee" | .file "tmpxft_0002a7e5_00000000-6_cuda-flush-denormals-to-zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Checks that cuda compilation does the right thing when passed
// -fcuda-flush-denormals-to-zero. This should be translated to
// -fdenormal-fp-math-f32=preserve-sign
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// CPUFTZ-NOT: -fdenormal-fp-math
// FTZ: "-fdenormal-fp-math-f32=preserve-sign,preserve-sign"
// NOFTZ: "-fdenormal-fp-math=ieee,ieee" | #include <hip/hip_runtime.h>
// Checks that cuda compilation does the right thing when passed
// -fcuda-flush-denormals-to-zero. This should be translated to
// -fdenormal-fp-math-f32=preserve-sign
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// CPUFTZ-NOT: -fdenormal-fp-math
// FTZ: "-fdenormal-fp-math-f32=preserve-sign,preserve-sign"
// NOFTZ: "-fdenormal-fp-math=ieee,ieee" |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Checks that cuda compilation does the right thing when passed
// -fcuda-flush-denormals-to-zero. This should be translated to
// -fdenormal-fp-math-f32=preserve-sign
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// CPUFTZ-NOT: -fdenormal-fp-math
// FTZ: "-fdenormal-fp-math-f32=preserve-sign,preserve-sign"
// NOFTZ: "-fdenormal-fp-math=ieee,ieee" | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Checks that cuda compilation does the right thing when passed
// -fcuda-flush-denormals-to-zero. This should be translated to
// -fdenormal-fp-math-f32=preserve-sign
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_20 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fcuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=FTZ %s
// RUN: %clang -no-canonical-prefixes -### -target x86_64-linux-gnu -c -march=haswell--cuda-gpu-arch=sm_10 -fno-cuda-flush-denormals-to-zero -nocudainc -nocudalib %s 2>&1 | FileCheck -check-prefix=NOFTZ %s
// CPUFTZ-NOT: -fdenormal-fp-math
// FTZ: "-fdenormal-fp-math-f32=preserve-sign,preserve-sign"
// NOFTZ: "-fdenormal-fp-math=ieee,ieee" | .text
.file "cuda-flush-denormals-to-zero.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002a7e5_00000000-6_cuda-flush-denormals-to-zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-flush-denormals-to-zero.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
int N = 1024;
int THREADS_PER_BLOCK = 512;
// Running one thread in each block
__global__ void add_blocks(int *a, int *b, int *c)
{
// blockIdx.x gives each block ID
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Running multiple threads in one block
__global__ void add_threads(int *a, int *b, int *c)
{
/* threadIdx.x gives the thread ID in each block */
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
// Running multiple threads in multiple blocks. While doing this seems unecessary, in some cases we need threads since they have communication (__shared__ variables) and
// synchronization (__syncthreads()) mechanisms
__global__ void add_threads_blocks(int *a, int *b, int *c, int n)
{
// 'index' is the index of each global thread in the device
int index = threadIdx.x * blockIdx.x * threadIdx.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(void)
{
int *a, *b, *c; // Host (CPU) copies of a, b, c
int *d_a, *d_b, *d_c; // Device (GPU) copies of a, b, c
size_t size = N * sizeof(int);
int max = 100, min = 0;
srand(1);
// Allocate memory in device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
// Allocate memory in host
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// Allocate random data in vectors a and b (inside host)
for(int i = 0; i < N; ++i)
{
a[i] = rand() % (max + 1 - min) + min;
b[i] = rand() % (max + 1 - min) + min;
}
// Copy data to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add_blocks<<<N,1>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
add_threads<<<1,N>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
// Launch add() kernel on device with N threads in N blocks
add_threads_blocks<<<(N + (THREADS_PER_BLOCK - 1)) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
for(int i = 0; i < N; ++i)
printf("A[%d]=%d, B[%d]=%d,C[%d]=%d\n", i, a[i], i, b[i], i, c[i]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z18add_threads_blocksPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R3, UR4, RZ ; /* 0x0000000403007c24 */
/* 0x001fc8000f8e02ff */
/*0040*/ IMAD R0, R0, R3, RZ ; /* 0x0000000300007224 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11add_threadsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_blocksPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
int N = 1024;
int THREADS_PER_BLOCK = 512;
// Running one thread in each block
__global__ void add_blocks(int *a, int *b, int *c)
{
// blockIdx.x gives each block ID
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Running multiple threads in one block
__global__ void add_threads(int *a, int *b, int *c)
{
/* threadIdx.x gives the thread ID in each block */
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
// Running multiple threads in multiple blocks. While doing this seems unecessary, in some cases we need threads since they have communication (__shared__ variables) and
// synchronization (__syncthreads()) mechanisms
__global__ void add_threads_blocks(int *a, int *b, int *c, int n)
{
// 'index' is the index of each global thread in the device
int index = threadIdx.x * blockIdx.x * threadIdx.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(void)
{
int *a, *b, *c; // Host (CPU) copies of a, b, c
int *d_a, *d_b, *d_c; // Device (GPU) copies of a, b, c
size_t size = N * sizeof(int);
int max = 100, min = 0;
srand(1);
// Allocate memory in device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
// Allocate memory in host
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// Allocate random data in vectors a and b (inside host)
for(int i = 0; i < N; ++i)
{
a[i] = rand() % (max + 1 - min) + min;
b[i] = rand() % (max + 1 - min) + min;
}
// Copy data to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add_blocks<<<N,1>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
add_threads<<<1,N>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
// Launch add() kernel on device with N threads in N blocks
add_threads_blocks<<<(N + (THREADS_PER_BLOCK - 1)) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
for(int i = 0; i < N; ++i)
printf("A[%d]=%d, B[%d]=%d,C[%d]=%d\n", i, a[i], i, b[i], i, c[i]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0013960a_00000000-6_mat_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
.type _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_, @function
_Z34__device_stub__Z10add_blocksPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_blocksPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_, .-_Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
.globl _Z10add_blocksPiS_S_
.type _Z10add_blocksPiS_S_, @function
_Z10add_blocksPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10add_blocksPiS_S_, .-_Z10add_blocksPiS_S_
.globl _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
.type _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_, @function
_Z35__device_stub__Z11add_threadsPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11add_threadsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_, .-_Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
.globl _Z11add_threadsPiS_S_
.type _Z11add_threadsPiS_S_, @function
_Z11add_threadsPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11add_threadsPiS_S_, .-_Z11add_threadsPiS_S_
.globl _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
.type _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i, @function
_Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18add_threads_blocksPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i, .-_Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
.globl _Z18add_threads_blocksPiS_S_i
.type _Z18add_threads_blocksPiS_S_i, @function
_Z18add_threads_blocksPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z18add_threads_blocksPiS_S_i, .-_Z18add_threads_blocksPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A[%d]=%d, B[%d]=%d,C[%d]=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq N(%rip), %r14
salq $2, %r14
movl $1, %edi
call srand@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
cmpl $0, N(%rip)
jle .L28
movl $0, %ebx
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpl %ebx, N(%rip)
jg .L29
.L28:
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl N(%rip), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L30:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl N(%rip), %edx
testl %edx, %edx
jle .L31
movl $0, %eax
.L32:
addl $1, %eax
cmpl %edx, %eax
jne .L32
.L31:
movl %edx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L33:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl N(%rip), %edx
testl %edx, %edx
jle .L34
movl $0, %eax
.L35:
addl $1, %eax
cmpl %edx, %eax
jne .L35
.L34:
movl THREADS_PER_BLOCK(%rip), %ecx
movl %ecx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L36:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl N(%rip), %edx
testl %edx, %edx
jle .L37
movl $0, %eax
.L38:
addl $1, %eax
cmpl %edx, %eax
jne .L38
movl $0, %ebx
leaq .LC0(%rip), %r14
.L39:
movl %ebx, %edx
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %eax
pushq %rax
.cfi_def_cfa_offset 120
pushq %rbx
.cfi_def_cfa_offset 128
movl 0(%rbp,%rbx,4), %r9d
movl %ebx, %r8d
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 112
cmpl %ebx, N(%rip)
jg .L39
.L37:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
jmp .L30
.L48:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
jmp .L33
.L49:
movl N(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
jmp .L36
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z18add_threads_blocksPiS_S_i"
.LC2:
.string "_Z11add_threadsPiS_S_"
.LC3:
.string "_Z10add_blocksPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18add_threads_blocksPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11add_threadsPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_blocksPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl THREADS_PER_BLOCK
.data
.align 4
.type THREADS_PER_BLOCK, @object
.size THREADS_PER_BLOCK, 4
THREADS_PER_BLOCK:
.long 512
.globl N
.align 4
.type N, @object
.size N, 4
N:
.long 1024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
int N = 1024;
int THREADS_PER_BLOCK = 512;
// Running one thread in each block
__global__ void add_blocks(int *a, int *b, int *c)
{
// blockIdx.x gives each block ID
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Running multiple threads in one block
__global__ void add_threads(int *a, int *b, int *c)
{
/* threadIdx.x gives the thread ID in each block */
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
// Running multiple threads in multiple blocks. While doing this seems unecessary, in some cases we need threads since they have communication (__shared__ variables) and
// synchronization (__syncthreads()) mechanisms
__global__ void add_threads_blocks(int *a, int *b, int *c, int n)
{
// 'index' is the index of each global thread in the device
int index = threadIdx.x * blockIdx.x * threadIdx.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(void)
{
int *a, *b, *c; // Host (CPU) copies of a, b, c
int *d_a, *d_b, *d_c; // Device (GPU) copies of a, b, c
size_t size = N * sizeof(int);
int max = 100, min = 0;
srand(1);
// Allocate memory in device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
// Allocate memory in host
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// Allocate random data in vectors a and b (inside host)
for(int i = 0; i < N; ++i)
{
a[i] = rand() % (max + 1 - min) + min;
b[i] = rand() % (max + 1 - min) + min;
}
// Copy data to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add_blocks<<<N,1>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
add_threads<<<1,N>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
// Launch add() kernel on device with N threads in N blocks
add_threads_blocks<<<(N + (THREADS_PER_BLOCK - 1)) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
for(int i = 0; i < N; ++i)
printf("A[%d]=%d, B[%d]=%d,C[%d]=%d\n", i, a[i], i, b[i], i, c[i]);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
int N = 1024;
int THREADS_PER_BLOCK = 512;
// Running one thread in each block
__global__ void add_blocks(int *a, int *b, int *c)
{
// blockIdx.x gives each block ID
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Running multiple threads in one block
__global__ void add_threads(int *a, int *b, int *c)
{
/* threadIdx.x gives the thread ID in each block */
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
// Running multiple threads in multiple blocks. While doing this seems unecessary, in some cases we need threads since they have communication (__shared__ variables) and
// synchronization (__syncthreads()) mechanisms
__global__ void add_threads_blocks(int *a, int *b, int *c, int n)
{
// 'index' is the index of each global thread in the device
int index = threadIdx.x * blockIdx.x * threadIdx.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(void)
{
int *a, *b, *c; // Host (CPU) copies of a, b, c
int *d_a, *d_b, *d_c; // Device (GPU) copies of a, b, c
size_t size = N * sizeof(int);
int max = 100, min = 0;
srand(1);
// Allocate memory in device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
// Allocate memory in host
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// Allocate random data in vectors a and b (inside host)
for(int i = 0; i < N; ++i)
{
a[i] = rand() % (max + 1 - min) + min;
b[i] = rand() % (max + 1 - min) + min;
}
// Copy data to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add_blocks<<<N,1>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
add_threads<<<1,N>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
// Launch add() kernel on device with N threads in N blocks
add_threads_blocks<<<(N + (THREADS_PER_BLOCK - 1)) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
for(int i = 0; i < N; ++i)
printf("A[%d]=%d, B[%d]=%d,C[%d]=%d\n", i, a[i], i, b[i], i, c[i]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
int N = 1024;
int THREADS_PER_BLOCK = 512;
// Running one thread in each block
__global__ void add_blocks(int *a, int *b, int *c)
{
// blockIdx.x gives each block ID
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Running multiple threads in one block
__global__ void add_threads(int *a, int *b, int *c)
{
/* threadIdx.x gives the thread ID in each block */
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
// Running multiple threads in multiple blocks. While doing this seems unecessary, in some cases we need threads since they have communication (__shared__ variables) and
// synchronization (__syncthreads()) mechanisms
__global__ void add_threads_blocks(int *a, int *b, int *c, int n)
{
// 'index' is the index of each global thread in the device
int index = threadIdx.x * blockIdx.x * threadIdx.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(void)
{
int *a, *b, *c; // Host (CPU) copies of a, b, c
int *d_a, *d_b, *d_c; // Device (GPU) copies of a, b, c
size_t size = N * sizeof(int);
int max = 100, min = 0;
srand(1);
// Allocate memory in device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
// Allocate memory in host
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// Allocate random data in vectors a and b (inside host)
for(int i = 0; i < N; ++i)
{
a[i] = rand() % (max + 1 - min) + min;
b[i] = rand() % (max + 1 - min) + min;
}
// Copy data to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add_blocks<<<N,1>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
add_threads<<<1,N>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
// Launch add() kernel on device with N threads in N blocks
add_threads_blocks<<<(N + (THREADS_PER_BLOCK - 1)) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
for(int i = 0; i < N; ++i)
printf("A[%d]=%d, B[%d]=%d,C[%d]=%d\n", i, a[i], i, b[i], i, c[i]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_blocksPiS_S_
.globl _Z10add_blocksPiS_S_
.p2align 8
.type _Z10add_blocksPiS_S_,@function
_Z10add_blocksPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_blocksPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_blocksPiS_S_, .Lfunc_end0-_Z10add_blocksPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11add_threadsPiS_S_
.globl _Z11add_threadsPiS_S_
.p2align 8
.type _Z11add_threadsPiS_S_,@function
_Z11add_threadsPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11add_threadsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11add_threadsPiS_S_, .Lfunc_end1-_Z11add_threadsPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18add_threads_blocksPiS_S_i
.globl _Z18add_threads_blocksPiS_S_i
.p2align 8
.type _Z18add_threads_blocksPiS_S_i,@function
_Z18add_threads_blocksPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_mul_lo_u32 v1, v0, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18add_threads_blocksPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18add_threads_blocksPiS_S_i, .Lfunc_end2-_Z18add_threads_blocksPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_blocksPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10add_blocksPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11add_threadsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11add_threadsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18add_threads_blocksPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18add_threads_blocksPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
int N = 1024;
int THREADS_PER_BLOCK = 512;
// Running one thread in each block
__global__ void add_blocks(int *a, int *b, int *c)
{
// blockIdx.x gives each block ID
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
// Running multiple threads in one block
__global__ void add_threads(int *a, int *b, int *c)
{
/* threadIdx.x gives the thread ID in each block */
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
}
// Running multiple threads in multiple blocks. While doing this seems unecessary, in some cases we need threads since they have communication (__shared__ variables) and
// synchronization (__syncthreads()) mechanisms
__global__ void add_threads_blocks(int *a, int *b, int *c, int n)
{
// 'index' is the index of each global thread in the device
int index = threadIdx.x * blockIdx.x * threadIdx.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(void)
{
int *a, *b, *c; // Host (CPU) copies of a, b, c
int *d_a, *d_b, *d_c; // Device (GPU) copies of a, b, c
size_t size = N * sizeof(int);
int max = 100, min = 0;
srand(1);
// Allocate memory in device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
// Allocate memory in host
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// Allocate random data in vectors a and b (inside host)
for(int i = 0; i < N; ++i)
{
a[i] = rand() % (max + 1 - min) + min;
b[i] = rand() % (max + 1 - min) + min;
}
// Copy data to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add_blocks<<<N,1>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
add_threads<<<1,N>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
// Launch add() kernel on device with N threads in N blocks
add_threads_blocks<<<(N + (THREADS_PER_BLOCK - 1)) / THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// Check if everything is alright
for(int i = 0; i < N; ++i)
assert(c[i] == a[i] + b[i]);
for(int i = 0; i < N; ++i)
printf("A[%d]=%d, B[%d]=%d,C[%d]=%d\n", i, a[i], i, b[i], i, c[i]);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "mat_sum.hip"
.globl _Z25__device_stub__add_blocksPiS_S_ # -- Begin function _Z25__device_stub__add_blocksPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_blocksPiS_S_,@function
_Z25__device_stub__add_blocksPiS_S_: # @_Z25__device_stub__add_blocksPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_blocksPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__add_blocksPiS_S_, .Lfunc_end0-_Z25__device_stub__add_blocksPiS_S_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__add_threadsPiS_S_ # -- Begin function _Z26__device_stub__add_threadsPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__add_threadsPiS_S_,@function
_Z26__device_stub__add_threadsPiS_S_: # @_Z26__device_stub__add_threadsPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11add_threadsPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__add_threadsPiS_S_, .Lfunc_end1-_Z26__device_stub__add_threadsPiS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__add_threads_blocksPiS_S_i # -- Begin function _Z33__device_stub__add_threads_blocksPiS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__add_threads_blocksPiS_S_i,@function
_Z33__device_stub__add_threads_blocksPiS_S_i: # @_Z33__device_stub__add_threads_blocksPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18add_threads_blocksPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__add_threads_blocksPiS_S_i, .Lfunc_end2-_Z33__device_stub__add_threads_blocksPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq N(%rip), %r12
shlq $2, %r12
movl $1, %edi
callq srand
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
cmpl $0, N(%rip)
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
incq %r13
movslq N(%rip), %rax
cmpq %rax, %r13
jl .LBB3_2
.LBB3_3: # %._crit_edge
movabsq $4294967296, %r13 # imm = 0x100000000
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl N(%rip), %edi
orq %r13, %rdi
leaq 1(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_blocksPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl N(%rip), %edx
orq %r13, %rdx
leaq 1(%r13), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11add_threadsPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl N(%rip), %eax
movl THREADS_PER_BLOCK(%rip), %ecx
addl %ecx, %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
orq %r13, %rax
orq %r13, %rcx
movq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl N(%rip), %esi
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl %esi, 108(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 108(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18add_threads_blocksPiS_S_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # %.preheader
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, N(%rip)
jle .LBB3_12
# %bb.10: # %.lr.ph94.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_11: # %.lr.ph94
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %r8d
movl (%r15,%r12,4), %r10d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str, %edi
movl %r12d, %esi
movl %r12d, %ecx
movl %r12d, %r9d
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
incq %r12
movslq N(%rip), %rax
cmpq %rax, %r12
jl .LBB3_11
.LBB3_12: # %._crit_edge95
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_blocksPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11add_threadsPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18add_threads_blocksPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 1024 # 0x400
.size N, 4
.type THREADS_PER_BLOCK,@object # @THREADS_PER_BLOCK
.globl THREADS_PER_BLOCK
.p2align 2, 0x0
THREADS_PER_BLOCK:
.long 512 # 0x200
.size THREADS_PER_BLOCK, 4
.type _Z10add_blocksPiS_S_,@object # @_Z10add_blocksPiS_S_
.section .rodata,"a",@progbits
.globl _Z10add_blocksPiS_S_
.p2align 3, 0x0
_Z10add_blocksPiS_S_:
.quad _Z25__device_stub__add_blocksPiS_S_
.size _Z10add_blocksPiS_S_, 8
.type _Z11add_threadsPiS_S_,@object # @_Z11add_threadsPiS_S_
.globl _Z11add_threadsPiS_S_
.p2align 3, 0x0
_Z11add_threadsPiS_S_:
.quad _Z26__device_stub__add_threadsPiS_S_
.size _Z11add_threadsPiS_S_, 8
.type _Z18add_threads_blocksPiS_S_i,@object # @_Z18add_threads_blocksPiS_S_i
.globl _Z18add_threads_blocksPiS_S_i
.p2align 3, 0x0
_Z18add_threads_blocksPiS_S_i:
.quad _Z33__device_stub__add_threads_blocksPiS_S_i
.size _Z18add_threads_blocksPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[%d]=%d, B[%d]=%d,C[%d]=%d\n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_blocksPiS_S_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11add_threadsPiS_S_"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18add_threads_blocksPiS_S_i"
.size .L__unnamed_3, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_blocksPiS_S_
.addrsig_sym _Z26__device_stub__add_threadsPiS_S_
.addrsig_sym _Z33__device_stub__add_threads_blocksPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_blocksPiS_S_
.addrsig_sym _Z11add_threadsPiS_S_
.addrsig_sym _Z18add_threads_blocksPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18add_threads_blocksPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R3, UR4, RZ ; /* 0x0000000403007c24 */
/* 0x001fc8000f8e02ff */
/*0040*/ IMAD R0, R0, R3, RZ ; /* 0x0000000300007224 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11add_threadsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_blocksPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_blocksPiS_S_
.globl _Z10add_blocksPiS_S_
.p2align 8
.type _Z10add_blocksPiS_S_,@function
_Z10add_blocksPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_blocksPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_blocksPiS_S_, .Lfunc_end0-_Z10add_blocksPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11add_threadsPiS_S_
.globl _Z11add_threadsPiS_S_
.p2align 8
.type _Z11add_threadsPiS_S_,@function
_Z11add_threadsPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11add_threadsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11add_threadsPiS_S_, .Lfunc_end1-_Z11add_threadsPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18add_threads_blocksPiS_S_i
.globl _Z18add_threads_blocksPiS_S_i
.p2align 8
.type _Z18add_threads_blocksPiS_S_i,@function
_Z18add_threads_blocksPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_mul_lo_u32 v1, v0, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18add_threads_blocksPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18add_threads_blocksPiS_S_i, .Lfunc_end2-_Z18add_threads_blocksPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_blocksPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10add_blocksPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11add_threadsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11add_threadsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18add_threads_blocksPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18add_threads_blocksPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013960a_00000000-6_mat_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
.type _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_, @function
_Z34__device_stub__Z10add_blocksPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_blocksPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_, .-_Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
.globl _Z10add_blocksPiS_S_
.type _Z10add_blocksPiS_S_, @function
_Z10add_blocksPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10add_blocksPiS_S_, .-_Z10add_blocksPiS_S_
.globl _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
.type _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_, @function
_Z35__device_stub__Z11add_threadsPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11add_threadsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_, .-_Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
.globl _Z11add_threadsPiS_S_
.type _Z11add_threadsPiS_S_, @function
_Z11add_threadsPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11add_threadsPiS_S_, .-_Z11add_threadsPiS_S_
.globl _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
.type _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i, @function
_Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18add_threads_blocksPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i, .-_Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
.globl _Z18add_threads_blocksPiS_S_i
.type _Z18add_threads_blocksPiS_S_i, @function
_Z18add_threads_blocksPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z18add_threads_blocksPiS_S_i, .-_Z18add_threads_blocksPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A[%d]=%d, B[%d]=%d,C[%d]=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq N(%rip), %r14
salq $2, %r14
movl $1, %edi
call srand@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
cmpl $0, N(%rip)
jle .L28
movl $0, %ebx
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpl %ebx, N(%rip)
jg .L29
.L28:
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl N(%rip), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L30:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl N(%rip), %edx
testl %edx, %edx
jle .L31
movl $0, %eax
.L32:
addl $1, %eax
cmpl %edx, %eax
jne .L32
.L31:
movl %edx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L33:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl N(%rip), %edx
testl %edx, %edx
jle .L34
movl $0, %eax
.L35:
addl $1, %eax
cmpl %edx, %eax
jne .L35
.L34:
movl THREADS_PER_BLOCK(%rip), %ecx
movl %ecx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L36:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl N(%rip), %edx
testl %edx, %edx
jle .L37
movl $0, %eax
.L38:
addl $1, %eax
cmpl %edx, %eax
jne .L38
movl $0, %ebx
leaq .LC0(%rip), %r14
.L39:
movl %ebx, %edx
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %eax
pushq %rax
.cfi_def_cfa_offset 120
pushq %rbx
.cfi_def_cfa_offset 128
movl 0(%rbp,%rbx,4), %r9d
movl %ebx, %r8d
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 112
cmpl %ebx, N(%rip)
jg .L39
.L37:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10add_blocksPiS_S_PiS_S_
jmp .L30
.L48:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z11add_threadsPiS_S_PiS_S_
jmp .L33
.L49:
movl N(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z18add_threads_blocksPiS_S_iPiS_S_i
jmp .L36
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z18add_threads_blocksPiS_S_i"
.LC2:
.string "_Z11add_threadsPiS_S_"
.LC3:
.string "_Z10add_blocksPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18add_threads_blocksPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11add_threadsPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_blocksPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl THREADS_PER_BLOCK
.data
.align 4
.type THREADS_PER_BLOCK, @object
.size THREADS_PER_BLOCK, 4
THREADS_PER_BLOCK:
.long 512
.globl N
.align 4
.type N, @object
.size N, 4
N:
.long 1024
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_sum.hip"
.globl _Z25__device_stub__add_blocksPiS_S_ # -- Begin function _Z25__device_stub__add_blocksPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__add_blocksPiS_S_,@function
_Z25__device_stub__add_blocksPiS_S_: # @_Z25__device_stub__add_blocksPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_blocksPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__add_blocksPiS_S_, .Lfunc_end0-_Z25__device_stub__add_blocksPiS_S_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__add_threadsPiS_S_ # -- Begin function _Z26__device_stub__add_threadsPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__add_threadsPiS_S_,@function
_Z26__device_stub__add_threadsPiS_S_: # @_Z26__device_stub__add_threadsPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11add_threadsPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__add_threadsPiS_S_, .Lfunc_end1-_Z26__device_stub__add_threadsPiS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__add_threads_blocksPiS_S_i # -- Begin function _Z33__device_stub__add_threads_blocksPiS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__add_threads_blocksPiS_S_i,@function
_Z33__device_stub__add_threads_blocksPiS_S_i: # @_Z33__device_stub__add_threads_blocksPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18add_threads_blocksPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z33__device_stub__add_threads_blocksPiS_S_i, .Lfunc_end2-_Z33__device_stub__add_threads_blocksPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq N(%rip), %r12
shlq $2, %r12
movl $1, %edi
callq srand
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
cmpl $0, N(%rip)
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
incq %r13
movslq N(%rip), %rax
cmpq %rax, %r13
jl .LBB3_2
.LBB3_3: # %._crit_edge
movabsq $4294967296, %r13 # imm = 0x100000000
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl N(%rip), %edi
orq %r13, %rdi
leaq 1(%r13), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_blocksPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl N(%rip), %edx
orq %r13, %rdx
leaq 1(%r13), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11add_threadsPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl N(%rip), %eax
movl THREADS_PER_BLOCK(%rip), %ecx
addl %ecx, %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
orq %r13, %rax
orq %r13, %rcx
movq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl N(%rip), %esi
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl %esi, 108(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 108(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18add_threads_blocksPiS_S_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # %.preheader
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, N(%rip)
jle .LBB3_12
# %bb.10: # %.lr.ph94.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_11: # %.lr.ph94
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %r8d
movl (%r15,%r12,4), %r10d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str, %edi
movl %r12d, %esi
movl %r12d, %ecx
movl %r12d, %r9d
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
incq %r12
movslq N(%rip), %rax
cmpq %rax, %r12
jl .LBB3_11
.LBB3_12: # %._crit_edge95
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_blocksPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11add_threadsPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18add_threads_blocksPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 1024 # 0x400
.size N, 4
.type THREADS_PER_BLOCK,@object # @THREADS_PER_BLOCK
.globl THREADS_PER_BLOCK
.p2align 2, 0x0
THREADS_PER_BLOCK:
.long 512 # 0x200
.size THREADS_PER_BLOCK, 4
.type _Z10add_blocksPiS_S_,@object # @_Z10add_blocksPiS_S_
.section .rodata,"a",@progbits
.globl _Z10add_blocksPiS_S_
.p2align 3, 0x0
_Z10add_blocksPiS_S_:
.quad _Z25__device_stub__add_blocksPiS_S_
.size _Z10add_blocksPiS_S_, 8
.type _Z11add_threadsPiS_S_,@object # @_Z11add_threadsPiS_S_
.globl _Z11add_threadsPiS_S_
.p2align 3, 0x0
_Z11add_threadsPiS_S_:
.quad _Z26__device_stub__add_threadsPiS_S_
.size _Z11add_threadsPiS_S_, 8
.type _Z18add_threads_blocksPiS_S_i,@object # @_Z18add_threads_blocksPiS_S_i
.globl _Z18add_threads_blocksPiS_S_i
.p2align 3, 0x0
_Z18add_threads_blocksPiS_S_i:
.quad _Z33__device_stub__add_threads_blocksPiS_S_i
.size _Z18add_threads_blocksPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[%d]=%d, B[%d]=%d,C[%d]=%d\n"
.size .L.str, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_blocksPiS_S_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11add_threadsPiS_S_"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18add_threads_blocksPiS_S_i"
.size .L__unnamed_3, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_blocksPiS_S_
.addrsig_sym _Z26__device_stub__add_threadsPiS_S_
.addrsig_sym _Z33__device_stub__add_threads_blocksPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_blocksPiS_S_
.addrsig_sym _Z11add_threadsPiS_S_
.addrsig_sym _Z18add_threads_blocksPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
__global__ void hello() {
printf("Hello world from device\n");
}
int main() {
hello<<<1, 1>>>();
cout << "Hello world from host" << endl;
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
__global__ void hello() {
printf("Hello world from device\n");
}
int main() {
hello<<<1, 1>>>();
cout << "Hello world from host" << endl;
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000f42d4_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from host"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
__global__ void hello() {
printf("Hello world from device\n");
}
int main() {
hello<<<1, 1>>>();
cout << "Hello world from host" << endl;
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void hello() {
printf("Hello world from device\n");
}
int main() {
hello<<<1, 1>>>();
cout << "Hello world from host" << endl;
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void hello() {
printf("Hello world from device\n");
}
int main() {
hello<<<1, 1>>>();
cout << "Hello world from host" << endl;
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5hellov
.globl _Z5hellov
.p2align 8
.type _Z5hellov,@function
_Z5hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 25
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5hellov, .Lfunc_end0-_Z5hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello world from device\n"
.size .str, 25
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
__global__ void hello() {
printf("Hello world from device\n");
}
int main() {
hello<<<1, 1>>>();
cout << "Hello world from host" << endl;
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello world from host"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5hellov
.globl _Z5hellov
.p2align 8
.type _Z5hellov,@function
_Z5hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 25
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5hellov, .Lfunc_end0-_Z5hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello world from device\n"
.size .str, 25
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f42d4_00000000-6_hello.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from host"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello world from host"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
long long res[64];
__global__ void fib(long long *res)
{
int idx = threadIdx.x;
res[idx] = (long long)(1.0/sqrt(5.0)*(pow((1+sqrt(5.0))/2.0, idx+1) - pow((1-sqrt(5.0))/2.0, idx+1)) + 0.5);
// printf("%d\n", res[idx]);
}
int main()
{
int n;
long long *gpures;
scanf("%d", &n);
cudaMalloc(&gpures, n*sizeof(long long));
fib<<<1,n>>>(gpures);
cudaMemcpy(res, gpures, n*sizeof(long long), cudaMemcpyDeviceToHost);
cudaFree(gpures);
for (int i = 0; i < n; ++i)
{
printf(i == n-1 ? "%lld\n" : "%lld ", res[i]);
}
return 0;
} | code for sm_80
Function : _Z3fibPx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x120 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0030*/ UMOV UR5, 0x9b97f4a8 ; /* 0x9b97f4a800057882 */
/* 0x000fe40000000000 */
/*0040*/ UMOV UR6, 0x3ff9e377 ; /* 0x3ff9e37700067882 */
/* 0x000fe20000000000 */
/*0050*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x001fc80007ffe0ff */
/*0060*/ I2F.F64 R6, R3 ; /* 0x0000000300067312 */
/* 0x000e240000201c00 */
/*0070*/ LOP3.LUT R0, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007007812 */
/* 0x001fe200078ec0ff */
/*0080*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e0006 */
/*0090*/ LEA.HI R5, R0, 0xfffffc0c, RZ, 0xc ; /* 0xfffffc0c00057811 */
/* 0x000fc800078f60ff */
/*00a0*/ SHF.L.U32 R0, R6.reuse, R5.reuse, RZ ; /* 0x0000000506007219 */
/* 0x0c0fe400000006ff */
/*00b0*/ SHF.L.U64.HI R5, R6, R5, R7.reuse ; /* 0x0000000506057219 */
/* 0x100fe40000010207 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*00d0*/ MOV R0, 0x110 ; /* 0x0000011000007802 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.NE.AND.EX P0, PT, R5, -0x80000000, PT, P0 ; /* 0x800000000500780c */
/* 0x000fe20003f05300 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fce00078e0007 */
/*0100*/ CALL.REL.NOINC 0x530 ; /* 0x0000042000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ DADD R4, R6, c[0x2][0x0] ; /* 0x0080000006047629 */
/* 0x000e220000000000 */
/*0130*/ BSSY B0, 0x250 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0010 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fcc00078e0011 */
/*0160*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x001fc800078ec0ff */
/*0170*/ ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fda0003f25270 */
/*0180*/ @P1 BRA 0x240 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0190*/ DSETP.GTU.AND P1, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f2c200 */
/*01a0*/ @P1 BRA 0x230 ; /* 0x0000008000001947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*01c0*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*01d0*/ ISETP.EQ.AND P1, PT, R0, 0x7ff00000, !P1 ; /* 0x7ff000000000780c */
/* 0x000fda0004f22270 */
/*01e0*/ @!P1 BRA 0x240 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f26270 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0210*/ SEL R9, RZ, 0x7ff00000, !P1 ; /* 0x7ff00000ff097807 */
/* 0x000fe20004800000 */
/*0220*/ BRA 0x240 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0230*/ DADD R8, R6, c[0x2][0x0] ; /* 0x0080000006087629 */
/* 0x00004c0000000000 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BSSY B0, 0x2d0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0260*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0006 */
/*0270*/ MOV R0, 0x2c0 ; /* 0x000002c000007802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0290*/ UMOV UR5, 0x372fe950 ; /* 0x372fe95000057882 */
/* 0x000fe40000000000 */
/*02a0*/ UMOV UR6, 0x3fe3c6ef ; /* 0x3fe3c6ef00067882 */
/* 0x000fe40000000000 */
/*02b0*/ CALL.REL.NOINC 0x530 ; /* 0x0000027000007944 */
/* 0x003fea0003c00000 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ FRND.F64.TRUNC R4, R6 ; /* 0x0000000600047313 */
/* 0x000e22000030d800 */
/*02e0*/ DADD R10, R6, c[0x2][0x8] ; /* 0x00800200060a7629 */
/* 0x000e620000000000 */
/*02f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0300*/ BSSY B0, 0x470 ; /* 0x0000016000007945 */
/* 0x000ff00003800000 */
/*0310*/ LOP3.LUT R10, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0a7812 */
/* 0x002fc800078ec0ff */
/*0320*/ ISETP.NE.AND P2, PT, R10, 0x7ff00000, PT ; /* 0x7ff000000a00780c */
/* 0x000fe20003f45270 */
/*0330*/ DSETP.NEU.AND P1, PT, R4, R6, PT ; /* 0x000000060400722a */
/* 0x0010640003f2d000 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0011 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0010 */
/*0360*/ @!P0 LOP3.LUT R11, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000050b8812 */
/* 0x000fca00078e3cff */
/*0370*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff058224 */
/* 0x000fe400078e000b */
/*0380*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff041424 */
/* 0x002fe400078e00ff */
/*0390*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff051424 */
/* 0x000fe200078e00ff */
/*03a0*/ @P2 BRA 0x460 ; /* 0x000000b000002947 */
/* 0x000fea0003800000 */
/*03b0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*03c0*/ @P0 BRA 0x450 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*03e0*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*03f0*/ ISETP.EQ.AND P0, PT, R0, 0x7ff00000, !P0 ; /* 0x7ff000000000780c */
/* 0x000fda0004702270 */
/*0400*/ @!P0 BRA 0x460 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0410*/ SHF.R.S32.HI R6, RZ, 0x1f, R7 ; /* 0x0000001fff067819 */
/* 0x000fe20000011407 */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0430*/ LOP3.LUT R5, R6, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000006057812 */
/* 0x000fe200078ec0ff */
/*0440*/ BRA 0x460 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0450*/ DADD R4, R6, c[0x2][0x8] ; /* 0x0080020006047629 */
/* 0x00004c0000000000 */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ DADD R4, -R4, R8 ; /* 0x0000000004047229 */
/* 0x002e620000000108 */
/*0480*/ IMAD.MOV.U32 R6, RZ, RZ, -0x3a401227 ; /* 0xc5bfedd9ff067424 */
/* 0x001fe200078e00ff */
/*0490*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*04a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3fdc9f25 ; /* 0x3fdc9f25ff077424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*04c0*/ DFMA R4, R4, R6, 0.5 ; /* 0x3fe000000404742b */
/* 0x002e220000000006 */
/*04d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd200078e0203 */
/*04e0*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x001fe40000000000 */
/*04f0*/ FSEL R5, R5, 1.75, P0 ; /* 0x3fe0000005057808 */
/* 0x000fcc0000000000 */
/*0500*/ F2I.S64.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000030d900 */
/*0510*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ USHF.R.U32.HI UR4, URZ, 0x14, UR6 ; /* 0x000000143f047899 */
/* 0x000fe20008011606 */
/*0540*/ IMAD.U32 R22, RZ, RZ, UR5 ; /* 0x00000005ff167e24 */
/* 0x000fe4000f8e00ff */
/*0550*/ IMAD.U32 R23, RZ, RZ, UR6 ; /* 0x00000006ff177e24 */
/* 0x000fe4000f8e00ff */
/*0560*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0570*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0580*/ IMAD.U32 R14, RZ, RZ, UR5 ; /* 0x00000005ff0e7e24 */
/* 0x000fc4000f8e00ff */
/*0590*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*05a0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff147424 */
/* 0x000fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff157424 */
/* 0x000fcc00078e00ff */
/*05c0*/ @!P1 DMUL R22, R22, 1.80143985094819840000e+16 ; /* 0x4350000016169828 */
/* 0x000e140000000000 */
/*05d0*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, R23 ; /* 0x000000ffff049224 */
/* 0x001fe400078e0017 */
/*05e0*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e9224 */
/* 0x000fc600078e0016 */
/*05f0*/ LOP3.LUT R4, R4, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff04047812 */
/* 0x000fc800078ec0ff */
/*0600*/ LOP3.LUT R15, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff00000040f7812 */
/* 0x000fe200078efcff */
/*0610*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0620*/ @!P1 LEA.HI R4, R23, 0xffffffca, RZ, 0xc ; /* 0xffffffca17049811 */
/* 0x000fe400078f60ff */
/*0630*/ ISETP.GE.U32.AND P2, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f46070 */
/*0640*/ @P2 IADD3 R11, R15, -0x100000, RZ ; /* 0xfff000000f0b2810 */
/* 0x000fca0007ffe0ff */
/*0650*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f2224 */
/* 0x000fcc00078e000b */
/*0660*/ DADD R16, R14, 1 ; /* 0x3ff000000e107429 */
/* 0x000e080000000000 */
/*0670*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*0680*/ MUFU.RCP64H R11, R17 ; /* 0x00000011000b7308 */
/* 0x001e240000001800 */
/*0690*/ DFMA R12, -R16, R10, 1 ; /* 0x3ff00000100c742b */
/* 0x001e0c000000010a */
/*06a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*06b0*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*06c0*/ DMUL R12, R10, R14 ; /* 0x0000000e0a0c7228 */
/* 0x001e0c0000000000 */
/*06d0*/ DFMA R12, R10, R14, R12 ; /* 0x0000000e0a0c722b */
/* 0x001e0c000000000c */
/*06e0*/ DMUL R18, R12, R12 ; /* 0x0000000c0c127228 */
/* 0x001e080000000000 */
/*06f0*/ DADD R16, R14, -R12 ; /* 0x000000000e107229 */
/* 0x000e48000000080c */
/*0700*/ DFMA R20, R18, R20, c[0x2][0x10] ; /* 0x008004001214762b */
/* 0x001e080000000014 */
/*0710*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x002e480000000010 */
/*0720*/ DFMA R20, R18, R20, c[0x2][0x18] ; /* 0x008006001214762b */
/* 0x001e080000000014 */
/*0730*/ DFMA R16, R14, -R12, R16 ; /* 0x8000000c0e10722b */
/* 0x002e480000000010 */
/*0740*/ DFMA R20, R18, R20, c[0x2][0x20] ; /* 0x008008001214762b */
/* 0x001e080000000014 */
/*0750*/ DMUL R10, R10, R16 ; /* 0x000000100a0a7228 */
/* 0x002fc80000000000 */
/*0760*/ DFMA R20, R18, R20, c[0x2][0x28] ; /* 0x00800a001214762b */
/* 0x001e0c0000000014 */
/*0770*/ DFMA R24, R18, R20, c[0x2][0x30] ; /* 0x00800c001218762b */
/* 0x001e080000000014 */
/*0780*/ DMUL R20, R12, R12 ; /* 0x0000000c0c147228 */
/* 0x000fc80000000000 */
/*0790*/ DFMA R24, R18, R24, c[0x2][0x38] ; /* 0x00800e001218762b */
/* 0x001e0c0000000018 */
/*07a0*/ DFMA R14, R18, R24, c[0x2][0x40] ; /* 0x00801000120e762b */
/* 0x001e0c0000000018 */
/*07b0*/ DADD R16, -R14, c[0x2][0x40] ; /* 0x008010000e107629 */
/* 0x001e0c0000000100 */
/*07c0*/ DFMA R24, R18, R24, R16 ; /* 0x000000181218722b */
/* 0x0010640000000010 */
/*07d0*/ IADD3 R19, R11, 0x100000, RZ ; /* 0x001000000b137810 */
/* 0x001fe20007ffe0ff */
/*07e0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000a */
/*07f0*/ DFMA R16, R12, R12, -R20 ; /* 0x0000000c0c10722b */
/* 0x000e080000000814 */
/*0800*/ DADD R24, RZ, R24 ; /* 0x00000000ff187229 */
/* 0x002e480000000018 */
/*0810*/ DFMA R18, R12, R18, R16 ; /* 0x000000120c12722b */
/* 0x001fc80000000010 */
/*0820*/ DMUL R16, R12, R20 ; /* 0x000000140c107228 */
/* 0x000e080000000000 */
/*0830*/ DADD R24, R24, c[0x2][0x48] ; /* 0x0080120018187629 */
/* 0x002fc80000000000 */
/*0840*/ DFMA R22, R12, R20, -R16 ; /* 0x000000140c16722b */
/* 0x001e0c0000000810 */
/*0850*/ DFMA R22, R10, R20, R22 ; /* 0x000000140a16722b */
/* 0x001e080000000016 */
/*0860*/ DADD R20, R14, R24 ; /* 0x000000000e147229 */
/* 0x000e480000000018 */
/*0870*/ DFMA R18, R12, R18, R22 ; /* 0x000000120c12722b */
/* 0x001fc80000000016 */
/*0880*/ DADD R22, R14, -R20 ; /* 0x000000000e167229 */
/* 0x002e080000000814 */
/*0890*/ DMUL R14, R20, R16 ; /* 0x00000010140e7228 */
/* 0x000e480000000000 */
/*08a0*/ DADD R24, R24, R22 ; /* 0x0000000018187229 */
/* 0x001fc80000000016 */
/*08b0*/ DFMA R22, R20, R16, -R14 ; /* 0x000000101416722b */
/* 0x002e0c000000080e */
/*08c0*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x001e0c0000000016 */
/*08d0*/ DFMA R24, R24, R16, R18 ; /* 0x000000101818722b */
/* 0x001e0c0000000012 */
/*08e0*/ DADD R18, R14, R24 ; /* 0x000000000e127229 */
/* 0x001e0c0000000018 */
/*08f0*/ DADD R16, R12, R18 ; /* 0x000000000c107229 */
/* 0x001e080000000012 */
/*0900*/ DADD R14, R14, -R18 ; /* 0x000000000e0e7229 */
/* 0x000e480000000812 */
/*0910*/ DADD R12, R12, -R16 ; /* 0x000000000c0c7229 */
/* 0x001e080000000810 */
/*0920*/ DADD R14, R24, R14 ; /* 0x00000000180e7229 */
/* 0x002fc8000000000e */
/*0930*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x001064000000000c */
/*0940*/ IADD3 R18, R4.reuse, -0x3ff, RZ ; /* 0xfffffc0104127810 */
/* 0x041fe40007ffe0ff */
/*0950*/ @P2 IADD3 R18, R4, -0x3fe, RZ ; /* 0xfffffc0204122810 */
/* 0x000fe20007ffe0ff */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R26 ; /* 0x000000ffff047224 */
/* 0x000fe200078e001a */
/*0970*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x002064000000000c */
/*0980*/ LOP3.LUT R14, R18, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000120e7812 */
/* 0x001fe200078e3cff */
/*0990*/ IMAD.MOV.U32 R15, RZ, RZ, 0x43300000 ; /* 0x43300000ff0f7424 */
/* 0x000fc600078e00ff */
/*09a0*/ DADD R18, R10, R12 ; /* 0x000000000a127229 */
/* 0x002e08000000000c */
/*09b0*/ DADD R12, R14, c[0x2][0x50] ; /* 0x008014000e0c7629 */
/* 0x000fc80000000000 */
/*09c0*/ DADD R14, R16, R18 ; /* 0x00000000100e7229 */
/* 0x001e0c0000000012 */
/*09d0*/ DFMA R10, R12, c[0x2][0x58], R14 ; /* 0x008016000c0a7a2b */
/* 0x001e08000000000e */
/*09e0*/ DADD R16, R16, -R14 ; /* 0x0000000010107229 */
/* 0x000e48000000080e */
/*09f0*/ DFMA R20, -R12, c[0x2][0x58], R10 ; /* 0x008016000c147a2b */
/* 0x001e08000000010a */
/*0a00*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x002fc80000000010 */
/*0a10*/ DADD R20, -R14, R20 ; /* 0x000000000e147229 */
/* 0x0010640000000114 */
/*0a20*/ IMAD.SHL.U32 R14, R5.reuse, 0x2, RZ ; /* 0x00000002050e7824 */
/* 0x041fe200078e00ff */
/*0a30*/ LOP3.LUT R15, R5, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff050f7812 */
/* 0x000fc600078ec0ff */
/*0a40*/ DADD R16, R16, -R20 ; /* 0x0000000010107229 */
/* 0x0020620000000814 */
/*0a50*/ ISETP.GT.U32.AND P1, PT, R14, -0x2000001, PT ; /* 0xfdffffff0e00780c */
/* 0x000fe20003f24070 */
/*0a60*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*0a70*/ IMAD.MOV.U32 R20, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff147424 */
/* 0x001fe200078e00ff */
/*0a80*/ SEL R15, R15, R5, P1 ; /* 0x000000050f0f7207 */
/* 0x000fe20000800000 */
/*0a90*/ DFMA R16, R12, c[0x2][0x60], R16 ; /* 0x008018000c107a2b */
/* 0x002e220000000010 */
/*0aa0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff157424 */
/* 0x000fca00078e00ff */
/*0ab0*/ DADD R12, R10, R16 ; /* 0x000000000a0c7229 */
/* 0x001e0c0000000010 */
/*0ac0*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080c */
/*0ad0*/ DMUL R4, R12, R14 ; /* 0x0000000e0c047228 */
/* 0x000e480000000000 */
/*0ae0*/ DADD R10, R16, R10 ; /* 0x00000000100a7229 */
/* 0x001fc8000000000a */
/*0af0*/ DFMA R12, R12, R14, -R4 ; /* 0x0000000e0c0c722b */
/* 0x002e0c0000000804 */
/*0b00*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001064000000000c */
/*0b10*/ IMAD.MOV.U32 R14, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0e7424 */
/* 0x001fe400078e00ff */
/*0b20*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0f7424 */
/* 0x000fe400078e00ff */
/*0b30*/ DADD R12, R4, R10 ; /* 0x00000000040c7229 */
/* 0x002e0c000000000a */
/*0b40*/ DFMA R14, R12, R14, 6.75539944105574400000e+15 ; /* 0x433800000c0e742b */
/* 0x001e08000000000e */
/*0b50*/ FSETP.GEU.AND P1, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f2e200 */
/*0b60*/ DADD R16, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e107429 */
/* 0x001e0c0000000000 */
/*0b70*/ DFMA R18, R16, c[0x2][0x68], R12 ; /* 0x00801a0010127a2b */
/* 0x001e0c000000000c */
/*0b80*/ DFMA R16, R16, c[0x2][0x70], R18 ; /* 0x00801c0010107a2b */
/* 0x001e0c0000000012 */
/*0b90*/ DFMA R18, R16, R20, c[0x2][0x78] ; /* 0x00801e001012762b */
/* 0x001e0c0000000014 */
/*0ba0*/ DFMA R18, R16, R18, c[0x2][0x80] ; /* 0x008020001012762b */
/* 0x001e0c0000000012 */
/*0bb0*/ DFMA R18, R16, R18, c[0x2][0x88] ; /* 0x008022001012762b */
/* 0x001e0c0000000012 */
/*0bc0*/ DFMA R18, R16, R18, c[0x2][0x90] ; /* 0x008024001012762b */
/* 0x001e0c0000000012 */
/*0bd0*/ DFMA R18, R16, R18, c[0x2][0x98] ; /* 0x008026001012762b */
/* 0x001e0c0000000012 */
/*0be0*/ DFMA R18, R16, R18, c[0x2][0xa0] ; /* 0x008028001012762b */
/* 0x001e0c0000000012 */
/*0bf0*/ DFMA R18, R16, R18, c[0x2][0xa8] ; /* 0x00802a001012762b */
/* 0x001e0c0000000012 */
/*0c00*/ DFMA R18, R16, R18, c[0x2][0xb0] ; /* 0x00802c001012762b */
/* 0x001e0c0000000012 */
/*0c10*/ DFMA R18, R16, R18, c[0x2][0xb8] ; /* 0x00802e001012762b */
/* 0x001e0c0000000012 */
/*0c20*/ DFMA R18, R16, R18, 1 ; /* 0x3ff000001012742b */
/* 0x001e0c0000000012 */
/*0c30*/ DFMA R18, R16, R18, 1 ; /* 0x3ff000001012742b */
/* 0x001e140000000012 */
/*0c40*/ IMAD R17, R14, 0x100000, R19 ; /* 0x001000000e117824 */
/* 0x001fe400078e0213 */
/*0c50*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0012 */
/*0c60*/ @!P1 BRA 0xd30 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0c70*/ FSETP.GEU.AND P2, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f4e200 */
/*0c80*/ DADD R16, R12, +INF ; /* 0x7ff000000c107429 */
/* 0x000fc80000000000 */
/*0c90*/ DSETP.GEU.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f2e000 */
/*0ca0*/ FSEL R16, R16, RZ, P1 ; /* 0x000000ff10107208 */
/* 0x001fe40000800000 */
/*0cb0*/ @!P2 LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0fa211 */
/* 0x000fe400078f08ff */
/*0cc0*/ FSEL R17, R17, RZ, P1 ; /* 0x000000ff11117208 */
/* 0x000fe40000800000 */
/*0cd0*/ @!P2 SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0fa819 */
/* 0x000fca000001140f */
/*0ce0*/ @!P2 IMAD.IADD R14, R14, 0x1, -R15 ; /* 0x000000010e0ea824 */
/* 0x000fe400078e0a0f */
/*0cf0*/ @!P2 IMAD R19, R15, 0x100000, R19 ; /* 0x001000000f13a824 */
/* 0x000fc600078e0213 */
/*0d00*/ @!P2 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0fa811 */
/* 0x000fe200078ea0ff */
/*0d10*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fcc00078e00ff */
/*0d20*/ @!P2 DMUL R16, R18, R14 ; /* 0x0000000e1210a228 */
/* 0x0000540000000000 */
/*0d30*/ LOP3.LUT R14, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110e7812 */
/* 0x003fe200078ec0ff */
/*0d40*/ DADD R4, R4, -R12 ; /* 0x0000000004047229 */
/* 0x000e06000000080c */
/*0d50*/ ISETP.NE.AND P1, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fc60003f25270 */
/*0d60*/ DADD R4, R10, R4 ; /* 0x000000000a047229 */
/* 0x001e220000000004 */
/*0d70*/ ISETP.EQ.AND P1, PT, R16, RZ, !P1 ; /* 0x000000ff1000720c */
/* 0x000fda0004f22270 */
/*0d80*/ @!P1 DFMA R16, R4, R16, R16 ; /* 0x000000100410922b */
/* 0x0010640000000010 */
/*0d90*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0000 */
/*0da0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0db0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff24004007950 */
/* 0x002fea0003c3ffff */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
long long res[64];
__global__ void fib(long long *res)
{
int idx = threadIdx.x;
res[idx] = (long long)(1.0/sqrt(5.0)*(pow((1+sqrt(5.0))/2.0, idx+1) - pow((1-sqrt(5.0))/2.0, idx+1)) + 0.5);
// printf("%d\n", res[idx]);
}
int main()
{
int n;
long long *gpures;
scanf("%d", &n);
cudaMalloc(&gpures, n*sizeof(long long));
fib<<<1,n>>>(gpures);
cudaMemcpy(res, gpures, n*sizeof(long long), cudaMemcpyDeviceToHost);
cudaFree(gpures);
for (int i = 0; i < n; ++i)
{
printf(i == n-1 ? "%lld\n" : "%lld ", res[i]);
}
return 0;
} | .file "tmpxft_0001c5d0_00000000-6_fab_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fibPxPx
.type _Z22__device_stub__Z3fibPxPx, @function
_Z22__device_stub__Z3fibPxPx:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fibPx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z3fibPxPx, .-_Z22__device_stub__Z3fibPxPx
.globl _Z3fibPx
.type _Z3fibPx, @function
_Z3fibPx:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fibPxPx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fibPx, .-_Z3fibPx
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lld\n"
.LC1:
.string "%lld "
.LC2:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
movslq 4(%rsp), %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
movslq 4(%rsp), %rdx
salq $3, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
leaq res(%rip), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .L13
movl $0, %ebx
leaq res(%rip), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L15:
movq 0(%r13,%rbx,8), %rdx
subl $1, %eax
cmpl %ebx, %eax
movq %rbp, %rsi
cmovne %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L15
.L13:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3fibPxPx
jmp .L12
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3fibPx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fibPx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res
.bss
.align 32
.type res, @object
.size res, 512
res:
.zero 512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
long long res[64];
__global__ void fib(long long *res)
{
int idx = threadIdx.x;
res[idx] = (long long)(1.0/sqrt(5.0)*(pow((1+sqrt(5.0))/2.0, idx+1) - pow((1-sqrt(5.0))/2.0, idx+1)) + 0.5);
// printf("%d\n", res[idx]);
}
int main()
{
int n;
long long *gpures;
scanf("%d", &n);
cudaMalloc(&gpures, n*sizeof(long long));
fib<<<1,n>>>(gpures);
cudaMemcpy(res, gpures, n*sizeof(long long), cudaMemcpyDeviceToHost);
cudaFree(gpures);
for (int i = 0; i < n; ++i)
{
printf(i == n-1 ? "%lld\n" : "%lld ", res[i]);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
long long res[64];
__global__ void fib(long long *res)
{
int idx = threadIdx.x;
res[idx] = (long long)(1.0/sqrt(5.0)*(pow((1+sqrt(5.0))/2.0, idx+1) - pow((1-sqrt(5.0))/2.0, idx+1)) + 0.5);
// printf("%d\n", res[idx]);
}
int main()
{
int n;
long long *gpures;
scanf("%d", &n);
hipMalloc(&gpures, n*sizeof(long long));
fib<<<1,n>>>(gpures);
hipMemcpy(res, gpures, n*sizeof(long long), hipMemcpyDeviceToHost);
hipFree(gpures);
for (int i = 0; i < n; ++i)
{
printf(i == n-1 ? "%lld\n" : "%lld ", res[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
long long res[64];
__global__ void fib(long long *res)
{
int idx = threadIdx.x;
res[idx] = (long long)(1.0/sqrt(5.0)*(pow((1+sqrt(5.0))/2.0, idx+1) - pow((1-sqrt(5.0))/2.0, idx+1)) + 0.5);
// printf("%d\n", res[idx]);
}
int main()
{
int n;
long long *gpures;
scanf("%d", &n);
hipMalloc(&gpures, n*sizeof(long long));
fib<<<1,n>>>(gpures);
hipMemcpy(res, gpures, n*sizeof(long long), hipMemcpyDeviceToHost);
hipFree(gpures);
for (int i = 0; i < n; ++i)
{
printf(i == n-1 ? "%lld\n" : "%lld ", res[i]);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fibPx
.globl _Z3fibPx
.p2align 8
.type _Z3fibPx,@function
_Z3fibPx:
v_add_nc_u32_e32 v1, 1, v0
s_mov_b32 s3, 0xbfdecc2c
s_mov_b32 s2, 0xaec51608
s_mov_b32 s5, 0x3fdecc2c
s_mov_b32 s4, 0xaec5160a
v_cvt_f64_i32_e32 v[1:2], v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[3:4], v[1:2], s[2:3]
v_mul_f64 v[5:6], v[1:2], s[4:5]
v_fma_f64 v[7:8], v[1:2], s[2:3], -v[3:4]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[9:10], v[1:2], s[4:5], -v[5:6]
s_mov_b32 s3, 0x3c031079
s_mov_b32 s2, 0x70b72d00
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[7:8], v[1:2], s[2:3], v[7:8]
s_mov_b32 s3, 0x3c67c875
s_mov_b32 s2, 0xcbdda34e
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[1:2], v[1:2], s[2:3], v[9:10]
v_cmp_class_f64_e64 s2, v[5:6], 0x204
s_mov_b32 s3, 0xbfe62e42
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[3:4], v[7:8]
v_add_f64 v[11:12], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v14, v10, v4 :: v_dual_cndmask_b32 v13, v9, v3
v_add_f64 v[3:4], v[9:10], -v[3:4]
v_cndmask_b32_e64 v16, v12, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v15, v11, v5, s2
v_mul_f64 v[17:18], v[13:14], s[4:5]
s_mov_b32 s2, 0xfefa39ef
v_add_f64 v[5:6], v[11:12], -v[5:6]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[13:14]|
v_mul_f64 v[19:20], v[15:16], s[4:5]
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[15:16]
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_rndne_f64_e32 v[17:18], v[17:18]
v_add_f64 v[1:2], v[1:2], -v[5:6]
v_rndne_f64_e32 v[19:20], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
v_fma_f64 v[21:22], v[17:18], s[2:3], v[13:14]
v_cvt_i32_f64_e32 v29, v[17:18]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[23:24], v[19:20], s[2:3], v[15:16]
s_mov_b32 s3, 0xbc7abc9e
s_mov_b32 s2, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[21:22], v[17:18], s[2:3], v[21:22]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[23:24], v[19:20], s[2:3], v[23:24]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], s[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_fma_f64 v[27:28], v[23:24], s[4:5], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
v_cmp_nlt_f64_e64 s5, 0x40900000, v[15:16]
v_cmp_neq_f64_e64 s4, 0x7ff00000, |v[15:16]|
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
v_cndmask_b32_e64 v2, 0, v2, s4
v_cndmask_b32_e64 v1, 0, v1, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
v_cmp_nlt_f64_e64 s2, 0x40900000, v[13:14]
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[13:14]
v_fma_f64 v[25:26], v[21:22], v[25:26], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], v[23:24], v[27:28], 1.0
s_and_b32 vcc_lo, s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], v[21:22], v[25:26], 1.0
v_cvt_i32_f64_e32 v21, v[19:20]
v_fma_f64 v[19:20], v[23:24], v[27:28], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[9:10], v[17:18], v29
v_ldexp_f64 v[11:12], v[19:20], v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0x7ff00000, v10, s2
v_mov_b32_e32 v10, 0xbfe3c6ef
v_cndmask_b32_e64 v7, 0x7ff00000, v12, s5
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v6, 0, v5, s3
v_cndmask_b32_e32 v5, 0, v9, vcc_lo
s_and_b32 vcc_lo, s6, s5
v_and_b32_e32 v9, 1, v0
v_cndmask_b32_e64 v8, 0, v7, s6
v_dual_cndmask_b32 v7, 0, v11 :: v_dual_lshlrev_b32 v0, 3, v0
v_fma_f64 v[3:4], v[5:6], v[3:4], v[5:6]
v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
v_cmp_eq_u32_e64 s3, 0, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[1:2], v[7:8], v[1:2], v[7:8]
v_cmp_class_f64_e64 s2, v[7:8], 0x204
v_cndmask_b32_e64 v9, 0x3ff00000, v10, s3
s_mov_b32 s3, 0x3fdc9f25
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v8, s2
v_cndmask_b32_e64 v1, v1, v7, s2
v_bfi_b32 v4, 0x7fffffff, v4, v9
s_mov_b32 s2, 0xc5bfedd9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], |v[1:2]|, -v[3:4]
v_fma_f64 v[1:2], v[1:2], s[2:3], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f64_e32 v[1:2], v[1:2]
v_ldexp_f64 v[3:4], v[1:2], 0xffffffe0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f64_e32 v[3:4], v[3:4]
v_fma_f64 v[1:2], v[3:4], 0xc1f00000, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f64_e32 v1, v[1:2]
v_cvt_i32_f64_e32 v2, v[3:4]
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fibPx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fibPx, .Lfunc_end0-_Z3fibPx
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fibPx
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z3fibPx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
long long res[64];
__global__ void fib(long long *res)
{
int idx = threadIdx.x;
res[idx] = (long long)(1.0/sqrt(5.0)*(pow((1+sqrt(5.0))/2.0, idx+1) - pow((1-sqrt(5.0))/2.0, idx+1)) + 0.5);
// printf("%d\n", res[idx]);
}
int main()
{
int n;
long long *gpures;
scanf("%d", &n);
hipMalloc(&gpures, n*sizeof(long long));
fib<<<1,n>>>(gpures);
hipMemcpy(res, gpures, n*sizeof(long long), hipMemcpyDeviceToHost);
hipFree(gpures);
for (int i = 0; i < n; ++i)
{
printf(i == n-1 ? "%lld\n" : "%lld ", res[i]);
}
return 0;
} | .text
.file "fab_cuda.hip"
.globl _Z18__device_stub__fibPx # -- Begin function _Z18__device_stub__fibPx
.p2align 4, 0x90
.type _Z18__device_stub__fibPx,@function
_Z18__device_stub__fibPx: # @_Z18__device_stub__fibPx
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fibPx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fibPx, .Lfunc_end0-_Z18__device_stub__fibPx
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3fibPx, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $3, %rdx
movl $res, %edi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.3: # %.lr.ph.preheader
xorl %ebx, %ebx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movq res(,%rbx,8), %rsi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jge .LBB1_7
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.1, %edi
cmpq %rax, %rbx
je .LBB1_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movl $.L.str.2, %edi
jmp .LBB1_6
.LBB1_7: # %._crit_edge
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fibPx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type res,@object # @res
.bss
.globl res
.p2align 4, 0x0
res:
.zero 512
.size res, 512
.type _Z3fibPx,@object # @_Z3fibPx
.section .rodata,"a",@progbits
.globl _Z3fibPx
.p2align 3, 0x0
_Z3fibPx:
.quad _Z18__device_stub__fibPx
.size _Z3fibPx, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lld\n"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lld "
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3fibPx"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fibPx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym res
.addrsig_sym _Z3fibPx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fibPx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x120 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0030*/ UMOV UR5, 0x9b97f4a8 ; /* 0x9b97f4a800057882 */
/* 0x000fe40000000000 */
/*0040*/ UMOV UR6, 0x3ff9e377 ; /* 0x3ff9e37700067882 */
/* 0x000fe20000000000 */
/*0050*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x001fc80007ffe0ff */
/*0060*/ I2F.F64 R6, R3 ; /* 0x0000000300067312 */
/* 0x000e240000201c00 */
/*0070*/ LOP3.LUT R0, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007007812 */
/* 0x001fe200078ec0ff */
/*0080*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e0006 */
/*0090*/ LEA.HI R5, R0, 0xfffffc0c, RZ, 0xc ; /* 0xfffffc0c00057811 */
/* 0x000fc800078f60ff */
/*00a0*/ SHF.L.U32 R0, R6.reuse, R5.reuse, RZ ; /* 0x0000000506007219 */
/* 0x0c0fe400000006ff */
/*00b0*/ SHF.L.U64.HI R5, R6, R5, R7.reuse ; /* 0x0000000506057219 */
/* 0x100fe40000010207 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*00d0*/ MOV R0, 0x110 ; /* 0x0000011000007802 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.NE.AND.EX P0, PT, R5, -0x80000000, PT, P0 ; /* 0x800000000500780c */
/* 0x000fe20003f05300 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fce00078e0007 */
/*0100*/ CALL.REL.NOINC 0x530 ; /* 0x0000042000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ DADD R4, R6, c[0x2][0x0] ; /* 0x0080000006047629 */
/* 0x000e220000000000 */
/*0130*/ BSSY B0, 0x250 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0010 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fcc00078e0011 */
/*0160*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x001fc800078ec0ff */
/*0170*/ ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fda0003f25270 */
/*0180*/ @P1 BRA 0x240 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0190*/ DSETP.GTU.AND P1, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f2c200 */
/*01a0*/ @P1 BRA 0x230 ; /* 0x0000008000001947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*01c0*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*01d0*/ ISETP.EQ.AND P1, PT, R0, 0x7ff00000, !P1 ; /* 0x7ff000000000780c */
/* 0x000fda0004f22270 */
/*01e0*/ @!P1 BRA 0x240 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f26270 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0210*/ SEL R9, RZ, 0x7ff00000, !P1 ; /* 0x7ff00000ff097807 */
/* 0x000fe20004800000 */
/*0220*/ BRA 0x240 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0230*/ DADD R8, R6, c[0x2][0x0] ; /* 0x0080000006087629 */
/* 0x00004c0000000000 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BSSY B0, 0x2d0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0260*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0006 */
/*0270*/ MOV R0, 0x2c0 ; /* 0x000002c000007802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0290*/ UMOV UR5, 0x372fe950 ; /* 0x372fe95000057882 */
/* 0x000fe40000000000 */
/*02a0*/ UMOV UR6, 0x3fe3c6ef ; /* 0x3fe3c6ef00067882 */
/* 0x000fe40000000000 */
/*02b0*/ CALL.REL.NOINC 0x530 ; /* 0x0000027000007944 */
/* 0x003fea0003c00000 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ FRND.F64.TRUNC R4, R6 ; /* 0x0000000600047313 */
/* 0x000e22000030d800 */
/*02e0*/ DADD R10, R6, c[0x2][0x8] ; /* 0x00800200060a7629 */
/* 0x000e620000000000 */
/*02f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0300*/ BSSY B0, 0x470 ; /* 0x0000016000007945 */
/* 0x000ff00003800000 */
/*0310*/ LOP3.LUT R10, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0a7812 */
/* 0x002fc800078ec0ff */
/*0320*/ ISETP.NE.AND P2, PT, R10, 0x7ff00000, PT ; /* 0x7ff000000a00780c */
/* 0x000fe20003f45270 */
/*0330*/ DSETP.NEU.AND P1, PT, R4, R6, PT ; /* 0x000000060400722a */
/* 0x0010640003f2d000 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0011 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0010 */
/*0360*/ @!P0 LOP3.LUT R11, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000050b8812 */
/* 0x000fca00078e3cff */
/*0370*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff058224 */
/* 0x000fe400078e000b */
/*0380*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff041424 */
/* 0x002fe400078e00ff */
/*0390*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff051424 */
/* 0x000fe200078e00ff */
/*03a0*/ @P2 BRA 0x460 ; /* 0x000000b000002947 */
/* 0x000fea0003800000 */
/*03b0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*03c0*/ @P0 BRA 0x450 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*03d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*03e0*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*03f0*/ ISETP.EQ.AND P0, PT, R0, 0x7ff00000, !P0 ; /* 0x7ff000000000780c */
/* 0x000fda0004702270 */
/*0400*/ @!P0 BRA 0x460 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0410*/ SHF.R.S32.HI R6, RZ, 0x1f, R7 ; /* 0x0000001fff067819 */
/* 0x000fe20000011407 */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0430*/ LOP3.LUT R5, R6, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000006057812 */
/* 0x000fe200078ec0ff */
/*0440*/ BRA 0x460 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0450*/ DADD R4, R6, c[0x2][0x8] ; /* 0x0080020006047629 */
/* 0x00004c0000000000 */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ DADD R4, -R4, R8 ; /* 0x0000000004047229 */
/* 0x002e620000000108 */
/*0480*/ IMAD.MOV.U32 R6, RZ, RZ, -0x3a401227 ; /* 0xc5bfedd9ff067424 */
/* 0x001fe200078e00ff */
/*0490*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*04a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3fdc9f25 ; /* 0x3fdc9f25ff077424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*04c0*/ DFMA R4, R4, R6, 0.5 ; /* 0x3fe000000404742b */
/* 0x002e220000000006 */
/*04d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd200078e0203 */
/*04e0*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x001fe40000000000 */
/*04f0*/ FSEL R5, R5, 1.75, P0 ; /* 0x3fe0000005057808 */
/* 0x000fcc0000000000 */
/*0500*/ F2I.S64.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000030d900 */
/*0510*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ USHF.R.U32.HI UR4, URZ, 0x14, UR6 ; /* 0x000000143f047899 */
/* 0x000fe20008011606 */
/*0540*/ IMAD.U32 R22, RZ, RZ, UR5 ; /* 0x00000005ff167e24 */
/* 0x000fe4000f8e00ff */
/*0550*/ IMAD.U32 R23, RZ, RZ, UR6 ; /* 0x00000006ff177e24 */
/* 0x000fe4000f8e00ff */
/*0560*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0570*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0580*/ IMAD.U32 R14, RZ, RZ, UR5 ; /* 0x00000005ff0e7e24 */
/* 0x000fc4000f8e00ff */
/*0590*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*05a0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff147424 */
/* 0x000fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff157424 */
/* 0x000fcc00078e00ff */
/*05c0*/ @!P1 DMUL R22, R22, 1.80143985094819840000e+16 ; /* 0x4350000016169828 */
/* 0x000e140000000000 */
/*05d0*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, R23 ; /* 0x000000ffff049224 */
/* 0x001fe400078e0017 */
/*05e0*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e9224 */
/* 0x000fc600078e0016 */
/*05f0*/ LOP3.LUT R4, R4, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff04047812 */
/* 0x000fc800078ec0ff */
/*0600*/ LOP3.LUT R15, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff00000040f7812 */
/* 0x000fe200078efcff */
/*0610*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0620*/ @!P1 LEA.HI R4, R23, 0xffffffca, RZ, 0xc ; /* 0xffffffca17049811 */
/* 0x000fe400078f60ff */
/*0630*/ ISETP.GE.U32.AND P2, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f46070 */
/*0640*/ @P2 IADD3 R11, R15, -0x100000, RZ ; /* 0xfff000000f0b2810 */
/* 0x000fca0007ffe0ff */
/*0650*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f2224 */
/* 0x000fcc00078e000b */
/*0660*/ DADD R16, R14, 1 ; /* 0x3ff000000e107429 */
/* 0x000e080000000000 */
/*0670*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*0680*/ MUFU.RCP64H R11, R17 ; /* 0x00000011000b7308 */
/* 0x001e240000001800 */
/*0690*/ DFMA R12, -R16, R10, 1 ; /* 0x3ff00000100c742b */
/* 0x001e0c000000010a */
/*06a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*06b0*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*06c0*/ DMUL R12, R10, R14 ; /* 0x0000000e0a0c7228 */
/* 0x001e0c0000000000 */
/*06d0*/ DFMA R12, R10, R14, R12 ; /* 0x0000000e0a0c722b */
/* 0x001e0c000000000c */
/*06e0*/ DMUL R18, R12, R12 ; /* 0x0000000c0c127228 */
/* 0x001e080000000000 */
/*06f0*/ DADD R16, R14, -R12 ; /* 0x000000000e107229 */
/* 0x000e48000000080c */
/*0700*/ DFMA R20, R18, R20, c[0x2][0x10] ; /* 0x008004001214762b */
/* 0x001e080000000014 */
/*0710*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x002e480000000010 */
/*0720*/ DFMA R20, R18, R20, c[0x2][0x18] ; /* 0x008006001214762b */
/* 0x001e080000000014 */
/*0730*/ DFMA R16, R14, -R12, R16 ; /* 0x8000000c0e10722b */
/* 0x002e480000000010 */
/*0740*/ DFMA R20, R18, R20, c[0x2][0x20] ; /* 0x008008001214762b */
/* 0x001e080000000014 */
/*0750*/ DMUL R10, R10, R16 ; /* 0x000000100a0a7228 */
/* 0x002fc80000000000 */
/*0760*/ DFMA R20, R18, R20, c[0x2][0x28] ; /* 0x00800a001214762b */
/* 0x001e0c0000000014 */
/*0770*/ DFMA R24, R18, R20, c[0x2][0x30] ; /* 0x00800c001218762b */
/* 0x001e080000000014 */
/*0780*/ DMUL R20, R12, R12 ; /* 0x0000000c0c147228 */
/* 0x000fc80000000000 */
/*0790*/ DFMA R24, R18, R24, c[0x2][0x38] ; /* 0x00800e001218762b */
/* 0x001e0c0000000018 */
/*07a0*/ DFMA R14, R18, R24, c[0x2][0x40] ; /* 0x00801000120e762b */
/* 0x001e0c0000000018 */
/*07b0*/ DADD R16, -R14, c[0x2][0x40] ; /* 0x008010000e107629 */
/* 0x001e0c0000000100 */
/*07c0*/ DFMA R24, R18, R24, R16 ; /* 0x000000181218722b */
/* 0x0010640000000010 */
/*07d0*/ IADD3 R19, R11, 0x100000, RZ ; /* 0x001000000b137810 */
/* 0x001fe20007ffe0ff */
/*07e0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000a */
/*07f0*/ DFMA R16, R12, R12, -R20 ; /* 0x0000000c0c10722b */
/* 0x000e080000000814 */
/*0800*/ DADD R24, RZ, R24 ; /* 0x00000000ff187229 */
/* 0x002e480000000018 */
/*0810*/ DFMA R18, R12, R18, R16 ; /* 0x000000120c12722b */
/* 0x001fc80000000010 */
/*0820*/ DMUL R16, R12, R20 ; /* 0x000000140c107228 */
/* 0x000e080000000000 */
/*0830*/ DADD R24, R24, c[0x2][0x48] ; /* 0x0080120018187629 */
/* 0x002fc80000000000 */
/*0840*/ DFMA R22, R12, R20, -R16 ; /* 0x000000140c16722b */
/* 0x001e0c0000000810 */
/*0850*/ DFMA R22, R10, R20, R22 ; /* 0x000000140a16722b */
/* 0x001e080000000016 */
/*0860*/ DADD R20, R14, R24 ; /* 0x000000000e147229 */
/* 0x000e480000000018 */
/*0870*/ DFMA R18, R12, R18, R22 ; /* 0x000000120c12722b */
/* 0x001fc80000000016 */
/*0880*/ DADD R22, R14, -R20 ; /* 0x000000000e167229 */
/* 0x002e080000000814 */
/*0890*/ DMUL R14, R20, R16 ; /* 0x00000010140e7228 */
/* 0x000e480000000000 */
/*08a0*/ DADD R24, R24, R22 ; /* 0x0000000018187229 */
/* 0x001fc80000000016 */
/*08b0*/ DFMA R22, R20, R16, -R14 ; /* 0x000000101416722b */
/* 0x002e0c000000080e */
/*08c0*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x001e0c0000000016 */
/*08d0*/ DFMA R24, R24, R16, R18 ; /* 0x000000101818722b */
/* 0x001e0c0000000012 */
/*08e0*/ DADD R18, R14, R24 ; /* 0x000000000e127229 */
/* 0x001e0c0000000018 */
/*08f0*/ DADD R16, R12, R18 ; /* 0x000000000c107229 */
/* 0x001e080000000012 */
/*0900*/ DADD R14, R14, -R18 ; /* 0x000000000e0e7229 */
/* 0x000e480000000812 */
/*0910*/ DADD R12, R12, -R16 ; /* 0x000000000c0c7229 */
/* 0x001e080000000810 */
/*0920*/ DADD R14, R24, R14 ; /* 0x00000000180e7229 */
/* 0x002fc8000000000e */
/*0930*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x001064000000000c */
/*0940*/ IADD3 R18, R4.reuse, -0x3ff, RZ ; /* 0xfffffc0104127810 */
/* 0x041fe40007ffe0ff */
/*0950*/ @P2 IADD3 R18, R4, -0x3fe, RZ ; /* 0xfffffc0204122810 */
/* 0x000fe20007ffe0ff */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R26 ; /* 0x000000ffff047224 */
/* 0x000fe200078e001a */
/*0970*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x002064000000000c */
/*0980*/ LOP3.LUT R14, R18, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000120e7812 */
/* 0x001fe200078e3cff */
/*0990*/ IMAD.MOV.U32 R15, RZ, RZ, 0x43300000 ; /* 0x43300000ff0f7424 */
/* 0x000fc600078e00ff */
/*09a0*/ DADD R18, R10, R12 ; /* 0x000000000a127229 */
/* 0x002e08000000000c */
/*09b0*/ DADD R12, R14, c[0x2][0x50] ; /* 0x008014000e0c7629 */
/* 0x000fc80000000000 */
/*09c0*/ DADD R14, R16, R18 ; /* 0x00000000100e7229 */
/* 0x001e0c0000000012 */
/*09d0*/ DFMA R10, R12, c[0x2][0x58], R14 ; /* 0x008016000c0a7a2b */
/* 0x001e08000000000e */
/*09e0*/ DADD R16, R16, -R14 ; /* 0x0000000010107229 */
/* 0x000e48000000080e */
/*09f0*/ DFMA R20, -R12, c[0x2][0x58], R10 ; /* 0x008016000c147a2b */
/* 0x001e08000000010a */
/*0a00*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x002fc80000000010 */
/*0a10*/ DADD R20, -R14, R20 ; /* 0x000000000e147229 */
/* 0x0010640000000114 */
/*0a20*/ IMAD.SHL.U32 R14, R5.reuse, 0x2, RZ ; /* 0x00000002050e7824 */
/* 0x041fe200078e00ff */
/*0a30*/ LOP3.LUT R15, R5, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff050f7812 */
/* 0x000fc600078ec0ff */
/*0a40*/ DADD R16, R16, -R20 ; /* 0x0000000010107229 */
/* 0x0020620000000814 */
/*0a50*/ ISETP.GT.U32.AND P1, PT, R14, -0x2000001, PT ; /* 0xfdffffff0e00780c */
/* 0x000fe20003f24070 */
/*0a60*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*0a70*/ IMAD.MOV.U32 R20, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff147424 */
/* 0x001fe200078e00ff */
/*0a80*/ SEL R15, R15, R5, P1 ; /* 0x000000050f0f7207 */
/* 0x000fe20000800000 */
/*0a90*/ DFMA R16, R12, c[0x2][0x60], R16 ; /* 0x008018000c107a2b */
/* 0x002e220000000010 */
/*0aa0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff157424 */
/* 0x000fca00078e00ff */
/*0ab0*/ DADD R12, R10, R16 ; /* 0x000000000a0c7229 */
/* 0x001e0c0000000010 */
/*0ac0*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080c */
/*0ad0*/ DMUL R4, R12, R14 ; /* 0x0000000e0c047228 */
/* 0x000e480000000000 */
/*0ae0*/ DADD R10, R16, R10 ; /* 0x00000000100a7229 */
/* 0x001fc8000000000a */
/*0af0*/ DFMA R12, R12, R14, -R4 ; /* 0x0000000e0c0c722b */
/* 0x002e0c0000000804 */
/*0b00*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001064000000000c */
/*0b10*/ IMAD.MOV.U32 R14, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0e7424 */
/* 0x001fe400078e00ff */
/*0b20*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0f7424 */
/* 0x000fe400078e00ff */
/*0b30*/ DADD R12, R4, R10 ; /* 0x00000000040c7229 */
/* 0x002e0c000000000a */
/*0b40*/ DFMA R14, R12, R14, 6.75539944105574400000e+15 ; /* 0x433800000c0e742b */
/* 0x001e08000000000e */
/*0b50*/ FSETP.GEU.AND P1, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f2e200 */
/*0b60*/ DADD R16, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e107429 */
/* 0x001e0c0000000000 */
/*0b70*/ DFMA R18, R16, c[0x2][0x68], R12 ; /* 0x00801a0010127a2b */
/* 0x001e0c000000000c */
/*0b80*/ DFMA R16, R16, c[0x2][0x70], R18 ; /* 0x00801c0010107a2b */
/* 0x001e0c0000000012 */
/*0b90*/ DFMA R18, R16, R20, c[0x2][0x78] ; /* 0x00801e001012762b */
/* 0x001e0c0000000014 */
/*0ba0*/ DFMA R18, R16, R18, c[0x2][0x80] ; /* 0x008020001012762b */
/* 0x001e0c0000000012 */
/*0bb0*/ DFMA R18, R16, R18, c[0x2][0x88] ; /* 0x008022001012762b */
/* 0x001e0c0000000012 */
/*0bc0*/ DFMA R18, R16, R18, c[0x2][0x90] ; /* 0x008024001012762b */
/* 0x001e0c0000000012 */
/*0bd0*/ DFMA R18, R16, R18, c[0x2][0x98] ; /* 0x008026001012762b */
/* 0x001e0c0000000012 */
/*0be0*/ DFMA R18, R16, R18, c[0x2][0xa0] ; /* 0x008028001012762b */
/* 0x001e0c0000000012 */
/*0bf0*/ DFMA R18, R16, R18, c[0x2][0xa8] ; /* 0x00802a001012762b */
/* 0x001e0c0000000012 */
/*0c00*/ DFMA R18, R16, R18, c[0x2][0xb0] ; /* 0x00802c001012762b */
/* 0x001e0c0000000012 */
/*0c10*/ DFMA R18, R16, R18, c[0x2][0xb8] ; /* 0x00802e001012762b */
/* 0x001e0c0000000012 */
/*0c20*/ DFMA R18, R16, R18, 1 ; /* 0x3ff000001012742b */
/* 0x001e0c0000000012 */
/*0c30*/ DFMA R18, R16, R18, 1 ; /* 0x3ff000001012742b */
/* 0x001e140000000012 */
/*0c40*/ IMAD R17, R14, 0x100000, R19 ; /* 0x001000000e117824 */
/* 0x001fe400078e0213 */
/*0c50*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0012 */
/*0c60*/ @!P1 BRA 0xd30 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0c70*/ FSETP.GEU.AND P2, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f4e200 */
/*0c80*/ DADD R16, R12, +INF ; /* 0x7ff000000c107429 */
/* 0x000fc80000000000 */
/*0c90*/ DSETP.GEU.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f2e000 */
/*0ca0*/ FSEL R16, R16, RZ, P1 ; /* 0x000000ff10107208 */
/* 0x001fe40000800000 */
/*0cb0*/ @!P2 LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0fa211 */
/* 0x000fe400078f08ff */
/*0cc0*/ FSEL R17, R17, RZ, P1 ; /* 0x000000ff11117208 */
/* 0x000fe40000800000 */
/*0cd0*/ @!P2 SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0fa819 */
/* 0x000fca000001140f */
/*0ce0*/ @!P2 IMAD.IADD R14, R14, 0x1, -R15 ; /* 0x000000010e0ea824 */
/* 0x000fe400078e0a0f */
/*0cf0*/ @!P2 IMAD R19, R15, 0x100000, R19 ; /* 0x001000000f13a824 */
/* 0x000fc600078e0213 */
/*0d00*/ @!P2 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0fa811 */
/* 0x000fe200078ea0ff */
/*0d10*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fcc00078e00ff */
/*0d20*/ @!P2 DMUL R16, R18, R14 ; /* 0x0000000e1210a228 */
/* 0x0000540000000000 */
/*0d30*/ LOP3.LUT R14, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110e7812 */
/* 0x003fe200078ec0ff */
/*0d40*/ DADD R4, R4, -R12 ; /* 0x0000000004047229 */
/* 0x000e06000000080c */
/*0d50*/ ISETP.NE.AND P1, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fc60003f25270 */
/*0d60*/ DADD R4, R10, R4 ; /* 0x000000000a047229 */
/* 0x001e220000000004 */
/*0d70*/ ISETP.EQ.AND P1, PT, R16, RZ, !P1 ; /* 0x000000ff1000720c */
/* 0x000fda0004f22270 */
/*0d80*/ @!P1 DFMA R16, R4, R16, R16 ; /* 0x000000100410922b */
/* 0x0010640000000010 */
/*0d90*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0000 */
/*0da0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0db0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff24004007950 */
/* 0x002fea0003c3ffff */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fibPx
.globl _Z3fibPx
.p2align 8
.type _Z3fibPx,@function
_Z3fibPx:
v_add_nc_u32_e32 v1, 1, v0
s_mov_b32 s3, 0xbfdecc2c
s_mov_b32 s2, 0xaec51608
s_mov_b32 s5, 0x3fdecc2c
s_mov_b32 s4, 0xaec5160a
v_cvt_f64_i32_e32 v[1:2], v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[3:4], v[1:2], s[2:3]
v_mul_f64 v[5:6], v[1:2], s[4:5]
v_fma_f64 v[7:8], v[1:2], s[2:3], -v[3:4]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[9:10], v[1:2], s[4:5], -v[5:6]
s_mov_b32 s3, 0x3c031079
s_mov_b32 s2, 0x70b72d00
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[7:8], v[1:2], s[2:3], v[7:8]
s_mov_b32 s3, 0x3c67c875
s_mov_b32 s2, 0xcbdda34e
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[1:2], v[1:2], s[2:3], v[9:10]
v_cmp_class_f64_e64 s2, v[5:6], 0x204
s_mov_b32 s3, 0xbfe62e42
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[3:4], v[7:8]
v_add_f64 v[11:12], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v14, v10, v4 :: v_dual_cndmask_b32 v13, v9, v3
v_add_f64 v[3:4], v[9:10], -v[3:4]
v_cndmask_b32_e64 v16, v12, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v15, v11, v5, s2
v_mul_f64 v[17:18], v[13:14], s[4:5]
s_mov_b32 s2, 0xfefa39ef
v_add_f64 v[5:6], v[11:12], -v[5:6]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[13:14]|
v_mul_f64 v[19:20], v[15:16], s[4:5]
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[15:16]
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_rndne_f64_e32 v[17:18], v[17:18]
v_add_f64 v[1:2], v[1:2], -v[5:6]
v_rndne_f64_e32 v[19:20], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
v_fma_f64 v[21:22], v[17:18], s[2:3], v[13:14]
v_cvt_i32_f64_e32 v29, v[17:18]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[23:24], v[19:20], s[2:3], v[15:16]
s_mov_b32 s3, 0xbc7abc9e
s_mov_b32 s2, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[21:22], v[17:18], s[2:3], v[21:22]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[23:24], v[19:20], s[2:3], v[23:24]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], s[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_fma_f64 v[27:28], v[23:24], s[4:5], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
v_cmp_nlt_f64_e64 s5, 0x40900000, v[15:16]
v_cmp_neq_f64_e64 s4, 0x7ff00000, |v[15:16]|
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
v_cndmask_b32_e64 v2, 0, v2, s4
v_cndmask_b32_e64 v1, 0, v1, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[25:26], v[21:22], v[25:26], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[27:28], v[23:24], v[27:28], s[2:3]
v_cmp_nlt_f64_e64 s2, 0x40900000, v[13:14]
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[13:14]
v_fma_f64 v[25:26], v[21:22], v[25:26], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], v[23:24], v[27:28], 1.0
s_and_b32 vcc_lo, s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], v[21:22], v[25:26], 1.0
v_cvt_i32_f64_e32 v21, v[19:20]
v_fma_f64 v[19:20], v[23:24], v[27:28], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[9:10], v[17:18], v29
v_ldexp_f64 v[11:12], v[19:20], v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0x7ff00000, v10, s2
v_mov_b32_e32 v10, 0xbfe3c6ef
v_cndmask_b32_e64 v7, 0x7ff00000, v12, s5
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v6, 0, v5, s3
v_cndmask_b32_e32 v5, 0, v9, vcc_lo
s_and_b32 vcc_lo, s6, s5
v_and_b32_e32 v9, 1, v0
v_cndmask_b32_e64 v8, 0, v7, s6
v_dual_cndmask_b32 v7, 0, v11 :: v_dual_lshlrev_b32 v0, 3, v0
v_fma_f64 v[3:4], v[5:6], v[3:4], v[5:6]
v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
v_cmp_eq_u32_e64 s3, 0, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[1:2], v[7:8], v[1:2], v[7:8]
v_cmp_class_f64_e64 s2, v[7:8], 0x204
v_cndmask_b32_e64 v9, 0x3ff00000, v10, s3
s_mov_b32 s3, 0x3fdc9f25
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v8, s2
v_cndmask_b32_e64 v1, v1, v7, s2
v_bfi_b32 v4, 0x7fffffff, v4, v9
s_mov_b32 s2, 0xc5bfedd9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], |v[1:2]|, -v[3:4]
v_fma_f64 v[1:2], v[1:2], s[2:3], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f64_e32 v[1:2], v[1:2]
v_ldexp_f64 v[3:4], v[1:2], 0xffffffe0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f64_e32 v[3:4], v[3:4]
v_fma_f64 v[1:2], v[3:4], 0xc1f00000, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f64_e32 v1, v[1:2]
v_cvt_i32_f64_e32 v2, v[3:4]
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fibPx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fibPx, .Lfunc_end0-_Z3fibPx
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fibPx
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z3fibPx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001c5d0_00000000-6_fab_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fibPxPx
.type _Z22__device_stub__Z3fibPxPx, @function
_Z22__device_stub__Z3fibPxPx:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fibPx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z3fibPxPx, .-_Z22__device_stub__Z3fibPxPx
.globl _Z3fibPx
.type _Z3fibPx, @function
_Z3fibPx:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fibPxPx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fibPx, .-_Z3fibPx
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lld\n"
.LC1:
.string "%lld "
.LC2:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
movslq 4(%rsp), %rsi
salq $3, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
movslq 4(%rsp), %rdx
salq $3, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
leaq res(%rip), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .L13
movl $0, %ebx
leaq res(%rip), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L15:
movq 0(%r13,%rbx,8), %rdx
subl $1, %eax
cmpl %ebx, %eax
movq %rbp, %rsi
cmovne %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L15
.L13:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3fibPxPx
jmp .L12
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3fibPx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fibPx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res
.bss
.align 32
.type res, @object
.size res, 512
res:
.zero 512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fab_cuda.hip"
.globl _Z18__device_stub__fibPx # -- Begin function _Z18__device_stub__fibPx
.p2align 4, 0x90
.type _Z18__device_stub__fibPx,@function
_Z18__device_stub__fibPx: # @_Z18__device_stub__fibPx
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fibPx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fibPx, .Lfunc_end0-_Z18__device_stub__fibPx
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3fibPx, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $3, %rdx
movl $res, %edi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.3: # %.lr.ph.preheader
xorl %ebx, %ebx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movq res(,%rbx,8), %rsi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jge .LBB1_7
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.1, %edi
cmpq %rax, %rbx
je .LBB1_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movl $.L.str.2, %edi
jmp .LBB1_6
.LBB1_7: # %._crit_edge
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fibPx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type res,@object # @res
.bss
.globl res
.p2align 4, 0x0
res:
.zero 512
.size res, 512
.type _Z3fibPx,@object # @_Z3fibPx
.section .rodata,"a",@progbits
.globl _Z3fibPx
.p2align 3, 0x0
_Z3fibPx:
.quad _Z18__device_stub__fibPx
.size _Z3fibPx, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lld\n"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lld "
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3fibPx"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fibPx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym res
.addrsig_sym _Z3fibPx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Babak Poursartip
// 09/15/2020
// udemy CUDA
// sum array
#include "common.h"
#include <cstdio>
#include <time.h>
// =================================
__global__ void sum_array_gpu(int *a, int *b, int *c, const int size) {
// 1d grid, 1d block thread
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
c[gid] = a[gid] + b[gid];
}
}
// =================================
void sum_array_cpu(int *a, int *b, int *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// =================================
int main() {
printf(" starts ... \n");
int size = 10000;
int block_size = 128;
const int NO_BYTES = size * sizeof(int);
int *h_a, *h_b, *h_output, *h_cpu_out;
// allocate arrays on the host
h_a = (int *)malloc(NO_BYTES);
h_b = (int *)malloc(NO_BYTES);
h_output = (int *)malloc(NO_BYTES);
h_cpu_out = (int *)malloc(NO_BYTES);
// initialize arrays on the host
time_t t;
srand((unsigned)time(&t));
for (int i = 0; i < size; ++i) {
h_a[i] = (int)(rand() & 0xFF);
}
for (int i = 0; i < size; ++i) {
h_b[i] = (int)(rand() & 0xFF);
}
memset(h_output, 0, NO_BYTES);
memset(h_cpu_out, 0, NO_BYTES);
sum_array_cpu(h_a, h_b, h_cpu_out, size);
// device arrays;
int *d_a, *d_b, *d_output;
cudaMalloc((void **)&d_a, NO_BYTES);
cudaMalloc((void **)&d_b, NO_BYTES);
cudaMalloc((void **)&d_output, NO_BYTES);
cudaMemcpy(d_a, h_a, NO_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, NO_BYTES, cudaMemcpyHostToDevice);
dim3 block(block_size);
// +1 to guarantee that we have more threads than array size
dim3 grid(size / block.x + 1);
sum_array_gpu<<<grid, block>>>(d_a, d_b, d_output, size);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, NO_BYTES, cudaMemcpyDeviceToHost);
// comparison the results of cpu and gpu
compare_arrays(h_output, h_cpu_out, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_output);
free(h_a);
free(h_b);
free(h_output);
cudaDeviceReset();
printf(" finished. \n");
return 0;
} | code for sm_80
Function : _Z13sum_array_gpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Babak Poursartip
// 09/15/2020
// udemy CUDA
// sum array
#include "common.h"
#include <cstdio>
#include <time.h>
// =================================
__global__ void sum_array_gpu(int *a, int *b, int *c, const int size) {
// 1d grid, 1d block thread
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
c[gid] = a[gid] + b[gid];
}
}
// =================================
void sum_array_cpu(int *a, int *b, int *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// =================================
int main() {
printf(" starts ... \n");
int size = 10000;
int block_size = 128;
const int NO_BYTES = size * sizeof(int);
int *h_a, *h_b, *h_output, *h_cpu_out;
// allocate arrays on the host
h_a = (int *)malloc(NO_BYTES);
h_b = (int *)malloc(NO_BYTES);
h_output = (int *)malloc(NO_BYTES);
h_cpu_out = (int *)malloc(NO_BYTES);
// initialize arrays on the host
time_t t;
srand((unsigned)time(&t));
for (int i = 0; i < size; ++i) {
h_a[i] = (int)(rand() & 0xFF);
}
for (int i = 0; i < size; ++i) {
h_b[i] = (int)(rand() & 0xFF);
}
memset(h_output, 0, NO_BYTES);
memset(h_cpu_out, 0, NO_BYTES);
sum_array_cpu(h_a, h_b, h_cpu_out, size);
// device arrays;
int *d_a, *d_b, *d_output;
cudaMalloc((void **)&d_a, NO_BYTES);
cudaMalloc((void **)&d_b, NO_BYTES);
cudaMalloc((void **)&d_output, NO_BYTES);
cudaMemcpy(d_a, h_a, NO_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, NO_BYTES, cudaMemcpyHostToDevice);
dim3 block(block_size);
// +1 to guarantee that we have more threads than array size
dim3 grid(size / block.x + 1);
sum_array_gpu<<<grid, block>>>(d_a, d_b, d_output, size);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, NO_BYTES, cudaMemcpyDeviceToHost);
// comparison the results of cpu and gpu
compare_arrays(h_output, h_cpu_out, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_output);
free(h_a);
free(h_b);
free(h_output);
cudaDeviceReset();
printf(" finished. \n");
return 0;
} | .file "tmpxft_00026b11_00000000-6_7_sum_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13sum_array_cpuPiS_S_i
.type _Z13sum_array_cpuPiS_S_i, @function
_Z13sum_array_cpuPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13sum_array_cpuPiS_S_i, .-_Z13sum_array_cpuPiS_S_i
.globl _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sum_array_gpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
.globl _Z13sum_array_gpuPiS_S_i
.type _Z13sum_array_gpuPiS_S_i, @function
_Z13sum_array_gpuPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13sum_array_gpuPiS_S_i, .-_Z13sum_array_gpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " starts ... \n"
.LC1:
.string " finished. \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movl $40000, %edi
call malloc@PLT
movq %rax, %r14
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %rbp, %rbx
leaq 40000(%rbp), %r15
.L16:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r15, %rbx
jne .L16
movq %r12, %rbx
leaq 40000(%r12), %r15
.L17:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r15, %rbx
jne .L17
movl $40000, %edx
movl $0, %esi
movq %r13, %rdi
call memset@PLT
movl $40000, %edx
movl $0, %esi
movq %r14, %rdi
call memset@PLT
movl $10000, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z13sum_array_cpuPiS_S_i
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $79, 44(%rsp)
movl $1, 48(%rsp)
movl $128, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $10000, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z14compare_arraysPKiS0_i@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
call cudaDeviceReset@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $10000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13sum_array_gpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sum_array_gpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Babak Poursartip
// 09/15/2020
// udemy CUDA
// sum array
#include "common.h"
#include <cstdio>
#include <time.h>
// =================================
__global__ void sum_array_gpu(int *a, int *b, int *c, const int size) {
// 1d grid, 1d block thread
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
c[gid] = a[gid] + b[gid];
}
}
// =================================
void sum_array_cpu(int *a, int *b, int *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// =================================
int main() {
printf(" starts ... \n");
int size = 10000;
int block_size = 128;
const int NO_BYTES = size * sizeof(int);
int *h_a, *h_b, *h_output, *h_cpu_out;
// allocate arrays on the host
h_a = (int *)malloc(NO_BYTES);
h_b = (int *)malloc(NO_BYTES);
h_output = (int *)malloc(NO_BYTES);
h_cpu_out = (int *)malloc(NO_BYTES);
// initialize arrays on the host
time_t t;
srand((unsigned)time(&t));
for (int i = 0; i < size; ++i) {
h_a[i] = (int)(rand() & 0xFF);
}
for (int i = 0; i < size; ++i) {
h_b[i] = (int)(rand() & 0xFF);
}
memset(h_output, 0, NO_BYTES);
memset(h_cpu_out, 0, NO_BYTES);
sum_array_cpu(h_a, h_b, h_cpu_out, size);
// device arrays;
int *d_a, *d_b, *d_output;
cudaMalloc((void **)&d_a, NO_BYTES);
cudaMalloc((void **)&d_b, NO_BYTES);
cudaMalloc((void **)&d_output, NO_BYTES);
cudaMemcpy(d_a, h_a, NO_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, NO_BYTES, cudaMemcpyHostToDevice);
dim3 block(block_size);
// +1 to guarantee that we have more threads than array size
dim3 grid(size / block.x + 1);
sum_array_gpu<<<grid, block>>>(d_a, d_b, d_output, size);
cudaDeviceSynchronize();
cudaMemcpy(h_output, d_output, NO_BYTES, cudaMemcpyDeviceToHost);
// comparison the results of cpu and gpu
compare_arrays(h_output, h_cpu_out, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_output);
free(h_a);
free(h_b);
free(h_output);
cudaDeviceReset();
printf(" finished. \n");
return 0;
} | // Babak Poursartip
// 09/15/2020
// udemy CUDA
// sum array
#include <hip/hip_runtime.h>
#include "common.h"
#include <cstdio>
#include <time.h>
// =================================
__global__ void sum_array_gpu(int *a, int *b, int *c, const int size) {
// 1d grid, 1d block thread
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
c[gid] = a[gid] + b[gid];
}
}
// =================================
void sum_array_cpu(int *a, int *b, int *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// =================================
int main() {
printf(" starts ... \n");
int size = 10000;
int block_size = 128;
const int NO_BYTES = size * sizeof(int);
int *h_a, *h_b, *h_output, *h_cpu_out;
// allocate arrays on the host
h_a = (int *)malloc(NO_BYTES);
h_b = (int *)malloc(NO_BYTES);
h_output = (int *)malloc(NO_BYTES);
h_cpu_out = (int *)malloc(NO_BYTES);
// initialize arrays on the host
time_t t;
srand((unsigned)time(&t));
for (int i = 0; i < size; ++i) {
h_a[i] = (int)(rand() & 0xFF);
}
for (int i = 0; i < size; ++i) {
h_b[i] = (int)(rand() & 0xFF);
}
memset(h_output, 0, NO_BYTES);
memset(h_cpu_out, 0, NO_BYTES);
sum_array_cpu(h_a, h_b, h_cpu_out, size);
// device arrays;
int *d_a, *d_b, *d_output;
hipMalloc((void **)&d_a, NO_BYTES);
hipMalloc((void **)&d_b, NO_BYTES);
hipMalloc((void **)&d_output, NO_BYTES);
hipMemcpy(d_a, h_a, NO_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, NO_BYTES, hipMemcpyHostToDevice);
dim3 block(block_size);
// +1 to guarantee that we have more threads than array size
dim3 grid(size / block.x + 1);
sum_array_gpu<<<grid, block>>>(d_a, d_b, d_output, size);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, NO_BYTES, hipMemcpyDeviceToHost);
// comparison the results of cpu and gpu
compare_arrays(h_output, h_cpu_out, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_output);
free(h_a);
free(h_b);
free(h_output);
hipDeviceReset();
printf(" finished. \n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Babak Poursartip
// 09/15/2020
// udemy CUDA
// sum array
#include <hip/hip_runtime.h>
#include "common.h"
#include <cstdio>
#include <time.h>
// =================================
__global__ void sum_array_gpu(int *a, int *b, int *c, const int size) {
// 1d grid, 1d block thread
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
c[gid] = a[gid] + b[gid];
}
}
// =================================
void sum_array_cpu(int *a, int *b, int *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// =================================
int main() {
printf(" starts ... \n");
int size = 10000;
int block_size = 128;
const int NO_BYTES = size * sizeof(int);
int *h_a, *h_b, *h_output, *h_cpu_out;
// allocate arrays on the host
h_a = (int *)malloc(NO_BYTES);
h_b = (int *)malloc(NO_BYTES);
h_output = (int *)malloc(NO_BYTES);
h_cpu_out = (int *)malloc(NO_BYTES);
// initialize arrays on the host
time_t t;
srand((unsigned)time(&t));
for (int i = 0; i < size; ++i) {
h_a[i] = (int)(rand() & 0xFF);
}
for (int i = 0; i < size; ++i) {
h_b[i] = (int)(rand() & 0xFF);
}
memset(h_output, 0, NO_BYTES);
memset(h_cpu_out, 0, NO_BYTES);
sum_array_cpu(h_a, h_b, h_cpu_out, size);
// device arrays;
int *d_a, *d_b, *d_output;
hipMalloc((void **)&d_a, NO_BYTES);
hipMalloc((void **)&d_b, NO_BYTES);
hipMalloc((void **)&d_output, NO_BYTES);
hipMemcpy(d_a, h_a, NO_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, NO_BYTES, hipMemcpyHostToDevice);
dim3 block(block_size);
// +1 to guarantee that we have more threads than array size
dim3 grid(size / block.x + 1);
sum_array_gpu<<<grid, block>>>(d_a, d_b, d_output, size);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, NO_BYTES, hipMemcpyDeviceToHost);
// comparison the results of cpu and gpu
compare_arrays(h_output, h_cpu_out, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_output);
free(h_a);
free(h_b);
free(h_output);
hipDeviceReset();
printf(" finished. \n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13sum_array_gpuPiS_S_i
.globl _Z13sum_array_gpuPiS_S_i
.p2align 8
.type _Z13sum_array_gpuPiS_S_i,@function
_Z13sum_array_gpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sum_array_gpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13sum_array_gpuPiS_S_i, .Lfunc_end0-_Z13sum_array_gpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sum_array_gpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sum_array_gpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Babak Poursartip
// 09/15/2020
// udemy CUDA
// sum array
#include <hip/hip_runtime.h>
#include "common.h"
#include <cstdio>
#include <time.h>
// =================================
__global__ void sum_array_gpu(int *a, int *b, int *c, const int size) {
// 1d grid, 1d block thread
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size) {
c[gid] = a[gid] + b[gid];
}
}
// =================================
void sum_array_cpu(int *a, int *b, int *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// =================================
int main() {
printf(" starts ... \n");
int size = 10000;
int block_size = 128;
const int NO_BYTES = size * sizeof(int);
int *h_a, *h_b, *h_output, *h_cpu_out;
// allocate arrays on the host
h_a = (int *)malloc(NO_BYTES);
h_b = (int *)malloc(NO_BYTES);
h_output = (int *)malloc(NO_BYTES);
h_cpu_out = (int *)malloc(NO_BYTES);
// initialize arrays on the host
time_t t;
srand((unsigned)time(&t));
for (int i = 0; i < size; ++i) {
h_a[i] = (int)(rand() & 0xFF);
}
for (int i = 0; i < size; ++i) {
h_b[i] = (int)(rand() & 0xFF);
}
memset(h_output, 0, NO_BYTES);
memset(h_cpu_out, 0, NO_BYTES);
sum_array_cpu(h_a, h_b, h_cpu_out, size);
// device arrays;
int *d_a, *d_b, *d_output;
hipMalloc((void **)&d_a, NO_BYTES);
hipMalloc((void **)&d_b, NO_BYTES);
hipMalloc((void **)&d_output, NO_BYTES);
hipMemcpy(d_a, h_a, NO_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, NO_BYTES, hipMemcpyHostToDevice);
dim3 block(block_size);
// +1 to guarantee that we have more threads than array size
dim3 grid(size / block.x + 1);
sum_array_gpu<<<grid, block>>>(d_a, d_b, d_output, size);
hipDeviceSynchronize();
hipMemcpy(h_output, d_output, NO_BYTES, hipMemcpyDeviceToHost);
// comparison the results of cpu and gpu
compare_arrays(h_output, h_cpu_out, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_output);
free(h_a);
free(h_b);
free(h_output);
hipDeviceReset();
printf(" finished. \n");
return 0;
} | .text
.file "7_sum_array.hip"
.globl _Z28__device_stub__sum_array_gpuPiS_S_i # -- Begin function _Z28__device_stub__sum_array_gpuPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__sum_array_gpuPiS_S_i,@function
_Z28__device_stub__sum_array_gpuPiS_S_i: # @_Z28__device_stub__sum_array_gpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sum_array_gpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__sum_array_gpuPiS_S_i, .Lfunc_end0-_Z28__device_stub__sum_array_gpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13sum_array_cpuPiS_S_i # -- Begin function _Z13sum_array_cpuPiS_S_i
.p2align 4, 0x90
.type _Z13sum_array_cpuPiS_S_i,@function
_Z13sum_array_cpuPiS_S_i: # @_Z13sum_array_cpuPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13sum_array_cpuPiS_S_i, .Lfunc_end1-_Z13sum_array_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r12
leaq 152(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_3
# %bb.4:
xorl %r13d, %r13d
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $40000, %edx # imm = 0x9C40
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %eax
addl (%rbx,%r13,4), %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_5
# %bb.6: # %_Z13sum_array_cpuPiS_S_i.exit
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 24(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967375, %rdi # imm = 0x10000004F
leaq 49(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 36(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13sum_array_gpuPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %rdi
movq %r12, %rsi
movl $10000, %edx # imm = 0x2710
callq _Z14compare_arraysPKiS0_i
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sum_array_gpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13sum_array_gpuPiS_S_i,@object # @_Z13sum_array_gpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13sum_array_gpuPiS_S_i
.p2align 3, 0x0
_Z13sum_array_gpuPiS_S_i:
.quad _Z28__device_stub__sum_array_gpuPiS_S_i
.size _Z13sum_array_gpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13sum_array_gpuPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " starts ... "
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " finished. "
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__sum_array_gpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13sum_array_gpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13sum_array_gpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13sum_array_gpuPiS_S_i
.globl _Z13sum_array_gpuPiS_S_i
.p2align 8
.type _Z13sum_array_gpuPiS_S_i,@function
_Z13sum_array_gpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sum_array_gpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13sum_array_gpuPiS_S_i, .Lfunc_end0-_Z13sum_array_gpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sum_array_gpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sum_array_gpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00026b11_00000000-6_7_sum_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13sum_array_cpuPiS_S_i
.type _Z13sum_array_cpuPiS_S_i, @function
_Z13sum_array_cpuPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13sum_array_cpuPiS_S_i, .-_Z13sum_array_cpuPiS_S_i
.globl _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sum_array_gpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
.globl _Z13sum_array_gpuPiS_S_i
.type _Z13sum_array_gpuPiS_S_i, @function
_Z13sum_array_gpuPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13sum_array_gpuPiS_S_i, .-_Z13sum_array_gpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " starts ... \n"
.LC1:
.string " finished. \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movl $40000, %edi
call malloc@PLT
movq %rax, %r14
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %rbp, %rbx
leaq 40000(%rbp), %r15
.L16:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r15, %rbx
jne .L16
movq %r12, %rbx
leaq 40000(%r12), %r15
.L17:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r15, %rbx
jne .L17
movl $40000, %edx
movl $0, %esi
movq %r13, %rdi
call memset@PLT
movl $40000, %edx
movl $0, %esi
movq %r14, %rdi
call memset@PLT
movl $10000, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z13sum_array_cpuPiS_S_i
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $79, 44(%rsp)
movl $1, 48(%rsp)
movl $128, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $10000, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z14compare_arraysPKiS0_i@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
call cudaDeviceReset@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $10000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13sum_array_gpuPiS_S_iPiS_S_i
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13sum_array_gpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sum_array_gpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "7_sum_array.hip"
.globl _Z28__device_stub__sum_array_gpuPiS_S_i # -- Begin function _Z28__device_stub__sum_array_gpuPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__sum_array_gpuPiS_S_i,@function
_Z28__device_stub__sum_array_gpuPiS_S_i: # @_Z28__device_stub__sum_array_gpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sum_array_gpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__sum_array_gpuPiS_S_i, .Lfunc_end0-_Z28__device_stub__sum_array_gpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13sum_array_cpuPiS_S_i # -- Begin function _Z13sum_array_cpuPiS_S_i
.p2align 4, 0x90
.type _Z13sum_array_cpuPiS_S_i,@function
_Z13sum_array_cpuPiS_S_i: # @_Z13sum_array_cpuPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13sum_array_cpuPiS_S_i, .Lfunc_end1-_Z13sum_array_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r12
leaq 152(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_3
# %bb.4:
xorl %r13d, %r13d
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $40000, %edx # imm = 0x9C40
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %eax
addl (%rbx,%r13,4), %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB2_5
# %bb.6: # %_Z13sum_array_cpuPiS_S_i.exit
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 24(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967375, %rdi # imm = 0x10000004F
leaq 49(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 36(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13sum_array_gpuPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %rdi
movq %r12, %rsi
movl $10000, %edx # imm = 0x2710
callq _Z14compare_arraysPKiS0_i
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sum_array_gpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13sum_array_gpuPiS_S_i,@object # @_Z13sum_array_gpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13sum_array_gpuPiS_S_i
.p2align 3, 0x0
_Z13sum_array_gpuPiS_S_i:
.quad _Z28__device_stub__sum_array_gpuPiS_S_i
.size _Z13sum_array_gpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13sum_array_gpuPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " starts ... "
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " finished. "
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__sum_array_gpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13sum_array_gpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define BLOCK_SIZE 16
/*
* prints matrices
* Because matrices filled with dummy 0s function takes 3 dim arguments:
* actual x and y dimension and dim as big square matrix's dimension
*/
__global__ void multiply(float *left, float *right, float *res, int dim) {
int i,j;
float temp = 0;
__shared__ float Left_shared_t [BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Right_shared_t[BLOCK_SIZE][BLOCK_SIZE];
// Row i of matrix left
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int tileNUM = 0; tileNUM < gridDim.x; tileNUM++) {
// Column j of matrix left
j = tileNUM * BLOCK_SIZE + threadIdx.x;
i = tileNUM * BLOCK_SIZE + threadIdx.y;
// Load left[i][j] to shared mem
Left_shared_t[threadIdx.y][threadIdx.x] = left[row * dim + j];// Coalesced access
// Load right[i][j] to shared mem
Right_shared_t[threadIdx.y][threadIdx.x] = right[i * dim + col]; // Coalesced access
// Synchronize before computation
__syncthreads();
// Accumulate one tile of res from tiles of left and right in shared mem
for (int k = 0; k < BLOCK_SIZE; k++) {
temp += Left_shared_t[threadIdx.y][k] * Right_shared_t[k][threadIdx.x]; //no shared memory bank conflict
}
// Synchronize
__syncthreads();
}
// Store accumulated value to res
res[row * dim + col] = temp;
} | .file "tmpxft_001b2125_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i
.globl _Z8multiplyPfS_S_i
.type _Z8multiplyPfS_S_i, @function
_Z8multiplyPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8multiplyPfS_S_i, .-_Z8multiplyPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8multiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define BLOCK_SIZE 16
/*
* prints matrices
* Because matrices filled with dummy 0s function takes 3 dim arguments:
* actual x and y dimension and dim as big square matrix's dimension
*/
__global__ void multiply(float *left, float *right, float *res, int dim) {
int i,j;
float temp = 0;
__shared__ float Left_shared_t [BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Right_shared_t[BLOCK_SIZE][BLOCK_SIZE];
// Row i of matrix left
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int tileNUM = 0; tileNUM < gridDim.x; tileNUM++) {
// Column j of matrix left
j = tileNUM * BLOCK_SIZE + threadIdx.x;
i = tileNUM * BLOCK_SIZE + threadIdx.y;
// Load left[i][j] to shared mem
Left_shared_t[threadIdx.y][threadIdx.x] = left[row * dim + j];// Coalesced access
// Load right[i][j] to shared mem
Right_shared_t[threadIdx.y][threadIdx.x] = right[i * dim + col]; // Coalesced access
// Synchronize before computation
__syncthreads();
// Accumulate one tile of res from tiles of left and right in shared mem
for (int k = 0; k < BLOCK_SIZE; k++) {
temp += Left_shared_t[threadIdx.y][k] * Right_shared_t[k][threadIdx.x]; //no shared memory bank conflict
}
// Synchronize
__syncthreads();
}
// Store accumulated value to res
res[row * dim + col] = temp;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
/*
* prints matrices
* Because matrices filled with dummy 0s function takes 3 dim arguments:
* actual x and y dimension and dim as big square matrix's dimension
*/
__global__ void multiply(float *left, float *right, float *res, int dim) {
int i,j;
float temp = 0;
__shared__ float Left_shared_t [BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Right_shared_t[BLOCK_SIZE][BLOCK_SIZE];
// Row i of matrix left
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int tileNUM = 0; tileNUM < gridDim.x; tileNUM++) {
// Column j of matrix left
j = tileNUM * BLOCK_SIZE + threadIdx.x;
i = tileNUM * BLOCK_SIZE + threadIdx.y;
// Load left[i][j] to shared mem
Left_shared_t[threadIdx.y][threadIdx.x] = left[row * dim + j];// Coalesced access
// Load right[i][j] to shared mem
Right_shared_t[threadIdx.y][threadIdx.x] = right[i * dim + col]; // Coalesced access
// Synchronize before computation
__syncthreads();
// Accumulate one tile of res from tiles of left and right in shared mem
for (int k = 0; k < BLOCK_SIZE; k++) {
temp += Left_shared_t[threadIdx.y][k] * Right_shared_t[k][threadIdx.x]; //no shared memory bank conflict
}
// Synchronize
__syncthreads();
}
// Store accumulated value to res
res[row * dim + col] = temp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
/*
* prints matrices
* Because matrices filled with dummy 0s function takes 3 dim arguments:
* actual x and y dimension and dim as big square matrix's dimension
*/
__global__ void multiply(float *left, float *right, float *res, int dim) {
int i,j;
float temp = 0;
__shared__ float Left_shared_t [BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Right_shared_t[BLOCK_SIZE][BLOCK_SIZE];
// Row i of matrix left
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int tileNUM = 0; tileNUM < gridDim.x; tileNUM++) {
// Column j of matrix left
j = tileNUM * BLOCK_SIZE + threadIdx.x;
i = tileNUM * BLOCK_SIZE + threadIdx.y;
// Load left[i][j] to shared mem
Left_shared_t[threadIdx.y][threadIdx.x] = left[row * dim + j];// Coalesced access
// Load right[i][j] to shared mem
Right_shared_t[threadIdx.y][threadIdx.x] = right[i * dim + col]; // Coalesced access
// Synchronize before computation
__syncthreads();
// Accumulate one tile of res from tiles of left and right in shared mem
for (int k = 0; k < BLOCK_SIZE; k++) {
temp += Left_shared_t[threadIdx.y][k] * Right_shared_t[k][threadIdx.x]; //no shared memory bank conflict
}
// Synchronize
__syncthreads();
}
// Store accumulated value to res
res[row * dim + col] = temp;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPfS_S_i
.globl _Z8multiplyPfS_S_i
.p2align 8
.type _Z8multiplyPfS_S_i,@function
_Z8multiplyPfS_S_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s5, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s4, v[6:7]
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0x400, v2
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v7, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v6, v8, v7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v10, s9, v3
v_add_nc_u32_e32 v9, s9, v4
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v10, s2, v[1:2]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v2, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPfS_S_i, .Lfunc_end0-_Z8multiplyPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
/*
* prints matrices
* Because matrices filled with dummy 0s function takes 3 dim arguments:
* actual x and y dimension and dim as big square matrix's dimension
*/
__global__ void multiply(float *left, float *right, float *res, int dim) {
int i,j;
float temp = 0;
__shared__ float Left_shared_t [BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Right_shared_t[BLOCK_SIZE][BLOCK_SIZE];
// Row i of matrix left
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int tileNUM = 0; tileNUM < gridDim.x; tileNUM++) {
// Column j of matrix left
j = tileNUM * BLOCK_SIZE + threadIdx.x;
i = tileNUM * BLOCK_SIZE + threadIdx.y;
// Load left[i][j] to shared mem
Left_shared_t[threadIdx.y][threadIdx.x] = left[row * dim + j];// Coalesced access
// Load right[i][j] to shared mem
Right_shared_t[threadIdx.y][threadIdx.x] = right[i * dim + col]; // Coalesced access
// Synchronize before computation
__syncthreads();
// Accumulate one tile of res from tiles of left and right in shared mem
for (int k = 0; k < BLOCK_SIZE; k++) {
temp += Left_shared_t[threadIdx.y][k] * Right_shared_t[k][threadIdx.x]; //no shared memory bank conflict
}
// Synchronize
__syncthreads();
}
// Store accumulated value to res
res[row * dim + col] = temp;
} | .text
.file "multiply.hip"
.globl _Z23__device_stub__multiplyPfS_S_i # -- Begin function _Z23__device_stub__multiplyPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPfS_S_i,@function
_Z23__device_stub__multiplyPfS_S_i: # @_Z23__device_stub__multiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPfS_S_i, .Lfunc_end0-_Z23__device_stub__multiplyPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPfS_S_i,@object # @_Z8multiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_S_i
.p2align 3, 0x0
_Z8multiplyPfS_S_i:
.quad _Z23__device_stub__multiplyPfS_S_i
.size _Z8multiplyPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8multiplyPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2125_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i
.globl _Z8multiplyPfS_S_i
.type _Z8multiplyPfS_S_i, @function
_Z8multiplyPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8multiplyPfS_S_i, .-_Z8multiplyPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8multiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiply.hip"
.globl _Z23__device_stub__multiplyPfS_S_i # -- Begin function _Z23__device_stub__multiplyPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPfS_S_i,@function
_Z23__device_stub__multiplyPfS_S_i: # @_Z23__device_stub__multiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPfS_S_i, .Lfunc_end0-_Z23__device_stub__multiplyPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPfS_S_i,@object # @_Z8multiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_S_i
.p2align 3, 0x0
_Z8multiplyPfS_S_i:
.quad _Z23__device_stub__multiplyPfS_S_i
.size _Z8multiplyPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8multiplyPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/extrema.h>
#include <iostream>
#include <cstdlib>
int main(int argc, char *argv[]) {
if (argc < 2 || argc > 2) {
std::cout << "Usage: " << argv[0] << " size\n";
return -1;
}
const size_t len = 1L << (atoi(argv[1]));
thrust::host_vector<int> h_a(len);
srand(0);
clock_t begin = clock();
for (size_t i = 0; i < len; ++i) {
h_a[i] = rand() / (float)RAND_MAX;
}
std::cout << "Elapsed time: "
<< double(clock() - begin) / CLOCKS_PER_SEC * 1000 << " ms\n";
// Copy host_vector to device_vector
thrust::device_vector<int> d_a = h_a;
thrust::min_element(d_a.begin(), d_a.end());
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/extrema.h>
#include <iostream>
#include <cstdlib>
int main(int argc, char *argv[]) {
if (argc < 2 || argc > 2) {
std::cout << "Usage: " << argv[0] << " size\n";
return -1;
}
const size_t len = 1L << (atoi(argv[1]));
thrust::host_vector<int> h_a(len);
srand(0);
clock_t begin = clock();
for (size_t i = 0; i < len; ++i) {
h_a[i] = rand() / (float)RAND_MAX;
}
std::cout << "Elapsed time: "
<< double(clock() - begin) / CLOCKS_PER_SEC * 1000 << " ms\n";
// Copy host_vector to device_vector
thrust::device_vector<int> d_a = h_a;
thrust::min_element(d_a.begin(), d_a.end());
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main(void)
{
printf("HOLA MUNDO\n");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main(void)
{
printf("HOLA MUNDO\n");
} | .file "tmpxft_0013a2b5_00000000-6_programa1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "HOLA MUNDO\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
int main(void)
{
printf("HOLA MUNDO\n");
} | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(void)
{
printf("HOLA MUNDO\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(void)
{
printf("HOLA MUNDO\n");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(void)
{
printf("HOLA MUNDO\n");
} | .text
.file "programa1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "HOLA MUNDO"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a2b5_00000000-6_programa1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "HOLA MUNDO\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "programa1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "HOLA MUNDO"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_rndwr_kernel(int *buffer, size_t reps, size_t steps, size_t elements)
{
// we don't want completely random writes here, since the performance would be awful
// instead, let each warp move around randomly, but keep the warp coalesced on 128B-aligned
// accesses
for(size_t j = 0; j < reps; j++) {
// starting point is naturally aligned
size_t p = blockIdx.x * blockDim.x + threadIdx.x;
// if we start outside the block, sit this out (just to keep small runs from crashing)
if(p >= elements) break;
// quadratic stepping via "acceleration" and "velocity"
size_t a = 548191;
size_t v = 24819 + (p >> 5); // velocity has to be different for each warp
for(size_t i = 0; i < steps; i++) {
size_t prev = p;
// delta is multiplied by 32 elements so warp stays converged (velocity is the
// same for all threads in the warp)
p = (p + (v << 5)) % elements;
v = (v + a) % elements;
buffer[prev] = p;
}
}
} | .file "tmpxft_0015b95a_00000000-6_gpu_rndwr_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm
.type _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm, @function
_Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16gpu_rndwr_kernelPimmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm, .-_Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm
.globl _Z16gpu_rndwr_kernelPimmm
.type _Z16gpu_rndwr_kernelPimmm, @function
_Z16gpu_rndwr_kernelPimmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16gpu_rndwr_kernelPimmm, .-_Z16gpu_rndwr_kernelPimmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16gpu_rndwr_kernelPimmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16gpu_rndwr_kernelPimmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_rndwr_kernel(int *buffer, size_t reps, size_t steps, size_t elements)
{
// we don't want completely random writes here, since the performance would be awful
// instead, let each warp move around randomly, but keep the warp coalesced on 128B-aligned
// accesses
for(size_t j = 0; j < reps; j++) {
// starting point is naturally aligned
size_t p = blockIdx.x * blockDim.x + threadIdx.x;
// if we start outside the block, sit this out (just to keep small runs from crashing)
if(p >= elements) break;
// quadratic stepping via "acceleration" and "velocity"
size_t a = 548191;
size_t v = 24819 + (p >> 5); // velocity has to be different for each warp
for(size_t i = 0; i < steps; i++) {
size_t prev = p;
// delta is multiplied by 32 elements so warp stays converged (velocity is the
// same for all threads in the warp)
p = (p + (v << 5)) % elements;
v = (v + a) % elements;
buffer[prev] = p;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_rndwr_kernel(int *buffer, size_t reps, size_t steps, size_t elements)
{
// we don't want completely random writes here, since the performance would be awful
// instead, let each warp move around randomly, but keep the warp coalesced on 128B-aligned
// accesses
for(size_t j = 0; j < reps; j++) {
// starting point is naturally aligned
size_t p = blockIdx.x * blockDim.x + threadIdx.x;
// if we start outside the block, sit this out (just to keep small runs from crashing)
if(p >= elements) break;
// quadratic stepping via "acceleration" and "velocity"
size_t a = 548191;
size_t v = 24819 + (p >> 5); // velocity has to be different for each warp
for(size_t i = 0; i < steps; i++) {
size_t prev = p;
// delta is multiplied by 32 elements so warp stays converged (velocity is the
// same for all threads in the warp)
p = (p + (v << 5)) % elements;
v = (v + a) % elements;
buffer[prev] = p;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_rndwr_kernel(int *buffer, size_t reps, size_t steps, size_t elements)
{
// we don't want completely random writes here, since the performance would be awful
// instead, let each warp move around randomly, but keep the warp coalesced on 128B-aligned
// accesses
for(size_t j = 0; j < reps; j++) {
// starting point is naturally aligned
size_t p = blockIdx.x * blockDim.x + threadIdx.x;
// if we start outside the block, sit this out (just to keep small runs from crashing)
if(p >= elements) break;
// quadratic stepping via "acceleration" and "velocity"
size_t a = 548191;
size_t v = 24819 + (p >> 5); // velocity has to be different for each warp
for(size_t i = 0; i < steps; i++) {
size_t prev = p;
// delta is multiplied by 32 elements so warp stays converged (velocity is the
// same for all threads in the warp)
p = (p + (v << 5)) % elements;
v = (v + a) % elements;
buffer[prev] = p;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16gpu_rndwr_kernelPimmm
.globl _Z16gpu_rndwr_kernelPimmm
.p2align 8
.type _Z16gpu_rndwr_kernelPimmm,@function
_Z16gpu_rndwr_kernelPimmm:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_14
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
v_mov_b32_e32 v4, v1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[3:4]
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
v_lshrrev_b32_e32 v0, 5, v3
s_mov_b64 s[10:11], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, v0, 0x60f3
v_add_co_ci_u32_e64 v6, null, 0, 0, s0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u64 s[6:7], 0
s_cselect_b32 s1, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[10:11], s[2:3]
s_cbranch_scc0 .LBB0_14
.LBB0_4:
v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
s_and_not1_b32 vcc_lo, exec_lo, s1
s_mov_b64 s[12:13], s[6:7]
s_cbranch_vccz .LBB0_6
s_branch .LBB0_3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_add_u32 s12, s12, -1
s_addc_u32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u64 s[12:13], 0
v_add_co_u32 v13, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v8, vcc_lo
v_dual_mov_b32 v7, v11 :: v_dual_mov_b32 v8, v12
global_store_b32 v[13:14], v11, off
s_cbranch_scc0 .LBB0_3
.LBB0_6:
v_lshlrev_b64 v[11:12], 5, v[9:10]
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v11, v7
v_add_co_ci_u32_e32 v13, vcc_lo, v12, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, s5, v13
v_cmpx_ne_u64_e32 0, v[1:2]
s_xor_b32 s14, exec_lo, s0
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v2, s4
v_cvt_f32_u32_e32 v11, s5
s_sub_u32 s0, 0, s4
s_subb_u32 s15, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x4f800000, v11
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x2f800000, v2
v_trunc_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, 0xcf800000, v11
v_cvt_u32_f32_e32 v11, v11
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, s0, v11
v_mul_hi_u32 v14, s0, v2
v_mul_lo_u32 v15, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v14, v12
v_mul_lo_u32 v14, s0, v2
v_add_nc_u32_e32 v12, v12, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v15, v2, v14
v_mul_lo_u32 v16, v2, v12
v_mul_hi_u32 v17, v2, v12
v_mul_hi_u32 v18, v11, v14
v_mul_lo_u32 v14, v11, v14
v_mul_hi_u32 v19, v11, v12
v_mul_lo_u32 v12, v11, v12
v_add_co_u32 v15, vcc_lo, v15, v16
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v15, v14
v_add_co_ci_u32_e32 v14, vcc_lo, v16, v18, vcc_lo
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v14, v12
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v11, vcc_lo, v11, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, s0, v2
v_mul_lo_u32 v15, s15, v2
v_mul_lo_u32 v14, s0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v12, v14
v_mul_lo_u32 v14, s0, v2
v_add_nc_u32_e32 v12, v12, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v15, v2, v14
v_mul_lo_u32 v16, v2, v12
v_mul_hi_u32 v17, v2, v12
v_mul_hi_u32 v18, v11, v14
v_mul_lo_u32 v14, v11, v14
v_mul_hi_u32 v19, v11, v12
v_mul_lo_u32 v12, v11, v12
v_add_co_u32 v15, vcc_lo, v15, v16
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v15, v14
v_add_co_ci_u32_e32 v14, vcc_lo, v16, v18, vcc_lo
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v14, v12
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v18, vcc_lo, v11, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v19, v0, v2
v_mad_u64_u32 v[14:15], null, v13, v2, 0
v_mad_u64_u32 v[11:12], null, v0, v18, 0
v_mad_u64_u32 v[16:17], null, v13, v18, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v19, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v14
v_add_co_ci_u32_e32 v2, vcc_lo, v11, v15, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v16
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v15, s5, v2
v_mad_u64_u32 v[11:12], null, s4, v2, 0
v_mul_lo_u32 v2, s4, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v0, v11
v_add3_u32 v2, v12, v2, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v13, v2
v_subrev_co_ci_u32_e64 v11, s0, s5, v12, vcc_lo
v_sub_co_ci_u32_e32 v2, vcc_lo, v13, v2, vcc_lo
v_sub_co_u32 v12, vcc_lo, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v13, s0, 0, v11, vcc_lo
v_cmp_le_u32_e64 s0, s4, v0
v_subrev_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e64 v14, 0, -1, s0
v_cmp_le_u32_e64 s0, s4, v12
v_cndmask_b32_e64 v17, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v15, 0, -1, s0
v_cmp_le_u32_e64 s0, s5, v13
v_cndmask_b32_e64 v16, 0, -1, s0
v_cmp_eq_u32_e64 s0, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v15, v16, v15, vcc_lo
v_sub_co_u32 v16, vcc_lo, v12, s4
v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v15
v_cndmask_b32_e64 v14, v17, v14, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, v13, v11, vcc_lo
v_cndmask_b32_e32 v13, v12, v16, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v14
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v12, v2, v11 :: v_dual_cndmask_b32 v11, v0, v13
.LBB0_8:
s_and_not1_saveexec_b32 s0, s14
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v2, s4
s_sub_i32 s14, 0, s4
v_mov_b32_e32 v12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v11, s14, v2
v_mul_hi_u32 v11, v2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v11
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s4
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v11, v0, v2, vcc_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v0, vcc_lo, v9, 0x85d5f
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v10, vcc_lo
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, s5, v13
v_cmpx_ne_u64_e32 0, v[1:2]
s_xor_b32 s14, exec_lo, s0
s_cbranch_execz .LBB0_12
v_cvt_f32_u32_e32 v2, s4
v_cvt_f32_u32_e32 v9, s5
s_sub_u32 s0, 0, s4
s_subb_u32 s15, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x4f800000, v9
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, 0x2f800000, v2
v_trunc_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, 0xcf800000, v9
v_cvt_u32_f32_e32 v9, v9
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, s0, v9
v_mul_hi_u32 v14, s0, v2
v_mul_lo_u32 v15, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v14, v10
v_mul_lo_u32 v14, s0, v2
v_add_nc_u32_e32 v10, v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v15, v2, v14
v_mul_lo_u32 v16, v2, v10
v_mul_hi_u32 v17, v2, v10
v_mul_hi_u32 v18, v9, v14
v_mul_lo_u32 v14, v9, v14
v_mul_hi_u32 v19, v9, v10
v_mul_lo_u32 v10, v9, v10
v_add_co_u32 v15, vcc_lo, v15, v16
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v15, v14
v_add_co_ci_u32_e32 v14, vcc_lo, v16, v18, vcc_lo
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v14, v10
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v10
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, s0, v2
v_mul_lo_u32 v15, s15, v2
v_mul_lo_u32 v14, s0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v10, v14
v_mul_lo_u32 v14, s0, v2
v_add_nc_u32_e32 v10, v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v15, v2, v14
v_mul_lo_u32 v16, v2, v10
v_mul_hi_u32 v17, v2, v10
v_mul_hi_u32 v18, v9, v14
v_mul_lo_u32 v14, v9, v14
v_mul_hi_u32 v19, v9, v10
v_mul_lo_u32 v10, v9, v10
v_add_co_u32 v15, vcc_lo, v15, v16
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v15, v14
v_add_co_ci_u32_e32 v14, vcc_lo, v16, v18, vcc_lo
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v14, v10
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v10
v_add_co_ci_u32_e32 v18, vcc_lo, v9, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v19, v0, v2
v_mad_u64_u32 v[14:15], null, v13, v2, 0
v_mad_u64_u32 v[9:10], null, v0, v18, 0
v_mad_u64_u32 v[16:17], null, v13, v18, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v19, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v14
v_add_co_ci_u32_e32 v2, vcc_lo, v9, v15, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v16
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v15, s5, v2
v_mad_u64_u32 v[9:10], null, s4, v2, 0
v_mul_lo_u32 v2, s4, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v0, v9
v_add3_u32 v2, v10, v2, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v13, v2
v_subrev_co_ci_u32_e64 v9, s0, s5, v10, vcc_lo
v_sub_co_ci_u32_e32 v2, vcc_lo, v13, v2, vcc_lo
v_sub_co_u32 v10, vcc_lo, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v13, s0, 0, v9, vcc_lo
v_cmp_le_u32_e64 s0, s4, v0
v_subrev_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e64 v14, 0, -1, s0
v_cmp_le_u32_e64 s0, s4, v10
v_cndmask_b32_e64 v17, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v15, 0, -1, s0
v_cmp_le_u32_e64 s0, s5, v13
v_cndmask_b32_e64 v16, 0, -1, s0
v_cmp_eq_u32_e64 s0, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v15, v16, v15, vcc_lo
v_sub_co_u32 v16, vcc_lo, v10, s4
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v15
v_cndmask_b32_e64 v14, v17, v14, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v13, v9, vcc_lo
v_cndmask_b32_e32 v13, v10, v16, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v2, v9, vcc_lo
v_cndmask_b32_e32 v9, v0, v13, vcc_lo
.LBB0_12:
s_and_not1_saveexec_b32 s0, s14
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v2, s4
s_sub_i32 s14, 0, s4
v_mov_b32_e32 v10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, s14, v2
v_mul_hi_u32 v9, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v9
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s4
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v9, v0, v2, vcc_lo
s_branch .LBB0_5
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16gpu_rndwr_kernelPimmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16gpu_rndwr_kernelPimmm, .Lfunc_end0-_Z16gpu_rndwr_kernelPimmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16gpu_rndwr_kernelPimmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16gpu_rndwr_kernelPimmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_rndwr_kernel(int *buffer, size_t reps, size_t steps, size_t elements)
{
// we don't want completely random writes here, since the performance would be awful
// instead, let each warp move around randomly, but keep the warp coalesced on 128B-aligned
// accesses
for(size_t j = 0; j < reps; j++) {
// starting point is naturally aligned
size_t p = blockIdx.x * blockDim.x + threadIdx.x;
// if we start outside the block, sit this out (just to keep small runs from crashing)
if(p >= elements) break;
// quadratic stepping via "acceleration" and "velocity"
size_t a = 548191;
size_t v = 24819 + (p >> 5); // velocity has to be different for each warp
for(size_t i = 0; i < steps; i++) {
size_t prev = p;
// delta is multiplied by 32 elements so warp stays converged (velocity is the
// same for all threads in the warp)
p = (p + (v << 5)) % elements;
v = (v + a) % elements;
buffer[prev] = p;
}
}
} | .text
.file "gpu_rndwr_kernel.hip"
.globl _Z31__device_stub__gpu_rndwr_kernelPimmm # -- Begin function _Z31__device_stub__gpu_rndwr_kernelPimmm
.p2align 4, 0x90
.type _Z31__device_stub__gpu_rndwr_kernelPimmm,@function
_Z31__device_stub__gpu_rndwr_kernelPimmm: # @_Z31__device_stub__gpu_rndwr_kernelPimmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16gpu_rndwr_kernelPimmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__gpu_rndwr_kernelPimmm, .Lfunc_end0-_Z31__device_stub__gpu_rndwr_kernelPimmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16gpu_rndwr_kernelPimmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16gpu_rndwr_kernelPimmm,@object # @_Z16gpu_rndwr_kernelPimmm
.section .rodata,"a",@progbits
.globl _Z16gpu_rndwr_kernelPimmm
.p2align 3, 0x0
_Z16gpu_rndwr_kernelPimmm:
.quad _Z31__device_stub__gpu_rndwr_kernelPimmm
.size _Z16gpu_rndwr_kernelPimmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16gpu_rndwr_kernelPimmm"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__gpu_rndwr_kernelPimmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16gpu_rndwr_kernelPimmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015b95a_00000000-6_gpu_rndwr_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm
.type _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm, @function
_Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16gpu_rndwr_kernelPimmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm, .-_Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm
.globl _Z16gpu_rndwr_kernelPimmm
.type _Z16gpu_rndwr_kernelPimmm, @function
_Z16gpu_rndwr_kernelPimmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16gpu_rndwr_kernelPimmmPimmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16gpu_rndwr_kernelPimmm, .-_Z16gpu_rndwr_kernelPimmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16gpu_rndwr_kernelPimmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16gpu_rndwr_kernelPimmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_rndwr_kernel.hip"
.globl _Z31__device_stub__gpu_rndwr_kernelPimmm # -- Begin function _Z31__device_stub__gpu_rndwr_kernelPimmm
.p2align 4, 0x90
.type _Z31__device_stub__gpu_rndwr_kernelPimmm,@function
_Z31__device_stub__gpu_rndwr_kernelPimmm: # @_Z31__device_stub__gpu_rndwr_kernelPimmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16gpu_rndwr_kernelPimmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__gpu_rndwr_kernelPimmm, .Lfunc_end0-_Z31__device_stub__gpu_rndwr_kernelPimmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16gpu_rndwr_kernelPimmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16gpu_rndwr_kernelPimmm,@object # @_Z16gpu_rndwr_kernelPimmm
.section .rodata,"a",@progbits
.globl _Z16gpu_rndwr_kernelPimmm
.p2align 3, 0x0
_Z16gpu_rndwr_kernelPimmm:
.quad _Z31__device_stub__gpu_rndwr_kernelPimmm
.size _Z16gpu_rndwr_kernelPimmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16gpu_rndwr_kernelPimmm"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__gpu_rndwr_kernelPimmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16gpu_rndwr_kernelPimmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // CS 4402 - Dana Zagar - 250790176
#include <cstdio>
#include <ctime>
using namespace std;
// A small prime number to prevent overflow and make verification feasible.
const int MAX_COEFF = 103;
// Print polynomial output.
void print_polynomial(int* poly, int range)
{
for (int i = 0; i < range; i++)
{
printf("%2d ", poly[i]);
}
printf("\n\n");
}
// Generates a random polynomial of size n.
void random_polynomial(int* p, int n)
{
for (int i=0; i<n; i++) {
p[i] = rand() % MAX_COEFF;
}
}
// Serial C function to find reduced polynomial product.
// For verification purposes.
void multiply_polynomials_serial(int *x, int *y, int size, int *ans)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
ans[i+j] = (ans[i+j] + x[i] * y[j]) % MAX_COEFF;
}
}
}
// First CUDA kernel to calculate the product terms over two given polynomials
// of size n, given n thread-blocks and n threads per.
__global__ void calculate_products(int *prods, int *x, int *y, size_t n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
prods[index] = (x[blockIdx.x] * y[threadIdx.x]) % MAX_COEFF;
}
// Second CUDA kernel to reduce the products by combining like terms on each
// diagonal of the "2d" product matrix.
__global__ void reduce_polynomial(int *prods, int *ans, size_t n)
{
int i, j;
// Envision the product array as a 2d matrix tilted like a diamond.
// Each block represents a row of the diamond, i.e. a diagonal.
// If the block index is within the first half of the diamond, the
// block index dictates the row index.
if (blockIdx.x <= (2*n-2)/2)
{
i = blockIdx.x, j = 0;
}
// Otherwise, the block index dictates the column index.
else
{
i = n-1, j = (blockIdx.x % n) + 1;
}
// Sum over the diagonal given by the block index.
while (i >= 0 && j < n)
{
ans[blockIdx.x] = (ans[blockIdx.x] + prods[i*n + j]) % MAX_COEFF;
i--;
j++;
}
}
int main() {
srand(time(NULL));
int exponent;
// Input the number of terms.
printf("Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: ");
scanf("%d", &exponent);
if (exponent < 1 || exponent > 10)
{
printf("Invalid input. Program will terminate.\n\n");
return 0;
}
int n = 1 << exponent; // Number of terms is 2^exponent.
printf("%d terms; input polynomials are of degree %d.\n\n", n, n-1);
int *X = NULL; // First polynomial of degree n-1.
int *Y = NULL; // Second polynomial of degree n-1.
int *P = NULL; // Interim products.
int *Poly = NULL; // Final.
int *PolyV = NULL; // Verification answer.
X = new int[n];
Y = new int[n];
P = new int[n*n];
Poly = new int[2*n-1];
PolyV = new int[2*n-1];
// Initialize values.
random_polynomial(X, n);
random_polynomial(Y, n);
for (int i = 0; i < n*n; i++)
{
P[i] = 0;
}
for (int i = 0; i < 2*n-1; i++)
{
Poly[i] = 0;
PolyV[i] = 0;
}
// Step 1: Calculating products.
int *Xd, *Yd, *Pd;
cudaMalloc((void **)&Xd, sizeof(int)*n);
cudaMalloc((void **)&Yd, sizeof(int)*n);
cudaMalloc((void **)&Pd, sizeof(int)*n*n);
cudaMemcpy(Xd, X, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(Yd, Y, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(Pd, P, sizeof(int)*n*n, cudaMemcpyHostToDevice);
calculate_products<<<n, n>>>(Pd, Xd, Yd, n);
// Step 2: Reducing like terms.
int *Polyd;
cudaMalloc((void **)&Polyd, sizeof(int)*2*n-1);
cudaMemcpy(Polyd, Poly, sizeof(int)*2*n-1, cudaMemcpyHostToDevice);
reduce_polynomial<<<2*n-1, 1>>>(Pd, Polyd, n);
cudaMemcpy(Poly, Polyd, sizeof(int)*2*n-1, cudaMemcpyDeviceToHost);
// Print input, output.
printf("CUDA Program Output\n\n");
printf("First input polynomial:\n");
print_polynomial(X, n);
printf("Second input polynomial:\n");
print_polynomial(Y, n);
printf("Result:\n");
print_polynomial(Poly, 2*n-1);
// Step 3: Verify using serial C function.
printf("Verification with Serial C Output\n\n");
multiply_polynomials_serial(X, Y, n, PolyV);
printf("Result:\n");
print_polynomial(PolyV, 2*n-1);
// Free memory.
delete [] X;
delete [] Y;
delete [] P;
delete [] Poly;
delete [] PolyV;
cudaFree(Xd);
cudaFree(Yd);
cudaFree(Pd);
cudaFree(Polyd);
return 0;
} | code for sm_80
Function : _Z17reduce_polynomialPiS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0040*/ ULEA UR4, UP0, UR6, 0xfffffffe, 0x1 ; /* 0xfffffffe06047891 */
/* 0x000fc8000f80083f */
/*0050*/ ULEA.HI.X UR5, UR6, 0xffffffff, UR7, 0x1, UP0 ; /* 0xffffffff06057891 */
/* 0x000fc800080f0c07 */
/*0060*/ USHF.R.U64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001205 */
/*0070*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fcc0008011605 */
/*0080*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fe2000f8e00ff */
/*0090*/ ISETP.LE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf03070 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0000 */
/*00b0*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*00c0*/ @P0 BRA 0x260 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f05070 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R2, 0x110 ; /* 0x0000011000027802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x470 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BRA 0x230 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000209000 */
/*0130*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f25070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0190*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R8, R3, c[0x0][0x170], R0 ; /* 0x00005c0003087a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R8, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008080a10 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fda0003f06070 */
/*0210*/ @P0 IADD3 R8, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008080a10 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P1 LOP3.LUT R8, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff089a12 */
/* 0x000fc600078e33ff */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0250*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0270*/ SHF.R.S32.HI R4, RZ, 0x1f, R8 ; /* 0x0000001fff047819 */
/* 0x000fc80000011408 */
/*0280*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x174], PT, P0 ; /* 0x00005d0004007a0c */
/* 0x000fc80003f06100 */
/*0290*/ ISETP.LT.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000701670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe200078010ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02d0*/ LEA.HI.X R3, R0, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f14ff */
/*02e0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0004 */
/*0300*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe20000011409 */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0008 */
/*0320*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe400078e02ff */
/*0330*/ IMAD.WIDE.U32 R4, R9, c[0x0][0x170], R4 ; /* 0x00005c0009047a25 */
/* 0x000fc800078e0004 */
/*0340*/ IMAD R7, R9, c[0x0][0x174], R0 ; /* 0x00005d0009077a24 */
/* 0x000fe200078e0200 */
/*0350*/ LEA R6, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004067a11 */
/* 0x000fc600078010ff */
/*0360*/ IMAD.IADD R5, R5, 0x1, R7 ; /* 0x0000000105057824 */
/* 0x000fca00078e0207 */
/*0370*/ LEA.HI.X R7, R4, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590004077a11 */
/* 0x000fca00000f1405 */
/*0380*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GT.AND P1, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f24270 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*03c0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3 R11, R6, R11, RZ ; /* 0x0000000b060b7210 */
/* 0x026fca0007ffe0ff */
/*03e0*/ IMAD.HI R0, R11, 0x13e22cbd, RZ ; /* 0x13e22cbd0b007827 */
/* 0x000fca00078e02ff */
/*03f0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*0400*/ LEA.HI.SX32 R0, R0, R5, 0x1d ; /* 0x0000000500007211 */
/* 0x000fe400078feaff */
/*0410*/ SHF.R.S32.HI R5, RZ, 0x1f, R8 ; /* 0x0000001fff057819 */
/* 0x000fc60000011408 */
/*0420*/ IMAD R11, R0, -0x67, R11 ; /* 0xffffff99000b7824 */
/* 0x000fe200078e020b */
/*0430*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fc80003f06100 */
/*0440*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003f2000c101904 */
/*0450*/ @!P0 BRA P1, 0x300 ; /* 0xfffffea000008947 */
/* 0x000fea000083ffff */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ I2F.U64.RP R3, c[0x0][0x170] ; /* 0x00005c0000037b12 */
/* 0x000e300000309000 */
/*0480*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0490*/ IADD3 R4, R3, 0x1ffffffe, RZ ; /* 0x1ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*04a0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*04b0*/ IMAD.WIDE.U32 R6, R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a25 */
/* 0x001fc800078e00ff */
/*04c0*/ IMAD R7, R4, c[0x0][0x174], R7 ; /* 0x00005d0004077a24 */
/* 0x000fe200078e0207 */
/*04d0*/ IADD3 R9, P0, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fc60007f1e0ff */
/*04e0*/ IMAD R7, R5, c[0x0][0x170], R7 ; /* 0x00005c0005077a24 */
/* 0x000fe400078e0207 */
/*04f0*/ IMAD.HI.U32 R6, R4, R9, RZ ; /* 0x0000000904067227 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.X R11, RZ, RZ, ~R7, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e07 */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0520*/ IMAD R13, R5, R11.reuse, RZ ; /* 0x0000000b050d7224 */
/* 0x080fe400078e02ff */
/*0530*/ IMAD.WIDE.U32 R6, P0, R4, R11, R6 ; /* 0x0000000b04067225 */
/* 0x000fc80007800006 */
/*0540*/ IMAD.HI.U32 R3, R5, R11, RZ ; /* 0x0000000b05037227 */
/* 0x000fc800078e00ff */
/*0550*/ IMAD.HI.U32 R6, P1, R5, R9, R6 ; /* 0x0000000905067227 */
/* 0x000fc80007820006 */
/*0560*/ IMAD.X R3, R3, 0x1, R5, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0605 */
/*0570*/ IADD3 R7, P2, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x000fc80007f5e0ff */
/*0580*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fe200017e2403 */
/*0590*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x170], RZ ; /* 0x00005c0007047a25 */
/* 0x000fc800078e00ff */
/*05a0*/ IMAD R6, R7, c[0x0][0x174], R5 ; /* 0x00005d0007067a24 */
/* 0x000fe200078e0205 */
/*05b0*/ IADD3 R5, P0, RZ, -R4, RZ ; /* 0x80000004ff057210 */
/* 0x000fc60007f1e0ff */
/*05c0*/ IMAD R4, R3, c[0x0][0x170], R6 ; /* 0x00005c0003047a24 */
/* 0x000fe400078e0206 */
/*05d0*/ IMAD.HI.U32 R6, R7, R5, RZ ; /* 0x0000000507067227 */
/* 0x000fc800078e00ff */
/*05e0*/ IMAD.X R4, RZ, RZ, ~R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fc800000e0e04 */
/*05f0*/ IMAD.WIDE.U32 R6, P0, R7, R4, R6 ; /* 0x0000000407067225 */
/* 0x000fc80007800006 */
/*0600*/ IMAD R8, R3.reuse, R4, RZ ; /* 0x0000000403087224 */
/* 0x040fe400078e02ff */
/*0610*/ IMAD.HI.U32 R7, P1, R3, R5, R6 ; /* 0x0000000503077227 */
/* 0x000fe20007820006 */
/*0620*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fc600000001ff */
/*0630*/ IMAD.HI.U32 R6, R3, R4, RZ ; /* 0x0000000403067227 */
/* 0x000fe200078e00ff */
/*0640*/ IADD3 R7, P2, R8, R7, RZ ; /* 0x0000000708077210 */
/* 0x000fc60007f5e0ff */
/*0650*/ IMAD.X R3, R6, 0x1, R3, P0 ; /* 0x0000000106037824 */
/* 0x000fe400000e0603 */
/*0660*/ IMAD.HI.U32 R4, R7, R0, RZ ; /* 0x0000000007047227 */
/* 0x000fc600078e00ff */
/*0670*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fc600017e2403 */
/*0680*/ IMAD.WIDE.U32 R4, RZ, R7, R4 ; /* 0x00000007ff047225 */
/* 0x000fcc00078e0004 */
/*0690*/ IMAD.HI.U32 R3, P0, R3, R0, R4 ; /* 0x0000000003037227 */
/* 0x000fca0007800004 */
/*06a0*/ IADD3 R7, P1, RZ, R3, RZ ; /* 0x00000003ff077210 */
/* 0x000fe20007f3e0ff */
/*06b0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fc800000e06ff */
/*06c0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x170], RZ ; /* 0x00005c0007047a25 */
/* 0x000fc800078e00ff */
/*06d0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*06e0*/ IADD3 R8, P1, -R4, R0, RZ ; /* 0x0000000004087210 */
/* 0x000fe20007f3e1ff */
/*06f0*/ IMAD R6, R7, c[0x0][0x174], R5 ; /* 0x00005d0007067a24 */
/* 0x000fc600078e0205 */
/*0700*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe20003f06070 */
/*0710*/ IMAD R3, R3, c[0x0][0x170], R6 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0206 */
/*0720*/ IMAD.X R5, RZ, RZ, ~R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0e03 */
/*0730*/ IADD3 R3, P1, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008037a10 */
/* 0x000fc80007f3e0ff */
/*0740*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x040fe40003f06100 */
/*0750*/ IADD3.X R4, R5, ~c[0x0][0x174], RZ, P1, !PT ; /* 0x80005d0005047a10 */
/* 0x000fe40000ffe4ff */
/*0760*/ SEL R3, R3, R8, P0 ; /* 0x0000000803037207 */
/* 0x000fe40000000000 */
/*0770*/ SEL R4, R4, R5, P0 ; /* 0x0000000504047207 */
/* 0x000fe40000000000 */
/*0780*/ ISETP.GE.U32.AND P0, PT, R3.reuse, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x040fe40003f06070 */
/*0790*/ IADD3 R8, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003087a10 */
/* 0x000fc40007ffe0ff */
/*07a0*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x174], PT, P0 ; /* 0x00005d0004007a0c */
/* 0x000fe40003f06100 */
/*07b0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25070 */
/*07c0*/ SEL R8, R8, R3, P0 ; /* 0x0000000308087207 */
/* 0x000fe20000000000 */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*07e0*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x174], PT, P1 ; /* 0x00005d00ff007a0c */
/* 0x000fc80003f25310 */
/*07f0*/ SEL R8, R8, 0xffffffff, P1 ; /* 0xffffffff08087807 */
/* 0x000fe20000800000 */
/*0800*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7f002007950 */
/* 0x000ff00003c3ffff */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18calculate_productsPiS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e6e0000002100 */
/*0050*/ IMAD.WIDE.U32 R2, R6, R11, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e000b */
/*0060*/ IMAD.WIDE.U32 R4, R9, R11, c[0x0][0x170] ; /* 0x00005c0009047625 */
/* 0x002fe400078e000b */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD R6, R6, c[0x0][0x0], R9 ; /* 0x0000000006067a24 */
/* 0x000fe400078e0209 */
/*00a0*/ IMAD R0, R2, R5, RZ ; /* 0x0000000502007224 */
/* 0x004fc800078e02ff */
/*00b0*/ IMAD.HI R7, R0, 0x13e22cbd, RZ ; /* 0x13e22cbd00077827 */
/* 0x000fca00078e02ff */
/*00c0*/ SHF.R.U32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011607 */
/*00d0*/ LEA.HI.SX32 R9, R7, R8, 0x1d ; /* 0x0000000807097211 */
/* 0x000fe200078feaff */
/*00e0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*00f0*/ IMAD R9, R9, -0x67, R0 ; /* 0xffffff9909097824 */
/* 0x000fca00078e0200 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CS 4402 - Dana Zagar - 250790176
#include <cstdio>
#include <ctime>
using namespace std;
// A small prime number to prevent overflow and make verification feasible.
const int MAX_COEFF = 103;
// Print polynomial output.
void print_polynomial(int* poly, int range)
{
for (int i = 0; i < range; i++)
{
printf("%2d ", poly[i]);
}
printf("\n\n");
}
// Generates a random polynomial of size n.
void random_polynomial(int* p, int n)
{
for (int i=0; i<n; i++) {
p[i] = rand() % MAX_COEFF;
}
}
// Serial C function to find reduced polynomial product.
// For verification purposes.
void multiply_polynomials_serial(int *x, int *y, int size, int *ans)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
ans[i+j] = (ans[i+j] + x[i] * y[j]) % MAX_COEFF;
}
}
}
// First CUDA kernel to calculate the product terms over two given polynomials
// of size n, given n thread-blocks and n threads per.
__global__ void calculate_products(int *prods, int *x, int *y, size_t n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
prods[index] = (x[blockIdx.x] * y[threadIdx.x]) % MAX_COEFF;
}
// Second CUDA kernel to reduce the products by combining like terms on each
// diagonal of the "2d" product matrix.
__global__ void reduce_polynomial(int *prods, int *ans, size_t n)
{
int i, j;
// Envision the product array as a 2d matrix tilted like a diamond.
// Each block represents a row of the diamond, i.e. a diagonal.
// If the block index is within the first half of the diamond, the
// block index dictates the row index.
if (blockIdx.x <= (2*n-2)/2)
{
i = blockIdx.x, j = 0;
}
// Otherwise, the block index dictates the column index.
else
{
i = n-1, j = (blockIdx.x % n) + 1;
}
// Sum over the diagonal given by the block index.
while (i >= 0 && j < n)
{
ans[blockIdx.x] = (ans[blockIdx.x] + prods[i*n + j]) % MAX_COEFF;
i--;
j++;
}
}
int main() {
srand(time(NULL));
int exponent;
// Input the number of terms.
printf("Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: ");
scanf("%d", &exponent);
if (exponent < 1 || exponent > 10)
{
printf("Invalid input. Program will terminate.\n\n");
return 0;
}
int n = 1 << exponent; // Number of terms is 2^exponent.
printf("%d terms; input polynomials are of degree %d.\n\n", n, n-1);
int *X = NULL; // First polynomial of degree n-1.
int *Y = NULL; // Second polynomial of degree n-1.
int *P = NULL; // Interim products.
int *Poly = NULL; // Final.
int *PolyV = NULL; // Verification answer.
X = new int[n];
Y = new int[n];
P = new int[n*n];
Poly = new int[2*n-1];
PolyV = new int[2*n-1];
// Initialize values.
random_polynomial(X, n);
random_polynomial(Y, n);
for (int i = 0; i < n*n; i++)
{
P[i] = 0;
}
for (int i = 0; i < 2*n-1; i++)
{
Poly[i] = 0;
PolyV[i] = 0;
}
// Step 1: Calculating products.
int *Xd, *Yd, *Pd;
cudaMalloc((void **)&Xd, sizeof(int)*n);
cudaMalloc((void **)&Yd, sizeof(int)*n);
cudaMalloc((void **)&Pd, sizeof(int)*n*n);
cudaMemcpy(Xd, X, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(Yd, Y, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(Pd, P, sizeof(int)*n*n, cudaMemcpyHostToDevice);
calculate_products<<<n, n>>>(Pd, Xd, Yd, n);
// Step 2: Reducing like terms.
int *Polyd;
cudaMalloc((void **)&Polyd, sizeof(int)*2*n-1);
cudaMemcpy(Polyd, Poly, sizeof(int)*2*n-1, cudaMemcpyHostToDevice);
reduce_polynomial<<<2*n-1, 1>>>(Pd, Polyd, n);
cudaMemcpy(Poly, Polyd, sizeof(int)*2*n-1, cudaMemcpyDeviceToHost);
// Print input, output.
printf("CUDA Program Output\n\n");
printf("First input polynomial:\n");
print_polynomial(X, n);
printf("Second input polynomial:\n");
print_polynomial(Y, n);
printf("Result:\n");
print_polynomial(Poly, 2*n-1);
// Step 3: Verify using serial C function.
printf("Verification with Serial C Output\n\n");
multiply_polynomials_serial(X, Y, n, PolyV);
printf("Result:\n");
print_polynomial(PolyV, 2*n-1);
// Free memory.
delete [] X;
delete [] Y;
delete [] P;
delete [] Poly;
delete [] PolyV;
cudaFree(Xd);
cudaFree(Yd);
cudaFree(Pd);
cudaFree(Polyd);
return 0;
} | .file "tmpxft_000488ec_00000000-6_dzagar_CS4402_a2q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n\n"
.text
.globl _Z16print_polynomialPii
.type _Z16print_polynomialPii, @function
_Z16print_polynomialPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z16print_polynomialPii, .-_Z16print_polynomialPii
.globl _Z17random_polynomialPii
.type _Z17random_polynomialPii, @function
_Z17random_polynomialPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L13
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L10:
call rand@PLT
movslq %eax, %rdx
imulq $333589693, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $103, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z17random_polynomialPii, .-_Z17random_polynomialPii
.globl _Z27multiply_polynomials_serialPiS_iS_
.type _Z27multiply_polynomials_serialPiS_iS_, @function
_Z27multiply_polynomials_serialPiS_iS_:
.LFB2059:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L22
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r10
movl %edx, %r11d
movq %rcx, %r9
movslq %edx, %rax
leaq (%rsi,%rax,4), %r8
movl $0, %ebx
.L18:
movq %r10, %rsi
movq %r9, %rcx
.L19:
movl (%rdi), %eax
imull (%rsi), %eax
addl (%rcx), %eax
movslq %eax, %rdx
imulq $333589693, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ebp
sarl $31, %ebp
subl %ebp, %edx
imull $103, %edx, %edx
subl %edx, %eax
movl %eax, (%rcx)
addq $4, %rcx
addq $4, %rsi
cmpq %r8, %rsi
jne .L19
addl $1, %ebx
addq $4, %r9
addq $4, %rdi
cmpl %ebx, %r11d
jne .L18
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z27multiply_polynomials_serialPiS_iS_, .-_Z27multiply_polynomials_serialPiS_iS_
.globl _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
.type _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m, @function
_Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18calculate_productsPiS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m, .-_Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
.globl _Z18calculate_productsPiS_S_m
.type _Z18calculate_productsPiS_S_m, @function
_Z18calculate_productsPiS_S_m:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18calculate_productsPiS_S_m, .-_Z18calculate_productsPiS_S_m
.globl _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
.type _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m, @function
_Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17reduce_polynomialPiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m, .-_Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
.globl _Z17reduce_polynomialPiS_m
.type _Z17reduce_polynomialPiS_m, @function
_Z17reduce_polynomialPiS_m:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z17reduce_polynomialPiS_m, .-_Z17reduce_polynomialPiS_m
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: "
.section .rodata.str1.1
.LC3:
.string "%d"
.section .rodata.str1.8
.align 8
.LC4:
.string "Invalid input. Program will terminate.\n\n"
.align 8
.LC5:
.string "%d terms; input polynomials are of degree %d.\n\n"
.section .rodata.str1.1
.LC6:
.string "CUDA Program Output\n\n"
.LC7:
.string "First input polynomial:\n"
.LC8:
.string "Second input polynomial:\n"
.LC9:
.string "Result:\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Verification with Serial C Output\n\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 60(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 60(%rsp), %ebx
leal -1(%rbx), %eax
cmpl $9, %eax
ja .L52
movl $1, %r12d
movl %ebx, %ecx
sall %cl, %r12d
leal -1(%r12), %ecx
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %r14
leaq 0(,%r14,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movl %r12d, %edx
movl %ebx, %ecx
sall %cl, %edx
movl %edx, %eax
cltq
leaq 0(,%rax,4), %rdx
movq %rdx, 32(%rsp)
movq %rdx, %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $2, %eax
movl %eax, %edx
movl %ebx, %ecx
sall %cl, %edx
movl %edx, 44(%rsp)
leal -1(%rdx), %r15d
movslq %r15d, %rax
leaq 0(,%rax,4), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbp
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z17random_polynomialPii
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z17random_polynomialPii
movq 24(%rsp), %rcx
movq %rcx, %rax
movq 32(%rsp), %rdx
addq %rcx, %rdx
.L44:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L44
movl 44(%rsp), %eax
leal -1(%rax), %edx
movl $0, %eax
.L45:
movl $0, (%rbx,%rax,4)
movl $0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %rdx
jne .L45
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movq %r14, %rax
imulq %r14, %rax
salq $2, %rax
leaq 80(%rsp), %rdi
movq %rax, 32(%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r12d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L46:
leaq -1(,%r14,8), %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r15d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L47:
movl $2, %ecx
movq %r13, %rdx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movq 16(%rsp), %r14
movq %r14, %rdi
call _Z16print_polynomialPii
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z16print_polynomialPii
leaq .LC9(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %esi
movq %rbx, %rdi
call _Z16print_polynomialPii
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rcx
movl %r12d, %edx
movq 8(%rsp), %r12
movq %r12, %rsi
movq %r14, %rdi
call _Z27multiply_polynomials_serialPiS_iS_
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %esi
movq %rbp, %rdi
call _Z16print_polynomialPii
movq %r14, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
.L43:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L43
.L53:
movq %r14, %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
jmp .L46
.L54:
movq %r14, %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
jmp .L47
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z17reduce_polynomialPiS_m"
.LC12:
.string "_Z18calculate_productsPiS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reduce_polynomialPiS_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calculate_productsPiS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CS 4402 - Dana Zagar - 250790176
#include <cstdio>
#include <ctime>
using namespace std;
// A small prime number to prevent overflow and make verification feasible.
const int MAX_COEFF = 103;
// Print polynomial output.
void print_polynomial(int* poly, int range)
{
for (int i = 0; i < range; i++)
{
printf("%2d ", poly[i]);
}
printf("\n\n");
}
// Generates a random polynomial of size n.
void random_polynomial(int* p, int n)
{
for (int i=0; i<n; i++) {
p[i] = rand() % MAX_COEFF;
}
}
// Serial C function to find reduced polynomial product.
// For verification purposes.
void multiply_polynomials_serial(int *x, int *y, int size, int *ans)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
ans[i+j] = (ans[i+j] + x[i] * y[j]) % MAX_COEFF;
}
}
}
// First CUDA kernel to calculate the product terms over two given polynomials
// of size n, given n thread-blocks and n threads per.
__global__ void calculate_products(int *prods, int *x, int *y, size_t n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
prods[index] = (x[blockIdx.x] * y[threadIdx.x]) % MAX_COEFF;
}
// Second CUDA kernel to reduce the products by combining like terms on each
// diagonal of the "2d" product matrix.
__global__ void reduce_polynomial(int *prods, int *ans, size_t n)
{
int i, j;
// Envision the product array as a 2d matrix tilted like a diamond.
// Each block represents a row of the diamond, i.e. a diagonal.
// If the block index is within the first half of the diamond, the
// block index dictates the row index.
if (blockIdx.x <= (2*n-2)/2)
{
i = blockIdx.x, j = 0;
}
// Otherwise, the block index dictates the column index.
else
{
i = n-1, j = (blockIdx.x % n) + 1;
}
// Sum over the diagonal given by the block index.
while (i >= 0 && j < n)
{
ans[blockIdx.x] = (ans[blockIdx.x] + prods[i*n + j]) % MAX_COEFF;
i--;
j++;
}
}
int main() {
srand(time(NULL));
int exponent;
// Input the number of terms.
printf("Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: ");
scanf("%d", &exponent);
if (exponent < 1 || exponent > 10)
{
printf("Invalid input. Program will terminate.\n\n");
return 0;
}
int n = 1 << exponent; // Number of terms is 2^exponent.
printf("%d terms; input polynomials are of degree %d.\n\n", n, n-1);
int *X = NULL; // First polynomial of degree n-1.
int *Y = NULL; // Second polynomial of degree n-1.
int *P = NULL; // Interim products.
int *Poly = NULL; // Final.
int *PolyV = NULL; // Verification answer.
X = new int[n];
Y = new int[n];
P = new int[n*n];
Poly = new int[2*n-1];
PolyV = new int[2*n-1];
// Initialize values.
random_polynomial(X, n);
random_polynomial(Y, n);
for (int i = 0; i < n*n; i++)
{
P[i] = 0;
}
for (int i = 0; i < 2*n-1; i++)
{
Poly[i] = 0;
PolyV[i] = 0;
}
// Step 1: Calculating products.
int *Xd, *Yd, *Pd;
cudaMalloc((void **)&Xd, sizeof(int)*n);
cudaMalloc((void **)&Yd, sizeof(int)*n);
cudaMalloc((void **)&Pd, sizeof(int)*n*n);
cudaMemcpy(Xd, X, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(Yd, Y, sizeof(int)*n, cudaMemcpyHostToDevice);
cudaMemcpy(Pd, P, sizeof(int)*n*n, cudaMemcpyHostToDevice);
calculate_products<<<n, n>>>(Pd, Xd, Yd, n);
// Step 2: Reducing like terms.
int *Polyd;
cudaMalloc((void **)&Polyd, sizeof(int)*2*n-1);
cudaMemcpy(Polyd, Poly, sizeof(int)*2*n-1, cudaMemcpyHostToDevice);
reduce_polynomial<<<2*n-1, 1>>>(Pd, Polyd, n);
cudaMemcpy(Poly, Polyd, sizeof(int)*2*n-1, cudaMemcpyDeviceToHost);
// Print input, output.
printf("CUDA Program Output\n\n");
printf("First input polynomial:\n");
print_polynomial(X, n);
printf("Second input polynomial:\n");
print_polynomial(Y, n);
printf("Result:\n");
print_polynomial(Poly, 2*n-1);
// Step 3: Verify using serial C function.
printf("Verification with Serial C Output\n\n");
multiply_polynomials_serial(X, Y, n, PolyV);
printf("Result:\n");
print_polynomial(PolyV, 2*n-1);
// Free memory.
delete [] X;
delete [] Y;
delete [] P;
delete [] Poly;
delete [] PolyV;
cudaFree(Xd);
cudaFree(Yd);
cudaFree(Pd);
cudaFree(Polyd);
return 0;
} | // CS 4402 - Dana Zagar - 250790176
#include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
using namespace std;
// A small prime number to prevent overflow and make verification feasible.
const int MAX_COEFF = 103;
// Print polynomial output.
void print_polynomial(int* poly, int range)
{
for (int i = 0; i < range; i++)
{
printf("%2d ", poly[i]);
}
printf("\n\n");
}
// Generates a random polynomial of size n.
void random_polynomial(int* p, int n)
{
for (int i=0; i<n; i++) {
p[i] = rand() % MAX_COEFF;
}
}
// Serial C function to find reduced polynomial product.
// For verification purposes.
void multiply_polynomials_serial(int *x, int *y, int size, int *ans)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
ans[i+j] = (ans[i+j] + x[i] * y[j]) % MAX_COEFF;
}
}
}
// First CUDA kernel to calculate the product terms over two given polynomials
// of size n, given n thread-blocks and n threads per.
__global__ void calculate_products(int *prods, int *x, int *y, size_t n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
prods[index] = (x[blockIdx.x] * y[threadIdx.x]) % MAX_COEFF;
}
// Second CUDA kernel to reduce the products by combining like terms on each
// diagonal of the "2d" product matrix.
__global__ void reduce_polynomial(int *prods, int *ans, size_t n)
{
int i, j;
// Envision the product array as a 2d matrix tilted like a diamond.
// Each block represents a row of the diamond, i.e. a diagonal.
// If the block index is within the first half of the diamond, the
// block index dictates the row index.
if (blockIdx.x <= (2*n-2)/2)
{
i = blockIdx.x, j = 0;
}
// Otherwise, the block index dictates the column index.
else
{
i = n-1, j = (blockIdx.x % n) + 1;
}
// Sum over the diagonal given by the block index.
while (i >= 0 && j < n)
{
ans[blockIdx.x] = (ans[blockIdx.x] + prods[i*n + j]) % MAX_COEFF;
i--;
j++;
}
}
int main() {
srand(time(NULL));
int exponent;
// Input the number of terms.
printf("Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: ");
scanf("%d", &exponent);
if (exponent < 1 || exponent > 10)
{
printf("Invalid input. Program will terminate.\n\n");
return 0;
}
int n = 1 << exponent; // Number of terms is 2^exponent.
printf("%d terms; input polynomials are of degree %d.\n\n", n, n-1);
int *X = NULL; // First polynomial of degree n-1.
int *Y = NULL; // Second polynomial of degree n-1.
int *P = NULL; // Interim products.
int *Poly = NULL; // Final.
int *PolyV = NULL; // Verification answer.
X = new int[n];
Y = new int[n];
P = new int[n*n];
Poly = new int[2*n-1];
PolyV = new int[2*n-1];
// Initialize values.
random_polynomial(X, n);
random_polynomial(Y, n);
for (int i = 0; i < n*n; i++)
{
P[i] = 0;
}
for (int i = 0; i < 2*n-1; i++)
{
Poly[i] = 0;
PolyV[i] = 0;
}
// Step 1: Calculating products.
int *Xd, *Yd, *Pd;
hipMalloc((void **)&Xd, sizeof(int)*n);
hipMalloc((void **)&Yd, sizeof(int)*n);
hipMalloc((void **)&Pd, sizeof(int)*n*n);
hipMemcpy(Xd, X, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(Yd, Y, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(Pd, P, sizeof(int)*n*n, hipMemcpyHostToDevice);
calculate_products<<<n, n>>>(Pd, Xd, Yd, n);
// Step 2: Reducing like terms.
int *Polyd;
hipMalloc((void **)&Polyd, sizeof(int)*2*n-1);
hipMemcpy(Polyd, Poly, sizeof(int)*2*n-1, hipMemcpyHostToDevice);
reduce_polynomial<<<2*n-1, 1>>>(Pd, Polyd, n);
hipMemcpy(Poly, Polyd, sizeof(int)*2*n-1, hipMemcpyDeviceToHost);
// Print input, output.
printf("CUDA Program Output\n\n");
printf("First input polynomial:\n");
print_polynomial(X, n);
printf("Second input polynomial:\n");
print_polynomial(Y, n);
printf("Result:\n");
print_polynomial(Poly, 2*n-1);
// Step 3: Verify using serial C function.
printf("Verification with Serial C Output\n\n");
multiply_polynomials_serial(X, Y, n, PolyV);
printf("Result:\n");
print_polynomial(PolyV, 2*n-1);
// Free memory.
delete [] X;
delete [] Y;
delete [] P;
delete [] Poly;
delete [] PolyV;
hipFree(Xd);
hipFree(Yd);
hipFree(Pd);
hipFree(Polyd);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // CS 4402 - Dana Zagar - 250790176
#include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
using namespace std;
// A small prime number to prevent overflow and make verification feasible.
const int MAX_COEFF = 103;
// Print polynomial output.
void print_polynomial(int* poly, int range)
{
for (int i = 0; i < range; i++)
{
printf("%2d ", poly[i]);
}
printf("\n\n");
}
// Generates a random polynomial of size n.
void random_polynomial(int* p, int n)
{
for (int i=0; i<n; i++) {
p[i] = rand() % MAX_COEFF;
}
}
// Serial C function to find reduced polynomial product.
// For verification purposes.
void multiply_polynomials_serial(int *x, int *y, int size, int *ans)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
ans[i+j] = (ans[i+j] + x[i] * y[j]) % MAX_COEFF;
}
}
}
// First CUDA kernel to calculate the product terms over two given polynomials
// of size n, given n thread-blocks and n threads per.
__global__ void calculate_products(int *prods, int *x, int *y, size_t n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
prods[index] = (x[blockIdx.x] * y[threadIdx.x]) % MAX_COEFF;
}
// Second CUDA kernel to reduce the products by combining like terms on each
// diagonal of the "2d" product matrix.
__global__ void reduce_polynomial(int *prods, int *ans, size_t n)
{
int i, j;
// Envision the product array as a 2d matrix tilted like a diamond.
// Each block represents a row of the diamond, i.e. a diagonal.
// If the block index is within the first half of the diamond, the
// block index dictates the row index.
if (blockIdx.x <= (2*n-2)/2)
{
i = blockIdx.x, j = 0;
}
// Otherwise, the block index dictates the column index.
else
{
i = n-1, j = (blockIdx.x % n) + 1;
}
// Sum over the diagonal given by the block index.
while (i >= 0 && j < n)
{
ans[blockIdx.x] = (ans[blockIdx.x] + prods[i*n + j]) % MAX_COEFF;
i--;
j++;
}
}
int main() {
srand(time(NULL));
int exponent;
// Input the number of terms.
printf("Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: ");
scanf("%d", &exponent);
if (exponent < 1 || exponent > 10)
{
printf("Invalid input. Program will terminate.\n\n");
return 0;
}
int n = 1 << exponent; // Number of terms is 2^exponent.
printf("%d terms; input polynomials are of degree %d.\n\n", n, n-1);
int *X = NULL; // First polynomial of degree n-1.
int *Y = NULL; // Second polynomial of degree n-1.
int *P = NULL; // Interim products.
int *Poly = NULL; // Final.
int *PolyV = NULL; // Verification answer.
X = new int[n];
Y = new int[n];
P = new int[n*n];
Poly = new int[2*n-1];
PolyV = new int[2*n-1];
// Initialize values.
random_polynomial(X, n);
random_polynomial(Y, n);
for (int i = 0; i < n*n; i++)
{
P[i] = 0;
}
for (int i = 0; i < 2*n-1; i++)
{
Poly[i] = 0;
PolyV[i] = 0;
}
// Step 1: Calculating products.
int *Xd, *Yd, *Pd;
hipMalloc((void **)&Xd, sizeof(int)*n);
hipMalloc((void **)&Yd, sizeof(int)*n);
hipMalloc((void **)&Pd, sizeof(int)*n*n);
hipMemcpy(Xd, X, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(Yd, Y, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(Pd, P, sizeof(int)*n*n, hipMemcpyHostToDevice);
calculate_products<<<n, n>>>(Pd, Xd, Yd, n);
// Step 2: Reducing like terms.
int *Polyd;
hipMalloc((void **)&Polyd, sizeof(int)*2*n-1);
hipMemcpy(Polyd, Poly, sizeof(int)*2*n-1, hipMemcpyHostToDevice);
reduce_polynomial<<<2*n-1, 1>>>(Pd, Polyd, n);
hipMemcpy(Poly, Polyd, sizeof(int)*2*n-1, hipMemcpyDeviceToHost);
// Print input, output.
printf("CUDA Program Output\n\n");
printf("First input polynomial:\n");
print_polynomial(X, n);
printf("Second input polynomial:\n");
print_polynomial(Y, n);
printf("Result:\n");
print_polynomial(Poly, 2*n-1);
// Step 3: Verify using serial C function.
printf("Verification with Serial C Output\n\n");
multiply_polynomials_serial(X, Y, n, PolyV);
printf("Result:\n");
print_polynomial(PolyV, 2*n-1);
// Free memory.
delete [] X;
delete [] Y;
delete [] P;
delete [] Poly;
delete [] PolyV;
hipFree(Xd);
hipFree(Yd);
hipFree(Pd);
hipFree(Polyd);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18calculate_productsPiS_S_m
.globl _Z18calculate_productsPiS_S_m
.p2align 8
.type _Z18calculate_productsPiS_S_m,@function
_Z18calculate_productsPiS_S_m:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s4, s15
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 2
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s8, 0xffff
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_load_b32 s2, s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v3, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v1, v3, 0x13e22cbd
v_lshrrev_b32_e32 v4, 31, v1
v_ashrrev_i32_e32 v5, 3, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v5, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, 0x67
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18calculate_productsPiS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18calculate_productsPiS_S_m, .Lfunc_end0-_Z18calculate_productsPiS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17reduce_polynomialPiS_m
.globl _Z17reduce_polynomialPiS_m
.p2align 8
.type _Z17reduce_polynomialPiS_m,@function
_Z17reduce_polynomialPiS_m:
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s6, s15
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, -1
s_addc_u32 s5, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_bitset0_b32 s5, 31
v_cmp_ge_u64_e64 s4, s[4:5], s[6:7]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_3
v_cmp_lt_u64_e64 s4, s[6:7], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_4
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s5, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s4, v0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s6, s4
s_mul_i32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s4, s6, s4
s_sub_i32 s5, s4, s2
s_cmp_ge_u32 s4, s2
s_cselect_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s5, s4, s2
s_cmp_ge_u32 s4, s2
s_cselect_b32 s4, s5, s4
s_branch .LBB1_5
.LBB1_3:
s_mov_b64 s[4:5], 0
s_mov_b32 s8, s6
s_branch .LBB1_6
.LBB1_4:
s_mov_b64 s[4:5], s[6:7]
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, 1
s_add_i32 s8, s2, -1
s_ashr_i32 s5, s4, 31
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ge_u64_e64 s9, s[4:5], s[2:3]
s_cmp_lt_i32 s8, 0
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_9
s_load_b128 s[12:15], s[0:1], 0x0
s_lshl_b64 s[0:1], s[6:7], 2
s_mul_i32 s7, s3, s8
s_mul_hi_u32 s9, s2, s8
s_mul_i32 s10, s2, s8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s14, s0
s_addc_u32 s1, s15, s1
s_add_i32 s11, s9, s7
s_load_b32 s6, s[0:1], 0x0
s_lshl_b64 s[10:11], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s7, s12, s10
s_addc_u32 s9, s13, s11
s_lshl_b64 s[10:11], s[2:3], 2
s_sub_u32 s10, 0, s10
s_subb_u32 s11, 0, s11
.p2align 6
.LBB1_8:
s_lshl_b64 s[12:13], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s7, s12
s_addc_u32 s13, s9, s13
global_load_b32 v1, v0, s[12:13]
s_add_i32 s12, s8, -1
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_i32 s6, s5, 0x13e22cbd
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_lshr_b32 s13, s6, 31
s_ashr_i32 s6, s6, 3
s_add_i32 s6, s6, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mulk_i32 s6, 0x67
s_sub_i32 s6, s5, s6
s_cmp_gt_i32 s8, 0
v_mov_b32_e32 v1, s6
s_cselect_b32 s13, -1, 0
s_add_i32 s4, s4, 1
s_mov_b32 s8, s12
s_ashr_i32 s5, s4, 31
global_store_b32 v0, v1, s[0:1]
v_cmp_lt_u64_e64 s14, s[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s12, s13, s14
s_add_u32 s7, s7, s10
s_addc_u32 s9, s9, s11
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB1_8
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17reduce_polynomialPiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17reduce_polynomialPiS_m, .Lfunc_end1-_Z17reduce_polynomialPiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18calculate_productsPiS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18calculate_productsPiS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17reduce_polynomialPiS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17reduce_polynomialPiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // CS 4402 - Dana Zagar - 250790176
#include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
using namespace std;
// A small prime number to prevent overflow and make verification feasible.
const int MAX_COEFF = 103;
// Print polynomial output.
void print_polynomial(int* poly, int range)
{
for (int i = 0; i < range; i++)
{
printf("%2d ", poly[i]);
}
printf("\n\n");
}
// Generates a random polynomial of size n.
void random_polynomial(int* p, int n)
{
for (int i=0; i<n; i++) {
p[i] = rand() % MAX_COEFF;
}
}
// Serial C function to find reduced polynomial product.
// For verification purposes.
void multiply_polynomials_serial(int *x, int *y, int size, int *ans)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
{
ans[i+j] = (ans[i+j] + x[i] * y[j]) % MAX_COEFF;
}
}
}
// First CUDA kernel to calculate the product terms over two given polynomials
// of size n, given n thread-blocks and n threads per.
__global__ void calculate_products(int *prods, int *x, int *y, size_t n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
prods[index] = (x[blockIdx.x] * y[threadIdx.x]) % MAX_COEFF;
}
// Second CUDA kernel to reduce the products by combining like terms on each
// diagonal of the "2d" product matrix.
__global__ void reduce_polynomial(int *prods, int *ans, size_t n)
{
int i, j;
// Envision the product array as a 2d matrix tilted like a diamond.
// Each block represents a row of the diamond, i.e. a diagonal.
// If the block index is within the first half of the diamond, the
// block index dictates the row index.
if (blockIdx.x <= (2*n-2)/2)
{
i = blockIdx.x, j = 0;
}
// Otherwise, the block index dictates the column index.
else
{
i = n-1, j = (blockIdx.x % n) + 1;
}
// Sum over the diagonal given by the block index.
while (i >= 0 && j < n)
{
ans[blockIdx.x] = (ans[blockIdx.x] + prods[i*n + j]) % MAX_COEFF;
i--;
j++;
}
}
int main() {
srand(time(NULL));
int exponent;
// Input the number of terms.
printf("Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: ");
scanf("%d", &exponent);
if (exponent < 1 || exponent > 10)
{
printf("Invalid input. Program will terminate.\n\n");
return 0;
}
int n = 1 << exponent; // Number of terms is 2^exponent.
printf("%d terms; input polynomials are of degree %d.\n\n", n, n-1);
int *X = NULL; // First polynomial of degree n-1.
int *Y = NULL; // Second polynomial of degree n-1.
int *P = NULL; // Interim products.
int *Poly = NULL; // Final.
int *PolyV = NULL; // Verification answer.
X = new int[n];
Y = new int[n];
P = new int[n*n];
Poly = new int[2*n-1];
PolyV = new int[2*n-1];
// Initialize values.
random_polynomial(X, n);
random_polynomial(Y, n);
for (int i = 0; i < n*n; i++)
{
P[i] = 0;
}
for (int i = 0; i < 2*n-1; i++)
{
Poly[i] = 0;
PolyV[i] = 0;
}
// Step 1: Calculating products.
int *Xd, *Yd, *Pd;
hipMalloc((void **)&Xd, sizeof(int)*n);
hipMalloc((void **)&Yd, sizeof(int)*n);
hipMalloc((void **)&Pd, sizeof(int)*n*n);
hipMemcpy(Xd, X, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(Yd, Y, sizeof(int)*n, hipMemcpyHostToDevice);
hipMemcpy(Pd, P, sizeof(int)*n*n, hipMemcpyHostToDevice);
calculate_products<<<n, n>>>(Pd, Xd, Yd, n);
// Step 2: Reducing like terms.
int *Polyd;
hipMalloc((void **)&Polyd, sizeof(int)*2*n-1);
hipMemcpy(Polyd, Poly, sizeof(int)*2*n-1, hipMemcpyHostToDevice);
reduce_polynomial<<<2*n-1, 1>>>(Pd, Polyd, n);
hipMemcpy(Poly, Polyd, sizeof(int)*2*n-1, hipMemcpyDeviceToHost);
// Print input, output.
printf("CUDA Program Output\n\n");
printf("First input polynomial:\n");
print_polynomial(X, n);
printf("Second input polynomial:\n");
print_polynomial(Y, n);
printf("Result:\n");
print_polynomial(Poly, 2*n-1);
// Step 3: Verify using serial C function.
printf("Verification with Serial C Output\n\n");
multiply_polynomials_serial(X, Y, n, PolyV);
printf("Result:\n");
print_polynomial(PolyV, 2*n-1);
// Free memory.
delete [] X;
delete [] Y;
delete [] P;
delete [] Poly;
delete [] PolyV;
hipFree(Xd);
hipFree(Yd);
hipFree(Pd);
hipFree(Polyd);
return 0;
} | .text
.file "dzagar_CS4402_a2q1.hip"
.globl _Z16print_polynomialPii # -- Begin function _Z16print_polynomialPii
.p2align 4, 0x90
.type _Z16print_polynomialPii,@function
_Z16print_polynomialPii: # @_Z16print_polynomialPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z16print_polynomialPii, .Lfunc_end0-_Z16print_polynomialPii
.cfi_endproc
# -- End function
.globl _Z17random_polynomialPii # -- Begin function _Z17random_polynomialPii
.p2align 4, 0x90
.type _Z17random_polynomialPii,@function
_Z17random_polynomialPii: # @_Z17random_polynomialPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $333589693, %rax, %rcx # imm = 0x13E22CBD
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
imull $103, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17random_polynomialPii, .Lfunc_end1-_Z17random_polynomialPii
.cfi_endproc
# -- End function
.globl _Z27multiply_polynomials_serialPiS_iS_ # -- Begin function _Z27multiply_polynomials_serialPiS_iS_
.p2align 4, 0x90
.type _Z27multiply_polynomials_serialPiS_iS_,@function
_Z27multiply_polynomials_serialPiS_iS_: # @_Z27multiply_polynomials_serialPiS_iS_
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r8,4), %r9d
imull (%rdi,%rdx,4), %r9d
addl (%rcx,%r8,4), %r9d
movslq %r9d, %r9
imulq $333589693, %r9, %r10 # imm = 0x13E22CBD
movq %r10, %r11
shrq $63, %r11
sarq $35, %r10
addl %r11d, %r10d
imull $103, %r10d, %r10d
subl %r10d, %r9d
movl %r9d, (%rcx,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addq $4, %rcx
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge19
retq
.Lfunc_end2:
.size _Z27multiply_polynomials_serialPiS_iS_, .Lfunc_end2-_Z27multiply_polynomials_serialPiS_iS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__calculate_productsPiS_S_m # -- Begin function _Z33__device_stub__calculate_productsPiS_S_m
.p2align 4, 0x90
.type _Z33__device_stub__calculate_productsPiS_S_m,@function
_Z33__device_stub__calculate_productsPiS_S_m: # @_Z33__device_stub__calculate_productsPiS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18calculate_productsPiS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z33__device_stub__calculate_productsPiS_S_m, .Lfunc_end3-_Z33__device_stub__calculate_productsPiS_S_m
.cfi_endproc
# -- End function
.globl _Z32__device_stub__reduce_polynomialPiS_m # -- Begin function _Z32__device_stub__reduce_polynomialPiS_m
.p2align 4, 0x90
.type _Z32__device_stub__reduce_polynomialPiS_m,@function
_Z32__device_stub__reduce_polynomialPiS_m: # @_Z32__device_stub__reduce_polynomialPiS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17reduce_polynomialPiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z32__device_stub__reduce_polynomialPiS_m, .Lfunc_end4-_Z32__device_stub__reduce_polynomialPiS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 140(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 140(%rsp), %ebp
leal -11(%rbp), %eax
cmpl $-11, %eax
ja .LBB5_2
# %bb.1:
movl $.Lstr.7, %edi
callq puts@PLT
jmp .LBB5_23
.LBB5_2:
movl $1, %r15d
movl %ebp, %ecx
shlq %cl, %r15
leal -1(%r15), %edx
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq (,%r15,4), %r14
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
movq %r14, 184(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movl %r15d, %eax
movl %ebp, %ecx
shll %cl, %eax
movq %rax, 176(%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
callq _Znam
movl $2, %r13d
movq %rbp, 192(%rsp) # 8-byte Spill
movl %ebp, %ecx
shll %cl, %r13d
movq %rax, 40(%rsp) # 8-byte Spill
decl %r13d
leaq (,%r13,4), %rbp
movq %rbp, %rdi
callq _Znam
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq _Znam
movq %rax, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $333589693, %rax, %rcx # imm = 0x13E22CBD
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
imull $103, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB5_3
# %bb.4: # %.lr.ph.i81.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i81
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $333589693, %rax, %rcx # imm = 0x13E22CBD
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
imull $103, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB5_5
# %bb.6: # %_Z17random_polynomialPii.exit85.preheader
movq 176(%rsp), %rdx # 8-byte Reload
cmpl $1, %edx
adcl $0, %edx
shlq $2, %rdx
movq 40(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
cmpl $2, %r13d
movl $1, %r12d
cmovgel %r13d, %r12d
shlq $2, %r12
movq 16(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq 32(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
leaq 56(%rsp), %rdi
movq 184(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 192(%rsp), %rcx # 8-byte Reload
addb $2, %cl
movq %r15, %r12
# kill: def $cl killed $cl killed $rcx
shlq %cl, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movabsq $4294967296, %rbp # imm = 0x100000000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
orq %rbp, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq 24(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %r15, 72(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18calculate_productsPiS_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
leaq -1(,%r15,8), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
orq %rbp, %rdi
incq %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_10
# %bb.9:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %r15, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z17reduce_polynomialPiS_m, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_10:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB5_11
# %bb.12: # %_Z16print_polynomialPii.exit
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_13: # %.lr.ph.i99
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB5_13
# %bb.14: # %_Z16print_polynomialPii.exit103
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r12d, %r12d
movq 16(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB5_15: # %.lr.ph.i106
# =>This Inner Loop Header: Depth=1
movl (%rbp,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB5_15
# %bb.16: # %_Z16print_polynomialPii.exit110
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
xorl %eax, %eax
movq 32(%rsp), %rcx # 8-byte Reload
movq %rbp, %r12
.p2align 4, 0x90
.LBB5_17: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_18 Depth 2
movl (%rbx,%rax,4), %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_18: # Parent Loop BB5_17 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rsi,4), %edi
imull %edx, %edi
addl (%rcx,%rsi,4), %edi
movslq %edi, %rdi
imulq $333589693, %rdi, %r8 # imm = 0x13E22CBD
movq %r8, %r9
shrq $63, %r9
sarq $35, %r8
addl %r9d, %r8d
imull $103, %r8d, %r8d
subl %r8d, %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq %rsi, %r15
jne .LBB5_18
# %bb.19: # %._crit_edge.i
# in Loop: Header=BB5_17 Depth=1
incq %rax
addq $4, %rcx
cmpq %r15, %rax
jne .LBB5_17
# %bb.20: # %_Z27multiply_polynomials_serialPiS_iS_.exit
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r15d, %r15d
movq 32(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB5_21: # %.lr.ph.i119
# =>This Inner Loop Header: Depth=1
movl (%rbp,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r13
jne .LBB5_21
# %bb.22: # %_Z16print_polynomialPii.exit123
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq 40(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
movq %rbp, %rdi
callq _ZdaPv
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
.LBB5_23:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calculate_productsPiS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17reduce_polynomialPiS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type _Z18calculate_productsPiS_S_m,@object # @_Z18calculate_productsPiS_S_m
.section .rodata,"a",@progbits
.globl _Z18calculate_productsPiS_S_m
.p2align 3, 0x0
_Z18calculate_productsPiS_S_m:
.quad _Z33__device_stub__calculate_productsPiS_S_m
.size _Z18calculate_productsPiS_S_m, 8
.type _Z17reduce_polynomialPiS_m,@object # @_Z17reduce_polynomialPiS_m
.globl _Z17reduce_polynomialPiS_m
.p2align 3, 0x0
_Z17reduce_polynomialPiS_m:
.quad _Z32__device_stub__reduce_polynomialPiS_m
.size _Z17reduce_polynomialPiS_m, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: "
.size .L.str.2, 121
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d terms
.size .L.str.5, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18calculate_productsPiS_S_m"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17reduce_polynomialPiS_m"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CUDA Program Output\n"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "First input polynomial:"
.size .Lstr.2, 24
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Second input polynomial:"
.size .Lstr.3, 25
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Verification with Serial C Output\n"
.size .Lstr.5, 35
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Result:"
.size .Lstr.6, 8
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Invalid input. Program will terminate.\n"
.size .Lstr.7, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__calculate_productsPiS_S_m
.addrsig_sym _Z32__device_stub__reduce_polynomialPiS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18calculate_productsPiS_S_m
.addrsig_sym _Z17reduce_polynomialPiS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17reduce_polynomialPiS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0040*/ ULEA UR4, UP0, UR6, 0xfffffffe, 0x1 ; /* 0xfffffffe06047891 */
/* 0x000fc8000f80083f */
/*0050*/ ULEA.HI.X UR5, UR6, 0xffffffff, UR7, 0x1, UP0 ; /* 0xffffffff06057891 */
/* 0x000fc800080f0c07 */
/*0060*/ USHF.R.U64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001205 */
/*0070*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fcc0008011605 */
/*0080*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fe2000f8e00ff */
/*0090*/ ISETP.LE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf03070 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0000 */
/*00b0*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*00c0*/ @P0 BRA 0x260 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f05070 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R2, 0x110 ; /* 0x0000011000027802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x470 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BRA 0x230 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000209000 */
/*0130*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f25070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0190*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R8, R3, c[0x0][0x170], R0 ; /* 0x00005c0003087a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R8, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008080a10 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fda0003f06070 */
/*0210*/ @P0 IADD3 R8, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008080a10 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P1 LOP3.LUT R8, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff089a12 */
/* 0x000fc600078e33ff */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0250*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0270*/ SHF.R.S32.HI R4, RZ, 0x1f, R8 ; /* 0x0000001fff047819 */
/* 0x000fc80000011408 */
/*0280*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x174], PT, P0 ; /* 0x00005d0004007a0c */
/* 0x000fc80003f06100 */
/*0290*/ ISETP.LT.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000701670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe200078010ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02d0*/ LEA.HI.X R3, R0, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f14ff */
/*02e0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0004 */
/*0300*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe20000011409 */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0008 */
/*0320*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe400078e02ff */
/*0330*/ IMAD.WIDE.U32 R4, R9, c[0x0][0x170], R4 ; /* 0x00005c0009047a25 */
/* 0x000fc800078e0004 */
/*0340*/ IMAD R7, R9, c[0x0][0x174], R0 ; /* 0x00005d0009077a24 */
/* 0x000fe200078e0200 */
/*0350*/ LEA R6, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004067a11 */
/* 0x000fc600078010ff */
/*0360*/ IMAD.IADD R5, R5, 0x1, R7 ; /* 0x0000000105057824 */
/* 0x000fca00078e0207 */
/*0370*/ LEA.HI.X R7, R4, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590004077a11 */
/* 0x000fca00000f1405 */
/*0380*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GT.AND P1, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f24270 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*03c0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3 R11, R6, R11, RZ ; /* 0x0000000b060b7210 */
/* 0x026fca0007ffe0ff */
/*03e0*/ IMAD.HI R0, R11, 0x13e22cbd, RZ ; /* 0x13e22cbd0b007827 */
/* 0x000fca00078e02ff */
/*03f0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*0400*/ LEA.HI.SX32 R0, R0, R5, 0x1d ; /* 0x0000000500007211 */
/* 0x000fe400078feaff */
/*0410*/ SHF.R.S32.HI R5, RZ, 0x1f, R8 ; /* 0x0000001fff057819 */
/* 0x000fc60000011408 */
/*0420*/ IMAD R11, R0, -0x67, R11 ; /* 0xffffff99000b7824 */
/* 0x000fe200078e020b */
/*0430*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fc80003f06100 */
/*0440*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003f2000c101904 */
/*0450*/ @!P0 BRA P1, 0x300 ; /* 0xfffffea000008947 */
/* 0x000fea000083ffff */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ I2F.U64.RP R3, c[0x0][0x170] ; /* 0x00005c0000037b12 */
/* 0x000e300000309000 */
/*0480*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0490*/ IADD3 R4, R3, 0x1ffffffe, RZ ; /* 0x1ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*04a0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*04b0*/ IMAD.WIDE.U32 R6, R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a25 */
/* 0x001fc800078e00ff */
/*04c0*/ IMAD R7, R4, c[0x0][0x174], R7 ; /* 0x00005d0004077a24 */
/* 0x000fe200078e0207 */
/*04d0*/ IADD3 R9, P0, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fc60007f1e0ff */
/*04e0*/ IMAD R7, R5, c[0x0][0x170], R7 ; /* 0x00005c0005077a24 */
/* 0x000fe400078e0207 */
/*04f0*/ IMAD.HI.U32 R6, R4, R9, RZ ; /* 0x0000000904067227 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.X R11, RZ, RZ, ~R7, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e07 */
/*0510*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0520*/ IMAD R13, R5, R11.reuse, RZ ; /* 0x0000000b050d7224 */
/* 0x080fe400078e02ff */
/*0530*/ IMAD.WIDE.U32 R6, P0, R4, R11, R6 ; /* 0x0000000b04067225 */
/* 0x000fc80007800006 */
/*0540*/ IMAD.HI.U32 R3, R5, R11, RZ ; /* 0x0000000b05037227 */
/* 0x000fc800078e00ff */
/*0550*/ IMAD.HI.U32 R6, P1, R5, R9, R6 ; /* 0x0000000905067227 */
/* 0x000fc80007820006 */
/*0560*/ IMAD.X R3, R3, 0x1, R5, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0605 */
/*0570*/ IADD3 R7, P2, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x000fc80007f5e0ff */
/*0580*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fe200017e2403 */
/*0590*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x170], RZ ; /* 0x00005c0007047a25 */
/* 0x000fc800078e00ff */
/*05a0*/ IMAD R6, R7, c[0x0][0x174], R5 ; /* 0x00005d0007067a24 */
/* 0x000fe200078e0205 */
/*05b0*/ IADD3 R5, P0, RZ, -R4, RZ ; /* 0x80000004ff057210 */
/* 0x000fc60007f1e0ff */
/*05c0*/ IMAD R4, R3, c[0x0][0x170], R6 ; /* 0x00005c0003047a24 */
/* 0x000fe400078e0206 */
/*05d0*/ IMAD.HI.U32 R6, R7, R5, RZ ; /* 0x0000000507067227 */
/* 0x000fc800078e00ff */
/*05e0*/ IMAD.X R4, RZ, RZ, ~R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fc800000e0e04 */
/*05f0*/ IMAD.WIDE.U32 R6, P0, R7, R4, R6 ; /* 0x0000000407067225 */
/* 0x000fc80007800006 */
/*0600*/ IMAD R8, R3.reuse, R4, RZ ; /* 0x0000000403087224 */
/* 0x040fe400078e02ff */
/*0610*/ IMAD.HI.U32 R7, P1, R3, R5, R6 ; /* 0x0000000503077227 */
/* 0x000fe20007820006 */
/*0620*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fc600000001ff */
/*0630*/ IMAD.HI.U32 R6, R3, R4, RZ ; /* 0x0000000403067227 */
/* 0x000fe200078e00ff */
/*0640*/ IADD3 R7, P2, R8, R7, RZ ; /* 0x0000000708077210 */
/* 0x000fc60007f5e0ff */
/*0650*/ IMAD.X R3, R6, 0x1, R3, P0 ; /* 0x0000000106037824 */
/* 0x000fe400000e0603 */
/*0660*/ IMAD.HI.U32 R4, R7, R0, RZ ; /* 0x0000000007047227 */
/* 0x000fc600078e00ff */
/*0670*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fc600017e2403 */
/*0680*/ IMAD.WIDE.U32 R4, RZ, R7, R4 ; /* 0x00000007ff047225 */
/* 0x000fcc00078e0004 */
/*0690*/ IMAD.HI.U32 R3, P0, R3, R0, R4 ; /* 0x0000000003037227 */
/* 0x000fca0007800004 */
/*06a0*/ IADD3 R7, P1, RZ, R3, RZ ; /* 0x00000003ff077210 */
/* 0x000fe20007f3e0ff */
/*06b0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fc800000e06ff */
/*06c0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x170], RZ ; /* 0x00005c0007047a25 */
/* 0x000fc800078e00ff */
/*06d0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*06e0*/ IADD3 R8, P1, -R4, R0, RZ ; /* 0x0000000004087210 */
/* 0x000fe20007f3e1ff */
/*06f0*/ IMAD R6, R7, c[0x0][0x174], R5 ; /* 0x00005d0007067a24 */
/* 0x000fc600078e0205 */
/*0700*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe20003f06070 */
/*0710*/ IMAD R3, R3, c[0x0][0x170], R6 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0206 */
/*0720*/ IMAD.X R5, RZ, RZ, ~R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0e03 */
/*0730*/ IADD3 R3, P1, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008037a10 */
/* 0x000fc80007f3e0ff */
/*0740*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x040fe40003f06100 */
/*0750*/ IADD3.X R4, R5, ~c[0x0][0x174], RZ, P1, !PT ; /* 0x80005d0005047a10 */
/* 0x000fe40000ffe4ff */
/*0760*/ SEL R3, R3, R8, P0 ; /* 0x0000000803037207 */
/* 0x000fe40000000000 */
/*0770*/ SEL R4, R4, R5, P0 ; /* 0x0000000504047207 */
/* 0x000fe40000000000 */
/*0780*/ ISETP.GE.U32.AND P0, PT, R3.reuse, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x040fe40003f06070 */
/*0790*/ IADD3 R8, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003087a10 */
/* 0x000fc40007ffe0ff */
/*07a0*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x174], PT, P0 ; /* 0x00005d0004007a0c */
/* 0x000fe40003f06100 */
/*07b0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25070 */
/*07c0*/ SEL R8, R8, R3, P0 ; /* 0x0000000308087207 */
/* 0x000fe20000000000 */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*07e0*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x174], PT, P1 ; /* 0x00005d00ff007a0c */
/* 0x000fc80003f25310 */
/*07f0*/ SEL R8, R8, 0xffffffff, P1 ; /* 0xffffffff08087807 */
/* 0x000fe20000800000 */
/*0800*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7f002007950 */
/* 0x000ff00003c3ffff */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18calculate_productsPiS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e6e0000002100 */
/*0050*/ IMAD.WIDE.U32 R2, R6, R11, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e000b */
/*0060*/ IMAD.WIDE.U32 R4, R9, R11, c[0x0][0x170] ; /* 0x00005c0009047625 */
/* 0x002fe400078e000b */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD R6, R6, c[0x0][0x0], R9 ; /* 0x0000000006067a24 */
/* 0x000fe400078e0209 */
/*00a0*/ IMAD R0, R2, R5, RZ ; /* 0x0000000502007224 */
/* 0x004fc800078e02ff */
/*00b0*/ IMAD.HI R7, R0, 0x13e22cbd, RZ ; /* 0x13e22cbd00077827 */
/* 0x000fca00078e02ff */
/*00c0*/ SHF.R.U32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011607 */
/*00d0*/ LEA.HI.SX32 R9, R7, R8, 0x1d ; /* 0x0000000807097211 */
/* 0x000fe200078feaff */
/*00e0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*00f0*/ IMAD R9, R9, -0x67, R0 ; /* 0xffffff9909097824 */
/* 0x000fca00078e0200 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18calculate_productsPiS_S_m
.globl _Z18calculate_productsPiS_S_m
.p2align 8
.type _Z18calculate_productsPiS_S_m,@function
_Z18calculate_productsPiS_S_m:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s4, s15
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 2
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s8, 0xffff
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_load_b32 s2, s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v3, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v1, v3, 0x13e22cbd
v_lshrrev_b32_e32 v4, 31, v1
v_ashrrev_i32_e32 v5, 3, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v5, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, 0x67
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18calculate_productsPiS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18calculate_productsPiS_S_m, .Lfunc_end0-_Z18calculate_productsPiS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17reduce_polynomialPiS_m
.globl _Z17reduce_polynomialPiS_m
.p2align 8
.type _Z17reduce_polynomialPiS_m,@function
_Z17reduce_polynomialPiS_m:
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s6, s15
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, -1
s_addc_u32 s5, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_bitset0_b32 s5, 31
v_cmp_ge_u64_e64 s4, s[4:5], s[6:7]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_3
v_cmp_lt_u64_e64 s4, s[6:7], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_4
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s5, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s4, v0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s6, s4
s_mul_i32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s4, s6, s4
s_sub_i32 s5, s4, s2
s_cmp_ge_u32 s4, s2
s_cselect_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s5, s4, s2
s_cmp_ge_u32 s4, s2
s_cselect_b32 s4, s5, s4
s_branch .LBB1_5
.LBB1_3:
s_mov_b64 s[4:5], 0
s_mov_b32 s8, s6
s_branch .LBB1_6
.LBB1_4:
s_mov_b64 s[4:5], s[6:7]
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, 1
s_add_i32 s8, s2, -1
s_ashr_i32 s5, s4, 31
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ge_u64_e64 s9, s[4:5], s[2:3]
s_cmp_lt_i32 s8, 0
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_9
s_load_b128 s[12:15], s[0:1], 0x0
s_lshl_b64 s[0:1], s[6:7], 2
s_mul_i32 s7, s3, s8
s_mul_hi_u32 s9, s2, s8
s_mul_i32 s10, s2, s8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s14, s0
s_addc_u32 s1, s15, s1
s_add_i32 s11, s9, s7
s_load_b32 s6, s[0:1], 0x0
s_lshl_b64 s[10:11], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s7, s12, s10
s_addc_u32 s9, s13, s11
s_lshl_b64 s[10:11], s[2:3], 2
s_sub_u32 s10, 0, s10
s_subb_u32 s11, 0, s11
.p2align 6
.LBB1_8:
s_lshl_b64 s[12:13], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s7, s12
s_addc_u32 s13, s9, s13
global_load_b32 v1, v0, s[12:13]
s_add_i32 s12, s8, -1
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_i32 s6, s5, 0x13e22cbd
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_lshr_b32 s13, s6, 31
s_ashr_i32 s6, s6, 3
s_add_i32 s6, s6, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mulk_i32 s6, 0x67
s_sub_i32 s6, s5, s6
s_cmp_gt_i32 s8, 0
v_mov_b32_e32 v1, s6
s_cselect_b32 s13, -1, 0
s_add_i32 s4, s4, 1
s_mov_b32 s8, s12
s_ashr_i32 s5, s4, 31
global_store_b32 v0, v1, s[0:1]
v_cmp_lt_u64_e64 s14, s[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s12, s13, s14
s_add_u32 s7, s7, s10
s_addc_u32 s9, s9, s11
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB1_8
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17reduce_polynomialPiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17reduce_polynomialPiS_m, .Lfunc_end1-_Z17reduce_polynomialPiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18calculate_productsPiS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18calculate_productsPiS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17reduce_polynomialPiS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17reduce_polynomialPiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000488ec_00000000-6_dzagar_CS4402_a2q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n\n"
.text
.globl _Z16print_polynomialPii
.type _Z16print_polynomialPii, @function
_Z16print_polynomialPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z16print_polynomialPii, .-_Z16print_polynomialPii
.globl _Z17random_polynomialPii
.type _Z17random_polynomialPii, @function
_Z17random_polynomialPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L13
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L10:
call rand@PLT
movslq %eax, %rdx
imulq $333589693, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $103, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z17random_polynomialPii, .-_Z17random_polynomialPii
.globl _Z27multiply_polynomials_serialPiS_iS_
.type _Z27multiply_polynomials_serialPiS_iS_, @function
_Z27multiply_polynomials_serialPiS_iS_:
.LFB2059:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L22
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r10
movl %edx, %r11d
movq %rcx, %r9
movslq %edx, %rax
leaq (%rsi,%rax,4), %r8
movl $0, %ebx
.L18:
movq %r10, %rsi
movq %r9, %rcx
.L19:
movl (%rdi), %eax
imull (%rsi), %eax
addl (%rcx), %eax
movslq %eax, %rdx
imulq $333589693, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ebp
sarl $31, %ebp
subl %ebp, %edx
imull $103, %edx, %edx
subl %edx, %eax
movl %eax, (%rcx)
addq $4, %rcx
addq $4, %rsi
cmpq %r8, %rsi
jne .L19
addl $1, %ebx
addq $4, %r9
addq $4, %rdi
cmpl %ebx, %r11d
jne .L18
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z27multiply_polynomials_serialPiS_iS_, .-_Z27multiply_polynomials_serialPiS_iS_
.globl _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
.type _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m, @function
_Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18calculate_productsPiS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m, .-_Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
.globl _Z18calculate_productsPiS_S_m
.type _Z18calculate_productsPiS_S_m, @function
_Z18calculate_productsPiS_S_m:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18calculate_productsPiS_S_m, .-_Z18calculate_productsPiS_S_m
.globl _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
.type _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m, @function
_Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17reduce_polynomialPiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m, .-_Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
.globl _Z17reduce_polynomialPiS_m
.type _Z17reduce_polynomialPiS_m, @function
_Z17reduce_polynomialPiS_m:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z17reduce_polynomialPiS_m, .-_Z17reduce_polynomialPiS_m
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: "
.section .rodata.str1.1
.LC3:
.string "%d"
.section .rodata.str1.8
.align 8
.LC4:
.string "Invalid input. Program will terminate.\n\n"
.align 8
.LC5:
.string "%d terms; input polynomials are of degree %d.\n\n"
.section .rodata.str1.1
.LC6:
.string "CUDA Program Output\n\n"
.LC7:
.string "First input polynomial:\n"
.LC8:
.string "Second input polynomial:\n"
.LC9:
.string "Result:\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Verification with Serial C Output\n\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 60(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 60(%rsp), %ebx
leal -1(%rbx), %eax
cmpl $9, %eax
ja .L52
movl $1, %r12d
movl %ebx, %ecx
sall %cl, %r12d
leal -1(%r12), %ecx
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %r14
leaq 0(,%r14,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movl %r12d, %edx
movl %ebx, %ecx
sall %cl, %edx
movl %edx, %eax
cltq
leaq 0(,%rax,4), %rdx
movq %rdx, 32(%rsp)
movq %rdx, %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $2, %eax
movl %eax, %edx
movl %ebx, %ecx
sall %cl, %edx
movl %edx, 44(%rsp)
leal -1(%rdx), %r15d
movslq %r15d, %rax
leaq 0(,%rax,4), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbp
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z17random_polynomialPii
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z17random_polynomialPii
movq 24(%rsp), %rcx
movq %rcx, %rax
movq 32(%rsp), %rdx
addq %rcx, %rdx
.L44:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L44
movl 44(%rsp), %eax
leal -1(%rax), %edx
movl $0, %eax
.L45:
movl $0, (%rbx,%rax,4)
movl $0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %rdx
jne .L45
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movq %r14, %rax
imulq %r14, %rax
salq $2, %rax
leaq 80(%rsp), %rdi
movq %rax, 32(%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r12d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L46:
leaq -1(,%r14,8), %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r15d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L47:
movl $2, %ecx
movq %r13, %rdx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movq 16(%rsp), %r14
movq %r14, %rdi
call _Z16print_polynomialPii
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z16print_polynomialPii
leaq .LC9(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %esi
movq %rbx, %rdi
call _Z16print_polynomialPii
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rcx
movl %r12d, %edx
movq 8(%rsp), %r12
movq %r12, %rsi
movq %r14, %rdi
call _Z27multiply_polynomials_serialPiS_iS_
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %esi
movq %rbp, %rdi
call _Z16print_polynomialPii
movq %r14, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
.L43:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L43
.L53:
movq %r14, %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z43__device_stub__Z18calculate_productsPiS_S_mPiS_S_m
jmp .L46
.L54:
movq %r14, %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z40__device_stub__Z17reduce_polynomialPiS_mPiS_m
jmp .L47
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z17reduce_polynomialPiS_m"
.LC12:
.string "_Z18calculate_productsPiS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z17reduce_polynomialPiS_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calculate_productsPiS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dzagar_CS4402_a2q1.hip"
.globl _Z16print_polynomialPii # -- Begin function _Z16print_polynomialPii
.p2align 4, 0x90
.type _Z16print_polynomialPii,@function
_Z16print_polynomialPii: # @_Z16print_polynomialPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z16print_polynomialPii, .Lfunc_end0-_Z16print_polynomialPii
.cfi_endproc
# -- End function
.globl _Z17random_polynomialPii # -- Begin function _Z17random_polynomialPii
.p2align 4, 0x90
.type _Z17random_polynomialPii,@function
_Z17random_polynomialPii: # @_Z17random_polynomialPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $333589693, %rax, %rcx # imm = 0x13E22CBD
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
imull $103, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17random_polynomialPii, .Lfunc_end1-_Z17random_polynomialPii
.cfi_endproc
# -- End function
.globl _Z27multiply_polynomials_serialPiS_iS_ # -- Begin function _Z27multiply_polynomials_serialPiS_iS_
.p2align 4, 0x90
.type _Z27multiply_polynomials_serialPiS_iS_,@function
_Z27multiply_polynomials_serialPiS_iS_: # @_Z27multiply_polynomials_serialPiS_iS_
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r8,4), %r9d
imull (%rdi,%rdx,4), %r9d
addl (%rcx,%r8,4), %r9d
movslq %r9d, %r9
imulq $333589693, %r9, %r10 # imm = 0x13E22CBD
movq %r10, %r11
shrq $63, %r11
sarq $35, %r10
addl %r11d, %r10d
imull $103, %r10d, %r10d
subl %r10d, %r9d
movl %r9d, (%rcx,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addq $4, %rcx
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge19
retq
.Lfunc_end2:
.size _Z27multiply_polynomials_serialPiS_iS_, .Lfunc_end2-_Z27multiply_polynomials_serialPiS_iS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__calculate_productsPiS_S_m # -- Begin function _Z33__device_stub__calculate_productsPiS_S_m
.p2align 4, 0x90
.type _Z33__device_stub__calculate_productsPiS_S_m,@function
_Z33__device_stub__calculate_productsPiS_S_m: # @_Z33__device_stub__calculate_productsPiS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18calculate_productsPiS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z33__device_stub__calculate_productsPiS_S_m, .Lfunc_end3-_Z33__device_stub__calculate_productsPiS_S_m
.cfi_endproc
# -- End function
.globl _Z32__device_stub__reduce_polynomialPiS_m # -- Begin function _Z32__device_stub__reduce_polynomialPiS_m
.p2align 4, 0x90
.type _Z32__device_stub__reduce_polynomialPiS_m,@function
_Z32__device_stub__reduce_polynomialPiS_m: # @_Z32__device_stub__reduce_polynomialPiS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17reduce_polynomialPiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z32__device_stub__reduce_polynomialPiS_m, .Lfunc_end4-_Z32__device_stub__reduce_polynomialPiS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 140(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 140(%rsp), %ebp
leal -11(%rbp), %eax
cmpl $-11, %eax
ja .LBB5_2
# %bb.1:
movl $.Lstr.7, %edi
callq puts@PLT
jmp .LBB5_23
.LBB5_2:
movl $1, %r15d
movl %ebp, %ecx
shlq %cl, %r15
leal -1(%r15), %edx
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq (,%r15,4), %r14
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
movq %r14, 184(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movl %r15d, %eax
movl %ebp, %ecx
shll %cl, %eax
movq %rax, 176(%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
callq _Znam
movl $2, %r13d
movq %rbp, 192(%rsp) # 8-byte Spill
movl %ebp, %ecx
shll %cl, %r13d
movq %rax, 40(%rsp) # 8-byte Spill
decl %r13d
leaq (,%r13,4), %rbp
movq %rbp, %rdi
callq _Znam
movq %rax, 16(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq _Znam
movq %rax, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $333589693, %rax, %rcx # imm = 0x13E22CBD
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
imull $103, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB5_3
# %bb.4: # %.lr.ph.i81.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i81
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $333589693, %rax, %rcx # imm = 0x13E22CBD
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
imull $103, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB5_5
# %bb.6: # %_Z17random_polynomialPii.exit85.preheader
movq 176(%rsp), %rdx # 8-byte Reload
cmpl $1, %edx
adcl $0, %edx
shlq $2, %rdx
movq 40(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
cmpl $2, %r13d
movl $1, %r12d
cmovgel %r13d, %r12d
shlq $2, %r12
movq 16(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq 32(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
leaq 56(%rsp), %rdi
movq 184(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 192(%rsp), %rcx # 8-byte Reload
addb $2, %cl
movq %r15, %r12
# kill: def $cl killed $cl killed $rcx
shlq %cl, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movabsq $4294967296, %rbp # imm = 0x100000000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
orq %rbp, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq 24(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %r15, 72(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18calculate_productsPiS_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
leaq -1(,%r15,8), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
orq %rbp, %rdi
incq %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_10
# %bb.9:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %r15, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z17reduce_polynomialPiS_m, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_10:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB5_11
# %bb.12: # %_Z16print_polynomialPii.exit
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_13: # %.lr.ph.i99
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB5_13
# %bb.14: # %_Z16print_polynomialPii.exit103
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r12d, %r12d
movq 16(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB5_15: # %.lr.ph.i106
# =>This Inner Loop Header: Depth=1
movl (%rbp,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB5_15
# %bb.16: # %_Z16print_polynomialPii.exit110
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
xorl %eax, %eax
movq 32(%rsp), %rcx # 8-byte Reload
movq %rbp, %r12
.p2align 4, 0x90
.LBB5_17: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_18 Depth 2
movl (%rbx,%rax,4), %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_18: # Parent Loop BB5_17 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rsi,4), %edi
imull %edx, %edi
addl (%rcx,%rsi,4), %edi
movslq %edi, %rdi
imulq $333589693, %rdi, %r8 # imm = 0x13E22CBD
movq %r8, %r9
shrq $63, %r9
sarq $35, %r8
addl %r9d, %r8d
imull $103, %r8d, %r8d
subl %r8d, %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq %rsi, %r15
jne .LBB5_18
# %bb.19: # %._crit_edge.i
# in Loop: Header=BB5_17 Depth=1
incq %rax
addq $4, %rcx
cmpq %r15, %rax
jne .LBB5_17
# %bb.20: # %_Z27multiply_polynomials_serialPiS_iS_.exit
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r15d, %r15d
movq 32(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB5_21: # %.lr.ph.i119
# =>This Inner Loop Header: Depth=1
movl (%rbp,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r13
jne .LBB5_21
# %bb.22: # %_Z16print_polynomialPii.exit123
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq 40(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
movq %rbp, %rdi
callq _ZdaPv
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
.LBB5_23:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calculate_productsPiS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17reduce_polynomialPiS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type _Z18calculate_productsPiS_S_m,@object # @_Z18calculate_productsPiS_S_m
.section .rodata,"a",@progbits
.globl _Z18calculate_productsPiS_S_m
.p2align 3, 0x0
_Z18calculate_productsPiS_S_m:
.quad _Z33__device_stub__calculate_productsPiS_S_m
.size _Z18calculate_productsPiS_S_m, 8
.type _Z17reduce_polynomialPiS_m,@object # @_Z17reduce_polynomialPiS_m
.globl _Z17reduce_polynomialPiS_m
.p2align 3, 0x0
_Z17reduce_polynomialPiS_m:
.quad _Z32__device_stub__reduce_polynomialPiS_m
.size _Z17reduce_polynomialPiS_m, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Input the desired number of terms in the polynomials. Enter an exponent on 2 [valid from 1-10] to define 2^input terms: "
.size .L.str.2, 121
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d terms
.size .L.str.5, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18calculate_productsPiS_S_m"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17reduce_polynomialPiS_m"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CUDA Program Output\n"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "First input polynomial:"
.size .Lstr.2, 24
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Second input polynomial:"
.size .Lstr.3, 25
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Verification with Serial C Output\n"
.size .Lstr.5, 35
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Result:"
.size .Lstr.6, 8
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Invalid input. Program will terminate.\n"
.size .Lstr.7, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__calculate_productsPiS_S_m
.addrsig_sym _Z32__device_stub__reduce_polynomialPiS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18calculate_productsPiS_S_m
.addrsig_sym _Z17reduce_polynomialPiS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define BLOCK1 1024
#define BLOCK2 32
int size;
float *matrixA, *vectorB, *vectorX;
__global__
void cudaPivot(float *A_d, int *max_pivot, int pivot, int size)
{
float max = fabsf(A_d[pivot * size + pivot]);
int maxi = pivot;
for (int i = pivot + 1; i < size; i++)
{
float abs = fabsf(A_d[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
*max_pivot = maxi;
return;
}
__global__
void cudaSwap(float *A_d, float *B_d, int *max_pivot, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot <= i) && (i < size))
{
float temp = A_d[pivot * size + i];
A_d[pivot * size + i] = A_d[*max_pivot * size + i];
A_d[*max_pivot * size + i] = temp;
}
else if (i == size)
{
float temp = B_d[pivot];
B_d[pivot] = B_d[*max_pivot];
B_d[*max_pivot] = temp;
}
return;
}
__global__
void cudaCalcM(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot < i) && (i < size))
{
M_d[i] = A_d[i * size + pivot] / A_d[pivot * size + pivot];
}
}
__global__
void cudaGauss(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if ((pivot < i) && (i < size) && (pivot <= j) && (j <= size))
{
if (j == size)
{
B_d[i] -= M_d[i] * B_d[pivot];
}
else
{
A_d[i * size + j] -= M_d[i] * A_d[pivot * size + j];
}
}
}
__global__
void cudaBackSub(float *A_d, float *B_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < pivot)
{
float m = B_d[pivot] / A_d[pivot * size + pivot];
B_d[i] -= m * A_d[i * size + pivot];
}
}
__global__
void cudaCoeff(float *A_d, float *B_d, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
B_d[i] = B_d[i] / A_d[i * size + i];
}
float *make_vector(int size)
{
float *vector = (float *) malloc(sizeof(float) * size);
if (vector == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return vector;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_vector(float *vector, int size)
{
for (int i = 0; i < size; i++)
vector[i] = (float) drand48();
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_vector(float *vector, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
printf(" %f", vector[i]);
printf(";");
}
printf(" ]\n");
}
void print_matrix(float *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_gaussian(float *A, float *B, float *X, int size)
{
int mat_size = sizeof(float) * size * size;
int vec_size = sizeof(float) * size;
int grid1 = ((size + 1) / BLOCK1) + (((size + 1) % BLOCK1 == 0) ? 0 : 1);
int grid2 = ((size + 1) / BLOCK2) + (((size + 1) % BLOCK2 == 0) ? 0 : 1);
int *max_pivot;
float *A_d, *B_d, *M_d;
dim3 dimBlock(BLOCK2, BLOCK2);
dim3 dimGrid(grid2, grid2);
cudaMalloc((void **) &A_d, mat_size);
cudaMemcpy(A_d, A, mat_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &B_d, vec_size);
cudaMemcpy(B_d, B, vec_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &M_d, vec_size);
cudaMalloc((void **) &max_pivot, sizeof(int));
for (int pivot = 0; pivot < size; pivot++)
{
cudaPivot<<<1, 1>>>(A_d, max_pivot, pivot, size);
cudaSwap<<<grid1, BLOCK1>>>(A_d, B_d, max_pivot, pivot, size);
cudaCalcM<<<grid1, BLOCK1>>>(A_d, B_d, M_d, pivot, size);
cudaGauss<<<dimGrid, dimBlock>>>(A_d, B_d, M_d, pivot, size);
}
for (int pivot = size - 1; pivot >= 0; pivot--)
{
cudaBackSub<<<grid1, BLOCK1>>>(A_d, B_d, pivot, size);
}
cudaCoeff<<<grid1, BLOCK1>>>(A_d, B_d, size);
cudaMemcpy(X, B_d, vec_size, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(M_d);
cudaFree(max_pivot);
}
int pivot_routine(float *matrix, int start, int end, int pivot)
{
float t_max = 0.0, max = 0.0;
int t_maxi = pivot, maxi = pivot;
{
for (int i = start; i < end; i++)
{
float abs = fabsf(matrix[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
if (max > t_max)
{
t_max = max;
t_maxi = maxi;
}
}
return t_maxi;
}
void gauss_routine(float *matrix, float *vector, int start, int end, int pivot)
{
for (int i = start; i < end; i++)
{
float m = matrix[i * size + pivot] / matrix[pivot * size + pivot];
for (int j = pivot; j < size; j++)
matrix[i * size + j] -= m * matrix[pivot * size + j];
vector[i] -= m * vector[pivot];
}
}
void back_routine(float *matrix, float *vector, int start, int end, int pivot)
{
float m = vector[pivot] / matrix[pivot * size + pivot];
for (int i = start; i < end; i++)
vector[i] -= m * matrix[i * size + pivot];
}
void single_gaussian(void)
{
int maxi;
float swap;
for (int i = 0; i < size; i++)
{
maxi = pivot_routine(matrixA, i, size, i);
for (int j = 0; j < size; j++)
{
swap = matrixA[i * size + j];
matrixA[i * size + j] = matrixA[maxi * size + j];
matrixA[maxi * size + j] = swap;
}
swap = vectorB[i];
vectorB[i] = vectorB[maxi];
vectorB[maxi] = swap;
gauss_routine(matrixA, vectorB, i + 1, size, i);
}
for (int i = size - 1; i >= 0; i--)
{
back_routine(matrixA, vectorB, 0, i, i);
vectorB[i] /= matrixA[i * size + i];
}
return;
}
float L2_norm(float *matrixA, float *vectorX, float *vectorB, int size)
{
float norm = 0.0, sum;
for (int i = 0; i < size; i++)
{
sum = 0.0;
for (int j = 0; j < size; j++)
sum += matrixA[i * size + j] * vectorX[j];
sum -= vectorB[i];
norm += sum * sum;
}
return sqrt(norm);
}
int main(int argc, char **argv, char **envp)
{
int opt, t_sec = time(NULL);
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
vectorB = make_vector(size);
vectorX = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_gaussian(matrixA, vectorB, vectorX, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
single_gaussian();
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
free(vectorX);
vectorX = vectorB;
free(matrixA);
free(vectorB);
matrixA = make_matrix(size);
vectorB = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
return 0;
} | .file "tmpxft_000a9921_00000000-6_prob2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "malloc"
.text
.globl _Z11make_vectori
.type _Z11make_vectori, @function
_Z11make_vectori:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
testq %rax, %rax
je .L7
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
testq %rax, %rax
je .L8
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L8:
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z11make_vectori, .-_Z11make_vectori
.globl _Z11make_matrixi
.type _Z11make_matrixi, @function
_Z11make_matrixi:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
testq %rax, %rax
je .L13
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
testq %rax, %rax
je .L14
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq .LC0(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z11make_matrixi, .-_Z11make_matrixi
.globl _Z10set_vectorPfi
.type _Z10set_vectorPfi, @function
_Z10set_vectorPfi:
.LFB2072:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L20
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L17:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2072:
.size _Z10set_vectorPfi, .-_Z10set_vectorPfi
.globl _Z10set_matrixPfi
.type _Z10set_matrixPfi, @function
_Z10set_matrixPfi:
.LFB2073:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L29
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L25:
leaq 0(%rbp,%r13), %rbx
.L26:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L25
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2073:
.size _Z10set_matrixPfi, .-_Z10set_matrixPfi
.section .rodata.str1.1
.LC1:
.string "["
.LC2:
.string " %f"
.LC3:
.string ";"
.LC4:
.string " ]\n"
.text
.globl _Z12print_vectorPfi
.type _Z12print_vectorPfi, @function
_Z12print_vectorPfi:
.LFB2074:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L33
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r13
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
.L34:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L34
.L33:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z12print_vectorPfi, .-_Z12print_vectorPfi
.globl _Z12print_matrixPfi
.type _Z12print_matrixPfi, @function
_Z12print_matrixPfi:
.LFB2075:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movl %esi, 12(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L38
movslq %ebx, %r14
leaq 0(,%r14,4), %r15
addq %r15, %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L39:
leaq 0(%rbp,%r14), %rbx
.L40:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L40
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L39
.L38:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z12print_matrixPfi, .-_Z12print_matrixPfi
.globl _Z13pivot_routinePfiii
.type _Z13pivot_routinePfiii, @function
_Z13pivot_routinePfiii:
.LFB2077:
.cfi_startproc
endbr64
movq %rdi, %r9
movl %esi, %eax
movl %edx, %edi
cmpl %edx, %esi
jge .L47
movl size(%rip), %edx
movslq %edx, %r8
salq $2, %r8
imull %esi, %edx
movslq %edx, %rdx
movslq %ecx, %rsi
addq %rsi, %rdx
leaq (%r9,%rdx,4), %rdx
movl %ecx, %esi
pxor %xmm1, %xmm1
movss .LC6(%rip), %xmm2
.L46:
movss (%rdx), %xmm0
andps %xmm2, %xmm0
comiss %xmm1, %xmm0
cmova %eax, %esi
maxss %xmm1, %xmm0
movaps %xmm0, %xmm1
addl $1, %eax
addq %r8, %rdx
cmpl %eax, %edi
jne .L46
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
cmovbe %ecx, %esi
.L43:
movl %esi, %eax
ret
.L47:
movl %ecx, %esi
jmp .L43
.cfi_endproc
.LFE2077:
.size _Z13pivot_routinePfiii, .-_Z13pivot_routinePfiii
.globl _Z13gauss_routinePfS_iii
.type _Z13gauss_routinePfS_iii, @function
_Z13gauss_routinePfS_iii:
.LFB2078:
.cfi_startproc
endbr64
cmpl %ecx, %edx
jge .L58
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %r9
movl %ecx, %r11d
movslq %r8d, %rax
leaq (%rsi,%rax,4), %rbx
movslq %edx, %r10
.L54:
movl %r10d, %esi
movl size(%rip), %eax
movl %eax, %ecx
imull %r10d, %ecx
addl %r8d, %ecx
movslq %ecx, %rcx
movl %eax, %edx
imull %r8d, %edx
addl %r8d, %edx
movslq %edx, %rdx
movss (%rdi,%rcx,4), %xmm2
divss (%rdi,%rdx,4), %xmm2
cmpl %r8d, %eax
jle .L52
movl %r8d, %ecx
.L53:
movl %eax, %edx
imull %esi, %edx
addl %ecx, %edx
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %rdx
imull %r8d, %eax
addl %ecx, %eax
cltq
movaps %xmm2, %xmm1
mulss (%rdi,%rax,4), %xmm1
movss (%rdx), %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%rdx)
addl $1, %ecx
movl size(%rip), %eax
cmpl %ecx, %eax
jg .L53
.L52:
mulss (%rbx), %xmm2
movss (%r9,%r10,4), %xmm0
subss %xmm2, %xmm0
movss %xmm0, (%r9,%r10,4)
addq $1, %r10
cmpl %r10d, %r11d
jg .L54
popq %rbx
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore 3
ret
.cfi_endproc
.LFE2078:
.size _Z13gauss_routinePfS_iii, .-_Z13gauss_routinePfS_iii
.globl _Z12back_routinePfS_iii
.type _Z12back_routinePfS_iii, @function
_Z12back_routinePfS_iii:
.LFB2079:
.cfi_startproc
endbr64
movslq %r8d, %r9
movl %r8d, %eax
imull size(%rip), %eax
addl %r8d, %eax
cltq
movss (%rsi,%r9,4), %xmm2
divss (%rdi,%rax,4), %xmm2
cmpl %ecx, %edx
jge .L61
movslq %edx, %rdx
.L63:
movl %edx, %eax
imull size(%rip), %eax
addl %r8d, %eax
cltq
movaps %xmm2, %xmm1
mulss (%rdi,%rax,4), %xmm1
movss (%rsi,%rdx,4), %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%rsi,%rdx,4)
addq $1, %rdx
cmpl %edx, %ecx
jg .L63
.L61:
ret
.cfi_endproc
.LFE2079:
.size _Z12back_routinePfS_iii, .-_Z12back_routinePfS_iii
.globl _Z15single_gaussianv
.type _Z15single_gaussianv, @function
_Z15single_gaussianv:
.LFB2080:
.cfi_startproc
endbr64
movl size(%rip), %edx
testl %edx, %edx
jle .L75
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $0, %ebp
.L69:
movl %ebp, %r12d
movl %ebp, %ebx
movl %ebp, %ecx
movl %ebp, %esi
movq matrixA(%rip), %rdi
call _Z13pivot_routinePfiii
movl %eax, %esi
movl size(%rip), %eax
testl %eax, %eax
jle .L67
movl $0, %edx
.L68:
movq matrixA(%rip), %rdi
movl %eax, %ecx
imull %ebx, %ecx
addl %edx, %ecx
movslq %ecx, %rcx
leaq (%rdi,%rcx,4), %rcx
movss (%rcx), %xmm0
imull %esi, %eax
addl %edx, %eax
cltq
movss (%rdi,%rax,4), %xmm1
movss %xmm1, (%rcx)
movl %esi, %eax
imull size(%rip), %eax
addl %edx, %eax
cltq
movq matrixA(%rip), %rcx
movss %xmm0, (%rcx,%rax,4)
addl $1, %edx
movl size(%rip), %eax
cmpl %edx, %eax
jg .L68
.L67:
movq vectorB(%rip), %rdx
leaq (%rdx,%rbp,4), %rax
movss (%rax), %xmm0
movslq %esi, %rsi
movss (%rdx,%rsi,4), %xmm1
movss %xmm1, (%rax)
movq vectorB(%rip), %rax
movss %xmm0, (%rax,%rsi,4)
leal 1(%r12), %edx
movl %ebx, %r8d
movl size(%rip), %ecx
movq vectorB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z13gauss_routinePfS_iii
movl size(%rip), %edx
addq $1, %rbp
cmpl %ebp, %edx
jg .L69
movl %edx, %ebx
subl $1, %ebx
js .L65
movslq %ebx, %rbp
salq $2, %rbp
.L70:
movl %ebx, %r8d
movl %ebx, %ecx
movl $0, %edx
movq vectorB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z12back_routinePfS_iii
movq %rbp, %rdx
addq vectorB(%rip), %rdx
movl %ebx, %eax
imull size(%rip), %eax
addl %ebx, %eax
cltq
movss (%rdx), %xmm0
movq matrixA(%rip), %rcx
divss (%rcx,%rax,4), %xmm0
movss %xmm0, (%rdx)
subl $1, %ebx
subq $4, %rbp
cmpl $-1, %ebx
jne .L70
.L65:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2080:
.size _Z15single_gaussianv, .-_Z15single_gaussianv
.globl _Z7L2_normPfS_S_i
.type _Z7L2_normPfS_S_i, @function
_Z7L2_normPfS_S_i:
.LFB2081:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L86
movq %rdx, %r8
movslq %ecx, %rcx
salq $2, %rcx
addq %rcx, %rdx
pxor %xmm0, %xmm0
.L80:
movl $0, %eax
pxor %xmm2, %xmm2
.L81:
movss (%rdi,%rax), %xmm1
mulss (%rsi,%rax), %xmm1
addss %xmm1, %xmm2
addq $4, %rax
cmpq %rcx, %rax
jne .L81
subss (%r8), %xmm2
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
addq $4, %r8
addq %rcx, %rdi
cmpq %rdx, %r8
jne .L80
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L93
.L79:
sqrtss %xmm0, %xmm0
ret
.L86:
pxor %xmm0, %xmm0
jmp .L79
.L93:
subq $8, %rsp
.cfi_def_cfa_offset 16
call sqrtf@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _Z7L2_normPfS_S_i, .-_Z7L2_normPfS_S_i
.globl _Z32__device_stub__Z9cudaPivotPfPiiiPfPiii
.type _Z32__device_stub__Z9cudaPivotPfPiiiPfPiii, @function
_Z32__device_stub__Z9cudaPivotPfPiiiPfPiii:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L98
.L94:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L99
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cudaPivotPfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L94
.L99:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z32__device_stub__Z9cudaPivotPfPiiiPfPiii, .-_Z32__device_stub__Z9cudaPivotPfPiiiPfPiii
.globl _Z9cudaPivotPfPiii
.type _Z9cudaPivotPfPiii, @function
_Z9cudaPivotPfPiii:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9cudaPivotPfPiiiPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _Z9cudaPivotPfPiii, .-_Z9cudaPivotPfPiii
.globl _Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii
.type _Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii, @function
_Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii:
.LFB2109:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L106
.L102:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L107
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cudaSwapPfS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L102
.L107:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2109:
.size _Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii, .-_Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii
.globl _Z8cudaSwapPfS_Piii
.type _Z8cudaSwapPfS_Piii, @function
_Z8cudaSwapPfS_Piii:
.LFB2110:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _Z8cudaSwapPfS_Piii, .-_Z8cudaSwapPfS_Piii
.globl _Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii
.type _Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii:
.LFB2111:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L114
.L110:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L115
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L114:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cudaCalcMPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L110
.L115:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2111:
.size _Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii
.globl _Z9cudaCalcMPfS_S_ii
.type _Z9cudaCalcMPfS_S_ii, @function
_Z9cudaCalcMPfS_S_ii:
.LFB2112:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2112:
.size _Z9cudaCalcMPfS_S_ii, .-_Z9cudaCalcMPfS_S_ii
.globl _Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii
.type _Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii:
.LFB2113:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L122
.L118:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L123
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L122:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cudaGaussPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L118
.L123:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2113:
.size _Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii
.globl _Z9cudaGaussPfS_S_ii
.type _Z9cudaGaussPfS_S_ii, @function
_Z9cudaGaussPfS_S_ii:
.LFB2114:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2114:
.size _Z9cudaGaussPfS_S_ii, .-_Z9cudaGaussPfS_S_ii
.globl _Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii
.type _Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii, @function
_Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii:
.LFB2115:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L130
.L126:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L131
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L130:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11cudaBackSubPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L126
.L131:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2115:
.size _Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii, .-_Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii
.globl _Z11cudaBackSubPfS_ii
.type _Z11cudaBackSubPfS_ii, @function
_Z11cudaBackSubPfS_ii:
.LFB2116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2116:
.size _Z11cudaBackSubPfS_ii, .-_Z11cudaBackSubPfS_ii
.globl _Z31__device_stub__Z9cudaCoeffPfS_iPfS_i
.type _Z31__device_stub__Z9cudaCoeffPfS_iPfS_i, @function
_Z31__device_stub__Z9cudaCoeffPfS_iPfS_i:
.LFB2117:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L138
.L134:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L139
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L138:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cudaCoeffPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L134
.L139:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2117:
.size _Z31__device_stub__Z9cudaCoeffPfS_iPfS_i, .-_Z31__device_stub__Z9cudaCoeffPfS_iPfS_i
.globl _Z9cudaCoeffPfS_i
.type _Z9cudaCoeffPfS_i, @function
_Z9cudaCoeffPfS_i:
.LFB2118:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9cudaCoeffPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2118:
.size _Z9cudaCoeffPfS_i, .-_Z9cudaCoeffPfS_i
.globl _Z13cuda_gaussianPfS_S_i
.type _Z13cuda_gaussianPfS_S_i, @function
_Z13cuda_gaussianPfS_S_i:
.LFB2076:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r15
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leal 1(%rcx), %eax
testl $1023, %eax
setne %r12b
movzbl %r12b, %r12d
leal 1024(%rcx), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $10, %edx
addl %edx, %r12d
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $1, 48(%rsp)
testb $31, %al
setne %cl
movzbl %cl, %ecx
leal 32(%rbp), %edx
testl %eax, %eax
cmovs %edx, %eax
sarl $5, %eax
addl %ecx, %eax
movl %eax, 52(%rsp)
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl %ebp, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leal 0(,%rbp,4), %r14d
movslq %r14d, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %ebp, %ebp
jle .L143
movl $0, %ebx
jmp .L148
.L156:
movl %ebp, %ecx
movl %ebx, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9cudaPivotPfPiiiPfPiii
jmp .L144
.L157:
movl %ebp, %r8d
movl %ebx, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z8cudaSwapPfS_PiiiPfS_Piii
jmp .L145
.L158:
movl %ebp, %r8d
movl %ebx, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z9cudaCalcMPfS_S_iiPfS_S_ii
jmp .L146
.L147:
leal 1(%rbx), %r13d
cmpl %r13d, %ebp
je .L150
movl %r13d, %ebx
.L148:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L156
.L144:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L157
.L145:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L158
.L146:
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L147
movl %ebp, %r8d
movl %ebx, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z9cudaGaussPfS_S_iiPfS_S_ii
jmp .L147
.L149:
subl $1, %ebx
cmpl $-1, %ebx
je .L143
.L150:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L149
movl %r13d, %ecx
movl %ebx, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11cudaBackSubPfS_iiPfS_ii
jmp .L149
.L143:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L159
.L151:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L160
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L159:
.cfi_restore_state
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9cudaCoeffPfS_iPfS_i
jmp .L151
.L160:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z13cuda_gaussianPfS_S_i, .-_Z13cuda_gaussianPfS_S_i
.section .rodata.str1.1
.LC7:
.string "Usage: %s -n N\n"
.LC8:
.string "n:p:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Multi Thread Computation Start\n"
.section .rodata.str1.1
.LC10:
.string "clock_gettime"
.section .rodata.str1.8
.align 8
.LC12:
.string "Multi Thread Computation End: %.3f us.\n"
.section .rodata.str1.1
.LC13:
.string "L2-norm : %g\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Single Thread Computation Start\n"
.align 8
.LC15:
.string "Single Thread Computation End: %.3f us.\n"
.text
.globl main
.type main, @function
main:
.LFB2082:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movq %rax, %r13
leaq .LC8(%rip), %r12
.L164:
movq %r12, %rdx
movq %rbx, %rsi
movl %ebp, %edi
call getopt@PLT
cmpl $-1, %eax
je .L174
cmpl $63, %eax
je .L163
cmpl $110, %eax
jne .L164
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, size(%rip)
jmp .L164
.L163:
movq (%rbx), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L174:
movl size(%rip), %edi
testl %edi, %edi
jle .L175
call _Z11make_matrixi
movq %rax, matrixA(%rip)
movl size(%rip), %edi
call _Z11make_vectori
movq %rax, vectorB(%rip)
movl size(%rip), %edi
call _Z11make_vectori
movq %rax, vectorX(%rip)
movslq %r13d, %r13
movq %r13, %rdi
call srand48@PLT
movl size(%rip), %esi
movq matrixA(%rip), %rdi
call _Z10set_matrixPfi
movl size(%rip), %esi
movq vectorB(%rip), %rdi
call _Z10set_vectorPfi
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L176
movl size(%rip), %ecx
movq vectorX(%rip), %rdx
movq vectorB(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z13cuda_gaussianPfS_S_i
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L177
imulq $1000000000, 16(%rsp), %rax
addq 24(%rsp), %rax
imulq $1000000000, (%rsp), %rdx
addq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC11(%rip), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl size(%rip), %ecx
movq vectorB(%rip), %rdx
movq vectorX(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z7L2_normPfS_S_i
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L178
call _Z15single_gaussianv
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
je .L179
imulq $1000000000, 16(%rsp), %rax
addq 24(%rsp), %rax
imulq $1000000000, (%rsp), %rdx
addq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC11(%rip), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq vectorX(%rip), %rdi
call free@PLT
movq vectorB(%rip), %rax
movq %rax, vectorX(%rip)
movq matrixA(%rip), %rdi
call free@PLT
movq vectorB(%rip), %rdi
call free@PLT
movl size(%rip), %edi
call _Z11make_matrixi
movq %rax, matrixA(%rip)
movl size(%rip), %edi
call _Z11make_vectori
movq %rax, vectorB(%rip)
movq %r13, %rdi
call srand48@PLT
movl size(%rip), %esi
movq matrixA(%rip), %rdi
call _Z10set_matrixPfi
movl size(%rip), %esi
movq vectorB(%rip), %rdi
call _Z10set_vectorPfi
movl size(%rip), %ecx
movq vectorB(%rip), %rdx
movq vectorX(%rip), %rsi
movq matrixA(%rip), %rdi
call _Z7L2_normPfS_S_i
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L180
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L175:
.cfi_restore_state
movq (%rbx), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L176:
leaq .LC10(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L177:
leaq .LC10(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L178:
leaq .LC10(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L179:
leaq .LC10(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L180:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z9cudaCoeffPfS_i"
.LC17:
.string "_Z11cudaBackSubPfS_ii"
.LC18:
.string "_Z9cudaGaussPfS_S_ii"
.LC19:
.string "_Z9cudaCalcMPfS_S_ii"
.LC20:
.string "_Z8cudaSwapPfS_Piii"
.LC21:
.string "_Z9cudaPivotPfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2120:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaCoeffPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cudaBackSubPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaGaussPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaCalcMPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cudaSwapPfS_Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaPivotPfPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2120:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl vectorX
.bss
.align 8
.type vectorX, @object
.size vectorX, 8
vectorX:
.zero 8
.globl vectorB
.align 8
.type vectorB, @object
.size vectorB, 8
vectorB:
.zero 8
.globl matrixA
.align 8
.type matrixA, @object
.size matrixA, 8
matrixA:
.zero 8
.globl size
.align 4
.type size, @object
.size size, 4
size:
.zero 4
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define BLOCK1 1024
#define BLOCK2 32
int size;
float *matrixA, *vectorB, *vectorX;
__global__
void cudaPivot(float *A_d, int *max_pivot, int pivot, int size)
{
float max = fabsf(A_d[pivot * size + pivot]);
int maxi = pivot;
for (int i = pivot + 1; i < size; i++)
{
float abs = fabsf(A_d[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
*max_pivot = maxi;
return;
}
__global__
void cudaSwap(float *A_d, float *B_d, int *max_pivot, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot <= i) && (i < size))
{
float temp = A_d[pivot * size + i];
A_d[pivot * size + i] = A_d[*max_pivot * size + i];
A_d[*max_pivot * size + i] = temp;
}
else if (i == size)
{
float temp = B_d[pivot];
B_d[pivot] = B_d[*max_pivot];
B_d[*max_pivot] = temp;
}
return;
}
__global__
void cudaCalcM(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot < i) && (i < size))
{
M_d[i] = A_d[i * size + pivot] / A_d[pivot * size + pivot];
}
}
__global__
void cudaGauss(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if ((pivot < i) && (i < size) && (pivot <= j) && (j <= size))
{
if (j == size)
{
B_d[i] -= M_d[i] * B_d[pivot];
}
else
{
A_d[i * size + j] -= M_d[i] * A_d[pivot * size + j];
}
}
}
__global__
void cudaBackSub(float *A_d, float *B_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < pivot)
{
float m = B_d[pivot] / A_d[pivot * size + pivot];
B_d[i] -= m * A_d[i * size + pivot];
}
}
__global__
void cudaCoeff(float *A_d, float *B_d, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
B_d[i] = B_d[i] / A_d[i * size + i];
}
float *make_vector(int size)
{
float *vector = (float *) malloc(sizeof(float) * size);
if (vector == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return vector;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_vector(float *vector, int size)
{
for (int i = 0; i < size; i++)
vector[i] = (float) drand48();
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_vector(float *vector, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
printf(" %f", vector[i]);
printf(";");
}
printf(" ]\n");
}
void print_matrix(float *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_gaussian(float *A, float *B, float *X, int size)
{
int mat_size = sizeof(float) * size * size;
int vec_size = sizeof(float) * size;
int grid1 = ((size + 1) / BLOCK1) + (((size + 1) % BLOCK1 == 0) ? 0 : 1);
int grid2 = ((size + 1) / BLOCK2) + (((size + 1) % BLOCK2 == 0) ? 0 : 1);
int *max_pivot;
float *A_d, *B_d, *M_d;
dim3 dimBlock(BLOCK2, BLOCK2);
dim3 dimGrid(grid2, grid2);
cudaMalloc((void **) &A_d, mat_size);
cudaMemcpy(A_d, A, mat_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &B_d, vec_size);
cudaMemcpy(B_d, B, vec_size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &M_d, vec_size);
cudaMalloc((void **) &max_pivot, sizeof(int));
for (int pivot = 0; pivot < size; pivot++)
{
cudaPivot<<<1, 1>>>(A_d, max_pivot, pivot, size);
cudaSwap<<<grid1, BLOCK1>>>(A_d, B_d, max_pivot, pivot, size);
cudaCalcM<<<grid1, BLOCK1>>>(A_d, B_d, M_d, pivot, size);
cudaGauss<<<dimGrid, dimBlock>>>(A_d, B_d, M_d, pivot, size);
}
for (int pivot = size - 1; pivot >= 0; pivot--)
{
cudaBackSub<<<grid1, BLOCK1>>>(A_d, B_d, pivot, size);
}
cudaCoeff<<<grid1, BLOCK1>>>(A_d, B_d, size);
cudaMemcpy(X, B_d, vec_size, cudaMemcpyDeviceToHost);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(M_d);
cudaFree(max_pivot);
}
int pivot_routine(float *matrix, int start, int end, int pivot)
{
float t_max = 0.0, max = 0.0;
int t_maxi = pivot, maxi = pivot;
{
for (int i = start; i < end; i++)
{
float abs = fabsf(matrix[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
if (max > t_max)
{
t_max = max;
t_maxi = maxi;
}
}
return t_maxi;
}
void gauss_routine(float *matrix, float *vector, int start, int end, int pivot)
{
for (int i = start; i < end; i++)
{
float m = matrix[i * size + pivot] / matrix[pivot * size + pivot];
for (int j = pivot; j < size; j++)
matrix[i * size + j] -= m * matrix[pivot * size + j];
vector[i] -= m * vector[pivot];
}
}
void back_routine(float *matrix, float *vector, int start, int end, int pivot)
{
float m = vector[pivot] / matrix[pivot * size + pivot];
for (int i = start; i < end; i++)
vector[i] -= m * matrix[i * size + pivot];
}
void single_gaussian(void)
{
int maxi;
float swap;
for (int i = 0; i < size; i++)
{
maxi = pivot_routine(matrixA, i, size, i);
for (int j = 0; j < size; j++)
{
swap = matrixA[i * size + j];
matrixA[i * size + j] = matrixA[maxi * size + j];
matrixA[maxi * size + j] = swap;
}
swap = vectorB[i];
vectorB[i] = vectorB[maxi];
vectorB[maxi] = swap;
gauss_routine(matrixA, vectorB, i + 1, size, i);
}
for (int i = size - 1; i >= 0; i--)
{
back_routine(matrixA, vectorB, 0, i, i);
vectorB[i] /= matrixA[i * size + i];
}
return;
}
float L2_norm(float *matrixA, float *vectorX, float *vectorB, int size)
{
float norm = 0.0, sum;
for (int i = 0; i < size; i++)
{
sum = 0.0;
for (int j = 0; j < size; j++)
sum += matrixA[i * size + j] * vectorX[j];
sum -= vectorB[i];
norm += sum * sum;
}
return sqrt(norm);
}
int main(int argc, char **argv, char **envp)
{
int opt, t_sec = time(NULL);
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
vectorB = make_vector(size);
vectorX = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_gaussian(matrixA, vectorB, vectorX, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
single_gaussian();
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
free(vectorX);
vectorX = vectorB;
free(matrixA);
free(vectorB);
matrixA = make_matrix(size);
vectorB = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
return 0;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define BLOCK1 1024
#define BLOCK2 32
int size;
float *matrixA, *vectorB, *vectorX;
__global__
void cudaPivot(float *A_d, int *max_pivot, int pivot, int size)
{
float max = fabsf(A_d[pivot * size + pivot]);
int maxi = pivot;
for (int i = pivot + 1; i < size; i++)
{
float abs = fabsf(A_d[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
*max_pivot = maxi;
return;
}
__global__
void cudaSwap(float *A_d, float *B_d, int *max_pivot, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot <= i) && (i < size))
{
float temp = A_d[pivot * size + i];
A_d[pivot * size + i] = A_d[*max_pivot * size + i];
A_d[*max_pivot * size + i] = temp;
}
else if (i == size)
{
float temp = B_d[pivot];
B_d[pivot] = B_d[*max_pivot];
B_d[*max_pivot] = temp;
}
return;
}
__global__
void cudaCalcM(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot < i) && (i < size))
{
M_d[i] = A_d[i * size + pivot] / A_d[pivot * size + pivot];
}
}
__global__
void cudaGauss(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if ((pivot < i) && (i < size) && (pivot <= j) && (j <= size))
{
if (j == size)
{
B_d[i] -= M_d[i] * B_d[pivot];
}
else
{
A_d[i * size + j] -= M_d[i] * A_d[pivot * size + j];
}
}
}
__global__
void cudaBackSub(float *A_d, float *B_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < pivot)
{
float m = B_d[pivot] / A_d[pivot * size + pivot];
B_d[i] -= m * A_d[i * size + pivot];
}
}
__global__
void cudaCoeff(float *A_d, float *B_d, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
B_d[i] = B_d[i] / A_d[i * size + i];
}
float *make_vector(int size)
{
float *vector = (float *) malloc(sizeof(float) * size);
if (vector == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return vector;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_vector(float *vector, int size)
{
for (int i = 0; i < size; i++)
vector[i] = (float) drand48();
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_vector(float *vector, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
printf(" %f", vector[i]);
printf(";");
}
printf(" ]\n");
}
void print_matrix(float *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_gaussian(float *A, float *B, float *X, int size)
{
int mat_size = sizeof(float) * size * size;
int vec_size = sizeof(float) * size;
int grid1 = ((size + 1) / BLOCK1) + (((size + 1) % BLOCK1 == 0) ? 0 : 1);
int grid2 = ((size + 1) / BLOCK2) + (((size + 1) % BLOCK2 == 0) ? 0 : 1);
int *max_pivot;
float *A_d, *B_d, *M_d;
dim3 dimBlock(BLOCK2, BLOCK2);
dim3 dimGrid(grid2, grid2);
hipMalloc((void **) &A_d, mat_size);
hipMemcpy(A_d, A, mat_size, hipMemcpyHostToDevice);
hipMalloc((void **) &B_d, vec_size);
hipMemcpy(B_d, B, vec_size, hipMemcpyHostToDevice);
hipMalloc((void **) &M_d, vec_size);
hipMalloc((void **) &max_pivot, sizeof(int));
for (int pivot = 0; pivot < size; pivot++)
{
cudaPivot<<<1, 1>>>(A_d, max_pivot, pivot, size);
cudaSwap<<<grid1, BLOCK1>>>(A_d, B_d, max_pivot, pivot, size);
cudaCalcM<<<grid1, BLOCK1>>>(A_d, B_d, M_d, pivot, size);
cudaGauss<<<dimGrid, dimBlock>>>(A_d, B_d, M_d, pivot, size);
}
for (int pivot = size - 1; pivot >= 0; pivot--)
{
cudaBackSub<<<grid1, BLOCK1>>>(A_d, B_d, pivot, size);
}
cudaCoeff<<<grid1, BLOCK1>>>(A_d, B_d, size);
hipMemcpy(X, B_d, vec_size, hipMemcpyDeviceToHost);
hipFree(A_d);
hipFree(B_d);
hipFree(M_d);
hipFree(max_pivot);
}
int pivot_routine(float *matrix, int start, int end, int pivot)
{
float t_max = 0.0, max = 0.0;
int t_maxi = pivot, maxi = pivot;
{
for (int i = start; i < end; i++)
{
float abs = fabsf(matrix[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
if (max > t_max)
{
t_max = max;
t_maxi = maxi;
}
}
return t_maxi;
}
void gauss_routine(float *matrix, float *vector, int start, int end, int pivot)
{
for (int i = start; i < end; i++)
{
float m = matrix[i * size + pivot] / matrix[pivot * size + pivot];
for (int j = pivot; j < size; j++)
matrix[i * size + j] -= m * matrix[pivot * size + j];
vector[i] -= m * vector[pivot];
}
}
void back_routine(float *matrix, float *vector, int start, int end, int pivot)
{
float m = vector[pivot] / matrix[pivot * size + pivot];
for (int i = start; i < end; i++)
vector[i] -= m * matrix[i * size + pivot];
}
void single_gaussian(void)
{
int maxi;
float swap;
for (int i = 0; i < size; i++)
{
maxi = pivot_routine(matrixA, i, size, i);
for (int j = 0; j < size; j++)
{
swap = matrixA[i * size + j];
matrixA[i * size + j] = matrixA[maxi * size + j];
matrixA[maxi * size + j] = swap;
}
swap = vectorB[i];
vectorB[i] = vectorB[maxi];
vectorB[maxi] = swap;
gauss_routine(matrixA, vectorB, i + 1, size, i);
}
for (int i = size - 1; i >= 0; i--)
{
back_routine(matrixA, vectorB, 0, i, i);
vectorB[i] /= matrixA[i * size + i];
}
return;
}
float L2_norm(float *matrixA, float *vectorX, float *vectorB, int size)
{
float norm = 0.0, sum;
for (int i = 0; i < size; i++)
{
sum = 0.0;
for (int j = 0; j < size; j++)
sum += matrixA[i * size + j] * vectorX[j];
sum -= vectorB[i];
norm += sum * sum;
}
return sqrt(norm);
}
int main(int argc, char **argv, char **envp)
{
int opt, t_sec = time(NULL);
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
vectorB = make_vector(size);
vectorX = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_gaussian(matrixA, vectorB, vectorX, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
single_gaussian();
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
free(vectorX);
vectorX = vectorB;
free(matrixA);
free(vectorB);
matrixA = make_matrix(size);
vectorB = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#define NANO 1000000000
#define PGSIZE 0x1000
#define BLOCK1 1024
#define BLOCK2 32
int size;
float *matrixA, *vectorB, *vectorX;
__global__
void cudaPivot(float *A_d, int *max_pivot, int pivot, int size)
{
float max = fabsf(A_d[pivot * size + pivot]);
int maxi = pivot;
for (int i = pivot + 1; i < size; i++)
{
float abs = fabsf(A_d[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
*max_pivot = maxi;
return;
}
__global__
void cudaSwap(float *A_d, float *B_d, int *max_pivot, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot <= i) && (i < size))
{
float temp = A_d[pivot * size + i];
A_d[pivot * size + i] = A_d[*max_pivot * size + i];
A_d[*max_pivot * size + i] = temp;
}
else if (i == size)
{
float temp = B_d[pivot];
B_d[pivot] = B_d[*max_pivot];
B_d[*max_pivot] = temp;
}
return;
}
__global__
void cudaCalcM(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ((pivot < i) && (i < size))
{
M_d[i] = A_d[i * size + pivot] / A_d[pivot * size + pivot];
}
}
__global__
void cudaGauss(float *A_d, float *B_d, float *M_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if ((pivot < i) && (i < size) && (pivot <= j) && (j <= size))
{
if (j == size)
{
B_d[i] -= M_d[i] * B_d[pivot];
}
else
{
A_d[i * size + j] -= M_d[i] * A_d[pivot * size + j];
}
}
}
__global__
void cudaBackSub(float *A_d, float *B_d, int pivot, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < pivot)
{
float m = B_d[pivot] / A_d[pivot * size + pivot];
B_d[i] -= m * A_d[i * size + pivot];
}
}
__global__
void cudaCoeff(float *A_d, float *B_d, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < size)
B_d[i] = B_d[i] / A_d[i * size + i];
}
float *make_vector(int size)
{
float *vector = (float *) malloc(sizeof(float) * size);
if (vector == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return vector;
}
float *make_matrix(int size)
{
float *matrix = (float *) malloc(sizeof(float) * size * size);
if (matrix == NULL)
{
perror("malloc");
exit(0);
}
if (malloc(PGSIZE) == NULL)
{
perror("malloc");
exit(0);
}
return matrix;
}
void set_vector(float *vector, int size)
{
for (int i = 0; i < size; i++)
vector[i] = (float) drand48();
}
void set_matrix(float *matrix, int size)
{
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
matrix[i * size + j] = (float) drand48();
}
}
void print_vector(float *vector, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
printf(" %f", vector[i]);
printf(";");
}
printf(" ]\n");
}
void print_matrix(float *matrix, int size)
{
printf("[");
for (int i = 0; i < size; i++)
{
for (int j = 0; j < size; j++)
printf(" %f", matrix[i * size + j]);
printf(";");
}
printf(" ]\n");
}
void cuda_gaussian(float *A, float *B, float *X, int size)
{
int mat_size = sizeof(float) * size * size;
int vec_size = sizeof(float) * size;
int grid1 = ((size + 1) / BLOCK1) + (((size + 1) % BLOCK1 == 0) ? 0 : 1);
int grid2 = ((size + 1) / BLOCK2) + (((size + 1) % BLOCK2 == 0) ? 0 : 1);
int *max_pivot;
float *A_d, *B_d, *M_d;
dim3 dimBlock(BLOCK2, BLOCK2);
dim3 dimGrid(grid2, grid2);
hipMalloc((void **) &A_d, mat_size);
hipMemcpy(A_d, A, mat_size, hipMemcpyHostToDevice);
hipMalloc((void **) &B_d, vec_size);
hipMemcpy(B_d, B, vec_size, hipMemcpyHostToDevice);
hipMalloc((void **) &M_d, vec_size);
hipMalloc((void **) &max_pivot, sizeof(int));
for (int pivot = 0; pivot < size; pivot++)
{
cudaPivot<<<1, 1>>>(A_d, max_pivot, pivot, size);
cudaSwap<<<grid1, BLOCK1>>>(A_d, B_d, max_pivot, pivot, size);
cudaCalcM<<<grid1, BLOCK1>>>(A_d, B_d, M_d, pivot, size);
cudaGauss<<<dimGrid, dimBlock>>>(A_d, B_d, M_d, pivot, size);
}
for (int pivot = size - 1; pivot >= 0; pivot--)
{
cudaBackSub<<<grid1, BLOCK1>>>(A_d, B_d, pivot, size);
}
cudaCoeff<<<grid1, BLOCK1>>>(A_d, B_d, size);
hipMemcpy(X, B_d, vec_size, hipMemcpyDeviceToHost);
hipFree(A_d);
hipFree(B_d);
hipFree(M_d);
hipFree(max_pivot);
}
int pivot_routine(float *matrix, int start, int end, int pivot)
{
float t_max = 0.0, max = 0.0;
int t_maxi = pivot, maxi = pivot;
{
for (int i = start; i < end; i++)
{
float abs = fabsf(matrix[i * size + pivot]);
if (abs > max)
{
max = abs;
maxi = i;
}
}
if (max > t_max)
{
t_max = max;
t_maxi = maxi;
}
}
return t_maxi;
}
void gauss_routine(float *matrix, float *vector, int start, int end, int pivot)
{
for (int i = start; i < end; i++)
{
float m = matrix[i * size + pivot] / matrix[pivot * size + pivot];
for (int j = pivot; j < size; j++)
matrix[i * size + j] -= m * matrix[pivot * size + j];
vector[i] -= m * vector[pivot];
}
}
void back_routine(float *matrix, float *vector, int start, int end, int pivot)
{
float m = vector[pivot] / matrix[pivot * size + pivot];
for (int i = start; i < end; i++)
vector[i] -= m * matrix[i * size + pivot];
}
void single_gaussian(void)
{
int maxi;
float swap;
for (int i = 0; i < size; i++)
{
maxi = pivot_routine(matrixA, i, size, i);
for (int j = 0; j < size; j++)
{
swap = matrixA[i * size + j];
matrixA[i * size + j] = matrixA[maxi * size + j];
matrixA[maxi * size + j] = swap;
}
swap = vectorB[i];
vectorB[i] = vectorB[maxi];
vectorB[maxi] = swap;
gauss_routine(matrixA, vectorB, i + 1, size, i);
}
for (int i = size - 1; i >= 0; i--)
{
back_routine(matrixA, vectorB, 0, i, i);
vectorB[i] /= matrixA[i * size + i];
}
return;
}
float L2_norm(float *matrixA, float *vectorX, float *vectorB, int size)
{
float norm = 0.0, sum;
for (int i = 0; i < size; i++)
{
sum = 0.0;
for (int j = 0; j < size; j++)
sum += matrixA[i * size + j] * vectorX[j];
sum -= vectorB[i];
norm += sum * sum;
}
return sqrt(norm);
}
int main(int argc, char **argv, char **envp)
{
int opt, t_sec = time(NULL);
struct timespec tstart, tend;
while ((opt = getopt(argc, argv, "n:p:")) != -1)
{
switch (opt)
{
case 'n':
size = atoi(optarg);
break;
case '?':
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
}
if (size <= 0)
{
printf("Usage: %s -n N\n", argv[0]);
exit(0);
}
matrixA = make_matrix(size);
vectorB = make_vector(size);
vectorX = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("Multi Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
cuda_gaussian(matrixA, vectorB, vectorX, size);
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
long start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
long end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
double microsec = (end_nsec - start_nsec) / 1000.0;
printf("Multi Thread Computation End: %.3f us.\n", microsec);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
printf("Single Thread Computation Start\n");
if (clock_gettime(CLOCK_MONOTONIC, &tstart) == -1)
{
perror("clock_gettime");
exit(0);
}
single_gaussian();
if (clock_gettime(CLOCK_MONOTONIC, &tend) == -1)
{
perror("clock_gettime");
exit(0);
}
start_nsec = tstart.tv_sec * NANO + tstart.tv_nsec;
end_nsec = tend.tv_sec * NANO + tend.tv_nsec;
microsec = (end_nsec - start_nsec) / 1000.0;
printf("Single Thread Computation End: %.3f us.\n", microsec);
free(vectorX);
vectorX = vectorB;
free(matrixA);
free(vectorB);
matrixA = make_matrix(size);
vectorB = make_vector(size);
srand48(t_sec);
set_matrix(matrixA, size);
set_vector(vectorB, size);
printf("L2-norm : %g\n", L2_norm(matrixA, vectorX, vectorB, size));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cudaPivotPfPiii
.globl _Z9cudaPivotPfPiii
.p2align 8
.type _Z9cudaPivotPfPiii,@function
_Z9cudaPivotPfPiii:
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_i32 s8, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s8, s3
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_add_i32 s6, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s2
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_load_b32 s6, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_bitset0_b32 s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v0, s6
s_mul_i32 s6, s3, s8
s_add_i32 s6, s2, s6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[10:11], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_load_b32 s7, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s9, |s7|, v0
v_cndmask_b32_e64 v0, v0, |s7|, s9
s_and_b32 s7, s9, exec_lo
s_cselect_b32 s2, s8, s2
s_add_i32 s8, s8, 1
s_add_i32 s6, s6, s3
s_cmp_ge_i32 s8, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaPivotPfPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cudaPivotPfPiii, .Lfunc_end0-_Z9cudaPivotPfPiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8cudaSwapPfS_Piii
.globl _Z8cudaSwapPfS_Piii
.p2align 8
.type _Z8cudaSwapPfS_Piii,@function
_Z8cudaSwapPfS_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_cmp_le_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s3
s_cbranch_execnz .LBB1_3
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execnz .LBB1_6
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB1_3:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e64 s7, v1
s_cbranch_execz .LBB1_5
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b32 s10, s[4:5], 0x0
s_ashr_i32 s13, s6, 31
s_mov_b32 s12, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s8, s12
s_addc_u32 s13, s9, s13
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[10:11], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_clause 0x1
s_load_b32 s10, s[8:9], 0x0
s_load_b32 s11, s[12:13], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s10
v_mov_b32_e32 v2, s11
s_clause 0x1
global_store_b32 v0, v1, s[12:13]
global_store_b32 v0, v2, s[8:9]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_2
.LBB1_6:
s_load_b32 s2, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s7, s6, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cudaSwapPfS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8cudaSwapPfS_Piii, .Lfunc_end1-_Z8cudaSwapPfS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9cudaCalcMPfS_S_ii
.globl _Z9cudaCalcMPfS_S_ii
.p2align 8
.type _Z9cudaCalcMPfS_S_ii,@function
_Z9cudaCalcMPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, s4, v1
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s5, s[4:5]
s_add_i32 s5, s5, 1
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v3, 31, v2
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
global_load_b32 v3, v[2:3], off
s_load_b32 s2, s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v0, null, s2, s2, v3
v_div_scale_f32 v5, vcc_lo, v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v4, 1.0
v_fmac_f32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v2, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v2, v4
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v0, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v0, v4, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, s2, v3
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaCalcMPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9cudaCalcMPfS_S_ii, .Lfunc_end2-_Z9cudaCalcMPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9cudaGaussPfS_S_ii
.globl _Z9cudaGaussPfS_S_ii
.p2align 8
.type _Z9cudaGaussPfS_S_ii,@function
_Z9cudaGaussPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_lt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v0
v_cmp_le_i32_e64 s3, s6, v2
v_cmp_ge_i32_e64 s4, s7, v2
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_6
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v7, v[3:4], off
v_cmpx_ne_u32_e64 s7, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB3_3
v_mad_u64_u32 v[3:4], null, s7, s6, v[2:3]
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, s7, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB3_3:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB3_5
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
.LBB3_5:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[5:6], off
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_fma_f32 v0, -v7, v0, v1
global_store_b32 v[3:4], v0, off
.LBB3_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaGaussPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9cudaGaussPfS_S_ii, .Lfunc_end3-_Z9cudaGaussPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11cudaBackSubPfS_ii
.globl _Z11cudaBackSubPfS_ii
.p2align 8
.type _Z11cudaBackSubPfS_ii,@function
_Z11cudaBackSubPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB4_2
s_clause 0x1
s_load_b32 s8, s[0:1], 0x14
s_load_b128 s[0:3], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v2, 31, v1
s_lshl_b64 s[6:7], s[4:5], 2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, s8, s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_add_u32 s2, s2, s6
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_addc_u32 s3, s3, s7
s_add_i32 s5, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s4
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v4, null, s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v4, v4, s0, s1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, -v4, v2, v3
global_store_b32 v[0:1], v2, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cudaBackSubPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z11cudaBackSubPfS_ii, .Lfunc_end4-_Z11cudaBackSubPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9cudaCoeffPfS_i
.globl _Z9cudaCoeffPfS_i
.p2align 8
.type _Z9cudaCoeffPfS_i,@function
_Z9cudaCoeffPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB5_2
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v1, s2, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, v2, v2, v4
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v3, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v4, v2, v4
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v3, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v7, v6
v_div_fmas_f32 v3, v3, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, v4
global_store_b32 v[0:1], v2, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaCoeffPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z9cudaCoeffPfS_i, .Lfunc_end5-_Z9cudaCoeffPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaPivotPfPiii
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z9cudaPivotPfPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cudaSwapPfS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cudaSwapPfS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaCalcMPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cudaCalcMPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
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.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
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.size: 8
.value_kind: global_buffer
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.size: 8
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.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaGaussPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cudaGaussPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
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.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
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.value_kind: by_value
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.size: 4
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- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cudaBackSubPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11cudaBackSubPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaCoeffPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9cudaCoeffPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 10
__global__
void outputFromGPU() {
printf("Hello from GPU!\n");
}
__global__
void add(int a, int b, int * c) {
*c = a + b;
}
__global__
void addTwoArrays(int* a, int* b, int* c) {
int bid = blockIdx.x;
if(bid < N) {
c[bid] = a[bid] + b[bid];
}
}
void mainForAdd() {
// printf("Hello from CPU!\n");
// outputFromGPU<<<2,5>>>();
// cudaDeviceSynchronize();
int a, b, c;
int * dev_c;
a = 3;
b = 4;
cudaMalloc((void **) &dev_c, sizeof(int));
add<<<1,1>>>(a,b,dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d + %d = %d\n", a, b, c);
cudaFree(dev_c);
}
void mainForAddTwoArrays() {
int i, a[N], b[N], c[N];
int *dev_a;
int *dev_b;
int *dev_c;
cudaMalloc((void**) &dev_a, N*sizeof(int));
cudaMalloc((void**) &dev_b, N*sizeof(int));
cudaMalloc((void**) &dev_c, N*sizeof(int));
for(i = 0; i < N; i++) {
a[i] = i;
b[i] = i*i;
}
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
// printf("here1\n");
addTwoArrays<<<N, 1>>>(dev_a, dev_b, dev_c);
// printf("here2\n");
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost);
printf("\na + b = c\n");
for(i = 0; i < N; i++) {
printf("\n%5d + %5d = %5d\n", a[i], b[i], c[i]);
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
}
int main(void) {
mainForAddTwoArrays();
} | code for sm_80
Function : _Z12addTwoArraysPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13outputFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x8 ; /* 0x0000000800007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 10
__global__
void outputFromGPU() {
printf("Hello from GPU!\n");
}
__global__
void add(int a, int b, int * c) {
*c = a + b;
}
__global__
void addTwoArrays(int* a, int* b, int* c) {
int bid = blockIdx.x;
if(bid < N) {
c[bid] = a[bid] + b[bid];
}
}
void mainForAdd() {
// printf("Hello from CPU!\n");
// outputFromGPU<<<2,5>>>();
// cudaDeviceSynchronize();
int a, b, c;
int * dev_c;
a = 3;
b = 4;
cudaMalloc((void **) &dev_c, sizeof(int));
add<<<1,1>>>(a,b,dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d + %d = %d\n", a, b, c);
cudaFree(dev_c);
}
void mainForAddTwoArrays() {
int i, a[N], b[N], c[N];
int *dev_a;
int *dev_b;
int *dev_c;
cudaMalloc((void**) &dev_a, N*sizeof(int));
cudaMalloc((void**) &dev_b, N*sizeof(int));
cudaMalloc((void**) &dev_c, N*sizeof(int));
for(i = 0; i < N; i++) {
a[i] = i;
b[i] = i*i;
}
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
// printf("here1\n");
addTwoArrays<<<N, 1>>>(dev_a, dev_b, dev_c);
// printf("here2\n");
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost);
printf("\na + b = c\n");
for(i = 0; i < N; i++) {
printf("\n%5d + %5d = %5d\n", a[i], b[i], c[i]);
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
}
int main(void) {
mainForAddTwoArrays();
} | .file "tmpxft_000bc685_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13outputFromGPUvv
.type _Z32__device_stub__Z13outputFromGPUvv, @function
_Z32__device_stub__Z13outputFromGPUvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13outputFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z13outputFromGPUvv, .-_Z32__device_stub__Z13outputFromGPUvv
.globl _Z13outputFromGPUv
.type _Z13outputFromGPUv, @function
_Z13outputFromGPUv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13outputFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13outputFromGPUv, .-_Z13outputFromGPUv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl _Z10mainForAddv
.type _Z10mainForAddv, @function
_Z10mainForAddv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %r8d
movl $4, %ecx
movl $3, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $4, %esi
movl $3, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10mainForAddv, .-_Z10mainForAddv
.globl _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
.type _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_, @function
_Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12addTwoArraysPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_, .-_Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
.globl _Z12addTwoArraysPiS_S_
.type _Z12addTwoArraysPiS_S_, @function
_Z12addTwoArraysPiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z12addTwoArraysPiS_S_, .-_Z12addTwoArraysPiS_S_
.section .rodata.str1.1
.LC1:
.string "\na + b = c\n"
.LC2:
.string "\n%5d + %5d = %5d\n"
.text
.globl _Z19mainForAddTwoArraysv
.type _Z19mainForAddTwoArraysv, @function
_Z19mainForAddTwoArraysv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L34:
movl %eax, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L34
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L35:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L36:
movl 96(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 144(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L36
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
jmp .L35
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19mainForAddTwoArraysv, .-_Z19mainForAddTwoArraysv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19mainForAddTwoArraysv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z12addTwoArraysPiS_S_"
.LC4:
.string "_Z3addiiPi"
.LC5:
.string "_Z13outputFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12addTwoArraysPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13outputFromGPUv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 10
__global__
void outputFromGPU() {
printf("Hello from GPU!\n");
}
__global__
void add(int a, int b, int * c) {
*c = a + b;
}
__global__
void addTwoArrays(int* a, int* b, int* c) {
int bid = blockIdx.x;
if(bid < N) {
c[bid] = a[bid] + b[bid];
}
}
void mainForAdd() {
// printf("Hello from CPU!\n");
// outputFromGPU<<<2,5>>>();
// cudaDeviceSynchronize();
int a, b, c;
int * dev_c;
a = 3;
b = 4;
cudaMalloc((void **) &dev_c, sizeof(int));
add<<<1,1>>>(a,b,dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d + %d = %d\n", a, b, c);
cudaFree(dev_c);
}
void mainForAddTwoArrays() {
int i, a[N], b[N], c[N];
int *dev_a;
int *dev_b;
int *dev_c;
cudaMalloc((void**) &dev_a, N*sizeof(int));
cudaMalloc((void**) &dev_b, N*sizeof(int));
cudaMalloc((void**) &dev_c, N*sizeof(int));
for(i = 0; i < N; i++) {
a[i] = i;
b[i] = i*i;
}
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
// printf("here1\n");
addTwoArrays<<<N, 1>>>(dev_a, dev_b, dev_c);
// printf("here2\n");
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost);
printf("\na + b = c\n");
for(i = 0; i < N; i++) {
printf("\n%5d + %5d = %5d\n", a[i], b[i], c[i]);
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
}
int main(void) {
mainForAddTwoArrays();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10
__global__
void outputFromGPU() {
printf("Hello from GPU!\n");
}
__global__
void add(int a, int b, int * c) {
*c = a + b;
}
__global__
void addTwoArrays(int* a, int* b, int* c) {
int bid = blockIdx.x;
if(bid < N) {
c[bid] = a[bid] + b[bid];
}
}
void mainForAdd() {
// printf("Hello from CPU!\n");
// outputFromGPU<<<2,5>>>();
// cudaDeviceSynchronize();
int a, b, c;
int * dev_c;
a = 3;
b = 4;
hipMalloc((void **) &dev_c, sizeof(int));
add<<<1,1>>>(a,b,dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("%d + %d = %d\n", a, b, c);
hipFree(dev_c);
}
void mainForAddTwoArrays() {
int i, a[N], b[N], c[N];
int *dev_a;
int *dev_b;
int *dev_c;
hipMalloc((void**) &dev_a, N*sizeof(int));
hipMalloc((void**) &dev_b, N*sizeof(int));
hipMalloc((void**) &dev_c, N*sizeof(int));
for(i = 0; i < N; i++) {
a[i] = i;
b[i] = i*i;
}
hipMemcpy(dev_a, a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, N*sizeof(int), hipMemcpyHostToDevice);
// printf("here1\n");
addTwoArrays<<<N, 1>>>(dev_a, dev_b, dev_c);
// printf("here2\n");
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost);
printf("\na + b = c\n");
for(i = 0; i < N; i++) {
printf("\n%5d + %5d = %5d\n", a[i], b[i], c[i]);
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
}
int main(void) {
mainForAddTwoArrays();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 10
__global__
void outputFromGPU() {
printf("Hello from GPU!\n");
}
__global__
void add(int a, int b, int * c) {
*c = a + b;
}
__global__
void addTwoArrays(int* a, int* b, int* c) {
int bid = blockIdx.x;
if(bid < N) {
c[bid] = a[bid] + b[bid];
}
}
void mainForAdd() {
// printf("Hello from CPU!\n");
// outputFromGPU<<<2,5>>>();
// cudaDeviceSynchronize();
int a, b, c;
int * dev_c;
a = 3;
b = 4;
hipMalloc((void **) &dev_c, sizeof(int));
add<<<1,1>>>(a,b,dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("%d + %d = %d\n", a, b, c);
hipFree(dev_c);
}
void mainForAddTwoArrays() {
int i, a[N], b[N], c[N];
int *dev_a;
int *dev_b;
int *dev_c;
hipMalloc((void**) &dev_a, N*sizeof(int));
hipMalloc((void**) &dev_b, N*sizeof(int));
hipMalloc((void**) &dev_c, N*sizeof(int));
for(i = 0; i < N; i++) {
a[i] = i;
b[i] = i*i;
}
hipMemcpy(dev_a, a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, N*sizeof(int), hipMemcpyHostToDevice);
// printf("here1\n");
addTwoArrays<<<N, 1>>>(dev_a, dev_b, dev_c);
// printf("here2\n");
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost);
printf("\na + b = c\n");
for(i = 0; i < N; i++) {
printf("\n%5d + %5d = %5d\n", a[i], b[i], c[i]);
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
}
int main(void) {
mainForAddTwoArrays();
} | .text
.file "cuda.hip"
.globl _Z28__device_stub__outputFromGPUv # -- Begin function _Z28__device_stub__outputFromGPUv
.p2align 4, 0x90
.type _Z28__device_stub__outputFromGPUv,@function
_Z28__device_stub__outputFromGPUv: # @_Z28__device_stub__outputFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__outputFromGPUv, .Lfunc_end0-_Z28__device_stub__outputFromGPUv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addiiPi, .Lfunc_end1-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__addTwoArraysPiS_S_ # -- Begin function _Z27__device_stub__addTwoArraysPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__addTwoArraysPiS_S_,@function
_Z27__device_stub__addTwoArraysPiS_S_: # @_Z27__device_stub__addTwoArraysPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12addTwoArraysPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__addTwoArraysPiS_S_, .Lfunc_end2-_Z27__device_stub__addTwoArraysPiS_S_
.cfi_endproc
# -- End function
.globl _Z10mainForAddv # -- Begin function _Z10mainForAddv
.p2align 4, 0x90
.type _Z10mainForAddv,@function
_Z10mainForAddv: # @_Z10mainForAddv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rsp), %rax
movl $3, 12(%rsp)
movl $4, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %ecx
movl $.L.str, %edi
movl $3, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10mainForAddv, .Lfunc_end3-_Z10mainForAddv
.cfi_endproc
# -- End function
.globl _Z19mainForAddTwoArraysv # -- Begin function _Z19mainForAddTwoArraysv
.p2align 4, 0x90
.type _Z19mainForAddTwoArraysv,@function
_Z19mainForAddTwoArraysv: # @_Z19mainForAddTwoArraysv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 144(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB4_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12addTwoArraysPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl 144(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB4_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z19mainForAddTwoArraysv, .Lfunc_end4-_Z19mainForAddTwoArraysv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z19mainForAddTwoArraysv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13outputFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12addTwoArraysPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13outputFromGPUv,@object # @_Z13outputFromGPUv
.section .rodata,"a",@progbits
.globl _Z13outputFromGPUv
.p2align 3, 0x0
_Z13outputFromGPUv:
.quad _Z28__device_stub__outputFromGPUv
.size _Z13outputFromGPUv, 8
.type _Z3addiiPi,@object # @_Z3addiiPi
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type _Z12addTwoArraysPiS_S_,@object # @_Z12addTwoArraysPiS_S_
.globl _Z12addTwoArraysPiS_S_
.p2align 3, 0x0
_Z12addTwoArraysPiS_S_:
.quad _Z27__device_stub__addTwoArraysPiS_S_
.size _Z12addTwoArraysPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%5d + %5d = %5d\n"
.size .L.str.2, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13outputFromGPUv"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addiiPi"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12addTwoArraysPiS_S_"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\na + b = c"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__outputFromGPUv
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym _Z27__device_stub__addTwoArraysPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13outputFromGPUv
.addrsig_sym _Z3addiiPi
.addrsig_sym _Z12addTwoArraysPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bc685_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13outputFromGPUvv
.type _Z32__device_stub__Z13outputFromGPUvv, @function
_Z32__device_stub__Z13outputFromGPUvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13outputFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z13outputFromGPUvv, .-_Z32__device_stub__Z13outputFromGPUvv
.globl _Z13outputFromGPUv
.type _Z13outputFromGPUv, @function
_Z13outputFromGPUv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13outputFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13outputFromGPUv, .-_Z13outputFromGPUv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl _Z10mainForAddv
.type _Z10mainForAddv, @function
_Z10mainForAddv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %r8d
movl $4, %ecx
movl $3, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $4, %esi
movl $3, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10mainForAddv, .-_Z10mainForAddv
.globl _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
.type _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_, @function
_Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12addTwoArraysPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_, .-_Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
.globl _Z12addTwoArraysPiS_S_
.type _Z12addTwoArraysPiS_S_, @function
_Z12addTwoArraysPiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z12addTwoArraysPiS_S_, .-_Z12addTwoArraysPiS_S_
.section .rodata.str1.1
.LC1:
.string "\na + b = c\n"
.LC2:
.string "\n%5d + %5d = %5d\n"
.text
.globl _Z19mainForAddTwoArraysv
.type _Z19mainForAddTwoArraysv, @function
_Z19mainForAddTwoArraysv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L34:
movl %eax, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L34
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L35:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L36:
movl 96(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 144(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L36
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z12addTwoArraysPiS_S_PiS_S_
jmp .L35
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19mainForAddTwoArraysv, .-_Z19mainForAddTwoArraysv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19mainForAddTwoArraysv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z12addTwoArraysPiS_S_"
.LC4:
.string "_Z3addiiPi"
.LC5:
.string "_Z13outputFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12addTwoArraysPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13outputFromGPUv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z28__device_stub__outputFromGPUv # -- Begin function _Z28__device_stub__outputFromGPUv
.p2align 4, 0x90
.type _Z28__device_stub__outputFromGPUv,@function
_Z28__device_stub__outputFromGPUv: # @_Z28__device_stub__outputFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__outputFromGPUv, .Lfunc_end0-_Z28__device_stub__outputFromGPUv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addiiPi, .Lfunc_end1-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__addTwoArraysPiS_S_ # -- Begin function _Z27__device_stub__addTwoArraysPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__addTwoArraysPiS_S_,@function
_Z27__device_stub__addTwoArraysPiS_S_: # @_Z27__device_stub__addTwoArraysPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12addTwoArraysPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__addTwoArraysPiS_S_, .Lfunc_end2-_Z27__device_stub__addTwoArraysPiS_S_
.cfi_endproc
# -- End function
.globl _Z10mainForAddv # -- Begin function _Z10mainForAddv
.p2align 4, 0x90
.type _Z10mainForAddv,@function
_Z10mainForAddv: # @_Z10mainForAddv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rsp), %rax
movl $3, 12(%rsp)
movl $4, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %ecx
movl $.L.str, %edi
movl $3, %esi
movl $4, %edx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10mainForAddv, .Lfunc_end3-_Z10mainForAddv
.cfi_endproc
# -- End function
.globl _Z19mainForAddTwoArraysv # -- Begin function _Z19mainForAddTwoArraysv
.p2align 4, 0x90
.type _Z19mainForAddTwoArraysv,@function
_Z19mainForAddTwoArraysv: # @_Z19mainForAddTwoArraysv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 144(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB4_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12addTwoArraysPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl 144(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB4_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z19mainForAddTwoArraysv, .Lfunc_end4-_Z19mainForAddTwoArraysv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z19mainForAddTwoArraysv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13outputFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12addTwoArraysPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13outputFromGPUv,@object # @_Z13outputFromGPUv
.section .rodata,"a",@progbits
.globl _Z13outputFromGPUv
.p2align 3, 0x0
_Z13outputFromGPUv:
.quad _Z28__device_stub__outputFromGPUv
.size _Z13outputFromGPUv, 8
.type _Z3addiiPi,@object # @_Z3addiiPi
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type _Z12addTwoArraysPiS_S_,@object # @_Z12addTwoArraysPiS_S_
.globl _Z12addTwoArraysPiS_S_
.p2align 3, 0x0
_Z12addTwoArraysPiS_S_:
.quad _Z27__device_stub__addTwoArraysPiS_S_
.size _Z12addTwoArraysPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%5d + %5d = %5d\n"
.size .L.str.2, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13outputFromGPUv"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addiiPi"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12addTwoArraysPiS_S_"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\na + b = c"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__outputFromGPUv
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym _Z27__device_stub__addTwoArraysPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13outputFromGPUv
.addrsig_sym _Z3addiiPi
.addrsig_sym _Z12addTwoArraysPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void test (int input, double *num){
int idx = threadIdx.x;
num[idx] =input-num[idx]*num[idx];
}
void run (int input, double *ans, int digit, double timer){
if (digit <= 0) return;
double *r;
double *num = new double[100];
for (int i=0; i<100; i++){
num[i] = *ans + timer*i;
}
cudaMalloc((void**) &r, 100*sizeof(double));
cudaMemcpy(r, num, 100*sizeof(double), cudaMemcpyHostToDevice);
test <<< 1,100 >>> (input,r);
cudaMemcpy(num, r, 100*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(r);
for (int i=0; i<100; i++){
if (num[i] < 0){
*ans += timer*(i-1);
break;
}else if (i == 99) {
*ans += timer*99;
}
}
delete num;
run(input,ans,digit - 1,timer/100);
}
int find_timer(int input){
int ans = 1, i = 100;
while(input /= i) ans *= 100;
//printf("%d",ans);
return ans;
}
int main (void){
//char trash[100+5];
int digit,input;
//scanf("%s %s",&trash,&trash);
scanf("%d %d",&digit,&input);
int timer = find_timer(input);
double *ans = new double;
run(input, ans, digit, timer);
printf("%.10f\n",*ans);
delete ans;
return 0;
} | code for sm_80
Function : _Z4testiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x001fca00078e0205 */
/*0050*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ I2F.F64 R2, c[0x0][0x160] ; /* 0x0000580000027b12 */
/* 0x000ea40000201c00 */
/*0070*/ DFMA R2, -R6, R6, R2 ; /* 0x000000060602722b */
/* 0x004e0e0000000102 */
/*0080*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void test (int input, double *num){
int idx = threadIdx.x;
num[idx] =input-num[idx]*num[idx];
}
void run (int input, double *ans, int digit, double timer){
if (digit <= 0) return;
double *r;
double *num = new double[100];
for (int i=0; i<100; i++){
num[i] = *ans + timer*i;
}
cudaMalloc((void**) &r, 100*sizeof(double));
cudaMemcpy(r, num, 100*sizeof(double), cudaMemcpyHostToDevice);
test <<< 1,100 >>> (input,r);
cudaMemcpy(num, r, 100*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(r);
for (int i=0; i<100; i++){
if (num[i] < 0){
*ans += timer*(i-1);
break;
}else if (i == 99) {
*ans += timer*99;
}
}
delete num;
run(input,ans,digit - 1,timer/100);
}
int find_timer(int input){
int ans = 1, i = 100;
while(input /= i) ans *= 100;
//printf("%d",ans);
return ans;
}
int main (void){
//char trash[100+5];
int digit,input;
//scanf("%s %s",&trash,&trash);
scanf("%d %d",&digit,&input);
int timer = find_timer(input);
double *ans = new double;
run(input, ans, digit, timer);
printf("%.10f\n",*ans);
delete ans;
return 0;
} | .file "tmpxft_0010587d_00000000-6_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10find_timeri
.type _Z10find_timeri, @function
_Z10find_timeri:
.LFB2058:
.cfi_startproc
endbr64
movslq %edi, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
sarl $31, %edi
subl %edi, %edx
je .L6
movl $1, %ecx
.L5:
imull $100, %ecx, %ecx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, %edx
jne .L5
.L3:
movl %ecx, %eax
ret
.L6:
movl $1, %ecx
jmp .L3
.cfi_endproc
.LFE2058:
.size _Z10find_timeri, .-_Z10find_timeri
.globl _Z24__device_stub__Z4testiPdiPd
.type _Z24__device_stub__Z4testiPdiPd, @function
_Z24__device_stub__Z4testiPdiPd:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z4testiPdiPd, .-_Z24__device_stub__Z4testiPdiPd
.globl _Z4testiPd
.type _Z4testiPd, @function
_Z4testiPd:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4testiPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4testiPd, .-_Z4testiPd
.globl _Z3runiPdid
.type _Z3runiPdid, @function
_Z3runiPdid:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
testl %edx, %edx
jle .L16
movl %edi, %r13d
movq %rsi, %rbp
movl %edx, %r12d
movl $800, %edi
call _Znam@PLT
movq %rax, %rbx
movsd 0(%rbp), %xmm1
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L18
leaq 24(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $800, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L19:
movl $2, %ecx
movl $800, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
pxor %xmm0, %xmm0
jmp .L24
.L30:
movq 24(%rsp), %rsi
movl %r13d, %edi
call _Z24__device_stub__Z4testiPdiPd
jmp .L19
.L31:
subl $1, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
addsd 0(%rbp), %xmm0
jmp .L22
.L23:
addq $1, %rax
.L24:
comisd (%rbx,%rax,8), %xmm0
ja .L31
cmpq $99, %rax
jne .L23
movsd 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
addsd 0(%rbp), %xmm0
.L22:
movsd %xmm0, 0(%rbp)
movl $8, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movsd 8(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
leal -1(%r12), %edx
movq %rbp, %rsi
movl %r13d, %edi
call _Z3runiPdid
.L16:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z3runiPdid, .-_Z3runiPdid
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%d %d"
.LC4:
.string "%.10f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdx
movq %rsp, %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
movl 4(%rsp), %edi
call _Z10find_timeri
movl %eax, %ebp
movl $8, %edi
call _Znwm@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
movl (%rsp), %edx
movq %rax, %rsi
movl 4(%rsp), %edi
call _Z3runiPdid
movsd (%rbx), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $8, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z4testiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079558144
.align 8
.LC2:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
__global__ void test (int input, double *num){
int idx = threadIdx.x;
num[idx] =input-num[idx]*num[idx];
}
void run (int input, double *ans, int digit, double timer){
if (digit <= 0) return;
double *r;
double *num = new double[100];
for (int i=0; i<100; i++){
num[i] = *ans + timer*i;
}
cudaMalloc((void**) &r, 100*sizeof(double));
cudaMemcpy(r, num, 100*sizeof(double), cudaMemcpyHostToDevice);
test <<< 1,100 >>> (input,r);
cudaMemcpy(num, r, 100*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(r);
for (int i=0; i<100; i++){
if (num[i] < 0){
*ans += timer*(i-1);
break;
}else if (i == 99) {
*ans += timer*99;
}
}
delete num;
run(input,ans,digit - 1,timer/100);
}
int find_timer(int input){
int ans = 1, i = 100;
while(input /= i) ans *= 100;
//printf("%d",ans);
return ans;
}
int main (void){
//char trash[100+5];
int digit,input;
//scanf("%s %s",&trash,&trash);
scanf("%d %d",&digit,&input);
int timer = find_timer(input);
double *ans = new double;
run(input, ans, digit, timer);
printf("%.10f\n",*ans);
delete ans;
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void test (int input, double *num){
int idx = threadIdx.x;
num[idx] =input-num[idx]*num[idx];
}
void run (int input, double *ans, int digit, double timer){
if (digit <= 0) return;
double *r;
double *num = new double[100];
for (int i=0; i<100; i++){
num[i] = *ans + timer*i;
}
hipMalloc((void**) &r, 100*sizeof(double));
hipMemcpy(r, num, 100*sizeof(double), hipMemcpyHostToDevice);
test <<< 1,100 >>> (input,r);
hipMemcpy(num, r, 100*sizeof(double), hipMemcpyDeviceToHost);
hipFree(r);
for (int i=0; i<100; i++){
if (num[i] < 0){
*ans += timer*(i-1);
break;
}else if (i == 99) {
*ans += timer*99;
}
}
delete num;
run(input,ans,digit - 1,timer/100);
}
int find_timer(int input){
int ans = 1, i = 100;
while(input /= i) ans *= 100;
//printf("%d",ans);
return ans;
}
int main (void){
//char trash[100+5];
int digit,input;
//scanf("%s %s",&trash,&trash);
scanf("%d %d",&digit,&input);
int timer = find_timer(input);
double *ans = new double;
run(input, ans, digit, timer);
printf("%.10f\n",*ans);
delete ans;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void test (int input, double *num){
int idx = threadIdx.x;
num[idx] =input-num[idx]*num[idx];
}
void run (int input, double *ans, int digit, double timer){
if (digit <= 0) return;
double *r;
double *num = new double[100];
for (int i=0; i<100; i++){
num[i] = *ans + timer*i;
}
hipMalloc((void**) &r, 100*sizeof(double));
hipMemcpy(r, num, 100*sizeof(double), hipMemcpyHostToDevice);
test <<< 1,100 >>> (input,r);
hipMemcpy(num, r, 100*sizeof(double), hipMemcpyDeviceToHost);
hipFree(r);
for (int i=0; i<100; i++){
if (num[i] < 0){
*ans += timer*(i-1);
break;
}else if (i == 99) {
*ans += timer*99;
}
}
delete num;
run(input,ans,digit - 1,timer/100);
}
int find_timer(int input){
int ans = 1, i = 100;
while(input /= i) ans *= 100;
//printf("%d",ans);
return ans;
}
int main (void){
//char trash[100+5];
int digit,input;
//scanf("%s %s",&trash,&trash);
scanf("%d %d",&digit,&input);
int timer = find_timer(input);
double *ans = new double;
run(input, ans, digit, timer);
printf("%.10f\n",*ans);
delete ans;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testiPd
.globl _Z4testiPd
.p2align 8
.type _Z4testiPd,@function
_Z4testiPd:
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 3, v0
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v4, s[2:3]
v_cvt_f64_i32_e32 v[2:3], s0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], -v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testiPd, .Lfunc_end0-_Z4testiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testiPd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4testiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void test (int input, double *num){
int idx = threadIdx.x;
num[idx] =input-num[idx]*num[idx];
}
void run (int input, double *ans, int digit, double timer){
if (digit <= 0) return;
double *r;
double *num = new double[100];
for (int i=0; i<100; i++){
num[i] = *ans + timer*i;
}
hipMalloc((void**) &r, 100*sizeof(double));
hipMemcpy(r, num, 100*sizeof(double), hipMemcpyHostToDevice);
test <<< 1,100 >>> (input,r);
hipMemcpy(num, r, 100*sizeof(double), hipMemcpyDeviceToHost);
hipFree(r);
for (int i=0; i<100; i++){
if (num[i] < 0){
*ans += timer*(i-1);
break;
}else if (i == 99) {
*ans += timer*99;
}
}
delete num;
run(input,ans,digit - 1,timer/100);
}
int find_timer(int input){
int ans = 1, i = 100;
while(input /= i) ans *= 100;
//printf("%d",ans);
return ans;
}
int main (void){
//char trash[100+5];
int digit,input;
//scanf("%s %s",&trash,&trash);
scanf("%d %d",&digit,&input);
int timer = find_timer(input);
double *ans = new double;
run(input, ans, digit, timer);
printf("%.10f\n",*ans);
delete ans;
return 0;
} | .text
.file "code.hip"
.globl _Z19__device_stub__testiPd # -- Begin function _Z19__device_stub__testiPd
.p2align 4, 0x90
.type _Z19__device_stub__testiPd,@function
_Z19__device_stub__testiPd: # @_Z19__device_stub__testiPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4testiPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__testiPd, .Lfunc_end0-_Z19__device_stub__testiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3runiPdid
.LCPI1_0:
.quad 0x4058c00000000000 # double 99
.LCPI1_1:
.quad 0x4059000000000000 # double 100
.text
.globl _Z3runiPdid
.p2align 4, 0x90
.type _Z3runiPdid,@function
_Z3runiPdid: # @_Z3runiPdid
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_12
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %r14
movl %edi, %ebp
movl $800, %edi # imm = 0x320
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq _Znam
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movq %rax, %r15
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rax,8)
incq %rax
cmpq $100, %rax
jne .LBB1_2
# %bb.3:
movq %rsp, %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq (%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 99(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq (%rsp), %rax
movl %ebp, 20(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4testiPd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rsi
movl $800, %edx # imm = 0x320
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 8(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
xorl %eax, %eax
xorpd %xmm1, %xmm1
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_6 Depth=1
incq %rax
cmpq $100, %rax
je .LBB1_11
.LBB1_6: # =>This Inner Loop Header: Depth=1
ucomisd (%r15,%rax,8), %xmm1
ja .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=1
cmpq $99, %rax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_6 Depth=1
movsd (%r14), %xmm2 # xmm2 = mem[0],zero
addsd %xmm0, %xmm2
movsd %xmm2, (%r14)
jmp .LBB1_10
.LBB1_7:
decl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd %xmm3, %xmm0
addsd (%r14), %xmm0
movsd %xmm0, (%r14)
.LBB1_11: # %.loopexit
movq %r15, %rdi
callq _ZdlPv
decl %ebx
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI1_1(%rip), %xmm0
movl %ebp, %edi
movq %r14, %rsi
movl %ebx, %edx
callq _Z3runiPdid
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_12:
retq
.Lfunc_end1:
.size _Z3runiPdid, .Lfunc_end1-_Z3runiPdid
.cfi_endproc
# -- End function
.globl _Z10find_timeri # -- Begin function _Z10find_timeri
.p2align 4, 0x90
.type _Z10find_timeri,@function
_Z10find_timeri: # @_Z10find_timeri
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal 99(%rdi), %ecx
movl $1, %eax
cmpl $199, %ecx
jb .LBB2_2
.p2align 4, 0x90
.LBB2_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %edi, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
leal (%rcx,%rdx), %edi
imull $100, %eax, %eax
addl %edx, %ecx
addl $99, %ecx
cmpl $198, %ecx
ja .LBB2_1
.LBB2_2: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10find_timeri, .Lfunc_end2-_Z10find_timeri
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 12(%rsp), %rsi
leaq 8(%rsp), %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebx
leal 99(%rbx), %eax
cmpl $199, %eax
jae .LBB3_2
# %bb.1:
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB3_5
.LBB3_2: # %.lr.ph.i.preheader
movl $1, %eax
movl %ebx, %ecx
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movslq %ecx, %rcx
imulq $1374389535, %rcx, %rdx # imm = 0x51EB851F
movq %rdx, %rsi
shrq $63, %rsi
sarq $37, %rdx
leal (%rdx,%rsi), %ecx
imull $100, %eax, %eax
addl %esi, %edx
addl $99, %edx
cmpl $198, %edx
ja .LBB3_3
# %bb.4: # %_Z10find_timeri.exit.loopexit
cvtsi2sd %eax, %xmm0
.LBB3_5: # %_Z10find_timeri.exit
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $8, %edi
callq _Znwm
movq %rax, %r14
movl 12(%rsp), %edx
movl %ebx, %edi
movq %rax, %rsi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _Z3runiPdid
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testiPd,@object # @_Z4testiPd
.section .rodata,"a",@progbits
.globl _Z4testiPd
.p2align 3, 0x0
_Z4testiPd:
.quad _Z19__device_stub__testiPd
.size _Z4testiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.10f\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testiPd"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x001fca00078e0205 */
/*0050*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ I2F.F64 R2, c[0x0][0x160] ; /* 0x0000580000027b12 */
/* 0x000ea40000201c00 */
/*0070*/ DFMA R2, -R6, R6, R2 ; /* 0x000000060602722b */
/* 0x004e0e0000000102 */
/*0080*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testiPd
.globl _Z4testiPd
.p2align 8
.type _Z4testiPd,@function
_Z4testiPd:
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 3, v0
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v4, s[2:3]
v_cvt_f64_i32_e32 v[2:3], s0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], -v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testiPd, .Lfunc_end0-_Z4testiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testiPd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4testiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010587d_00000000-6_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10find_timeri
.type _Z10find_timeri, @function
_Z10find_timeri:
.LFB2058:
.cfi_startproc
endbr64
movslq %edi, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
sarl $31, %edi
subl %edi, %edx
je .L6
movl $1, %ecx
.L5:
imull $100, %ecx, %ecx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, %edx
jne .L5
.L3:
movl %ecx, %eax
ret
.L6:
movl $1, %ecx
jmp .L3
.cfi_endproc
.LFE2058:
.size _Z10find_timeri, .-_Z10find_timeri
.globl _Z24__device_stub__Z4testiPdiPd
.type _Z24__device_stub__Z4testiPdiPd, @function
_Z24__device_stub__Z4testiPdiPd:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z4testiPdiPd, .-_Z24__device_stub__Z4testiPdiPd
.globl _Z4testiPd
.type _Z4testiPd, @function
_Z4testiPd:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4testiPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4testiPd, .-_Z4testiPd
.globl _Z3runiPdid
.type _Z3runiPdid, @function
_Z3runiPdid:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
testl %edx, %edx
jle .L16
movl %edi, %r13d
movq %rsi, %rbp
movl %edx, %r12d
movl $800, %edi
call _Znam@PLT
movq %rax, %rbx
movsd 0(%rbp), %xmm1
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L18
leaq 24(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $800, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L19:
movl $2, %ecx
movl $800, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
pxor %xmm0, %xmm0
jmp .L24
.L30:
movq 24(%rsp), %rsi
movl %r13d, %edi
call _Z24__device_stub__Z4testiPdiPd
jmp .L19
.L31:
subl $1, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
addsd 0(%rbp), %xmm0
jmp .L22
.L23:
addq $1, %rax
.L24:
comisd (%rbx,%rax,8), %xmm0
ja .L31
cmpq $99, %rax
jne .L23
movsd 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
addsd 0(%rbp), %xmm0
.L22:
movsd %xmm0, 0(%rbp)
movl $8, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movsd 8(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
leal -1(%r12), %edx
movq %rbp, %rsi
movl %r13d, %edi
call _Z3runiPdid
.L16:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z3runiPdid, .-_Z3runiPdid
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%d %d"
.LC4:
.string "%.10f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdx
movq %rsp, %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
movl 4(%rsp), %edi
call _Z10find_timeri
movl %eax, %ebp
movl $8, %edi
call _Znwm@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
movl (%rsp), %edx
movq %rax, %rsi
movl 4(%rsp), %edi
call _Z3runiPdid
movsd (%rbx), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $8, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z4testiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079558144
.align 8
.LC2:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "code.hip"
.globl _Z19__device_stub__testiPd # -- Begin function _Z19__device_stub__testiPd
.p2align 4, 0x90
.type _Z19__device_stub__testiPd,@function
_Z19__device_stub__testiPd: # @_Z19__device_stub__testiPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4testiPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__testiPd, .Lfunc_end0-_Z19__device_stub__testiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3runiPdid
.LCPI1_0:
.quad 0x4058c00000000000 # double 99
.LCPI1_1:
.quad 0x4059000000000000 # double 100
.text
.globl _Z3runiPdid
.p2align 4, 0x90
.type _Z3runiPdid,@function
_Z3runiPdid: # @_Z3runiPdid
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_12
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %r14
movl %edi, %ebp
movl $800, %edi # imm = 0x320
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq _Znam
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movq %rax, %r15
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rax,8)
incq %rax
cmpq $100, %rax
jne .LBB1_2
# %bb.3:
movq %rsp, %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq (%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 99(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq (%rsp), %rax
movl %ebp, 20(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4testiPd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rsi
movl $800, %edx # imm = 0x320
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 8(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
xorl %eax, %eax
xorpd %xmm1, %xmm1
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_6 Depth=1
incq %rax
cmpq $100, %rax
je .LBB1_11
.LBB1_6: # =>This Inner Loop Header: Depth=1
ucomisd (%r15,%rax,8), %xmm1
ja .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=1
cmpq $99, %rax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_6 Depth=1
movsd (%r14), %xmm2 # xmm2 = mem[0],zero
addsd %xmm0, %xmm2
movsd %xmm2, (%r14)
jmp .LBB1_10
.LBB1_7:
decl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd %xmm3, %xmm0
addsd (%r14), %xmm0
movsd %xmm0, (%r14)
.LBB1_11: # %.loopexit
movq %r15, %rdi
callq _ZdlPv
decl %ebx
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI1_1(%rip), %xmm0
movl %ebp, %edi
movq %r14, %rsi
movl %ebx, %edx
callq _Z3runiPdid
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_12:
retq
.Lfunc_end1:
.size _Z3runiPdid, .Lfunc_end1-_Z3runiPdid
.cfi_endproc
# -- End function
.globl _Z10find_timeri # -- Begin function _Z10find_timeri
.p2align 4, 0x90
.type _Z10find_timeri,@function
_Z10find_timeri: # @_Z10find_timeri
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal 99(%rdi), %ecx
movl $1, %eax
cmpl $199, %ecx
jb .LBB2_2
.p2align 4, 0x90
.LBB2_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %edi, %rcx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
leal (%rcx,%rdx), %edi
imull $100, %eax, %eax
addl %edx, %ecx
addl $99, %ecx
cmpl $198, %ecx
ja .LBB2_1
.LBB2_2: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10find_timeri, .Lfunc_end2-_Z10find_timeri
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 12(%rsp), %rsi
leaq 8(%rsp), %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebx
leal 99(%rbx), %eax
cmpl $199, %eax
jae .LBB3_2
# %bb.1:
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB3_5
.LBB3_2: # %.lr.ph.i.preheader
movl $1, %eax
movl %ebx, %ecx
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movslq %ecx, %rcx
imulq $1374389535, %rcx, %rdx # imm = 0x51EB851F
movq %rdx, %rsi
shrq $63, %rsi
sarq $37, %rdx
leal (%rdx,%rsi), %ecx
imull $100, %eax, %eax
addl %esi, %edx
addl $99, %edx
cmpl $198, %edx
ja .LBB3_3
# %bb.4: # %_Z10find_timeri.exit.loopexit
cvtsi2sd %eax, %xmm0
.LBB3_5: # %_Z10find_timeri.exit
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $8, %edi
callq _Znwm
movq %rax, %r14
movl 12(%rsp), %edx
movl %ebx, %edi
movq %rax, %rsi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _Z3runiPdid
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %r14, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testiPd,@object # @_Z4testiPd
.section .rodata,"a",@progbits
.globl _Z4testiPd
.p2align 3, 0x0
_Z4testiPd:
.quad _Z19__device_stub__testiPd
.size _Z4testiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.10f\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testiPd"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void init_check(int *d_check, int nz)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= nz) {
return;
}
d_check[i] = -1;
} | code for sm_80
Function : _Z10init_checkPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0xffffffff ; /* 0xffffffff00057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void init_check(int *d_check, int nz)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= nz) {
return;
}
d_check[i] = -1;
} | .file "tmpxft_000d230a_00000000-6_init_check.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z10init_checkPiiPii
.type _Z31__device_stub__Z10init_checkPiiPii, @function
_Z31__device_stub__Z10init_checkPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_checkPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z10init_checkPiiPii, .-_Z31__device_stub__Z10init_checkPiiPii
.globl _Z10init_checkPii
.type _Z10init_checkPii, @function
_Z10init_checkPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10init_checkPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10init_checkPii, .-_Z10init_checkPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10init_checkPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_checkPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void init_check(int *d_check, int nz)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= nz) {
return;
}
d_check[i] = -1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_check(int *d_check, int nz)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= nz) {
return;
}
d_check[i] = -1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_check(int *d_check, int nz)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= nz) {
return;
}
d_check[i] = -1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10init_checkPii
.globl _Z10init_checkPii
.p2align 8
.type _Z10init_checkPii,@function
_Z10init_checkPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, -1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10init_checkPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10init_checkPii, .Lfunc_end0-_Z10init_checkPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10init_checkPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10init_checkPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_check(int *d_check, int nz)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= nz) {
return;
}
d_check[i] = -1;
} | .text
.file "init_check.hip"
.globl _Z25__device_stub__init_checkPii # -- Begin function _Z25__device_stub__init_checkPii
.p2align 4, 0x90
.type _Z25__device_stub__init_checkPii,@function
_Z25__device_stub__init_checkPii: # @_Z25__device_stub__init_checkPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10init_checkPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__init_checkPii, .Lfunc_end0-_Z25__device_stub__init_checkPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_checkPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10init_checkPii,@object # @_Z10init_checkPii
.section .rodata,"a",@progbits
.globl _Z10init_checkPii
.p2align 3, 0x0
_Z10init_checkPii:
.quad _Z25__device_stub__init_checkPii
.size _Z10init_checkPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10init_checkPii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__init_checkPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10init_checkPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10init_checkPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0xffffffff ; /* 0xffffffff00057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10init_checkPii
.globl _Z10init_checkPii
.p2align 8
.type _Z10init_checkPii,@function
_Z10init_checkPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, -1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10init_checkPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10init_checkPii, .Lfunc_end0-_Z10init_checkPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10init_checkPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10init_checkPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d230a_00000000-6_init_check.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z10init_checkPiiPii
.type _Z31__device_stub__Z10init_checkPiiPii, @function
_Z31__device_stub__Z10init_checkPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_checkPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z10init_checkPiiPii, .-_Z31__device_stub__Z10init_checkPiiPii
.globl _Z10init_checkPii
.type _Z10init_checkPii, @function
_Z10init_checkPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10init_checkPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10init_checkPii, .-_Z10init_checkPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10init_checkPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_checkPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init_check.hip"
.globl _Z25__device_stub__init_checkPii # -- Begin function _Z25__device_stub__init_checkPii
.p2align 4, 0x90
.type _Z25__device_stub__init_checkPii,@function
_Z25__device_stub__init_checkPii: # @_Z25__device_stub__init_checkPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10init_checkPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__init_checkPii, .Lfunc_end0-_Z25__device_stub__init_checkPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_checkPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10init_checkPii,@object # @_Z10init_checkPii
.section .rodata,"a",@progbits
.globl _Z10init_checkPii
.p2align 3, 0x0
_Z10init_checkPii:
.quad _Z25__device_stub__init_checkPii
.size _Z10init_checkPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10init_checkPii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__init_checkPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10init_checkPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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