system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
const int INF = (1 << 30) - 1;
int vertex_num, edge_num, matrix_size;
int *dist;
double cal_time(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec - start.tv_nsec) < 0)
{
temp.tv_sec = end.tv_sec - start.tv_sec - 1;
temp.tv_nsec = 1000000000 + end.tv_nsec - start.tv_nsec;
}
else
{
temp.tv_sec = end.tv_sec - start.tv_sec;
temp.tv_nsec = end.tv_nsec - start.tv_nsec;
}
return temp.tv_sec + (double)temp.tv_nsec / 1000000000.0;
}
__device__ __host__ size_t index_convert(int i, int j, int row_size)
{
return i * row_size + j;
}
void input(char *input_file_path, int &block_factor)
{
FILE *input_file = fopen(input_file_path, "rb");
fread(&vertex_num, sizeof(int), 1, input_file);
fread(&edge_num, sizeof(int), 1, input_file);
matrix_size = ceil((double)vertex_num / (double)block_factor) * block_factor;
cudaMallocHost((void **)&dist, matrix_size * matrix_size * sizeof(int));
for (int i = 0; i < matrix_size; ++i)
{
for (int j = 0; j < matrix_size; ++j)
{
if (i != j)
dist[index_convert(i, j, matrix_size)] = INF;
else if (i < vertex_num)
dist[index_convert(i, j, matrix_size)] = 0;
else
dist[index_convert(i, j, matrix_size)] = INF;
}
}
int data[3];
for (int i = 0; i < edge_num; ++i)
{
fread(data, sizeof(int), 3, input_file);
dist[index_convert(data[0], data[1], matrix_size)] = data[2];
}
fclose(input_file);
}
void output(char *output_file_path)
{
FILE *output_file = fopen(output_file_path, "w");
for (int i = 0; i < vertex_num; ++i)
{
fwrite(&dist[index_convert(i, 0, matrix_size)], sizeof(int), vertex_num, output_file);
}
fclose(output_file);
}
__constant__ int size[3]; //matrix size, block_factor, grid_size
__global__ void phase1(int *d_dist, int round)
{
__shared__ int share[4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * round;
int j_offset = size[1] * round;
share[index_convert(j, i, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(j, i, size[1])] > share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])])
share[index_convert(j, i, size[1])] = share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(j, i, size[1])];
}
__global__ void phase2(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset, j_offset;
if (blockIdx.x == 0)
{
i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
j_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = share[index_convert(i, j, size[1])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(j_offset + i, j_offset + j, size[0])];
}
else
{
i_offset = size[1] * round;
j_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, i_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = share[index_convert(i, j, size[1])];
}
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
__global__ void phase3(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
int j_offset = size[1] * ((round + blockIdx.x + 1) % size[2]);
int r_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, r_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(r_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
int main(int argc, char **argv)
{
double total_time, bfd_time;
timespec total_time1, total_time2, bfd_time1, bfd_time2;
clock_gettime(CLOCK_MONOTONIC, &total_time1);
cudaSetDevice(0);
int block_factor = 32;
if (argc == 4)
block_factor = atoi(argv[3]);
input(argv[1], block_factor);
int grid_size = matrix_size / block_factor;
int size_info[3] = {matrix_size, block_factor, grid_size};
cudaMemcpyToSymbol(size, size_info, 3 * sizeof(int));
int *d_dist;
clock_gettime(CLOCK_MONOTONIC, &bfd_time1);
cudaMalloc(&d_dist, (size_t)sizeof(int) * matrix_size * matrix_size);
cudaMemcpy(d_dist, dist, (size_t)sizeof(int) * matrix_size * matrix_size, cudaMemcpyHostToDevice);
dim3 block(block_factor, block_factor);
dim3 grid2(2, grid_size - 1);
dim3 grid3(grid_size - 1, grid_size - 1);
for (int r = 0; r < grid_size; ++r)
{
phase1<<<1, block>>>(d_dist, r);
phase2<<<grid2, block>>>(d_dist, r);
phase3<<<grid3, block>>>(d_dist, r);
}
cudaMemcpy(dist, d_dist, (size_t)sizeof(int) * matrix_size * matrix_size, cudaMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &bfd_time2);
output(argv[2]);
cudaFree(d_dist);
cudaFree(dist);
clock_gettime(CLOCK_MONOTONIC, &total_time2);
bfd_time = cal_time(bfd_time1, bfd_time2);
total_time = cal_time(total_time1, total_time2);
printf(" vertex: %d\n", vertex_num);
printf(" I/O time: %.5f\n", total_time - bfd_time);
printf(" cal time: %.5f\n", bfd_time);
printf(" runtime: %.5f\n", total_time);
return 0;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
const int INF = (1 << 30) - 1;
int vertex_num, edge_num, matrix_size;
int *dist;
double cal_time(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec - start.tv_nsec) < 0)
{
temp.tv_sec = end.tv_sec - start.tv_sec - 1;
temp.tv_nsec = 1000000000 + end.tv_nsec - start.tv_nsec;
}
else
{
temp.tv_sec = end.tv_sec - start.tv_sec;
temp.tv_nsec = end.tv_nsec - start.tv_nsec;
}
return temp.tv_sec + (double)temp.tv_nsec / 1000000000.0;
}
__device__ __host__ size_t index_convert(int i, int j, int row_size)
{
return i * row_size + j;
}
void input(char *input_file_path, int &block_factor)
{
FILE *input_file = fopen(input_file_path, "rb");
fread(&vertex_num, sizeof(int), 1, input_file);
fread(&edge_num, sizeof(int), 1, input_file);
matrix_size = ceil((double)vertex_num / (double)block_factor) * block_factor;
hipHostMalloc((void **)&dist, matrix_size * matrix_size * sizeof(int), hipHostMallocDefault);
for (int i = 0; i < matrix_size; ++i)
{
for (int j = 0; j < matrix_size; ++j)
{
if (i != j)
dist[index_convert(i, j, matrix_size)] = INF;
else if (i < vertex_num)
dist[index_convert(i, j, matrix_size)] = 0;
else
dist[index_convert(i, j, matrix_size)] = INF;
}
}
int data[3];
for (int i = 0; i < edge_num; ++i)
{
fread(data, sizeof(int), 3, input_file);
dist[index_convert(data[0], data[1], matrix_size)] = data[2];
}
fclose(input_file);
}
void output(char *output_file_path)
{
FILE *output_file = fopen(output_file_path, "w");
for (int i = 0; i < vertex_num; ++i)
{
fwrite(&dist[index_convert(i, 0, matrix_size)], sizeof(int), vertex_num, output_file);
}
fclose(output_file);
}
__constant__ int size[3]; //matrix size, block_factor, grid_size
__global__ void phase1(int *d_dist, int round)
{
__shared__ int share[4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * round;
int j_offset = size[1] * round;
share[index_convert(j, i, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(j, i, size[1])] > share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])])
share[index_convert(j, i, size[1])] = share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(j, i, size[1])];
}
__global__ void phase2(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset, j_offset;
if (blockIdx.x == 0)
{
i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
j_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = share[index_convert(i, j, size[1])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(j_offset + i, j_offset + j, size[0])];
}
else
{
i_offset = size[1] * round;
j_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, i_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = share[index_convert(i, j, size[1])];
}
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
__global__ void phase3(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
int j_offset = size[1] * ((round + blockIdx.x + 1) % size[2]);
int r_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, r_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(r_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
int main(int argc, char **argv)
{
double total_time, bfd_time;
timespec total_time1, total_time2, bfd_time1, bfd_time2;
clock_gettime(CLOCK_MONOTONIC, &total_time1);
hipSetDevice(0);
int block_factor = 32;
if (argc == 4)
block_factor = atoi(argv[3]);
input(argv[1], block_factor);
int grid_size = matrix_size / block_factor;
int size_info[3] = {matrix_size, block_factor, grid_size};
hipMemcpyToSymbol(HIP_SYMBOL(size), size_info, 3 * sizeof(int));
int *d_dist;
clock_gettime(CLOCK_MONOTONIC, &bfd_time1);
hipMalloc(&d_dist, (size_t)sizeof(int) * matrix_size * matrix_size);
hipMemcpy(d_dist, dist, (size_t)sizeof(int) * matrix_size * matrix_size, hipMemcpyHostToDevice);
dim3 block(block_factor, block_factor);
dim3 grid2(2, grid_size - 1);
dim3 grid3(grid_size - 1, grid_size - 1);
for (int r = 0; r < grid_size; ++r)
{
phase1<<<1, block>>>(d_dist, r);
phase2<<<grid2, block>>>(d_dist, r);
phase3<<<grid3, block>>>(d_dist, r);
}
hipMemcpy(dist, d_dist, (size_t)sizeof(int) * matrix_size * matrix_size, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &bfd_time2);
output(argv[2]);
hipFree(d_dist);
hipFree(dist);
clock_gettime(CLOCK_MONOTONIC, &total_time2);
bfd_time = cal_time(bfd_time1, bfd_time2);
total_time = cal_time(total_time1, total_time2);
printf(" vertex: %d\n", vertex_num);
printf(" I/O time: %.5f\n", total_time - bfd_time);
printf(" cal time: %.5f\n", bfd_time);
printf(" runtime: %.5f\n", total_time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
const int INF = (1 << 30) - 1;
int vertex_num, edge_num, matrix_size;
int *dist;
double cal_time(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec - start.tv_nsec) < 0)
{
temp.tv_sec = end.tv_sec - start.tv_sec - 1;
temp.tv_nsec = 1000000000 + end.tv_nsec - start.tv_nsec;
}
else
{
temp.tv_sec = end.tv_sec - start.tv_sec;
temp.tv_nsec = end.tv_nsec - start.tv_nsec;
}
return temp.tv_sec + (double)temp.tv_nsec / 1000000000.0;
}
__device__ __host__ size_t index_convert(int i, int j, int row_size)
{
return i * row_size + j;
}
void input(char *input_file_path, int &block_factor)
{
FILE *input_file = fopen(input_file_path, "rb");
fread(&vertex_num, sizeof(int), 1, input_file);
fread(&edge_num, sizeof(int), 1, input_file);
matrix_size = ceil((double)vertex_num / (double)block_factor) * block_factor;
hipHostMalloc((void **)&dist, matrix_size * matrix_size * sizeof(int), hipHostMallocDefault);
for (int i = 0; i < matrix_size; ++i)
{
for (int j = 0; j < matrix_size; ++j)
{
if (i != j)
dist[index_convert(i, j, matrix_size)] = INF;
else if (i < vertex_num)
dist[index_convert(i, j, matrix_size)] = 0;
else
dist[index_convert(i, j, matrix_size)] = INF;
}
}
int data[3];
for (int i = 0; i < edge_num; ++i)
{
fread(data, sizeof(int), 3, input_file);
dist[index_convert(data[0], data[1], matrix_size)] = data[2];
}
fclose(input_file);
}
void output(char *output_file_path)
{
FILE *output_file = fopen(output_file_path, "w");
for (int i = 0; i < vertex_num; ++i)
{
fwrite(&dist[index_convert(i, 0, matrix_size)], sizeof(int), vertex_num, output_file);
}
fclose(output_file);
}
__constant__ int size[3]; //matrix size, block_factor, grid_size
__global__ void phase1(int *d_dist, int round)
{
__shared__ int share[4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * round;
int j_offset = size[1] * round;
share[index_convert(j, i, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(j, i, size[1])] > share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])])
share[index_convert(j, i, size[1])] = share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(j, i, size[1])];
}
__global__ void phase2(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset, j_offset;
if (blockIdx.x == 0)
{
i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
j_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = share[index_convert(i, j, size[1])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(j_offset + i, j_offset + j, size[0])];
}
else
{
i_offset = size[1] * round;
j_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, i_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = share[index_convert(i, j, size[1])];
}
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
__global__ void phase3(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
int j_offset = size[1] * ((round + blockIdx.x + 1) % size[2]);
int r_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, r_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(r_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
int main(int argc, char **argv)
{
double total_time, bfd_time;
timespec total_time1, total_time2, bfd_time1, bfd_time2;
clock_gettime(CLOCK_MONOTONIC, &total_time1);
hipSetDevice(0);
int block_factor = 32;
if (argc == 4)
block_factor = atoi(argv[3]);
input(argv[1], block_factor);
int grid_size = matrix_size / block_factor;
int size_info[3] = {matrix_size, block_factor, grid_size};
hipMemcpyToSymbol(HIP_SYMBOL(size), size_info, 3 * sizeof(int));
int *d_dist;
clock_gettime(CLOCK_MONOTONIC, &bfd_time1);
hipMalloc(&d_dist, (size_t)sizeof(int) * matrix_size * matrix_size);
hipMemcpy(d_dist, dist, (size_t)sizeof(int) * matrix_size * matrix_size, hipMemcpyHostToDevice);
dim3 block(block_factor, block_factor);
dim3 grid2(2, grid_size - 1);
dim3 grid3(grid_size - 1, grid_size - 1);
for (int r = 0; r < grid_size; ++r)
{
phase1<<<1, block>>>(d_dist, r);
phase2<<<grid2, block>>>(d_dist, r);
phase3<<<grid3, block>>>(d_dist, r);
}
hipMemcpy(dist, d_dist, (size_t)sizeof(int) * matrix_size * matrix_size, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &bfd_time2);
output(argv[2]);
hipFree(d_dist);
hipFree(dist);
clock_gettime(CLOCK_MONOTONIC, &total_time2);
bfd_time = cal_time(bfd_time1, bfd_time2);
total_time = cal_time(total_time1, total_time2);
printf(" vertex: %d\n", vertex_num);
printf(" I/O time: %.5f\n", total_time - bfd_time);
printf(" cal time: %.5f\n", bfd_time);
printf(" runtime: %.5f\n", total_time);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6phase1Pii
.globl _Z6phase1Pii
.p2align 8
.type _Z6phase1Pii,@function
_Z6phase1Pii:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size@rel32@lo+8
s_addc_u32 s3, s3, size@rel32@hi+16
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, size@rel32@lo+4
s_addc_u32 s5, s5, size@rel32@hi+12
s_load_b32 s6, s[0:1], 0x8
s_clause 0x1
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[4:5], 0x0
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v2
v_add_nc_u32_e32 v1, s4, v4
s_cmp_lt_i32 s2, 1
v_mul_lo_u32 v1, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add3_u32 v0, s4, v2, v1
v_add_lshl_u32 v2, v3, v4, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v2, v5
s_cbranch_scc1 .LBB0_5
v_lshlrev_b32_e32 v3, 2, v3
v_lshlrev_b32_e32 v4, 2, v4
s_lshl_b32 s0, s2, 2
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v3, 4, v3
v_add_nc_u32_e32 v4, s0, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v3
ds_load_b32 v6, v4
ds_load_b32 v7, v2
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v6, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB0_2
ds_store_b32 v2, v5
s_branch .LBB0_2
.LBB0_5:
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6phase1Pii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6phase1Pii, .Lfunc_end0-_Z6phase1Pii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6phase2Pii
.globl _Z6phase2Pii
.p2align 8
.type _Z6phase2Pii,@function
_Z6phase2Pii:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size@rel32@lo+8
s_addc_u32 s3, s3, size@rel32@hi+16
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s4, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x8
v_and_b32_e32 v0, 0x3ff, v0
s_cmp_lg_u32 s14, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, s4, v1
v_add_nc_u32_e32 v3, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_lshl_u32 v2, v2, v0, 2
s_cbranch_scc0 .LBB1_9
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, size@rel32@lo+12
s_addc_u32 s1, s1, size@rel32@hi+20
s_load_b32 s7, s[0:1], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, size@rel32@lo+4
s_addc_u32 s1, s1, size@rel32@hi+12
s_add_i32 s9, s15, s5
s_load_b32 s1, s[0:1], 0x0
s_add_i32 s9, s9, 1
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v4, s7
s_sub_i32 s8, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v4
s_mul_i32 s8, s8, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s0, s8
s_add_i32 s0, s0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s0, s9, s0
s_mul_i32 s8, s0, s7
s_mul_i32 s0, s4, s5
s_sub_i32 s8, s9, s8
v_add_nc_u32_e32 v6, s0, v1
s_sub_i32 s9, s8, s7
s_cmp_ge_u32 s8, s7
s_cselect_b32 s8, s9, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s1, v6, v[0:1]
s_sub_i32 s1, s8, s7
s_cmp_ge_u32 s8, s7
s_cselect_b32 s1, s1, s8
s_mul_i32 s1, s1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s0, v4
v_add_nc_u32_e32 v5, s1, v4
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[7:8]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
v_mul_lo_u32 v6, v3, s4
v_add_lshl_u32 v6, v6, v0, 2
s_waitcnt vmcnt(1)
ds_store_b32 v2, v4
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
ds_load_b32 v4, v2
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB1_3
.LBB1_2:
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, size@rel32@lo+12
s_addc_u32 s1, s1, size@rel32@hi+20
v_mul_lo_u32 v3, v3, s4
s_load_b32 s6, s[0:1], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, size@rel32@lo+4
s_addc_u32 s1, s1, size@rel32@hi+12
s_add_i32 s8, s15, s5
s_load_b32 s7, s[0:1], 0x0
s_add_i32 s8, s8, 1
v_add_lshl_u32 v3, v3, v0, 2
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v4, s6
s_sub_i32 s1, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v4
s_mul_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s0, s1
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s0, s8, s0
s_mul_i32 s0, s0, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s0, s8, s0
s_sub_i32 s1, s0, s6
s_cmp_ge_u32 s0, s6
s_cselect_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s1, s0, s6
s_cmp_ge_u32 s0, s6
s_cselect_b32 s0, s1, s0
s_mul_i32 s1, s4, s5
s_mul_i32 s0, s0, s4
v_add_nc_u32_e32 v4, s1, v0
v_add_nc_u32_e32 v7, s0, v1
v_add_nc_u32_e32 v9, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, s7, v[4:5]
v_mad_u64_u32 v[7:8], null, s7, v9, v[4:5]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_lshlrev_b64 v[6:7], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v5, v[4:5], off
global_load_b32 v4, v[6:7], off
s_waitcnt vmcnt(1)
ds_store_b32 v2, v5
ds_store_b32 v3, v5
.LBB1_3:
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, size@rel32@lo+8
s_addc_u32 s7, s7, size@rel32@hi+16
v_lshl_add_u32 v2, s4, 1, v1
s_load_b32 s5, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s4
v_add_lshl_u32 v3, v3, v0, 2
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b32 v3, v4
v_mul_lo_u32 v2, s5, v1
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB1_8
v_add_nc_u32_e32 v3, s5, v1
v_lshlrev_b32_e32 v4, 2, v0
s_mul_i32 s4, s5, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v5, s5, v3
v_add_lshl_u32 v3, v2, v0, 2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v4, s4, 3, v4
s_lshl_b32 s4, s5, 2
v_lshlrev_b32_e32 v5, 2, v5
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v4, s4, v4
v_add_nc_u32_e32 v5, 4, v5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB1_8
.LBB1_6:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v6, v5
ds_load_b32 v7, v4
ds_load_b32 v8, v3
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v6, v7, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v8, v6
s_cbranch_execz .LBB1_5
ds_store_b32 v3, v6
s_branch .LBB1_5
.LBB1_8:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, size@rel32@lo+4
s_addc_u32 s5, s5, size@rel32@hi+12
v_add_nc_u32_e32 v1, s0, v1
s_load_b32 s4, s[4:5], 0x0
v_add_lshl_u32 v2, v2, v0, 2
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s1, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB1_9:
s_branch .LBB1_2
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6phase2Pii
.amdhsa_group_segment_fixed_size 49152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6phase2Pii, .Lfunc_end1-_Z6phase2Pii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6phase3Pii
.globl _Z6phase3Pii
.p2align 8
.type _Z6phase3Pii,@function
_Z6phase3Pii:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size@rel32@lo+12
s_addc_u32 s3, s3, size@rel32@hi+20
s_load_b32 s6, s[0:1], 0x8
s_load_b32 s4, s[2:3], 0x0
v_bfe_u32 v3, v0, 10, 10
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size@rel32@lo+4
s_addc_u32 s3, s3, size@rel32@hi+12
v_and_b32_e32 v0, 0x3ff, v0
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s8, 0, s4
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size@rel32@lo+8
s_addc_u32 s3, s3, size@rel32@hi+16
s_add_i32 s9, s6, 1
s_load_b32 s2, s[2:3], 0x0
v_rcp_iflag_f32_e32 v1, v1
s_add_i32 s10, s9, s15
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s8, s7
s_mul_hi_u32 s8, s7, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s8
s_mul_hi_u32 s3, s10, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s4
s_sub_i32 s3, s10, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s3, s4
s_cmp_ge_u32 s3, s4
s_cselect_b32 s3, s8, s3
s_sub_i32 s8, s3, s4
s_cmp_ge_u32 s3, s4
s_cselect_b32 s3, s8, s3
s_add_i32 s9, s9, s14
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s3, s2, v[3:4]
s_mul_hi_u32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s4
s_sub_i32 s3, s9, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s7, s3, s4
s_cmp_ge_u32 s3, s4
v_mul_lo_u32 v6, s5, v1
s_cselect_b32 s3, s7, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s3, s4
s_cmp_ge_u32 s3, s4
s_mul_i32 s4, s2, s6
s_cselect_b32 s3, s7, s3
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1]
v_add_nc_u32_e32 v2, s4, v3
v_add3_u32 v4, s4, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v6, v6, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, s5, v2, v[1:2]
v_lshlrev_b64 v[1:2], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v1, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
s_clause 0x2
global_load_b32 v8, v[1:2], off
global_load_b32 v6, v[6:7], off
global_load_b32 v5, v[4:5], off
v_add_nc_u32_e32 v4, s2, v3
v_lshl_add_u32 v7, s2, 1, v3
v_mul_lo_u32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v4, v4, s2
v_mul_lo_u32 v7, v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_lshl_u32 v3, v3, v0, 2
v_add_lshl_u32 v9, v4, v0, 2
s_delay_alu instid0(VALU_DEP_3)
v_add_lshl_u32 v7, v7, v0, 2
s_waitcnt vmcnt(2)
ds_store_b32 v3, v8
s_waitcnt vmcnt(1)
ds_store_b32 v9, v6
s_waitcnt vmcnt(0)
ds_store_b32 v7, v5
s_cbranch_scc1 .LBB2_5
v_lshlrev_b32_e32 v0, 2, v0
s_mul_i32 s0, s2, s2
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v0, s0, 3, v0
s_lshl_b32 s0, s2, 2
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, s0, v0
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB2_5
.LBB2_3:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v4
ds_load_b32 v6, v0
ds_load_b32 v7, v3
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v6, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB2_2
ds_store_b32 v3, v5
s_branch .LBB2_2
.LBB2_5:
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6phase3Pii
.amdhsa_group_segment_fixed_size 49152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6phase3Pii, .Lfunc_end2-_Z6phase3Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected size
.type size,@object
.section .bss,"aw",@nobits
.globl size
.p2align 2, 0x0
size:
.zero 12
.size size, 12
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym size
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6phase1Pii
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z6phase1Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 49152
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6phase2Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6phase2Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 49152
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6phase3Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6phase3Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
const int INF = (1 << 30) - 1;
int vertex_num, edge_num, matrix_size;
int *dist;
double cal_time(struct timespec start, struct timespec end)
{
struct timespec temp;
if ((end.tv_nsec - start.tv_nsec) < 0)
{
temp.tv_sec = end.tv_sec - start.tv_sec - 1;
temp.tv_nsec = 1000000000 + end.tv_nsec - start.tv_nsec;
}
else
{
temp.tv_sec = end.tv_sec - start.tv_sec;
temp.tv_nsec = end.tv_nsec - start.tv_nsec;
}
return temp.tv_sec + (double)temp.tv_nsec / 1000000000.0;
}
__device__ __host__ size_t index_convert(int i, int j, int row_size)
{
return i * row_size + j;
}
void input(char *input_file_path, int &block_factor)
{
FILE *input_file = fopen(input_file_path, "rb");
fread(&vertex_num, sizeof(int), 1, input_file);
fread(&edge_num, sizeof(int), 1, input_file);
matrix_size = ceil((double)vertex_num / (double)block_factor) * block_factor;
hipHostMalloc((void **)&dist, matrix_size * matrix_size * sizeof(int), hipHostMallocDefault);
for (int i = 0; i < matrix_size; ++i)
{
for (int j = 0; j < matrix_size; ++j)
{
if (i != j)
dist[index_convert(i, j, matrix_size)] = INF;
else if (i < vertex_num)
dist[index_convert(i, j, matrix_size)] = 0;
else
dist[index_convert(i, j, matrix_size)] = INF;
}
}
int data[3];
for (int i = 0; i < edge_num; ++i)
{
fread(data, sizeof(int), 3, input_file);
dist[index_convert(data[0], data[1], matrix_size)] = data[2];
}
fclose(input_file);
}
void output(char *output_file_path)
{
FILE *output_file = fopen(output_file_path, "w");
for (int i = 0; i < vertex_num; ++i)
{
fwrite(&dist[index_convert(i, 0, matrix_size)], sizeof(int), vertex_num, output_file);
}
fclose(output_file);
}
__constant__ int size[3]; //matrix size, block_factor, grid_size
__global__ void phase1(int *d_dist, int round)
{
__shared__ int share[4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * round;
int j_offset = size[1] * round;
share[index_convert(j, i, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(j, i, size[1])] > share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])])
share[index_convert(j, i, size[1])] = share[index_convert(j, k, size[1])] + share[index_convert(k, i, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(j, i, size[1])];
}
__global__ void phase2(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset, j_offset;
if (blockIdx.x == 0)
{
i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
j_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = share[index_convert(i, j, size[1])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(j_offset + i, j_offset + j, size[0])];
}
else
{
i_offset = size[1] * round;
j_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, i_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = share[index_convert(i, j, size[1])];
}
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
__global__ void phase3(int *d_dist, int round)
{
__shared__ int share[3 * 4 * 1024];
int i = threadIdx.y;
int j = threadIdx.x;
int i_offset = size[1] * ((round + blockIdx.y + 1) % size[2]);
int j_offset = size[1] * ((round + blockIdx.x + 1) % size[2]);
int r_offset = size[1] * round;
share[index_convert(i, j, size[1])] = d_dist[index_convert(i_offset + i, j_offset + j, size[0])];
share[index_convert(i + size[1], j, size[1])] = d_dist[index_convert(i_offset + i, r_offset + j, size[0])];
share[index_convert(i + 2 * size[1], j, size[1])] = d_dist[index_convert(r_offset + i, j_offset + j, size[0])];
#pragma unroll 32
for (int k = 0; k < size[1]; ++k)
{
__syncthreads();
if (share[index_convert(i, j, size[1])] >
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])])
share[index_convert(i, j, size[1])] =
share[index_convert(i + size[1], k, size[1])] + share[index_convert(k + 2 * size[1], j, size[1])];
}
d_dist[index_convert(i_offset + i, j_offset + j, size[0])] = share[index_convert(i, j, size[1])];
}
int main(int argc, char **argv)
{
double total_time, bfd_time;
timespec total_time1, total_time2, bfd_time1, bfd_time2;
clock_gettime(CLOCK_MONOTONIC, &total_time1);
hipSetDevice(0);
int block_factor = 32;
if (argc == 4)
block_factor = atoi(argv[3]);
input(argv[1], block_factor);
int grid_size = matrix_size / block_factor;
int size_info[3] = {matrix_size, block_factor, grid_size};
hipMemcpyToSymbol(HIP_SYMBOL(size), size_info, 3 * sizeof(int));
int *d_dist;
clock_gettime(CLOCK_MONOTONIC, &bfd_time1);
hipMalloc(&d_dist, (size_t)sizeof(int) * matrix_size * matrix_size);
hipMemcpy(d_dist, dist, (size_t)sizeof(int) * matrix_size * matrix_size, hipMemcpyHostToDevice);
dim3 block(block_factor, block_factor);
dim3 grid2(2, grid_size - 1);
dim3 grid3(grid_size - 1, grid_size - 1);
for (int r = 0; r < grid_size; ++r)
{
phase1<<<1, block>>>(d_dist, r);
phase2<<<grid2, block>>>(d_dist, r);
phase3<<<grid3, block>>>(d_dist, r);
}
hipMemcpy(dist, d_dist, (size_t)sizeof(int) * matrix_size * matrix_size, hipMemcpyDeviceToHost);
clock_gettime(CLOCK_MONOTONIC, &bfd_time2);
output(argv[2]);
hipFree(d_dist);
hipFree(dist);
clock_gettime(CLOCK_MONOTONIC, &total_time2);
bfd_time = cal_time(bfd_time1, bfd_time2);
total_time = cal_time(total_time1, total_time2);
printf(" vertex: %d\n", vertex_num);
printf(" I/O time: %.5f\n", total_time - bfd_time);
printf(" cal time: %.5f\n", bfd_time);
printf(" runtime: %.5f\n", total_time);
return 0;
} | .text
.file "hw4-1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8cal_time8timespecS_
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z8cal_time8timespecS_
.p2align 4, 0x90
.type _Z8cal_time8timespecS_,@function
_Z8cal_time8timespecS_: # @_Z8cal_time8timespecS_
.cfi_startproc
# %bb.0:
movq %rcx, %rax
subq %rsi, %rax
js .LBB0_1
# %bb.2:
subq %rdi, %rdx
movq %rdx, %rdi
jmp .LBB0_3
.LBB0_1:
notq %rdi
addq %rdx, %rdi
subq %rsi, %rcx
addq $1000000000, %rcx # imm = 0x3B9ACA00
movq %rcx, %rax
.LBB0_3:
cvtsi2sd %rdi, %xmm1
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z8cal_time8timespecS_, .Lfunc_end0-_Z8cal_time8timespecS_
.cfi_endproc
# -- End function
.globl _Z13index_convertiii # -- Begin function _Z13index_convertiii
.p2align 4, 0x90
.type _Z13index_convertiii,@function
_Z13index_convertiii: # @_Z13index_convertiii
.cfi_startproc
# %bb.0:
imull %edx, %edi
addl %esi, %edi
movslq %edi, %rax
retq
.Lfunc_end1:
.size _Z13index_convertiii, .Lfunc_end1-_Z13index_convertiii
.cfi_endproc
# -- End function
.globl _Z5inputPcRi # -- Begin function _Z5inputPcRi
.p2align 4, 0x90
.type _Z5inputPcRi,@function
_Z5inputPcRi: # @_Z5inputPcRi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $vertex_num, %edi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movl $edge_num, %edi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cvtsi2sdl vertex_num(%rip), %xmm0
cvtsi2sdl (%r14), %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
divsd %xmm1, %xmm0
callq ceil@PLT
mulsd 24(%rsp), %xmm0 # 8-byte Folded Reload
cvttsd2si %xmm0, %esi
movl %esi, matrix_size(%rip)
imull %esi, %esi
shlq $2, %rsi
xorl %ebp, %ebp
movl $dist, %edi
xorl %edx, %edx
callq hipHostMalloc
cmpl $0, matrix_size(%rip)
jg .LBB2_1
.LBB2_5: # %._crit_edge26
cmpl $0, edge_num(%rip)
jle .LBB2_8
# %bb.6: # %.lr.ph29
xorl %ebp, %ebp
leaq 12(%rsp), %r14
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movl $3, %edx
movq %r14, %rdi
movq %rbx, %rcx
callq fread
movl 20(%rsp), %eax
movq dist(%rip), %rcx
movslq 12(%rsp), %rdx
movslq 16(%rsp), %rsi
movslq matrix_size(%rip), %rdi
imulq %rdx, %rdi
addq %rsi, %rdi
movl %eax, (%rcx,%rdi,4)
incl %ebp
cmpl edge_num(%rip), %ebp
jl .LBB2_7
.LBB2_8: # %._crit_edge30
movq %rbx, %rdi
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.p2align 4, 0x90
.LBB2_12: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
.cfi_def_cfa_offset 64
incl %ebp
cmpl matrix_size(%rip), %ebp
jge .LBB2_5
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl matrix_size(%rip), %edx
testl %edx, %edx
jle .LBB2_12
# %bb.2: # %.lr.ph
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
movq dist(%rip), %rcx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_3 Depth=2
movl $1073741823, (%rcx,%rdx,4) # imm = 0x3FFFFFFF
.LBB2_11: # in Loop: Header=BB2_3 Depth=2
incl %eax
movl matrix_size(%rip), %edx
cmpl %edx, %eax
jge .LBB2_12
.LBB2_3: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %edx
addl %eax, %edx
movslq %edx, %rdx
cmpl %eax, %ebp
jne .LBB2_4
# %bb.9: # in Loop: Header=BB2_3 Depth=2
cmpl vertex_num(%rip), %ebp
jge .LBB2_4
# %bb.10: # in Loop: Header=BB2_3 Depth=2
movl $0, (%rcx,%rdx,4)
jmp .LBB2_11
.Lfunc_end2:
.size _Z5inputPcRi, .Lfunc_end2-_Z5inputPcRi
.cfi_endproc
# -- End function
.globl _Z6outputPc # -- Begin function _Z6outputPc
.p2align 4, 0x90
.type _Z6outputPc,@function
_Z6outputPc: # @_Z6outputPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl vertex_num(%rip), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq matrix_size(%rip), %rdi
movslq %r14d, %r14
imulq %r14, %rdi
shlq $2, %rdi
addq dist(%rip), %rdi
movslq %eax, %rdx
movl $4, %esi
movq %rbx, %rcx
callq fwrite
incl %r14d
movl vertex_num(%rip), %eax
cmpl %eax, %r14d
jl .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z6outputPc, .Lfunc_end3-_Z6outputPc
.cfi_endproc
# -- End function
.globl _Z21__device_stub__phase1Pii # -- Begin function _Z21__device_stub__phase1Pii
.p2align 4, 0x90
.type _Z21__device_stub__phase1Pii,@function
_Z21__device_stub__phase1Pii: # @_Z21__device_stub__phase1Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6phase1Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z21__device_stub__phase1Pii, .Lfunc_end4-_Z21__device_stub__phase1Pii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__phase2Pii # -- Begin function _Z21__device_stub__phase2Pii
.p2align 4, 0x90
.type _Z21__device_stub__phase2Pii,@function
_Z21__device_stub__phase2Pii: # @_Z21__device_stub__phase2Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6phase2Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z21__device_stub__phase2Pii, .Lfunc_end5-_Z21__device_stub__phase2Pii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__phase3Pii # -- Begin function _Z21__device_stub__phase3Pii
.p2align 4, 0x90
.type _Z21__device_stub__phase3Pii,@function
_Z21__device_stub__phase3Pii: # @_Z21__device_stub__phase3Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6phase3Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z21__device_stub__phase3Pii, .Lfunc_end6-_Z21__device_stub__phase3Pii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebx
leaq 152(%rsp), %rsi
movl $1, %edi
callq clock_gettime
xorl %edi, %edi
callq hipSetDevice
movl $32, 12(%rsp)
cmpl $4, %ebx
jne .LBB7_2
# %bb.1:
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 12(%rsp)
.LBB7_2:
movq %r14, 104(%rsp) # 8-byte Spill
movq 8(%r14), %rdi
leaq 12(%rsp), %rsi
callq _Z5inputPcRi
movl matrix_size(%rip), %ecx
movl 12(%rsp), %ebx
movl %ecx, %eax
cltd
idivl %ebx
movl %eax, %r14d
movl %ecx, 124(%rsp)
movl %ebx, 128(%rsp)
movl %eax, 132(%rsp)
xorl %ebp, %ebp
leaq 124(%rsp), %rsi
movl $size, %edi
movl $12, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 136(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movslq matrix_size(%rip), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movq dist(%rip), %rsi
movslq matrix_size(%rip), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB7_11
# %bb.3: # %.lr.ph
movq %rbx, %r15
shlq $32, %r15
orq %rbx, %r15
leal -1(%r14), %eax
movq %rax, %r12
shlq $32, %r12
leaq 2(%r12), %r13
orq %rax, %r12
leaq 80(%rsp), %rbx
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_10: # in Loop: Header=BB7_4 Depth=1
incl %ebp
cmpl %ebp, %r14d
je .LBB7_11
.LBB7_4: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5: # in Loop: Header=BB7_4 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6phase1Pii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6: # in Loop: Header=BB7_4 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_8
# %bb.7: # in Loop: Header=BB7_4 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6phase2Pii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_8: # in Loop: Header=BB7_4 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_10
# %bb.9: # in Loop: Header=BB7_4 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6phase3Pii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_10
.LBB7_11: # %._crit_edge
movq dist(%rip), %rdi
movq 16(%rsp), %rsi
movslq matrix_size(%rip), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 24(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 104(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl vertex_num(%rip), %eax
testl %eax, %eax
jle .LBB7_14
# %bb.12: # %.lr.ph.i.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_13: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movslq matrix_size(%rip), %rdi
movslq %r14d, %r14
imulq %r14, %rdi
shlq $2, %rdi
addq dist(%rip), %rdi
movslq %eax, %rdx
movl $4, %esi
movq %rbx, %rcx
callq fwrite
incl %r14d
movl vertex_num(%rip), %eax
cmpl %eax, %r14d
jl .LBB7_13
.LBB7_14: # %_Z6outputPc.exit
movq %rbx, %rdi
callq fclose
movq 16(%rsp), %rdi
callq hipFree
movq dist(%rip), %rdi
callq hipFree
leaq 80(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 136(%rsp), %rax
movq 32(%rsp), %rcx
subq 144(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rax, %rsi
negq %rsi
testq %rcx, %rcx
notq %rax
cmovnsq %rcx, %rdx
cmovnsq %rsi, %rax
addq 24(%rsp), %rax
cvtsi2sd %rax, %xmm0
cvtsi2sd %rdx, %xmm2
movsd .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm2
movapd %xmm2, %xmm3
movq 88(%rsp), %rax
subq 160(%rsp), %rax
movq 152(%rsp), %rcx
leaq 1000000000(%rax), %rdx
movq %rcx, %rsi
negq %rsi
testq %rax, %rax
notq %rcx
cmovnsq %rax, %rdx
cmovnsq %rsi, %rcx
addq 80(%rsp), %rcx
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
cvtsi2sd %rdx, %xmm4
addsd %xmm0, %xmm3
movsd %xmm3, 112(%rsp) # 8-byte Spill
divsd %xmm1, %xmm4
addsd %xmm2, %xmm4
movsd %xmm4, 104(%rsp) # 8-byte Spill
movl vertex_num(%rip), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 112(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.5, %edi
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6phase1Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6phase2Pii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6phase3Pii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $size, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type vertex_num,@object # @vertex_num
.bss
.globl vertex_num
.p2align 2, 0x0
vertex_num:
.long 0 # 0x0
.size vertex_num, 4
.type edge_num,@object # @edge_num
.globl edge_num
.p2align 2, 0x0
edge_num:
.long 0 # 0x0
.size edge_num, 4
.type matrix_size,@object # @matrix_size
.globl matrix_size
.p2align 2, 0x0
matrix_size:
.long 0 # 0x0
.size matrix_size, 4
.type dist,@object # @dist
.globl dist
.p2align 3, 0x0
dist:
.quad 0
.size dist, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type size,@object # @size
.local size
.comm size,12,4
.type _Z6phase1Pii,@object # @_Z6phase1Pii
.section .rodata,"a",@progbits
.globl _Z6phase1Pii
.p2align 3, 0x0
_Z6phase1Pii:
.quad _Z21__device_stub__phase1Pii
.size _Z6phase1Pii, 8
.type _Z6phase2Pii,@object # @_Z6phase2Pii
.globl _Z6phase2Pii
.p2align 3, 0x0
_Z6phase2Pii:
.quad _Z21__device_stub__phase2Pii
.size _Z6phase2Pii, 8
.type _Z6phase3Pii,@object # @_Z6phase3Pii
.globl _Z6phase3Pii
.p2align 3, 0x0
_Z6phase3Pii:
.quad _Z21__device_stub__phase3Pii
.size _Z6phase3Pii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " vertex: %d\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " I/O time: %.5f\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " cal time: %.5f\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " runtime: %.5f\n"
.size .L.str.5, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6phase1Pii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6phase2Pii"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6phase3Pii"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "size"
.size .L__unnamed_4, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__phase1Pii
.addrsig_sym _Z21__device_stub__phase2Pii
.addrsig_sym _Z21__device_stub__phase3Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vertex_num
.addrsig_sym edge_num
.addrsig_sym dist
.addrsig_sym size
.addrsig_sym _Z6phase1Pii
.addrsig_sym _Z6phase2Pii
.addrsig_sym _Z6phase3Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103a38_00000000-6_hw4-1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8cal_time8timespecS_
.type _Z8cal_time8timespecS_, @function
_Z8cal_time8timespecS_:
.LFB2057:
.cfi_startproc
endbr64
movq %rdx, %r8
subq %rdi, %r8
movq %rcx, %rax
subq %rsi, %rax
js .L6
.L5:
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r8, %xmm1
addsd %xmm1, %xmm0
ret
.L6:
leaq -1(%r8), %r8
leaq 1000000000(%rcx), %rax
subq %rsi, %rax
jmp .L5
.cfi_endproc
.LFE2057:
.size _Z8cal_time8timespecS_, .-_Z8cal_time8timespecS_
.globl _Z13index_convertiii
.type _Z13index_convertiii, @function
_Z13index_convertiii:
.LFB2058:
.cfi_startproc
endbr64
imull %edx, %edi
addl %esi, %edi
movslq %edi, %rax
ret
.cfi_endproc
.LFE2058:
.size _Z13index_convertiii, .-_Z13index_convertiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "rb"
.text
.globl _Z5inputPcRi
.type _Z5inputPcRi, @function
_Z5inputPcRi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
leaq vertex_num(%rip), %rdi
call __fread_chk@PLT
movq %rbx, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
leaq edge_num(%rip), %rdi
call __fread_chk@PLT
pxor %xmm1, %xmm1
cvtsi2sdl 0(%rbp), %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl vertex_num(%rip), %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm4
movsd .LC5(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC2(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L9
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC4(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L9:
mulsd %xmm4, %xmm1
cvttsd2sil %xmm1, %eax
movl %eax, matrix_size(%rip)
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq dist(%rip), %rdi
call cudaMallocHost@PLT
movl $0, %ecx
cmpl $0, matrix_size(%rip)
jg .L10
.L11:
cmpl $0, edge_num(%rip)
jle .L17
movl $0, %ebp
leaq 12(%rsp), %r12
.L18:
movq %rbx, %r8
movl $3, %ecx
movl $4, %edx
movl $12, %esi
movq %r12, %rdi
call __fread_chk@PLT
movl matrix_size(%rip), %eax
imull 12(%rsp), %eax
addl 16(%rsp), %eax
cltq
movl 20(%rsp), %ecx
movq dist(%rip), %rdx
movl %ecx, (%rdx,%rax,4)
addl $1, %ebp
cmpl %ebp, edge_num(%rip)
jg .L18
.L17:
movq %rbx, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
imull %ecx, %eax
addl %edx, %eax
cltq
movq dist(%rip), %rsi
movl $1073741823, (%rsi,%rax,4)
.L13:
addl $1, %edx
movl matrix_size(%rip), %eax
cmpl %edx, %eax
jle .L16
.L15:
cmpl %edx, %ecx
jne .L28
cmpl %ecx, vertex_num(%rip)
jle .L14
imull %ecx, %eax
addl %edx, %eax
cltq
movq dist(%rip), %rsi
movl $0, (%rsi,%rax,4)
jmp .L13
.L14:
imull %ecx, %eax
addl %edx, %eax
cltq
movq dist(%rip), %rsi
movl $1073741823, (%rsi,%rax,4)
jmp .L13
.L16:
addl $1, %ecx
cmpl %ecx, matrix_size(%rip)
jle .L11
.L10:
movl matrix_size(%rip), %eax
movl $0, %edx
testl %eax, %eax
jg .L15
jmp .L16
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z5inputPcRi, .-_Z5inputPcRi
.section .rodata.str1.1
.LC6:
.string "w"
.text
.globl _Z6outputPc
.type _Z6outputPc, @function
_Z6outputPc:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC6(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl vertex_num(%rip), %edx
testl %edx, %edx
jle .L30
movl $0, %ebx
.L31:
movslq %edx, %rdx
movl %ebx, %eax
imull matrix_size(%rip), %eax
cltq
movq dist(%rip), %rcx
leaq (%rcx,%rax,4), %rdi
movq %rbp, %rcx
movl $4, %esi
call fwrite@PLT
addl $1, %ebx
movl vertex_num(%rip), %edx
cmpl %ebx, %edx
jg .L31
.L30:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z6outputPc, .-_Z6outputPc
.globl _Z26__device_stub__Z6phase1PiiPii
.type _Z26__device_stub__Z6phase1PiiPii, @function
_Z26__device_stub__Z6phase1PiiPii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6phase1Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z26__device_stub__Z6phase1PiiPii, .-_Z26__device_stub__Z6phase1PiiPii
.globl _Z6phase1Pii
.type _Z6phase1Pii, @function
_Z6phase1Pii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6phase1PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6phase1Pii, .-_Z6phase1Pii
.globl _Z26__device_stub__Z6phase2PiiPii
.type _Z26__device_stub__Z6phase2PiiPii, @function
_Z26__device_stub__Z6phase2PiiPii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6phase2Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z26__device_stub__Z6phase2PiiPii, .-_Z26__device_stub__Z6phase2PiiPii
.globl _Z6phase2Pii
.type _Z6phase2Pii, @function
_Z6phase2Pii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6phase2PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z6phase2Pii, .-_Z6phase2Pii
.globl _Z26__device_stub__Z6phase3PiiPii
.type _Z26__device_stub__Z6phase3PiiPii, @function
_Z26__device_stub__Z6phase3PiiPii:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6phase3Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z26__device_stub__Z6phase3PiiPii, .-_Z26__device_stub__Z6phase3PiiPii
.globl _Z6phase3Pii
.type _Z6phase3Pii, @function
_Z6phase3Pii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6phase3PiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z6phase3Pii, .-_Z6phase3Pii
.section .rodata.str1.1
.LC7:
.string " vertex: %d\n"
.LC8:
.string " I/O time: %.5f\n"
.LC9:
.string " cal time: %.5f\n"
.LC10:
.string " runtime: %.5f\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $176, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl $32, 28(%rsp)
cmpl $4, %ebx
je .L68
.L59:
leaq 28(%rsp), %rsi
movq 8(%r12), %rdi
call _Z5inputPcRi
movl matrix_size(%rip), %ecx
movl 28(%rsp), %ebx
movl %ecx, %eax
cltd
idivl %ebx
movl %eax, %ebp
movl %ecx, 156(%rsp)
movl %ebx, 160(%rsp)
movl %eax, 164(%rsp)
leaq 156(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $12, %edx
leaq _ZL4size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 112(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movslq matrix_size(%rip), %rsi
imulq %rsi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq matrix_size(%rip), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movl $1, %ecx
movq dist(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 44(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
leal -1(%rbp), %eax
movl $2, 56(%rsp)
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl %eax, 68(%rsp)
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
testl %ebp, %ebp
jle .L60
movl $0, %ebx
jmp .L64
.L68:
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
jmp .L59
.L69:
movl %ebx, %esi
movq 32(%rsp), %rdi
call _Z26__device_stub__Z6phase1PiiPii
jmp .L61
.L70:
movl %ebx, %esi
movq 32(%rsp), %rdi
call _Z26__device_stub__Z6phase2PiiPii
jmp .L62
.L63:
addl $1, %ebx
cmpl %ebx, %ebp
je .L60
.L64:
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L61:
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L62:
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L63
movl %ebx, %esi
movq 32(%rsp), %rdi
call _Z26__device_stub__Z6phase3PiiPii
jmp .L63
.L60:
movslq matrix_size(%rip), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq dist(%rip), %rdi
call cudaMemcpy@PLT
leaq 128(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 16(%r12), %rdi
call _Z6outputPc
movq 32(%rsp), %rdi
call cudaFree@PLT
movq dist(%rip), %rdi
call cudaFree@PLT
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 128(%rsp), %rdx
movq 136(%rsp), %rcx
movq 112(%rsp), %rdi
movq 120(%rsp), %rsi
call _Z8cal_time8timespecS_
movsd %xmm0, (%rsp)
movq 96(%rsp), %rdx
movq 104(%rsp), %rcx
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
call _Z8cal_time8timespecS_
movsd %xmm0, 8(%rsp)
movl vertex_num(%rip), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6phase3Pii"
.LC12:
.string "_Z6phase2Pii"
.LC13:
.string "_Z6phase1Pii"
.LC14:
.string "size"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6phase3Pii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6phase2Pii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6phase1Pii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4size
.comm _ZL4size,12,8
.globl dist
.bss
.align 8
.type dist, @object
.size dist, 8
dist:
.zero 8
.globl matrix_size
.align 4
.type matrix_size, @object
.size matrix_size, 4
matrix_size:
.zero 4
.globl edge_num
.align 4
.type edge_num, @object
.size edge_num, 4
edge_num:
.zero 4
.globl vertex_num
.align 4
.type vertex_num, @object
.size vertex_num, 4
vertex_num:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw4-1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8cal_time8timespecS_
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z8cal_time8timespecS_
.p2align 4, 0x90
.type _Z8cal_time8timespecS_,@function
_Z8cal_time8timespecS_: # @_Z8cal_time8timespecS_
.cfi_startproc
# %bb.0:
movq %rcx, %rax
subq %rsi, %rax
js .LBB0_1
# %bb.2:
subq %rdi, %rdx
movq %rdx, %rdi
jmp .LBB0_3
.LBB0_1:
notq %rdi
addq %rdx, %rdi
subq %rsi, %rcx
addq $1000000000, %rcx # imm = 0x3B9ACA00
movq %rcx, %rax
.LBB0_3:
cvtsi2sd %rdi, %xmm1
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z8cal_time8timespecS_, .Lfunc_end0-_Z8cal_time8timespecS_
.cfi_endproc
# -- End function
.globl _Z13index_convertiii # -- Begin function _Z13index_convertiii
.p2align 4, 0x90
.type _Z13index_convertiii,@function
_Z13index_convertiii: # @_Z13index_convertiii
.cfi_startproc
# %bb.0:
imull %edx, %edi
addl %esi, %edi
movslq %edi, %rax
retq
.Lfunc_end1:
.size _Z13index_convertiii, .Lfunc_end1-_Z13index_convertiii
.cfi_endproc
# -- End function
.globl _Z5inputPcRi # -- Begin function _Z5inputPcRi
.p2align 4, 0x90
.type _Z5inputPcRi,@function
_Z5inputPcRi: # @_Z5inputPcRi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
movl $vertex_num, %edi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movl $edge_num, %edi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fread
cvtsi2sdl vertex_num(%rip), %xmm0
cvtsi2sdl (%r14), %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
divsd %xmm1, %xmm0
callq ceil@PLT
mulsd 24(%rsp), %xmm0 # 8-byte Folded Reload
cvttsd2si %xmm0, %esi
movl %esi, matrix_size(%rip)
imull %esi, %esi
shlq $2, %rsi
xorl %ebp, %ebp
movl $dist, %edi
xorl %edx, %edx
callq hipHostMalloc
cmpl $0, matrix_size(%rip)
jg .LBB2_1
.LBB2_5: # %._crit_edge26
cmpl $0, edge_num(%rip)
jle .LBB2_8
# %bb.6: # %.lr.ph29
xorl %ebp, %ebp
leaq 12(%rsp), %r14
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movl $3, %edx
movq %r14, %rdi
movq %rbx, %rcx
callq fread
movl 20(%rsp), %eax
movq dist(%rip), %rcx
movslq 12(%rsp), %rdx
movslq 16(%rsp), %rsi
movslq matrix_size(%rip), %rdi
imulq %rdx, %rdi
addq %rsi, %rdi
movl %eax, (%rcx,%rdi,4)
incl %ebp
cmpl edge_num(%rip), %ebp
jl .LBB2_7
.LBB2_8: # %._crit_edge30
movq %rbx, %rdi
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.p2align 4, 0x90
.LBB2_12: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
.cfi_def_cfa_offset 64
incl %ebp
cmpl matrix_size(%rip), %ebp
jge .LBB2_5
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl matrix_size(%rip), %edx
testl %edx, %edx
jle .LBB2_12
# %bb.2: # %.lr.ph
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
movq dist(%rip), %rcx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_3 Depth=2
movl $1073741823, (%rcx,%rdx,4) # imm = 0x3FFFFFFF
.LBB2_11: # in Loop: Header=BB2_3 Depth=2
incl %eax
movl matrix_size(%rip), %edx
cmpl %edx, %eax
jge .LBB2_12
.LBB2_3: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %edx
addl %eax, %edx
movslq %edx, %rdx
cmpl %eax, %ebp
jne .LBB2_4
# %bb.9: # in Loop: Header=BB2_3 Depth=2
cmpl vertex_num(%rip), %ebp
jge .LBB2_4
# %bb.10: # in Loop: Header=BB2_3 Depth=2
movl $0, (%rcx,%rdx,4)
jmp .LBB2_11
.Lfunc_end2:
.size _Z5inputPcRi, .Lfunc_end2-_Z5inputPcRi
.cfi_endproc
# -- End function
.globl _Z6outputPc # -- Begin function _Z6outputPc
.p2align 4, 0x90
.type _Z6outputPc,@function
_Z6outputPc: # @_Z6outputPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl vertex_num(%rip), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq matrix_size(%rip), %rdi
movslq %r14d, %r14
imulq %r14, %rdi
shlq $2, %rdi
addq dist(%rip), %rdi
movslq %eax, %rdx
movl $4, %esi
movq %rbx, %rcx
callq fwrite
incl %r14d
movl vertex_num(%rip), %eax
cmpl %eax, %r14d
jl .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z6outputPc, .Lfunc_end3-_Z6outputPc
.cfi_endproc
# -- End function
.globl _Z21__device_stub__phase1Pii # -- Begin function _Z21__device_stub__phase1Pii
.p2align 4, 0x90
.type _Z21__device_stub__phase1Pii,@function
_Z21__device_stub__phase1Pii: # @_Z21__device_stub__phase1Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6phase1Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z21__device_stub__phase1Pii, .Lfunc_end4-_Z21__device_stub__phase1Pii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__phase2Pii # -- Begin function _Z21__device_stub__phase2Pii
.p2align 4, 0x90
.type _Z21__device_stub__phase2Pii,@function
_Z21__device_stub__phase2Pii: # @_Z21__device_stub__phase2Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6phase2Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z21__device_stub__phase2Pii, .Lfunc_end5-_Z21__device_stub__phase2Pii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__phase3Pii # -- Begin function _Z21__device_stub__phase3Pii
.p2align 4, 0x90
.type _Z21__device_stub__phase3Pii,@function
_Z21__device_stub__phase3Pii: # @_Z21__device_stub__phase3Pii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6phase3Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z21__device_stub__phase3Pii, .Lfunc_end6-_Z21__device_stub__phase3Pii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebx
leaq 152(%rsp), %rsi
movl $1, %edi
callq clock_gettime
xorl %edi, %edi
callq hipSetDevice
movl $32, 12(%rsp)
cmpl $4, %ebx
jne .LBB7_2
# %bb.1:
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 12(%rsp)
.LBB7_2:
movq %r14, 104(%rsp) # 8-byte Spill
movq 8(%r14), %rdi
leaq 12(%rsp), %rsi
callq _Z5inputPcRi
movl matrix_size(%rip), %ecx
movl 12(%rsp), %ebx
movl %ecx, %eax
cltd
idivl %ebx
movl %eax, %r14d
movl %ecx, 124(%rsp)
movl %ebx, 128(%rsp)
movl %eax, 132(%rsp)
xorl %ebp, %ebp
leaq 124(%rsp), %rsi
movl $size, %edi
movl $12, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 136(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movslq matrix_size(%rip), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movq dist(%rip), %rsi
movslq matrix_size(%rip), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB7_11
# %bb.3: # %.lr.ph
movq %rbx, %r15
shlq $32, %r15
orq %rbx, %r15
leal -1(%r14), %eax
movq %rax, %r12
shlq $32, %r12
leaq 2(%r12), %r13
orq %rax, %r12
leaq 80(%rsp), %rbx
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_10: # in Loop: Header=BB7_4 Depth=1
incl %ebp
cmpl %ebp, %r14d
je .LBB7_11
.LBB7_4: # =>This Inner Loop Header: Depth=1
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5: # in Loop: Header=BB7_4 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6phase1Pii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6: # in Loop: Header=BB7_4 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_8
# %bb.7: # in Loop: Header=BB7_4 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6phase2Pii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_8: # in Loop: Header=BB7_4 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_10
# %bb.9: # in Loop: Header=BB7_4 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6phase3Pii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_10
.LBB7_11: # %._crit_edge
movq dist(%rip), %rdi
movq 16(%rsp), %rsi
movslq matrix_size(%rip), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 24(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 104(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl vertex_num(%rip), %eax
testl %eax, %eax
jle .LBB7_14
# %bb.12: # %.lr.ph.i.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_13: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movslq matrix_size(%rip), %rdi
movslq %r14d, %r14
imulq %r14, %rdi
shlq $2, %rdi
addq dist(%rip), %rdi
movslq %eax, %rdx
movl $4, %esi
movq %rbx, %rcx
callq fwrite
incl %r14d
movl vertex_num(%rip), %eax
cmpl %eax, %r14d
jl .LBB7_13
.LBB7_14: # %_Z6outputPc.exit
movq %rbx, %rdi
callq fclose
movq 16(%rsp), %rdi
callq hipFree
movq dist(%rip), %rdi
callq hipFree
leaq 80(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 136(%rsp), %rax
movq 32(%rsp), %rcx
subq 144(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rax, %rsi
negq %rsi
testq %rcx, %rcx
notq %rax
cmovnsq %rcx, %rdx
cmovnsq %rsi, %rax
addq 24(%rsp), %rax
cvtsi2sd %rax, %xmm0
cvtsi2sd %rdx, %xmm2
movsd .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm2
movapd %xmm2, %xmm3
movq 88(%rsp), %rax
subq 160(%rsp), %rax
movq 152(%rsp), %rcx
leaq 1000000000(%rax), %rdx
movq %rcx, %rsi
negq %rsi
testq %rax, %rax
notq %rcx
cmovnsq %rax, %rdx
cmovnsq %rsi, %rcx
addq 80(%rsp), %rcx
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
cvtsi2sd %rdx, %xmm4
addsd %xmm0, %xmm3
movsd %xmm3, 112(%rsp) # 8-byte Spill
divsd %xmm1, %xmm4
addsd %xmm2, %xmm4
movsd %xmm4, 104(%rsp) # 8-byte Spill
movl vertex_num(%rip), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 112(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.5, %edi
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6phase1Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6phase2Pii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6phase3Pii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $size, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type vertex_num,@object # @vertex_num
.bss
.globl vertex_num
.p2align 2, 0x0
vertex_num:
.long 0 # 0x0
.size vertex_num, 4
.type edge_num,@object # @edge_num
.globl edge_num
.p2align 2, 0x0
edge_num:
.long 0 # 0x0
.size edge_num, 4
.type matrix_size,@object # @matrix_size
.globl matrix_size
.p2align 2, 0x0
matrix_size:
.long 0 # 0x0
.size matrix_size, 4
.type dist,@object # @dist
.globl dist
.p2align 3, 0x0
dist:
.quad 0
.size dist, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type size,@object # @size
.local size
.comm size,12,4
.type _Z6phase1Pii,@object # @_Z6phase1Pii
.section .rodata,"a",@progbits
.globl _Z6phase1Pii
.p2align 3, 0x0
_Z6phase1Pii:
.quad _Z21__device_stub__phase1Pii
.size _Z6phase1Pii, 8
.type _Z6phase2Pii,@object # @_Z6phase2Pii
.globl _Z6phase2Pii
.p2align 3, 0x0
_Z6phase2Pii:
.quad _Z21__device_stub__phase2Pii
.size _Z6phase2Pii, 8
.type _Z6phase3Pii,@object # @_Z6phase3Pii
.globl _Z6phase3Pii
.p2align 3, 0x0
_Z6phase3Pii:
.quad _Z21__device_stub__phase3Pii
.size _Z6phase3Pii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " vertex: %d\n"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " I/O time: %.5f\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " cal time: %.5f\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " runtime: %.5f\n"
.size .L.str.5, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6phase1Pii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6phase2Pii"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6phase3Pii"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "size"
.size .L__unnamed_4, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__phase1Pii
.addrsig_sym _Z21__device_stub__phase2Pii
.addrsig_sym _Z21__device_stub__phase3Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vertex_num
.addrsig_sym edge_num
.addrsig_sym dist
.addrsig_sym size
.addrsig_sym _Z6phase1Pii
.addrsig_sym _Z6phase2Pii
.addrsig_sym _Z6phase3Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define WARP_SIZE 32
extern "C"
{
__global__ void cuda_test(
int anglebatch,
int numgroups,
int ncornr,
int size_maxCorner,
double* psicbatch)
{
int Groups=192;
#define psicbatch(ig,b,c) psicbatch[(ig) + Groups * ((b) + size_maxCorner *(c) )]
printf("anglebatch = %d\n", anglebatch);
//printf("numgroups = %d\n", numgroups);
//printf("ncornr = %d\n", ncornr);
//printf("size_maxCorner = %d\n",size_maxCorner);
for (int angle=blockIdx.x; angle<anglebatch; angle+=gridDim.x) {
for(int c=0; c<size_maxCorner; c++) {
{
for (int g=threadIdx.x; g<numgroups; g+= blockDim.x) {
psicbatch(g,c,angle) = 1;
}
}
}
}
}
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* AngleOrder,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib )
{
// double omega[3];
int c,ig,i,icface,ifp,cez,k,ii;
// double Q[Groups * size_maxCorner];
// double src[Groups * size_maxCorner];
// double SigtVol[Groups * size_maxCorner];
// double afpm[size_maxcf];
// double psifp[Groups * size_maxcf];
// int ez_exit[size_maxcf];
// double coefpsic[size_maxcf];
// double tpsic[Groups * size_maxCorner];
// double psi_opp[Groups];
double area_opp,area_inv,sumArea;
double r_psifp;
double psi_opp,tpsic;
double omega0, omega1, omega2;
__shared__ double *Q, *src, *volume, *coefpsic, *afpm, *psifp;
__shared__ int *ez_exit;
__shared__ double sm_agg[625];
int offset = 0;
Q = &(sm_agg[0]);
offset += size_maxCorner * WARP_SIZE;
src = &(sm_agg[offset]);
offset += size_maxCorner * WARP_SIZE;
volume = &(sm_agg[offset]);
offset += size_maxCorner;
coefpsic = &(sm_agg[offset]);
offset += size_maxcf;
afpm = &(sm_agg[offset]);
offset += size_maxcf;
psifp = &(sm_agg[offset]);
offset += size_maxcf * WARP_SIZE;
//note ez_exit has integer type
ez_exit = (int*) &(sm_agg[offset]);
const double fouralpha = 1.82;
// const double fouralpha4 = 5.82;
#define soa_omega(a,b) soa_omega[a + 3 * b]
// #define tpsic(ig,c) tpsic[ (ig) + Groups * (c)]
#define EB_ListExit(a,ia) EB_ListExit[ a + 2 * (ia) ]
#define soa_A_fp(a,icface,c,zone) soa_A_fp[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_A_ez(a,icface,c,zone) soa_A_ez[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_Connect(a,icface,c,zone) soa_Connect[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define psifp(ig,jf) psifp[(ig) + Groups * (jf)]
#define psib(ig,b,c) psib[(ig) + Groups * ((b) + nbelem * (c) )]
#define psic(ig,b,c) psic[(ig) + Groups * ((b) + size_maxCorner *(c) )]
#define Q(ig,c) Q[(ig) + Groups * (c)]
#define src(ig,c) src[(ig) + Groups * (c)]
// #define SigtVol(ig,c) SigtVol[(ig) + Groups * (c)]
#define soa_Sigt(ig,zone) soa_Sigt[(ig) + Groups * (zone)]
#define soa_Volume(c,zone) soa_Volume[(ig) + Groups * (zone)]
#define soa_SigtInv(ig,zone) soa_SigtInv[(ig) + Groups * (zone)]
#define soa_STotal(ig,c,zone) soa_STotal[ig + Groups * ( c + size_maxCorner * (zone) )]
#define soa_STime(ig,c,Angle,zone) soa_STime[ig + Groups * ( c + size_maxCorner * ( Angle + nAngle * (zone) ) )]
#define nextZ(a,b) nextZ[ (a) + nzones * (b) ]
#define next(a,b) next[ (a) + (ncornr+1) * (b) ]
// for(int Angle=0;Angle<nAngle;Angle++)
int Angle = blockIdx.y;
ig = threadIdx.x;
// if(ig==0) printf("my offset=%d\n",offset);
// if(ig==0)
// {
// printf("psic=%x\n",psic);
// printf("nextZ=%x\n",psic);
// printf("next=%x\n",psic);
// printf("psib=%x\n",psic);
// }
{
omega0 = soa_omega(0,Angle);
omega1 = soa_omega(1,Angle);
omega2 = soa_omega(2,Angle);
int ndone = 0;
for(ii=0;ii<nzones;ii++)
{
int zone = nextZ(ii,Angle) - 1;
int nCorner = soa_nCorner[zone];
int nCFaces = soa_nCFaces[zone];
int c0 = soa_c0[zone] ;
double Sigt = soa_Sigt(ig,zone);
for(c=0;c<nCorner;c++)
{
double source = soa_STotal(ig,c,zone) + soa_STime(ig,c,Angle,zone);
Q(ig,c) = soa_SigtInv(ig,zone)*source ;
src(ig,c) = soa_Volume(c,zone) *source;
//SigtVol(ig,c) = soa_Sigt(ig,zone)*soa_Volume(c,zone);
volume[c] = soa_Volume(c,zone);
}
for(i=0;i<nCorner;i++)
{
int ic = next(ndone+i,Angle);
c = ic - c0 - 1;
sumArea = 0.0;
for(icface=0;icface<nCFaces;icface++)
{
afpm[icface] = omega0*soa_A_fp(0,icface,c,zone) +
omega1*soa_A_fp(1,icface,c,zone) +
omega2*soa_A_fp(2,icface,c,zone);
int icfp = soa_Connect(1,icface,c,zone) - 1;
int ib = soa_Connect(2,icface,c,zone) - 1;
if ( afpm[icface] >= 0.0 )
{
sumArea = sumArea + afpm[icface];
}
else
{
if (icfp == 0)
{
// psifp(ig,icface) = psib(ig,ib,Angle);
r_psifp = psib(ig,ib,Angle);
// r_psifp = 0.3;
}
else
{
// psifp(ig,icface) = psic(ig,icfp,Angle);
r_psifp = psic(ig,icfp,Angle);
// r_psifp = 0.7;
}
src(ig,c) -= afpm[icface]*r_psifp;
psifp(ig,icface) = r_psifp;
}
}
int nxez = 0;
for(icface=0;icface<nCFaces;icface++)
{
double aez = omega0*soa_A_ez(0,icface,c,zone) + omega1*soa_A_ez(1,icface,c,zone) + omega2*soa_A_ez(2,icface,c,zone) ;
if (aez > 0.0 )
{
sumArea = sumArea + aez;
area_opp = .0;
cez = soa_Connect(2,icface,c,zone) - 1;
ez_exit[nxez] = cez;
coefpsic[nxez] = aez;
nxez = nxez + 1;
if (nCFaces == 3)
{
ifp = (icface+1)%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = -afpm[ifp];
psi_opp = psifp(ig,ifp);
}
}
else
{
ifp = icface;
area_opp = 0.0;
psi_opp = 0.0;
for(k=0;k<nCFaces-2;k++)
{
ifp = ifp%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = area_opp - afpm[ifp];
psi_opp = psi_opp - afpm[ifp]*psifp(ig,ifp);
}
}
area_inv = 1.0/area_opp;
psi_opp = psi_opp*area_inv;
}
if (area_opp > 0.0) {
double aez2 = aez*aez;
{
double sigv = Sigt*volume[c];
double sigv2 = sigv*sigv;
double gnum = aez2*( fouralpha*sigv2 + aez*(4.0*sigv + 3.0*aez) );
double gtau = gnum/( gnum + 4.0*sigv2*sigv2 + aez*sigv*(6.0*sigv2 + 2.0*aez*(2.0*sigv + aez)) ) ;
double sez = gtau*sigv*( psi_opp - Q(ig,c) ) + 0.5*aez*(1.0 - gtau)*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
else
{
double sez = 0.5*aez*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
}
// printf("ckim angle,zone,corner,aez_cnt %d,%d,%d,%d\n",Angle,zone,c,aez_cnt);
tpsic = src(ig,c)/(sumArea + Sigt*volume[c]);
for(icface=0;icface<nxez;icface++)
{
int cez = ez_exit[icface];
src(ig,cez) = src(ig,cez) + coefpsic[icface]*tpsic;
}
//hope that ther is no self referencing
psic(ig,c0+c,Angle) = tpsic;
}
ndone = ndone + nCorner;
}
}
// ExitBdy => getExitList(QuadSet, Angle)
// for(i=0;i<EB_nExit;i++)
// {
// int ib = EB_ListExit(1,i);
// int ic = EB_ListExit(2,i);
// for(ig=0;ig<Groups;ig++)
// psib(ig,ib) = psic(ig,ic);
// }
}
void CC_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib )
{
double omega[3];
int c,ig,i,icface,ifp,cez,k,ii;
double Q[Groups * size_maxCorner];
double src[Groups * size_maxCorner];
double SigtVol[Groups * size_maxCorner];
double afpm[size_maxcf];
double psifp[Groups * size_maxcf];
int ez_exit[size_maxcf];
double coefpsic[size_maxcf];
double tpsic[Groups * size_maxCorner];
double psi_opp[Groups];
double area_opp,area_inv,sumArea;
const double fouralpha = 1.82;
// const double fouralpha4 = 5.82;
#define soa_omega(a,b) soa_omega[a + 3 * b]
#define tpsic(ig,c) tpsic[ (ig) + Groups * (c)]
#define EB_ListExit(a,ia) EB_ListExit[ a + 2 * (ia) ]
#define soa_A_fp(a,icface,c,zone) soa_A_fp[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_A_ez(a,icface,c,zone) soa_A_ez[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_Connect(a,icface,c,zone) soa_Connect[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define psifp(ig,jf) psifp[(ig) + Groups * (jf)]
#define psib(ig,b,c) psib[(ig) + Groups * ((b) + nbelem * (c) )]
#define psic(ig,b,c) psic[(ig) + Groups * ((b) + size_maxCorner *(c) )]
#define Q(ig,c) Q[(ig) + Groups * (c)]
#define src(ig,c) src[(ig) + Groups * (c)]
#define SigtVol(ig,c) SigtVol[(ig) + Groups * (c)]
#define soa_Sigt(ig,zone) soa_Sigt[(ig) + Groups * (zone)]
#define soa_Volume(c,zone) soa_Volume[(ig) + Groups * (zone)]
#define soa_SigtInv(ig,zone) soa_SigtInv[(ig) + Groups * (zone)]
#define soa_STotal(ig,c,zone) soa_STotal[ig + Groups * ( c + size_maxCorner * (zone) )]
#define soa_STime(ig,c,Angle,zone) soa_STime[ig + Groups * ( c + size_maxCorner * ( Angle + nAngle * (zone) ) )]
#define nextZ(a,b) nextZ[ (a) + nzones * (b) ]
#define next(a,b) next[ (a) + (ncornr+1) * (b) ]
for(int Angle=0;Angle<nAngle;Angle++)
{
omega[0] = soa_omega(0,Angle);
omega[1] = soa_omega(1,Angle);
omega[2] = soa_omega(2,Angle);
int ndone = 0;
for(ii=0;ii<nzones;ii++)
{
int zone = nextZ(ii,Angle) - 1;
int nCorner = soa_nCorner[zone];
int nCFaces = soa_nCFaces[zone];
int c0 = soa_c0[zone] ;
for(c=0;c<nCorner;c++)
{
for(ig=0;ig<Groups;ig++)
{
double source = soa_STotal(ig,c,zone) + soa_STime(ig,c,Angle,zone);
Q(ig,c) = soa_SigtInv(ig,zone)*source ;
src(ig,c) = soa_Volume(c,zone) *source;
SigtVol(ig,c) = soa_Sigt(ig,zone)*soa_Volume(c,zone);
}
}
for(i=0;i<nCorner;i++)
{
int ic = next(ndone+i,Angle);
c = ic - c0 - 1;
sumArea = 0.0;
for(icface=0;icface<nCFaces;icface++)
{
afpm[icface] = omega[0]*soa_A_fp(0,icface,c,zone) +
omega[1]*soa_A_fp(1,icface,c,zone) +
omega[2]*soa_A_fp(2,icface,c,zone);
int icfp = soa_Connect(1,icface,c,zone) - 1;
int ib = soa_Connect(2,icface,c,zone) - 1;
if ( afpm[icface] >= 0.0 )
{
sumArea = sumArea + afpm[icface];
}
else
{
if (icfp == 0)
{
for(ig=0;ig<Groups;ig++) psifp(ig,icface) = psib(ig,ib,Angle);
}
else
{
for(ig=0;ig<Groups;ig++) psifp(ig,icface) = psic(ig,icfp,Angle);
}
for(ig=0;ig<Groups;ig++) src(ig,c) = src(ig,c) - afpm[icface]*psifp(ig,icface);
}
}
int nxez = 0;
for(icface=0;icface<nCFaces;icface++)
{
double aez = omega[0]*soa_A_ez(0,icface,c,zone) + omega[1]*soa_A_ez(1,icface,c,zone) + omega[2]*soa_A_ez(2,icface,c,zone) ;
if (aez > 0.0 )
{
sumArea = sumArea + aez;
area_opp = .0;
cez = soa_Connect(2,icface,c,zone) - 1;
ez_exit[nxez] = cez;
coefpsic[nxez] = aez;
nxez = nxez + 1;
if (nCFaces == 3)
{
ifp = icface%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = -afpm[ifp];
for(ig=0;ig<Groups;ig++) psi_opp[ig] = psifp(ig,ifp);
}
}
else
{
ifp = icface;
area_opp = 0.0;
for(ig=0;ig<Groups;ig++) psi_opp[ig] = 0.0;
for(k=0;k<nCFaces-2;k++)
{
ifp = ifp%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = area_opp - afpm[ifp];
for(ig=0;ig<Groups;ig++) psi_opp[ig] = psi_opp[ig] - afpm[ifp]*psifp(ig,ifp);
}
}
area_inv = 1.0/area_opp;
for(ig=0;ig<Groups;ig++)
psi_opp[ig] = psi_opp[ig]*area_inv;
}
if (area_opp > 0.0) {
double aez2 = aez*aez;
for(ig=0;ig<Groups;ig++)
{
double sigv = SigtVol(ig,c);
double sigv2 = sigv*sigv;
double gnum = aez2*( fouralpha*sigv2 + aez*(4.0*sigv + 3.0*aez) );
double gtau = gnum/( gnum + 4.0*sigv2*sigv2 + aez*sigv*(6.0*sigv2 + 2.0*aez*(2.0*sigv + aez)) ) ;
double sez = gtau*sigv*( psi_opp[ig] - Q(ig,c) ) + 0.5*aez*(1.0 - gtau)*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
else
{
for(ig=0;ig<Groups;ig++)
{
double sez = 0.5*aez*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
}
}
// printf("ckim angle,zone,corner,aez_cnt %d,%d,%d,%d\n",Angle,zone,c,aez_cnt);
for(ig=0;ig<Groups;ig++)
tpsic(ig,c) = src(ig,c)/(sumArea + SigtVol(ig,c));
for(icface=0;icface<nxez;icface++)
{
int cez = ez_exit[icface];
for(ig=0;ig<Groups;ig++)
src(ig,cez) = src(ig,cez) + coefpsic[icface]*tpsic(ig,c);
}
}
ndone = ndone + nCorner;
for(c=0;c<nCorner;c++)
{
for(ig=0;ig<Groups;ig++)
psic(ig,c0+c,Angle) = tpsic(ig,c);
}
}
ndone++;
}
// ExitBdy => getExitList(QuadSet, Angle)
// for(i=0;i<EB_nExit;i++)
// {
// int ib = EB_ListExit(1,i);
// int ic = EB_ListExit(2,i);
// for(ig=0;ig<Groups;ig++)
// psib(ig,ib) = psic(ig,ic);
// }
}
} | .file "tmpxft_001ab0ec_00000000-6_cu_sweep.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl CC_sweep
.type CC_sweep, @function
CC_sweep:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $408, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -324(%rbp)
movl %esi, -224(%rbp)
movl %edx, -316(%rbp)
movl %ecx, %r10d
movl %r8d, %ebx
movl %r9d, %r12d
movq 32(%rbp), %r11
movq 40(%rbp), %rsi
movq 48(%rbp), %rax
movq %rax, -344(%rbp)
movq 56(%rbp), %rax
movq %rax, -352(%rbp)
movq 64(%rbp), %rax
movq %rax, -360(%rbp)
movq 72(%rbp), %rax
movq %rax, -368(%rbp)
movq 80(%rbp), %rax
movq %rax, -256(%rbp)
movq 88(%rbp), %rax
movq %rax, -264(%rbp)
movq 96(%rbp), %rax
movq %rax, -376(%rbp)
movq 104(%rbp), %rax
movq %rax, -384(%rbp)
movq 112(%rbp), %rax
movq %rax, -392(%rbp)
movq 120(%rbp), %rax
movq %rax, -272(%rbp)
movq 128(%rbp), %rax
movq %rax, -280(%rbp)
movq 136(%rbp), %rax
movq %rax, -216(%rbp)
movq 144(%rbp), %rax
movq %rax, -288(%rbp)
movq 152(%rbp), %rax
movq %rax, -304(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl %edi, %eax
imull %r9d, %eax
cltq
leaq 0(,%rax,8), %rdx
leaq 15(%rdx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdi
subq %rax, %rdi
.L4:
cmpq %rdi, %rsp
je .L5
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L4
.L5:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L6
movq %rcx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L6:
movq %rsp, -144(%rbp)
leaq 15(%rdx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdi
subq %rax, %rdi
.L7:
cmpq %rdi, %rsp
je .L8
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L7
.L8:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L9
movq %rcx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L9:
movq %rsp, -96(%rbp)
leaq 15(%rdx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdi
subq %rax, %rdi
.L10:
cmpq %rdi, %rsp
je .L11
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L10
.L11:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L12
movq %rcx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L12:
movq %rsp, -168(%rbp)
movslq -224(%rbp), %rcx
leaq 0(,%rcx,8), %rdi
leaq 15(%rdi), %rax
movq %rax, %r8
andq $-16, %r8
andq $-4096, %rax
movq %rsp, %r9
subq %rax, %r9
.L13:
cmpq %r9, %rsp
je .L14
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L13
.L14:
movq %r8, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L15
movq %r8, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L15:
movq %rsp, -120(%rbp)
movl -224(%rbp), %eax
imull %r12d, %eax
cltq
leaq 15(,%rax,8), %rax
movq %rax, %r8
andq $-16, %r8
andq $-4096, %rax
movq %rsp, %r9
subq %rax, %r9
.L16:
cmpq %r9, %rsp
je .L17
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L16
.L17:
movq %r8, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L18
movq %r8, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L18:
movq %rsp, -88(%rbp)
leaq 15(,%rcx,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %r8
subq %rax, %r8
.L19:
cmpq %r8, %rsp
je .L20
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L19
.L20:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L21
movq %rcx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L21:
movq %rsp, -104(%rbp)
leaq 15(%rdi), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdi
subq %rax, %rdi
.L22:
cmpq %rdi, %rsp
je .L23
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L22
.L23:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L24
movq %rcx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L24:
movq %rsp, -112(%rbp)
leaq 15(%rdx), %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L25:
cmpq %rcx, %rsp
je .L26
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L25
.L26:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L27
movq %rdx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L27:
movq %rsp, -200(%rbp)
movslq %r12d, %rax
movq %rax, -208(%rbp)
leaq 0(,%rax,8), %r15
leaq 15(%r15), %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L28:
cmpq %rcx, %rsp
je .L29
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L28
.L29:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L30
movq %rdx, %rax
andl $4095, %eax
orq $0, -8(%rsp,%rax)
.L30:
movq %rsp, %r13
cmpl $0, -316(%rbp)
jle .L3
movq %r11, %rcx
leal 1(%rbx), %r11d
leaq 0(%r13,%r15), %r14
movl $0, -312(%rbp)
movl $0, %edi
movl $0, %ebx
movl $0, -320(%rbp)
movl $0, -296(%rbp)
movsd .LC4(%rip), %xmm15
movq %r14, -400(%rbp)
movq %r15, %r14
movl %r11d, %r9d
movl %r10d, %r15d
movq %rsi, %r10
movq %r13, -408(%rbp)
movl %r12d, %r13d
movl %edi, %r12d
jmp .L84
.L37:
movslq %ebx, %rax
movq -256(%rbp), %rdi
leaq (%rdi,%rax,8), %r9
movl -72(%rbp), %eax
addl %ebx, %eax
cltq
movq -264(%rbp), %rdi
leaq (%rdi,%rax,8), %r8
movslq %r13d, %rdx
salq $3, %rdx
movq -144(%rbp), %rax
leaq (%rax,%rdx), %rdi
movq -96(%rbp), %rax
leaq (%rax,%rdx), %rsi
movq -168(%rbp), %rax
addq %rax, %rdx
movl $0, %eax
.L35:
movsd (%r9,%rax), %xmm1
addsd (%r8,%rax), %xmm1
movapd %xmm1, %xmm3
mulsd (%r11,%rax), %xmm3
movsd %xmm3, (%rdi,%rax)
movsd (%r10,%rax), %xmm3
mulsd %xmm3, %xmm1
movsd %xmm1, (%rsi,%rax)
mulsd (%rcx,%rax), %xmm3
movsd %xmm3, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %r15
jne .L35
.L38:
addl $1, %r12d
addl %r14d, %ebx
addl %r14d, %r13d
cmpl %r12d, -176(%rbp)
je .L36
.L34:
testl %r14d, %r14d
jg .L37
jmp .L38
.L36:
movl -76(%rbp), %r13d
movq -128(%rbp), %r9
movq -136(%rbp), %r12
movslq -328(%rbp), %rax
movslq -308(%rbp), %rdx
addq %rdx, %rax
movq -344(%rbp), %rdi
leaq (%rdi,%rax,4), %rbx
movq %rbx, -152(%rbp)
movslq -176(%rbp), %rdx
addq %rax, %rdx
leaq (%rdi,%rdx,4), %rax
movq %rax, -232(%rbp)
movslq %r13d, %rax
movq -120(%rbp), %rdi
leaq (%rdi,%rax,8), %rax
movq %rax, -248(%rbp)
movsd .LC6(%rip), %xmm12
movapd %xmm0, %xmm14
movapd %xmm4, %xmm0
movapd %xmm2, %xmm4
movl %r13d, %ebx
movq -400(%rbp), %r13
movq %r9, -448(%rbp)
jmp .L77
.L120:
movl 4(%rsi), %ebx
movl (%rsi), %edx
subl $1, %edx
je .L43
testl %r14d, %r14d
jle .L42
movl -292(%rbp), %ebx
addl %ebx, %edx
imull %r14d, %edx
movslq %edx, %rdx
movq -288(%rbp), %rbx
leaq (%rbx,%rdx,8), %r13
movslq %r8d, %rdx
movq -88(%rbp), %rbx
leaq (%rbx,%rdx,8), %rbx
movl $0, %edx
.L47:
movsd 0(%r13,%rdx), %xmm2
movsd %xmm2, (%rbx,%rdx)
addq $8, %rdx
cmpq %rdx, %r15
jne .L47
jmp .L46
.L43:
testl %r14d, %r14d
jle .L42
movl -240(%rbp), %edx
leal -1(%rbx,%rdx), %edx
imull %r14d, %edx
movslq %edx, %rdx
movq -304(%rbp), %rbx
leaq (%rbx,%rdx,8), %r13
movslq %r8d, %rdx
movq -88(%rbp), %rbx
leaq (%rbx,%rdx,8), %rbx
movl $0, %edx
.L45:
movsd 0(%r13,%rdx), %xmm2
movsd %xmm2, (%rbx,%rdx)
addq $8, %rdx
cmpq %rdx, %r15
jne .L45
.L46:
movslq %r8d, %rdx
movq -88(%rbp), %rbx
leaq (%rbx,%rdx,8), %rbx
movq %rdi, %rdx
.L48:
movapd %xmm1, %xmm3
mulsd (%rbx), %xmm3
movsd (%rdx), %xmm2
subsd %xmm3, %xmm2
movsd %xmm2, (%rdx)
addq $8, %rdx
addq $8, %rbx
cmpq %r9, %rdx
jne .L48
.L42:
addq $24, %rax
addq $8, %rcx
addq $12, %rsi
addl %r14d, %r8d
cmpq %r11, %rcx
je .L129
.L49:
movapd %xmm0, %xmm1
mulsd (%rax), %xmm1
movapd %xmm4, %xmm2
mulsd 8(%rax), %xmm2
addsd %xmm2, %xmm1
movapd %xmm14, %xmm2
mulsd 16(%rax), %xmm2
addsd %xmm2, %xmm1
movsd %xmm1, (%rcx)
comisd %xmm6, %xmm1
jb .L120
addsd %xmm1, %xmm5
jmp .L42
.L129:
movl -76(%rbp), %ebx
movq -128(%rbp), %r13
movq -136(%rbp), %r11
movq -160(%rbp), %rdx
movq -72(%rbp), %r8
movq -280(%rbp), %rax
addq %rax, %r8
movq -216(%rbp), %rax
leaq 8(%rax,%r10,4), %rsi
movq -144(%rbp), %rax
leaq (%rax,%r11), %r10
addq %rdx, %rax
movq %rax, -184(%rbp)
movq -168(%rbp), %rax
addq %rax, %r11
movl $0, -76(%rbp)
movl $0, %r9d
pxor %xmm6, %xmm6
movsd .LC1(%rip), %xmm11
leal -2(%rbx), %eax
movl %eax, -172(%rbp)
movl %r14d, -72(%rbp)
movq %rsi, %r14
jmp .L70
.L134:
movq %r12, %rax
cmpl $0, -72(%rbp)
jle .L130
.L53:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %r13, %rax
jne .L53
cmpl $2, %ebx
jle .L131
.L89:
movl %r9d, %eax
pxor %xmm7, %xmm7
movl $0, %esi
movl %ecx, -128(%rbp)
movl %r9d, -136(%rbp)
movq %r11, -160(%rbp)
movq -120(%rbp), %rcx
movl -172(%rbp), %r9d
jmp .L64
.L135:
movl -72(%rbp), %esi
testl %esi, %esi
jle .L50
imull %esi, %eax
cltq
movq -88(%rbp), %rsi
leaq (%rsi,%rax,8), %rdx
movl $0, %eax
.L57:
movsd (%rdx,%rax), %xmm1
movsd %xmm1, (%r12,%rax)
addq $8, %rax
cmpq %rax, %r15
jne .L57
movapd %xmm3, %xmm7
mulsd %xmm3, %xmm7
cmpl $0, -72(%rbp)
jg .L86
jmp .L50
.L130:
cmpl $2, %ebx
jg .L89
pxor %xmm7, %xmm7
jmp .L60
.L61:
addl $1, %esi
cmpl %r9d, %esi
je .L132
.L64:
cltd
idivl %ebx
movl %edx, %eax
movslq %edx, %r11
movsd (%rcx,%r11,8), %xmm2
comisd %xmm2, %xmm6
jbe .L61
subsd %xmm2, %xmm7
movl -72(%rbp), %r11d
testl %r11d, %r11d
jle .L61
imull %r11d, %edx
movslq %edx, %rdx
movq -88(%rbp), %r11
leaq (%r11,%rdx,8), %r11
movl $0, %edx
.L63:
movapd %xmm2, %xmm8
mulsd (%r11,%rdx), %xmm8
movsd (%r12,%rdx), %xmm1
subsd %xmm8, %xmm1
movsd %xmm1, (%r12,%rdx)
addq $8, %rdx
cmpq %rdx, %r15
jne .L63
jmp .L61
.L132:
movl -128(%rbp), %ecx
movl -136(%rbp), %r9d
movq -160(%rbp), %r11
.L60:
movsd .LC1(%rip), %xmm2
divsd %xmm7, %xmm2
cmpl $0, -72(%rbp)
jle .L50
.L88:
movq %r12, %rax
.L65:
movapd %xmm2, %xmm1
mulsd (%rax), %xmm1
movsd %xmm1, (%rax)
addq $8, %rax
cmpq %r13, %rax
jne .L65
comisd %xmm6, %xmm7
jbe .L55
movapd %xmm3, %xmm7
mulsd %xmm3, %xmm7
.L86:
movapd %xmm3, %xmm10
mulsd .LC2(%rip), %xmm10
movapd %xmm3, %xmm9
addsd %xmm3, %xmm9
movapd %xmm3, %xmm8
mulsd .LC3(%rip), %xmm8
movl -72(%rbp), %eax
imull %eax, %ecx
movslq %ecx, %rdx
salq $3, %rdx
movq -144(%rbp), %rax
leaq (%rax,%rdx), %rcx
movq -96(%rbp), %rax
addq %rax, %rdx
movl $0, %eax
movq %xmm0, %rsi
movsd %xmm4, -128(%rbp)
movsd %xmm14, -136(%rbp)
.L68:
movsd (%r11,%rax), %xmm1
movapd %xmm1, %xmm2
mulsd %xmm1, %xmm2
movapd %xmm1, %xmm0
mulsd %xmm15, %xmm0
addsd %xmm10, %xmm0
mulsd %xmm3, %xmm0
movapd %xmm2, %xmm4
mulsd %xmm13, %xmm4
addsd %xmm4, %xmm0
mulsd %xmm7, %xmm0
movapd %xmm1, %xmm4
addsd %xmm1, %xmm4
addsd %xmm3, %xmm4
mulsd %xmm9, %xmm4
movapd %xmm2, %xmm14
mulsd %xmm12, %xmm14
addsd %xmm4, %xmm14
movapd %xmm3, %xmm4
mulsd %xmm1, %xmm4
mulsd %xmm14, %xmm4
movapd %xmm2, %xmm14
mulsd %xmm15, %xmm14
mulsd %xmm14, %xmm2
addsd %xmm0, %xmm2
addsd %xmm4, %xmm2
divsd %xmm2, %xmm0
movsd (%r10,%rax), %xmm14
movapd %xmm11, %xmm4
subsd %xmm0, %xmm4
mulsd %xmm8, %xmm4
movapd %xmm14, %xmm2
subsd (%rcx,%rax), %xmm2
mulsd %xmm2, %xmm4
movsd (%r12,%rax), %xmm2
subsd %xmm14, %xmm2
mulsd %xmm0, %xmm1
mulsd %xmm1, %xmm2
addsd %xmm4, %xmm2
movapd %xmm2, %xmm0
addsd (%rdi,%rax), %xmm0
movsd %xmm0, (%rdi,%rax)
movsd (%rdx,%rax), %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %r15
jne .L68
movq %rsi, %xmm0
movsd -128(%rbp), %xmm4
movsd -136(%rbp), %xmm14
.L50:
addl $1, %r9d
addq $24, %r8
addq $12, %r14
cmpl %r9d, %ebx
je .L133
.L70:
movapd %xmm0, %xmm3
mulsd (%r8), %xmm3
movapd %xmm4, %xmm1
mulsd 8(%r8), %xmm1
addsd %xmm1, %xmm3
movapd %xmm14, %xmm1
mulsd 16(%r8), %xmm1
addsd %xmm1, %xmm3
comisd %xmm6, %xmm3
jbe .L50
addsd %xmm3, %xmm5
movl (%r14), %eax
leal -1(%rax), %ecx
movl -76(%rbp), %esi
movslq %esi, %rax
movq -104(%rbp), %rdx
movl %ecx, (%rdx,%rax,4)
movq -112(%rbp), %rdx
movsd %xmm3, (%rdx,%rax,8)
addl $1, %esi
movl %esi, -76(%rbp)
cmpl $3, %ebx
jne .L134
movslq %r9d, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %r9d, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %edx
movl %r9d, %eax
subl %edx, %eax
movslq %eax, %rdx
movq -120(%rbp), %rsi
comisd (%rsi,%rdx,8), %xmm6
ja .L135
.L55:
cmpl $0, -72(%rbp)
jle .L50
mulsd .LC3(%rip), %xmm3
movl -72(%rbp), %eax
imull %eax, %ecx
movq %rdi, %rax
movq %r10, %rdx
movslq %ecx, %rcx
movq -192(%rbp), %rsi
subq %rsi, %rcx
movq -184(%rbp), %rsi
.L69:
movsd (%rdx), %xmm1
subsd (%rdx,%rcx,8), %xmm1
mulsd %xmm3, %xmm1
movapd %xmm1, %xmm2
addsd (%rax), %xmm2
movsd %xmm2, (%rax)
movsd (%rax,%rcx,8), %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rax,%rcx,8)
addq $8, %rdx
addq $8, %rax
cmpq %rsi, %rdx
jne .L69
jmp .L50
.L133:
movl -72(%rbp), %r14d
testl %r14d, %r14d
jle .L71
.L85:
movl -80(%rbp), %edx
imull %r14d, %edx
movslq %edx, %rdx
salq $3, %rdx
movq -96(%rbp), %rax
leaq (%rax,%rdx), %rsi
movq -168(%rbp), %rax
leaq (%rax,%rdx), %rcx
movq -200(%rbp), %rax
addq %rax, %rdx
movl $0, %eax
.L72:
movapd %xmm5, %xmm2
addsd (%rcx,%rax,8), %xmm2
movsd (%rsi,%rax,8), %xmm1
divsd %xmm2, %xmm1
movsd %xmm1, (%rdx,%rax,8)
addq $1, %rax
cmpl %eax, %r14d
jg .L72
.L71:
movl -76(%rbp), %eax
testl %eax, %eax
jle .L73
movslq %eax, %rdi
movl -80(%rbp), %eax
imull %r14d, %eax
cltq
movq -200(%rbp), %rsi
leaq (%rsi,%rax,8), %r8
movl $0, %esi
movq -208(%rbp), %r11
movq %r15, -72(%rbp)
movq -96(%rbp), %r9
movq -104(%rbp), %r10
movq -112(%rbp), %r15
.L76:
movl (%r10,%rsi,4), %edx
testl %r14d, %r14d
jle .L74
movsd (%r15,%rsi,8), %xmm2
imull %r14d, %edx
movslq %edx, %rdx
leaq (%r9,%rdx,8), %rax
addq %r11, %rdx
leaq (%r9,%rdx,8), %rcx
movq %r8, %rdx
.L75:
movapd %xmm2, %xmm1
mulsd (%rdx), %xmm1
addsd (%rax), %xmm1
movsd %xmm1, (%rax)
addq $8, %rax
addq $8, %rdx
cmpq %rcx, %rax
jne .L75
.L74:
addq $1, %rsi
cmpq %rdi, %rsi
jne .L76
movq -72(%rbp), %r15
.L73:
addq $4, -152(%rbp)
movq -152(%rbp), %rax
movq -232(%rbp), %rdi
cmpq %rdi, %rax
je .L136
.L77:
movl -220(%rbp), %eax
notl %eax
movq -152(%rbp), %rsi
movl %eax, %edi
addl (%rsi), %edi
movl %edi, -80(%rbp)
testl %ebx, %ebx
jle .L39
movl -236(%rbp), %eax
addl %edi, %eax
movl -224(%rbp), %esi
imull %esi, %eax
leal (%rax,%rax,2), %eax
movslq %eax, %r10
leaq 0(,%r10,8), %rax
movq %rax, -72(%rbp)
movq -272(%rbp), %rsi
addq %rsi, %rax
movq -216(%rbp), %rsi
leaq 4(%rsi,%r10,4), %rsi
imull %r14d, %edi
movslq %edi, %rcx
movq %rcx, -192(%rbp)
leaq 0(,%rcx,8), %r11
movq -96(%rbp), %r8
leaq (%r8,%r11), %rdi
movq -208(%rbp), %rdx
addq %rcx, %rdx
salq $3, %rdx
leaq (%r8,%rdx), %r9
movq -120(%rbp), %rcx
movl $0, %r8d
pxor %xmm5, %xmm5
movapd %xmm5, %xmm6
movl %ebx, -76(%rbp)
movq %r13, -128(%rbp)
movq %r11, -136(%rbp)
movq %rdx, -160(%rbp)
movq -248(%rbp), %r11
jmp .L49
.L136:
movapd %xmm4, %xmm2
movapd %xmm0, %xmm4
movapd %xmm14, %xmm0
movq -448(%rbp), %r9
movl -176(%rbp), %r10d
addl %r10d, -308(%rbp)
movl -220(%rbp), %esi
movl -312(%rbp), %eax
addl %eax, %esi
imull %r14d, %esi
movl $0, %r8d
movl $0, %edi
movq -288(%rbp), %r11
movq -200(%rbp), %rbx
jmp .L78
.L81:
movslq %r8d, %rax
leaq (%rbx,%rax,8), %rcx
movslq %esi, %rax
leaq (%r11,%rax,8), %rdx
movl $0, %eax
.L79:
movsd (%rcx,%rax), %xmm1
movsd %xmm1, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %r15
jne .L79
.L82:
addl $1, %edi
addl %r14d, %r8d
addl %r14d, %esi
cmpl %edi, %r10d
je .L80
.L78:
testl %r14d, %r14d
jg .L81
jmp .L82
.L137:
movq -416(%rbp), %rcx
movl -420(%rbp), %ebx
movl -424(%rbp), %r9d
movl -428(%rbp), %r12d
movl %r14d, %r13d
movq %r15, %r14
movl -432(%rbp), %r15d
movq -440(%rbp), %r10
.L32:
addl $1, -296(%rbp)
movl -296(%rbp), %eax
addq $24, %rcx
addl %r15d, -320(%rbp)
addl %r9d, %ebx
addl 16(%rbp), %r12d
movl -324(%rbp), %esi
addl %esi, -312(%rbp)
cmpl %eax, -316(%rbp)
je .L3
.L84:
movsd (%rcx), %xmm4
movsd 8(%rcx), %xmm2
movsd 16(%rcx), %xmm0
testl %r15d, %r15d
jle .L32
movl %ebx, -328(%rbp)
movl -312(%rbp), %eax
movl %eax, -292(%rbp)
movl %r12d, -240(%rbp)
movslq -320(%rbp), %rdx
leaq (%r10,%rdx,4), %r11
movslq %r15d, %rax
addq %rdx, %rax
leaq (%r10,%rax,4), %rax
movq %rax, -336(%rbp)
movl $0, -308(%rbp)
movsd .LC5(%rip), %xmm13
movq %rcx, -416(%rbp)
movl %ebx, -420(%rbp)
movl %r9d, -424(%rbp)
movq %r11, %r9
movl %r12d, -428(%rbp)
movl %r15d, -432(%rbp)
movq %r14, %r15
movl %r13d, %r14d
movq %r10, -440(%rbp)
movq -408(%rbp), %r12
jmp .L83
.L33:
movl -176(%rbp), %edi
addl %edi, -308(%rbp)
.L80:
addq $4, %r9
movq -336(%rbp), %rax
cmpq %rax, %r9
je .L137
.L83:
movl (%r9), %eax
leal -1(%rax), %ecx
movslq %ecx, %rax
movq -352(%rbp), %rdi
movl (%rdi,%rax,4), %edi
movl %edi, -176(%rbp)
movq -360(%rbp), %rbx
movl (%rbx,%rax,4), %r13d
movq -368(%rbp), %rbx
movl (%rbx,%rax,4), %eax
movl %eax, -220(%rbp)
testl %edi, %edi
jle .L33
movl -324(%rbp), %esi
movl %esi, %edi
imull %ecx, %edi
movl %edi, -236(%rbp)
movl %edi, %ebx
imull %r14d, %ebx
movl -316(%rbp), %eax
imull %ecx, %eax
movl -296(%rbp), %edx
addl %edx, %eax
imull %esi, %eax
subl %edi, %eax
imull %r14d, %eax
movl %eax, -72(%rbp)
imull %r14d, %ecx
movslq %ecx, %rcx
salq $3, %rcx
movq -376(%rbp), %rax
leaq (%rax,%rcx), %r11
movq -384(%rbp), %rax
leaq (%rax,%rcx), %r10
movq -392(%rbp), %rax
addq %rax, %rcx
movl $0, %edi
movl $0, %eax
movl %r13d, -76(%rbp)
movl %edi, %r13d
movq %r9, -128(%rbp)
movq %r12, -136(%rbp)
movl %eax, %r12d
jmp .L34
.L39:
movl $0, -76(%rbp)
pxor %xmm5, %xmm5
testl %r14d, %r14d
jg .L85
jmp .L73
.L131:
movsd .LC1(%rip), %xmm2
pxor %xmm1, %xmm1
divsd %xmm1, %xmm2
movapd %xmm1, %xmm7
jmp .L88
.L3:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L138
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L138:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size CC_sweep, .-CC_sweep
.globl _Z32__device_stub__Z9cuda_testiiiiPdiiiiPd
.type _Z32__device_stub__Z9cuda_testiiiiPdiiiiPd, @function
_Z32__device_stub__Z9cuda_testiiiiPdiiiiPd:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L143
.L139:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L144
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L143:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq cuda_test(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L139
.L144:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9cuda_testiiiiPdiiiiPd, .-_Z32__device_stub__Z9cuda_testiiiiPdiiiiPd
.globl cuda_test
.type cuda_test, @function
cuda_test:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9cuda_testiiiiPdiiiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size cuda_test, .-cuda_test
.globl _Z76__device_stub__Z9GPU_sweepiiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_iiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_
.type _Z76__device_stub__Z9GPU_sweepiiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_iiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_, @function
_Z76__device_stub__Z9GPU_sweepiiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_iiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $440, %rsp
.cfi_def_cfa_offset 448
movl %edi, 156(%rsp)
movl %esi, 152(%rsp)
movl %edx, 148(%rsp)
movl %ecx, 144(%rsp)
movl %r8d, 140(%rsp)
movl %r9d, 136(%rsp)
movq 456(%rsp), %rax
movq %rax, 128(%rsp)
movq 464(%rsp), %rax
movq %rax, 120(%rsp)
movq 472(%rsp), %rax
movq %rax, 112(%rsp)
movq 480(%rsp), %rax
movq %rax, 104(%rsp)
movq 488(%rsp), %rax
movq %rax, 96(%rsp)
movq 496(%rsp), %rax
movq %rax, 88(%rsp)
movq 504(%rsp), %rax
movq %rax, 80(%rsp)
movq 512(%rsp), %rax
movq %rax, 72(%rsp)
movq 520(%rsp), %rax
movq %rax, 64(%rsp)
movq 528(%rsp), %rax
movq %rax, 56(%rsp)
movq 536(%rsp), %rax
movq %rax, 48(%rsp)
movq 544(%rsp), %rax
movq %rax, 40(%rsp)
movq 552(%rsp), %rax
movq %rax, 32(%rsp)
movq 560(%rsp), %rax
movq %rax, 24(%rsp)
movq 568(%rsp), %rax
movq %rax, 16(%rsp)
movq 576(%rsp), %rax
movq %rax, 8(%rsp)
movq 584(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 424(%rsp)
xorl %eax, %eax
leaq 156(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 148(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rax
movq %rax, 248(%rsp)
leaq 140(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 128(%rsp), %rax
movq %rax, 280(%rsp)
leaq 120(%rsp), %rax
movq %rax, 288(%rsp)
leaq 112(%rsp), %rax
movq %rax, 296(%rsp)
leaq 104(%rsp), %rax
movq %rax, 304(%rsp)
leaq 96(%rsp), %rax
movq %rax, 312(%rsp)
leaq 88(%rsp), %rax
movq %rax, 320(%rsp)
leaq 80(%rsp), %rax
movq %rax, 328(%rsp)
leaq 72(%rsp), %rax
movq %rax, 336(%rsp)
leaq 64(%rsp), %rax
movq %rax, 344(%rsp)
leaq 56(%rsp), %rax
movq %rax, 352(%rsp)
leaq 48(%rsp), %rax
movq %rax, 360(%rsp)
leaq 40(%rsp), %rax
movq %rax, 368(%rsp)
leaq 32(%rsp), %rax
movq %rax, 376(%rsp)
leaq 24(%rsp), %rax
movq %rax, 384(%rsp)
leaq 16(%rsp), %rax
movq %rax, 392(%rsp)
leaq 8(%rsp), %rax
movq %rax, 400(%rsp)
movq %rsp, %rax
movq %rax, 408(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
leaq 168(%rsp), %rcx
leaq 160(%rsp), %rdx
leaq 188(%rsp), %rsi
leaq 176(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L151
.L147:
movq 424(%rsp), %rax
subq %fs:40, %rax
jne .L152
addq $440, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L151:
.cfi_restore_state
pushq 168(%rsp)
.cfi_def_cfa_offset 456
pushq 168(%rsp)
.cfi_def_cfa_offset 464
leaq 240(%rsp), %r9
movq 204(%rsp), %rcx
movl 212(%rsp), %r8d
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
leaq GPU_sweep(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 448
jmp .L147
.L152:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z76__device_stub__Z9GPU_sweepiiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_iiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_, .-_Z76__device_stub__Z9GPU_sweepiiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_iiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_
.globl GPU_sweep
.type GPU_sweep, @function
GPU_sweep:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 152(%rsp)
.cfi_def_cfa_offset 24
pushq 152(%rsp)
.cfi_def_cfa_offset 32
pushq 152(%rsp)
.cfi_def_cfa_offset 40
pushq 152(%rsp)
.cfi_def_cfa_offset 48
pushq 152(%rsp)
.cfi_def_cfa_offset 56
pushq 152(%rsp)
.cfi_def_cfa_offset 64
pushq 152(%rsp)
.cfi_def_cfa_offset 72
pushq 152(%rsp)
.cfi_def_cfa_offset 80
pushq 152(%rsp)
.cfi_def_cfa_offset 88
pushq 152(%rsp)
.cfi_def_cfa_offset 96
pushq 152(%rsp)
.cfi_def_cfa_offset 104
pushq 152(%rsp)
.cfi_def_cfa_offset 112
pushq 152(%rsp)
.cfi_def_cfa_offset 120
pushq 152(%rsp)
.cfi_def_cfa_offset 128
pushq 152(%rsp)
.cfi_def_cfa_offset 136
pushq 152(%rsp)
.cfi_def_cfa_offset 144
pushq 152(%rsp)
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
call _Z76__device_stub__Z9GPU_sweepiiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_iiiiiiiPiPdS_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S_S0_S0_
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size GPU_sweep, .-GPU_sweep
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "GPU_sweep"
.LC8:
.string "cuda_test"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq GPU_sweep(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq cuda_test(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1074266112
.align 8
.LC3:
.long 0
.long 1071644672
.align 8
.LC4:
.long 0
.long 1074790400
.align 8
.LC5:
.long 1374389535
.long 1073553080
.align 8
.LC6:
.long 0
.long 1075314688
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define WARP_SIZE 32
extern "C"
{
__global__ void cuda_test(
int anglebatch,
int numgroups,
int ncornr,
int size_maxCorner,
double* psicbatch)
{
int Groups=192;
#define psicbatch(ig,b,c) psicbatch[(ig) + Groups * ((b) + size_maxCorner *(c) )]
printf("anglebatch = %d\n", anglebatch);
//printf("numgroups = %d\n", numgroups);
//printf("ncornr = %d\n", ncornr);
//printf("size_maxCorner = %d\n",size_maxCorner);
for (int angle=blockIdx.x; angle<anglebatch; angle+=gridDim.x) {
for(int c=0; c<size_maxCorner; c++) {
{
for (int g=threadIdx.x; g<numgroups; g+= blockDim.x) {
psicbatch(g,c,angle) = 1;
}
}
}
}
}
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* AngleOrder,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib )
{
// double omega[3];
int c,ig,i,icface,ifp,cez,k,ii;
// double Q[Groups * size_maxCorner];
// double src[Groups * size_maxCorner];
// double SigtVol[Groups * size_maxCorner];
// double afpm[size_maxcf];
// double psifp[Groups * size_maxcf];
// int ez_exit[size_maxcf];
// double coefpsic[size_maxcf];
// double tpsic[Groups * size_maxCorner];
// double psi_opp[Groups];
double area_opp,area_inv,sumArea;
double r_psifp;
double psi_opp,tpsic;
double omega0, omega1, omega2;
__shared__ double *Q, *src, *volume, *coefpsic, *afpm, *psifp;
__shared__ int *ez_exit;
__shared__ double sm_agg[625];
int offset = 0;
Q = &(sm_agg[0]);
offset += size_maxCorner * WARP_SIZE;
src = &(sm_agg[offset]);
offset += size_maxCorner * WARP_SIZE;
volume = &(sm_agg[offset]);
offset += size_maxCorner;
coefpsic = &(sm_agg[offset]);
offset += size_maxcf;
afpm = &(sm_agg[offset]);
offset += size_maxcf;
psifp = &(sm_agg[offset]);
offset += size_maxcf * WARP_SIZE;
//note ez_exit has integer type
ez_exit = (int*) &(sm_agg[offset]);
const double fouralpha = 1.82;
// const double fouralpha4 = 5.82;
#define soa_omega(a,b) soa_omega[a + 3 * b]
// #define tpsic(ig,c) tpsic[ (ig) + Groups * (c)]
#define EB_ListExit(a,ia) EB_ListExit[ a + 2 * (ia) ]
#define soa_A_fp(a,icface,c,zone) soa_A_fp[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_A_ez(a,icface,c,zone) soa_A_ez[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_Connect(a,icface,c,zone) soa_Connect[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define psifp(ig,jf) psifp[(ig) + Groups * (jf)]
#define psib(ig,b,c) psib[(ig) + Groups * ((b) + nbelem * (c) )]
#define psic(ig,b,c) psic[(ig) + Groups * ((b) + size_maxCorner *(c) )]
#define Q(ig,c) Q[(ig) + Groups * (c)]
#define src(ig,c) src[(ig) + Groups * (c)]
// #define SigtVol(ig,c) SigtVol[(ig) + Groups * (c)]
#define soa_Sigt(ig,zone) soa_Sigt[(ig) + Groups * (zone)]
#define soa_Volume(c,zone) soa_Volume[(ig) + Groups * (zone)]
#define soa_SigtInv(ig,zone) soa_SigtInv[(ig) + Groups * (zone)]
#define soa_STotal(ig,c,zone) soa_STotal[ig + Groups * ( c + size_maxCorner * (zone) )]
#define soa_STime(ig,c,Angle,zone) soa_STime[ig + Groups * ( c + size_maxCorner * ( Angle + nAngle * (zone) ) )]
#define nextZ(a,b) nextZ[ (a) + nzones * (b) ]
#define next(a,b) next[ (a) + (ncornr+1) * (b) ]
// for(int Angle=0;Angle<nAngle;Angle++)
int Angle = blockIdx.y;
ig = threadIdx.x;
// if(ig==0) printf("my offset=%d\n",offset);
// if(ig==0)
// {
// printf("psic=%x\n",psic);
// printf("nextZ=%x\n",psic);
// printf("next=%x\n",psic);
// printf("psib=%x\n",psic);
// }
{
omega0 = soa_omega(0,Angle);
omega1 = soa_omega(1,Angle);
omega2 = soa_omega(2,Angle);
int ndone = 0;
for(ii=0;ii<nzones;ii++)
{
int zone = nextZ(ii,Angle) - 1;
int nCorner = soa_nCorner[zone];
int nCFaces = soa_nCFaces[zone];
int c0 = soa_c0[zone] ;
double Sigt = soa_Sigt(ig,zone);
for(c=0;c<nCorner;c++)
{
double source = soa_STotal(ig,c,zone) + soa_STime(ig,c,Angle,zone);
Q(ig,c) = soa_SigtInv(ig,zone)*source ;
src(ig,c) = soa_Volume(c,zone) *source;
//SigtVol(ig,c) = soa_Sigt(ig,zone)*soa_Volume(c,zone);
volume[c] = soa_Volume(c,zone);
}
for(i=0;i<nCorner;i++)
{
int ic = next(ndone+i,Angle);
c = ic - c0 - 1;
sumArea = 0.0;
for(icface=0;icface<nCFaces;icface++)
{
afpm[icface] = omega0*soa_A_fp(0,icface,c,zone) +
omega1*soa_A_fp(1,icface,c,zone) +
omega2*soa_A_fp(2,icface,c,zone);
int icfp = soa_Connect(1,icface,c,zone) - 1;
int ib = soa_Connect(2,icface,c,zone) - 1;
if ( afpm[icface] >= 0.0 )
{
sumArea = sumArea + afpm[icface];
}
else
{
if (icfp == 0)
{
// psifp(ig,icface) = psib(ig,ib,Angle);
r_psifp = psib(ig,ib,Angle);
// r_psifp = 0.3;
}
else
{
// psifp(ig,icface) = psic(ig,icfp,Angle);
r_psifp = psic(ig,icfp,Angle);
// r_psifp = 0.7;
}
src(ig,c) -= afpm[icface]*r_psifp;
psifp(ig,icface) = r_psifp;
}
}
int nxez = 0;
for(icface=0;icface<nCFaces;icface++)
{
double aez = omega0*soa_A_ez(0,icface,c,zone) + omega1*soa_A_ez(1,icface,c,zone) + omega2*soa_A_ez(2,icface,c,zone) ;
if (aez > 0.0 )
{
sumArea = sumArea + aez;
area_opp = .0;
cez = soa_Connect(2,icface,c,zone) - 1;
ez_exit[nxez] = cez;
coefpsic[nxez] = aez;
nxez = nxez + 1;
if (nCFaces == 3)
{
ifp = (icface+1)%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = -afpm[ifp];
psi_opp = psifp(ig,ifp);
}
}
else
{
ifp = icface;
area_opp = 0.0;
psi_opp = 0.0;
for(k=0;k<nCFaces-2;k++)
{
ifp = ifp%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = area_opp - afpm[ifp];
psi_opp = psi_opp - afpm[ifp]*psifp(ig,ifp);
}
}
area_inv = 1.0/area_opp;
psi_opp = psi_opp*area_inv;
}
if (area_opp > 0.0) {
double aez2 = aez*aez;
{
double sigv = Sigt*volume[c];
double sigv2 = sigv*sigv;
double gnum = aez2*( fouralpha*sigv2 + aez*(4.0*sigv + 3.0*aez) );
double gtau = gnum/( gnum + 4.0*sigv2*sigv2 + aez*sigv*(6.0*sigv2 + 2.0*aez*(2.0*sigv + aez)) ) ;
double sez = gtau*sigv*( psi_opp - Q(ig,c) ) + 0.5*aez*(1.0 - gtau)*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
else
{
double sez = 0.5*aez*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
}
// printf("ckim angle,zone,corner,aez_cnt %d,%d,%d,%d\n",Angle,zone,c,aez_cnt);
tpsic = src(ig,c)/(sumArea + Sigt*volume[c]);
for(icface=0;icface<nxez;icface++)
{
int cez = ez_exit[icface];
src(ig,cez) = src(ig,cez) + coefpsic[icface]*tpsic;
}
//hope that ther is no self referencing
psic(ig,c0+c,Angle) = tpsic;
}
ndone = ndone + nCorner;
}
}
// ExitBdy => getExitList(QuadSet, Angle)
// for(i=0;i<EB_nExit;i++)
// {
// int ib = EB_ListExit(1,i);
// int ic = EB_ListExit(2,i);
// for(ig=0;ig<Groups;ig++)
// psib(ig,ib) = psic(ig,ic);
// }
}
void CC_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib )
{
double omega[3];
int c,ig,i,icface,ifp,cez,k,ii;
double Q[Groups * size_maxCorner];
double src[Groups * size_maxCorner];
double SigtVol[Groups * size_maxCorner];
double afpm[size_maxcf];
double psifp[Groups * size_maxcf];
int ez_exit[size_maxcf];
double coefpsic[size_maxcf];
double tpsic[Groups * size_maxCorner];
double psi_opp[Groups];
double area_opp,area_inv,sumArea;
const double fouralpha = 1.82;
// const double fouralpha4 = 5.82;
#define soa_omega(a,b) soa_omega[a + 3 * b]
#define tpsic(ig,c) tpsic[ (ig) + Groups * (c)]
#define EB_ListExit(a,ia) EB_ListExit[ a + 2 * (ia) ]
#define soa_A_fp(a,icface,c,zone) soa_A_fp[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_A_ez(a,icface,c,zone) soa_A_ez[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_Connect(a,icface,c,zone) soa_Connect[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define psifp(ig,jf) psifp[(ig) + Groups * (jf)]
#define psib(ig,b,c) psib[(ig) + Groups * ((b) + nbelem * (c) )]
#define psic(ig,b,c) psic[(ig) + Groups * ((b) + size_maxCorner *(c) )]
#define Q(ig,c) Q[(ig) + Groups * (c)]
#define src(ig,c) src[(ig) + Groups * (c)]
#define SigtVol(ig,c) SigtVol[(ig) + Groups * (c)]
#define soa_Sigt(ig,zone) soa_Sigt[(ig) + Groups * (zone)]
#define soa_Volume(c,zone) soa_Volume[(ig) + Groups * (zone)]
#define soa_SigtInv(ig,zone) soa_SigtInv[(ig) + Groups * (zone)]
#define soa_STotal(ig,c,zone) soa_STotal[ig + Groups * ( c + size_maxCorner * (zone) )]
#define soa_STime(ig,c,Angle,zone) soa_STime[ig + Groups * ( c + size_maxCorner * ( Angle + nAngle * (zone) ) )]
#define nextZ(a,b) nextZ[ (a) + nzones * (b) ]
#define next(a,b) next[ (a) + (ncornr+1) * (b) ]
for(int Angle=0;Angle<nAngle;Angle++)
{
omega[0] = soa_omega(0,Angle);
omega[1] = soa_omega(1,Angle);
omega[2] = soa_omega(2,Angle);
int ndone = 0;
for(ii=0;ii<nzones;ii++)
{
int zone = nextZ(ii,Angle) - 1;
int nCorner = soa_nCorner[zone];
int nCFaces = soa_nCFaces[zone];
int c0 = soa_c0[zone] ;
for(c=0;c<nCorner;c++)
{
for(ig=0;ig<Groups;ig++)
{
double source = soa_STotal(ig,c,zone) + soa_STime(ig,c,Angle,zone);
Q(ig,c) = soa_SigtInv(ig,zone)*source ;
src(ig,c) = soa_Volume(c,zone) *source;
SigtVol(ig,c) = soa_Sigt(ig,zone)*soa_Volume(c,zone);
}
}
for(i=0;i<nCorner;i++)
{
int ic = next(ndone+i,Angle);
c = ic - c0 - 1;
sumArea = 0.0;
for(icface=0;icface<nCFaces;icface++)
{
afpm[icface] = omega[0]*soa_A_fp(0,icface,c,zone) +
omega[1]*soa_A_fp(1,icface,c,zone) +
omega[2]*soa_A_fp(2,icface,c,zone);
int icfp = soa_Connect(1,icface,c,zone) - 1;
int ib = soa_Connect(2,icface,c,zone) - 1;
if ( afpm[icface] >= 0.0 )
{
sumArea = sumArea + afpm[icface];
}
else
{
if (icfp == 0)
{
for(ig=0;ig<Groups;ig++) psifp(ig,icface) = psib(ig,ib,Angle);
}
else
{
for(ig=0;ig<Groups;ig++) psifp(ig,icface) = psic(ig,icfp,Angle);
}
for(ig=0;ig<Groups;ig++) src(ig,c) = src(ig,c) - afpm[icface]*psifp(ig,icface);
}
}
int nxez = 0;
for(icface=0;icface<nCFaces;icface++)
{
double aez = omega[0]*soa_A_ez(0,icface,c,zone) + omega[1]*soa_A_ez(1,icface,c,zone) + omega[2]*soa_A_ez(2,icface,c,zone) ;
if (aez > 0.0 )
{
sumArea = sumArea + aez;
area_opp = .0;
cez = soa_Connect(2,icface,c,zone) - 1;
ez_exit[nxez] = cez;
coefpsic[nxez] = aez;
nxez = nxez + 1;
if (nCFaces == 3)
{
ifp = icface%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = -afpm[ifp];
for(ig=0;ig<Groups;ig++) psi_opp[ig] = psifp(ig,ifp);
}
}
else
{
ifp = icface;
area_opp = 0.0;
for(ig=0;ig<Groups;ig++) psi_opp[ig] = 0.0;
for(k=0;k<nCFaces-2;k++)
{
ifp = ifp%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = area_opp - afpm[ifp];
for(ig=0;ig<Groups;ig++) psi_opp[ig] = psi_opp[ig] - afpm[ifp]*psifp(ig,ifp);
}
}
area_inv = 1.0/area_opp;
for(ig=0;ig<Groups;ig++)
psi_opp[ig] = psi_opp[ig]*area_inv;
}
if (area_opp > 0.0) {
double aez2 = aez*aez;
for(ig=0;ig<Groups;ig++)
{
double sigv = SigtVol(ig,c);
double sigv2 = sigv*sigv;
double gnum = aez2*( fouralpha*sigv2 + aez*(4.0*sigv + 3.0*aez) );
double gtau = gnum/( gnum + 4.0*sigv2*sigv2 + aez*sigv*(6.0*sigv2 + 2.0*aez*(2.0*sigv + aez)) ) ;
double sez = gtau*sigv*( psi_opp[ig] - Q(ig,c) ) + 0.5*aez*(1.0 - gtau)*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
else
{
for(ig=0;ig<Groups;ig++)
{
double sez = 0.5*aez*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
}
}
// printf("ckim angle,zone,corner,aez_cnt %d,%d,%d,%d\n",Angle,zone,c,aez_cnt);
for(ig=0;ig<Groups;ig++)
tpsic(ig,c) = src(ig,c)/(sumArea + SigtVol(ig,c));
for(icface=0;icface<nxez;icface++)
{
int cez = ez_exit[icface];
for(ig=0;ig<Groups;ig++)
src(ig,cez) = src(ig,cez) + coefpsic[icface]*tpsic(ig,c);
}
}
ndone = ndone + nCorner;
for(c=0;c<nCorner;c++)
{
for(ig=0;ig<Groups;ig++)
psic(ig,c0+c,Angle) = tpsic(ig,c);
}
}
ndone++;
}
// ExitBdy => getExitList(QuadSet, Angle)
// for(i=0;i<EB_nExit;i++)
// {
// int ib = EB_ListExit(1,i);
// int ic = EB_ListExit(2,i);
// for(ig=0;ig<Groups;ig++)
// psib(ig,ib) = psic(ig,ic);
// }
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define WARP_SIZE 32
extern "C"
{
__global__ void cuda_test(
int anglebatch,
int numgroups,
int ncornr,
int size_maxCorner,
double* psicbatch)
{
int Groups=192;
#define psicbatch(ig,b,c) psicbatch[(ig) + Groups * ((b) + size_maxCorner *(c) )]
printf("anglebatch = %d\n", anglebatch);
//printf("numgroups = %d\n", numgroups);
//printf("ncornr = %d\n", ncornr);
//printf("size_maxCorner = %d\n",size_maxCorner);
for (int angle=blockIdx.x; angle<anglebatch; angle+=gridDim.x) {
for(int c=0; c<size_maxCorner; c++) {
{
for (int g=threadIdx.x; g<numgroups; g+= blockDim.x) {
psicbatch(g,c,angle) = 1;
}
}
}
}
}
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* AngleOrder,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib )
{
// double omega[3];
int c,ig,i,icface,ifp,cez,k,ii;
// double Q[Groups * size_maxCorner];
// double src[Groups * size_maxCorner];
// double SigtVol[Groups * size_maxCorner];
// double afpm[size_maxcf];
// double psifp[Groups * size_maxcf];
// int ez_exit[size_maxcf];
// double coefpsic[size_maxcf];
// double tpsic[Groups * size_maxCorner];
// double psi_opp[Groups];
double area_opp,area_inv,sumArea;
double r_psifp;
double psi_opp,tpsic;
double omega0, omega1, omega2;
__shared__ double *Q, *src, *volume, *coefpsic, *afpm, *psifp;
__shared__ int *ez_exit;
__shared__ double sm_agg[625];
int offset = 0;
Q = &(sm_agg[0]);
offset += size_maxCorner * WARP_SIZE;
src = &(sm_agg[offset]);
offset += size_maxCorner * WARP_SIZE;
volume = &(sm_agg[offset]);
offset += size_maxCorner;
coefpsic = &(sm_agg[offset]);
offset += size_maxcf;
afpm = &(sm_agg[offset]);
offset += size_maxcf;
psifp = &(sm_agg[offset]);
offset += size_maxcf * WARP_SIZE;
//note ez_exit has integer type
ez_exit = (int*) &(sm_agg[offset]);
const double fouralpha = 1.82;
// const double fouralpha4 = 5.82;
#define soa_omega(a,b) soa_omega[a + 3 * b]
// #define tpsic(ig,c) tpsic[ (ig) + Groups * (c)]
#define EB_ListExit(a,ia) EB_ListExit[ a + 2 * (ia) ]
#define soa_A_fp(a,icface,c,zone) soa_A_fp[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_A_ez(a,icface,c,zone) soa_A_ez[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_Connect(a,icface,c,zone) soa_Connect[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define psifp(ig,jf) psifp[(ig) + Groups * (jf)]
#define psib(ig,b,c) psib[(ig) + Groups * ((b) + nbelem * (c) )]
#define psic(ig,b,c) psic[(ig) + Groups * ((b) + size_maxCorner *(c) )]
#define Q(ig,c) Q[(ig) + Groups * (c)]
#define src(ig,c) src[(ig) + Groups * (c)]
// #define SigtVol(ig,c) SigtVol[(ig) + Groups * (c)]
#define soa_Sigt(ig,zone) soa_Sigt[(ig) + Groups * (zone)]
#define soa_Volume(c,zone) soa_Volume[(ig) + Groups * (zone)]
#define soa_SigtInv(ig,zone) soa_SigtInv[(ig) + Groups * (zone)]
#define soa_STotal(ig,c,zone) soa_STotal[ig + Groups * ( c + size_maxCorner * (zone) )]
#define soa_STime(ig,c,Angle,zone) soa_STime[ig + Groups * ( c + size_maxCorner * ( Angle + nAngle * (zone) ) )]
#define nextZ(a,b) nextZ[ (a) + nzones * (b) ]
#define next(a,b) next[ (a) + (ncornr+1) * (b) ]
// for(int Angle=0;Angle<nAngle;Angle++)
int Angle = blockIdx.y;
ig = threadIdx.x;
// if(ig==0) printf("my offset=%d\n",offset);
// if(ig==0)
// {
// printf("psic=%x\n",psic);
// printf("nextZ=%x\n",psic);
// printf("next=%x\n",psic);
// printf("psib=%x\n",psic);
// }
{
omega0 = soa_omega(0,Angle);
omega1 = soa_omega(1,Angle);
omega2 = soa_omega(2,Angle);
int ndone = 0;
for(ii=0;ii<nzones;ii++)
{
int zone = nextZ(ii,Angle) - 1;
int nCorner = soa_nCorner[zone];
int nCFaces = soa_nCFaces[zone];
int c0 = soa_c0[zone] ;
double Sigt = soa_Sigt(ig,zone);
for(c=0;c<nCorner;c++)
{
double source = soa_STotal(ig,c,zone) + soa_STime(ig,c,Angle,zone);
Q(ig,c) = soa_SigtInv(ig,zone)*source ;
src(ig,c) = soa_Volume(c,zone) *source;
//SigtVol(ig,c) = soa_Sigt(ig,zone)*soa_Volume(c,zone);
volume[c] = soa_Volume(c,zone);
}
for(i=0;i<nCorner;i++)
{
int ic = next(ndone+i,Angle);
c = ic - c0 - 1;
sumArea = 0.0;
for(icface=0;icface<nCFaces;icface++)
{
afpm[icface] = omega0*soa_A_fp(0,icface,c,zone) +
omega1*soa_A_fp(1,icface,c,zone) +
omega2*soa_A_fp(2,icface,c,zone);
int icfp = soa_Connect(1,icface,c,zone) - 1;
int ib = soa_Connect(2,icface,c,zone) - 1;
if ( afpm[icface] >= 0.0 )
{
sumArea = sumArea + afpm[icface];
}
else
{
if (icfp == 0)
{
// psifp(ig,icface) = psib(ig,ib,Angle);
r_psifp = psib(ig,ib,Angle);
// r_psifp = 0.3;
}
else
{
// psifp(ig,icface) = psic(ig,icfp,Angle);
r_psifp = psic(ig,icfp,Angle);
// r_psifp = 0.7;
}
src(ig,c) -= afpm[icface]*r_psifp;
psifp(ig,icface) = r_psifp;
}
}
int nxez = 0;
for(icface=0;icface<nCFaces;icface++)
{
double aez = omega0*soa_A_ez(0,icface,c,zone) + omega1*soa_A_ez(1,icface,c,zone) + omega2*soa_A_ez(2,icface,c,zone) ;
if (aez > 0.0 )
{
sumArea = sumArea + aez;
area_opp = .0;
cez = soa_Connect(2,icface,c,zone) - 1;
ez_exit[nxez] = cez;
coefpsic[nxez] = aez;
nxez = nxez + 1;
if (nCFaces == 3)
{
ifp = (icface+1)%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = -afpm[ifp];
psi_opp = psifp(ig,ifp);
}
}
else
{
ifp = icface;
area_opp = 0.0;
psi_opp = 0.0;
for(k=0;k<nCFaces-2;k++)
{
ifp = ifp%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = area_opp - afpm[ifp];
psi_opp = psi_opp - afpm[ifp]*psifp(ig,ifp);
}
}
area_inv = 1.0/area_opp;
psi_opp = psi_opp*area_inv;
}
if (area_opp > 0.0) {
double aez2 = aez*aez;
{
double sigv = Sigt*volume[c];
double sigv2 = sigv*sigv;
double gnum = aez2*( fouralpha*sigv2 + aez*(4.0*sigv + 3.0*aez) );
double gtau = gnum/( gnum + 4.0*sigv2*sigv2 + aez*sigv*(6.0*sigv2 + 2.0*aez*(2.0*sigv + aez)) ) ;
double sez = gtau*sigv*( psi_opp - Q(ig,c) ) + 0.5*aez*(1.0 - gtau)*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
else
{
double sez = 0.5*aez*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
}
// printf("ckim angle,zone,corner,aez_cnt %d,%d,%d,%d\n",Angle,zone,c,aez_cnt);
tpsic = src(ig,c)/(sumArea + Sigt*volume[c]);
for(icface=0;icface<nxez;icface++)
{
int cez = ez_exit[icface];
src(ig,cez) = src(ig,cez) + coefpsic[icface]*tpsic;
}
//hope that ther is no self referencing
psic(ig,c0+c,Angle) = tpsic;
}
ndone = ndone + nCorner;
}
}
// ExitBdy => getExitList(QuadSet, Angle)
// for(i=0;i<EB_nExit;i++)
// {
// int ib = EB_ListExit(1,i);
// int ic = EB_ListExit(2,i);
// for(ig=0;ig<Groups;ig++)
// psib(ig,ib) = psic(ig,ic);
// }
}
void CC_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib )
{
double omega[3];
int c,ig,i,icface,ifp,cez,k,ii;
double Q[Groups * size_maxCorner];
double src[Groups * size_maxCorner];
double SigtVol[Groups * size_maxCorner];
double afpm[size_maxcf];
double psifp[Groups * size_maxcf];
int ez_exit[size_maxcf];
double coefpsic[size_maxcf];
double tpsic[Groups * size_maxCorner];
double psi_opp[Groups];
double area_opp,area_inv,sumArea;
const double fouralpha = 1.82;
// const double fouralpha4 = 5.82;
#define soa_omega(a,b) soa_omega[a + 3 * b]
#define tpsic(ig,c) tpsic[ (ig) + Groups * (c)]
#define EB_ListExit(a,ia) EB_ListExit[ a + 2 * (ia) ]
#define soa_A_fp(a,icface,c,zone) soa_A_fp[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_A_ez(a,icface,c,zone) soa_A_ez[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define soa_Connect(a,icface,c,zone) soa_Connect[ a + 3 * ( icface + size_maxcf * ( c + size_maxCorner * (zone) ) )]
#define psifp(ig,jf) psifp[(ig) + Groups * (jf)]
#define psib(ig,b,c) psib[(ig) + Groups * ((b) + nbelem * (c) )]
#define psic(ig,b,c) psic[(ig) + Groups * ((b) + size_maxCorner *(c) )]
#define Q(ig,c) Q[(ig) + Groups * (c)]
#define src(ig,c) src[(ig) + Groups * (c)]
#define SigtVol(ig,c) SigtVol[(ig) + Groups * (c)]
#define soa_Sigt(ig,zone) soa_Sigt[(ig) + Groups * (zone)]
#define soa_Volume(c,zone) soa_Volume[(ig) + Groups * (zone)]
#define soa_SigtInv(ig,zone) soa_SigtInv[(ig) + Groups * (zone)]
#define soa_STotal(ig,c,zone) soa_STotal[ig + Groups * ( c + size_maxCorner * (zone) )]
#define soa_STime(ig,c,Angle,zone) soa_STime[ig + Groups * ( c + size_maxCorner * ( Angle + nAngle * (zone) ) )]
#define nextZ(a,b) nextZ[ (a) + nzones * (b) ]
#define next(a,b) next[ (a) + (ncornr+1) * (b) ]
for(int Angle=0;Angle<nAngle;Angle++)
{
omega[0] = soa_omega(0,Angle);
omega[1] = soa_omega(1,Angle);
omega[2] = soa_omega(2,Angle);
int ndone = 0;
for(ii=0;ii<nzones;ii++)
{
int zone = nextZ(ii,Angle) - 1;
int nCorner = soa_nCorner[zone];
int nCFaces = soa_nCFaces[zone];
int c0 = soa_c0[zone] ;
for(c=0;c<nCorner;c++)
{
for(ig=0;ig<Groups;ig++)
{
double source = soa_STotal(ig,c,zone) + soa_STime(ig,c,Angle,zone);
Q(ig,c) = soa_SigtInv(ig,zone)*source ;
src(ig,c) = soa_Volume(c,zone) *source;
SigtVol(ig,c) = soa_Sigt(ig,zone)*soa_Volume(c,zone);
}
}
for(i=0;i<nCorner;i++)
{
int ic = next(ndone+i,Angle);
c = ic - c0 - 1;
sumArea = 0.0;
for(icface=0;icface<nCFaces;icface++)
{
afpm[icface] = omega[0]*soa_A_fp(0,icface,c,zone) +
omega[1]*soa_A_fp(1,icface,c,zone) +
omega[2]*soa_A_fp(2,icface,c,zone);
int icfp = soa_Connect(1,icface,c,zone) - 1;
int ib = soa_Connect(2,icface,c,zone) - 1;
if ( afpm[icface] >= 0.0 )
{
sumArea = sumArea + afpm[icface];
}
else
{
if (icfp == 0)
{
for(ig=0;ig<Groups;ig++) psifp(ig,icface) = psib(ig,ib,Angle);
}
else
{
for(ig=0;ig<Groups;ig++) psifp(ig,icface) = psic(ig,icfp,Angle);
}
for(ig=0;ig<Groups;ig++) src(ig,c) = src(ig,c) - afpm[icface]*psifp(ig,icface);
}
}
int nxez = 0;
for(icface=0;icface<nCFaces;icface++)
{
double aez = omega[0]*soa_A_ez(0,icface,c,zone) + omega[1]*soa_A_ez(1,icface,c,zone) + omega[2]*soa_A_ez(2,icface,c,zone) ;
if (aez > 0.0 )
{
sumArea = sumArea + aez;
area_opp = .0;
cez = soa_Connect(2,icface,c,zone) - 1;
ez_exit[nxez] = cez;
coefpsic[nxez] = aez;
nxez = nxez + 1;
if (nCFaces == 3)
{
ifp = icface%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = -afpm[ifp];
for(ig=0;ig<Groups;ig++) psi_opp[ig] = psifp(ig,ifp);
}
}
else
{
ifp = icface;
area_opp = 0.0;
for(ig=0;ig<Groups;ig++) psi_opp[ig] = 0.0;
for(k=0;k<nCFaces-2;k++)
{
ifp = ifp%nCFaces;
if ( afpm[ifp] < 0.0 )
{
area_opp = area_opp - afpm[ifp];
for(ig=0;ig<Groups;ig++) psi_opp[ig] = psi_opp[ig] - afpm[ifp]*psifp(ig,ifp);
}
}
area_inv = 1.0/area_opp;
for(ig=0;ig<Groups;ig++)
psi_opp[ig] = psi_opp[ig]*area_inv;
}
if (area_opp > 0.0) {
double aez2 = aez*aez;
for(ig=0;ig<Groups;ig++)
{
double sigv = SigtVol(ig,c);
double sigv2 = sigv*sigv;
double gnum = aez2*( fouralpha*sigv2 + aez*(4.0*sigv + 3.0*aez) );
double gtau = gnum/( gnum + 4.0*sigv2*sigv2 + aez*sigv*(6.0*sigv2 + 2.0*aez*(2.0*sigv + aez)) ) ;
double sez = gtau*sigv*( psi_opp[ig] - Q(ig,c) ) + 0.5*aez*(1.0 - gtau)*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
else
{
for(ig=0;ig<Groups;ig++)
{
double sez = 0.5*aez*( Q(ig,c) - Q(ig,cez) );
src(ig,c) = src(ig,c) + sez;
src(ig,cez) = src(ig,cez) - sez;
}
}
}
}
// printf("ckim angle,zone,corner,aez_cnt %d,%d,%d,%d\n",Angle,zone,c,aez_cnt);
for(ig=0;ig<Groups;ig++)
tpsic(ig,c) = src(ig,c)/(sumArea + SigtVol(ig,c));
for(icface=0;icface<nxez;icface++)
{
int cez = ez_exit[icface];
for(ig=0;ig<Groups;ig++)
src(ig,cez) = src(ig,cez) + coefpsic[icface]*tpsic(ig,c);
}
}
ndone = ndone + nCorner;
for(c=0;c<nCorner;c++)
{
for(ig=0;ig<Groups;ig++)
psic(ig,c0+c,Angle) = tpsic(ig,c);
}
}
ndone++;
}
// ExitBdy => getExitList(QuadSet, Angle)
// for(i=0;i<EB_nExit;i++)
// {
// int ib = EB_ListExit(1,i);
// int ic = EB_ListExit(2,i);
// for(ig=0;ig<Groups;ig++)
// psib(ig,ib) = psic(ig,ic);
// }
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
//Compile with nvcc -arch sm_20 -lineinfo -Xcompiler -Wall -O4 -g sample_base.cu -o hello
//Check cuda call for errors, Call after each cuda call
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
//This is the kernel that runs on the GPU
__global__ void hello_from_GPU()
{
//printf("Hello world from the device! block=%d, thread=%d\n", blockIdx.x, threadIdx.x);
}
//This is the main function
int main(int argc, char **argv)
{
double **hostMatrix, *hostGpuOutput;
double *deviceMatrix, *deviceMatrixTransposed;
int dim_x = 1, dim_y = 1;
#ifdef DEBUG
int max_withd = 3;
#endif
if ( argc != 3)
{
printf("Insuffisend arguments exiting\n");
exit(EXIT_FAILURE);
}
else
{
dim_x = atoi(argv[1]);
dim_y = atoi(argv[2]);
}
hostMatrix = (double**)malloc(sizeof(double*)*dim_x);
if ( hostMatrix == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n");
exit(EXIT_FAILURE);
}
for ( int i = 0; i < dim_y; i++){
hostMatrix[i] = (double*)malloc( sizeof(double) * dim_y);
if (hostMatrix[i] == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n" );
exit(EXIT_FAILURE);
}
for ( int j = 0; j < dim_y; j++) {
hostMatrix[i][j] = j + (i * dim_x);
}
}
deviceMatrix = NULL;
cudaMalloc((void**)&deviceMatrix, sizeof(double)*dim_x*dim_y);
deviceMatrixTransposed = NULL;
cudaMalloc((void**)&deviceMatrixTransposed, sizeof(double)*dim_x*dim_y);
//Kernel invocation with <<< # of blocks , # of threads per block>>>(args...)
hello_from_GPU<<<10,10>>>();
cudaCheckError();
cudaDeviceSynchronize();
//Reset the GPU
cudaDeviceReset();
return 0;
}
// Yey | code for sm_80
Function : _Z14hello_from_GPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
//Compile with nvcc -arch sm_20 -lineinfo -Xcompiler -Wall -O4 -g sample_base.cu -o hello
//Check cuda call for errors, Call after each cuda call
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
//This is the kernel that runs on the GPU
__global__ void hello_from_GPU()
{
//printf("Hello world from the device! block=%d, thread=%d\n", blockIdx.x, threadIdx.x);
}
//This is the main function
int main(int argc, char **argv)
{
double **hostMatrix, *hostGpuOutput;
double *deviceMatrix, *deviceMatrixTransposed;
int dim_x = 1, dim_y = 1;
#ifdef DEBUG
int max_withd = 3;
#endif
if ( argc != 3)
{
printf("Insuffisend arguments exiting\n");
exit(EXIT_FAILURE);
}
else
{
dim_x = atoi(argv[1]);
dim_y = atoi(argv[2]);
}
hostMatrix = (double**)malloc(sizeof(double*)*dim_x);
if ( hostMatrix == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n");
exit(EXIT_FAILURE);
}
for ( int i = 0; i < dim_y; i++){
hostMatrix[i] = (double*)malloc( sizeof(double) * dim_y);
if (hostMatrix[i] == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n" );
exit(EXIT_FAILURE);
}
for ( int j = 0; j < dim_y; j++) {
hostMatrix[i][j] = j + (i * dim_x);
}
}
deviceMatrix = NULL;
cudaMalloc((void**)&deviceMatrix, sizeof(double)*dim_x*dim_y);
deviceMatrixTransposed = NULL;
cudaMalloc((void**)&deviceMatrixTransposed, sizeof(double)*dim_x*dim_y);
//Kernel invocation with <<< # of blocks , # of threads per block>>>(args...)
hello_from_GPU<<<10,10>>>();
cudaCheckError();
cudaDeviceSynchronize();
//Reset the GPU
cudaDeviceReset();
return 0;
}
// Yey | .file "tmpxft_0012b25c_00000000-6_sample_base.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14hello_from_GPUvv
.type _Z33__device_stub__Z14hello_from_GPUvv, @function
_Z33__device_stub__Z14hello_from_GPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14hello_from_GPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14hello_from_GPUvv, .-_Z33__device_stub__Z14hello_from_GPUvv
.globl _Z14hello_from_GPUv
.type _Z14hello_from_GPUv, @function
_Z14hello_from_GPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14hello_from_GPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14hello_from_GPUv, .-_Z14hello_from_GPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Insuffisend arguments exiting\n"
.align 8
.LC1:
.string "Error in Host Matrix allocation\n"
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/koxakis/Code-Projects/master/C/Cuda/sample_base.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Cuda failure %s:%d: '%s'\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L25
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movslq %r12d, %rsi
movq %rsi, 8(%rsp)
leaq 0(,%rsi,8), %rdi
call malloc@PLT
testq %rax, %rax
je .L13
testl %ebx, %ebx
jle .L15
movq (%rsp), %rcx
movslq %ecx, %r13
salq $3, %r13
movq %rax, %rbp
movl %ecx, %r15d
leal -1(%rcx), %edx
leaq 8(%rax,%rdx,8), %r14
movl %ecx, %ebx
jmp .L18
.L25:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
addq $8, %rbp
addl %r12d, %ebx
cmpq %r14, %rbp
je .L15
.L18:
movq %r13, %rdi
call malloc@PLT
movq %rax, 0(%rbp)
testq %rax, %rax
je .L26
movl %ebx, %edx
subl %r15d, %edx
.L17:
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rax)
addl $1, %edx
addq $8, %rax
cmpl %ebx, %edx
jne .L17
jmp .L27
.L15:
movq $0, 16(%rsp)
movslq (%rsp), %rbx
movq 8(%rsp), %rax
imulq %rax, %rbx
salq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call _Z33__device_stub__Z14hello_from_GPUvv
jmp .L19
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $70, %ecx
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14hello_from_GPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14hello_from_GPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
//Compile with nvcc -arch sm_20 -lineinfo -Xcompiler -Wall -O4 -g sample_base.cu -o hello
//Check cuda call for errors, Call after each cuda call
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
//This is the kernel that runs on the GPU
__global__ void hello_from_GPU()
{
//printf("Hello world from the device! block=%d, thread=%d\n", blockIdx.x, threadIdx.x);
}
//This is the main function
int main(int argc, char **argv)
{
double **hostMatrix, *hostGpuOutput;
double *deviceMatrix, *deviceMatrixTransposed;
int dim_x = 1, dim_y = 1;
#ifdef DEBUG
int max_withd = 3;
#endif
if ( argc != 3)
{
printf("Insuffisend arguments exiting\n");
exit(EXIT_FAILURE);
}
else
{
dim_x = atoi(argv[1]);
dim_y = atoi(argv[2]);
}
hostMatrix = (double**)malloc(sizeof(double*)*dim_x);
if ( hostMatrix == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n");
exit(EXIT_FAILURE);
}
for ( int i = 0; i < dim_y; i++){
hostMatrix[i] = (double*)malloc( sizeof(double) * dim_y);
if (hostMatrix[i] == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n" );
exit(EXIT_FAILURE);
}
for ( int j = 0; j < dim_y; j++) {
hostMatrix[i][j] = j + (i * dim_x);
}
}
deviceMatrix = NULL;
cudaMalloc((void**)&deviceMatrix, sizeof(double)*dim_x*dim_y);
deviceMatrixTransposed = NULL;
cudaMalloc((void**)&deviceMatrixTransposed, sizeof(double)*dim_x*dim_y);
//Kernel invocation with <<< # of blocks , # of threads per block>>>(args...)
hello_from_GPU<<<10,10>>>();
cudaCheckError();
cudaDeviceSynchronize();
//Reset the GPU
cudaDeviceReset();
return 0;
}
// Yey | #include <hip/hip_runtime.h>
#include<stdio.h>
//Compile with nvcc -arch sm_20 -lineinfo -Xcompiler -Wall -O4 -g sample_base.cu -o hello
//Check cuda call for errors, Call after each cuda call
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
//This is the kernel that runs on the GPU
__global__ void hello_from_GPU()
{
//printf("Hello world from the device! block=%d, thread=%d\n", blockIdx.x, threadIdx.x);
}
//This is the main function
int main(int argc, char **argv)
{
double **hostMatrix, *hostGpuOutput;
double *deviceMatrix, *deviceMatrixTransposed;
int dim_x = 1, dim_y = 1;
#ifdef DEBUG
int max_withd = 3;
#endif
if ( argc != 3)
{
printf("Insuffisend arguments exiting\n");
exit(EXIT_FAILURE);
}
else
{
dim_x = atoi(argv[1]);
dim_y = atoi(argv[2]);
}
hostMatrix = (double**)malloc(sizeof(double*)*dim_x);
if ( hostMatrix == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n");
exit(EXIT_FAILURE);
}
for ( int i = 0; i < dim_y; i++){
hostMatrix[i] = (double*)malloc( sizeof(double) * dim_y);
if (hostMatrix[i] == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n" );
exit(EXIT_FAILURE);
}
for ( int j = 0; j < dim_y; j++) {
hostMatrix[i][j] = j + (i * dim_x);
}
}
deviceMatrix = NULL;
hipMalloc((void**)&deviceMatrix, sizeof(double)*dim_x*dim_y);
deviceMatrixTransposed = NULL;
hipMalloc((void**)&deviceMatrixTransposed, sizeof(double)*dim_x*dim_y);
//Kernel invocation with <<< # of blocks , # of threads per block>>>(args...)
hello_from_GPU<<<10,10>>>();
cudaCheckError();
hipDeviceSynchronize();
//Reset the GPU
hipDeviceReset();
return 0;
}
// Yey |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//Compile with nvcc -arch sm_20 -lineinfo -Xcompiler -Wall -O4 -g sample_base.cu -o hello
//Check cuda call for errors, Call after each cuda call
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
//This is the kernel that runs on the GPU
__global__ void hello_from_GPU()
{
//printf("Hello world from the device! block=%d, thread=%d\n", blockIdx.x, threadIdx.x);
}
//This is the main function
int main(int argc, char **argv)
{
double **hostMatrix, *hostGpuOutput;
double *deviceMatrix, *deviceMatrixTransposed;
int dim_x = 1, dim_y = 1;
#ifdef DEBUG
int max_withd = 3;
#endif
if ( argc != 3)
{
printf("Insuffisend arguments exiting\n");
exit(EXIT_FAILURE);
}
else
{
dim_x = atoi(argv[1]);
dim_y = atoi(argv[2]);
}
hostMatrix = (double**)malloc(sizeof(double*)*dim_x);
if ( hostMatrix == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n");
exit(EXIT_FAILURE);
}
for ( int i = 0; i < dim_y; i++){
hostMatrix[i] = (double*)malloc( sizeof(double) * dim_y);
if (hostMatrix[i] == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n" );
exit(EXIT_FAILURE);
}
for ( int j = 0; j < dim_y; j++) {
hostMatrix[i][j] = j + (i * dim_x);
}
}
deviceMatrix = NULL;
hipMalloc((void**)&deviceMatrix, sizeof(double)*dim_x*dim_y);
deviceMatrixTransposed = NULL;
hipMalloc((void**)&deviceMatrixTransposed, sizeof(double)*dim_x*dim_y);
//Kernel invocation with <<< # of blocks , # of threads per block>>>(args...)
hello_from_GPU<<<10,10>>>();
cudaCheckError();
hipDeviceSynchronize();
//Reset the GPU
hipDeviceReset();
return 0;
}
// Yey | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14hello_from_GPUv
.globl _Z14hello_from_GPUv
.p2align 8
.type _Z14hello_from_GPUv,@function
_Z14hello_from_GPUv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14hello_from_GPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14hello_from_GPUv, .Lfunc_end0-_Z14hello_from_GPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14hello_from_GPUv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14hello_from_GPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//Compile with nvcc -arch sm_20 -lineinfo -Xcompiler -Wall -O4 -g sample_base.cu -o hello
//Check cuda call for errors, Call after each cuda call
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
//This is the kernel that runs on the GPU
__global__ void hello_from_GPU()
{
//printf("Hello world from the device! block=%d, thread=%d\n", blockIdx.x, threadIdx.x);
}
//This is the main function
int main(int argc, char **argv)
{
double **hostMatrix, *hostGpuOutput;
double *deviceMatrix, *deviceMatrixTransposed;
int dim_x = 1, dim_y = 1;
#ifdef DEBUG
int max_withd = 3;
#endif
if ( argc != 3)
{
printf("Insuffisend arguments exiting\n");
exit(EXIT_FAILURE);
}
else
{
dim_x = atoi(argv[1]);
dim_y = atoi(argv[2]);
}
hostMatrix = (double**)malloc(sizeof(double*)*dim_x);
if ( hostMatrix == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n");
exit(EXIT_FAILURE);
}
for ( int i = 0; i < dim_y; i++){
hostMatrix[i] = (double*)malloc( sizeof(double) * dim_y);
if (hostMatrix[i] == NULL){
fprintf(stderr, "Error in Host Matrix allocation\n" );
exit(EXIT_FAILURE);
}
for ( int j = 0; j < dim_y; j++) {
hostMatrix[i][j] = j + (i * dim_x);
}
}
deviceMatrix = NULL;
hipMalloc((void**)&deviceMatrix, sizeof(double)*dim_x*dim_y);
deviceMatrixTransposed = NULL;
hipMalloc((void**)&deviceMatrixTransposed, sizeof(double)*dim_x*dim_y);
//Kernel invocation with <<< # of blocks , # of threads per block>>>(args...)
hello_from_GPU<<<10,10>>>();
cudaCheckError();
hipDeviceSynchronize();
//Reset the GPU
hipDeviceReset();
return 0;
}
// Yey | .text
.file "sample_base.hip"
.globl _Z29__device_stub__hello_from_GPUv # -- Begin function _Z29__device_stub__hello_from_GPUv
.p2align 4, 0x90
.type _Z29__device_stub__hello_from_GPUv,@function
_Z29__device_stub__hello_from_GPUv: # @_Z29__device_stub__hello_from_GPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14hello_from_GPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__hello_from_GPUv, .Lfunc_end0-_Z29__device_stub__hello_from_GPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $3, %edi
jne .LBB1_5
# %bb.1: # %._crit_edge
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %r14d, %rcx
movq $0, 8(%rsp)
movslq %eax, %rbx
imulq %rcx, %rbx
shlq $3, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, (%rsp)
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14hello_from_GPUv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 96
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $72, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14hello_from_GPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14hello_from_GPUv,@object # @_Z14hello_from_GPUv
.section .rodata,"a",@progbits
.globl _Z14hello_from_GPUv
.p2align 3, 0x0
_Z14hello_from_GPUv:
.quad _Z29__device_stub__hello_from_GPUv
.size _Z14hello_from_GPUv, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/koxakis/Code-Projects/master/C/Cuda/sample_base.hip"
.size .L.str.3, 109
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14hello_from_GPUv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Insuffisend arguments exiting"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__hello_from_GPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14hello_from_GPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14hello_from_GPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14hello_from_GPUv
.globl _Z14hello_from_GPUv
.p2align 8
.type _Z14hello_from_GPUv,@function
_Z14hello_from_GPUv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14hello_from_GPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14hello_from_GPUv, .Lfunc_end0-_Z14hello_from_GPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14hello_from_GPUv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14hello_from_GPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012b25c_00000000-6_sample_base.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14hello_from_GPUvv
.type _Z33__device_stub__Z14hello_from_GPUvv, @function
_Z33__device_stub__Z14hello_from_GPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14hello_from_GPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14hello_from_GPUvv, .-_Z33__device_stub__Z14hello_from_GPUvv
.globl _Z14hello_from_GPUv
.type _Z14hello_from_GPUv, @function
_Z14hello_from_GPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14hello_from_GPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14hello_from_GPUv, .-_Z14hello_from_GPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Insuffisend arguments exiting\n"
.align 8
.LC1:
.string "Error in Host Matrix allocation\n"
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/koxakis/Code-Projects/master/C/Cuda/sample_base.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Cuda failure %s:%d: '%s'\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L25
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movslq %r12d, %rsi
movq %rsi, 8(%rsp)
leaq 0(,%rsi,8), %rdi
call malloc@PLT
testq %rax, %rax
je .L13
testl %ebx, %ebx
jle .L15
movq (%rsp), %rcx
movslq %ecx, %r13
salq $3, %r13
movq %rax, %rbp
movl %ecx, %r15d
leal -1(%rcx), %edx
leaq 8(%rax,%rdx,8), %r14
movl %ecx, %ebx
jmp .L18
.L25:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
addq $8, %rbp
addl %r12d, %ebx
cmpq %r14, %rbp
je .L15
.L18:
movq %r13, %rdi
call malloc@PLT
movq %rax, 0(%rbp)
testq %rax, %rax
je .L26
movl %ebx, %edx
subl %r15d, %edx
.L17:
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rax)
addl $1, %edx
addq $8, %rax
cmpl %ebx, %edx
jne .L17
jmp .L27
.L15:
movq $0, 16(%rsp)
movslq (%rsp), %rbx
movq 8(%rsp), %rax
imulq %rax, %rbx
salq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call _Z33__device_stub__Z14hello_from_GPUvv
jmp .L19
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $70, %ecx
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14hello_from_GPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14hello_from_GPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample_base.hip"
.globl _Z29__device_stub__hello_from_GPUv # -- Begin function _Z29__device_stub__hello_from_GPUv
.p2align 4, 0x90
.type _Z29__device_stub__hello_from_GPUv,@function
_Z29__device_stub__hello_from_GPUv: # @_Z29__device_stub__hello_from_GPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14hello_from_GPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__hello_from_GPUv, .Lfunc_end0-_Z29__device_stub__hello_from_GPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $3, %edi
jne .LBB1_5
# %bb.1: # %._crit_edge
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %r14d, %rcx
movq $0, 8(%rsp)
movslq %eax, %rbx
imulq %rcx, %rbx
shlq $3, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, (%rsp)
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14hello_from_GPUv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 96
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $72, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14hello_from_GPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14hello_from_GPUv,@object # @_Z14hello_from_GPUv
.section .rodata,"a",@progbits
.globl _Z14hello_from_GPUv
.p2align 3, 0x0
_Z14hello_from_GPUv:
.quad _Z29__device_stub__hello_from_GPUv
.size _Z14hello_from_GPUv, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/koxakis/Code-Projects/master/C/Cuda/sample_base.hip"
.size .L.str.3, 109
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14hello_from_GPUv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Insuffisend arguments exiting"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__hello_from_GPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14hello_from_GPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
__global__ void mmult(double* A, double* B, double* C, int N)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < N) && (col < N))
{
double dot = .0;
for(int i = 0; i < N; ++i)
dot += A[row*N + i] * B[col + i*N];
C[row*N + col] = dot;
}
}
#define CUDA_CHECK(stmt) do { \
cudaError_t err = stmt; \
if(err != cudaSuccess) { \
std::cerr << "Failed to run statement: " << #stmt << std::endl; \
return -1; \
} \
} while(0)
extern bool do_cuda_mmult(double* A, double* B, double* C, int N)
{
double *deviceA, *deviceB, *deviceC;
int bytes = sizeof(double) * N * N;
CUDA_CHECK(cudaMalloc((void**)&deviceA, bytes));
CUDA_CHECK(cudaMalloc((void**)&deviceB, bytes));
CUDA_CHECK(cudaMalloc((void**)&deviceC, bytes));
CUDA_CHECK(cudaMemcpy(deviceA, A, bytes, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaMemcpy(deviceB, B, bytes, cudaMemcpyHostToDevice));
//cudaMemcpy(deviceC, C, bytes, cudaMemcpyHostToDevice);
static unsigned int constexpr TILE_WIDTH = 8;
dim3 dimGrid{ (N-1)/TILE_WIDTH+1, (N-1)/TILE_WIDTH+1, 1u };
dim3 dimBlock{ TILE_WIDTH, TILE_WIDTH, 1 };
mmult<<< dimGrid, dimBlock >>>(deviceA, deviceB, deviceC, N);
cudaThreadSynchronize();
CUDA_CHECK(cudaMemcpy(C, deviceC, bytes, cudaMemcpyDeviceToHost));
return true;
} | code for sm_80
Function : _Z5mmultPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
__global__ void mmult(double* A, double* B, double* C, int N)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < N) && (col < N))
{
double dot = .0;
for(int i = 0; i < N; ++i)
dot += A[row*N + i] * B[col + i*N];
C[row*N + col] = dot;
}
}
#define CUDA_CHECK(stmt) do { \
cudaError_t err = stmt; \
if(err != cudaSuccess) { \
std::cerr << "Failed to run statement: " << #stmt << std::endl; \
return -1; \
} \
} while(0)
extern bool do_cuda_mmult(double* A, double* B, double* C, int N)
{
double *deviceA, *deviceB, *deviceC;
int bytes = sizeof(double) * N * N;
CUDA_CHECK(cudaMalloc((void**)&deviceA, bytes));
CUDA_CHECK(cudaMalloc((void**)&deviceB, bytes));
CUDA_CHECK(cudaMalloc((void**)&deviceC, bytes));
CUDA_CHECK(cudaMemcpy(deviceA, A, bytes, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaMemcpy(deviceB, B, bytes, cudaMemcpyHostToDevice));
//cudaMemcpy(deviceC, C, bytes, cudaMemcpyHostToDevice);
static unsigned int constexpr TILE_WIDTH = 8;
dim3 dimGrid{ (N-1)/TILE_WIDTH+1, (N-1)/TILE_WIDTH+1, 1u };
dim3 dimBlock{ TILE_WIDTH, TILE_WIDTH, 1 };
mmult<<< dimGrid, dimBlock >>>(deviceA, deviceB, deviceC, N);
cudaThreadSynchronize();
CUDA_CHECK(cudaMemcpy(C, deviceC, bytes, cudaMemcpyDeviceToHost));
return true;
} | .file "tmpxft_000bc852_00000000-6_cuda_mmult.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
.type _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i, @function
_Z29__device_stub__Z5mmultPdS_S_iPdS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5mmultPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i, .-_Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
.globl _Z5mmultPdS_S_i
.type _Z5mmultPdS_S_i, @function
_Z5mmultPdS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5mmultPdS_S_i, .-_Z5mmultPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to run statement: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaMalloc((void**)&deviceA, bytes)"
.align 8
.LC2:
.string "cudaMalloc((void**)&deviceB, bytes)"
.align 8
.LC3:
.string "cudaMalloc((void**)&deviceC, bytes)"
.align 8
.LC4:
.string "cudaMemcpy(deviceA, A, bytes, cudaMemcpyHostToDevice)"
.align 8
.LC5:
.string "cudaMemcpy(deviceB, B, bytes, cudaMemcpyHostToDevice)"
.align 8
.LC6:
.string "cudaMemcpy(C, deviceC, bytes, cudaMemcpyDeviceToHost)"
.text
.globl _Z13do_cuda_mmultPdS_S_i
.type _Z13do_cuda_mmultPdS_S_i, @function
_Z13do_cuda_mmultPdS_S_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L49
leal -1(%rbp), %eax
shrl $3, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L17
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $53, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L51
cmpb $0, 56(%rbx)
je .L41
movzbl 67(%rbx), %esi
.L42:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L45:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L52
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %esi
.L16:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L17:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $1, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L46:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L55
cmpb $0, 56(%rbx)
je .L21
movzbl 67(%rbx), %esi
.L22:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L55:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L56:
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L47:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L57
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L57:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L48:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $53, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L59
cmpb $0, 56(%rbx)
je .L31
movzbl 67(%rbx), %esi
.L32:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L59:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L60
call _ZSt16__throw_bad_castv@PLT
.L60:
call __stack_chk_fail@PLT
.L31:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L49:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $53, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L61
cmpb $0, 56(%rbx)
je .L36
movzbl 67(%rbx), %esi
.L37:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L61:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L62
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L37
.L50:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
jmp .L38
.L51:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L63
call _ZSt16__throw_bad_castv@PLT
.L63:
call __stack_chk_fail@PLT
.L41:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z13do_cuda_mmultPdS_S_i, .-_Z13do_cuda_mmultPdS_S_i
.section .rodata.str1.1
.LC7:
.string "_Z5mmultPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5mmultPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
__global__ void mmult(double* A, double* B, double* C, int N)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < N) && (col < N))
{
double dot = .0;
for(int i = 0; i < N; ++i)
dot += A[row*N + i] * B[col + i*N];
C[row*N + col] = dot;
}
}
#define CUDA_CHECK(stmt) do { \
cudaError_t err = stmt; \
if(err != cudaSuccess) { \
std::cerr << "Failed to run statement: " << #stmt << std::endl; \
return -1; \
} \
} while(0)
extern bool do_cuda_mmult(double* A, double* B, double* C, int N)
{
double *deviceA, *deviceB, *deviceC;
int bytes = sizeof(double) * N * N;
CUDA_CHECK(cudaMalloc((void**)&deviceA, bytes));
CUDA_CHECK(cudaMalloc((void**)&deviceB, bytes));
CUDA_CHECK(cudaMalloc((void**)&deviceC, bytes));
CUDA_CHECK(cudaMemcpy(deviceA, A, bytes, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaMemcpy(deviceB, B, bytes, cudaMemcpyHostToDevice));
//cudaMemcpy(deviceC, C, bytes, cudaMemcpyHostToDevice);
static unsigned int constexpr TILE_WIDTH = 8;
dim3 dimGrid{ (N-1)/TILE_WIDTH+1, (N-1)/TILE_WIDTH+1, 1u };
dim3 dimBlock{ TILE_WIDTH, TILE_WIDTH, 1 };
mmult<<< dimGrid, dimBlock >>>(deviceA, deviceB, deviceC, N);
cudaThreadSynchronize();
CUDA_CHECK(cudaMemcpy(C, deviceC, bytes, cudaMemcpyDeviceToHost));
return true;
} | #include <iostream>
#include <hip/hip_runtime.h>
__global__ void mmult(double* A, double* B, double* C, int N)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < N) && (col < N))
{
double dot = .0;
for(int i = 0; i < N; ++i)
dot += A[row*N + i] * B[col + i*N];
C[row*N + col] = dot;
}
}
#define CUDA_CHECK(stmt) do { \
hipError_t err = stmt; \
if(err != hipSuccess) { \
std::cerr << "Failed to run statement: " << #stmt << std::endl; \
return -1; \
} \
} while(0)
extern bool do_cuda_mmult(double* A, double* B, double* C, int N)
{
double *deviceA, *deviceB, *deviceC;
int bytes = sizeof(double) * N * N;
CUDA_CHECK(hipMalloc((void**)&deviceA, bytes));
CUDA_CHECK(hipMalloc((void**)&deviceB, bytes));
CUDA_CHECK(hipMalloc((void**)&deviceC, bytes));
CUDA_CHECK(hipMemcpy(deviceA, A, bytes, hipMemcpyHostToDevice));
CUDA_CHECK(hipMemcpy(deviceB, B, bytes, hipMemcpyHostToDevice));
//cudaMemcpy(deviceC, C, bytes, cudaMemcpyHostToDevice);
static unsigned int constexpr TILE_WIDTH = 8;
dim3 dimGrid{ (N-1)/TILE_WIDTH+1, (N-1)/TILE_WIDTH+1, 1u };
dim3 dimBlock{ TILE_WIDTH, TILE_WIDTH, 1 };
mmult<<< dimGrid, dimBlock >>>(deviceA, deviceB, deviceC, N);
hipDeviceSynchronize();
CUDA_CHECK(hipMemcpy(C, deviceC, bytes, hipMemcpyDeviceToHost));
return true;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
__global__ void mmult(double* A, double* B, double* C, int N)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < N) && (col < N))
{
double dot = .0;
for(int i = 0; i < N; ++i)
dot += A[row*N + i] * B[col + i*N];
C[row*N + col] = dot;
}
}
#define CUDA_CHECK(stmt) do { \
hipError_t err = stmt; \
if(err != hipSuccess) { \
std::cerr << "Failed to run statement: " << #stmt << std::endl; \
return -1; \
} \
} while(0)
extern bool do_cuda_mmult(double* A, double* B, double* C, int N)
{
double *deviceA, *deviceB, *deviceC;
int bytes = sizeof(double) * N * N;
CUDA_CHECK(hipMalloc((void**)&deviceA, bytes));
CUDA_CHECK(hipMalloc((void**)&deviceB, bytes));
CUDA_CHECK(hipMalloc((void**)&deviceC, bytes));
CUDA_CHECK(hipMemcpy(deviceA, A, bytes, hipMemcpyHostToDevice));
CUDA_CHECK(hipMemcpy(deviceB, B, bytes, hipMemcpyHostToDevice));
//cudaMemcpy(deviceC, C, bytes, cudaMemcpyHostToDevice);
static unsigned int constexpr TILE_WIDTH = 8;
dim3 dimGrid{ (N-1)/TILE_WIDTH+1, (N-1)/TILE_WIDTH+1, 1u };
dim3 dimBlock{ TILE_WIDTH, TILE_WIDTH, 1 };
mmult<<< dimGrid, dimBlock >>>(deviceA, deviceB, deviceC, N);
hipDeviceSynchronize();
CUDA_CHECK(hipMemcpy(C, deviceC, bytes, hipMemcpyDeviceToHost));
return true;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5mmultPdS_S_i
.globl _Z5mmultPdS_S_i
.p2align 8
.type _Z5mmultPdS_S_i,@function
_Z5mmultPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5mmultPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5mmultPdS_S_i, .Lfunc_end0-_Z5mmultPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5mmultPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5mmultPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
__global__ void mmult(double* A, double* B, double* C, int N)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < N) && (col < N))
{
double dot = .0;
for(int i = 0; i < N; ++i)
dot += A[row*N + i] * B[col + i*N];
C[row*N + col] = dot;
}
}
#define CUDA_CHECK(stmt) do { \
hipError_t err = stmt; \
if(err != hipSuccess) { \
std::cerr << "Failed to run statement: " << #stmt << std::endl; \
return -1; \
} \
} while(0)
extern bool do_cuda_mmult(double* A, double* B, double* C, int N)
{
double *deviceA, *deviceB, *deviceC;
int bytes = sizeof(double) * N * N;
CUDA_CHECK(hipMalloc((void**)&deviceA, bytes));
CUDA_CHECK(hipMalloc((void**)&deviceB, bytes));
CUDA_CHECK(hipMalloc((void**)&deviceC, bytes));
CUDA_CHECK(hipMemcpy(deviceA, A, bytes, hipMemcpyHostToDevice));
CUDA_CHECK(hipMemcpy(deviceB, B, bytes, hipMemcpyHostToDevice));
//cudaMemcpy(deviceC, C, bytes, cudaMemcpyHostToDevice);
static unsigned int constexpr TILE_WIDTH = 8;
dim3 dimGrid{ (N-1)/TILE_WIDTH+1, (N-1)/TILE_WIDTH+1, 1u };
dim3 dimBlock{ TILE_WIDTH, TILE_WIDTH, 1 };
mmult<<< dimGrid, dimBlock >>>(deviceA, deviceB, deviceC, N);
hipDeviceSynchronize();
CUDA_CHECK(hipMemcpy(C, deviceC, bytes, hipMemcpyDeviceToHost));
return true;
} | .text
.file "cuda_mmult.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__mmultPdS_S_i # -- Begin function _Z20__device_stub__mmultPdS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__mmultPdS_S_i,@function
_Z20__device_stub__mmultPdS_S_i: # @_Z20__device_stub__mmultPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5mmultPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__mmultPdS_S_i, .Lfunc_end0-_Z20__device_stub__mmultPdS_S_i
.cfi_endproc
# -- End function
.globl _Z13do_cuda_mmultPdS_S_i # -- Begin function _Z13do_cuda_mmultPdS_S_i
.p2align 4, 0x90
.type _Z13do_cuda_mmultPdS_S_i,@function
_Z13do_cuda_mmultPdS_S_i: # @_Z13do_cuda_mmultPdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movl %ecx, %eax
imull %ecx, %eax
shll $3, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
jmp .LBB1_2
.LBB1_6: # %.critedge
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_9
# %bb.7:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
jmp .LBB1_2
.LBB1_9: # %.critedge50
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_11
# %bb.10:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
.LBB1_2:
movl $34, %edx
.LBB1_3:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_15: # %.critedge58
movb $1, %al
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11: # %.critedge52
.cfi_def_cfa_offset 80
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_16
# %bb.12:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $51, %edx
jmp .LBB1_3
.LBB1_16: # %.critedge54
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
jmp .LBB1_22
.LBB1_18: # %.critedge56
leal -1(%r15), %eax
shrl $3, %eax
leaq 1(%rax), %rcx
shlq $32, %rcx
leaq (%rax,%rcx), %rdi
incq %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl %r15d, %ecx
callq _Z20__device_stub__mmultPdS_S_i
.LBB1_20:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_15
# %bb.21:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
.LBB1_22: # %.critedge58
movl $51, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_15
.LBB1_8:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z13do_cuda_mmultPdS_S_i, .Lfunc_end1-_Z13do_cuda_mmultPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5mmultPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5mmultPdS_S_i,@object # @_Z5mmultPdS_S_i
.section .rodata,"a",@progbits
.globl _Z5mmultPdS_S_i
.p2align 3, 0x0
_Z5mmultPdS_S_i:
.quad _Z20__device_stub__mmultPdS_S_i
.size _Z5mmultPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to run statement: "
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void**)&deviceA, bytes)"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc((void**)&deviceB, bytes)"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void**)&deviceC, bytes)"
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy(deviceA, A, bytes, hipMemcpyHostToDevice)"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(deviceB, B, bytes, hipMemcpyHostToDevice)"
.size .L.str.5, 52
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(C, deviceC, bytes, hipMemcpyDeviceToHost)"
.size .L.str.6, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5mmultPdS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__mmultPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5mmultPdS_S_i
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5mmultPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5mmultPdS_S_i
.globl _Z5mmultPdS_S_i
.p2align 8
.type _Z5mmultPdS_S_i,@function
_Z5mmultPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5mmultPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5mmultPdS_S_i, .Lfunc_end0-_Z5mmultPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5mmultPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5mmultPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bc852_00000000-6_cuda_mmult.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
.type _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i, @function
_Z29__device_stub__Z5mmultPdS_S_iPdS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5mmultPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i, .-_Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
.globl _Z5mmultPdS_S_i
.type _Z5mmultPdS_S_i, @function
_Z5mmultPdS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5mmultPdS_S_i, .-_Z5mmultPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to run statement: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaMalloc((void**)&deviceA, bytes)"
.align 8
.LC2:
.string "cudaMalloc((void**)&deviceB, bytes)"
.align 8
.LC3:
.string "cudaMalloc((void**)&deviceC, bytes)"
.align 8
.LC4:
.string "cudaMemcpy(deviceA, A, bytes, cudaMemcpyHostToDevice)"
.align 8
.LC5:
.string "cudaMemcpy(deviceB, B, bytes, cudaMemcpyHostToDevice)"
.align 8
.LC6:
.string "cudaMemcpy(C, deviceC, bytes, cudaMemcpyDeviceToHost)"
.text
.globl _Z13do_cuda_mmultPdS_S_i
.type _Z13do_cuda_mmultPdS_S_i, @function
_Z13do_cuda_mmultPdS_S_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L49
leal -1(%rbp), %eax
shrl $3, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L17
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $53, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L51
cmpb $0, 56(%rbx)
je .L41
movzbl 67(%rbx), %esi
.L42:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L45:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L52
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %esi
.L16:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L17:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $1, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L46:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L55
cmpb $0, 56(%rbx)
je .L21
movzbl 67(%rbx), %esi
.L22:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L55:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L56:
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L47:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L57
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L57:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L48:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $53, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L59
cmpb $0, 56(%rbx)
je .L31
movzbl 67(%rbx), %esi
.L32:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L59:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L60
call _ZSt16__throw_bad_castv@PLT
.L60:
call __stack_chk_fail@PLT
.L31:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L49:
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $53, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L61
cmpb $0, 56(%rbx)
je .L36
movzbl 67(%rbx), %esi
.L37:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L61:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L62
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L37
.L50:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5mmultPdS_S_iPdS_S_i
jmp .L38
.L51:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L63
call _ZSt16__throw_bad_castv@PLT
.L63:
call __stack_chk_fail@PLT
.L41:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z13do_cuda_mmultPdS_S_i, .-_Z13do_cuda_mmultPdS_S_i
.section .rodata.str1.1
.LC7:
.string "_Z5mmultPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5mmultPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_mmult.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__mmultPdS_S_i # -- Begin function _Z20__device_stub__mmultPdS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__mmultPdS_S_i,@function
_Z20__device_stub__mmultPdS_S_i: # @_Z20__device_stub__mmultPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5mmultPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__mmultPdS_S_i, .Lfunc_end0-_Z20__device_stub__mmultPdS_S_i
.cfi_endproc
# -- End function
.globl _Z13do_cuda_mmultPdS_S_i # -- Begin function _Z13do_cuda_mmultPdS_S_i
.p2align 4, 0x90
.type _Z13do_cuda_mmultPdS_S_i,@function
_Z13do_cuda_mmultPdS_S_i: # @_Z13do_cuda_mmultPdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movl %ecx, %eax
imull %ecx, %eax
shll $3, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
jmp .LBB1_2
.LBB1_6: # %.critedge
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_9
# %bb.7:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
jmp .LBB1_2
.LBB1_9: # %.critedge50
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_11
# %bb.10:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
.LBB1_2:
movl $34, %edx
.LBB1_3:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_15: # %.critedge58
movb $1, %al
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11: # %.critedge52
.cfi_def_cfa_offset 80
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_16
# %bb.12:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $51, %edx
jmp .LBB1_3
.LBB1_16: # %.critedge54
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
jmp .LBB1_22
.LBB1_18: # %.critedge56
leal -1(%r15), %eax
shrl $3, %eax
leaq 1(%rax), %rcx
shlq $32, %rcx
leaq (%rax,%rcx), %rdi
incq %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl %r15d, %ecx
callq _Z20__device_stub__mmultPdS_S_i
.LBB1_20:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_15
# %bb.21:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
.LBB1_22: # %.critedge58
movl $51, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_15
.LBB1_8:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z13do_cuda_mmultPdS_S_i, .Lfunc_end1-_Z13do_cuda_mmultPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5mmultPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5mmultPdS_S_i,@object # @_Z5mmultPdS_S_i
.section .rodata,"a",@progbits
.globl _Z5mmultPdS_S_i
.p2align 3, 0x0
_Z5mmultPdS_S_i:
.quad _Z20__device_stub__mmultPdS_S_i
.size _Z5mmultPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to run statement: "
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void**)&deviceA, bytes)"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc((void**)&deviceB, bytes)"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void**)&deviceC, bytes)"
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy(deviceA, A, bytes, hipMemcpyHostToDevice)"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(deviceB, B, bytes, hipMemcpyHostToDevice)"
.size .L.str.5, 52
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(C, deviceC, bytes, hipMemcpyDeviceToHost)"
.size .L.str.6, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5mmultPdS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__mmultPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5mmultPdS_S_i
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <vector>
#include <algorithm>
#include <iostream>
#define TILE_WIDTH 16
__global__ void sum_matrices(float *ma, float *mb, float *mc, int height, int width)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // linie
int col = blockIdx.x * blockDim.x + threadIdx.x; // coloana
// se poate si invers, adica row = blockIdx.x * blockDim.x + threadIdx.x;
if (row < height && col < width) {
mc[row * height + col] = ma[row * height + col] + mb[row * height + col];
}
}
int main() {
// size
const size_t n = 1 << 6;
// setam dimensiunea unui bloc pentru linie, respectiv coloana
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
// determinam numarul de blocuri pentru linie, respectiv coloana
const dim3 num_blocks(n / block_size.x, n / block_size.y);
// nu avem dim2 in CUDA
// alocam memorie pentru host
float *host_a = 0, *host_b = 0, *host_c = 0;
host_a = (float *) malloc(n * n * sizeof(float));
host_b = (float *) malloc(n * n * sizeof(float));
host_c = (float *) malloc(n * n * sizeof(float));
for (int i = 0; i < n * n; i++) {
host_a[i] = 2;
host_b[i] = 4;
host_c[i] = 0;
}
// alocam memorie pentru device
float *device_a = 0, *device_b = 0, *device_c = 0;
cudaMalloc((void**)&device_a, sizeof(float) * n * n);
cudaMalloc((void**)&device_b, sizeof(float) * n * n);
cudaMalloc((void**)&device_c, sizeof(float) * n * n);
// transfer date CPU -> GPU
cudaMemcpy(device_a, &host_a[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_b, &host_b[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_c, &host_c[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
// evenimente CUDA, pe care le folosim pentru masurarea timpului de executie
cudaEvent_t launch_begin, launch_end;
// creeam evenimentele
cudaEventCreate(&launch_begin);
cudaEventCreate(&launch_end);
// lansam in executie evenimentul pentru start
cudaEventRecord(launch_begin);
// lansam kernel-ul in executie
sum_matrices<<<num_blocks, block_size>>>(device_a, device_b, device_c, n, n);
// lansam in executie evenimentul pentru stop
cudaEventRecord(launch_end);
// in loc sa folosim cudaDeviceSynchronize, folosim cudaEventSynchronize
// prin care se asteapta terminarea thread-urilor
cudaEventSynchronize(launch_end);
float time = 0;
// determinam timpul de executie
cudaEventElapsedTime(&time, launch_begin, launch_end);
std::cout << "Time = " << time << std::endl;
cudaMemcpy(host_c, &device_c[0], sizeof(float) * n * n, cudaMemcpyDeviceToHost);
for (int i = 0; i < 20; i++) {
std::cout << host_c[i] << " ";
}
std::cout << std::endl;
// distrugem evenimentele
cudaEventDestroy(launch_begin);
cudaEventDestroy(launch_end);
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
free(host_a);
free(host_b);
free(host_c);
return 0;
} | code for sm_80
Function : _Z12sum_matricesPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <vector>
#include <algorithm>
#include <iostream>
#define TILE_WIDTH 16
__global__ void sum_matrices(float *ma, float *mb, float *mc, int height, int width)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // linie
int col = blockIdx.x * blockDim.x + threadIdx.x; // coloana
// se poate si invers, adica row = blockIdx.x * blockDim.x + threadIdx.x;
if (row < height && col < width) {
mc[row * height + col] = ma[row * height + col] + mb[row * height + col];
}
}
int main() {
// size
const size_t n = 1 << 6;
// setam dimensiunea unui bloc pentru linie, respectiv coloana
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
// determinam numarul de blocuri pentru linie, respectiv coloana
const dim3 num_blocks(n / block_size.x, n / block_size.y);
// nu avem dim2 in CUDA
// alocam memorie pentru host
float *host_a = 0, *host_b = 0, *host_c = 0;
host_a = (float *) malloc(n * n * sizeof(float));
host_b = (float *) malloc(n * n * sizeof(float));
host_c = (float *) malloc(n * n * sizeof(float));
for (int i = 0; i < n * n; i++) {
host_a[i] = 2;
host_b[i] = 4;
host_c[i] = 0;
}
// alocam memorie pentru device
float *device_a = 0, *device_b = 0, *device_c = 0;
cudaMalloc((void**)&device_a, sizeof(float) * n * n);
cudaMalloc((void**)&device_b, sizeof(float) * n * n);
cudaMalloc((void**)&device_c, sizeof(float) * n * n);
// transfer date CPU -> GPU
cudaMemcpy(device_a, &host_a[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_b, &host_b[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_c, &host_c[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
// evenimente CUDA, pe care le folosim pentru masurarea timpului de executie
cudaEvent_t launch_begin, launch_end;
// creeam evenimentele
cudaEventCreate(&launch_begin);
cudaEventCreate(&launch_end);
// lansam in executie evenimentul pentru start
cudaEventRecord(launch_begin);
// lansam kernel-ul in executie
sum_matrices<<<num_blocks, block_size>>>(device_a, device_b, device_c, n, n);
// lansam in executie evenimentul pentru stop
cudaEventRecord(launch_end);
// in loc sa folosim cudaDeviceSynchronize, folosim cudaEventSynchronize
// prin care se asteapta terminarea thread-urilor
cudaEventSynchronize(launch_end);
float time = 0;
// determinam timpul de executie
cudaEventElapsedTime(&time, launch_begin, launch_end);
std::cout << "Time = " << time << std::endl;
cudaMemcpy(host_c, &device_c[0], sizeof(float) * n * n, cudaMemcpyDeviceToHost);
for (int i = 0; i < 20; i++) {
std::cout << host_c[i] << " ";
}
std::cout << std::endl;
// distrugem evenimentele
cudaEventDestroy(launch_begin);
cudaEventDestroy(launch_end);
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
free(host_a);
free(host_b);
free(host_c);
return 0;
} | .file "tmpxft_00148b6b_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4289:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4289:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii:
.LFB4311:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sum_matricesPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4311:
.size _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
.globl _Z12sum_matricesPfS_S_ii
.type _Z12sum_matricesPfS_S_ii, @function
_Z12sum_matricesPfS_S_ii:
.LFB4312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4312:
.size _Z12sum_matricesPfS_S_ii, .-_Z12sum_matricesPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Time = "
.LC4:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4286:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 56(%rsp)
movl $4, 60(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
movl $16384, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
addq $4, %rax
cmpq $16384, %rax
jne .L12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $16384, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %r13
leaq 80(%rbx), %r15
leaq _ZSt4cout(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %r13
cmpq %r15, %r13
jne .L14
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %r8d
movl $64, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4286:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12sum_matricesPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4314:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sum_matricesPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4314:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.align 4
.LC1:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <vector>
#include <algorithm>
#include <iostream>
#define TILE_WIDTH 16
__global__ void sum_matrices(float *ma, float *mb, float *mc, int height, int width)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // linie
int col = blockIdx.x * blockDim.x + threadIdx.x; // coloana
// se poate si invers, adica row = blockIdx.x * blockDim.x + threadIdx.x;
if (row < height && col < width) {
mc[row * height + col] = ma[row * height + col] + mb[row * height + col];
}
}
int main() {
// size
const size_t n = 1 << 6;
// setam dimensiunea unui bloc pentru linie, respectiv coloana
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
// determinam numarul de blocuri pentru linie, respectiv coloana
const dim3 num_blocks(n / block_size.x, n / block_size.y);
// nu avem dim2 in CUDA
// alocam memorie pentru host
float *host_a = 0, *host_b = 0, *host_c = 0;
host_a = (float *) malloc(n * n * sizeof(float));
host_b = (float *) malloc(n * n * sizeof(float));
host_c = (float *) malloc(n * n * sizeof(float));
for (int i = 0; i < n * n; i++) {
host_a[i] = 2;
host_b[i] = 4;
host_c[i] = 0;
}
// alocam memorie pentru device
float *device_a = 0, *device_b = 0, *device_c = 0;
cudaMalloc((void**)&device_a, sizeof(float) * n * n);
cudaMalloc((void**)&device_b, sizeof(float) * n * n);
cudaMalloc((void**)&device_c, sizeof(float) * n * n);
// transfer date CPU -> GPU
cudaMemcpy(device_a, &host_a[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_b, &host_b[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_c, &host_c[0], sizeof(float) * n * n, cudaMemcpyHostToDevice);
// evenimente CUDA, pe care le folosim pentru masurarea timpului de executie
cudaEvent_t launch_begin, launch_end;
// creeam evenimentele
cudaEventCreate(&launch_begin);
cudaEventCreate(&launch_end);
// lansam in executie evenimentul pentru start
cudaEventRecord(launch_begin);
// lansam kernel-ul in executie
sum_matrices<<<num_blocks, block_size>>>(device_a, device_b, device_c, n, n);
// lansam in executie evenimentul pentru stop
cudaEventRecord(launch_end);
// in loc sa folosim cudaDeviceSynchronize, folosim cudaEventSynchronize
// prin care se asteapta terminarea thread-urilor
cudaEventSynchronize(launch_end);
float time = 0;
// determinam timpul de executie
cudaEventElapsedTime(&time, launch_begin, launch_end);
std::cout << "Time = " << time << std::endl;
cudaMemcpy(host_c, &device_c[0], sizeof(float) * n * n, cudaMemcpyDeviceToHost);
for (int i = 0; i < 20; i++) {
std::cout << host_c[i] << " ";
}
std::cout << std::endl;
// distrugem evenimentele
cudaEventDestroy(launch_begin);
cudaEventDestroy(launch_end);
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
free(host_a);
free(host_b);
free(host_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <vector>
#include <algorithm>
#include <iostream>
#define TILE_WIDTH 16
__global__ void sum_matrices(float *ma, float *mb, float *mc, int height, int width)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // linie
int col = blockIdx.x * blockDim.x + threadIdx.x; // coloana
// se poate si invers, adica row = blockIdx.x * blockDim.x + threadIdx.x;
if (row < height && col < width) {
mc[row * height + col] = ma[row * height + col] + mb[row * height + col];
}
}
int main() {
// size
const size_t n = 1 << 6;
// setam dimensiunea unui bloc pentru linie, respectiv coloana
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
// determinam numarul de blocuri pentru linie, respectiv coloana
const dim3 num_blocks(n / block_size.x, n / block_size.y);
// nu avem dim2 in CUDA
// alocam memorie pentru host
float *host_a = 0, *host_b = 0, *host_c = 0;
host_a = (float *) malloc(n * n * sizeof(float));
host_b = (float *) malloc(n * n * sizeof(float));
host_c = (float *) malloc(n * n * sizeof(float));
for (int i = 0; i < n * n; i++) {
host_a[i] = 2;
host_b[i] = 4;
host_c[i] = 0;
}
// alocam memorie pentru device
float *device_a = 0, *device_b = 0, *device_c = 0;
hipMalloc((void**)&device_a, sizeof(float) * n * n);
hipMalloc((void**)&device_b, sizeof(float) * n * n);
hipMalloc((void**)&device_c, sizeof(float) * n * n);
// transfer date CPU -> GPU
hipMemcpy(device_a, &host_a[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_b, &host_b[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_c, &host_c[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
// evenimente CUDA, pe care le folosim pentru masurarea timpului de executie
hipEvent_t launch_begin, launch_end;
// creeam evenimentele
hipEventCreate(&launch_begin);
hipEventCreate(&launch_end);
// lansam in executie evenimentul pentru start
hipEventRecord(launch_begin);
// lansam kernel-ul in executie
sum_matrices<<<num_blocks, block_size>>>(device_a, device_b, device_c, n, n);
// lansam in executie evenimentul pentru stop
hipEventRecord(launch_end);
// in loc sa folosim cudaDeviceSynchronize, folosim cudaEventSynchronize
// prin care se asteapta terminarea thread-urilor
hipEventSynchronize(launch_end);
float time = 0;
// determinam timpul de executie
hipEventElapsedTime(&time, launch_begin, launch_end);
std::cout << "Time = " << time << std::endl;
hipMemcpy(host_c, &device_c[0], sizeof(float) * n * n, hipMemcpyDeviceToHost);
for (int i = 0; i < 20; i++) {
std::cout << host_c[i] << " ";
}
std::cout << std::endl;
// distrugem evenimentele
hipEventDestroy(launch_begin);
hipEventDestroy(launch_end);
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
free(host_a);
free(host_b);
free(host_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <vector>
#include <algorithm>
#include <iostream>
#define TILE_WIDTH 16
__global__ void sum_matrices(float *ma, float *mb, float *mc, int height, int width)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // linie
int col = blockIdx.x * blockDim.x + threadIdx.x; // coloana
// se poate si invers, adica row = blockIdx.x * blockDim.x + threadIdx.x;
if (row < height && col < width) {
mc[row * height + col] = ma[row * height + col] + mb[row * height + col];
}
}
int main() {
// size
const size_t n = 1 << 6;
// setam dimensiunea unui bloc pentru linie, respectiv coloana
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
// determinam numarul de blocuri pentru linie, respectiv coloana
const dim3 num_blocks(n / block_size.x, n / block_size.y);
// nu avem dim2 in CUDA
// alocam memorie pentru host
float *host_a = 0, *host_b = 0, *host_c = 0;
host_a = (float *) malloc(n * n * sizeof(float));
host_b = (float *) malloc(n * n * sizeof(float));
host_c = (float *) malloc(n * n * sizeof(float));
for (int i = 0; i < n * n; i++) {
host_a[i] = 2;
host_b[i] = 4;
host_c[i] = 0;
}
// alocam memorie pentru device
float *device_a = 0, *device_b = 0, *device_c = 0;
hipMalloc((void**)&device_a, sizeof(float) * n * n);
hipMalloc((void**)&device_b, sizeof(float) * n * n);
hipMalloc((void**)&device_c, sizeof(float) * n * n);
// transfer date CPU -> GPU
hipMemcpy(device_a, &host_a[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_b, &host_b[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_c, &host_c[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
// evenimente CUDA, pe care le folosim pentru masurarea timpului de executie
hipEvent_t launch_begin, launch_end;
// creeam evenimentele
hipEventCreate(&launch_begin);
hipEventCreate(&launch_end);
// lansam in executie evenimentul pentru start
hipEventRecord(launch_begin);
// lansam kernel-ul in executie
sum_matrices<<<num_blocks, block_size>>>(device_a, device_b, device_c, n, n);
// lansam in executie evenimentul pentru stop
hipEventRecord(launch_end);
// in loc sa folosim cudaDeviceSynchronize, folosim cudaEventSynchronize
// prin care se asteapta terminarea thread-urilor
hipEventSynchronize(launch_end);
float time = 0;
// determinam timpul de executie
hipEventElapsedTime(&time, launch_begin, launch_end);
std::cout << "Time = " << time << std::endl;
hipMemcpy(host_c, &device_c[0], sizeof(float) * n * n, hipMemcpyDeviceToHost);
for (int i = 0; i < 20; i++) {
std::cout << host_c[i] << " ";
}
std::cout << std::endl;
// distrugem evenimentele
hipEventDestroy(launch_begin);
hipEventDestroy(launch_end);
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
free(host_a);
free(host_b);
free(host_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sum_matricesPfS_S_ii
.globl _Z12sum_matricesPfS_S_ii
.p2align 8
.type _Z12sum_matricesPfS_S_ii,@function
_Z12sum_matricesPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sum_matricesPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sum_matricesPfS_S_ii, .Lfunc_end0-_Z12sum_matricesPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sum_matricesPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sum_matricesPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <vector>
#include <algorithm>
#include <iostream>
#define TILE_WIDTH 16
__global__ void sum_matrices(float *ma, float *mb, float *mc, int height, int width)
{
int row = blockIdx.y * blockDim.y + threadIdx.y; // linie
int col = blockIdx.x * blockDim.x + threadIdx.x; // coloana
// se poate si invers, adica row = blockIdx.x * blockDim.x + threadIdx.x;
if (row < height && col < width) {
mc[row * height + col] = ma[row * height + col] + mb[row * height + col];
}
}
int main() {
// size
const size_t n = 1 << 6;
// setam dimensiunea unui bloc pentru linie, respectiv coloana
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
// determinam numarul de blocuri pentru linie, respectiv coloana
const dim3 num_blocks(n / block_size.x, n / block_size.y);
// nu avem dim2 in CUDA
// alocam memorie pentru host
float *host_a = 0, *host_b = 0, *host_c = 0;
host_a = (float *) malloc(n * n * sizeof(float));
host_b = (float *) malloc(n * n * sizeof(float));
host_c = (float *) malloc(n * n * sizeof(float));
for (int i = 0; i < n * n; i++) {
host_a[i] = 2;
host_b[i] = 4;
host_c[i] = 0;
}
// alocam memorie pentru device
float *device_a = 0, *device_b = 0, *device_c = 0;
hipMalloc((void**)&device_a, sizeof(float) * n * n);
hipMalloc((void**)&device_b, sizeof(float) * n * n);
hipMalloc((void**)&device_c, sizeof(float) * n * n);
// transfer date CPU -> GPU
hipMemcpy(device_a, &host_a[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_b, &host_b[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_c, &host_c[0], sizeof(float) * n * n, hipMemcpyHostToDevice);
// evenimente CUDA, pe care le folosim pentru masurarea timpului de executie
hipEvent_t launch_begin, launch_end;
// creeam evenimentele
hipEventCreate(&launch_begin);
hipEventCreate(&launch_end);
// lansam in executie evenimentul pentru start
hipEventRecord(launch_begin);
// lansam kernel-ul in executie
sum_matrices<<<num_blocks, block_size>>>(device_a, device_b, device_c, n, n);
// lansam in executie evenimentul pentru stop
hipEventRecord(launch_end);
// in loc sa folosim cudaDeviceSynchronize, folosim cudaEventSynchronize
// prin care se asteapta terminarea thread-urilor
hipEventSynchronize(launch_end);
float time = 0;
// determinam timpul de executie
hipEventElapsedTime(&time, launch_begin, launch_end);
std::cout << "Time = " << time << std::endl;
hipMemcpy(host_c, &device_c[0], sizeof(float) * n * n, hipMemcpyDeviceToHost);
for (int i = 0; i < 20; i++) {
std::cout << host_c[i] << " ";
}
std::cout << std::endl;
// distrugem evenimentele
hipEventDestroy(launch_begin);
hipEventDestroy(launch_end);
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
free(host_a);
free(host_b);
free(host_c);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__sum_matricesPfS_S_ii # -- Begin function _Z27__device_stub__sum_matricesPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__sum_matricesPfS_S_ii,@function
_Z27__device_stub__sum_matricesPfS_S_ii: # @_Z27__device_stub__sum_matricesPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sum_matricesPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__sum_matricesPfS_S_ii, .Lfunc_end0-_Z27__device_stub__sum_matricesPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%rbx,%r12,4) # imm = 0x40000000
movl $1082130432, (%r14,%r12,4) # imm = 0x40800000
incq %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_1
# %bb.2:
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movq $0, 8(%rsp)
leaq 32(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 32(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $17179869188, %rdi # imm = 0x400000004
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $64, 52(%rsp)
movl $64, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12sum_matricesPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_15
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $20, %r12
jne .LBB1_9
# %bb.10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r12)
je .LBB1_13
# %bb.12:
movzbl 67(%r12), %eax
jmp .LBB1_14
.LBB1_13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sum_matricesPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sum_matricesPfS_S_ii,@object # @_Z12sum_matricesPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12sum_matricesPfS_S_ii
.p2align 3, 0x0
_Z12sum_matricesPfS_S_ii:
.quad _Z27__device_stub__sum_matricesPfS_S_ii
.size _Z12sum_matricesPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time = "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sum_matricesPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sum_matricesPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sum_matricesPfS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12sum_matricesPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sum_matricesPfS_S_ii
.globl _Z12sum_matricesPfS_S_ii
.p2align 8
.type _Z12sum_matricesPfS_S_ii,@function
_Z12sum_matricesPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sum_matricesPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sum_matricesPfS_S_ii, .Lfunc_end0-_Z12sum_matricesPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sum_matricesPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sum_matricesPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00148b6b_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4289:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4289:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii:
.LFB4311:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sum_matricesPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4311:
.size _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
.globl _Z12sum_matricesPfS_S_ii
.type _Z12sum_matricesPfS_S_ii, @function
_Z12sum_matricesPfS_S_ii:
.LFB4312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4312:
.size _Z12sum_matricesPfS_S_ii, .-_Z12sum_matricesPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Time = "
.LC4:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4286:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 56(%rsp)
movl $4, 60(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
movl $16384, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
movl $0x00000000, (%rbx,%rax)
addq $4, %rax
cmpq $16384, %rax
jne .L12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $16384, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %r13
leaq 80(%rbx), %r15
leaq _ZSt4cout(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %r13
cmpq %r15, %r13
jne .L14
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %r8d
movl $64, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z12sum_matricesPfS_S_iiPfS_S_ii
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4286:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12sum_matricesPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4314:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sum_matricesPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4314:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.align 4
.LC1:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__sum_matricesPfS_S_ii # -- Begin function _Z27__device_stub__sum_matricesPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__sum_matricesPfS_S_ii,@function
_Z27__device_stub__sum_matricesPfS_S_ii: # @_Z27__device_stub__sum_matricesPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sum_matricesPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__sum_matricesPfS_S_ii, .Lfunc_end0-_Z27__device_stub__sum_matricesPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%rbx,%r12,4) # imm = 0x40000000
movl $1082130432, (%r14,%r12,4) # imm = 0x40800000
incq %r12
cmpq $4096, %r12 # imm = 0x1000
jne .LBB1_1
# %bb.2:
movq $0, 32(%rsp)
movq $0, 24(%rsp)
movq $0, 8(%rsp)
leaq 32(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq 32(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $17179869188, %rdi # imm = 0x400000004
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $64, 52(%rsp)
movl $64, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12sum_matricesPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_15
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $20, %r12
jne .LBB1_9
# %bb.10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r12)
je .LBB1_13
# %bb.12:
movzbl 67(%r12), %eax
jmp .LBB1_14
.LBB1_13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sum_matricesPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sum_matricesPfS_S_ii,@object # @_Z12sum_matricesPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12sum_matricesPfS_S_ii
.p2align 3, 0x0
_Z12sum_matricesPfS_S_ii:
.quad _Z27__device_stub__sum_matricesPfS_S_ii
.size _Z12sum_matricesPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time = "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sum_matricesPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sum_matricesPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sum_matricesPfS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* GPU vector add test program for CUDA */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
static int nblock_size = 64;
static int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static cudaError_t crc;
/*--------------------------------------------------------------------*/
__global__ void gadd(float a[], float b[], float c[], int nx) {
int j;
j = threadIdx.x+blockDim.x*blockIdx.x;
if (j < nx)
a[j] = b[j] + c[j];
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpadd(float *a, float *b, float *c, int nx) {
/* Vector Add Interface for C */
dim3 dimBlock(nblock_size);
dim3 dimGrid((nx - 1)/nblock_size + 1);
gadd<<<dimGrid,dimBlock>>>(a,b,c,nx);
cudaThreadSynchronize();
return;
}
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = cudaGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
cudaThreadSynchronize();
crc = cudaGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct cudaDeviceProp prop;
/* returns number of device */
crc = cudaGetDeviceCount(&ndevs);
if (crc) {
printf("cudaGetDeviceCount Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = cudaGetDeviceProperties(&prop,j);
if (crc) {
printf("cudaGetDeviceProperties Error=%i:%s\n",crc,
cudaGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = cudaGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = cudaSetDevice(devid);
if (crc) {
printf("cudaSetDevice Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
crc = cudaThreadExit();
if (crc) {
printf("cudaThreadExit Error=%d:%s\n",crc,cudaGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize(int nblock) {
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("cudaMalloc float Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(float **g_f, int *irc) {
/* deallocate global memory on GPU, return pointer to C */
crc = cudaFree((void *)*g_f);
if (crc) {
printf("cudaFree Error=%d:%s\n",crc,cudaGetErrorString(crc));
*irc = 1;
}
*g_f = NULL;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpadd_(unsigned long *gp_a, unsigned long *gp_b,
unsigned long *gp_c, int *nx) {
/* Vector Add Interface for Fortran */
float *a, *b, *c;
a = (float *)*gp_a;
b = (float *)*gp_b;
c = (float *)*gp_c;
gpadd(a,b,c,*nx);
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize_(int *nblock) {
setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_f, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
float *f;
f = (float *)*gp_f;
gpu_deallocate(&f,irc);
*gp_f = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
} | code for sm_80
Function : _Z11emptyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4gaddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* GPU vector add test program for CUDA */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
static int nblock_size = 64;
static int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static cudaError_t crc;
/*--------------------------------------------------------------------*/
__global__ void gadd(float a[], float b[], float c[], int nx) {
int j;
j = threadIdx.x+blockDim.x*blockIdx.x;
if (j < nx)
a[j] = b[j] + c[j];
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpadd(float *a, float *b, float *c, int nx) {
/* Vector Add Interface for C */
dim3 dimBlock(nblock_size);
dim3 dimGrid((nx - 1)/nblock_size + 1);
gadd<<<dimGrid,dimBlock>>>(a,b,c,nx);
cudaThreadSynchronize();
return;
}
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = cudaGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
cudaThreadSynchronize();
crc = cudaGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct cudaDeviceProp prop;
/* returns number of device */
crc = cudaGetDeviceCount(&ndevs);
if (crc) {
printf("cudaGetDeviceCount Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = cudaGetDeviceProperties(&prop,j);
if (crc) {
printf("cudaGetDeviceProperties Error=%i:%s\n",crc,
cudaGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = cudaGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = cudaSetDevice(devid);
if (crc) {
printf("cudaSetDevice Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
crc = cudaThreadExit();
if (crc) {
printf("cudaThreadExit Error=%d:%s\n",crc,cudaGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize(int nblock) {
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("cudaMalloc float Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(float **g_f, int *irc) {
/* deallocate global memory on GPU, return pointer to C */
crc = cudaFree((void *)*g_f);
if (crc) {
printf("cudaFree Error=%d:%s\n",crc,cudaGetErrorString(crc));
*irc = 1;
}
*g_f = NULL;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpadd_(unsigned long *gp_a, unsigned long *gp_b,
unsigned long *gp_c, int *nx) {
/* Vector Add Interface for Fortran */
float *a, *b, *c;
a = (float *)*gp_a;
b = (float *)*gp_b;
c = (float *)*gp_c;
gpadd(a,b,c,*nx);
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize_(int *nblock) {
setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_f, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
float *f;
f = (float *)*gp_f;
gpu_deallocate(&f,irc);
*gp_f = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
} | .file "tmpxft_0016a191_00000000-6_gpulib_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaThreadExit Error=%d:%s\n"
.text
.globl end_cu
.type end_cu, @function
end_cu:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaThreadExit@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L6
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2060:
.size end_cu, .-end_cu
.globl setgbsize
.type setgbsize, @function
setgbsize:
.LFB2061:
.cfi_startproc
endbr64
movl %edi, _ZL11nblock_size(%rip)
ret
.cfi_endproc
.LFE2061:
.size setgbsize, .-setgbsize
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaMalloc float Error=%d:%s,l=%d\n"
.text
.globl gpu_fallocate
.type gpu_fallocate, @function
gpu_fallocate:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L12
.L9:
movq (%rsp), %rax
movq %rax, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %r8d
movl _ZL3crc(%rip), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, (%r12)
jmp .L9
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size gpu_fallocate, .-gpu_fallocate
.section .rodata.str1.1
.LC2:
.string "cudaFree Error=%d:%s\n"
.text
.globl gpu_deallocate
.type gpu_deallocate, @function
gpu_deallocate:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movq (%rdi), %rdi
call cudaFree@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L17
.L15:
movq $0, (%rbx)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 0(%rbp)
jmp .L15
.cfi_endproc
.LFE2063:
.size gpu_deallocate, .-gpu_deallocate
.section .rodata.str1.8
.align 8
.LC3:
.string "cudaMemcpyHostToDevice float Error=%d:%s\n"
.text
.globl gpu_fcopyin
.type gpu_fcopyin, @function
gpu_fcopyin:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L21
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size gpu_fcopyin, .-gpu_fcopyin
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaMemcpyDeviceToHost float Error=%d:%s\n"
.text
.globl gpu_fcopyout
.type gpu_fcopyout, @function
gpu_fcopyout:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L25
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size gpu_fcopyout, .-gpu_fcopyout
.globl end_cu_
.type end_cu_, @function
end_cu_:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call end_cu
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size end_cu_, .-end_cu_
.globl setgbsize_
.type setgbsize_, @function
setgbsize_:
.LFB2069:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl %eax, _ZL11nblock_size(%rip)
ret
.cfi_endproc
.LFE2069:
.size setgbsize_, .-setgbsize_
.globl gpu_fallocate_
.type gpu_fallocate_, @function
gpu_fallocate_:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl (%rsi), %esi
movq %rsp, %rdi
call gpu_fallocate
movq (%rsp), %rax
movq %rax, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size gpu_fallocate_, .-gpu_fallocate_
.globl gpu_deallocate_
.type gpu_deallocate_, @function
gpu_deallocate_:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq (%rdi), %rax
movq %rax, (%rsp)
movq %rsp, %rdi
call gpu_deallocate
movq $0, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size gpu_deallocate_, .-gpu_deallocate_
.globl gpu_fcopyin_
.type gpu_fcopyin_, @function
gpu_fcopyin_:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_fcopyin
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size gpu_fcopyin_, .-gpu_fcopyin_
.globl gpu_fcopyout_
.type gpu_fcopyout_, @function
gpu_fcopyout_:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_fcopyout
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size gpu_fcopyout_, .-gpu_fcopyout_
.globl _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
.type _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4gaddPfS_S_iPfS_S_i:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4gaddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i, .-_Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
.globl _Z4gaddPfS_S_i
.type _Z4gaddPfS_S_i, @function
_Z4gaddPfS_S_i:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z4gaddPfS_S_i, .-_Z4gaddPfS_S_i
.globl gpadd
.type gpadd, @function
gpadd:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl _ZL11nblock_size(%rip), %ecx
movl %ecx, 8(%rsp)
movl $1, 12(%rsp)
leal -1(%rbx), %eax
cltd
idivl %ecx
addl $1, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L50:
call cudaThreadSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
jmp .L50
.cfi_endproc
.LFE2057:
.size gpadd, .-gpadd
.globl gpadd_
.type gpadd_, @function
gpadd_:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rcx), %ecx
movq (%rdx), %rdx
movq (%rsi), %rsi
movq (%rdi), %rdi
call gpadd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size gpadd_, .-gpadd_
.globl _Z30__device_stub__Z11emptyKernelvv
.type _Z30__device_stub__Z11emptyKernelvv, @function
_Z30__device_stub__Z11emptyKernelvv:
.LFB2100:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11emptyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z30__device_stub__Z11emptyKernelvv, .-_Z30__device_stub__Z11emptyKernelvv
.globl _Z11emptyKernelv
.type _Z11emptyKernelv, @function
_Z11emptyKernelv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11emptyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z11emptyKernelv, .-_Z11emptyKernelv
.section .rodata.str1.1
.LC5:
.string "emptyKernel error=%d:%s\n"
.text
.globl emptykernel
.type emptykernel, @function
emptykernel:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl _ZL11nblock_size(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32768, %edx
cmpl %edx, %eax
cmovg %edx, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L64:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L68
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
call _Z30__device_stub__Z11emptyKernelvv
jmp .L64
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size emptykernel, .-emptykernel
.section .rodata.str1.8
.align 8
.LC6:
.string "cudaGetDeviceCount Error=%i:%s\n"
.align 8
.LC7:
.string "cudaGetDeviceProperties Error=%i:%s\n"
.align 8
.LC8:
.string "j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n"
.align 8
.LC10:
.string " CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n"
.section .rodata.str1.1
.LC11:
.string "using device j=%i\n"
.LC12:
.string "cudaSetDevice Error=%i:%s\n"
.text
.globl init_cu
.type init_cu, @function
init_cu:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1080, %rsp
.cfi_def_cfa_offset 1136
movl %edi, %ebp
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L70
movl 28(%rsp), %ecx
movl $0, %ebx
movl $-1, %r13d
movl $0, %r14d
leaq .LC7(%rip), %r15
testl %ecx, %ecx
jg .L71
.L72:
testl %ebp, %ebp
js .L78
movl %ebp, %eax
cltd
idivl %ecx
movl %edx, %r13d
.L78:
movl %r13d, _ZL5devid(%rip)
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl _ZL5devid(%rip), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, _ZL3crc(%rip)
movl 368(%rsp), %eax
movl %eax, maxgsx(%rip)
movl 392(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 396(%rsp), %eax
leal (%rax,%rdx,2), %eax
movl %eax, mmcc(%rip)
movl _ZL5devid(%rip), %edi
call cudaSetDevice@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L87
call emptykernel
.L69:
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L73
.L74:
testl %ebp, %ebp
jle .L89
.L75:
addl $1, %ebx
movl 28(%rsp), %ecx
cmpl %ebx, %ecx
jle .L72
.L71:
leaq 32(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
je .L74
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 32(%rsp)
jmp .L74
.L89:
movl 420(%rsp), %r12d
leaq 32(%rsp), %rcx
movl %r12d, %r8d
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
movl 392(%rsp), %eax
leal (%rax,%rax,4), %ecx
movl 396(%rsp), %eax
leal (%rax,%rcx,2), %ecx
movl %ecx, mmcc(%rip)
testq %rdx, %rdx
js .L76
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L77:
mulsd .LC9(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %r14d, %r12d
jle .L75
movl %ebx, %r13d
movl %r12d, %r14d
jmp .L75
.L76:
movq %rdx, %rax
shrq %rax
movq %rdx, %rsi
andl $1, %esi
orq %rsi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L77
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L73:
movq 8(%rsp), %rax
movl $1, (%rax)
jmp .L69
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size init_cu, .-init_cu
.globl init_cu_
.type init_cu_, @function
init_cu_:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdi), %edi
call init_cu
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size init_cu_, .-init_cu_
.section .rodata.str1.1
.LC13:
.string "_Z11emptyKernelv"
.LC14:
.string "_Z4gaddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11emptyKernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gaddPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3crc
.comm _ZL3crc,4,4
.local _ZL5devid
.comm _ZL5devid,4,4
.globl mmcc
.bss
.align 4
.type mmcc, @object
.size mmcc, 4
mmcc:
.zero 4
.globl maxgsx
.data
.align 4
.type maxgsx, @object
.size maxgsx, 4
maxgsx:
.long 65535
.align 4
.type _ZL11nblock_size, @object
.size _ZL11nblock_size, 4
_ZL11nblock_size:
.long 64
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* GPU vector add test program for CUDA */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
static int nblock_size = 64;
static int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static cudaError_t crc;
/*--------------------------------------------------------------------*/
__global__ void gadd(float a[], float b[], float c[], int nx) {
int j;
j = threadIdx.x+blockDim.x*blockIdx.x;
if (j < nx)
a[j] = b[j] + c[j];
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpadd(float *a, float *b, float *c, int nx) {
/* Vector Add Interface for C */
dim3 dimBlock(nblock_size);
dim3 dimGrid((nx - 1)/nblock_size + 1);
gadd<<<dimGrid,dimBlock>>>(a,b,c,nx);
cudaThreadSynchronize();
return;
}
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = cudaGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
cudaThreadSynchronize();
crc = cudaGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct cudaDeviceProp prop;
/* returns number of device */
crc = cudaGetDeviceCount(&ndevs);
if (crc) {
printf("cudaGetDeviceCount Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = cudaGetDeviceProperties(&prop,j);
if (crc) {
printf("cudaGetDeviceProperties Error=%i:%s\n",crc,
cudaGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = cudaGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = cudaSetDevice(devid);
if (crc) {
printf("cudaSetDevice Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
crc = cudaThreadExit();
if (crc) {
printf("cudaThreadExit Error=%d:%s\n",crc,cudaGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize(int nblock) {
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("cudaMalloc float Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(float **g_f, int *irc) {
/* deallocate global memory on GPU, return pointer to C */
crc = cudaFree((void *)*g_f);
if (crc) {
printf("cudaFree Error=%d:%s\n",crc,cudaGetErrorString(crc));
*irc = 1;
}
*g_f = NULL;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpadd_(unsigned long *gp_a, unsigned long *gp_b,
unsigned long *gp_c, int *nx) {
/* Vector Add Interface for Fortran */
float *a, *b, *c;
a = (float *)*gp_a;
b = (float *)*gp_b;
c = (float *)*gp_c;
gpadd(a,b,c,*nx);
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize_(int *nblock) {
setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_f, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
float *f;
f = (float *)*gp_f;
gpu_deallocate(&f,irc);
*gp_f = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
} | /* GPU vector add test program for CUDA */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
static int nblock_size = 64;
static int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static hipError_t crc;
/*--------------------------------------------------------------------*/
__global__ void gadd(float a[], float b[], float c[], int nx) {
int j;
j = threadIdx.x+blockDim.x*blockIdx.x;
if (j < nx)
a[j] = b[j] + c[j];
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpadd(float *a, float *b, float *c, int nx) {
/* Vector Add Interface for C */
dim3 dimBlock(nblock_size);
dim3 dimGrid((nx - 1)/nblock_size + 1);
gadd<<<dimGrid,dimBlock>>>(a,b,c,nx);
hipDeviceSynchronize();
return;
}
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = hipGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
crc = hipGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct hipDeviceProp_t prop;
/* returns number of device */
crc = hipGetDeviceCount(&ndevs);
if (crc) {
printf("hipGetDeviceCount Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = hipGetDeviceProperties(&prop,j);
if (crc) {
printf("hipGetDeviceProperties Error=%i:%s\n",crc,
hipGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = hipGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = hipSetDevice(devid);
if (crc) {
printf("hipSetDevice Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
crc = hipDeviceReset();
if (crc) {
printf("hipDeviceReset Error=%d:%s\n",crc,hipGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize(int nblock) {
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("hipMalloc float Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(float **g_f, int *irc) {
/* deallocate global memory on GPU, return pointer to C */
crc = hipFree((void *)*g_f);
if (crc) {
printf("hipFree Error=%d:%s\n",crc,hipGetErrorString(crc));
*irc = 1;
}
*g_f = NULL;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpadd_(unsigned long *gp_a, unsigned long *gp_b,
unsigned long *gp_c, int *nx) {
/* Vector Add Interface for Fortran */
float *a, *b, *c;
a = (float *)*gp_a;
b = (float *)*gp_b;
c = (float *)*gp_c;
gpadd(a,b,c,*nx);
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize_(int *nblock) {
setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_f, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
float *f;
f = (float *)*gp_f;
gpu_deallocate(&f,irc);
*gp_f = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* GPU vector add test program for CUDA */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
static int nblock_size = 64;
static int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static hipError_t crc;
/*--------------------------------------------------------------------*/
__global__ void gadd(float a[], float b[], float c[], int nx) {
int j;
j = threadIdx.x+blockDim.x*blockIdx.x;
if (j < nx)
a[j] = b[j] + c[j];
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpadd(float *a, float *b, float *c, int nx) {
/* Vector Add Interface for C */
dim3 dimBlock(nblock_size);
dim3 dimGrid((nx - 1)/nblock_size + 1);
gadd<<<dimGrid,dimBlock>>>(a,b,c,nx);
hipDeviceSynchronize();
return;
}
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = hipGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
crc = hipGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct hipDeviceProp_t prop;
/* returns number of device */
crc = hipGetDeviceCount(&ndevs);
if (crc) {
printf("hipGetDeviceCount Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = hipGetDeviceProperties(&prop,j);
if (crc) {
printf("hipGetDeviceProperties Error=%i:%s\n",crc,
hipGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = hipGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = hipSetDevice(devid);
if (crc) {
printf("hipSetDevice Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
crc = hipDeviceReset();
if (crc) {
printf("hipDeviceReset Error=%d:%s\n",crc,hipGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize(int nblock) {
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("hipMalloc float Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(float **g_f, int *irc) {
/* deallocate global memory on GPU, return pointer to C */
crc = hipFree((void *)*g_f);
if (crc) {
printf("hipFree Error=%d:%s\n",crc,hipGetErrorString(crc));
*irc = 1;
}
*g_f = NULL;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpadd_(unsigned long *gp_a, unsigned long *gp_b,
unsigned long *gp_c, int *nx) {
/* Vector Add Interface for Fortran */
float *a, *b, *c;
a = (float *)*gp_a;
b = (float *)*gp_b;
c = (float *)*gp_c;
gpadd(a,b,c,*nx);
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize_(int *nblock) {
setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_f, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
float *f;
f = (float *)*gp_f;
gpu_deallocate(&f,irc);
*gp_f = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gaddPfS_S_i
.globl _Z4gaddPfS_S_i
.p2align 8
.type _Z4gaddPfS_S_i,@function
_Z4gaddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gaddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gaddPfS_S_i, .Lfunc_end0-_Z4gaddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11emptyKernelv
.globl _Z11emptyKernelv
.p2align 8
.type _Z11emptyKernelv,@function
_Z11emptyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11emptyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11emptyKernelv, .Lfunc_end1-_Z11emptyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gaddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gaddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11emptyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11emptyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* GPU vector add test program for CUDA */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
static int nblock_size = 64;
static int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static hipError_t crc;
/*--------------------------------------------------------------------*/
__global__ void gadd(float a[], float b[], float c[], int nx) {
int j;
j = threadIdx.x+blockDim.x*blockIdx.x;
if (j < nx)
a[j] = b[j] + c[j];
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpadd(float *a, float *b, float *c, int nx) {
/* Vector Add Interface for C */
dim3 dimBlock(nblock_size);
dim3 dimGrid((nx - 1)/nblock_size + 1);
gadd<<<dimGrid,dimBlock>>>(a,b,c,nx);
hipDeviceSynchronize();
return;
}
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = hipGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
crc = hipGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct hipDeviceProp_t prop;
/* returns number of device */
crc = hipGetDeviceCount(&ndevs);
if (crc) {
printf("hipGetDeviceCount Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = hipGetDeviceProperties(&prop,j);
if (crc) {
printf("hipGetDeviceProperties Error=%i:%s\n",crc,
hipGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = hipGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = hipSetDevice(devid);
if (crc) {
printf("hipSetDevice Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
crc = hipDeviceReset();
if (crc) {
printf("hipDeviceReset Error=%d:%s\n",crc,hipGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize(int nblock) {
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("hipMalloc float Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(float **g_f, int *irc) {
/* deallocate global memory on GPU, return pointer to C */
crc = hipFree((void *)*g_f);
if (crc) {
printf("hipFree Error=%d:%s\n",crc,hipGetErrorString(crc));
*irc = 1;
}
*g_f = NULL;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpadd_(unsigned long *gp_a, unsigned long *gp_b,
unsigned long *gp_c, int *nx) {
/* Vector Add Interface for Fortran */
float *a, *b, *c;
a = (float *)*gp_a;
b = (float *)*gp_b;
c = (float *)*gp_c;
gpadd(a,b,c,*nx);
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void setgbsize_(int *nblock) {
setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_f, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
float *f;
f = (float *)*gp_f;
gpu_deallocate(&f,irc);
*gp_f = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
} | .text
.file "gpulib_cu.hip"
.globl _Z19__device_stub__gaddPfS_S_i # -- Begin function _Z19__device_stub__gaddPfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__gaddPfS_S_i,@function
_Z19__device_stub__gaddPfS_S_i: # @_Z19__device_stub__gaddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4gaddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__gaddPfS_S_i, .Lfunc_end0-_Z19__device_stub__gaddPfS_S_i
.cfi_endproc
# -- End function
.globl gpadd # -- Begin function gpadd
.p2align 4, 0x90
.type gpadd,@function
gpadd: # @gpadd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl _ZL11nblock_size(%rip), %ecx
movabsq $4294967296, %rsi # imm = 0x100000000
leal -1(%rbx), %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movq %rcx, %rdx
orq %rsi, %rdx
leal 1(%rax), %edi
orq %rsi, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4gaddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size gpadd, .Lfunc_end1-gpadd
.cfi_endproc
# -- End function
.globl _Z26__device_stub__emptyKernelv # -- Begin function _Z26__device_stub__emptyKernelv
.p2align 4, 0x90
.type _Z26__device_stub__emptyKernelv,@function
_Z26__device_stub__emptyKernelv: # @_Z26__device_stub__emptyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z26__device_stub__emptyKernelv, .Lfunc_end2-_Z26__device_stub__emptyKernelv
.cfi_endproc
# -- End function
.globl emptykernel # -- Begin function emptykernel
.p2align 4, 0x90
.type emptykernel,@function
emptykernel: # @emptykernel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl _ZL11nblock_size(%rip), %ebx
cmpl $32768, %ebx # imm = 0x8000
movl $32768, %r14d # imm = 0x8000
cmovll %ebx, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
orq %rax, %r14
callq hipGetLastError
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_4
# %bb.3:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_4:
.cfi_def_cfa_offset 80
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size emptykernel, .Lfunc_end3-emptykernel
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function init_cu
.LCPI4_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI4_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl init_cu
.p2align 4, 0x90
.type init_cu,@function
init_cu: # @init_cu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB4_1
# %bb.14:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%rbx)
jmp .LBB4_13
.LBB4_1: # %.preheader
movq %rbx, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %ecx
movl $-1, %r14d
testl %ecx, %ecx
jle .LBB4_8
# %bb.2: # %.lr.ph
leaq 24(%rsp), %r15
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_3 Depth=1
incl %r12d
movl 12(%rsp), %ecx
cmpl %ecx, %r12d
jge .LBB4_8
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movl %eax, %edi
movl %eax, %r13d
callq hipGetErrorString
movl $.L.str.2, %edi
movl %r13d, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movb $0, 24(%rsp)
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
testl %ebp, %ebp
jg .LBB4_7
# %bb.6: # in Loop: Header=BB4_3 Depth=1
movl 412(%rsp), %r13d
movl $.L.str.3, %edi
movl %r12d, %esi
movq %r15, %rdx
movl %r13d, %ecx
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movq %rsi, %xmm0
punpckldq .LCPI4_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI4_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
mulsd .LCPI4_2(%rip), %xmm1
movl 384(%rsp), %eax
leal (%rax,%rax,4), %edx
addl %edx, %edx
addl 388(%rsp), %edx
movl %edx, mmcc(%rip)
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
cmpl %ebx, %r13d
cmovgl %r12d, %r14d
cmovgl %r13d, %ebx
jmp .LBB4_7
.LBB4_8: # %._crit_edge
testl %ebp, %ebp
js .LBB4_10
# %bb.9:
movl %ebp, %eax
cltd
idivl %ecx
movl %edx, %r14d
.LBB4_10:
movl %r14d, _ZL5devid(%rip)
movl $.L.str.5, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl _ZL5devid(%rip), %esi
leaq 24(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 360(%rsp), %eax
movl 384(%rsp), %ecx
movl %eax, maxgsx(%rip)
leal (%rcx,%rcx,4), %eax
addl %eax, %eax
addl 388(%rsp), %eax
movl %eax, mmcc(%rip)
movl _ZL5devid(%rip), %edi
callq hipSetDevice
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax # 8-byte Reload
movl $1, (%rax)
jmp .LBB4_13
.LBB4_12:
callq emptykernel
.LBB4_13:
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size init_cu, .Lfunc_end4-init_cu
.cfi_endproc
# -- End function
.globl end_cu # -- Begin function end_cu
.p2align 4, 0x90
.type end_cu,@function
end_cu: # @end_cu
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
testl %eax, %eax
je .LBB5_1
# %bb.2:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.7, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB5_1:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size end_cu, .Lfunc_end5-end_cu
.cfi_endproc
# -- End function
.globl setgbsize # -- Begin function setgbsize
.p2align 4, 0x90
.type setgbsize,@function
setgbsize: # @setgbsize
.cfi_startproc
# %bb.0:
movl %edi, _ZL11nblock_size(%rip)
retq
.Lfunc_end6:
.size setgbsize, .Lfunc_end6-setgbsize
.cfi_endproc
# -- End function
.globl gpu_fallocate # -- Begin function gpu_fallocate
.p2align 4, 0x90
.type gpu_fallocate,@function
gpu_fallocate: # @gpu_fallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB7_2
# %bb.1:
movl %eax, %edi
movl %eax, %r15d
callq hipGetErrorString
movl $.L.str.8, %edi
movl %r15d, %esi
movq %rax, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB7_2:
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size gpu_fallocate, .Lfunc_end7-gpu_fallocate
.cfi_endproc
# -- End function
.globl gpu_deallocate # -- Begin function gpu_deallocate
.p2align 4, 0x90
.type gpu_deallocate,@function
gpu_deallocate: # @gpu_deallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
callq hipFree
testl %eax, %eax
je .LBB8_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB8_2:
movq $0, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size gpu_deallocate, .Lfunc_end8-gpu_deallocate
.cfi_endproc
# -- End function
.globl gpu_fcopyin # -- Begin function gpu_fcopyin
.p2align 4, 0x90
.type gpu_fcopyin,@function
gpu_fcopyin: # @gpu_fcopyin
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movslq %edx, %rdx
shlq $2, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB9_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB9_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.10, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end9:
.size gpu_fcopyin, .Lfunc_end9-gpu_fcopyin
.cfi_endproc
# -- End function
.globl gpu_fcopyout # -- Begin function gpu_fcopyout
.p2align 4, 0x90
.type gpu_fcopyout,@function
gpu_fcopyout: # @gpu_fcopyout
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq %edx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end10:
.size gpu_fcopyout, .Lfunc_end10-gpu_fcopyout
.cfi_endproc
# -- End function
.globl gpadd_ # -- Begin function gpadd_
.p2align 4, 0x90
.type gpadd_,@function
gpadd_: # @gpadd_
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
movq (%rsi), %rsi
movq (%rdx), %rdx
movl (%rcx), %ecx
jmp gpadd # TAILCALL
.Lfunc_end11:
.size gpadd_, .Lfunc_end11-gpadd_
.cfi_endproc
# -- End function
.globl init_cu_ # -- Begin function init_cu_
.p2align 4, 0x90
.type init_cu_,@function
init_cu_: # @init_cu_
.cfi_startproc
# %bb.0:
movl (%rdi), %edi
jmp init_cu # TAILCALL
.Lfunc_end12:
.size init_cu_, .Lfunc_end12-init_cu_
.cfi_endproc
# -- End function
.globl end_cu_ # -- Begin function end_cu_
.p2align 4, 0x90
.type end_cu_,@function
end_cu_: # @end_cu_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
testl %eax, %eax
je .LBB13_1
# %bb.2:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.7, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB13_1: # %end_cu.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end13:
.size end_cu_, .Lfunc_end13-end_cu_
.cfi_endproc
# -- End function
.globl setgbsize_ # -- Begin function setgbsize_
.p2align 4, 0x90
.type setgbsize_,@function
setgbsize_: # @setgbsize_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl %eax, _ZL11nblock_size(%rip)
retq
.Lfunc_end14:
.size setgbsize_, .Lfunc_end14-setgbsize_
.cfi_endproc
# -- End function
.globl gpu_fallocate_ # -- Begin function gpu_fallocate_
.p2align 4, 0x90
.type gpu_fallocate_,@function
gpu_fallocate_: # @gpu_fallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movq %rdi, %rbx
movslq (%rsi), %r15
leaq (,%r15,4), %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB15_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %edi
movl %ebp, %esi
movq %rax, %rdx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB15_2: # %gpu_fallocate.exit
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end15:
.size gpu_fallocate_, .Lfunc_end15-gpu_fallocate_
.cfi_endproc
# -- End function
.globl gpu_deallocate_ # -- Begin function gpu_deallocate_
.p2align 4, 0x90
.type gpu_deallocate_,@function
gpu_deallocate_: # @gpu_deallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
callq hipFree
testl %eax, %eax
je .LBB16_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB16_2: # %gpu_deallocate.exit
movq $0, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end16:
.size gpu_deallocate_, .Lfunc_end16-gpu_deallocate_
.cfi_endproc
# -- End function
.globl gpu_fcopyin_ # -- Begin function gpu_fcopyin_
.p2align 4, 0x90
.type gpu_fcopyin_,@function
gpu_fcopyin_: # @gpu_fcopyin_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movq (%rsi), %rdi
movslq (%rdx), %rdx
shlq $2, %rdx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB17_2
# %bb.1: # %gpu_fcopyin.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB17_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.10, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end17:
.size gpu_fcopyin_, .Lfunc_end17-gpu_fcopyin_
.cfi_endproc
# -- End function
.globl gpu_fcopyout_ # -- Begin function gpu_fcopyout_
.p2align 4, 0x90
.type gpu_fcopyout_,@function
gpu_fcopyout_: # @gpu_fcopyout_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movslq (%rdx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB18_2
# %bb.1: # %gpu_fcopyout.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB18_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end18:
.size gpu_fcopyout_, .Lfunc_end18-gpu_fcopyout_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB19_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB19_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gaddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11emptyKernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end19:
.size __hip_module_ctor, .Lfunc_end19-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB20_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB20_2:
retq
.Lfunc_end20:
.size __hip_module_dtor, .Lfunc_end20-__hip_module_dtor
.cfi_endproc
# -- End function
.type maxgsx,@object # @maxgsx
.data
.globl maxgsx
.p2align 2, 0x0
maxgsx:
.long 65535 # 0xffff
.size maxgsx, 4
.type mmcc,@object # @mmcc
.bss
.globl mmcc
.p2align 2, 0x0
mmcc:
.long 0 # 0x0
.size mmcc, 4
.type _Z4gaddPfS_S_i,@object # @_Z4gaddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z4gaddPfS_S_i
.p2align 3, 0x0
_Z4gaddPfS_S_i:
.quad _Z19__device_stub__gaddPfS_S_i
.size _Z4gaddPfS_S_i, 8
.type _ZL11nblock_size,@object # @_ZL11nblock_size
.data
.p2align 2, 0x0
_ZL11nblock_size:
.long 64 # 0x40
.size _ZL11nblock_size, 4
.type _Z11emptyKernelv,@object # @_Z11emptyKernelv
.section .rodata,"a",@progbits
.globl _Z11emptyKernelv
.p2align 3, 0x0
_Z11emptyKernelv:
.quad _Z26__device_stub__emptyKernelv
.size _Z11emptyKernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "emptyKernel error=%d:%s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount Error=%i:%s\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipGetDeviceProperties Error=%i:%s\n"
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n"
.size .L.str.3, 55
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n"
.size .L.str.4, 51
.type _ZL5devid,@object # @_ZL5devid
.local _ZL5devid
.comm _ZL5devid,4,4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "using device j=%i\n"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice Error=%i:%s\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceReset Error=%d:%s\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc float Error=%d:%s,l=%d\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipFree Error=%d:%s\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMemcpyHostToDevice float Error=%d:%s\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipMemcpyDeviceToHost float Error=%d:%s\n"
.size .L.str.11, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4gaddPfS_S_i"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11emptyKernelv"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gaddPfS_S_i
.addrsig_sym _Z26__device_stub__emptyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gaddPfS_S_i
.addrsig_sym _Z11emptyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11emptyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4gaddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gaddPfS_S_i
.globl _Z4gaddPfS_S_i
.p2align 8
.type _Z4gaddPfS_S_i,@function
_Z4gaddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gaddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gaddPfS_S_i, .Lfunc_end0-_Z4gaddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11emptyKernelv
.globl _Z11emptyKernelv
.p2align 8
.type _Z11emptyKernelv,@function
_Z11emptyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11emptyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11emptyKernelv, .Lfunc_end1-_Z11emptyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gaddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gaddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11emptyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11emptyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016a191_00000000-6_gpulib_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaThreadExit Error=%d:%s\n"
.text
.globl end_cu
.type end_cu, @function
end_cu:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaThreadExit@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L6
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2060:
.size end_cu, .-end_cu
.globl setgbsize
.type setgbsize, @function
setgbsize:
.LFB2061:
.cfi_startproc
endbr64
movl %edi, _ZL11nblock_size(%rip)
ret
.cfi_endproc
.LFE2061:
.size setgbsize, .-setgbsize
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaMalloc float Error=%d:%s,l=%d\n"
.text
.globl gpu_fallocate
.type gpu_fallocate, @function
gpu_fallocate:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L12
.L9:
movq (%rsp), %rax
movq %rax, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %r8d
movl _ZL3crc(%rip), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, (%r12)
jmp .L9
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size gpu_fallocate, .-gpu_fallocate
.section .rodata.str1.1
.LC2:
.string "cudaFree Error=%d:%s\n"
.text
.globl gpu_deallocate
.type gpu_deallocate, @function
gpu_deallocate:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movq (%rdi), %rdi
call cudaFree@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L17
.L15:
movq $0, (%rbx)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 0(%rbp)
jmp .L15
.cfi_endproc
.LFE2063:
.size gpu_deallocate, .-gpu_deallocate
.section .rodata.str1.8
.align 8
.LC3:
.string "cudaMemcpyHostToDevice float Error=%d:%s\n"
.text
.globl gpu_fcopyin
.type gpu_fcopyin, @function
gpu_fcopyin:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L21
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size gpu_fcopyin, .-gpu_fcopyin
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaMemcpyDeviceToHost float Error=%d:%s\n"
.text
.globl gpu_fcopyout
.type gpu_fcopyout, @function
gpu_fcopyout:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L25
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size gpu_fcopyout, .-gpu_fcopyout
.globl end_cu_
.type end_cu_, @function
end_cu_:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call end_cu
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size end_cu_, .-end_cu_
.globl setgbsize_
.type setgbsize_, @function
setgbsize_:
.LFB2069:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl %eax, _ZL11nblock_size(%rip)
ret
.cfi_endproc
.LFE2069:
.size setgbsize_, .-setgbsize_
.globl gpu_fallocate_
.type gpu_fallocate_, @function
gpu_fallocate_:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl (%rsi), %esi
movq %rsp, %rdi
call gpu_fallocate
movq (%rsp), %rax
movq %rax, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size gpu_fallocate_, .-gpu_fallocate_
.globl gpu_deallocate_
.type gpu_deallocate_, @function
gpu_deallocate_:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq (%rdi), %rax
movq %rax, (%rsp)
movq %rsp, %rdi
call gpu_deallocate
movq $0, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size gpu_deallocate_, .-gpu_deallocate_
.globl gpu_fcopyin_
.type gpu_fcopyin_, @function
gpu_fcopyin_:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_fcopyin
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size gpu_fcopyin_, .-gpu_fcopyin_
.globl gpu_fcopyout_
.type gpu_fcopyout_, @function
gpu_fcopyout_:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_fcopyout
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size gpu_fcopyout_, .-gpu_fcopyout_
.globl _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
.type _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4gaddPfS_S_iPfS_S_i:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4gaddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i, .-_Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
.globl _Z4gaddPfS_S_i
.type _Z4gaddPfS_S_i, @function
_Z4gaddPfS_S_i:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z4gaddPfS_S_i, .-_Z4gaddPfS_S_i
.globl gpadd
.type gpadd, @function
gpadd:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl _ZL11nblock_size(%rip), %ecx
movl %ecx, 8(%rsp)
movl $1, 12(%rsp)
leal -1(%rbx), %eax
cltd
idivl %ecx
addl $1, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L50:
call cudaThreadSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z28__device_stub__Z4gaddPfS_S_iPfS_S_i
jmp .L50
.cfi_endproc
.LFE2057:
.size gpadd, .-gpadd
.globl gpadd_
.type gpadd_, @function
gpadd_:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rcx), %ecx
movq (%rdx), %rdx
movq (%rsi), %rsi
movq (%rdi), %rdi
call gpadd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size gpadd_, .-gpadd_
.globl _Z30__device_stub__Z11emptyKernelvv
.type _Z30__device_stub__Z11emptyKernelvv, @function
_Z30__device_stub__Z11emptyKernelvv:
.LFB2100:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11emptyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z30__device_stub__Z11emptyKernelvv, .-_Z30__device_stub__Z11emptyKernelvv
.globl _Z11emptyKernelv
.type _Z11emptyKernelv, @function
_Z11emptyKernelv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11emptyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z11emptyKernelv, .-_Z11emptyKernelv
.section .rodata.str1.1
.LC5:
.string "emptyKernel error=%d:%s\n"
.text
.globl emptykernel
.type emptykernel, @function
emptykernel:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl _ZL11nblock_size(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32768, %edx
cmpl %edx, %eax
cmovg %edx, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L64:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L68
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
call _Z30__device_stub__Z11emptyKernelvv
jmp .L64
.L68:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size emptykernel, .-emptykernel
.section .rodata.str1.8
.align 8
.LC6:
.string "cudaGetDeviceCount Error=%i:%s\n"
.align 8
.LC7:
.string "cudaGetDeviceProperties Error=%i:%s\n"
.align 8
.LC8:
.string "j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n"
.align 8
.LC10:
.string " CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n"
.section .rodata.str1.1
.LC11:
.string "using device j=%i\n"
.LC12:
.string "cudaSetDevice Error=%i:%s\n"
.text
.globl init_cu
.type init_cu, @function
init_cu:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1080, %rsp
.cfi_def_cfa_offset 1136
movl %edi, %ebp
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L70
movl 28(%rsp), %ecx
movl $0, %ebx
movl $-1, %r13d
movl $0, %r14d
leaq .LC7(%rip), %r15
testl %ecx, %ecx
jg .L71
.L72:
testl %ebp, %ebp
js .L78
movl %ebp, %eax
cltd
idivl %ecx
movl %edx, %r13d
.L78:
movl %r13d, _ZL5devid(%rip)
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl _ZL5devid(%rip), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, _ZL3crc(%rip)
movl 368(%rsp), %eax
movl %eax, maxgsx(%rip)
movl 392(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 396(%rsp), %eax
leal (%rax,%rdx,2), %eax
movl %eax, mmcc(%rip)
movl _ZL5devid(%rip), %edi
call cudaSetDevice@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L87
call emptykernel
.L69:
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L73
.L74:
testl %ebp, %ebp
jle .L89
.L75:
addl $1, %ebx
movl 28(%rsp), %ecx
cmpl %ebx, %ecx
jle .L72
.L71:
leaq 32(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
je .L74
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 32(%rsp)
jmp .L74
.L89:
movl 420(%rsp), %r12d
leaq 32(%rsp), %rcx
movl %r12d, %r8d
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
movl 392(%rsp), %eax
leal (%rax,%rax,4), %ecx
movl 396(%rsp), %eax
leal (%rax,%rcx,2), %ecx
movl %ecx, mmcc(%rip)
testq %rdx, %rdx
js .L76
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L77:
mulsd .LC9(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %r14d, %r12d
jle .L75
movl %ebx, %r13d
movl %r12d, %r14d
jmp .L75
.L76:
movq %rdx, %rax
shrq %rax
movq %rdx, %rsi
andl $1, %esi
orq %rsi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L77
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L73:
movq 8(%rsp), %rax
movl $1, (%rax)
jmp .L69
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size init_cu, .-init_cu
.globl init_cu_
.type init_cu_, @function
init_cu_:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdi), %edi
call init_cu
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size init_cu_, .-init_cu_
.section .rodata.str1.1
.LC13:
.string "_Z11emptyKernelv"
.LC14:
.string "_Z4gaddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11emptyKernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gaddPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3crc
.comm _ZL3crc,4,4
.local _ZL5devid
.comm _ZL5devid,4,4
.globl mmcc
.bss
.align 4
.type mmcc, @object
.size mmcc, 4
mmcc:
.zero 4
.globl maxgsx
.data
.align 4
.type maxgsx, @object
.size maxgsx, 4
maxgsx:
.long 65535
.align 4
.type _ZL11nblock_size, @object
.size _ZL11nblock_size, 4
_ZL11nblock_size:
.long 64
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpulib_cu.hip"
.globl _Z19__device_stub__gaddPfS_S_i # -- Begin function _Z19__device_stub__gaddPfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__gaddPfS_S_i,@function
_Z19__device_stub__gaddPfS_S_i: # @_Z19__device_stub__gaddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4gaddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__gaddPfS_S_i, .Lfunc_end0-_Z19__device_stub__gaddPfS_S_i
.cfi_endproc
# -- End function
.globl gpadd # -- Begin function gpadd
.p2align 4, 0x90
.type gpadd,@function
gpadd: # @gpadd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl _ZL11nblock_size(%rip), %ecx
movabsq $4294967296, %rsi # imm = 0x100000000
leal -1(%rbx), %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movq %rcx, %rdx
orq %rsi, %rdx
leal 1(%rax), %edi
orq %rsi, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4gaddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size gpadd, .Lfunc_end1-gpadd
.cfi_endproc
# -- End function
.globl _Z26__device_stub__emptyKernelv # -- Begin function _Z26__device_stub__emptyKernelv
.p2align 4, 0x90
.type _Z26__device_stub__emptyKernelv,@function
_Z26__device_stub__emptyKernelv: # @_Z26__device_stub__emptyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z26__device_stub__emptyKernelv, .Lfunc_end2-_Z26__device_stub__emptyKernelv
.cfi_endproc
# -- End function
.globl emptykernel # -- Begin function emptykernel
.p2align 4, 0x90
.type emptykernel,@function
emptykernel: # @emptykernel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl _ZL11nblock_size(%rip), %ebx
cmpl $32768, %ebx # imm = 0x8000
movl $32768, %r14d # imm = 0x8000
cmovll %ebx, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
orq %rax, %r14
callq hipGetLastError
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB3_4
# %bb.3:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_4:
.cfi_def_cfa_offset 80
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size emptykernel, .Lfunc_end3-emptykernel
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function init_cu
.LCPI4_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI4_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl init_cu
.p2align 4, 0x90
.type init_cu,@function
init_cu: # @init_cu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB4_1
# %bb.14:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%rbx)
jmp .LBB4_13
.LBB4_1: # %.preheader
movq %rbx, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %ecx
movl $-1, %r14d
testl %ecx, %ecx
jle .LBB4_8
# %bb.2: # %.lr.ph
leaq 24(%rsp), %r15
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_3 Depth=1
incl %r12d
movl 12(%rsp), %ecx
cmpl %ecx, %r12d
jge .LBB4_8
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movl %eax, %edi
movl %eax, %r13d
callq hipGetErrorString
movl $.L.str.2, %edi
movl %r13d, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movb $0, 24(%rsp)
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
testl %ebp, %ebp
jg .LBB4_7
# %bb.6: # in Loop: Header=BB4_3 Depth=1
movl 412(%rsp), %r13d
movl $.L.str.3, %edi
movl %r12d, %esi
movq %r15, %rdx
movl %r13d, %ecx
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movq %rsi, %xmm0
punpckldq .LCPI4_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI4_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
mulsd .LCPI4_2(%rip), %xmm1
movl 384(%rsp), %eax
leal (%rax,%rax,4), %edx
addl %edx, %edx
addl 388(%rsp), %edx
movl %edx, mmcc(%rip)
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
cmpl %ebx, %r13d
cmovgl %r12d, %r14d
cmovgl %r13d, %ebx
jmp .LBB4_7
.LBB4_8: # %._crit_edge
testl %ebp, %ebp
js .LBB4_10
# %bb.9:
movl %ebp, %eax
cltd
idivl %ecx
movl %edx, %r14d
.LBB4_10:
movl %r14d, _ZL5devid(%rip)
movl $.L.str.5, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl _ZL5devid(%rip), %esi
leaq 24(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 360(%rsp), %eax
movl 384(%rsp), %ecx
movl %eax, maxgsx(%rip)
leal (%rcx,%rcx,4), %eax
addl %eax, %eax
addl 388(%rsp), %eax
movl %eax, mmcc(%rip)
movl _ZL5devid(%rip), %edi
callq hipSetDevice
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax # 8-byte Reload
movl $1, (%rax)
jmp .LBB4_13
.LBB4_12:
callq emptykernel
.LBB4_13:
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size init_cu, .Lfunc_end4-init_cu
.cfi_endproc
# -- End function
.globl end_cu # -- Begin function end_cu
.p2align 4, 0x90
.type end_cu,@function
end_cu: # @end_cu
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
testl %eax, %eax
je .LBB5_1
# %bb.2:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.7, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB5_1:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size end_cu, .Lfunc_end5-end_cu
.cfi_endproc
# -- End function
.globl setgbsize # -- Begin function setgbsize
.p2align 4, 0x90
.type setgbsize,@function
setgbsize: # @setgbsize
.cfi_startproc
# %bb.0:
movl %edi, _ZL11nblock_size(%rip)
retq
.Lfunc_end6:
.size setgbsize, .Lfunc_end6-setgbsize
.cfi_endproc
# -- End function
.globl gpu_fallocate # -- Begin function gpu_fallocate
.p2align 4, 0x90
.type gpu_fallocate,@function
gpu_fallocate: # @gpu_fallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB7_2
# %bb.1:
movl %eax, %edi
movl %eax, %r15d
callq hipGetErrorString
movl $.L.str.8, %edi
movl %r15d, %esi
movq %rax, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB7_2:
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size gpu_fallocate, .Lfunc_end7-gpu_fallocate
.cfi_endproc
# -- End function
.globl gpu_deallocate # -- Begin function gpu_deallocate
.p2align 4, 0x90
.type gpu_deallocate,@function
gpu_deallocate: # @gpu_deallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
callq hipFree
testl %eax, %eax
je .LBB8_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB8_2:
movq $0, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size gpu_deallocate, .Lfunc_end8-gpu_deallocate
.cfi_endproc
# -- End function
.globl gpu_fcopyin # -- Begin function gpu_fcopyin
.p2align 4, 0x90
.type gpu_fcopyin,@function
gpu_fcopyin: # @gpu_fcopyin
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movslq %edx, %rdx
shlq $2, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB9_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB9_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.10, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end9:
.size gpu_fcopyin, .Lfunc_end9-gpu_fcopyin
.cfi_endproc
# -- End function
.globl gpu_fcopyout # -- Begin function gpu_fcopyout
.p2align 4, 0x90
.type gpu_fcopyout,@function
gpu_fcopyout: # @gpu_fcopyout
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq %edx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end10:
.size gpu_fcopyout, .Lfunc_end10-gpu_fcopyout
.cfi_endproc
# -- End function
.globl gpadd_ # -- Begin function gpadd_
.p2align 4, 0x90
.type gpadd_,@function
gpadd_: # @gpadd_
.cfi_startproc
# %bb.0:
movq (%rdi), %rdi
movq (%rsi), %rsi
movq (%rdx), %rdx
movl (%rcx), %ecx
jmp gpadd # TAILCALL
.Lfunc_end11:
.size gpadd_, .Lfunc_end11-gpadd_
.cfi_endproc
# -- End function
.globl init_cu_ # -- Begin function init_cu_
.p2align 4, 0x90
.type init_cu_,@function
init_cu_: # @init_cu_
.cfi_startproc
# %bb.0:
movl (%rdi), %edi
jmp init_cu # TAILCALL
.Lfunc_end12:
.size init_cu_, .Lfunc_end12-init_cu_
.cfi_endproc
# -- End function
.globl end_cu_ # -- Begin function end_cu_
.p2align 4, 0x90
.type end_cu_,@function
end_cu_: # @end_cu_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
testl %eax, %eax
je .LBB13_1
# %bb.2:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.7, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB13_1: # %end_cu.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end13:
.size end_cu_, .Lfunc_end13-end_cu_
.cfi_endproc
# -- End function
.globl setgbsize_ # -- Begin function setgbsize_
.p2align 4, 0x90
.type setgbsize_,@function
setgbsize_: # @setgbsize_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl %eax, _ZL11nblock_size(%rip)
retq
.Lfunc_end14:
.size setgbsize_, .Lfunc_end14-setgbsize_
.cfi_endproc
# -- End function
.globl gpu_fallocate_ # -- Begin function gpu_fallocate_
.p2align 4, 0x90
.type gpu_fallocate_,@function
gpu_fallocate_: # @gpu_fallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movq %rdi, %rbx
movslq (%rsi), %r15
leaq (,%r15,4), %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB15_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %edi
movl %ebp, %esi
movq %rax, %rdx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB15_2: # %gpu_fallocate.exit
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end15:
.size gpu_fallocate_, .Lfunc_end15-gpu_fallocate_
.cfi_endproc
# -- End function
.globl gpu_deallocate_ # -- Begin function gpu_deallocate_
.p2align 4, 0x90
.type gpu_deallocate_,@function
gpu_deallocate_: # @gpu_deallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
callq hipFree
testl %eax, %eax
je .LBB16_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB16_2: # %gpu_deallocate.exit
movq $0, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end16:
.size gpu_deallocate_, .Lfunc_end16-gpu_deallocate_
.cfi_endproc
# -- End function
.globl gpu_fcopyin_ # -- Begin function gpu_fcopyin_
.p2align 4, 0x90
.type gpu_fcopyin_,@function
gpu_fcopyin_: # @gpu_fcopyin_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movq (%rsi), %rdi
movslq (%rdx), %rdx
shlq $2, %rdx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB17_2
# %bb.1: # %gpu_fcopyin.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB17_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.10, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end17:
.size gpu_fcopyin_, .Lfunc_end17-gpu_fcopyin_
.cfi_endproc
# -- End function
.globl gpu_fcopyout_ # -- Begin function gpu_fcopyout_
.p2align 4, 0x90
.type gpu_fcopyout_,@function
gpu_fcopyout_: # @gpu_fcopyout_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movslq (%rdx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB18_2
# %bb.1: # %gpu_fcopyout.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB18_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end18:
.size gpu_fcopyout_, .Lfunc_end18-gpu_fcopyout_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB19_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB19_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gaddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11emptyKernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end19:
.size __hip_module_ctor, .Lfunc_end19-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB20_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB20_2:
retq
.Lfunc_end20:
.size __hip_module_dtor, .Lfunc_end20-__hip_module_dtor
.cfi_endproc
# -- End function
.type maxgsx,@object # @maxgsx
.data
.globl maxgsx
.p2align 2, 0x0
maxgsx:
.long 65535 # 0xffff
.size maxgsx, 4
.type mmcc,@object # @mmcc
.bss
.globl mmcc
.p2align 2, 0x0
mmcc:
.long 0 # 0x0
.size mmcc, 4
.type _Z4gaddPfS_S_i,@object # @_Z4gaddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z4gaddPfS_S_i
.p2align 3, 0x0
_Z4gaddPfS_S_i:
.quad _Z19__device_stub__gaddPfS_S_i
.size _Z4gaddPfS_S_i, 8
.type _ZL11nblock_size,@object # @_ZL11nblock_size
.data
.p2align 2, 0x0
_ZL11nblock_size:
.long 64 # 0x40
.size _ZL11nblock_size, 4
.type _Z11emptyKernelv,@object # @_Z11emptyKernelv
.section .rodata,"a",@progbits
.globl _Z11emptyKernelv
.p2align 3, 0x0
_Z11emptyKernelv:
.quad _Z26__device_stub__emptyKernelv
.size _Z11emptyKernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "emptyKernel error=%d:%s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount Error=%i:%s\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipGetDeviceProperties Error=%i:%s\n"
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n"
.size .L.str.3, 55
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n"
.size .L.str.4, 51
.type _ZL5devid,@object # @_ZL5devid
.local _ZL5devid
.comm _ZL5devid,4,4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "using device j=%i\n"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice Error=%i:%s\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceReset Error=%d:%s\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc float Error=%d:%s,l=%d\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipFree Error=%d:%s\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMemcpyHostToDevice float Error=%d:%s\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipMemcpyDeviceToHost float Error=%d:%s\n"
.size .L.str.11, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4gaddPfS_S_i"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11emptyKernelv"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gaddPfS_S_i
.addrsig_sym _Z26__device_stub__emptyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gaddPfS_S_i
.addrsig_sym _Z11emptyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void gscale(const int lengthB, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthB)
{
b[i] = a[0]*b[i]; // REMEMBER ZERO INDEXING IN C LANGUAGE!!
}
}
} | code for sm_80
Function : gscale
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fcc0000000f00 */
/*00a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ DMUL R4, R4, R6 ; /* 0x0000000604047228 */
/* 0x004e0e0000000000 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void gscale(const int lengthB, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthB)
{
b[i] = a[0]*b[i]; // REMEMBER ZERO INDEXING IN C LANGUAGE!!
}
}
} | .file "tmpxft_0019e6b2_00000000-6_gscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6gscaleiPKdPdiPKdPd
.type _Z29__device_stub__Z6gscaleiPKdPdiPKdPd, @function
_Z29__device_stub__Z6gscaleiPKdPdiPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gscale(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6gscaleiPKdPdiPKdPd, .-_Z29__device_stub__Z6gscaleiPKdPdiPKdPd
.globl gscale
.type gscale, @function
gscale:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6gscaleiPKdPdiPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gscale, .-gscale
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gscale"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gscale(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void gscale(const int lengthB, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthB)
{
b[i] = a[0]*b[i]; // REMEMBER ZERO INDEXING IN C LANGUAGE!!
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gscale(const int lengthB, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthB)
{
b[i] = a[0]*b[i]; // REMEMBER ZERO INDEXING IN C LANGUAGE!!
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gscale(const int lengthB, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthB)
{
b[i] = a[0]*b[i]; // REMEMBER ZERO INDEXING IN C LANGUAGE!!
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gscale
.globl gscale
.p2align 8
.type gscale,@function
gscale:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[2:3], s[0:1], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gscale
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gscale, .Lfunc_end0-gscale
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gscale
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gscale.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gscale(const int lengthB, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthB)
{
b[i] = a[0]*b[i]; // REMEMBER ZERO INDEXING IN C LANGUAGE!!
}
}
} | .text
.file "gscale.hip"
.globl __device_stub__gscale # -- Begin function __device_stub__gscale
.p2align 4, 0x90
.type __device_stub__gscale,@function
__device_stub__gscale: # @__device_stub__gscale
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gscale, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__gscale, .Lfunc_end0-__device_stub__gscale
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gscale, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gscale,@object # @gscale
.section .rodata,"a",@progbits
.globl gscale
.p2align 3, 0x0
gscale:
.quad __device_stub__gscale
.size gscale, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gscale"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gscale
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gscale
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : gscale
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fcc0000000f00 */
/*00a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ DMUL R4, R4, R6 ; /* 0x0000000604047228 */
/* 0x004e0e0000000000 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gscale
.globl gscale
.p2align 8
.type gscale,@function
gscale:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[2:3], s[0:1], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gscale
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gscale, .Lfunc_end0-gscale
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gscale
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gscale.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019e6b2_00000000-6_gscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6gscaleiPKdPdiPKdPd
.type _Z29__device_stub__Z6gscaleiPKdPdiPKdPd, @function
_Z29__device_stub__Z6gscaleiPKdPdiPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gscale(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6gscaleiPKdPdiPKdPd, .-_Z29__device_stub__Z6gscaleiPKdPdiPKdPd
.globl gscale
.type gscale, @function
gscale:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6gscaleiPKdPdiPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gscale, .-gscale
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gscale"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gscale(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gscale.hip"
.globl __device_stub__gscale # -- Begin function __device_stub__gscale
.p2align 4, 0x90
.type __device_stub__gscale,@function
__device_stub__gscale: # @__device_stub__gscale
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gscale, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__gscale, .Lfunc_end0-__device_stub__gscale
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gscale, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gscale,@object # @gscale
.section .rodata,"a",@progbits
.globl gscale
.p2align 3, 0x0
gscale:
.quad __device_stub__gscale
.size gscale, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gscale"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gscale
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gscale
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <ctype.h>
#include <vector>
#include <string>
typedef std::vector<double> double_vec;
int main()
{
double_vec stocks;
std::string value, prev_val;
while (true)
{
std::getline(std::cin, value);
if (!isdigit(value[0]))
{
break;
}
else
{
stocks.push_back(std::stod(value));
}
}
thrust::host_vector<double> host(int(stocks.size()));
host = stocks;
thrust::device_vector<double> dev(host);
thrust::device_vector<double> ganho_diario(int(stocks.size()) - 1, 0);
// ganho diário
thrust::transform(
dev.begin() + 1,
dev.end(),
dev.begin(),
ganho_diario.begin(),
thrust::minus<double>()
);
double sumDiffs = thrust::reduce(ganho_diario.begin(), ganho_diario.end(), 0.0, thrust::plus<double>());
double avgDiffs = sumDiffs / int(stocks.size());
std::cout << "O ganho médio foi de: US$ " << avgDiffs << std::endl;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <ctype.h>
#include <vector>
#include <string>
typedef std::vector<double> double_vec;
int main()
{
double_vec stocks;
std::string value, prev_val;
while (true)
{
std::getline(std::cin, value);
if (!isdigit(value[0]))
{
break;
}
else
{
stocks.push_back(std::stod(value));
}
}
thrust::host_vector<double> host(int(stocks.size()));
host = stocks;
thrust::device_vector<double> dev(host);
thrust::device_vector<double> ganho_diario(int(stocks.size()) - 1, 0);
// ganho diário
thrust::transform(
dev.begin() + 1,
dev.end(),
dev.begin(),
ganho_diario.begin(),
thrust::minus<double>()
);
double sumDiffs = thrust::reduce(ganho_diario.begin(), ganho_diario.end(), 0.0, thrust::plus<double>());
double avgDiffs = sumDiffs / int(stocks.size());
std::cout << "O ganho médio foi de: US$ " << avgDiffs << std::endl;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
#define N 32
#define NT 16
#define NB 2
// reduction with 2 blocks of 16 each
__global__ void reduction(int * input, int * output)
{
__shared__ int tmp[NT];
tmp[threadIdx.x] = input[threadIdx.x + blockIdx.x * blockDim.x];
__syncthreads();
// 16 -> 8
if (threadIdx.x < blockDim.x/2)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/2];
__syncthreads();
// 8 -> 4
if (threadIdx.x < blockDim.x/4)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/4];
__syncthreads();
// 4 -> 2
if (threadIdx.x < blockDim.x/8)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/8];
__syncthreads();
// 2 -> 1
if (threadIdx.x == 0)
{
tmp[threadIdx.x] += tmp[threadIdx.x + 1];
output[blockIdx.x] = tmp[threadIdx.x];
}
}
int main()
{
int h_input[N], h_output[NB];
int * d_input, * d_output;
for (int i=0; i<N; i++)
h_input[i] = 1;
cudaMalloc( (void**)&d_input, N*sizeof(int) );
cudaMalloc( (void**)&d_output, NB*sizeof(int) );
cudaMemcpy( d_input, h_input, N*sizeof(int), cudaMemcpyHostToDevice );
reduction<<< NB,NT >>>(d_input, d_output);
cudaMemcpy( h_output, d_output, NB*sizeof(int), cudaMemcpyDeviceToHost );
cout << "Result0 is " << h_output[0] << endl;
cout << "Result1 is " << h_output[1] << endl;
return 0;
} | code for sm_80
Function : _Z9reductionPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R8 ; /* 0x0000000006027a24 */
/* 0x001fc800078e0208 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0009 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0080*/ MOV R10, c[0x0][0x0] ; /* 0x00000000000a7a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.SHL.U32 R0, R8, 0x4, RZ ; /* 0x0000000408007824 */
/* 0x000fc600078e00ff */
/*00a0*/ SHF.R.U32.HI R5, RZ, 0x1, R10.reuse ; /* 0x00000001ff057819 */
/* 0x100fe4000001160a */
/*00b0*/ SHF.R.U32.HI R7, RZ, 0x2, R10.reuse ; /* 0x00000002ff077819 */
/* 0x100fe4000001160a */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R8.reuse, R5, PT ; /* 0x000000050800720c */
/* 0x040fe40003f26070 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe40003f06070 */
/*00e0*/ SHF.R.U32.HI R3, RZ, 0x3, R10 ; /* 0x00000003ff037819 */
/* 0x001fd2000001160a */
/*00f0*/ @!P1 LEA R5, R5, R0.reuse, 0x2 ; /* 0x0000000005059211 */
/* 0x080fe400078e10ff */
/*0100*/ @!P0 LEA R7, R7, R0, 0x2 ; /* 0x0000000007078211 */
/* 0x000fe200078e10ff */
/*0110*/ STS [R8.X4], R2 ; /* 0x0000000208007388 */
/* 0x004fe80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P1 LDS R5, [R5] ; /* 0x0000000005059984 */
/* 0x000fe80000000800 */
/*0140*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000e240000004800 */
/*0150*/ @!P1 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104049824 */
/* 0x001fca00078e0205 */
/*0160*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x000fe80000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26070 */
/*0190*/ @!P1 LEA R0, R3, R0, 0x2 ; /* 0x0000000003009211 */
/* 0x000fe200078e10ff */
/*01a0*/ @!P0 LDS R7, [R7] ; /* 0x0000000007078984 */
/* 0x000fe80000000800 */
/*01b0*/ @!P0 LDS R2, [R8.X4] ; /* 0x0000000008028984 */
/* 0x000e240000004800 */
/*01c0*/ @!P0 IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102028824 */
/* 0x001fca00078e0207 */
/*01d0*/ @!P0 STS [R8.X4], R2 ; /* 0x0000000208008388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fca0003f05270 */
/*0200*/ @!P1 LDS R0, [R0] ; /* 0x0000000000009984 */
/* 0x000fe80000000800 */
/*0210*/ @!P1 LDS R3, [R8.X4] ; /* 0x0000000008039984 */
/* 0x000e240000004800 */
/*0220*/ @!P1 IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103039824 */
/* 0x001fca00078e0200 */
/*0230*/ @!P1 STS [R8.X4], R3 ; /* 0x0000000308009388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000a00 */
/*0270*/ IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fe200078e0009 */
/*0280*/ IADD3 R5, R5, R4, RZ ; /* 0x0000000405057210 */
/* 0x001fca0007ffe0ff */
/*0290*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STS [RZ], R5 ; /* 0x00000005ff007388 */
/* 0x000fe20000000800 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
#define N 32
#define NT 16
#define NB 2
// reduction with 2 blocks of 16 each
__global__ void reduction(int * input, int * output)
{
__shared__ int tmp[NT];
tmp[threadIdx.x] = input[threadIdx.x + blockIdx.x * blockDim.x];
__syncthreads();
// 16 -> 8
if (threadIdx.x < blockDim.x/2)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/2];
__syncthreads();
// 8 -> 4
if (threadIdx.x < blockDim.x/4)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/4];
__syncthreads();
// 4 -> 2
if (threadIdx.x < blockDim.x/8)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/8];
__syncthreads();
// 2 -> 1
if (threadIdx.x == 0)
{
tmp[threadIdx.x] += tmp[threadIdx.x + 1];
output[blockIdx.x] = tmp[threadIdx.x];
}
}
int main()
{
int h_input[N], h_output[NB];
int * d_input, * d_output;
for (int i=0; i<N; i++)
h_input[i] = 1;
cudaMalloc( (void**)&d_input, N*sizeof(int) );
cudaMalloc( (void**)&d_output, NB*sizeof(int) );
cudaMemcpy( d_input, h_input, N*sizeof(int), cudaMemcpyHostToDevice );
reduction<<< NB,NT >>>(d_input, d_output);
cudaMemcpy( h_output, d_output, NB*sizeof(int), cudaMemcpyDeviceToHost );
cout << "Result0 is " << h_output[0] << endl;
cout << "Result1 is " << h_output[1] << endl;
return 0;
} | .file "tmpxft_000ab937_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9reductionPiS_PiS_
.type _Z30__device_stub__Z9reductionPiS_PiS_, @function
_Z30__device_stub__Z9reductionPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z9reductionPiS_PiS_, .-_Z30__device_stub__Z9reductionPiS_PiS_
.globl _Z9reductionPiS_
.type _Z9reductionPiS_, @function
_Z9reductionPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9reductionPiS_, .-_Z9reductionPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result0 is "
.LC1:
.string "Result1 is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $192, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rax
leaq 176(%rsp), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 40(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 44(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9reductionPiS_PiS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9reductionPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
#define N 32
#define NT 16
#define NB 2
// reduction with 2 blocks of 16 each
__global__ void reduction(int * input, int * output)
{
__shared__ int tmp[NT];
tmp[threadIdx.x] = input[threadIdx.x + blockIdx.x * blockDim.x];
__syncthreads();
// 16 -> 8
if (threadIdx.x < blockDim.x/2)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/2];
__syncthreads();
// 8 -> 4
if (threadIdx.x < blockDim.x/4)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/4];
__syncthreads();
// 4 -> 2
if (threadIdx.x < blockDim.x/8)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/8];
__syncthreads();
// 2 -> 1
if (threadIdx.x == 0)
{
tmp[threadIdx.x] += tmp[threadIdx.x + 1];
output[blockIdx.x] = tmp[threadIdx.x];
}
}
int main()
{
int h_input[N], h_output[NB];
int * d_input, * d_output;
for (int i=0; i<N; i++)
h_input[i] = 1;
cudaMalloc( (void**)&d_input, N*sizeof(int) );
cudaMalloc( (void**)&d_output, NB*sizeof(int) );
cudaMemcpy( d_input, h_input, N*sizeof(int), cudaMemcpyHostToDevice );
reduction<<< NB,NT >>>(d_input, d_output);
cudaMemcpy( h_output, d_output, NB*sizeof(int), cudaMemcpyDeviceToHost );
cout << "Result0 is " << h_output[0] << endl;
cout << "Result1 is " << h_output[1] << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define N 32
#define NT 16
#define NB 2
// reduction with 2 blocks of 16 each
__global__ void reduction(int * input, int * output)
{
__shared__ int tmp[NT];
tmp[threadIdx.x] = input[threadIdx.x + blockIdx.x * blockDim.x];
__syncthreads();
// 16 -> 8
if (threadIdx.x < blockDim.x/2)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/2];
__syncthreads();
// 8 -> 4
if (threadIdx.x < blockDim.x/4)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/4];
__syncthreads();
// 4 -> 2
if (threadIdx.x < blockDim.x/8)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/8];
__syncthreads();
// 2 -> 1
if (threadIdx.x == 0)
{
tmp[threadIdx.x] += tmp[threadIdx.x + 1];
output[blockIdx.x] = tmp[threadIdx.x];
}
}
int main()
{
int h_input[N], h_output[NB];
int * d_input, * d_output;
for (int i=0; i<N; i++)
h_input[i] = 1;
hipMalloc( (void**)&d_input, N*sizeof(int) );
hipMalloc( (void**)&d_output, NB*sizeof(int) );
hipMemcpy( d_input, h_input, N*sizeof(int), hipMemcpyHostToDevice );
reduction<<< NB,NT >>>(d_input, d_output);
hipMemcpy( h_output, d_output, NB*sizeof(int), hipMemcpyDeviceToHost );
cout << "Result0 is " << h_output[0] << endl;
cout << "Result1 is " << h_output[1] << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define N 32
#define NT 16
#define NB 2
// reduction with 2 blocks of 16 each
__global__ void reduction(int * input, int * output)
{
__shared__ int tmp[NT];
tmp[threadIdx.x] = input[threadIdx.x + blockIdx.x * blockDim.x];
__syncthreads();
// 16 -> 8
if (threadIdx.x < blockDim.x/2)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/2];
__syncthreads();
// 8 -> 4
if (threadIdx.x < blockDim.x/4)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/4];
__syncthreads();
// 4 -> 2
if (threadIdx.x < blockDim.x/8)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/8];
__syncthreads();
// 2 -> 1
if (threadIdx.x == 0)
{
tmp[threadIdx.x] += tmp[threadIdx.x + 1];
output[blockIdx.x] = tmp[threadIdx.x];
}
}
int main()
{
int h_input[N], h_output[NB];
int * d_input, * d_output;
for (int i=0; i<N; i++)
h_input[i] = 1;
hipMalloc( (void**)&d_input, N*sizeof(int) );
hipMalloc( (void**)&d_output, NB*sizeof(int) );
hipMemcpy( d_input, h_input, N*sizeof(int), hipMemcpyHostToDevice );
reduction<<< NB,NT >>>(d_input, d_output);
hipMemcpy( h_output, d_output, NB*sizeof(int), hipMemcpyDeviceToHost );
cout << "Result0 is " << h_output[0] << endl;
cout << "Result1 is " << h_output[1] << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 8
.type _Z9reductionPiS_,@function
_Z9reductionPiS_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_bfe_u32 s4, s6, 0xf0001
s_mov_b32 s5, exec_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_2
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s3, 2
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 3
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v2, v1
ds_load_b32 v3, v0 offset:4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
global_store_b32 v0, v2, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPiS_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPiS_, .Lfunc_end0-_Z9reductionPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define N 32
#define NT 16
#define NB 2
// reduction with 2 blocks of 16 each
__global__ void reduction(int * input, int * output)
{
__shared__ int tmp[NT];
tmp[threadIdx.x] = input[threadIdx.x + blockIdx.x * blockDim.x];
__syncthreads();
// 16 -> 8
if (threadIdx.x < blockDim.x/2)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/2];
__syncthreads();
// 8 -> 4
if (threadIdx.x < blockDim.x/4)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/4];
__syncthreads();
// 4 -> 2
if (threadIdx.x < blockDim.x/8)
tmp[threadIdx.x] += tmp[threadIdx.x + blockDim.x/8];
__syncthreads();
// 2 -> 1
if (threadIdx.x == 0)
{
tmp[threadIdx.x] += tmp[threadIdx.x + 1];
output[blockIdx.x] = tmp[threadIdx.x];
}
}
int main()
{
int h_input[N], h_output[NB];
int * d_input, * d_output;
for (int i=0; i<N; i++)
h_input[i] = 1;
hipMalloc( (void**)&d_input, N*sizeof(int) );
hipMalloc( (void**)&d_output, NB*sizeof(int) );
hipMemcpy( d_input, h_input, N*sizeof(int), hipMemcpyHostToDevice );
reduction<<< NB,NT >>>(d_input, d_output);
hipMemcpy( h_output, d_output, NB*sizeof(int), hipMemcpyDeviceToHost );
cout << "Result0 is " << h_output[0] << endl;
cout << "Result1 is " << h_output[1] << endl;
return 0;
} | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__reductionPiS_ # -- Begin function _Z24__device_stub__reductionPiS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPiS_,@function
_Z24__device_stub__reductionPiS_: # @_Z24__device_stub__reductionPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPiS_, .Lfunc_end0-_Z24__device_stub__reductionPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $232, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, 96(%rsp,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 14(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z9reductionPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movq %rsp, %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPiS_,@object # @_Z9reductionPiS_
.section .rodata,"a",@progbits
.globl _Z9reductionPiS_
.p2align 3, 0x0
_Z9reductionPiS_:
.quad _Z24__device_stub__reductionPiS_
.size _Z9reductionPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result0 is "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Result1 is "
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R8 ; /* 0x0000000006027a24 */
/* 0x001fc800078e0208 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0009 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0080*/ MOV R10, c[0x0][0x0] ; /* 0x00000000000a7a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.SHL.U32 R0, R8, 0x4, RZ ; /* 0x0000000408007824 */
/* 0x000fc600078e00ff */
/*00a0*/ SHF.R.U32.HI R5, RZ, 0x1, R10.reuse ; /* 0x00000001ff057819 */
/* 0x100fe4000001160a */
/*00b0*/ SHF.R.U32.HI R7, RZ, 0x2, R10.reuse ; /* 0x00000002ff077819 */
/* 0x100fe4000001160a */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R8.reuse, R5, PT ; /* 0x000000050800720c */
/* 0x040fe40003f26070 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe40003f06070 */
/*00e0*/ SHF.R.U32.HI R3, RZ, 0x3, R10 ; /* 0x00000003ff037819 */
/* 0x001fd2000001160a */
/*00f0*/ @!P1 LEA R5, R5, R0.reuse, 0x2 ; /* 0x0000000005059211 */
/* 0x080fe400078e10ff */
/*0100*/ @!P0 LEA R7, R7, R0, 0x2 ; /* 0x0000000007078211 */
/* 0x000fe200078e10ff */
/*0110*/ STS [R8.X4], R2 ; /* 0x0000000208007388 */
/* 0x004fe80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P1 LDS R5, [R5] ; /* 0x0000000005059984 */
/* 0x000fe80000000800 */
/*0140*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000e240000004800 */
/*0150*/ @!P1 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104049824 */
/* 0x001fca00078e0205 */
/*0160*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x000fe80000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26070 */
/*0190*/ @!P1 LEA R0, R3, R0, 0x2 ; /* 0x0000000003009211 */
/* 0x000fe200078e10ff */
/*01a0*/ @!P0 LDS R7, [R7] ; /* 0x0000000007078984 */
/* 0x000fe80000000800 */
/*01b0*/ @!P0 LDS R2, [R8.X4] ; /* 0x0000000008028984 */
/* 0x000e240000004800 */
/*01c0*/ @!P0 IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102028824 */
/* 0x001fca00078e0207 */
/*01d0*/ @!P0 STS [R8.X4], R2 ; /* 0x0000000208008388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fca0003f05270 */
/*0200*/ @!P1 LDS R0, [R0] ; /* 0x0000000000009984 */
/* 0x000fe80000000800 */
/*0210*/ @!P1 LDS R3, [R8.X4] ; /* 0x0000000008039984 */
/* 0x000e240000004800 */
/*0220*/ @!P1 IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103039824 */
/* 0x001fca00078e0200 */
/*0230*/ @!P1 STS [R8.X4], R3 ; /* 0x0000000308009388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000a00 */
/*0270*/ IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fe200078e0009 */
/*0280*/ IADD3 R5, R5, R4, RZ ; /* 0x0000000405057210 */
/* 0x001fca0007ffe0ff */
/*0290*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STS [RZ], R5 ; /* 0x00000005ff007388 */
/* 0x000fe20000000800 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 8
.type _Z9reductionPiS_,@function
_Z9reductionPiS_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_bfe_u32 s4, s6, 0xf0001
s_mov_b32 s5, exec_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_2
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s3, 2
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 3
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v2, v1
ds_load_b32 v3, v0 offset:4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
global_store_b32 v0, v2, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPiS_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPiS_, .Lfunc_end0-_Z9reductionPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab937_00000000-6_reduction.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9reductionPiS_PiS_
.type _Z30__device_stub__Z9reductionPiS_PiS_, @function
_Z30__device_stub__Z9reductionPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z9reductionPiS_PiS_, .-_Z30__device_stub__Z9reductionPiS_PiS_
.globl _Z9reductionPiS_
.type _Z9reductionPiS_, @function
_Z9reductionPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9reductionPiS_, .-_Z9reductionPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result0 is "
.LC1:
.string "Result1 is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $192, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rax
leaq 176(%rsp), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 40(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 44(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9reductionPiS_PiS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9reductionPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__reductionPiS_ # -- Begin function _Z24__device_stub__reductionPiS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPiS_,@function
_Z24__device_stub__reductionPiS_: # @_Z24__device_stub__reductionPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPiS_, .Lfunc_end0-_Z24__device_stub__reductionPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $232, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, 96(%rsp,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 14(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z9reductionPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movq %rsp, %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPiS_,@object # @_Z9reductionPiS_
.section .rodata,"a",@progbits
.globl _Z9reductionPiS_
.p2align 3, 0x0
_Z9reductionPiS_:
.quad _Z24__device_stub__reductionPiS_
.size _Z9reductionPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result0 is "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Result1 is "
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(int *output, int length, int *n1, int *n2) {
int blockID = blockIdx.x;
int threadID = threadIdx.x;
int blockOffset = blockID * length;
output[blockOffset + threadID] += n1[blockID] + n2[blockID];
} | code for sm_80
Function : _Z3addPiiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R4, c[0x0][0x168], R3 ; /* 0x00005a0004067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R7, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R4, R7.reuse, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x080fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0207 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R9, R0, R5, R2 ; /* 0x0000000500097210 */
/* 0x004fca0007ffe002 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(int *output, int length, int *n1, int *n2) {
int blockID = blockIdx.x;
int threadID = threadIdx.x;
int blockOffset = blockID * length;
output[blockOffset + threadID] += n1[blockID] + n2[blockID];
} | .file "tmpxft_0018a804_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiiS_S_PiiS_S_
.type _Z27__device_stub__Z3addPiiS_S_PiiS_S_, @function
_Z27__device_stub__Z3addPiiS_S_PiiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPiiS_S_PiiS_S_, .-_Z27__device_stub__Z3addPiiS_S_PiiS_S_
.globl _Z3addPiiS_S_
.type _Z3addPiiS_S_, @function
_Z3addPiiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiiS_S_PiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiiS_S_, .-_Z3addPiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(int *output, int length, int *n1, int *n2) {
int blockID = blockIdx.x;
int threadID = threadIdx.x;
int blockOffset = blockID * length;
output[blockOffset + threadID] += n1[blockID] + n2[blockID];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *output, int length, int *n1, int *n2) {
int blockID = blockIdx.x;
int threadID = threadIdx.x;
int blockOffset = blockID * length;
output[blockOffset + threadID] += n1[blockID] + n2[blockID];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *output, int length, int *n1, int *n2) {
int blockID = blockIdx.x;
int threadID = threadIdx.x;
int blockOffset = blockID * length;
output[blockOffset + threadID] += n1[blockID] + n2[blockID];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiiS_S_
.globl _Z3addPiiS_S_
.p2align 8
.type _Z3addPiiS_S_,@function
_Z3addPiiS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_ashr_i32 s5, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x10
global_load_b32 v2, v[0:1], off
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v2, s1, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiiS_S_, .Lfunc_end0-_Z3addPiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *output, int length, int *n1, int *n2) {
int blockID = blockIdx.x;
int threadID = threadIdx.x;
int blockOffset = blockID * length;
output[blockOffset + threadID] += n1[blockID] + n2[blockID];
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiiS_S_ # -- Begin function _Z18__device_stub__addPiiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiiS_S_,@function
_Z18__device_stub__addPiiS_S_: # @_Z18__device_stub__addPiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiiS_S_, .Lfunc_end0-_Z18__device_stub__addPiiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiiS_S_,@object # @_Z3addPiiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiiS_S_
.p2align 3, 0x0
_Z3addPiiS_S_:
.quad _Z18__device_stub__addPiiS_S_
.size _Z3addPiiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R4, c[0x0][0x168], R3 ; /* 0x00005a0004067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R7, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R4, R7.reuse, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x080fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0207 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R9, R0, R5, R2 ; /* 0x0000000500097210 */
/* 0x004fca0007ffe002 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiiS_S_
.globl _Z3addPiiS_S_
.p2align 8
.type _Z3addPiiS_S_,@function
_Z3addPiiS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_ashr_i32 s5, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x10
global_load_b32 v2, v[0:1], off
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v2, s1, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiiS_S_, .Lfunc_end0-_Z3addPiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018a804_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiiS_S_PiiS_S_
.type _Z27__device_stub__Z3addPiiS_S_PiiS_S_, @function
_Z27__device_stub__Z3addPiiS_S_PiiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPiiS_S_PiiS_S_, .-_Z27__device_stub__Z3addPiiS_S_PiiS_S_
.globl _Z3addPiiS_S_
.type _Z3addPiiS_S_, @function
_Z3addPiiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiiS_S_PiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiiS_S_, .-_Z3addPiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiiS_S_ # -- Begin function _Z18__device_stub__addPiiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiiS_S_,@function
_Z18__device_stub__addPiiS_S_: # @_Z18__device_stub__addPiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiiS_S_, .Lfunc_end0-_Z18__device_stub__addPiiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiiS_S_,@object # @_Z3addPiiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiiS_S_
.p2align 3, 0x0
_Z3addPiiS_S_:
.quad _Z18__device_stub__addPiiS_S_
.size _Z3addPiiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
const int N = 11;
const int blocksize = 11;
__global__
void hello(char * ar)
{
int i = threadIdx.x;
ar[i] = ar[i] + 1;
}
int main()
{
char a[] = { 'G', 'd', 'k', 'k', 'n', (char)31, 'v', 'n', 'q', 'k', 'c', 0 };
char *ad;
const int csize = N * sizeof(char);
printf("%s\n", a);
int res = cudaMalloc((void**)&ad, csize);
res = cudaMemcpy(ad, a, csize, cudaMemcpyHostToDevice);
dim3 dimBlock(blocksize, 1);
dim3 dimGrid(1, 1);
hello<<<dimGrid, dimBlock>>>(ad);
res = cudaMemcpy(a, ad, csize, cudaMemcpyDeviceToHost);
res = cudaFree(ad);
printf("%s\n", a);
return 0;
} | code for sm_80
Function : _Z5helloPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x001fc80007f1e0ff */
/*0040*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0050*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0060*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
const int N = 11;
const int blocksize = 11;
__global__
void hello(char * ar)
{
int i = threadIdx.x;
ar[i] = ar[i] + 1;
}
int main()
{
char a[] = { 'G', 'd', 'k', 'k', 'n', (char)31, 'v', 'n', 'q', 'k', 'c', 0 };
char *ad;
const int csize = N * sizeof(char);
printf("%s\n", a);
int res = cudaMalloc((void**)&ad, csize);
res = cudaMemcpy(ad, a, csize, cudaMemcpyHostToDevice);
dim3 dimBlock(blocksize, 1);
dim3 dimGrid(1, 1);
hello<<<dimGrid, dimBlock>>>(ad);
res = cudaMemcpy(a, ad, csize, cudaMemcpyDeviceToHost);
res = cudaFree(ad);
printf("%s\n", a);
return 0;
} | .file "tmpxft_00074466_00000000-6_stuff.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5helloPcPc
.type _Z24__device_stub__Z5helloPcPc, @function
_Z24__device_stub__Z5helloPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5helloPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z5helloPcPc, .-_Z24__device_stub__Z5helloPcPc
.globl _Z5helloPc
.type _Z5helloPc, @function
_Z5helloPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5helloPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5helloPc, .-_Z5helloPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $7959583950532994119, %rax
movq %rax, 44(%rsp)
movl $6515569, 52(%rsp)
leaq 44(%rsp), %rbx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $11, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $11, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $11, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rbx
movl $2, %ecx
movl $11, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5helloPcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5helloPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5helloPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
const int N = 11;
const int blocksize = 11;
__global__
void hello(char * ar)
{
int i = threadIdx.x;
ar[i] = ar[i] + 1;
}
int main()
{
char a[] = { 'G', 'd', 'k', 'k', 'n', (char)31, 'v', 'n', 'q', 'k', 'c', 0 };
char *ad;
const int csize = N * sizeof(char);
printf("%s\n", a);
int res = cudaMalloc((void**)&ad, csize);
res = cudaMemcpy(ad, a, csize, cudaMemcpyHostToDevice);
dim3 dimBlock(blocksize, 1);
dim3 dimGrid(1, 1);
hello<<<dimGrid, dimBlock>>>(ad);
res = cudaMemcpy(a, ad, csize, cudaMemcpyDeviceToHost);
res = cudaFree(ad);
printf("%s\n", a);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
const int N = 11;
const int blocksize = 11;
__global__
void hello(char * ar)
{
int i = threadIdx.x;
ar[i] = ar[i] + 1;
}
int main()
{
char a[] = { 'G', 'd', 'k', 'k', 'n', (char)31, 'v', 'n', 'q', 'k', 'c', 0 };
char *ad;
const int csize = N * sizeof(char);
printf("%s\n", a);
int res = hipMalloc((void**)&ad, csize);
res = hipMemcpy(ad, a, csize, hipMemcpyHostToDevice);
dim3 dimBlock(blocksize, 1);
dim3 dimGrid(1, 1);
hello<<<dimGrid, dimBlock>>>(ad);
res = hipMemcpy(a, ad, csize, hipMemcpyDeviceToHost);
res = hipFree(ad);
printf("%s\n", a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
const int N = 11;
const int blocksize = 11;
__global__
void hello(char * ar)
{
int i = threadIdx.x;
ar[i] = ar[i] + 1;
}
int main()
{
char a[] = { 'G', 'd', 'k', 'k', 'n', (char)31, 'v', 'n', 'q', 'k', 'c', 0 };
char *ad;
const int csize = N * sizeof(char);
printf("%s\n", a);
int res = hipMalloc((void**)&ad, csize);
res = hipMemcpy(ad, a, csize, hipMemcpyHostToDevice);
dim3 dimBlock(blocksize, 1);
dim3 dimGrid(1, 1);
hello<<<dimGrid, dimBlock>>>(ad);
res = hipMemcpy(a, ad, csize, hipMemcpyDeviceToHost);
res = hipFree(ad);
printf("%s\n", a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5helloPc
.globl _Z5helloPc
.p2align 8
.type _Z5helloPc,@function
_Z5helloPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5helloPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5helloPc, .Lfunc_end0-_Z5helloPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5helloPc
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z5helloPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
const int N = 11;
const int blocksize = 11;
__global__
void hello(char * ar)
{
int i = threadIdx.x;
ar[i] = ar[i] + 1;
}
int main()
{
char a[] = { 'G', 'd', 'k', 'k', 'n', (char)31, 'v', 'n', 'q', 'k', 'c', 0 };
char *ad;
const int csize = N * sizeof(char);
printf("%s\n", a);
int res = hipMalloc((void**)&ad, csize);
res = hipMemcpy(ad, a, csize, hipMemcpyHostToDevice);
dim3 dimBlock(blocksize, 1);
dim3 dimGrid(1, 1);
hello<<<dimGrid, dimBlock>>>(ad);
res = hipMemcpy(a, ad, csize, hipMemcpyDeviceToHost);
res = hipFree(ad);
printf("%s\n", a);
return 0;
} | .text
.file "stuff.hip"
.globl _Z20__device_stub__helloPc # -- Begin function _Z20__device_stub__helloPc
.p2align 4, 0x90
.type _Z20__device_stub__helloPc,@function
_Z20__device_stub__helloPc: # @_Z20__device_stub__helloPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5helloPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__helloPc, .Lfunc_end0-_Z20__device_stub__helloPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movabsq $7959583950532994119, %rax # imm = 0x6E761F6E6B6B6447
movq %rax, 20(%rsp)
movl $6515569, 28(%rsp) # imm = 0x636B71
leaq 20(%rsp), %rbx
movq %rbx, %rdi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $11, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $11, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 10(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z5helloPc, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 20(%rsp), %rbx
movl $11, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5helloPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5helloPc,@object # @_Z5helloPc
.section .rodata,"a",@progbits
.globl _Z5helloPc
.p2align 3, 0x0
_Z5helloPc:
.quad _Z20__device_stub__helloPc
.size _Z5helloPc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5helloPc"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__helloPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5helloPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5helloPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x001fc80007f1e0ff */
/*0040*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0050*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0060*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5helloPc
.globl _Z5helloPc
.p2align 8
.type _Z5helloPc,@function
_Z5helloPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5helloPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5helloPc, .Lfunc_end0-_Z5helloPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5helloPc
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z5helloPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074466_00000000-6_stuff.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5helloPcPc
.type _Z24__device_stub__Z5helloPcPc, @function
_Z24__device_stub__Z5helloPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5helloPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z5helloPcPc, .-_Z24__device_stub__Z5helloPcPc
.globl _Z5helloPc
.type _Z5helloPc, @function
_Z5helloPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5helloPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5helloPc, .-_Z5helloPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $7959583950532994119, %rax
movq %rax, 44(%rsp)
movl $6515569, 52(%rsp)
leaq 44(%rsp), %rbx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $11, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $11, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $11, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rbx
movl $2, %ecx
movl $11, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5helloPcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5helloPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5helloPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stuff.hip"
.globl _Z20__device_stub__helloPc # -- Begin function _Z20__device_stub__helloPc
.p2align 4, 0x90
.type _Z20__device_stub__helloPc,@function
_Z20__device_stub__helloPc: # @_Z20__device_stub__helloPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5helloPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__helloPc, .Lfunc_end0-_Z20__device_stub__helloPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movabsq $7959583950532994119, %rax # imm = 0x6E761F6E6B6B6447
movq %rax, 20(%rsp)
movl $6515569, 28(%rsp) # imm = 0x636B71
leaq 20(%rsp), %rbx
movq %rbx, %rdi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $11, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $11, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 10(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z5helloPc, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 20(%rsp), %rbx
movl $11, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5helloPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5helloPc,@object # @_Z5helloPc
.section .rodata,"a",@progbits
.globl _Z5helloPc
.p2align 3, 0x0
_Z5helloPc:
.quad _Z20__device_stub__helloPc
.size _Z5helloPc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5helloPc"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__helloPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5helloPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Includes
#include <stdio.h>
// Constants
#define WPT 128
#define THREADS 512
#define BLOCKS 14*2*4
#define N (BLOCKS*THREADS)
// Kernel
__global__ void pebench(unsigned *A, unsigned *B) {
unsigned i = blockIdx.x*THREADS + threadIdx.x;
unsigned acc = A[i];
for (unsigned w=0; w<WPT; w++) {
acc = acc * acc;
}
B[i] = acc;
}
// Timers
cudaEvent_t start;
void timer_start();
void timer_stop();
// Main function
int main(void) {
unsigned size = N*sizeof(unsigned);
// Allocate and initialise the data
unsigned *A = (unsigned *)malloc(size);
unsigned *B = (unsigned *)malloc(size);
for (unsigned i=0; i<N; i++) {
A[i] = i;
B[i] = 0;
}
// Allocate CUDA arrays
unsigned *devA = 0;
unsigned *devB = 0;
cudaMalloc(&devA, size);
cudaMalloc(&devB, size);
// Copy to the GPU
cudaMemcpy(devA, A, size, cudaMemcpyHostToDevice);
// Configure the kernel
dim3 threads(THREADS);
dim3 blocks(BLOCKS);
// Launch the kernel
timer_start();
pebench<<<blocks, threads>>>(devA, devB);
timer_stop();
// Copy from the GPU
cudaMemcpy(B, devB, size, cudaMemcpyDeviceToHost);
// Clean-up and exit
cudaFree(A);
cudaFree(B);
free(A);
free(B);
return 0;
}
// Start the timer
void timer_start() {
cudaDeviceSynchronize();
cudaEventCreate(&start);
cudaEventRecord(start);
}
// End the timer
void timer_stop() {
cudaDeviceSynchronize();
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float timer = 0;
cudaEventElapsedTime(&timer,start,stop);
printf("Execution time: %.3lf ms \n", timer);
float megabytes = (N*2*sizeof(unsigned)) / (1024*1024.0);
printf("Bandwidth: %.3lf GB/s \n", megabytes/timer);
} | code for sm_80
Function : _Z7pebenchPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ LEA R3, R3, R2, 0x9 ; /* 0x0000000203037211 */
/* 0x001fca00078e48ff */
/*0060*/ IMAD.WIDE.U32 R4, R3, R0, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e0000 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R2, R4, R4, RZ ; /* 0x0000000404027224 */
/* 0x004fc800078e02ff */
/*0090*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0200*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0230*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0240*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0250*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0260*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0280*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0300*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0310*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0320*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0330*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0340*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0370*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0380*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0390*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0400*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0410*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0420*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0430*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0440*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0450*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0460*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0470*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0480*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0490*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0500*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0510*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0520*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0530*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0540*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0550*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0560*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0570*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0580*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0590*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0600*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0610*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0620*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0630*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0640*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0650*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0660*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0670*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0680*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0690*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0700*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0710*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0720*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0730*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0740*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0750*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0760*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0770*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0780*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0790*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0800*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0810*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0820*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0830*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0840*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0850*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0860*/ IMAD R4, R2, R2, RZ ; /* 0x0000000202047224 */
/* 0x000fe400078e02ff */
/*0870*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0000 */
/*0880*/ IMAD R5, R4, R4, RZ ; /* 0x0000000404057224 */
/* 0x000fca00078e02ff */
/*0890*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Includes
#include <stdio.h>
// Constants
#define WPT 128
#define THREADS 512
#define BLOCKS 14*2*4
#define N (BLOCKS*THREADS)
// Kernel
__global__ void pebench(unsigned *A, unsigned *B) {
unsigned i = blockIdx.x*THREADS + threadIdx.x;
unsigned acc = A[i];
for (unsigned w=0; w<WPT; w++) {
acc = acc * acc;
}
B[i] = acc;
}
// Timers
cudaEvent_t start;
void timer_start();
void timer_stop();
// Main function
int main(void) {
unsigned size = N*sizeof(unsigned);
// Allocate and initialise the data
unsigned *A = (unsigned *)malloc(size);
unsigned *B = (unsigned *)malloc(size);
for (unsigned i=0; i<N; i++) {
A[i] = i;
B[i] = 0;
}
// Allocate CUDA arrays
unsigned *devA = 0;
unsigned *devB = 0;
cudaMalloc(&devA, size);
cudaMalloc(&devB, size);
// Copy to the GPU
cudaMemcpy(devA, A, size, cudaMemcpyHostToDevice);
// Configure the kernel
dim3 threads(THREADS);
dim3 blocks(BLOCKS);
// Launch the kernel
timer_start();
pebench<<<blocks, threads>>>(devA, devB);
timer_stop();
// Copy from the GPU
cudaMemcpy(B, devB, size, cudaMemcpyDeviceToHost);
// Clean-up and exit
cudaFree(A);
cudaFree(B);
free(A);
free(B);
return 0;
}
// Start the timer
void timer_start() {
cudaDeviceSynchronize();
cudaEventCreate(&start);
cudaEventRecord(start);
}
// End the timer
void timer_stop() {
cudaDeviceSynchronize();
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float timer = 0;
cudaEventElapsedTime(&timer,start,stop);
printf("Execution time: %.3lf ms \n", timer);
float megabytes = (N*2*sizeof(unsigned)) / (1024*1024.0);
printf("Bandwidth: %.3lf GB/s \n", megabytes/timer);
} | .file "tmpxft_000a50ad_00000000-6_pebench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11timer_startv
.type _Z11timer_startv, @function
_Z11timer_startv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaDeviceSynchronize@PLT
leaq start(%rip), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq start(%rip), %rdi
call cudaEventRecord@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11timer_startv, .-_Z11timer_startv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Execution time: %.3lf ms \n"
.LC3:
.string "Bandwidth: %.3lf GB/s \n"
.text
.globl _Z10timer_stopv
.type _Z10timer_stopv, @function
_Z10timer_stopv:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 16(%rsp), %rdx
movq start(%rip), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC2(%rip), %xmm0
divss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10timer_stopv, .-_Z10timer_stopv
.globl _Z28__device_stub__Z7pebenchPjS_PjS_
.type _Z28__device_stub__Z7pebenchPjS_PjS_, @function
_Z28__device_stub__Z7pebenchPjS_PjS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7pebenchPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z7pebenchPjS_PjS_, .-_Z28__device_stub__Z7pebenchPjS_PjS_
.globl _Z7pebenchPjS_
.type _Z7pebenchPjS_, @function
_Z7pebenchPjS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7pebenchPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7pebenchPjS_, .-_Z7pebenchPjS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $229376, %edi
call malloc@PLT
movq %rax, %rbp
movl $229376, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L18:
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $57344, %rax
jne .L18
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $229376, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $229376, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $229376, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $112, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
call _Z11timer_startv
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call _Z10timer_stopv
movl $2, %ecx
movl $229376, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7pebenchPjS_PjS_
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7pebenchPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7pebenchPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl start
.bss
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1054867456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Includes
#include <stdio.h>
// Constants
#define WPT 128
#define THREADS 512
#define BLOCKS 14*2*4
#define N (BLOCKS*THREADS)
// Kernel
__global__ void pebench(unsigned *A, unsigned *B) {
unsigned i = blockIdx.x*THREADS + threadIdx.x;
unsigned acc = A[i];
for (unsigned w=0; w<WPT; w++) {
acc = acc * acc;
}
B[i] = acc;
}
// Timers
cudaEvent_t start;
void timer_start();
void timer_stop();
// Main function
int main(void) {
unsigned size = N*sizeof(unsigned);
// Allocate and initialise the data
unsigned *A = (unsigned *)malloc(size);
unsigned *B = (unsigned *)malloc(size);
for (unsigned i=0; i<N; i++) {
A[i] = i;
B[i] = 0;
}
// Allocate CUDA arrays
unsigned *devA = 0;
unsigned *devB = 0;
cudaMalloc(&devA, size);
cudaMalloc(&devB, size);
// Copy to the GPU
cudaMemcpy(devA, A, size, cudaMemcpyHostToDevice);
// Configure the kernel
dim3 threads(THREADS);
dim3 blocks(BLOCKS);
// Launch the kernel
timer_start();
pebench<<<blocks, threads>>>(devA, devB);
timer_stop();
// Copy from the GPU
cudaMemcpy(B, devB, size, cudaMemcpyDeviceToHost);
// Clean-up and exit
cudaFree(A);
cudaFree(B);
free(A);
free(B);
return 0;
}
// Start the timer
void timer_start() {
cudaDeviceSynchronize();
cudaEventCreate(&start);
cudaEventRecord(start);
}
// End the timer
void timer_stop() {
cudaDeviceSynchronize();
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float timer = 0;
cudaEventElapsedTime(&timer,start,stop);
printf("Execution time: %.3lf ms \n", timer);
float megabytes = (N*2*sizeof(unsigned)) / (1024*1024.0);
printf("Bandwidth: %.3lf GB/s \n", megabytes/timer);
} | // Includes
#include <hip/hip_runtime.h>
#include <stdio.h>
// Constants
#define WPT 128
#define THREADS 512
#define BLOCKS 14*2*4
#define N (BLOCKS*THREADS)
// Kernel
__global__ void pebench(unsigned *A, unsigned *B) {
unsigned i = blockIdx.x*THREADS + threadIdx.x;
unsigned acc = A[i];
for (unsigned w=0; w<WPT; w++) {
acc = acc * acc;
}
B[i] = acc;
}
// Timers
hipEvent_t start;
void timer_start();
void timer_stop();
// Main function
int main(void) {
unsigned size = N*sizeof(unsigned);
// Allocate and initialise the data
unsigned *A = (unsigned *)malloc(size);
unsigned *B = (unsigned *)malloc(size);
for (unsigned i=0; i<N; i++) {
A[i] = i;
B[i] = 0;
}
// Allocate CUDA arrays
unsigned *devA = 0;
unsigned *devB = 0;
hipMalloc(&devA, size);
hipMalloc(&devB, size);
// Copy to the GPU
hipMemcpy(devA, A, size, hipMemcpyHostToDevice);
// Configure the kernel
dim3 threads(THREADS);
dim3 blocks(BLOCKS);
// Launch the kernel
timer_start();
pebench<<<blocks, threads>>>(devA, devB);
timer_stop();
// Copy from the GPU
hipMemcpy(B, devB, size, hipMemcpyDeviceToHost);
// Clean-up and exit
hipFree(A);
hipFree(B);
free(A);
free(B);
return 0;
}
// Start the timer
void timer_start() {
hipDeviceSynchronize();
hipEventCreate(&start);
hipEventRecord(start);
}
// End the timer
void timer_stop() {
hipDeviceSynchronize();
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(stop);
hipEventSynchronize(stop);
float timer = 0;
hipEventElapsedTime(&timer,start,stop);
printf("Execution time: %.3lf ms \n", timer);
float megabytes = (N*2*sizeof(unsigned)) / (1024*1024.0);
printf("Bandwidth: %.3lf GB/s \n", megabytes/timer);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Includes
#include <hip/hip_runtime.h>
#include <stdio.h>
// Constants
#define WPT 128
#define THREADS 512
#define BLOCKS 14*2*4
#define N (BLOCKS*THREADS)
// Kernel
__global__ void pebench(unsigned *A, unsigned *B) {
unsigned i = blockIdx.x*THREADS + threadIdx.x;
unsigned acc = A[i];
for (unsigned w=0; w<WPT; w++) {
acc = acc * acc;
}
B[i] = acc;
}
// Timers
hipEvent_t start;
void timer_start();
void timer_stop();
// Main function
int main(void) {
unsigned size = N*sizeof(unsigned);
// Allocate and initialise the data
unsigned *A = (unsigned *)malloc(size);
unsigned *B = (unsigned *)malloc(size);
for (unsigned i=0; i<N; i++) {
A[i] = i;
B[i] = 0;
}
// Allocate CUDA arrays
unsigned *devA = 0;
unsigned *devB = 0;
hipMalloc(&devA, size);
hipMalloc(&devB, size);
// Copy to the GPU
hipMemcpy(devA, A, size, hipMemcpyHostToDevice);
// Configure the kernel
dim3 threads(THREADS);
dim3 blocks(BLOCKS);
// Launch the kernel
timer_start();
pebench<<<blocks, threads>>>(devA, devB);
timer_stop();
// Copy from the GPU
hipMemcpy(B, devB, size, hipMemcpyDeviceToHost);
// Clean-up and exit
hipFree(A);
hipFree(B);
free(A);
free(B);
return 0;
}
// Start the timer
void timer_start() {
hipDeviceSynchronize();
hipEventCreate(&start);
hipEventRecord(start);
}
// End the timer
void timer_stop() {
hipDeviceSynchronize();
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(stop);
hipEventSynchronize(stop);
float timer = 0;
hipEventElapsedTime(&timer,start,stop);
printf("Execution time: %.3lf ms \n", timer);
float megabytes = (N*2*sizeof(unsigned)) / (1024*1024.0);
printf("Bandwidth: %.3lf GB/s \n", megabytes/timer);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7pebenchPjS_
.globl _Z7pebenchPjS_
.p2align 8
.type _Z7pebenchPjS_,@function
_Z7pebenchPjS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_lshl_add_u32 v0, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_movk_i32 s2, 0x80
global_load_b32 v2, v[2:3], off
.LBB0_1:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v2, v2
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7pebenchPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7pebenchPjS_, .Lfunc_end0-_Z7pebenchPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7pebenchPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7pebenchPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Includes
#include <hip/hip_runtime.h>
#include <stdio.h>
// Constants
#define WPT 128
#define THREADS 512
#define BLOCKS 14*2*4
#define N (BLOCKS*THREADS)
// Kernel
__global__ void pebench(unsigned *A, unsigned *B) {
unsigned i = blockIdx.x*THREADS + threadIdx.x;
unsigned acc = A[i];
for (unsigned w=0; w<WPT; w++) {
acc = acc * acc;
}
B[i] = acc;
}
// Timers
hipEvent_t start;
void timer_start();
void timer_stop();
// Main function
int main(void) {
unsigned size = N*sizeof(unsigned);
// Allocate and initialise the data
unsigned *A = (unsigned *)malloc(size);
unsigned *B = (unsigned *)malloc(size);
for (unsigned i=0; i<N; i++) {
A[i] = i;
B[i] = 0;
}
// Allocate CUDA arrays
unsigned *devA = 0;
unsigned *devB = 0;
hipMalloc(&devA, size);
hipMalloc(&devB, size);
// Copy to the GPU
hipMemcpy(devA, A, size, hipMemcpyHostToDevice);
// Configure the kernel
dim3 threads(THREADS);
dim3 blocks(BLOCKS);
// Launch the kernel
timer_start();
pebench<<<blocks, threads>>>(devA, devB);
timer_stop();
// Copy from the GPU
hipMemcpy(B, devB, size, hipMemcpyDeviceToHost);
// Clean-up and exit
hipFree(A);
hipFree(B);
free(A);
free(B);
return 0;
}
// Start the timer
void timer_start() {
hipDeviceSynchronize();
hipEventCreate(&start);
hipEventRecord(start);
}
// End the timer
void timer_stop() {
hipDeviceSynchronize();
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(stop);
hipEventSynchronize(stop);
float timer = 0;
hipEventElapsedTime(&timer,start,stop);
printf("Execution time: %.3lf ms \n", timer);
float megabytes = (N*2*sizeof(unsigned)) / (1024*1024.0);
printf("Bandwidth: %.3lf GB/s \n", megabytes/timer);
} | .text
.file "pebench.hip"
.globl _Z22__device_stub__pebenchPjS_ # -- Begin function _Z22__device_stub__pebenchPjS_
.p2align 4, 0x90
.type _Z22__device_stub__pebenchPjS_,@function
_Z22__device_stub__pebenchPjS_: # @_Z22__device_stub__pebenchPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7pebenchPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__pebenchPjS_, .Lfunc_end0-_Z22__device_stub__pebenchPjS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3ee00000 # float 0.4375
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $229376, %edi # imm = 0x38000
callq malloc
movq %rax, %rbx
movl $229376, %edi # imm = 0x38000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movl $229376, %edx # imm = 0x38000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r15d, (%rbx,%r15,4)
incq %r15
cmpq $57344, %r15 # imm = 0xE000
jne .LBB1_1
# %bb.2:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
leaq 24(%rsp), %rdi
movl $229376, %esi # imm = 0x38000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $229376, %esi # imm = 0x38000
callq hipMalloc
movq 24(%rsp), %rdi
movl $229376, %edx # imm = 0x38000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl $start, %edi
callq hipEventCreate
movq start(%rip), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967408, %rdi # imm = 0x100000070
leaq 400(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rax
movq %rax, 40(%rsp)
movq %rsp, %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7pebenchPjS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $0, (%rsp)
movq start(%rip), %rsi
movq 32(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movl $229376, %edx # imm = 0x38000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11timer_startv # -- Begin function _Z11timer_startv
.p2align 4, 0x90
.type _Z11timer_startv,@function
_Z11timer_startv: # @_Z11timer_startv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipDeviceSynchronize
movl $start, %edi
callq hipEventCreate
movq start(%rip), %rdi
xorl %esi, %esi
popq %rax
.cfi_def_cfa_offset 8
jmp hipEventRecord # TAILCALL
.Lfunc_end2:
.size _Z11timer_startv, .Lfunc_end2-_Z11timer_startv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10timer_stopv
.LCPI3_0:
.long 0x3ee00000 # float 0.4375
.text
.globl _Z10timer_stopv
.p2align 4, 0x90
.type _Z10timer_stopv,@function
_Z10timer_stopv: # @_Z10timer_stopv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 12(%rsp)
movq start(%rip), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10timer_stopv, .Lfunc_end3-_Z10timer_stopv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7pebenchPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7pebenchPjS_,@object # @_Z7pebenchPjS_
.section .rodata,"a",@progbits
.globl _Z7pebenchPjS_
.p2align 3, 0x0
_Z7pebenchPjS_:
.quad _Z22__device_stub__pebenchPjS_
.size _Z7pebenchPjS_, 8
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0
.size start, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Execution time: %.3lf ms \n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Bandwidth: %.3lf GB/s \n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7pebenchPjS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__pebenchPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7pebenchPjS_
.addrsig_sym start
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7pebenchPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ LEA R3, R3, R2, 0x9 ; /* 0x0000000203037211 */
/* 0x001fca00078e48ff */
/*0060*/ IMAD.WIDE.U32 R4, R3, R0, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e0000 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R2, R4, R4, RZ ; /* 0x0000000404027224 */
/* 0x004fc800078e02ff */
/*0090*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*01f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0200*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0210*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0230*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0240*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0250*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0260*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0280*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*02f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0300*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0310*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0320*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0330*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0340*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0370*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0380*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0390*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*03f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0400*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0410*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0420*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0430*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0440*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0450*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0460*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0470*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0480*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0490*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*04f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0500*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0510*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0520*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0530*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0540*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0550*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0560*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0570*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0580*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0590*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*05f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0600*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0610*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0620*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0630*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0640*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0650*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0660*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0670*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0680*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0690*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*06f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0700*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0710*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0720*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0730*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0740*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0750*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0760*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0770*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0780*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0790*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07a0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07b0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07c0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07d0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07e0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*07f0*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0800*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0810*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0820*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0830*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0840*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0850*/ IMAD R2, R2, R2, RZ ; /* 0x0000000202027224 */
/* 0x000fc800078e02ff */
/*0860*/ IMAD R4, R2, R2, RZ ; /* 0x0000000202047224 */
/* 0x000fe400078e02ff */
/*0870*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0000 */
/*0880*/ IMAD R5, R4, R4, RZ ; /* 0x0000000404057224 */
/* 0x000fca00078e02ff */
/*0890*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7pebenchPjS_
.globl _Z7pebenchPjS_
.p2align 8
.type _Z7pebenchPjS_,@function
_Z7pebenchPjS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_lshl_add_u32 v0, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_movk_i32 s2, 0x80
global_load_b32 v2, v[2:3], off
.LBB0_1:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v2, v2
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7pebenchPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7pebenchPjS_, .Lfunc_end0-_Z7pebenchPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7pebenchPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7pebenchPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a50ad_00000000-6_pebench.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11timer_startv
.type _Z11timer_startv, @function
_Z11timer_startv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaDeviceSynchronize@PLT
leaq start(%rip), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq start(%rip), %rdi
call cudaEventRecord@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11timer_startv, .-_Z11timer_startv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Execution time: %.3lf ms \n"
.LC3:
.string "Bandwidth: %.3lf GB/s \n"
.text
.globl _Z10timer_stopv
.type _Z10timer_stopv, @function
_Z10timer_stopv:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 16(%rsp), %rdx
movq start(%rip), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC2(%rip), %xmm0
divss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10timer_stopv, .-_Z10timer_stopv
.globl _Z28__device_stub__Z7pebenchPjS_PjS_
.type _Z28__device_stub__Z7pebenchPjS_PjS_, @function
_Z28__device_stub__Z7pebenchPjS_PjS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7pebenchPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z7pebenchPjS_PjS_, .-_Z28__device_stub__Z7pebenchPjS_PjS_
.globl _Z7pebenchPjS_
.type _Z7pebenchPjS_, @function
_Z7pebenchPjS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7pebenchPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7pebenchPjS_, .-_Z7pebenchPjS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $229376, %edi
call malloc@PLT
movq %rax, %rbp
movl $229376, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L18:
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $57344, %rax
jne .L18
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $229376, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $229376, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $229376, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $112, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
call _Z11timer_startv
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call _Z10timer_stopv
movl $2, %ecx
movl $229376, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7pebenchPjS_PjS_
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7pebenchPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7pebenchPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl start
.bss
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1054867456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pebench.hip"
.globl _Z22__device_stub__pebenchPjS_ # -- Begin function _Z22__device_stub__pebenchPjS_
.p2align 4, 0x90
.type _Z22__device_stub__pebenchPjS_,@function
_Z22__device_stub__pebenchPjS_: # @_Z22__device_stub__pebenchPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7pebenchPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__pebenchPjS_, .Lfunc_end0-_Z22__device_stub__pebenchPjS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3ee00000 # float 0.4375
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $229376, %edi # imm = 0x38000
callq malloc
movq %rax, %rbx
movl $229376, %edi # imm = 0x38000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movl $229376, %edx # imm = 0x38000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r15d, (%rbx,%r15,4)
incq %r15
cmpq $57344, %r15 # imm = 0xE000
jne .LBB1_1
# %bb.2:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
leaq 24(%rsp), %rdi
movl $229376, %esi # imm = 0x38000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $229376, %esi # imm = 0x38000
callq hipMalloc
movq 24(%rsp), %rdi
movl $229376, %edx # imm = 0x38000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl $start, %edi
callq hipEventCreate
movq start(%rip), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967408, %rdi # imm = 0x100000070
leaq 400(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rax
movq %rax, 40(%rsp)
movq %rsp, %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7pebenchPjS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $0, (%rsp)
movq start(%rip), %rsi
movq 32(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movl $229376, %edx # imm = 0x38000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11timer_startv # -- Begin function _Z11timer_startv
.p2align 4, 0x90
.type _Z11timer_startv,@function
_Z11timer_startv: # @_Z11timer_startv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipDeviceSynchronize
movl $start, %edi
callq hipEventCreate
movq start(%rip), %rdi
xorl %esi, %esi
popq %rax
.cfi_def_cfa_offset 8
jmp hipEventRecord # TAILCALL
.Lfunc_end2:
.size _Z11timer_startv, .Lfunc_end2-_Z11timer_startv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10timer_stopv
.LCPI3_0:
.long 0x3ee00000 # float 0.4375
.text
.globl _Z10timer_stopv
.p2align 4, 0x90
.type _Z10timer_stopv,@function
_Z10timer_stopv: # @_Z10timer_stopv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 12(%rsp)
movq start(%rip), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10timer_stopv, .Lfunc_end3-_Z10timer_stopv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7pebenchPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7pebenchPjS_,@object # @_Z7pebenchPjS_
.section .rodata,"a",@progbits
.globl _Z7pebenchPjS_
.p2align 3, 0x0
_Z7pebenchPjS_:
.quad _Z22__device_stub__pebenchPjS_
.size _Z7pebenchPjS_, 8
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0
.size start, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Execution time: %.3lf ms \n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Bandwidth: %.3lf GB/s \n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7pebenchPjS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__pebenchPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7pebenchPjS_
.addrsig_sym start
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//#include <mma.h>
#include <cuda_fp16.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096*4
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//using namespace nvcuda;
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, half *data1, half *data2, half *data3, half *data4, half *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
half s2 = data2[gid];
half s4 = data4[gid];
half2 mult = __halves2half2(s2, s4);
half result1 = data1[gid];
half result2 = data3[gid];
half2 result = __halves2half2(result1, result2);
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
result = result*mult+result;
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = __high2half(result) + __low2half(result);
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
half *data1 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *data2 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *res = (half*) malloc(TOTAL_THREADS*sizeof(half));
uint32_t *startClk_g;
uint32_t *stopClk_g;
half *data1_g;
half *data2_g;
half *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (half)i;
data2[i] = (half)i;
}
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( cudaMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(half), cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(half), cudaMemcpyHostToDevice) );
max_flops<<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, data2_g, data1_g, data2_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(half), cudaMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | .file "tmpxft_0008554b_00000000-6_alu_lat_half.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL15__float2half_rnf, @function
_ZL15__float2half_rnf:
.LFB2186:
.cfi_startproc
movd %xmm0, %edx
movl %edx, %ecx
andl $2147483647, %ecx
movl %edx, %eax
shrl $16, %eax
andl $32768, %eax
cmpl $2139095039, %ecx
jbe .L2
orb $124, %ah
cmpl $2139095040, %ecx
movl $32767, %edx
cmovne %edx, %eax
ret
.L2:
cmpl $1199566847, %ecx
jbe .L4
orw $31743, %ax
jmp .L5
.L4:
cmpl $947912703, %ecx
jbe .L6
movl %ecx, %edi
sall $19, %edi
subl $939524096, %ecx
shrl $13, %ecx
orl %ecx, %eax
.L7:
cmpl $-2147483648, %edi
jbe .L11
.L5:
addl $1, %eax
.L10:
ret
.L6:
cmpl $855638016, %ecx
jbe .L10
movl %ecx, %esi
shrl $23, %esi
andl $8388607, %edx
orl $8388608, %edx
leal -94(%rsi), %ecx
movl %edx, %edi
sall %cl, %edi
movl $126, %ecx
subl %esi, %ecx
shrl %cl, %edx
orl %edx, %eax
jmp .L7
.L11:
jne .L10
testb $1, %al
je .L10
jmp .L5
.cfi_endproc
.LFE2186:
.size _ZL15__float2half_rnf, .-_ZL15__float2half_rnf
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2435:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2435:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2431:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L20
ret
.L20:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L21
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2431:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
.type _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_, @function
_Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_:
.LFB2457:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2457:
.size _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_, .-_Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
.globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, @function
_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_:
.LFB2458:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2458:
.size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, .-_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shen203/GPU_Microbenchmark/master/alu_lat_half/alu_lat_half.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "int32 latency = %f (clk)\n"
.LC5:
.string "Total Clk number = %u \n"
.text
.globl main
.type main, @function
main:
.LFB2432:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $2, %edi
call malloc@PLT
movq %rax, %r15
movl $2, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %edi
call malloc@PLT
movq %rax, %r14
pxor %xmm0, %xmm0
call _ZL15__float2half_rnf
movw %ax, (%r15)
pxor %xmm0, %xmm0
call _ZL15__float2half_rnf
movw %ax, 0(%r13)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $75, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $76, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $77, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $78, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $79, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $2, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $2, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L31:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $88, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $2, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $89, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl (%r12), %eax
subl 0(%rbp), %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl (%r12), %edx
subl 0(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq 48(%rsp)
.cfi_def_cfa_offset 160
movq %rcx, %r9
movq %rdx, %r8
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2432:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2460:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2460:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 947912704
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//#include <mma.h>
#include <cuda_fp16.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096*4
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//using namespace nvcuda;
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, half *data1, half *data2, half *data3, half *data4, half *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
half s2 = data2[gid];
half s4 = data4[gid];
half2 mult = __halves2half2(s2, s4);
half result1 = data1[gid];
half result2 = data3[gid];
half2 result = __halves2half2(result1, result2);
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
result = result*mult+result;
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = __high2half(result) + __low2half(result);
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
half *data1 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *data2 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *res = (half*) malloc(TOTAL_THREADS*sizeof(half));
uint32_t *startClk_g;
uint32_t *stopClk_g;
half *data1_g;
half *data2_g;
half *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (half)i;
data2[i] = (half)i;
}
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( cudaMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(half), cudaMemcpyHostToDevice) );
gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(half), cudaMemcpyHostToDevice) );
max_flops<<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, data2_g, data1_g, data2_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(half), cudaMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//#include <mma.h>
#include <hip/hip_fp16.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096*4
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//using namespace nvcuda;
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, half *data1, half *data2, half *data3, half *data4, half *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
half s2 = data2[gid];
half s4 = data4[gid];
half2 mult = __halves2half2(s2, s4);
half result1 = data1[gid];
half result2 = data3[gid];
half2 result = __halves2half2(result1, result2);
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
result = result*mult+result;
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = __high2half(result) + __low2half(result);
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
half *data1 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *data2 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *res = (half*) malloc(TOTAL_THREADS*sizeof(half));
uint32_t *startClk_g;
uint32_t *stopClk_g;
half *data1_g;
half *data2_g;
half *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (half)i;
data2[i] = (half)i;
}
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMalloc(&data2_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(half), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(half), hipMemcpyHostToDevice) );
max_flops<<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, data2_g, data1_g, data2_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(half), hipMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//#include <mma.h>
#include <hip/hip_fp16.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096*4
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//using namespace nvcuda;
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, half *data1, half *data2, half *data3, half *data4, half *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
half s2 = data2[gid];
half s4 = data4[gid];
half2 mult = __halves2half2(s2, s4);
half result1 = data1[gid];
half result2 = data3[gid];
half2 result = __halves2half2(result1, result2);
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
result = result*mult+result;
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = __high2half(result) + __low2half(result);
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
half *data1 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *data2 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *res = (half*) malloc(TOTAL_THREADS*sizeof(half));
uint32_t *startClk_g;
uint32_t *stopClk_g;
half *data1_g;
half *data2_g;
half *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (half)i;
data2[i] = (half)i;
}
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMalloc(&data2_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(half), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(half), hipMemcpyHostToDevice) );
max_flops<<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, data2_g, data1_g, data2_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(half), hipMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.p2align 8
.type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_,@function
_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b256 s[4:11], s[0:1], 0x10
s_movk_i32 s3, 0x4000
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 1, v[1:2]
v_add_co_u32 v6, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
global_load_u16 v3, v[6:7], off
global_load_u16 v0, v[8:9], off
v_add_co_u32 v6, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_d16_hi_b16 v3, v[6:7], off
global_load_d16_hi_b16 v0, v[4:5], off
bar.sync 0
mov.u32 s2, %clock
.LBB0_1:
s_waitcnt vmcnt(0)
v_pk_fma_f16 v0, v0, v3, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc0 .LBB0_1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x30
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshrrev_b32_e32 v5, 16, v0
v_lshlrev_b64 v[1:2], 1, v[1:2]
bar.sync 0
mov.u32 s3, %clock
v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
v_add_f16_e32 v9, v5, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[5:6], v7, off
global_store_b32 v[3:4], v8, off
global_store_b16 v[0:1], v9, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, .Lfunc_end0-_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//#include <mma.h>
#include <hip/hip_fp16.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096*4
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//using namespace nvcuda;
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, half *data1, half *data2, half *data3, half *data4, half *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
half s2 = data2[gid];
half s4 = data4[gid];
half2 mult = __halves2half2(s2, s4);
half result1 = data1[gid];
half result2 = data3[gid];
half2 result = __halves2half2(result1, result2);
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
result = result*mult+result;
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = __high2half(result) + __low2half(result);
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
half *data1 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *data2 = (half*) malloc(TOTAL_THREADS*sizeof(half));
half *res = (half*) malloc(TOTAL_THREADS*sizeof(half));
uint32_t *startClk_g;
uint32_t *stopClk_g;
half *data1_g;
half *data2_g;
half *res_g;
for (uint32_t i=0; i<TOTAL_THREADS; i++) {
data1[i] = (half)i;
data2[i] = (half)i;
}
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMalloc(&data2_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(half)) );
gpuErrchk( hipMemcpy(data1_g, data1, TOTAL_THREADS*sizeof(half), hipMemcpyHostToDevice) );
gpuErrchk( hipMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(half), hipMemcpyHostToDevice) );
max_flops<<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, data2_g, data1_g, data2_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(half), hipMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | .text
.file "alu_lat_half.hip"
.globl _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ # -- Begin function _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.p2align 4, 0x90
.type _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_,@function
_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_: # @_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_, .Lfunc_end0-_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x38800000 # float 6.10351563E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $2, %edi
callq malloc
movq %rax, %r13
movl $2, %edi
callq malloc
movq %rax, %r12
movl $2, %edi
callq malloc
movq %rax, %r15
movw $0, (%r13)
movw $0, (%r12)
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit20
leaq 16(%rsp), %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit22
leaq 8(%rsp), %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit24
movq %rsp, %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit26
movq 16(%rsp), %rdi
movl $2, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit28
movq 8(%rsp), %rdi
movl $2, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit30
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdi, 88(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit32
movq 32(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit34
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit36
movq (%rsp), %rsi
movl $2, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit38
movl (%r14), %eax
subl (%rbx), %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl (%r14), %esi
subl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $77, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $78, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %r8d
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_,@object # @_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.section .rodata,"a",@progbits
.globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.p2align 3, 0x0
_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_:
.quad _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shen203/GPU_Microbenchmark/master/alu_lat_half/alu_lat_half.hip"
.size .L.str, 121
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "int32 latency = %f (clk)\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008554b_00000000-6_alu_lat_half.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL15__float2half_rnf, @function
_ZL15__float2half_rnf:
.LFB2186:
.cfi_startproc
movd %xmm0, %edx
movl %edx, %ecx
andl $2147483647, %ecx
movl %edx, %eax
shrl $16, %eax
andl $32768, %eax
cmpl $2139095039, %ecx
jbe .L2
orb $124, %ah
cmpl $2139095040, %ecx
movl $32767, %edx
cmovne %edx, %eax
ret
.L2:
cmpl $1199566847, %ecx
jbe .L4
orw $31743, %ax
jmp .L5
.L4:
cmpl $947912703, %ecx
jbe .L6
movl %ecx, %edi
sall $19, %edi
subl $939524096, %ecx
shrl $13, %ecx
orl %ecx, %eax
.L7:
cmpl $-2147483648, %edi
jbe .L11
.L5:
addl $1, %eax
.L10:
ret
.L6:
cmpl $855638016, %ecx
jbe .L10
movl %ecx, %esi
shrl $23, %esi
andl $8388607, %edx
orl $8388608, %edx
leal -94(%rsi), %ecx
movl %edx, %edi
sall %cl, %edi
movl $126, %ecx
subl %esi, %ecx
shrl %cl, %edx
orl %edx, %eax
jmp .L7
.L11:
jne .L10
testb $1, %al
je .L10
jmp .L5
.cfi_endproc
.LFE2186:
.size _ZL15__float2half_rnf, .-_ZL15__float2half_rnf
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2435:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2435:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2431:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L20
ret
.L20:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L21
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2431:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
.type _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_, @function
_Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_:
.LFB2457:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2457:
.size _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_, .-_Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
.globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, @function
_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_:
.LFB2458:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2458:
.size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, .-_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shen203/GPU_Microbenchmark/master/alu_lat_half/alu_lat_half.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "int32 latency = %f (clk)\n"
.LC5:
.string "Total Clk number = %u \n"
.text
.globl main
.type main, @function
main:
.LFB2432:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $2, %edi
call malloc@PLT
movq %rax, %r15
movl $2, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %edi
call malloc@PLT
movq %rax, %r14
pxor %xmm0, %xmm0
call _ZL15__float2half_rnf
movw %ax, (%r15)
pxor %xmm0, %xmm0
call _ZL15__float2half_rnf
movw %ax, 0(%r13)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $75, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $76, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $77, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $78, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $79, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $2, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $2, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L31:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $88, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $2, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $89, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl (%r12), %eax
subl 0(%rbp), %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl (%r12), %edx
subl 0(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq 48(%rsp)
.cfi_def_cfa_offset 160
movq %rcx, %r9
movq %rdx, %r8
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z50__device_stub__Z9max_flopsPjS_P6__halfS1_S1_S1_S1_PjS_P6__halfS1_S1_S1_S1_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2432:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2460:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2460:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 947912704
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "alu_lat_half.hip"
.globl _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_ # -- Begin function _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.p2align 4, 0x90
.type _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_,@function
_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_: # @_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_, .Lfunc_end0-_Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x38800000 # float 6.10351563E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $2, %edi
callq malloc
movq %rax, %r13
movl $2, %edi
callq malloc
movq %rax, %r12
movl $2, %edi
callq malloc
movq %rax, %r15
movw $0, (%r13)
movw $0, (%r12)
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit20
leaq 16(%rsp), %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit22
leaq 8(%rsp), %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit24
movq %rsp, %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit26
movq 16(%rsp), %rdi
movl $2, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit28
movq 8(%rsp), %rdi
movl $2, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit30
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdi, 88(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit32
movq 32(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit34
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit36
movq (%rsp), %rsi
movl $2, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit38
movl (%r14), %eax
subl (%rbx), %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl (%r14), %esi
subl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $77, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $78, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %r8d
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_,@object # @_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.section .rodata,"a",@progbits
.globl _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.p2align 3, 0x0
_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_:
.quad _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.size _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shen203/GPU_Microbenchmark/master/alu_lat_half/alu_lat_half.hip"
.size .L.str, 121
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "int32 latency = %f (clk)\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_flopsPjS_P6__halfS1_S1_S1_S1_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_flopsPjS_P6__halfS1_S1_S1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_flopsPjS_P6__halfS1_S1_S1_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Program to encapsulate Poisson Solver
#include <stdio.h>
#include <string>
#include <string.h>
#include <iostream>
using namespace std;
#define CST_ME 9.109e-31 // electron mass (kg)
#define CST_E 1.602e-19 // electron charge (C)
#define CST_KB 1.381e-23 // boltzmann constant (m^2 kg s^-2 K^-1)
#define CST_EPSILON 8.854e-12 // free space electric permittivity (s^2 C^2 m^-3 kg^-1)
#define CHARGE_DEP_BLOCK_DIM 512 //block dimension for particle2grid kernel
#define JACOBI_BLOCK_DIM 128 //block dimension for jacobi_iteration kernel
#define CN_SCAN_BLOCK_DIM 64 //block dimension for Crank-Nicolson scan kernel
#define CN_MAP_BLOCK_DIM 64 //block dimension for Crank-Nicolson map kernel
extern __shared__ double sh_mem[];
/******************************************************************************
* Helper function to check cuda errors
******************************************************************************/
void cu_check(cudaError_t cuError, const string file, const int line)
{
// function variables
// function body
if (0 == cuError)
{
return;
} else
{
cout << "CUDA error found in file " << file << " at line " << line << ". (error code: " << cuError << ")" << endl;
cout << "Exiting simulation" << endl;
exit(1);
}
}
/******************************************************************************
* Helper function to synchronize the threads
******************************************************************************/
void cu_sync_check(const string file, const int line)
{
// function variables
cudaError_t cuError;
// function body
cudaDeviceSynchronize();
cuError = cudaGetLastError();
if (0 == cuError)
{
return;
} else
{
cout << "CUDA error found in file " << file << " at line " << line << ". (error code: " << cuError << ")" << endl;
cout << "Exiting simulation" << endl;
exit(1);
}
}
/******************************************************************************
* Helper functions for the global static variables
******************************************************************************/
double init_ds(void)
{
// function variables
static double ds = 0.0;
// function body
if (ds == 0.0) ds = 0.1;
return ds;
}
/**********************************************************/
double init_Dl(void)
{
// function variables
static double Dl = 0.0;
// function body
if (Dl == 0.0) {
double ne = 1.0e9;
double Te = 1000.0;
Dl = sqrt(CST_EPSILON*CST_KB*Te/(ne*CST_E*CST_E));
}
return Dl;
}
/**********************************************************/
double init_epsilon0(void)
{
// function variables
double Te;
const double Dl = init_Dl();
static double epsilon0 = 0.0;
// function body
if (epsilon0 == 0.0) {
Te = 1000.0;
epsilon0 = CST_EPSILON; // SI units
epsilon0 /= pow(Dl*sqrt(CST_ME/(CST_KB*Te)),2); // time units
epsilon0 /= CST_E*CST_E; // charge units
epsilon0 *= Dl*Dl*Dl; // length units
epsilon0 *= CST_ME; // mass units
}
//Si epsilon es un double, tal y como están realizadas las operaciones, vale inf
//return epsilon0;
return 1;
}
/**********************************************************/
int init_nn(void)
{
// function variables
static int nn = 201;
// function body
return nn;
}
/******************************************************************************
*
* Jacobi iteration of the Jacobi method, full version that calculates the
* maximum error of the solution, in order to test convergence of the method
*
******************************************************************************/
__global__ void jacobi_iteration (int nn, double ds, double epsilon0, double *g_rho, double *g_phi, double *g_error)
{
/*----------------------------- function body -------------------------*/
// shared memory pointers
double *sh_old_phi= (double *) sh_mem;
double *sh_error = (double *) &sh_old_phi[JACOBI_BLOCK_DIM+2]; // manually set up shared memory
// registers
double new_phi, dummy_rho;
int tid = (int) threadIdx.x;
int sh_tid = (int) threadIdx.x + 1;
int g_tid = (int) (threadIdx.x + blockDim.x * blockIdx.x) + 1;
int bdim = (int) blockDim.x;
int bid = (int) blockIdx.x;
int gdim = (int) gridDim.x;
/*------------------------------ kernel body --------------------------*/
// load phi data from global to shared memory
if (g_tid < nn - 1) sh_old_phi[sh_tid] = g_phi[g_tid];
// load comunication zones, load the edges of the tile of data
if (bid < gdim-1) {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (sh_tid == bdim) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
} else {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (g_tid == nn-2) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
}
// load charge density data into registers
if (g_tid < nn - 1) {
dummy_rho = ds*ds*g_rho[g_tid]/epsilon0;
}
__syncthreads();
// actualize interior mesh points
if (g_tid < nn - 1) {
new_phi = 0.5*(dummy_rho + sh_old_phi[sh_tid-1] + sh_old_phi[sh_tid+1]);
// store new values of phi in global memory
g_phi[g_tid] = new_phi;
// evaluate local errors
sh_error[tid] = fabs(new_phi-sh_old_phi[sh_tid]);
}
__syncthreads();
// reduction for obtaining maximum error in current block
for (int stride = 1; stride < bdim; stride <<= 1) {
if ((tid%(stride*2) == 0) && (tid+stride < bdim) && (g_tid+stride < nn-1)) {
if (sh_error[tid]<sh_error[tid+stride]) sh_error[tid] = sh_error[tid+stride];
}
__syncthreads();
}
// store maximun error in global memory
if (tid == 0) g_error[bid] = sh_error[tid];
return;
}
/******************************************************************************
*
* Jacobi iteration of the Jacobi method, version that does not calculates
* maximum error
*
******************************************************************************/
__global__ void jacobi_iter_no_error (int nn, double ds, double epsilon0, double *g_rho, double *g_phi)
{
/*----------------------------- function body -------------------------*/
// shared memory pointers
double *sh_old_phi= (double *) sh_mem;
// registers
double new_phi, dummy_rho;
int sh_tid = (int) threadIdx.x + 1;
int g_tid = (int) (threadIdx.x + blockDim.x * blockIdx.x) + 1;
int bdim = (int) blockDim.x;
int bid = (int) blockIdx.x;
int gdim = (int) gridDim.x;
/*------------------------------ kernel body --------------------------*/
// load phi data from global to shared memory
if (g_tid < nn - 1) sh_old_phi[sh_tid] = g_phi[g_tid];
// load comunication zones, load the edges of the tile of data
if (bid < gdim-1) {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (sh_tid == bdim) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
} else {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (g_tid == nn-2) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
}
// load charge density data into registers
if (g_tid < nn - 1) {
dummy_rho = ds*ds*g_rho[g_tid]/epsilon0;
}
__syncthreads();
// actualize interior mesh points
if (g_tid < nn - 1) {
new_phi = 0.5*(dummy_rho + sh_old_phi[sh_tid-1] + sh_old_phi[sh_tid+1]);
// store new values of phi in global memory
g_phi[g_tid] = new_phi;
}
return;
}
/******************************************************************************
*
* This function solves Poisson's equation by means of the Jacobi method in the
* GPU. Based in the work by Antonio Tejero-del-Caz for his PhD. Jacobi method
* is iterative, and the error has to be calculated every iteration until it
* reaches an acceptable value.
*
* Checking error takes around 9 times longer than no checking, so we could
* check every 9 iterations or more.
*
* In practice, as there is a minimum number of iterations according to theory,
* the minimum number of iterations is always enough to obtain an acceptable
* error.
*
******************************************************************************/
void poisson_solver_jacobi(double max_error, double *d_rho, double *d_phi)
{
/*--------------------------- function variables -----------------------*/
// host memory pointers
static const double ds = init_ds(); // spatial step
static const int nn = init_nn(); // number of nodes
static const double epsilon0 = init_epsilon0(); // electric permitivity of free space
double *h_error;
double t_error = max_error*10;
// Jacobi method is iterative, here we save the min number of iteration according
// to theory so that the solution is valid. It turns out to be enough to have
// the minimum error that it can be obtained using this method, so that it always
// performs the same number of iterations
int min_iteration = 2*nn;
dim3 blockdim, griddim;
size_t sh_mem_size;
cudaError_t cuError;
// device memory pointers
double *d_error;
/*----------------------------- function body -------------------------*/
// set dimensions of grid of blocks and blocks of threads for jacobi kernel
blockdim = JACOBI_BLOCK_DIM;
griddim = (int) ((nn-2)/JACOBI_BLOCK_DIM) + 1;
// define size of shared memory for jacobi_iteration kernel
sh_mem_size = (2*JACOBI_BLOCK_DIM+2)*sizeof(double);
// allocate host and device memory for vector of errors
cuError = cudaMalloc((void **) &d_error, griddim.x*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
h_error = (double*) malloc(griddim.x*sizeof(double));
int iter_count = 0;
// execute jacobi iterations until solved
// no need to check error until minimum number of interations is reached
while(min_iteration>0) {
// execute all but one iteration without checking errors
cudaGetLastError();
jacobi_iter_no_error<<<griddim, blockdim, sizeof(double)>>>(nn, ds, epsilon0, d_rho, d_phi);
min_iteration--;
}
while (t_error>=max_error) {
// execute at least one iteration checking errors
cudaGetLastError();
jacobi_iteration<<<griddim, blockdim, sh_mem_size>>>(nn, ds, epsilon0, d_rho, d_phi, d_error);
cu_sync_check(__FILE__, __LINE__);
// copy error vector from device to host memory
cuError = cudaMemcpy(h_error, d_error, griddim.x*sizeof(double), cudaMemcpyDeviceToHost);
cu_check(cuError, __FILE__, __LINE__);
// evaluate max error of the iteration
t_error = 0;
for (int i = 0; i<griddim.x; i++)
{
if (h_error[i] > t_error) t_error = h_error[i];
}
iter_count++;
}
printf("iter_count = %i\n", iter_count);
// free device memory
cudaFree(d_error);
free(h_error);
return;
}
/*************************************************************************
*
* Here we find the modification to include the Crank-Nicholson method
* for Poisson's equation solver. These kernels are executed in the same
* order as they are declared.
*
* The Crank-Nocholson algorithm is basicly a exact method that performs
* two sums over the elements of the input array, with coefficients that
* depend on the system of differental equations. As Poisson's equation
* is the same in all the iterations, the method does not change. Moreover,
* as the system has certain periodicities, the coefficients can be
* calculated before programming time and introduced in the sums.
*
* The sums over many elements are performed using the scan algorithm,
* modified with the coefficients for the method. The synchronization
* threads can be performed in the same kernel, but the synchronazation
* between the blocks required ending the kernels and running the next.
*
*************************************************************************/
__global__ void cn_map_rho(double* d_temp1, double* d_rho, double ds, double epsilon0, int max_idx) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
d_temp1[idx] = -((double) idx+1)*ds*ds*d_rho[idx]/epsilon0;
}
}
/**********************************************************/
__global__ void cn_fw_part_scan(double *d_des, double *d_src, int max_idx) {
// We start the algorithm knowing that we will need to use more than one block
double *sh_src= (double *) sh_mem;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
sh_src[threadIdx.x] = d_src[idx];
__syncthreads();
// SCAN OVER SH_src:
// reduction over the elements on the left
for (int stride = 1; stride<blockDim.x; stride = stride*2) {
int k = threadIdx.x - stride;
if (k>=0) {
sh_src[threadIdx.x] += sh_src[k];
}
__syncthreads();
}
d_des[idx] = sh_src[threadIdx.x];
}
return;
}
/**********************************************************/
__global__ void cn_fw_glob_scan(double *d_des, double* d_src, int max_idx, double* d_phi) {
// It is necessary to synchronize all the blocks, which can only be done by
// ending the kernel and starting a new one
double *sh_acum = (double *) sh_mem;
double *sh_phi_0 = (double *) &sh_mem[1];
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx < max_idx) {
// first thread saves the acum
if (threadIdx.x == 0) {
double r_acum = 0.0;
for (int i = blockDim.x-1; i<blockIdx.x*blockDim.x; i+=blockDim.x) {
r_acum += d_src[i];
}
sh_acum[0] = r_acum;
}
// first thread of the other blocks
if ((threadIdx.x == blockDim.x-1)||(idx==max_idx-1)) {
sh_phi_0[0] = d_phi[0];
}
}
__syncthreads();
if (idx < max_idx) {
//d_des[idx] = sh_acum[0] + d_src[idx]; // this line woould be a simple scan, no coefs
d_des[idx] = (sh_acum[0] + d_src[idx]- sh_phi_0[0])/((double) (idx+1)*(idx+2));
}
}
/**********************************************************/
__global__ void cn_bw_part_scan(double *d_des, double *d_src, int max_idx) {
// block kernel, d_des can be equal to d_src
double *sh_src= (double *) sh_mem;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
sh_src[threadIdx.x] = d_src[idx];
__syncthreads();
// SCAN over SH_src inverted:
// reduction over the elements on the left
for (int stride = 1; stride<blockDim.x; stride = stride*2) {
int k = threadIdx.x + stride;
// it is necessary to check if it is the last block
if (blockIdx.x ==gridDim.x - 1) {
if (k<max_idx%blockDim.x) {
sh_src[threadIdx.x] += sh_src[k];
}
} else {
if (k<blockDim.x) {
sh_src[threadIdx.x] += sh_src[k];
}
}
__syncthreads();
}
d_des[idx] = sh_src[threadIdx.x];
}
}
/**********************************************************/
__global__ void cn_bw_glob_scan(double *d_des, double* d_src, int max_idx, double* d_phi_L) {
// It is necessary to synchronize all the blocks, which can only be done by
// ending the kernel and starting a new one
// global kernel, d_des cannot be the same as d_src
double *sh_acum= (double *) sh_mem;
double *sh_phi_L = (double *) &sh_mem[1];
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
if (threadIdx.x == 0) {
double r_acum = 0.0;
for (int i = (blockIdx.x+1)*blockDim.x; i<max_idx; i+=blockDim.x) {
r_acum += d_src[i];
}
sh_acum[0] = r_acum;
}
if ((threadIdx.x == blockDim.x-1)||(idx==max_idx-1)) {
sh_phi_L[0] = d_phi_L[0]/((double) max_idx+1); // max_idx+1 == nn-1
}
__syncthreads();
d_des[idx] = (sh_phi_L[0]-sh_acum[0]-d_src[idx])*((double) idx+1);
}
}
/**********************************************************/
void poisson_solver_cn(double max_error, double *d_rho, double *d_phi) {
// It is necessary to synchronize all the blocks, which can only be done by
// ending the kernel and starting a new one
// max_error is conserved for compatibility with poisson_solver_jacobi
// In PIC code, just change the library, it has the same function poisson_solver
// global variables in host
int nn = init_nn();
double epsilon0 = init_epsilon0();
double ds = init_ds();
cudaError_t cuError;
// Allocate device memory
double* d_temp1;
cuError = cudaMalloc ((void **) &d_temp1, (nn-2)*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
double* d_temp2;
cuError = cudaMalloc ((void **) &d_temp2, (nn-2)*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
// Size of grids for each part of the algorithm
int map_blocks_per_grid = (nn+CN_MAP_BLOCK_DIM-1)/CN_MAP_BLOCK_DIM;
int scan_blocks_per_grid = (nn-2+CN_SCAN_BLOCK_DIM-1)/CN_SCAN_BLOCK_DIM;
// Shared mem for scan part
size_t sh_mem_size;
sh_mem_size = (CN_SCAN_BLOCK_DIM)*sizeof(double);
// Obtain rho_1, stored in d_temp1
cn_map_rho<<<map_blocks_per_grid, CN_MAP_BLOCK_DIM>>>(d_temp1, &d_rho[1], ds, epsilon0, nn-2);
// Obtain D_2, stored in d_temp1. Modified to substract d_phi[0], even if it is not part of scan
cn_fw_part_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, sh_mem_size>>>(d_temp2, d_temp1, nn-2);
cn_fw_glob_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, 2*sizeof(double)>>>(d_temp1, d_temp2, nn-2, d_phi);
// Obtain d_phi. Modified to add d_phi[nn-1]
cn_bw_part_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, sh_mem_size>>>(d_temp2, d_temp1, nn-2);
cn_bw_glob_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, 2*sizeof(double)>>>(&d_phi[1], d_temp2, nn-2, &d_phi[nn-1]);
cudaFree(d_temp1);
cudaFree(d_temp2);
}
/******************************************************************************
* main
******************************************************************************/
int main(int argc, char** argv) {
printf("Initiating Poisson Solver Capsule to compare different algorithms\n\n");
cudaDeviceReset();
int nn = init_nn();
int nc = nn-1;
double max_error = 1.0e-4;
cudaError_t cuError;
// Initialize the memories
double* h_rho = (double*) malloc(nn*sizeof(double));
double* h_phi = (double*) malloc(nn*sizeof(double));
double* d_rho;
double* d_phi;
cuError = cudaMalloc ((void **) &d_rho, nn*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
cuError = cudaMalloc ((void **) &d_phi, nn*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
double phi_0 = 0.5;
double phi_L = 2.0;
double x_0 = 0.0;
double ds = init_ds();
double x_L = nn*ds;
// Initialize h_rho anyway, no influence in the calculation time (Care with overflows)
for (int i=0; i<nn; i++) {
h_rho[i] = 1.0;
h_phi[i] = phi_0 + ((double) i)*(phi_L - phi_0)/((double) nc);
}
// Copy to device
cuError = cudaMemcpy(d_rho, h_rho, nn*sizeof(double), cudaMemcpyHostToDevice);
cu_check(cuError, __FILE__, __LINE__);
cuError = cudaMemcpy(d_phi, h_phi, nn*sizeof(double), cudaMemcpyHostToDevice);
cu_check(cuError, __FILE__, __LINE__);
// RUNS PoissonSolver once, uncomment to run
poisson_solver_cn(max_error, d_rho, d_phi);
// RUNS PoissonSolver many times, uncomment to run
// for (int i=0;i<100000;i++) poisson_solver_cn(max_error, d_rho, d_phi);
// RUNS PoissonSolver many times, uncomment to run
// for (int i=0;i<1000;i++) poisson_solver_jacobi(max_error, d_rho, d_phi);
// FROM WHERE we obtain the following measures
// 1e6 repetitions of poisson_solver_cn takes 108 seconds
// => each repetition takes 0.1ms (as expected)
// 1000 repetitions of jacobi with error calculation every iteration (original)
// take 37 seconds
// => each repetition takes 37 ms
// 10000 iteraciones de jacobi poisson_solver, modified for no error checking
// take 42 segundos
// => cada una 4.2 ms, great improvement!!
// CONCLUSION: Jacobi method without error checking is 9 times faster
// Crank-Nicholson method is 370 times faster (programming time is worth the effort)
// Bring back d_phi to host
cuError = cudaMemcpy(h_phi, d_phi, nn*sizeof(double), cudaMemcpyDeviceToHost);
cu_check(cuError, __FILE__, __LINE__);
cuError = cudaMemcpy(h_rho, d_rho, nn*sizeof(double), cudaMemcpyDeviceToHost);
cu_check(cuError, __FILE__, __LINE__);
for (int i=0; i<nn; i++) {
printf("%g\t%g\t%g\n",x_0 + ((double) i)*(x_L-x_0)/((double) nc), h_rho[i], h_phi[i]);
}
// Free memory
free(h_rho);
free(h_phi);
cudaFree (d_rho);
cudaFree (d_phi);
} | // Program to encapsulate Poisson Solver
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <string>
#include <string.h>
#include <iostream>
using namespace std;
#define CST_ME 9.109e-31 // electron mass (kg)
#define CST_E 1.602e-19 // electron charge (C)
#define CST_KB 1.381e-23 // boltzmann constant (m^2 kg s^-2 K^-1)
#define CST_EPSILON 8.854e-12 // free space electric permittivity (s^2 C^2 m^-3 kg^-1)
#define CHARGE_DEP_BLOCK_DIM 512 //block dimension for particle2grid kernel
#define JACOBI_BLOCK_DIM 128 //block dimension for jacobi_iteration kernel
#define CN_SCAN_BLOCK_DIM 64 //block dimension for Crank-Nicolson scan kernel
#define CN_MAP_BLOCK_DIM 64 //block dimension for Crank-Nicolson map kernel
extern __shared__ double sh_mem[];
/******************************************************************************
* Helper function to check cuda errors
******************************************************************************/
void cu_check(hipError_t cuError, const string file, const int line)
{
// function variables
// function body
if (0 == cuError)
{
return;
} else
{
cout << "CUDA error found in file " << file << " at line " << line << ". (error code: " << cuError << ")" << endl;
cout << "Exiting simulation" << endl;
exit(1);
}
}
/******************************************************************************
* Helper function to synchronize the threads
******************************************************************************/
void cu_sync_check(const string file, const int line)
{
// function variables
hipError_t cuError;
// function body
hipDeviceSynchronize();
cuError = hipGetLastError();
if (0 == cuError)
{
return;
} else
{
cout << "CUDA error found in file " << file << " at line " << line << ". (error code: " << cuError << ")" << endl;
cout << "Exiting simulation" << endl;
exit(1);
}
}
/******************************************************************************
* Helper functions for the global static variables
******************************************************************************/
double init_ds(void)
{
// function variables
static double ds = 0.0;
// function body
if (ds == 0.0) ds = 0.1;
return ds;
}
/**********************************************************/
double init_Dl(void)
{
// function variables
static double Dl = 0.0;
// function body
if (Dl == 0.0) {
double ne = 1.0e9;
double Te = 1000.0;
Dl = sqrt(CST_EPSILON*CST_KB*Te/(ne*CST_E*CST_E));
}
return Dl;
}
/**********************************************************/
double init_epsilon0(void)
{
// function variables
double Te;
const double Dl = init_Dl();
static double epsilon0 = 0.0;
// function body
if (epsilon0 == 0.0) {
Te = 1000.0;
epsilon0 = CST_EPSILON; // SI units
epsilon0 /= pow(Dl*sqrt(CST_ME/(CST_KB*Te)),2); // time units
epsilon0 /= CST_E*CST_E; // charge units
epsilon0 *= Dl*Dl*Dl; // length units
epsilon0 *= CST_ME; // mass units
}
//Si epsilon es un double, tal y como están realizadas las operaciones, vale inf
//return epsilon0;
return 1;
}
/**********************************************************/
int init_nn(void)
{
// function variables
static int nn = 201;
// function body
return nn;
}
/******************************************************************************
*
* Jacobi iteration of the Jacobi method, full version that calculates the
* maximum error of the solution, in order to test convergence of the method
*
******************************************************************************/
__global__ void jacobi_iteration (int nn, double ds, double epsilon0, double *g_rho, double *g_phi, double *g_error)
{
/*----------------------------- function body -------------------------*/
// shared memory pointers
double *sh_old_phi= (double *) sh_mem;
double *sh_error = (double *) &sh_old_phi[JACOBI_BLOCK_DIM+2]; // manually set up shared memory
// registers
double new_phi, dummy_rho;
int tid = (int) threadIdx.x;
int sh_tid = (int) threadIdx.x + 1;
int g_tid = (int) (threadIdx.x + blockDim.x * blockIdx.x) + 1;
int bdim = (int) blockDim.x;
int bid = (int) blockIdx.x;
int gdim = (int) gridDim.x;
/*------------------------------ kernel body --------------------------*/
// load phi data from global to shared memory
if (g_tid < nn - 1) sh_old_phi[sh_tid] = g_phi[g_tid];
// load comunication zones, load the edges of the tile of data
if (bid < gdim-1) {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (sh_tid == bdim) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
} else {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (g_tid == nn-2) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
}
// load charge density data into registers
if (g_tid < nn - 1) {
dummy_rho = ds*ds*g_rho[g_tid]/epsilon0;
}
__syncthreads();
// actualize interior mesh points
if (g_tid < nn - 1) {
new_phi = 0.5*(dummy_rho + sh_old_phi[sh_tid-1] + sh_old_phi[sh_tid+1]);
// store new values of phi in global memory
g_phi[g_tid] = new_phi;
// evaluate local errors
sh_error[tid] = fabs(new_phi-sh_old_phi[sh_tid]);
}
__syncthreads();
// reduction for obtaining maximum error in current block
for (int stride = 1; stride < bdim; stride <<= 1) {
if ((tid%(stride*2) == 0) && (tid+stride < bdim) && (g_tid+stride < nn-1)) {
if (sh_error[tid]<sh_error[tid+stride]) sh_error[tid] = sh_error[tid+stride];
}
__syncthreads();
}
// store maximun error in global memory
if (tid == 0) g_error[bid] = sh_error[tid];
return;
}
/******************************************************************************
*
* Jacobi iteration of the Jacobi method, version that does not calculates
* maximum error
*
******************************************************************************/
__global__ void jacobi_iter_no_error (int nn, double ds, double epsilon0, double *g_rho, double *g_phi)
{
/*----------------------------- function body -------------------------*/
// shared memory pointers
double *sh_old_phi= (double *) sh_mem;
// registers
double new_phi, dummy_rho;
int sh_tid = (int) threadIdx.x + 1;
int g_tid = (int) (threadIdx.x + blockDim.x * blockIdx.x) + 1;
int bdim = (int) blockDim.x;
int bid = (int) blockIdx.x;
int gdim = (int) gridDim.x;
/*------------------------------ kernel body --------------------------*/
// load phi data from global to shared memory
if (g_tid < nn - 1) sh_old_phi[sh_tid] = g_phi[g_tid];
// load comunication zones, load the edges of the tile of data
if (bid < gdim-1) {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (sh_tid == bdim) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
} else {
if (sh_tid == 1) sh_old_phi[sh_tid-1] = g_phi[g_tid-1];
if (g_tid == nn-2) sh_old_phi[sh_tid+1] = g_phi[g_tid+1];
}
// load charge density data into registers
if (g_tid < nn - 1) {
dummy_rho = ds*ds*g_rho[g_tid]/epsilon0;
}
__syncthreads();
// actualize interior mesh points
if (g_tid < nn - 1) {
new_phi = 0.5*(dummy_rho + sh_old_phi[sh_tid-1] + sh_old_phi[sh_tid+1]);
// store new values of phi in global memory
g_phi[g_tid] = new_phi;
}
return;
}
/******************************************************************************
*
* This function solves Poisson's equation by means of the Jacobi method in the
* GPU. Based in the work by Antonio Tejero-del-Caz for his PhD. Jacobi method
* is iterative, and the error has to be calculated every iteration until it
* reaches an acceptable value.
*
* Checking error takes around 9 times longer than no checking, so we could
* check every 9 iterations or more.
*
* In practice, as there is a minimum number of iterations according to theory,
* the minimum number of iterations is always enough to obtain an acceptable
* error.
*
******************************************************************************/
void poisson_solver_jacobi(double max_error, double *d_rho, double *d_phi)
{
/*--------------------------- function variables -----------------------*/
// host memory pointers
static const double ds = init_ds(); // spatial step
static const int nn = init_nn(); // number of nodes
static const double epsilon0 = init_epsilon0(); // electric permitivity of free space
double *h_error;
double t_error = max_error*10;
// Jacobi method is iterative, here we save the min number of iteration according
// to theory so that the solution is valid. It turns out to be enough to have
// the minimum error that it can be obtained using this method, so that it always
// performs the same number of iterations
int min_iteration = 2*nn;
dim3 blockdim, griddim;
size_t sh_mem_size;
hipError_t cuError;
// device memory pointers
double *d_error;
/*----------------------------- function body -------------------------*/
// set dimensions of grid of blocks and blocks of threads for jacobi kernel
blockdim = JACOBI_BLOCK_DIM;
griddim = (int) ((nn-2)/JACOBI_BLOCK_DIM) + 1;
// define size of shared memory for jacobi_iteration kernel
sh_mem_size = (2*JACOBI_BLOCK_DIM+2)*sizeof(double);
// allocate host and device memory for vector of errors
cuError = hipMalloc((void **) &d_error, griddim.x*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
h_error = (double*) malloc(griddim.x*sizeof(double));
int iter_count = 0;
// execute jacobi iterations until solved
// no need to check error until minimum number of interations is reached
while(min_iteration>0) {
// execute all but one iteration without checking errors
hipGetLastError();
jacobi_iter_no_error<<<griddim, blockdim, sizeof(double)>>>(nn, ds, epsilon0, d_rho, d_phi);
min_iteration--;
}
while (t_error>=max_error) {
// execute at least one iteration checking errors
hipGetLastError();
jacobi_iteration<<<griddim, blockdim, sh_mem_size>>>(nn, ds, epsilon0, d_rho, d_phi, d_error);
cu_sync_check(__FILE__, __LINE__);
// copy error vector from device to host memory
cuError = hipMemcpy(h_error, d_error, griddim.x*sizeof(double), hipMemcpyDeviceToHost);
cu_check(cuError, __FILE__, __LINE__);
// evaluate max error of the iteration
t_error = 0;
for (int i = 0; i<griddim.x; i++)
{
if (h_error[i] > t_error) t_error = h_error[i];
}
iter_count++;
}
printf("iter_count = %i\n", iter_count);
// free device memory
hipFree(d_error);
free(h_error);
return;
}
/*************************************************************************
*
* Here we find the modification to include the Crank-Nicholson method
* for Poisson's equation solver. These kernels are executed in the same
* order as they are declared.
*
* The Crank-Nocholson algorithm is basicly a exact method that performs
* two sums over the elements of the input array, with coefficients that
* depend on the system of differental equations. As Poisson's equation
* is the same in all the iterations, the method does not change. Moreover,
* as the system has certain periodicities, the coefficients can be
* calculated before programming time and introduced in the sums.
*
* The sums over many elements are performed using the scan algorithm,
* modified with the coefficients for the method. The synchronization
* threads can be performed in the same kernel, but the synchronazation
* between the blocks required ending the kernels and running the next.
*
*************************************************************************/
__global__ void cn_map_rho(double* d_temp1, double* d_rho, double ds, double epsilon0, int max_idx) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
d_temp1[idx] = -((double) idx+1)*ds*ds*d_rho[idx]/epsilon0;
}
}
/**********************************************************/
__global__ void cn_fw_part_scan(double *d_des, double *d_src, int max_idx) {
// We start the algorithm knowing that we will need to use more than one block
double *sh_src= (double *) sh_mem;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
sh_src[threadIdx.x] = d_src[idx];
__syncthreads();
// SCAN OVER SH_src:
// reduction over the elements on the left
for (int stride = 1; stride<blockDim.x; stride = stride*2) {
int k = threadIdx.x - stride;
if (k>=0) {
sh_src[threadIdx.x] += sh_src[k];
}
__syncthreads();
}
d_des[idx] = sh_src[threadIdx.x];
}
return;
}
/**********************************************************/
__global__ void cn_fw_glob_scan(double *d_des, double* d_src, int max_idx, double* d_phi) {
// It is necessary to synchronize all the blocks, which can only be done by
// ending the kernel and starting a new one
double *sh_acum = (double *) sh_mem;
double *sh_phi_0 = (double *) &sh_mem[1];
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx < max_idx) {
// first thread saves the acum
if (threadIdx.x == 0) {
double r_acum = 0.0;
for (int i = blockDim.x-1; i<blockIdx.x*blockDim.x; i+=blockDim.x) {
r_acum += d_src[i];
}
sh_acum[0] = r_acum;
}
// first thread of the other blocks
if ((threadIdx.x == blockDim.x-1)||(idx==max_idx-1)) {
sh_phi_0[0] = d_phi[0];
}
}
__syncthreads();
if (idx < max_idx) {
//d_des[idx] = sh_acum[0] + d_src[idx]; // this line woould be a simple scan, no coefs
d_des[idx] = (sh_acum[0] + d_src[idx]- sh_phi_0[0])/((double) (idx+1)*(idx+2));
}
}
/**********************************************************/
__global__ void cn_bw_part_scan(double *d_des, double *d_src, int max_idx) {
// block kernel, d_des can be equal to d_src
double *sh_src= (double *) sh_mem;
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
sh_src[threadIdx.x] = d_src[idx];
__syncthreads();
// SCAN over SH_src inverted:
// reduction over the elements on the left
for (int stride = 1; stride<blockDim.x; stride = stride*2) {
int k = threadIdx.x + stride;
// it is necessary to check if it is the last block
if (blockIdx.x ==gridDim.x - 1) {
if (k<max_idx%blockDim.x) {
sh_src[threadIdx.x] += sh_src[k];
}
} else {
if (k<blockDim.x) {
sh_src[threadIdx.x] += sh_src[k];
}
}
__syncthreads();
}
d_des[idx] = sh_src[threadIdx.x];
}
}
/**********************************************************/
__global__ void cn_bw_glob_scan(double *d_des, double* d_src, int max_idx, double* d_phi_L) {
// It is necessary to synchronize all the blocks, which can only be done by
// ending the kernel and starting a new one
// global kernel, d_des cannot be the same as d_src
double *sh_acum= (double *) sh_mem;
double *sh_phi_L = (double *) &sh_mem[1];
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if (idx<max_idx) {
if (threadIdx.x == 0) {
double r_acum = 0.0;
for (int i = (blockIdx.x+1)*blockDim.x; i<max_idx; i+=blockDim.x) {
r_acum += d_src[i];
}
sh_acum[0] = r_acum;
}
if ((threadIdx.x == blockDim.x-1)||(idx==max_idx-1)) {
sh_phi_L[0] = d_phi_L[0]/((double) max_idx+1); // max_idx+1 == nn-1
}
__syncthreads();
d_des[idx] = (sh_phi_L[0]-sh_acum[0]-d_src[idx])*((double) idx+1);
}
}
/**********************************************************/
void poisson_solver_cn(double max_error, double *d_rho, double *d_phi) {
// It is necessary to synchronize all the blocks, which can only be done by
// ending the kernel and starting a new one
// max_error is conserved for compatibility with poisson_solver_jacobi
// In PIC code, just change the library, it has the same function poisson_solver
// global variables in host
int nn = init_nn();
double epsilon0 = init_epsilon0();
double ds = init_ds();
hipError_t cuError;
// Allocate device memory
double* d_temp1;
cuError = hipMalloc ((void **) &d_temp1, (nn-2)*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
double* d_temp2;
cuError = hipMalloc ((void **) &d_temp2, (nn-2)*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
// Size of grids for each part of the algorithm
int map_blocks_per_grid = (nn+CN_MAP_BLOCK_DIM-1)/CN_MAP_BLOCK_DIM;
int scan_blocks_per_grid = (nn-2+CN_SCAN_BLOCK_DIM-1)/CN_SCAN_BLOCK_DIM;
// Shared mem for scan part
size_t sh_mem_size;
sh_mem_size = (CN_SCAN_BLOCK_DIM)*sizeof(double);
// Obtain rho_1, stored in d_temp1
cn_map_rho<<<map_blocks_per_grid, CN_MAP_BLOCK_DIM>>>(d_temp1, &d_rho[1], ds, epsilon0, nn-2);
// Obtain D_2, stored in d_temp1. Modified to substract d_phi[0], even if it is not part of scan
cn_fw_part_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, sh_mem_size>>>(d_temp2, d_temp1, nn-2);
cn_fw_glob_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, 2*sizeof(double)>>>(d_temp1, d_temp2, nn-2, d_phi);
// Obtain d_phi. Modified to add d_phi[nn-1]
cn_bw_part_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, sh_mem_size>>>(d_temp2, d_temp1, nn-2);
cn_bw_glob_scan<<<scan_blocks_per_grid, CN_SCAN_BLOCK_DIM, 2*sizeof(double)>>>(&d_phi[1], d_temp2, nn-2, &d_phi[nn-1]);
hipFree(d_temp1);
hipFree(d_temp2);
}
/******************************************************************************
* main
******************************************************************************/
int main(int argc, char** argv) {
printf("Initiating Poisson Solver Capsule to compare different algorithms\n\n");
hipDeviceReset();
int nn = init_nn();
int nc = nn-1;
double max_error = 1.0e-4;
hipError_t cuError;
// Initialize the memories
double* h_rho = (double*) malloc(nn*sizeof(double));
double* h_phi = (double*) malloc(nn*sizeof(double));
double* d_rho;
double* d_phi;
cuError = hipMalloc ((void **) &d_rho, nn*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
cuError = hipMalloc ((void **) &d_phi, nn*sizeof(double));
cu_check(cuError, __FILE__, __LINE__);
double phi_0 = 0.5;
double phi_L = 2.0;
double x_0 = 0.0;
double ds = init_ds();
double x_L = nn*ds;
// Initialize h_rho anyway, no influence in the calculation time (Care with overflows)
for (int i=0; i<nn; i++) {
h_rho[i] = 1.0;
h_phi[i] = phi_0 + ((double) i)*(phi_L - phi_0)/((double) nc);
}
// Copy to device
cuError = hipMemcpy(d_rho, h_rho, nn*sizeof(double), hipMemcpyHostToDevice);
cu_check(cuError, __FILE__, __LINE__);
cuError = hipMemcpy(d_phi, h_phi, nn*sizeof(double), hipMemcpyHostToDevice);
cu_check(cuError, __FILE__, __LINE__);
// RUNS PoissonSolver once, uncomment to run
poisson_solver_cn(max_error, d_rho, d_phi);
// RUNS PoissonSolver many times, uncomment to run
// for (int i=0;i<100000;i++) poisson_solver_cn(max_error, d_rho, d_phi);
// RUNS PoissonSolver many times, uncomment to run
// for (int i=0;i<1000;i++) poisson_solver_jacobi(max_error, d_rho, d_phi);
// FROM WHERE we obtain the following measures
// 1e6 repetitions of poisson_solver_cn takes 108 seconds
// => each repetition takes 0.1ms (as expected)
// 1000 repetitions of jacobi with error calculation every iteration (original)
// take 37 seconds
// => each repetition takes 37 ms
// 10000 iteraciones de jacobi poisson_solver, modified for no error checking
// take 42 segundos
// => cada una 4.2 ms, great improvement!!
// CONCLUSION: Jacobi method without error checking is 9 times faster
// Crank-Nicholson method is 370 times faster (programming time is worth the effort)
// Bring back d_phi to host
cuError = hipMemcpy(h_phi, d_phi, nn*sizeof(double), hipMemcpyDeviceToHost);
cu_check(cuError, __FILE__, __LINE__);
cuError = hipMemcpy(h_rho, d_rho, nn*sizeof(double), hipMemcpyDeviceToHost);
cu_check(cuError, __FILE__, __LINE__);
for (int i=0; i<nn; i++) {
printf("%g\t%g\t%g\n",x_0 + ((double) i)*(x_L-x_0)/((double) nc), h_rho[i], h_phi[i]);
}
// Free memory
free(h_rho);
free(h_phi);
hipFree (d_rho);
hipFree (d_phi);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
__global__
void Dense(int n, int m, float *W, float *b, float *x, float* y)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int jn = j*n;
float r = b[j];
for (int i = 0; i < n; i++)
r = r+W[jn+i]*x[i];
y[j] = r;
}
int main(void)
{
int N = 1024;
int M = 2048;
int blockSize = 128;
int numBlocks = 2048/blockSize;
float *x, *y, *b, *W;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, M*sizeof(float));
cudaMallocManaged(&b, M*sizeof(float));
cudaMallocManaged(&W, M*N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f*i;
}
for (int j = 0; j < M; j++) {
b[j] = -0.5f*N*(N-1)+3.5f;
}
for (int j=0;j<M;j++)
for(int i=0;i<N;i++) {
W[j*N+i]=1;
}
for(int t=0;t<1000;t++)
Dense<<<numBlocks, blockSize>>>(N, M, W, b, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int j = 0; j < M; j++)
maxError = fmax(maxError, fabs(y[j]-3.5f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(W);
cudaFree(b);
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z5DenseiiPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0030*/ MOV R9, c[0x0][0x160] ; /* 0x0000580000097a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0202 */
/*0080*/ IMAD.WIDE R2, R7, R0, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fe200078e0200 */
/*0090*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011407 */
/*00a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000166000c1e1900 */
/*00b0*/ @!P0 BRA 0xa10 ; /* 0x0000095000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R9.reuse, -0x1, RZ ; /* 0xffffffff09027810 */
/* 0x041fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x900 ; /* 0x000007f000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R10, -R9, c[0x0][0x160], RZ ; /* 0x00005800090a7a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD R3, R7, c[0x0][0x160], RZ ; /* 0x0000580007037a24 */
/* 0x000fe200078e02ff */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0200 */
/*0170*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fd60000000f00 */
/*0180*/ @!P0 BRA 0x790 ; /* 0x0000060000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x550 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080404117981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0404157981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R23, [R4.64+0x10] ; /* 0x0000100404177981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R20, [R2.64+0x14] ; /* 0x0000140402147981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f22000c1e1900 */
/*02b0*/ FFMA R15, R14, R15, R13 ; /* 0x0000000f0e0f7223 */
/* 0x024fc6000000000d */
/*02c0*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ FFMA R25, R16, R25, R15 ; /* 0x0000001910197223 */
/* 0x008fc6000000000f */
/*02f0*/ LDG.E R15, [R4.64+0x20] ; /* 0x00002004040f7981 */
/* 0x000ee8000c1e1900 */
/*0300*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000ee2000c1e1900 */
/*0310*/ FFMA R25, R17, R18, R25 ; /* 0x0000001211197223 */
/* 0x010fc60000000019 */
/*0320*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240402127981 */
/* 0x000f22000c1e1900 */
/*0340*/ FFMA R25, R21, R22, R25 ; /* 0x0000001615197223 */
/* 0x000fc60000000019 */
/*0350*/ LDG.E R21, [R4.64+0x28] ; /* 0x0000280404157981 */
/* 0x000128000c1e1900 */
/*0360*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000f22000c1e1900 */
/*0370*/ FFMA R25, R23, R24, R25 ; /* 0x0000001817197223 */
/* 0x000fc60000000019 */
/*0380*/ LDG.E R23, [R4.64+0x2c] ; /* 0x00002c0404177981 */
/* 0x000128000c1e1900 */
/*0390*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000322000c1e1900 */
/*03a0*/ FFMA R25, R19, R20, R25 ; /* 0x0000001413197223 */
/* 0x000fc60000000019 */
/*03b0*/ LDG.E R19, [R4.64+0x30] ; /* 0x0000300404137981 */
/* 0x000128000c1e1900 */
/*03c0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x000322000c1e1900 */
/*03d0*/ FFMA R25, R11, R12, R25 ; /* 0x0000000c0b197223 */
/* 0x000fc60000000019 */
/*03e0*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003404040b7981 */
/* 0x000128000c1e1900 */
/*03f0*/ LDG.E R12, [R2.64+0x34] ; /* 0x00003404020c7981 */
/* 0x000322000c1e1900 */
/*0400*/ FFMA R25, R13, R14, R25 ; /* 0x0000000e0d197223 */
/* 0x004fc60000000019 */
/*0410*/ LDG.E R13, [R4.64+0x38] ; /* 0x00003804040d7981 */
/* 0x0000a8000c1e1900 */
/*0420*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0002a2000c1e1900 */
/*0430*/ FFMA R25, R15, R16, R25 ; /* 0x000000100f197223 */
/* 0x008fc60000000019 */
/*0440*/ LDG.E R15, [R4.64+0x3c] ; /* 0x00003c04040f7981 */
/* 0x0000e8000c1e1900 */
/*0450*/ LDG.E R16, [R2.64+0x3c] ; /* 0x00003c0402107981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0470*/ FFMA R17, R17, R18, R25 ; /* 0x0000001211117223 */
/* 0x010fe20000000019 */
/*0480*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*04a0*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fe20007f7e0ff */
/*04b0*/ FFMA R17, R21, R22, R17 ; /* 0x0000001615117223 */
/* 0x000fe20000000011 */
/*04c0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fc60007f5e0ff */
/*04d0*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*04e0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*04f0*/ FFMA R17, R23, R24, R17 ; /* 0x0000001817117223 */
/* 0x000fc80000000011 */
/*0500*/ FFMA R17, R19, R20, R17 ; /* 0x0000001413117223 */
/* 0x000fc80000000011 */
/*0510*/ FFMA R11, R11, R12, R17 ; /* 0x0000000c0b0b7223 */
/* 0x000fc80000000011 */
/*0520*/ FFMA R13, R13, R14, R11 ; /* 0x0000000e0d0d7223 */
/* 0x004fc8000000000b */
/*0530*/ FFMA R13, R15, R16, R13 ; /* 0x000000100f0d7223 */
/* 0x008fe2000000000d */
/*0540*/ @P1 BRA 0x1d0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0550*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*0560*/ @!P1 BRA 0x770 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R22, [R4.64+0x4] ; /* 0x0000040404167981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000128000c1e1900 */
/*05c0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000f28000c1e1900 */
/*05d0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000f28000c1e1900 */
/*0610*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f22000c1e1900 */
/*0650*/ FFMA R21, R20, R21, R13 ; /* 0x0000001514157223 */
/* 0x024fc6000000000d */
/*0660*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x0000a8000c1e1900 */
/*0670*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x0002a2000c1e1900 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0690*/ FFMA R21, R22, R23, R21 ; /* 0x0000001716157223 */
/* 0x008fe20000000015 */
/*06a0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fe20007f5e0ff */
/*06d0*/ FFMA R21, R24, R25, R21 ; /* 0x0000001918157223 */
/* 0x010fc60000000015 */
/*06e0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*06f0*/ FFMA R18, R18, R19, R21 ; /* 0x0000001312127223 */
/* 0x000fc80000000015 */
/*0700*/ FFMA R16, R16, R17, R18 ; /* 0x0000001110107223 */
/* 0x000fc80000000012 */
/*0710*/ FFMA R14, R14, R15, R16 ; /* 0x0000000f0e0e7223 */
/* 0x000fc80000000010 */
/*0720*/ FFMA R11, R11, R12, R14 ; /* 0x0000000c0b0b7223 */
/* 0x000fe2000000000e */
/*0730*/ IADD3 R12, P1, R2, 0x20, RZ ; /* 0x00000020020c7810 */
/* 0x000fca0007f3e0ff */
/*0740*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x002fe400008e0603 */
/*0750*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0760*/ FFMA R13, R13, R20, R11 ; /* 0x000000140d0d7223 */
/* 0x004fe4000000000b */
/*0770*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0780*/ @!P0 BRA 0x900 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*07b0*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x0000e8000c1e1900 */
/*07c0*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000128000c1e1900 */
/*07e0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000322000c1e1900 */
/*0810*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*0820*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0830*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0840*/ FFMA R11, R12, R11, R13 ; /* 0x0000000b0c0b7223 */
/* 0x024fe2000000000d */
/*0850*/ IADD3 R12, P2, R4, 0x10, RZ ; /* 0x00000010040c7810 */
/* 0x000fc80007f5e0ff */
/*0860*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x001fe400017fe4ff */
/*0870*/ MOV R4, R12 ; /* 0x0000000c00047202 */
/* 0x000fe20000000f00 */
/*0880*/ FFMA R11, R14, R15, R11 ; /* 0x0000000f0e0b7223 */
/* 0x008fe2000000000b */
/*0890*/ IADD3 R14, P1, R2, 0x10, RZ ; /* 0x00000010020e7810 */
/* 0x000fca0007f3e0ff */
/*08a0*/ IMAD.X R15, RZ, RZ, R3, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e0603 */
/*08b0*/ FFMA R11, R16, R17, R11 ; /* 0x00000011100b7223 */
/* 0x010fe4000000000b */
/*08c0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000e */
/*08d0*/ MOV R3, R15 ; /* 0x0000000f00037202 */
/* 0x000fe20000000f00 */
/*08e0*/ FFMA R13, R18, R19, R11 ; /* 0x00000013120d7223 */
/* 0x000fe2000000000b */
/*08f0*/ @P0 BRA 0x790 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0900*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0910*/ @!P0 BRA 0xa10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0920*/ IMAD R5, R7, c[0x0][0x160], R6 ; /* 0x0000580007057a24 */
/* 0x000fe400078e0206 */
/*0930*/ IMAD.WIDE R2, R6, R0, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fc800078e0200 */
/*0940*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*0950*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fca0000000f00 */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0970*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x0000aa000c1e1900 */
/*0980*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0990*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*09b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc40003f05270 */
/*09c0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f3e0ff */
/*09d0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe400017fe4ff */
/*09e0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ FFMA R13, R0, R4, R13 ; /* 0x00000004000d7223 */
/* 0x024fcc000000000d */
/*0a00*/ @P0 BRA 0x960 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0a10*/ LEA R2, P0, R7, c[0x0][0x180], 0x2 ; /* 0x0000600007027a11 */
/* 0x001fc800078010ff */
/*0a20*/ LEA.HI.X R3, R7, c[0x0][0x184], R8, 0x2, P0 ; /* 0x0000610007037a11 */
/* 0x000fca00000f1408 */
/*0a30*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x020fe2000c101904 */
/*0a40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
__global__
void Dense(int n, int m, float *W, float *b, float *x, float* y)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int jn = j*n;
float r = b[j];
for (int i = 0; i < n; i++)
r = r+W[jn+i]*x[i];
y[j] = r;
}
int main(void)
{
int N = 1024;
int M = 2048;
int blockSize = 128;
int numBlocks = 2048/blockSize;
float *x, *y, *b, *W;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, M*sizeof(float));
cudaMallocManaged(&b, M*sizeof(float));
cudaMallocManaged(&W, M*N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f*i;
}
for (int j = 0; j < M; j++) {
b[j] = -0.5f*N*(N-1)+3.5f;
}
for (int j=0;j<M;j++)
for(int i=0;i<N;i++) {
W[j*N+i]=1;
}
for(int t=0;t<1000;t++)
Dense<<<numBlocks, blockSize>>>(N, M, W, b, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int j = 0; j < M; j++)
maxError = fmax(maxError, fabs(y[j]-3.5f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(W);
cudaFree(b);
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_00014d31_00000000-6_naive_mul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
.type _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_, @function
_Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5DenseiiPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_, .-_Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
.globl _Z5DenseiiPfS_S_S_
.type _Z5DenseiiPfS_S_S_, @function
_Z5DenseiiPfS_S_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5DenseiiPfS_S_S_, .-_Z5DenseiiPfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8192, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $8192, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $8388608, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
movl $0, %eax
movss .LC1(%rip), %xmm0
.L13:
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $8192, %rax
jne .L13
movl $4096, %ecx
movss .LC2(%rip), %xmm0
.L14:
leaq -4096(%rcx), %rax
.L15:
movq 40(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L15
addq $4096, %rcx
cmpq $8392704, %rcx
jne .L14
movl $1000, %ebx
jmp .L16
.L17:
subl $1, %ebx
je .L27
.L16:
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 24(%rsp), %r9
movq 16(%rsp), %r8
movq 32(%rsp), %rcx
movq 40(%rsp), %rdx
movl $2048, %esi
movl $1024, %edi
call _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
jmp .L17
.L27:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 8192(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L18:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L18
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z5DenseiiPfS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5DenseiiPfS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long -922763376
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1080033280
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
__global__
void Dense(int n, int m, float *W, float *b, float *x, float* y)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int jn = j*n;
float r = b[j];
for (int i = 0; i < n; i++)
r = r+W[jn+i]*x[i];
y[j] = r;
}
int main(void)
{
int N = 1024;
int M = 2048;
int blockSize = 128;
int numBlocks = 2048/blockSize;
float *x, *y, *b, *W;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, M*sizeof(float));
cudaMallocManaged(&b, M*sizeof(float));
cudaMallocManaged(&W, M*N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f*i;
}
for (int j = 0; j < M; j++) {
b[j] = -0.5f*N*(N-1)+3.5f;
}
for (int j=0;j<M;j++)
for(int i=0;i<N;i++) {
W[j*N+i]=1;
}
for(int t=0;t<1000;t++)
Dense<<<numBlocks, blockSize>>>(N, M, W, b, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int j = 0; j < M; j++)
maxError = fmax(maxError, fabs(y[j]-3.5f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(W);
cudaFree(b);
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
__global__
void Dense(int n, int m, float *W, float *b, float *x, float* y)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int jn = j*n;
float r = b[j];
for (int i = 0; i < n; i++)
r = r+W[jn+i]*x[i];
y[j] = r;
}
int main(void)
{
int N = 1024;
int M = 2048;
int blockSize = 128;
int numBlocks = 2048/blockSize;
float *x, *y, *b, *W;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, M*sizeof(float));
hipMallocManaged(&b, M*sizeof(float));
hipMallocManaged(&W, M*N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f*i;
}
for (int j = 0; j < M; j++) {
b[j] = -0.5f*N*(N-1)+3.5f;
}
for (int j=0;j<M;j++)
for(int i=0;i<N;i++) {
W[j*N+i]=1;
}
for(int t=0;t<1000;t++)
Dense<<<numBlocks, blockSize>>>(N, M, W, b, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int j = 0; j < M; j++)
maxError = fmax(maxError, fabs(y[j]-3.5f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(W);
hipFree(b);
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
__global__
void Dense(int n, int m, float *W, float *b, float *x, float* y)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int jn = j*n;
float r = b[j];
for (int i = 0; i < n; i++)
r = r+W[jn+i]*x[i];
y[j] = r;
}
int main(void)
{
int N = 1024;
int M = 2048;
int blockSize = 128;
int numBlocks = 2048/blockSize;
float *x, *y, *b, *W;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, M*sizeof(float));
hipMallocManaged(&b, M*sizeof(float));
hipMallocManaged(&W, M*N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f*i;
}
for (int j = 0; j < M; j++) {
b[j] = -0.5f*N*(N-1)+3.5f;
}
for (int j=0;j<M;j++)
for(int i=0;i<N;i++) {
W[j*N+i]=1;
}
for(int t=0;t<1000;t++)
Dense<<<numBlocks, blockSize>>>(N, M, W, b, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int j = 0; j < M; j++)
maxError = fmax(maxError, fabs(y[j]-3.5f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(W);
hipFree(b);
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5DenseiiPfS_S_S_
.globl _Z5DenseiiPfS_S_S_
.p2align 8
.type _Z5DenseiiPfS_S_S_,@function
_Z5DenseiiPfS_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
global_load_b32 v0, v[3:4], off
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_mul_lo_u32 v3, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.LBB0_2:
global_load_b32 v5, v[3:4], off
s_load_b32 s5, s[2:3], 0x0
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_i32 s4, s4, -1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v5
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5DenseiiPfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5DenseiiPfS_S_S_, .Lfunc_end0-_Z5DenseiiPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5DenseiiPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5DenseiiPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
__global__
void Dense(int n, int m, float *W, float *b, float *x, float* y)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int jn = j*n;
float r = b[j];
for (int i = 0; i < n; i++)
r = r+W[jn+i]*x[i];
y[j] = r;
}
int main(void)
{
int N = 1024;
int M = 2048;
int blockSize = 128;
int numBlocks = 2048/blockSize;
float *x, *y, *b, *W;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, M*sizeof(float));
hipMallocManaged(&b, M*sizeof(float));
hipMallocManaged(&W, M*N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f*i;
}
for (int j = 0; j < M; j++) {
b[j] = -0.5f*N*(N-1)+3.5f;
}
for (int j=0;j<M;j++)
for(int i=0;i<N;i++) {
W[j*N+i]=1;
}
for(int t=0;t<1000;t++)
Dense<<<numBlocks, blockSize>>>(N, M, W, b, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int j = 0; j < M; j++)
maxError = fmax(maxError, fabs(y[j]-3.5f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(W);
hipFree(b);
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "naive_mul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__DenseiiPfS_S_S_ # -- Begin function _Z20__device_stub__DenseiiPfS_S_S_
.p2align 4, 0x90
.type _Z20__device_stub__DenseiiPfS_S_S_,@function
_Z20__device_stub__DenseiiPfS_S_S_: # @_Z20__device_stub__DenseiiPfS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5DenseiiPfS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z20__device_stub__DenseiiPfS_S_S_, .Lfunc_end0-_Z20__device_stub__DenseiiPfS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0600000 # float -3.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 32(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rcx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2: # %.preheader51
movq 16(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl $-922763376, (%rax,%rcx,4) # imm = 0xC8FFBF90
incq %rcx
cmpq $2048, %rcx # imm = 0x800
jne .LBB1_3
# %bb.4: # %.preheader50
movq 8(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rax,%rdx,4) # imm = 0x3F800000
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $2048, %rcx # imm = 0x800
jne .LBB1_5
# %bb.8: # %.preheader
movl $1000, %r12d # imm = 0x3E8
movabsq $4294967312, %rbx # imm = 0x100000010
leaq 112(%rbx), %r14
leaq 56(%rsp), %r13
leaq 48(%rsp), %rbp
leaq 128(%rsp), %r15
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
decl %r12d
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $1024, 44(%rsp) # imm = 0x400
movl $2048, 40(%rsp) # imm = 0x800
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z5DenseiiPfS_S_S_, %edi
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 24(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $2048, %rax # imm = 0x800
jne .LBB1_13
# %bb.14:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 176(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 176(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5DenseiiPfS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5DenseiiPfS_S_S_,@object # @_Z5DenseiiPfS_S_S_
.section .rodata,"a",@progbits
.globl _Z5DenseiiPfS_S_S_
.p2align 3, 0x0
_Z5DenseiiPfS_S_S_:
.quad _Z20__device_stub__DenseiiPfS_S_S_
.size _Z5DenseiiPfS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5DenseiiPfS_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__DenseiiPfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5DenseiiPfS_S_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5DenseiiPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0030*/ MOV R9, c[0x0][0x160] ; /* 0x0000580000097a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0202 */
/*0080*/ IMAD.WIDE R2, R7, R0, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fe200078e0200 */
/*0090*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fc80000011407 */
/*00a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000166000c1e1900 */
/*00b0*/ @!P0 BRA 0xa10 ; /* 0x0000095000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R9.reuse, -0x1, RZ ; /* 0xffffffff09027810 */
/* 0x041fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x900 ; /* 0x000007f000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R10, -R9, c[0x0][0x160], RZ ; /* 0x00005800090a7a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD R3, R7, c[0x0][0x160], RZ ; /* 0x0000580007037a24 */
/* 0x000fe200078e02ff */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0200 */
/*0170*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fd60000000f00 */
/*0180*/ @!P0 BRA 0x790 ; /* 0x0000060000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x550 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080404117981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0404157981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R23, [R4.64+0x10] ; /* 0x0000100404177981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R20, [R2.64+0x14] ; /* 0x0000140402147981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f22000c1e1900 */
/*02b0*/ FFMA R15, R14, R15, R13 ; /* 0x0000000f0e0f7223 */
/* 0x024fc6000000000d */
/*02c0*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ FFMA R25, R16, R25, R15 ; /* 0x0000001910197223 */
/* 0x008fc6000000000f */
/*02f0*/ LDG.E R15, [R4.64+0x20] ; /* 0x00002004040f7981 */
/* 0x000ee8000c1e1900 */
/*0300*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000ee2000c1e1900 */
/*0310*/ FFMA R25, R17, R18, R25 ; /* 0x0000001211197223 */
/* 0x010fc60000000019 */
/*0320*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240402127981 */
/* 0x000f22000c1e1900 */
/*0340*/ FFMA R25, R21, R22, R25 ; /* 0x0000001615197223 */
/* 0x000fc60000000019 */
/*0350*/ LDG.E R21, [R4.64+0x28] ; /* 0x0000280404157981 */
/* 0x000128000c1e1900 */
/*0360*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000f22000c1e1900 */
/*0370*/ FFMA R25, R23, R24, R25 ; /* 0x0000001817197223 */
/* 0x000fc60000000019 */
/*0380*/ LDG.E R23, [R4.64+0x2c] ; /* 0x00002c0404177981 */
/* 0x000128000c1e1900 */
/*0390*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000322000c1e1900 */
/*03a0*/ FFMA R25, R19, R20, R25 ; /* 0x0000001413197223 */
/* 0x000fc60000000019 */
/*03b0*/ LDG.E R19, [R4.64+0x30] ; /* 0x0000300404137981 */
/* 0x000128000c1e1900 */
/*03c0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x000322000c1e1900 */
/*03d0*/ FFMA R25, R11, R12, R25 ; /* 0x0000000c0b197223 */
/* 0x000fc60000000019 */
/*03e0*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003404040b7981 */
/* 0x000128000c1e1900 */
/*03f0*/ LDG.E R12, [R2.64+0x34] ; /* 0x00003404020c7981 */
/* 0x000322000c1e1900 */
/*0400*/ FFMA R25, R13, R14, R25 ; /* 0x0000000e0d197223 */
/* 0x004fc60000000019 */
/*0410*/ LDG.E R13, [R4.64+0x38] ; /* 0x00003804040d7981 */
/* 0x0000a8000c1e1900 */
/*0420*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0002a2000c1e1900 */
/*0430*/ FFMA R25, R15, R16, R25 ; /* 0x000000100f197223 */
/* 0x008fc60000000019 */
/*0440*/ LDG.E R15, [R4.64+0x3c] ; /* 0x00003c04040f7981 */
/* 0x0000e8000c1e1900 */
/*0450*/ LDG.E R16, [R2.64+0x3c] ; /* 0x00003c0402107981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0470*/ FFMA R17, R17, R18, R25 ; /* 0x0000001211117223 */
/* 0x010fe20000000019 */
/*0480*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*04a0*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fe20007f7e0ff */
/*04b0*/ FFMA R17, R21, R22, R17 ; /* 0x0000001615117223 */
/* 0x000fe20000000011 */
/*04c0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fc60007f5e0ff */
/*04d0*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*04e0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*04f0*/ FFMA R17, R23, R24, R17 ; /* 0x0000001817117223 */
/* 0x000fc80000000011 */
/*0500*/ FFMA R17, R19, R20, R17 ; /* 0x0000001413117223 */
/* 0x000fc80000000011 */
/*0510*/ FFMA R11, R11, R12, R17 ; /* 0x0000000c0b0b7223 */
/* 0x000fc80000000011 */
/*0520*/ FFMA R13, R13, R14, R11 ; /* 0x0000000e0d0d7223 */
/* 0x004fc8000000000b */
/*0530*/ FFMA R13, R15, R16, R13 ; /* 0x000000100f0d7223 */
/* 0x008fe2000000000d */
/*0540*/ @P1 BRA 0x1d0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0550*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*0560*/ @!P1 BRA 0x770 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R22, [R4.64+0x4] ; /* 0x0000040404167981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000128000c1e1900 */
/*05c0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x000f28000c1e1900 */
/*05d0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000f28000c1e1900 */
/*0610*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f22000c1e1900 */
/*0650*/ FFMA R21, R20, R21, R13 ; /* 0x0000001514157223 */
/* 0x024fc6000000000d */
/*0660*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x0000a8000c1e1900 */
/*0670*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x0002a2000c1e1900 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0690*/ FFMA R21, R22, R23, R21 ; /* 0x0000001716157223 */
/* 0x008fe20000000015 */
/*06a0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fe20007f5e0ff */
/*06d0*/ FFMA R21, R24, R25, R21 ; /* 0x0000001918157223 */
/* 0x010fc60000000015 */
/*06e0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*06f0*/ FFMA R18, R18, R19, R21 ; /* 0x0000001312127223 */
/* 0x000fc80000000015 */
/*0700*/ FFMA R16, R16, R17, R18 ; /* 0x0000001110107223 */
/* 0x000fc80000000012 */
/*0710*/ FFMA R14, R14, R15, R16 ; /* 0x0000000f0e0e7223 */
/* 0x000fc80000000010 */
/*0720*/ FFMA R11, R11, R12, R14 ; /* 0x0000000c0b0b7223 */
/* 0x000fe2000000000e */
/*0730*/ IADD3 R12, P1, R2, 0x20, RZ ; /* 0x00000020020c7810 */
/* 0x000fca0007f3e0ff */
/*0740*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x002fe400008e0603 */
/*0750*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0760*/ FFMA R13, R13, R20, R11 ; /* 0x000000140d0d7223 */
/* 0x004fe4000000000b */
/*0770*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0780*/ @!P0 BRA 0x900 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*07b0*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x0000e8000c1e1900 */
/*07c0*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000128000c1e1900 */
/*07e0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000322000c1e1900 */
/*0810*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*0820*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0830*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0840*/ FFMA R11, R12, R11, R13 ; /* 0x0000000b0c0b7223 */
/* 0x024fe2000000000d */
/*0850*/ IADD3 R12, P2, R4, 0x10, RZ ; /* 0x00000010040c7810 */
/* 0x000fc80007f5e0ff */
/*0860*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x001fe400017fe4ff */
/*0870*/ MOV R4, R12 ; /* 0x0000000c00047202 */
/* 0x000fe20000000f00 */
/*0880*/ FFMA R11, R14, R15, R11 ; /* 0x0000000f0e0b7223 */
/* 0x008fe2000000000b */
/*0890*/ IADD3 R14, P1, R2, 0x10, RZ ; /* 0x00000010020e7810 */
/* 0x000fca0007f3e0ff */
/*08a0*/ IMAD.X R15, RZ, RZ, R3, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e0603 */
/*08b0*/ FFMA R11, R16, R17, R11 ; /* 0x00000011100b7223 */
/* 0x010fe4000000000b */
/*08c0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000e */
/*08d0*/ MOV R3, R15 ; /* 0x0000000f00037202 */
/* 0x000fe20000000f00 */
/*08e0*/ FFMA R13, R18, R19, R11 ; /* 0x00000013120d7223 */
/* 0x000fe2000000000b */
/*08f0*/ @P0 BRA 0x790 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0900*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0910*/ @!P0 BRA 0xa10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0920*/ IMAD R5, R7, c[0x0][0x160], R6 ; /* 0x0000580007057a24 */
/* 0x000fe400078e0206 */
/*0930*/ IMAD.WIDE R2, R6, R0, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fc800078e0200 */
/*0940*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*0950*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fca0000000f00 */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0970*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x0000aa000c1e1900 */
/*0980*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0990*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*09b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc40003f05270 */
/*09c0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f3e0ff */
/*09d0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe400017fe4ff */
/*09e0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ FFMA R13, R0, R4, R13 ; /* 0x00000004000d7223 */
/* 0x024fcc000000000d */
/*0a00*/ @P0 BRA 0x960 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0a10*/ LEA R2, P0, R7, c[0x0][0x180], 0x2 ; /* 0x0000600007027a11 */
/* 0x001fc800078010ff */
/*0a20*/ LEA.HI.X R3, R7, c[0x0][0x184], R8, 0x2, P0 ; /* 0x0000610007037a11 */
/* 0x000fca00000f1408 */
/*0a30*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x020fe2000c101904 */
/*0a40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5DenseiiPfS_S_S_
.globl _Z5DenseiiPfS_S_S_
.p2align 8
.type _Z5DenseiiPfS_S_S_,@function
_Z5DenseiiPfS_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
global_load_b32 v0, v[3:4], off
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_mul_lo_u32 v3, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.LBB0_2:
global_load_b32 v5, v[3:4], off
s_load_b32 s5, s[2:3], 0x0
v_add_co_u32 v3, vcc_lo, v3, 4
s_add_i32 s4, s4, -1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v5
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5DenseiiPfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5DenseiiPfS_S_S_, .Lfunc_end0-_Z5DenseiiPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5DenseiiPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5DenseiiPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014d31_00000000-6_naive_mul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
.type _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_, @function
_Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5DenseiiPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_, .-_Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
.globl _Z5DenseiiPfS_S_S_
.type _Z5DenseiiPfS_S_S_, @function
_Z5DenseiiPfS_S_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5DenseiiPfS_S_S_, .-_Z5DenseiiPfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8192, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $8192, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $8388608, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
movl $0, %eax
movss .LC1(%rip), %xmm0
.L13:
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $8192, %rax
jne .L13
movl $4096, %ecx
movss .LC2(%rip), %xmm0
.L14:
leaq -4096(%rcx), %rax
.L15:
movq 40(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L15
addq $4096, %rcx
cmpq $8392704, %rcx
jne .L14
movl $1000, %ebx
jmp .L16
.L17:
subl $1, %ebx
je .L27
.L16:
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 24(%rsp), %r9
movq 16(%rsp), %r8
movq 32(%rsp), %rcx
movq 40(%rsp), %rdx
movl $2048, %esi
movl $1024, %edi
call _Z32__device_stub__Z5DenseiiPfS_S_S_iiPfS_S_S_
jmp .L17
.L27:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 8192(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L18:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L18
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z5DenseiiPfS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5DenseiiPfS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long -922763376
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1080033280
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naive_mul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__DenseiiPfS_S_S_ # -- Begin function _Z20__device_stub__DenseiiPfS_S_S_
.p2align 4, 0x90
.type _Z20__device_stub__DenseiiPfS_S_S_,@function
_Z20__device_stub__DenseiiPfS_S_S_: # @_Z20__device_stub__DenseiiPfS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5DenseiiPfS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z20__device_stub__DenseiiPfS_S_S_, .Lfunc_end0-_Z20__device_stub__DenseiiPfS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0600000 # float -3.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 32(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rcx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2: # %.preheader51
movq 16(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl $-922763376, (%rax,%rcx,4) # imm = 0xC8FFBF90
incq %rcx
cmpq $2048, %rcx # imm = 0x800
jne .LBB1_3
# %bb.4: # %.preheader50
movq 8(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rax,%rdx,4) # imm = 0x3F800000
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $2048, %rcx # imm = 0x800
jne .LBB1_5
# %bb.8: # %.preheader
movl $1000, %r12d # imm = 0x3E8
movabsq $4294967312, %rbx # imm = 0x100000010
leaq 112(%rbx), %r14
leaq 56(%rsp), %r13
leaq 48(%rsp), %rbp
leaq 128(%rsp), %r15
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
decl %r12d
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $1024, 44(%rsp) # imm = 0x400
movl $2048, 40(%rsp) # imm = 0x800
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z5DenseiiPfS_S_S_, %edi
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 24(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $2048, %rax # imm = 0x800
jne .LBB1_13
# %bb.14:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 176(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 176(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB1_18
.LBB1_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5DenseiiPfS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5DenseiiPfS_S_S_,@object # @_Z5DenseiiPfS_S_S_
.section .rodata,"a",@progbits
.globl _Z5DenseiiPfS_S_S_
.p2align 3, 0x0
_Z5DenseiiPfS_S_S_:
.quad _Z20__device_stub__DenseiiPfS_S_S_
.size _Z5DenseiiPfS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5DenseiiPfS_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__DenseiiPfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5DenseiiPfS_S_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void update_write_permutation(int *write_permutation, int *nnz_num, int total_pad_row_num, int pad_M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= total_pad_row_num) {
return;
}
write_permutation[i] -= (i / pad_M) * pad_M;
} | code for sm_80
Function : _Z24update_write_permutationPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IABS R8, c[0x0][0x174] ; /* 0x00005d0000087a13 */
/* 0x000fe40000000000 */
/*00b0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00c0*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*0120*/ IADD3 R9, RZ, -R5, RZ ; /* 0x80000005ff097210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0150*/ MOV R9, R10 ; /* 0x0000000a00097202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.HI.U32 R5, R5, R9, RZ ; /* 0x0000000905057227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0180*/ IMAD R5, R8, R5, R9 ; /* 0x0000000508057224 */
/* 0x000fca00078e0209 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f05270 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*01d0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fca00078e0a08 */
/*01e0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*01f0*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff058a12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R7, R7, R5, -R0 ; /* 0x0000000507077210 */
/* 0x004fca0007ffe800 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update_write_permutation(int *write_permutation, int *nnz_num, int total_pad_row_num, int pad_M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= total_pad_row_num) {
return;
}
write_permutation[i] -= (i / pad_M) * pad_M;
} | .file "tmpxft_00155229_00000000-6_update_write_permutation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii
.type _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii, @function
_Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24update_write_permutationPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii, .-_Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii
.globl _Z24update_write_permutationPiS_ii
.type _Z24update_write_permutationPiS_ii, @function
_Z24update_write_permutationPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24update_write_permutationPiS_ii, .-_Z24update_write_permutationPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24update_write_permutationPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24update_write_permutationPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update_write_permutation(int *write_permutation, int *nnz_num, int total_pad_row_num, int pad_M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= total_pad_row_num) {
return;
}
write_permutation[i] -= (i / pad_M) * pad_M;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_write_permutation(int *write_permutation, int *nnz_num, int total_pad_row_num, int pad_M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= total_pad_row_num) {
return;
}
write_permutation[i] -= (i / pad_M) * pad_M;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_write_permutation(int *write_permutation, int *nnz_num, int total_pad_row_num, int pad_M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= total_pad_row_num) {
return;
}
write_permutation[i] -= (i / pad_M) * pad_M;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24update_write_permutationPiS_ii
.globl _Z24update_write_permutationPiS_ii
.p2align 8
.type _Z24update_write_permutationPiS_ii,@function
_Z24update_write_permutationPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
v_ashrrev_i32_e32 v6, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v7, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s1, s0, 31
s_add_i32 s0, s0, s1
global_load_b32 v0, v[2:3], off
s_xor_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s0
s_sub_i32 s1, 0, s0
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v7, v4
v_mul_lo_u32 v4, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v7, v4
v_subrev_nc_u32_e32 v5, s0, v4
v_cmp_le_u32_e32 vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s0, v4
v_cmp_le_u32_e32 vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_xor_b32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v6
v_sub_nc_u32_e32 v1, v4, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24update_write_permutationPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24update_write_permutationPiS_ii, .Lfunc_end0-_Z24update_write_permutationPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24update_write_permutationPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24update_write_permutationPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_write_permutation(int *write_permutation, int *nnz_num, int total_pad_row_num, int pad_M)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= total_pad_row_num) {
return;
}
write_permutation[i] -= (i / pad_M) * pad_M;
} | .text
.file "update_write_permutation.hip"
.globl _Z39__device_stub__update_write_permutationPiS_ii # -- Begin function _Z39__device_stub__update_write_permutationPiS_ii
.p2align 4, 0x90
.type _Z39__device_stub__update_write_permutationPiS_ii,@function
_Z39__device_stub__update_write_permutationPiS_ii: # @_Z39__device_stub__update_write_permutationPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24update_write_permutationPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__update_write_permutationPiS_ii, .Lfunc_end0-_Z39__device_stub__update_write_permutationPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24update_write_permutationPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24update_write_permutationPiS_ii,@object # @_Z24update_write_permutationPiS_ii
.section .rodata,"a",@progbits
.globl _Z24update_write_permutationPiS_ii
.p2align 3, 0x0
_Z24update_write_permutationPiS_ii:
.quad _Z39__device_stub__update_write_permutationPiS_ii
.size _Z24update_write_permutationPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24update_write_permutationPiS_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__update_write_permutationPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24update_write_permutationPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24update_write_permutationPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IABS R8, c[0x0][0x174] ; /* 0x00005d0000087a13 */
/* 0x000fe40000000000 */
/*00b0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00c0*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*0120*/ IADD3 R9, RZ, -R5, RZ ; /* 0x80000005ff097210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0150*/ MOV R9, R10 ; /* 0x0000000a00097202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.HI.U32 R5, R5, R9, RZ ; /* 0x0000000905057227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0180*/ IMAD R5, R8, R5, R9 ; /* 0x0000000508057224 */
/* 0x000fca00078e0209 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f05270 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*01d0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fca00078e0a08 */
/*01e0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*01f0*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff058a12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R7, R7, R5, -R0 ; /* 0x0000000507077210 */
/* 0x004fca0007ffe800 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24update_write_permutationPiS_ii
.globl _Z24update_write_permutationPiS_ii
.p2align 8
.type _Z24update_write_permutationPiS_ii,@function
_Z24update_write_permutationPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
v_ashrrev_i32_e32 v6, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v7, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s1, s0, 31
s_add_i32 s0, s0, s1
global_load_b32 v0, v[2:3], off
s_xor_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s0
s_sub_i32 s1, 0, s0
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v7, v4
v_mul_lo_u32 v4, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v7, v4
v_subrev_nc_u32_e32 v5, s0, v4
v_cmp_le_u32_e32 vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s0, v4
v_cmp_le_u32_e32 vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_xor_b32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v6
v_sub_nc_u32_e32 v1, v4, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24update_write_permutationPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24update_write_permutationPiS_ii, .Lfunc_end0-_Z24update_write_permutationPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24update_write_permutationPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24update_write_permutationPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155229_00000000-6_update_write_permutation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii
.type _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii, @function
_Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24update_write_permutationPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii, .-_Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii
.globl _Z24update_write_permutationPiS_ii
.type _Z24update_write_permutationPiS_ii, @function
_Z24update_write_permutationPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24update_write_permutationPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24update_write_permutationPiS_ii, .-_Z24update_write_permutationPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24update_write_permutationPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24update_write_permutationPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_write_permutation.hip"
.globl _Z39__device_stub__update_write_permutationPiS_ii # -- Begin function _Z39__device_stub__update_write_permutationPiS_ii
.p2align 4, 0x90
.type _Z39__device_stub__update_write_permutationPiS_ii,@function
_Z39__device_stub__update_write_permutationPiS_ii: # @_Z39__device_stub__update_write_permutationPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24update_write_permutationPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__update_write_permutationPiS_ii, .Lfunc_end0-_Z39__device_stub__update_write_permutationPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24update_write_permutationPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24update_write_permutationPiS_ii,@object # @_Z24update_write_permutationPiS_ii
.section .rodata,"a",@progbits
.globl _Z24update_write_permutationPiS_ii
.p2align 3, 0x0
_Z24update_write_permutationPiS_ii:
.quad _Z39__device_stub__update_write_permutationPiS_ii
.size _Z24update_write_permutationPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24update_write_permutationPiS_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__update_write_permutationPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24update_write_permutationPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void big_add(int *a, int *b, int *c, unsigned int N){
// init thread id
int tid;
tid = blockIdx.x * blockDim.x + threadIdx.x;
// stride is for big arrays, i.e. bigger than threads we have
int stride = blockDim.x * gridDim.x;
// do the operations
while(tid < N){
c[tid] = a[tid] + b[tid];
tid += stride;
}
} | code for sm_80
Function : _Z7big_addPiS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void big_add(int *a, int *b, int *c, unsigned int N){
// init thread id
int tid;
tid = blockIdx.x * blockDim.x + threadIdx.x;
// stride is for big arrays, i.e. bigger than threads we have
int stride = blockDim.x * gridDim.x;
// do the operations
while(tid < N){
c[tid] = a[tid] + b[tid];
tid += stride;
}
} | .file "tmpxft_000056ca_00000000-6_big_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j
.type _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j, @function
_Z31__device_stub__Z7big_addPiS_S_jPiS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7big_addPiS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j, .-_Z31__device_stub__Z7big_addPiS_S_jPiS_S_j
.globl _Z7big_addPiS_S_j
.type _Z7big_addPiS_S_j, @function
_Z7big_addPiS_S_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7big_addPiS_S_j, .-_Z7big_addPiS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7big_addPiS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7big_addPiS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void big_add(int *a, int *b, int *c, unsigned int N){
// init thread id
int tid;
tid = blockIdx.x * blockDim.x + threadIdx.x;
// stride is for big arrays, i.e. bigger than threads we have
int stride = blockDim.x * gridDim.x;
// do the operations
while(tid < N){
c[tid] = a[tid] + b[tid];
tid += stride;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void big_add(int *a, int *b, int *c, unsigned int N){
// init thread id
int tid;
tid = blockIdx.x * blockDim.x + threadIdx.x;
// stride is for big arrays, i.e. bigger than threads we have
int stride = blockDim.x * gridDim.x;
// do the operations
while(tid < N){
c[tid] = a[tid] + b[tid];
tid += stride;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void big_add(int *a, int *b, int *c, unsigned int N){
// init thread id
int tid;
tid = blockIdx.x * blockDim.x + threadIdx.x;
// stride is for big arrays, i.e. bigger than threads we have
int stride = blockDim.x * gridDim.x;
// do the operations
while(tid < N){
c[tid] = a[tid] + b[tid];
tid += stride;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7big_addPiS_S_j
.globl _Z7big_addPiS_S_j
.p2align 8
.type _Z7big_addPiS_S_j,@function
_Z7big_addPiS_S_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_le_u32_e64 s0, s12, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7big_addPiS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7big_addPiS_S_j, .Lfunc_end0-_Z7big_addPiS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7big_addPiS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7big_addPiS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void big_add(int *a, int *b, int *c, unsigned int N){
// init thread id
int tid;
tid = blockIdx.x * blockDim.x + threadIdx.x;
// stride is for big arrays, i.e. bigger than threads we have
int stride = blockDim.x * gridDim.x;
// do the operations
while(tid < N){
c[tid] = a[tid] + b[tid];
tid += stride;
}
} | .text
.file "big_add.hip"
.globl _Z22__device_stub__big_addPiS_S_j # -- Begin function _Z22__device_stub__big_addPiS_S_j
.p2align 4, 0x90
.type _Z22__device_stub__big_addPiS_S_j,@function
_Z22__device_stub__big_addPiS_S_j: # @_Z22__device_stub__big_addPiS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7big_addPiS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__big_addPiS_S_j, .Lfunc_end0-_Z22__device_stub__big_addPiS_S_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7big_addPiS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7big_addPiS_S_j,@object # @_Z7big_addPiS_S_j
.section .rodata,"a",@progbits
.globl _Z7big_addPiS_S_j
.p2align 3, 0x0
_Z7big_addPiS_S_j:
.quad _Z22__device_stub__big_addPiS_S_j
.size _Z7big_addPiS_S_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7big_addPiS_S_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__big_addPiS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7big_addPiS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7big_addPiS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7big_addPiS_S_j
.globl _Z7big_addPiS_S_j
.p2align 8
.type _Z7big_addPiS_S_j,@function
_Z7big_addPiS_S_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_le_u32_e64 s0, s12, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7big_addPiS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7big_addPiS_S_j, .Lfunc_end0-_Z7big_addPiS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7big_addPiS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7big_addPiS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000056ca_00000000-6_big_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j
.type _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j, @function
_Z31__device_stub__Z7big_addPiS_S_jPiS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7big_addPiS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j, .-_Z31__device_stub__Z7big_addPiS_S_jPiS_S_j
.globl _Z7big_addPiS_S_j
.type _Z7big_addPiS_S_j, @function
_Z7big_addPiS_S_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7big_addPiS_S_jPiS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7big_addPiS_S_j, .-_Z7big_addPiS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7big_addPiS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7big_addPiS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "big_add.hip"
.globl _Z22__device_stub__big_addPiS_S_j # -- Begin function _Z22__device_stub__big_addPiS_S_j
.p2align 4, 0x90
.type _Z22__device_stub__big_addPiS_S_j,@function
_Z22__device_stub__big_addPiS_S_j: # @_Z22__device_stub__big_addPiS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7big_addPiS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__big_addPiS_S_j, .Lfunc_end0-_Z22__device_stub__big_addPiS_S_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7big_addPiS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7big_addPiS_S_j,@object # @_Z7big_addPiS_S_j
.section .rodata,"a",@progbits
.globl _Z7big_addPiS_S_j
.p2align 3, 0x0
_Z7big_addPiS_S_j:
.quad _Z22__device_stub__big_addPiS_S_j
.size _Z7big_addPiS_S_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7big_addPiS_S_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__big_addPiS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7big_addPiS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <sys/time.h>
#include <stdio.h>
#include<math.h>
//TODO for writing to file, will be deleted
//#include <stdlib.h>
#include <cuda_runtime.h>
#define NUM_STREAMS 16
// time stamp function in ms
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000 + tv.tv_sec*1000 ;
}
void initData(float* data, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
data[i*n*n + j*n + k] = (float) (i+j+k)*(float)1.1;
}
}
}
}
void debugPrint(float* data, int n){
int i,j,k;
for(i = 0; i < 3; i++){
printf("--------layer %d--------\n",i);
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
printf("%lf ",data[i*n*n + j*n + k]);
}
printf("\n");
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_stencil(float *a, float *b, int n){
int i,j,k;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
a[i*n*n + j*n + k] = ((float)0.8)*(b[(i-1)*n*n+j*n+k]+b[(i+1)*n*n+j*n+k]+b[i*n*n+(j-1)*n+k]+b[i*n*n+(j+1)*n+k]+b[i*n*n+j*n+(k-1)]+b[i*n*n+j*n+(k+1)]);
}
}
}
}
// host side validation
bool val(float *a, float *b, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
if(a[i*n*n + j*n + k] != b[i*n*n+j*n+k]){
//printf("%d,%d,%d expect %lf, actual %lf\n",i,j,k,a[i*n*n + j*n + k],b[i*n*n+j*n+k]);
return false;
}
}
}
}
return true;
}
double h_sum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += data[i*n*n + j*n + k]*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
double h_rsum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += roundf(data[i*n*n + j*n + k]*100)/100*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
__device__ void globalToShared(float *sm, float *b, int l, int n, int smx, int smy, int ix, int iy){
sm[smx+smy*(blockDim.x+2)] = b[ix + iy*n + l*n*n];
if(smx==1){
sm[0+smy*(blockDim.x+2)] = b[ix-1 + iy*n + l*n*n];
}
if(smx==blockDim.x || ix==n-2){
sm[smx+1+smy*(blockDim.x+2)] = b[ix+1 + iy*n + l*n*n];
}
if(smy==1){
sm[smx] = b[ix + (iy-1)*n + l*n*n];
}
if(smy==blockDim.y || iy==n-2){
sm[smx+(smy+1)*(blockDim.x+2)] = b[ix + (iy+1)*n + l*n*n];
}
}
__global__ void kernal( float *a, float *b, int n, int height){
extern __shared__ float sm[];
int ix = threadIdx.x + 1;
int iy = threadIdx.y + 1;
int gx = threadIdx.x + 1 + blockIdx.x*blockDim.x;
int gy = threadIdx.y + 1 + blockIdx.y*blockDim.y;
float down,up,self;
float l1,l2,l3,l4;
if(gx<n-1&&gy<n-1){
down = b[gx+gy*n];
globalToShared(sm, b, 1, n, ix, iy, gx, gy);
__syncthreads();
self = sm[ix + iy*(blockDim.x+2)];
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
int layer;
#pragma unroll
for(layer = 2; layer < height; layer++){
globalToShared(sm, b, layer, n, ix, iy, gx, gy);
__syncthreads();
up = sm[ix + iy*(blockDim.x+2)];
a[gx + gy*n + (layer-1)*n*n] = ((float)0.8)*(down+up+l1+l2+l3+l4);
down = self;
self = up;
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
}
}
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 2) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int n = atoi( argv[1] );
//int pad_n = n + 32 - (n-2)%32;
int noElems = n*n*n ;
int bytes = noElems * sizeof(float) ;
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
//float *h_B = (float *) malloc( bytes ) ;
//float *h_dA = (float *) malloc( bytes ) ;
float *h_B;
float *h_dA;
cudaMallocHost((void**)&h_B,bytes);
cudaMallocHost((void**)&h_dA,bytes);
// init matrices with random data
initData(h_B, n);
memset(h_A, 0.0, bytes);
memset(h_dA, 0.0, bytes);
// alloc memory dev-side
float *d_A, *d_B ;
cudaMalloc( (void **) &d_A, bytes ) ;
cudaMalloc( (void **) &d_B, bytes ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
double timeStampA = getTimeStamp() ;
double timeStampD = getTimeStamp() ;
if(n>=250){
//transfer data to dev
//stream creation
int batch_h = (n+NUM_STREAMS-1)/NUM_STREAMS;
int batch_size = n*n*batch_h;
int last_batch = noElems-(NUM_STREAMS-1)*batch_size;
int b_size[NUM_STREAMS];
b_size[0] = batch_h;
b_size[NUM_STREAMS-1] = n-(NUM_STREAMS-1)*batch_h + 2;
for(int k = 1; k < NUM_STREAMS-1; k++){
b_size[k] = batch_h+2;
}
int offset[NUM_STREAMS];
offset[0] = 0;
for(int k = 1; k < NUM_STREAMS; k++){
offset[k] = k*batch_h-2;
}
//for(int k = 0; k < NUM_STREAMS; k++){
// printf("b_size %d is %d\n",k,b_size[k]);
// printf("off %d is %d\n",k,offset[k]);
//}
timeStampA = getTimeStamp() ;
cudaStream_t stream[NUM_STREAMS+1];
for (int i = 1; i < NUM_STREAMS; i++){
cudaStreamCreate(&(stream[i]));
cudaMemcpyAsync(&d_B[(i-1)*batch_size],&h_B[(i-1)*batch_size],batch_size*sizeof(float),cudaMemcpyHostToDevice,stream[i]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[i-1],d_B+n*n*offset[i-1],n,b_size[i-1]);
cudaMemcpyAsync(&h_dA[n*n*(1+offset[i-1])],&d_A[n*n*(1+offset[i-1])],(b_size[i-1]-2)*n*n*sizeof(float),cudaMemcpyDeviceToHost,stream[i]);
}
cudaStreamCreate(&(stream[NUM_STREAMS]));
cudaMemcpyAsync(&d_B[(NUM_STREAMS-1)*batch_size],&h_B[(NUM_STREAMS-1)*batch_size],last_batch*sizeof(float),cudaMemcpyHostToDevice,stream[NUM_STREAMS]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[NUM_STREAMS-1],d_B+n*n*offset[NUM_STREAMS-1],n,b_size[NUM_STREAMS-1]);
cudaMemcpyAsync(&h_dA[n*n*(1+offset[NUM_STREAMS-1])],&d_A[n*n*(1+offset[NUM_STREAMS-1])],(b_size[NUM_STREAMS-1]-2)*n*n*sizeof(float),cudaMemcpyDeviceToHost,stream[NUM_STREAMS]);
//sync all streams and done
for(int i = 1; i < NUM_STREAMS+1; i++){
cudaStreamSynchronize(stream[i]);
}
timeStampD = getTimeStamp() ;
}else{
timeStampA = getTimeStamp() ;
//transfer data to dev
cudaMemcpy( d_B, h_B, bytes, cudaMemcpyHostToDevice ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A,d_B,n,n);
cudaDeviceSynchronize() ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
//copy data back
cudaMemcpy( h_dA, d_A, bytes, cudaMemcpyDeviceToHost ) ;
timeStampD = getTimeStamp() ;
}
h_stencil(h_A,h_B,n);
//h_dA = h_A;
bool match = val(h_A,h_dA,n);
//float h_Result = h_rsum(h_A,n);
float h_dResult = h_sum(h_dA,n);
// print out results
//if(!memcmp(h_A,h_dA,n*n*n*sizeof(float))){
if(match){
//debugPrint(h_A, n);
//debugPrint(h_dC, nx, ny);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d: %lf %.6f\n", n, h_dResult, timeStampD-timeStampA);
//fclose(fptr);
//printf("%lf %lf %d\n", h_dResult, h_Result, (int)round(timeStampD-timeStampA));
printf("%lf %d\n", h_dResult, (int)round(timeStampD-timeStampA));
}else{
//debugPrint(h_A, n);
//debugPrint(h_dA, n);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d Error: function failed.\n", n);
//fclose(fptr);
printf("Error: function failed.\n");
}
// free GPU resources
cudaFree(d_A);
cudaFree(d_B);
cudaDeviceReset();
} | code for sm_80
Function : _Z6kernalPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR8, -0x1, URZ ; /* 0xffffffff08047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R20, SR_TID.Y ; /* 0x0000000000147919 */
/* 0x000e680000002200 */
/*0050*/ S2R R21, SR_TID.X ; /* 0x0000000000157919 */
/* 0x000ea80000002100 */
/*0060*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000ee20000002500 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], RZ ; /* 0x0000010011117a24 */
/* 0x001fe200078e02ff */
/*0080*/ IADD3 R22, R20, 0x1, RZ ; /* 0x0000000114167810 */
/* 0x002fc40007ffe0ff */
/*0090*/ IADD3 R0, R21, 0x1, RZ ; /* 0x0000000115007810 */
/* 0x004fe40007ffe0ff */
/*00a0*/ IADD3 R19, R22, R17, RZ ; /* 0x0000001116137210 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD R2, R18, c[0x0][0x0], R0 ; /* 0x0000000012027a24 */
/* 0x008fe200078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R19, UR4, PT ; /* 0x0000000413007c0c */
/* 0x000fc8000bf06270 */
/*00d0*/ ISETP.GE.OR P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fda0008706670 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ UIADD3 UR4, UR8, -0x2, URZ ; /* 0xfffffffe08047890 */
/* 0x000fe2000fffe03f */
/*0100*/ ISETP.NE.AND P2, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe20003f45270 */
/*0110*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0120*/ ISETP.NE.AND P3, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f65270 */
/*0130*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R16, R18.reuse, c[0x0][0x0], R21 ; /* 0x0000000012107a24 */
/* 0x040fe200078e0215 */
/*0150*/ ISETP.NE.AND P0, PT, R19.reuse, UR4, PT ; /* 0x0000000413007c0c */
/* 0x040fe2000bf05270 */
/*0160*/ IMAD R18, R18, c[0x0][0x0], RZ ; /* 0x0000000012127a24 */
/* 0x000fe200078e02ff */
/*0170*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf25270 */
/*0180*/ UIMAD UR4, UR8, UR6, URZ ; /* 0x00000006080472a4 */
/* 0x000fe2000f8e023f */
/*0190*/ ISETP.EQ.OR P0, PT, R22, c[0x0][0x4], !P0 ; /* 0x0000010016007a0c */
/* 0x000fe20004702670 */
/*01a0*/ IMAD R2, R19.reuse, c[0x0][0x170], R16 ; /* 0x00005c0013027a24 */
/* 0x040fe200078e0210 */
/*01b0*/ ISETP.EQ.OR P1, PT, R0, c[0x0][0x0], !P1 ; /* 0x0000000000007a0c */
/* 0x000fe20004f22670 */
/*01c0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*01d0*/ @!P2 IMAD R3, R19, c[0x0][0x170], R18 ; /* 0x00005c001303aa24 */
/* 0x000fe200078e0212 */
/*01e0*/ MOV R11, UR4 ; /* 0x00000004000b7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ @!P3 IMAD R4, R17, c[0x0][0x170], R16 ; /* 0x00005c001104ba24 */
/* 0x000fe200078e0210 */
/*0200*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x000fe20008000f00 */
/*0210*/ IMAD.WIDE R8, R2, R25, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fe200078e0219 */
/*0220*/ @!P2 IADD3 R6, R3, UR4, RZ ; /* 0x000000040306ac10 */
/* 0x000fc4000fffe0ff */
/*0230*/ @!P3 IADD3 R12, R4, UR4, RZ ; /* 0x00000004040cbc10 */
/* 0x000fe4000fffe0ff */
/*0240*/ @P0 IADD3 R5, R19, 0x1, RZ ; /* 0x0000000113050810 */
/* 0x000fe20007ffe0ff */
/*0250*/ UMOV UR5, 0x2 ; /* 0x0000000200057882 */
/* 0x000fe20000000000 */
/*0260*/ @P1 IADD3 R10, R2, 0x1, R11 ; /* 0x00000001020a1810 */
/* 0x000fe20007ffe00b */
/*0270*/ @!P3 IMAD.WIDE R12, R12, R25.reuse, c[0x0][0x168] ; /* 0x00005a000c0cb625 */
/* 0x080fe200078e0219 */
/*0280*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000800 */
/*0290*/ LDG.E R27, [R8.64+0x4] ; /* 0x0000040a081b7981 */
/* 0x000164000c1e1900 */
/*02a0*/ @P0 IMAD R5, R5, c[0x0][0x170], R16 ; /* 0x00005c0005050a24 */
/* 0x000fe400078e0210 */
/*02b0*/ @P1 IMAD.WIDE R10, R10, R25.reuse, c[0x0][0x168] ; /* 0x00005a000a0a1625 */
/* 0x080fe200078e0219 */
/*02c0*/ @!P3 LDG.E R13, [R12.64+0x4] ; /* 0x0000040a0c0db981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ @P0 IADD3 R14, R5, UR4, RZ ; /* 0x00000004050e0c10 */
/* 0x000fe2000fffe0ff */
/*02e0*/ IMAD.WIDE R4, R7, 0x4, R8 ; /* 0x0000000407047825 */
/* 0x000fe200078e0208 */
/*02f0*/ @P1 LDG.E R29, [R10.64+0x4] ; /* 0x0000040a0a1d1981 */
/* 0x000ee6000c1e1900 */
/*0300*/ @!P2 IMAD.WIDE R6, R6, R25.reuse, c[0x0][0x168] ; /* 0x00005a000606a625 */
/* 0x080fe200078e0219 */
/*0310*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040a04177981 */
/* 0x000326000c1e1900 */
/*0320*/ @P0 IMAD.WIDE R14, R14, R25, c[0x0][0x168] ; /* 0x00005a000e0e0625 */
/* 0x000fe200078e0219 */
/*0330*/ @!P2 LDG.E R24, [R6.64] ; /* 0x0000000a0618a981 */
/* 0x0000aa000c1e1900 */
/*0340*/ @P0 LDG.E R14, [R14.64+0x4] ; /* 0x0000040a0e0e0981 */
/* 0x000ee2000c1e1900 */
/*0350*/ UIADD3 UR5, UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fcc000fffe03f */
/*0360*/ IMAD R3, R22, UR5, RZ ; /* 0x0000000516037c24 */
/* 0x000fe2000f8e02ff */
/*0370*/ IADD3 R22, R20, 0x2, RZ ; /* 0x0000000214167810 */
/* 0x000fc80007ffe0ff */
/*0380*/ IADD3 R4, R3, R21, RZ ; /* 0x0000001503047210 */
/* 0x002fe20007ffe0ff */
/*0390*/ IMAD R5, R22, UR5, R21.reuse ; /* 0x0000000516057c24 */
/* 0x100fe4000f8e0215 */
/*03a0*/ IMAD R6, R20, UR5, R21 ; /* 0x0000000514067c24 */
/* 0x001fe2000f8e0215 */
/*03b0*/ UISETP.GE.AND UP0, UPT, UR7, 0x3, UPT ; /* 0x000000030700788c */
/* 0x000fcc000bf06270 */
/*03c0*/ PLOP3.LUT P4, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f8f008 */
/*03d0*/ STS [R4.X4+0x4], R23 ; /* 0x0000041704007388 */
/* 0x0101e80000004800 */
/*03e0*/ @!P2 STS [R3.X4], R24 ; /* 0x000000180300a388 */
/* 0x0041e80000004800 */
/*03f0*/ @P1 STS [R4.X4+0x8], R29 ; /* 0x0000081d04001388 */
/* 0x0081e80000004800 */
/*0400*/ @!P3 STS [R0.X4], R13 ; /* 0x0000000d0000b388 */
/* 0x0001e80000004800 */
/*0410*/ @P0 STS [R5.X4+0x4], R14 ; /* 0x0000040e05000388 */
/* 0x0001e80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ LDS R21, [R4.X4] ; /* 0x0000000004157984 */
/* 0x0000680000004800 */
/*0440*/ LDS R20, [R4.X4+0x8] ; /* 0x0000080004147984 */
/* 0x0000a80000004800 */
/*0450*/ LDS R26, [R6.X4+0x4] ; /* 0x00000400061a7984 */
/* 0x0000e80000004800 */
/*0460*/ LDS R10, [R5.X4+0x4] ; /* 0x00000400050a7984 */
/* 0x0001280000004800 */
/*0470*/ LDS R11, [R4.X4+0x4] ; /* 0x00000400040b7984 */
/* 0x0000280000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P4 EXIT ; /* 0x000000000000c94d */
/* 0x000fea0003800000 */
/*04a0*/ UISETP.NE.AND UP0, UPT, UR7, 0x3, UPT ; /* 0x000000030700788c */
/* 0x006fe2000bf05270 */
/*04b0*/ IADD3 R9, R19.reuse, 0x1, RZ ; /* 0x0000000113097810 */
/* 0x040fe20007ffe0ff */
/*04c0*/ UIADD3 UR5, UR7, -0x2, URZ ; /* 0xfffffffe07057890 */
/* 0x000fe2000fffe03f */
/*04d0*/ SHF.R.S32.HI R13, RZ, 0x1f, R2 ; /* 0x0000001fff0d7819 */
/* 0x001fe20000011402 */
/*04e0*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe20000000000 */
/*04f0*/ LEA R12, P4, R2.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a00020c7a11 */
/* 0x040fe200078810ff */
/*0500*/ ULOP3.LUT UR8, UR5, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000105087892 */
/* 0x000fe2000f8ec03f */
/*0510*/ PLOP3.LUT P5, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003faf008 */
/*0520*/ IMAD.MOV.U32 R29, RZ, RZ, R10 ; /* 0x000000ffff1d7224 */
/* 0x010fe200078e000a */
/*0530*/ LEA.HI.X R13, R2.reuse, c[0x0][0x16c], R13, 0x2, P4 ; /* 0x00005b00020d7a11 */
/* 0x040fe200020f140d */
/*0540*/ IMAD R7, R19, c[0x0][0x170], R18 ; /* 0x00005c0013077a24 */
/* 0x000fe200078e0212 */
/*0550*/ IADD3 R10, R2, 0x1, RZ ; /* 0x00000001020a7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD R8, R17, c[0x0][0x170], R16 ; /* 0x00005c0011087a24 */
/* 0x000fc400078e0210 */
/*0570*/ IMAD R9, R9, c[0x0][0x170], R16 ; /* 0x00005c0009097a24 */
/* 0x000fcc00078e0210 */
/*0580*/ @!P5 BRA 0xb10 ; /* 0x000005800000d947 */
/* 0x000fea0003800000 */
/*0590*/ UIADD3 UR5, UR5, -UR8, URZ ; /* 0x8000000805057290 */
/* 0x000fe4000fffe03f */
/*05a0*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe40000000000 */
/*05b0*/ UIMAD UR9, UR4, UR6, URZ ; /* 0x00000006040972a4 */
/* 0x000fe2000f8e023f */
/*05c0*/ @!P2 MOV R23, 0x4 ; /* 0x000000040017a802 */
/* 0x000fe40000000f00 */
/*05d0*/ @P1 MOV R14, 0x4 ; /* 0x00000004000e1802 */
/* 0x001fc60000000f00 */
/*05e0*/ MOV R25, UR9 ; /* 0x0000000900197c02 */
/* 0x000fe40008000f00 */
/*05f0*/ @!P2 IADD3 R22, R7, UR9, RZ ; /* 0x000000090716ac10 */
/* 0x000fe4000fffe0ff */
/*0600*/ @P1 IADD3 R15, R10, UR9, RZ ; /* 0x000000090a0f1c10 */
/* 0x000fe2000fffe0ff */
/*0610*/ IMAD.WIDE R24, R25, 0x4, R12 ; /* 0x0000000419187825 */
/* 0x000fe200078e020c */
/*0620*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fe40000000f00 */
/*0630*/ @!P3 IADD3 R16, R8, UR9, RZ ; /* 0x000000090810bc10 */
/* 0x000fe2000fffe0ff */
/*0640*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff120424 */
/* 0x000fe200078e00ff */
/*0650*/ @P0 IADD3 R19, R9, UR9, RZ ; /* 0x0000000909130c10 */
/* 0x000fe2000fffe0ff */
/*0660*/ @!P2 IMAD.WIDE R22, R22, R23, c[0x0][0x168] ; /* 0x00005a001616a625 */
/* 0x000fe200078e0217 */
/*0670*/ LDG.E R25, [R24.64+0x4] ; /* 0x0000040a18197981 */
/* 0x004ea6000c1e1900 */
/*0680*/ @P1 IMAD.WIDE R14, R15, R14, c[0x0][0x168] ; /* 0x00005a000f0e1625 */
/* 0x000fc400078e020e */
/*0690*/ @!P2 LDG.E R22, [R22.64] ; /* 0x0000000a1616a981 */
/* 0x010f24000c1e1900 */
/*06a0*/ @!P3 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a001010b625 */
/* 0x000fe400078e0211 */
/*06b0*/ @P1 LDG.E R15, [R14.64+0x4] ; /* 0x0000040a0e0f1981 */
/* 0x008ee4000c1e1900 */
/*06c0*/ @P0 IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013120625 */
/* 0x000fe400078e0212 */
/*06d0*/ @!P3 LDG.E R17, [R16.64+0x4] ; /* 0x0000040a1011b981 */
/* 0x000ee8000c1e1900 */
/*06e0*/ @P0 LDG.E R18, [R18.64+0x4] ; /* 0x0000040a12120981 */
/* 0x000ee2000c1e1900 */
/*06f0*/ UIADD3 UR7, -UR4, UR9, URZ ; /* 0x0000000904077290 */
/* 0x000fc6000fffe13f */
/*0700*/ STS [R4.X4+0x4], R25 ; /* 0x0000041904007388 */
/* 0x0041e80000004800 */
/*0710*/ @!P2 STS [R3.X4], R22 ; /* 0x000000160300a388 */
/* 0x010fe80000004800 */
/*0720*/ @P1 STS [R4.X4+0x8], R15 ; /* 0x0000080f04001388 */
/* 0x008fe80000004800 */
/*0730*/ @!P3 STS [R0.X4], R17 ; /* 0x000000110000b388 */
/* 0x000fe80000004800 */
/*0740*/ @P0 STS [R5.X4+0x4], R18 ; /* 0x0000041205000388 */
/* 0x000fe80000004800 */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ LDS R24, [R4.X4+0x4] ; /* 0x0000040004187984 */
/* 0x000e620000004800 */
/*0770*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x001fe200000001ff */
/*0780*/ FADD R28, R24, R27 ; /* 0x0000001b181c7221 */
/* 0x022fc40000000000 */
/*0790*/ LDS R27, [R6.X4+0x4] ; /* 0x00000400061b7984 */
/* 0x000fe40000004800 */
/*07a0*/ FADD R21, R28, R21 ; /* 0x000000151c157221 */
/* 0x000fe40000000000 */
/*07b0*/ LDS R28, [R5.X4+0x4] ; /* 0x00000400051c7984 */
/* 0x000fe40000004800 */
/*07c0*/ FADD R21, R21, R20 ; /* 0x0000001415157221 */
/* 0x000fe20000000000 */
/*07d0*/ IADD3 R20, R2, UR7, RZ ; /* 0x0000000702147c10 */
/* 0x000fc6000fffe0ff */
/*07e0*/ FADD R26, R21, R26 ; /* 0x0000001a151a7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R26, R26, R29 ; /* 0x0000001d1a1a7221 */
/* 0x000fe40000000000 */
/*0800*/ IMAD.WIDE R20, R20, R25, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fe200078e0219 */
/*0810*/ LDS R29, [R4.X4] ; /* 0x00000000041d7984 */
/* 0x000fe60000004800 */
/*0820*/ FMUL R23, R26, 0.80000001192092895508 ; /* 0x3f4ccccd1a177820 */
/* 0x000fe40000400000 */
/*0830*/ LDS R26, [R4.X4+0x8] ; /* 0x00000800041a7984 */
/* 0x000fe80000004800 */
/*0840*/ STG.E [R20.64+0x4], R23 ; /* 0x0000041714007986 */
/* 0x0001e2000c10190a */
/*0850*/ ULEA UR7, UR4, UR7, 0x1 ; /* 0x0000000704077291 */
/* 0x000fcc000f8e083f */
/*0860*/ MOV R17, UR7 ; /* 0x0000000700117c02 */
/* 0x000fe40008000f00 */
/*0870*/ @!P2 IADD3 R14, R7, UR7, RZ ; /* 0x00000007070eac10 */
/* 0x000fe4000fffe0ff */
/*0880*/ @P1 IADD3 R18, R10, UR7, RZ ; /* 0x000000070a121c10 */
/* 0x000fe2000fffe0ff */
/*0890*/ IMAD.WIDE R16, R17, 0x4, R12 ; /* 0x0000000411107825 */
/* 0x000fe200078e020c */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08b0*/ @!P3 IADD3 R20, R8, UR7, RZ ; /* 0x000000070814bc10 */
/* 0x001fe4000fffe0ff */
/*08c0*/ @P0 IADD3 R22, R9, UR7, RZ ; /* 0x0000000709160c10 */
/* 0x000fe2000fffe0ff */
/*08d0*/ @!P2 IMAD.WIDE R14, R14, R25, c[0x0][0x168] ; /* 0x00005a000e0ea625 */
/* 0x000fc800078e0219 */
/*08e0*/ @P1 IMAD.WIDE R18, R18, R25, c[0x0][0x168] ; /* 0x00005a0012121625 */
/* 0x000fc800078e0219 */
/*08f0*/ @!P3 IMAD.WIDE R20, R20, R25, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x000fc800078e0219 */
/*0900*/ @P0 IMAD.WIDE R22, R22, R25, c[0x0][0x168] ; /* 0x00005a0016160625 */
/* 0x000fe200078e0219 */
/*0910*/ LDG.E R17, [R16.64+0x4] ; /* 0x0000040a10117981 */
/* 0x000ea8000c1e1900 */
/*0920*/ @!P2 LDG.E R14, [R14.64] ; /* 0x0000000a0e0ea981 */
/* 0x0000e8000c1e1900 */
/*0930*/ @P1 LDG.E R19, [R18.64+0x4] ; /* 0x0000040a12131981 */
/* 0x000f28000c1e1900 */
/*0940*/ @P0 LDG.E R22, [R22.64+0x4] ; /* 0x0000040a16160981 */
/* 0x000f28000c1e1900 */
/*0950*/ @!P3 LDG.E R15, [R20.64+0x4] ; /* 0x0000040a140fb981 */
/* 0x001f22000c1e1900 */
/*0960*/ UIADD3 UR5, UR5, -0x2, URZ ; /* 0xfffffffe05057890 */
/* 0x000fcc000fffe03f */
/*0970*/ ISETP.NE.AND P4, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf85270 */
/*0980*/ UIADD3 UR6, UR6, 0x2, URZ ; /* 0x0000000206067890 */
/* 0x000fe2000fffe03f */
/*0990*/ STS [R4.X4+0x4], R17 ; /* 0x0000041104007388 */
/* 0x004fe80000004800 */
/*09a0*/ @!P2 STS [R3.X4], R14 ; /* 0x0000000e0300a388 */
/* 0x0081e80000004800 */
/*09b0*/ @P1 STS [R4.X4+0x8], R19 ; /* 0x0000081304001388 */
/* 0x010fe80000004800 */
/*09c0*/ @!P3 STS [R0.X4], R15 ; /* 0x0000000f0000b388 */
/* 0x0003e80000004800 */
/*09d0*/ @P0 STS [R5.X4+0x4], R22 ; /* 0x0000041605000388 */
/* 0x000fe80000004800 */
/*09e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09f0*/ LDS R16, [R4.X4+0x4] ; /* 0x0000040004107984 */
/* 0x000ea20000004800 */
/*0a00*/ IADD3 R14, R2, UR9, RZ ; /* 0x00000009020e7c10 */
/* 0x001fc6000fffe0ff */
/*0a10*/ LDS R21, [R4.X4] ; /* 0x0000000004157984 */
/* 0x0000e40000004800 */
/*0a20*/ IMAD.WIDE R14, R14, R25, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x002fe400078e0219 */
/*0a30*/ LDS R20, [R4.X4+0x8] ; /* 0x0000080004147984 */
/* 0x0000640000004800 */
/*0a40*/ FADD R18, R16, R11 ; /* 0x0000000b10127221 */
/* 0x004fc80000000000 */
/*0a50*/ FADD R29, R29, R18 ; /* 0x000000121d1d7221 */
/* 0x000fc80000000000 */
/*0a60*/ FADD R18, R26, R29 ; /* 0x0000001d1a127221 */
/* 0x000fe40000000000 */
/*0a70*/ LDS R26, [R6.X4+0x4] ; /* 0x00000400061a7984 */
/* 0x0000a40000004800 */
/*0a80*/ FADD R27, R27, R18 ; /* 0x000000121b1b7221 */
/* 0x000fe40000000000 */
/*0a90*/ LDS R29, [R5.X4+0x4] ; /* 0x00000400051d7984 */
/* 0x0001240000004800 */
/*0aa0*/ FADD R27, R28, R27 ; /* 0x0000001b1c1b7221 */
/* 0x000fc80000000000 */
/*0ab0*/ FMUL R17, R27, 0.80000001192092895508 ; /* 0x3f4ccccd1b117820 */
/* 0x000fe20000400000 */
/*0ac0*/ MOV R27, R24 ; /* 0x00000018001b7202 */
/* 0x000fc80000000f00 */
/*0ad0*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0001e2000c10190a */
/*0ae0*/ MOV R11, R16 ; /* 0x00000010000b7202 */
/* 0x000fc60000000f00 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ @P4 BRA 0x5b0 ; /* 0xfffffaa000004947 */
/* 0x00afea000383ffff */
/*0b10*/ ISETP.NE.AND P4, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fda000bf85270 */
/*0b20*/ @!P4 EXIT ; /* 0x000000000000c94d */
/* 0x000fea0003800000 */
/*0b30*/ UIMAD UR6, UR4, UR6, URZ ; /* 0x00000006040672a4 */
/* 0x000fcc000f8e023f */
/*0b40*/ MOV R11, UR6 ; /* 0x00000006000b7c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.U32 R15, RZ, RZ, UR6 ; /* 0x00000006ff0f7e24 */
/* 0x001fe2000f8e00ff */
/*0b60*/ MOV R17, UR6 ; /* 0x0000000600117c02 */
/* 0x000fe40008000f00 */
/*0b70*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe20008000f00 */
/*0b80*/ IMAD.WIDE R14, R15, 0x4, R12 ; /* 0x000000040f0e7825 */
/* 0x000fe200078e020c */
/*0b90*/ @!P2 IADD3 R6, R7, UR6, RZ ; /* 0x000000060706ac10 */
/* 0x000fe4000fffe0ff */
/*0ba0*/ @P1 IADD3 R10, R10, 0x1, R11 ; /* 0x000000010a0a1810 */
/* 0x000fe40007ffe00b */
/*0bb0*/ @!P3 IADD3 R8, R8, 0x1, R17 ; /* 0x000000010808b810 */
/* 0x000fe20007ffe011 */
/*0bc0*/ @!P2 IMAD.WIDE R12, R6, R25.reuse, c[0x0][0x168] ; /* 0x00005a00060ca625 */
/* 0x080fe200078e0219 */
/*0bd0*/ @P0 IADD3 R16, R9, 0x1, R16 ; /* 0x0000000109100810 */
/* 0x000fe20007ffe010 */
/*0be0*/ LDG.E R15, [R14.64+0x4] ; /* 0x0000040a0e0f7981 */
/* 0x010f24000c1e1900 */
/*0bf0*/ @P1 IMAD.WIDE R6, R10, R25, c[0x0][0x168] ; /* 0x00005a000a061625 */
/* 0x000fc400078e0219 */
/*0c00*/ @!P2 LDG.E R12, [R12.64] ; /* 0x0000000a0c0ca981 */
/* 0x0080e4000c1e1900 */
/*0c10*/ @!P3 IMAD.WIDE R8, R8, R25.reuse, c[0x0][0x168] ; /* 0x00005a000808b625 */
/* 0x080fe400078e0219 */
/*0c20*/ @P1 LDG.E R7, [R6.64] ; /* 0x0000000a06071981 */
/* 0x004ea4000c1e1900 */
/*0c30*/ @P0 IMAD.WIDE R10, R16, R25, c[0x0][0x168] ; /* 0x00005a00100a0625 */
/* 0x000fe400078e0219 */
/*0c40*/ @!P3 LDG.E R9, [R8.64] ; /* 0x0000000a0809b981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ @P0 LDG.E R10, [R10.64] ; /* 0x0000000a0a0a0981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ MOV R13, UR4 ; /* 0x00000004000d7c02 */
/* 0x001fc80008000f00 */
/*0c70*/ IADD3 R2, R2, UR6, -R13 ; /* 0x0000000602027c10 */
/* 0x000fc8000fffe80d */
/*0c80*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ STS [R4.X4+0x4], R15 ; /* 0x0000040f04007388 */
/* 0x010fe80000004800 */
/*0ca0*/ @!P2 STS [R3.X4], R12 ; /* 0x0000000c0300a388 */
/* 0x0081e80000004800 */
/*0cb0*/ @P1 STS [R4.X4+0x8], R7 ; /* 0x0000080704001388 */
/* 0x004fe80000004800 */
/*0cc0*/ @!P3 STS [R0.X4], R9 ; /* 0x000000090000b388 */
/* 0x000fe80000004800 */
/*0cd0*/ @P0 STS [R5.X4+0x4], R10 ; /* 0x0000040a05000388 */
/* 0x000fe80000004800 */
/*0ce0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0cf0*/ LDS R14, [R4.X4+0x4] ; /* 0x00000400040e7984 */
/* 0x000e620000004800 */
/*0d00*/ IMAD.WIDE R2, R2, R25, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fc800078e0219 */
/*0d10*/ FADD R14, R14, R27 ; /* 0x0000001b0e0e7221 */
/* 0x022fc80000000000 */
/*0d20*/ FADD R21, R14, R21 ; /* 0x000000150e157221 */
/* 0x000fc80000000000 */
/*0d30*/ FADD R21, R21, R20 ; /* 0x0000001415157221 */
/* 0x000fc80000000000 */
/*0d40*/ FADD R26, R21, R26 ; /* 0x0000001a151a7221 */
/* 0x000fc80000000000 */
/*0d50*/ FADD R26, R26, R29 ; /* 0x0000001d1a1a7221 */
/* 0x000fc80000000000 */
/*0d60*/ FMUL R5, R26, 0.80000001192092895508 ; /* 0x3f4ccccd1a057820 */
/* 0x000fca0000400000 */
/*0d70*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c10190a */
/*0d80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0d90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0da0*/ BRA 0xda0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <sys/time.h>
#include <stdio.h>
#include<math.h>
//TODO for writing to file, will be deleted
//#include <stdlib.h>
#include <cuda_runtime.h>
#define NUM_STREAMS 16
// time stamp function in ms
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000 + tv.tv_sec*1000 ;
}
void initData(float* data, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
data[i*n*n + j*n + k] = (float) (i+j+k)*(float)1.1;
}
}
}
}
void debugPrint(float* data, int n){
int i,j,k;
for(i = 0; i < 3; i++){
printf("--------layer %d--------\n",i);
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
printf("%lf ",data[i*n*n + j*n + k]);
}
printf("\n");
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_stencil(float *a, float *b, int n){
int i,j,k;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
a[i*n*n + j*n + k] = ((float)0.8)*(b[(i-1)*n*n+j*n+k]+b[(i+1)*n*n+j*n+k]+b[i*n*n+(j-1)*n+k]+b[i*n*n+(j+1)*n+k]+b[i*n*n+j*n+(k-1)]+b[i*n*n+j*n+(k+1)]);
}
}
}
}
// host side validation
bool val(float *a, float *b, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
if(a[i*n*n + j*n + k] != b[i*n*n+j*n+k]){
//printf("%d,%d,%d expect %lf, actual %lf\n",i,j,k,a[i*n*n + j*n + k],b[i*n*n+j*n+k]);
return false;
}
}
}
}
return true;
}
double h_sum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += data[i*n*n + j*n + k]*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
double h_rsum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += roundf(data[i*n*n + j*n + k]*100)/100*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
__device__ void globalToShared(float *sm, float *b, int l, int n, int smx, int smy, int ix, int iy){
sm[smx+smy*(blockDim.x+2)] = b[ix + iy*n + l*n*n];
if(smx==1){
sm[0+smy*(blockDim.x+2)] = b[ix-1 + iy*n + l*n*n];
}
if(smx==blockDim.x || ix==n-2){
sm[smx+1+smy*(blockDim.x+2)] = b[ix+1 + iy*n + l*n*n];
}
if(smy==1){
sm[smx] = b[ix + (iy-1)*n + l*n*n];
}
if(smy==blockDim.y || iy==n-2){
sm[smx+(smy+1)*(blockDim.x+2)] = b[ix + (iy+1)*n + l*n*n];
}
}
__global__ void kernal( float *a, float *b, int n, int height){
extern __shared__ float sm[];
int ix = threadIdx.x + 1;
int iy = threadIdx.y + 1;
int gx = threadIdx.x + 1 + blockIdx.x*blockDim.x;
int gy = threadIdx.y + 1 + blockIdx.y*blockDim.y;
float down,up,self;
float l1,l2,l3,l4;
if(gx<n-1&&gy<n-1){
down = b[gx+gy*n];
globalToShared(sm, b, 1, n, ix, iy, gx, gy);
__syncthreads();
self = sm[ix + iy*(blockDim.x+2)];
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
int layer;
#pragma unroll
for(layer = 2; layer < height; layer++){
globalToShared(sm, b, layer, n, ix, iy, gx, gy);
__syncthreads();
up = sm[ix + iy*(blockDim.x+2)];
a[gx + gy*n + (layer-1)*n*n] = ((float)0.8)*(down+up+l1+l2+l3+l4);
down = self;
self = up;
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
}
}
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 2) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int n = atoi( argv[1] );
//int pad_n = n + 32 - (n-2)%32;
int noElems = n*n*n ;
int bytes = noElems * sizeof(float) ;
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
//float *h_B = (float *) malloc( bytes ) ;
//float *h_dA = (float *) malloc( bytes ) ;
float *h_B;
float *h_dA;
cudaMallocHost((void**)&h_B,bytes);
cudaMallocHost((void**)&h_dA,bytes);
// init matrices with random data
initData(h_B, n);
memset(h_A, 0.0, bytes);
memset(h_dA, 0.0, bytes);
// alloc memory dev-side
float *d_A, *d_B ;
cudaMalloc( (void **) &d_A, bytes ) ;
cudaMalloc( (void **) &d_B, bytes ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
double timeStampA = getTimeStamp() ;
double timeStampD = getTimeStamp() ;
if(n>=250){
//transfer data to dev
//stream creation
int batch_h = (n+NUM_STREAMS-1)/NUM_STREAMS;
int batch_size = n*n*batch_h;
int last_batch = noElems-(NUM_STREAMS-1)*batch_size;
int b_size[NUM_STREAMS];
b_size[0] = batch_h;
b_size[NUM_STREAMS-1] = n-(NUM_STREAMS-1)*batch_h + 2;
for(int k = 1; k < NUM_STREAMS-1; k++){
b_size[k] = batch_h+2;
}
int offset[NUM_STREAMS];
offset[0] = 0;
for(int k = 1; k < NUM_STREAMS; k++){
offset[k] = k*batch_h-2;
}
//for(int k = 0; k < NUM_STREAMS; k++){
// printf("b_size %d is %d\n",k,b_size[k]);
// printf("off %d is %d\n",k,offset[k]);
//}
timeStampA = getTimeStamp() ;
cudaStream_t stream[NUM_STREAMS+1];
for (int i = 1; i < NUM_STREAMS; i++){
cudaStreamCreate(&(stream[i]));
cudaMemcpyAsync(&d_B[(i-1)*batch_size],&h_B[(i-1)*batch_size],batch_size*sizeof(float),cudaMemcpyHostToDevice,stream[i]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[i-1],d_B+n*n*offset[i-1],n,b_size[i-1]);
cudaMemcpyAsync(&h_dA[n*n*(1+offset[i-1])],&d_A[n*n*(1+offset[i-1])],(b_size[i-1]-2)*n*n*sizeof(float),cudaMemcpyDeviceToHost,stream[i]);
}
cudaStreamCreate(&(stream[NUM_STREAMS]));
cudaMemcpyAsync(&d_B[(NUM_STREAMS-1)*batch_size],&h_B[(NUM_STREAMS-1)*batch_size],last_batch*sizeof(float),cudaMemcpyHostToDevice,stream[NUM_STREAMS]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[NUM_STREAMS-1],d_B+n*n*offset[NUM_STREAMS-1],n,b_size[NUM_STREAMS-1]);
cudaMemcpyAsync(&h_dA[n*n*(1+offset[NUM_STREAMS-1])],&d_A[n*n*(1+offset[NUM_STREAMS-1])],(b_size[NUM_STREAMS-1]-2)*n*n*sizeof(float),cudaMemcpyDeviceToHost,stream[NUM_STREAMS]);
//sync all streams and done
for(int i = 1; i < NUM_STREAMS+1; i++){
cudaStreamSynchronize(stream[i]);
}
timeStampD = getTimeStamp() ;
}else{
timeStampA = getTimeStamp() ;
//transfer data to dev
cudaMemcpy( d_B, h_B, bytes, cudaMemcpyHostToDevice ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A,d_B,n,n);
cudaDeviceSynchronize() ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
//copy data back
cudaMemcpy( h_dA, d_A, bytes, cudaMemcpyDeviceToHost ) ;
timeStampD = getTimeStamp() ;
}
h_stencil(h_A,h_B,n);
//h_dA = h_A;
bool match = val(h_A,h_dA,n);
//float h_Result = h_rsum(h_A,n);
float h_dResult = h_sum(h_dA,n);
// print out results
//if(!memcmp(h_A,h_dA,n*n*n*sizeof(float))){
if(match){
//debugPrint(h_A, n);
//debugPrint(h_dC, nx, ny);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d: %lf %.6f\n", n, h_dResult, timeStampD-timeStampA);
//fclose(fptr);
//printf("%lf %lf %d\n", h_dResult, h_Result, (int)round(timeStampD-timeStampA));
printf("%lf %d\n", h_dResult, (int)round(timeStampD-timeStampA));
}else{
//debugPrint(h_A, n);
//debugPrint(h_dA, n);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d Error: function failed.\n", n);
//fclose(fptr);
printf("Error: function failed.\n");
}
// free GPU resources
cudaFree(d_A);
cudaFree(d_B);
cudaDeviceReset();
} | .file "tmpxft_000ca051_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12getTimeStampv
.type _Z12getTimeStampv, @function
_Z12getTimeStampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
imulq $1000, (%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12getTimeStampv, .-_Z12getTimeStampv
.globl _Z8initDataPfi
.type _Z8initDataPfi, @function
_Z8initDataPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r11
movl %esi, %ebx
leal (%rsi,%rsi), %r8d
movl %esi, %ebp
imull %esi, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movslq %esi, %r9
salq $2, %r9
movl $0, %r10d
movss .LC1(%rip), %xmm1
.L9:
movl %r10d, %edi
leal (%rbx,%r10), %ecx
movq %r11, %rsi
.L12:
movq %rsi, %rdx
movl %edi, %eax
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L10
addl $1, %edi
addq %r9, %rsi
addl $1, %ecx
cmpl %r8d, %ecx
jne .L12
addl $1, %r10d
addl $1, %r8d
addq %rbp, %r11
cmpl %r10d, %ebx
jne .L9
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z8initDataPfi, .-_Z8initDataPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "--------layer %d--------\n"
.LC3:
.string "%lf "
.LC4:
.string "\n"
.text
.globl _Z10debugPrintPfi
.type _Z10debugPrintPfi, @function
_Z10debugPrintPfi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 32(%rsp)
movl %esi, %r14d
movl %esi, %eax
imull %esi, %eax
movl %eax, 28(%rsp)
movslq %esi, %rdx
leaq 0(,%rdx,4), %r15
movq %rdx, %rax
negq %rax
salq $2, %rax
movq %rax, 8(%rsp)
movl $0, 20(%rsp)
movl $0, %ebx
leaq .LC3(%rip), %r12
movq %rdx, 40(%rsp)
.L22:
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r14d, %r14d
jle .L19
movslq 20(%rsp), %rax
movq 40(%rsp), %rcx
addq %rcx, %rax
movq 32(%rsp), %rdx
leaq (%rdx,%rax,4), %rbp
movl $0, %r13d
movl %ebx, 24(%rsp)
.L20:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, %r14d
jne .L20
movl 24(%rsp), %ebx
.L19:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 28(%rsp), %ecx
addl %ecx, 20(%rsp)
cmpl $3, %ebx
jne .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10debugPrintPfi, .-_Z10debugPrintPfi
.globl _Z9h_stencilPfS_i
.type _Z9h_stencilPfS_i, @function
_Z9h_stencilPfS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -8(%rsp)
cmpl $2, %edx
jle .L27
movq %rsi, %r14
movl %edx, %eax
imull %edx, %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %r15
movslq %eax, %r11
addq %r11, %rdx
leaq 0(,%rdx,4), %r12
leal -1(%rax), %ebp
salq $2, %r11
movq %rsi, %rbx
subq %r15, %rbx
movq %rbx, -40(%rsp)
leaq (%rsi,%r15), %rbx
movq %rbx, -32(%rsp)
movq %rsi, %rbx
subq %r11, %rbx
movq %rbx, -24(%rsp)
leaq (%rsi,%r11), %rbx
movq %rbx, -16(%rsp)
movl $1, %r13d
leal -1(%rax), %r10d
movss .LC5(%rip), %xmm1
.L29:
movq -40(%rsp), %rax
leaq (%r12,%rax), %r9
movq -32(%rsp), %rax
leaq (%r12,%rax), %r8
movq -24(%rsp), %rax
leaq (%r12,%rax), %rdi
movq -16(%rsp), %rax
leaq (%r12,%rax), %rsi
leaq (%r14,%r12), %rdx
movq -8(%rsp), %rax
leaq (%rax,%r12), %rcx
movl $1, %ebx
.L32:
movl $1, %eax
.L30:
movss (%r9,%rax,4), %xmm0
addss (%r8,%rax,4), %xmm0
addss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
addss -4(%rdx,%rax,4), %xmm0
addss 4(%rdx,%rax,4), %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq %r10, %rax
jne .L30
addl $1, %ebx
addq %r11, %r9
addq %r11, %r8
addq %r11, %rdi
addq %r11, %rsi
addq %r11, %rdx
addq %r11, %rcx
cmpl %ebp, %ebx
jne .L32
addl $1, %r13d
addq %r15, %r12
cmpl %ebp, %r13d
jne .L29
.L27:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9h_stencilPfS_i, .-_Z9h_stencilPfS_i
.globl _Z3valPfS_i
.type _Z3valPfS_i, @function
_Z3valPfS_i:
.LFB2061:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L42
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rcx
movl %edx, %edi
movl %edx, %eax
imull %edx, %eax
cltq
leaq 0(,%rax,4), %r9
movslq %edx, %r8
leaq 0(,%r8,4), %r11
negq %r8
salq $2, %r8
movq %r11, %rbx
movl $0, %r12d
movl $0, %ebp
.L37:
movq %rbx, %rdx
movl %ebp, %r10d
.L41:
leaq (%rdx,%r8), %rax
.L39:
movss (%rcx,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L43
jne .L43
addq $4, %rax
cmpq %rdx, %rax
jne .L39
leal 1(%r10), %eax
addq %r11, %rdx
cmpl %eax, %edi
je .L40
movl %eax, %r10d
jmp .L41
.L40:
leal 1(%r12), %eax
addq %r9, %rbx
cmpl %r10d, %r12d
je .L44
movl %eax, %r12d
jmp .L37
.L42:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
movl $1, %eax
ret
.L43:
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
.cfi_offset 6, -24
.cfi_offset 12, -16
movl $0, %eax
.L35:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movl $1, %eax
jmp .L35
.cfi_endproc
.LFE2061:
.size _Z3valPfS_i, .-_Z3valPfS_i
.globl _Z5h_sumPfi
.type _Z5h_sumPfi, @function
_Z5h_sumPfi:
.LFB2062:
.cfi_startproc
endbr64
cmpl $2, %esi
jle .L58
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %esi, %edx
imull %esi, %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %rbp
movslq %esi, %r9
addq %r9, %rdx
leaq (%rdi,%rdx,4), %r11
leal -1(%rsi), %ebx
salq $2, %r9
movl %esi, %r8d
pxor %xmm2, %xmm2
movl $1, %r10d
leal -1(%rsi), %edi
movss .LC7(%rip), %xmm3
movss .LC6(%rip), %xmm4
jmp .L53
.L54:
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm2
addq $1, %rax
cmpq %rdi, %rax
je .L65
.L55:
movss (%rsi,%rax,4), %xmm0
leal (%rcx,%rax), %edx
movaps %xmm3, %xmm1
testb $1, %dl
je .L54
movaps %xmm4, %xmm1
jmp .L54
.L65:
addq %r9, %rsi
addl $1, %ecx
cmpl %r8d, %ecx
je .L56
.L57:
movl $1, %eax
jmp .L55
.L56:
addl $1, %r10d
addl $1, %r8d
addq %rbp, %r11
cmpl %ebx, %r10d
je .L51
.L53:
leal 1(%r10), %ecx
movq %r11, %rsi
jmp .L57
.L58:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
pxor %xmm2, %xmm2
movapd %xmm2, %xmm0
ret
.L51:
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
.cfi_offset 6, -16
movapd %xmm2, %xmm0
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z5h_sumPfi, .-_Z5h_sumPfi
.globl _Z6h_rsumPfi
.type _Z6h_rsumPfi, @function
_Z6h_rsumPfi:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %esi, 44(%rsp)
cmpl $2, %esi
jle .L73
movl %esi, %eax
imull %esi, %eax
cltq
leaq 0(,%rax,4), %rdx
movq %rdx, 32(%rsp)
movslq %esi, %r15
leal -3(%rsi), %edx
addq %r15, %rax
addq %rdx, %rax
leaq 4(%rdi,%rax,4), %rax
movq %rax, 24(%rsp)
leal -1(%rsi), %eax
movl %eax, 40(%rsp)
salq $2, %r15
movq $0x000000000, (%rsp)
movl $1, 20(%rsp)
notq %rdx
leaq 0(,%rdx,4), %rax
movq %rax, 8(%rsp)
jmp .L68
.L69:
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $4, %rbx
addl $1, %ebp
cmpq %r12, %rbx
je .L77
.L70:
movss .LC9(%rip), %xmm0
mulss 4(%rbx), %xmm0
call roundf@PLT
divss .LC9(%rip), %xmm0
movss .LC7(%rip), %xmm1
testb $1, %bpl
je .L69
movss .LC6(%rip), %xmm1
jmp .L69
.L77:
addq %r15, %r12
addl $1, %r13d
cmpl %r14d, %r13d
je .L71
.L72:
movq 8(%rsp), %rax
leaq (%rax,%r12), %rbx
movl %r13d, %ebp
jmp .L70
.L71:
addl $1, 20(%rsp)
movl 20(%rsp), %eax
movq 32(%rsp), %rsi
addq %rsi, 24(%rsp)
movl 40(%rsp), %edi
cmpl %edi, %eax
je .L66
.L68:
movl 20(%rsp), %eax
leal 2(%rax), %r13d
movq 24(%rsp), %r12
movl 44(%rsp), %edx
leal (%rdx,%rax), %r14d
jmp .L72
.L73:
movq $0x000000000, (%rsp)
.L66:
movsd (%rsp), %xmm0
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z6h_rsumPfi, .-_Z6h_rsumPfi
.globl _Z14globalToSharedPfS_iiiiii
.type _Z14globalToSharedPfS_iiiiii, @function
_Z14globalToSharedPfS_iiiiii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z14globalToSharedPfS_iiiiii, .-_Z14globalToSharedPfS_iiiiii
.globl _Z29__device_stub__Z6kernalPfS_iiPfS_ii
.type _Z29__device_stub__Z6kernalPfS_iiPfS_ii, @function
_Z29__device_stub__Z6kernalPfS_iiPfS_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L84
.L80:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L85
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernalPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L80
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z29__device_stub__Z6kernalPfS_iiPfS_ii, .-_Z29__device_stub__Z6kernalPfS_iiPfS_ii
.globl _Z6kernalPfS_ii
.type _Z6kernalPfS_ii, @function
_Z6kernalPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernalPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z6kernalPfS_ii, .-_Z6kernalPfS_ii
.section .rodata.str1.1
.LC10:
.string "Error: wrong number of args\n"
.LC11:
.string "%lf %d\n"
.LC12:
.string "Error: function failed.\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $440, %rsp
.cfi_def_cfa_offset 496
movq %fs:40, %rax
movq %rax, 424(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L107
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 32(%rsp)
movl %eax, %r14d
movl %eax, %r13d
imull %eax, %r13d
movl %r13d, 8(%rsp)
movl %eax, %r12d
imull %r13d, %r12d
leal 0(,%r12,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
movl %r15d, %esi
movq 80(%rsp), %rdi
call _Z8initDataPfi
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %rbp, %rdi
call __memset_chk@PLT
movq %rbx, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call memset@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 120(%rsp)
leal 29(%r15), %ebp
shrl $5, %ebp
movl %ebp, 124(%rsp)
movl %ebp, 128(%rsp)
movl $1, 132(%rsp)
call _Z12getTimeStampv
call _Z12getTimeStampv
cmpl $249, %r15d
jle .L90
movl %r15d, %eax
leal 30(%r15), %ecx
addl $15, %eax
cmovns %eax, %ecx
sarl $4, %ecx
movl %r13d, %ebx
imull %ecx, %ebx
movl %ebx, %eax
sall $4, %eax
movl %ebx, %edx
subl %eax, %edx
movl %edx, 60(%rsp)
leal (%rdx,%r12), %eax
movl %eax, 56(%rsp)
movl %ecx, 160(%rsp)
movl %ecx, %edx
sall $4, %edx
movl %ecx, %eax
subl %edx, %eax
addl %r15d, %eax
movl %eax, 44(%rsp)
leaq 164(%rsp), %rax
leaq 220(%rsp), %rsi
leal 2(%rcx), %edx
.L91:
movl %edx, (%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L91
movl $0, 224(%rsp)
leal -2(%rcx), %edx
leaq 228(%rsp), %rax
leaq 288(%rsp), %rsi
.L92:
movl %edx, (%rax)
addl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L92
call _Z12getTimeStampv
movsd %xmm0, 48(%rsp)
movslq %ebx, %rbx
leaq 0(,%rbx,4), %rax
leaq 288(%rsp), %rcx
movq %rcx, 64(%rsp)
leaq 296(%rsp), %r12
leaq 416(%rsp), %rcx
movq %rcx, 16(%rsp)
movq %r12, %rbx
movl $0, %ebp
movl $0, %r13d
leaq 224(%rsp), %r15
movq %r12, 72(%rsp)
movq %rax, %r12
jmp .L94
.L107:
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
movl 0(%rbp,%r15), %eax
leal 1(%rax), %edi
movl 8(%rsp), %eax
imull %eax, %edi
movslq %edi, %rdi
salq $2, %rdi
movl 160(%rsp,%rbp), %eax
leal -2(%rax), %edx
imull %r14d, %edx
imull %r14d, %edx
movslq %edx, %rdx
salq $2, %rdx
movq %rdi, %rsi
addq 96(%rsp), %rsi
addq 88(%rsp), %rdi
movq (%rsp), %rax
movq (%rax), %r8
movl $2, %ecx
call cudaMemcpyAsync@PLT
addq $8, %rbx
addq %r12, %r13
addq $4, %rbp
movq 16(%rsp), %rax
cmpq %rax, %rbx
je .L108
.L94:
movq %rbx, (%rsp)
movq %rbx, %rdi
call cudaStreamCreate@PLT
movq %r13, %rsi
addq 80(%rsp), %rsi
movq %r13, %rdi
addq 104(%rsp), %rdi
movq (%rbx), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movl $32, 112(%rsp)
movl $32, 116(%rsp)
movl 120(%rsp), %ecx
movl $0, %r9d
movl $4624, %r8d
movq 112(%rsp), %rdx
movq 124(%rsp), %rdi
movl 132(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L93
movl 8(%rsp), %edi
imull 0(%rbp,%r15), %edi
movslq %edi, %rdi
salq $2, %rdi
movl 160(%rsp,%rbp), %ecx
movq %rdi, %rsi
addq 104(%rsp), %rsi
addq 96(%rsp), %rdi
movl %r14d, %edx
call _Z29__device_stub__Z6kernalPfS_iiPfS_ii
jmp .L93
.L108:
movq 72(%rsp), %r12
leaq 416(%rsp), %rdi
call cudaStreamCreate@PLT
movl 60(%rsp), %edi
negl %edi
movslq %edi, %rdi
salq $2, %rdi
movslq 56(%rsp), %rdx
salq $2, %rdx
movq %rdi, %rsi
addq 80(%rsp), %rsi
addq 104(%rsp), %rdi
movq 416(%rsp), %r8
movl $1, %ecx
call cudaMemcpyAsync@PLT
movl $32, 112(%rsp)
movl $32, 116(%rsp)
movl 120(%rsp), %ecx
movl $0, %r9d
movl $4624, %r8d
movq 112(%rsp), %rdx
movq 124(%rsp), %rdi
movl 132(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L95:
movl 284(%rsp), %eax
leal 1(%rax), %edi
movl 8(%rsp), %eax
imull %eax, %edi
movslq %edi, %rdi
salq $2, %rdi
movl 44(%rsp), %edx
movq 32(%rsp), %rax
imull %eax, %edx
imull %eax, %edx
movslq %edx, %rdx
salq $2, %rdx
movq %rdi, %rsi
addq 96(%rsp), %rsi
addq 88(%rsp), %rdi
movq 416(%rsp), %r8
movl $2, %ecx
call cudaMemcpyAsync@PLT
movq 64(%rsp), %rbx
addq $136, %rbx
.L96:
movq (%r12), %rdi
call cudaStreamSynchronize@PLT
addq $8, %r12
cmpq %rbx, %r12
jne .L96
call _Z12getTimeStampv
movsd %xmm0, 8(%rsp)
.L97:
movl %r14d, %edx
movq 80(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call _Z9h_stencilPfS_i
movq 88(%rsp), %rbp
movl %r14d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z3valPfS_i
movl %eax, %ebx
movl %r14d, %esi
movq %rbp, %rdi
call _Z5h_sumPfi
movsd %xmm0, (%rsp)
testb %bl, %bl
je .L99
movsd 8(%rsp), %xmm1
subsd 48(%rsp), %xmm1
movapd %xmm1, %xmm0
call round@PLT
cvttsd2sil %xmm0, %edx
pxor %xmm0, %xmm0
cvtsd2ss (%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L100:
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 424(%rsp), %rax
subq %fs:40, %rax
jne .L110
movl $0, %eax
addq $440, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
movl 8(%rsp), %edi
imull 284(%rsp), %edi
movslq %edi, %rdi
salq $2, %rdi
movl 44(%rsp), %eax
leal 2(%rax), %ecx
movq %rdi, %rsi
addq 104(%rsp), %rsi
addq 96(%rsp), %rdi
movl %r14d, %edx
call _Z29__device_stub__Z6kernalPfS_iiPfS_ii
jmp .L95
.L90:
call _Z12getTimeStampv
movsd %xmm0, 48(%rsp)
movl $1, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 148(%rsp)
movl %ebp, 152(%rsp)
movl $32, 136(%rsp)
movl $32, 140(%rsp)
movl $0, %r9d
movl $4624, %r8d
movq 136(%rsp), %rdx
movl $1, %ecx
movq 148(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L111
.L98:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
call _Z12getTimeStampv
movsd %xmm0, 8(%rsp)
jmp .L97
.L111:
movl %r15d, %ecx
movl %r15d, %edx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z29__device_stub__Z6kernalPfS_iiPfS_ii
jmp .L98
.L99:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L100
.L110:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z6kernalPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernalPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1066192077
.align 4
.LC5:
.long 1061997773
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long -1082130432
.align 4
.LC9:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <sys/time.h>
#include <stdio.h>
#include<math.h>
//TODO for writing to file, will be deleted
//#include <stdlib.h>
#include <cuda_runtime.h>
#define NUM_STREAMS 16
// time stamp function in ms
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000 + tv.tv_sec*1000 ;
}
void initData(float* data, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
data[i*n*n + j*n + k] = (float) (i+j+k)*(float)1.1;
}
}
}
}
void debugPrint(float* data, int n){
int i,j,k;
for(i = 0; i < 3; i++){
printf("--------layer %d--------\n",i);
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
printf("%lf ",data[i*n*n + j*n + k]);
}
printf("\n");
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_stencil(float *a, float *b, int n){
int i,j,k;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
a[i*n*n + j*n + k] = ((float)0.8)*(b[(i-1)*n*n+j*n+k]+b[(i+1)*n*n+j*n+k]+b[i*n*n+(j-1)*n+k]+b[i*n*n+(j+1)*n+k]+b[i*n*n+j*n+(k-1)]+b[i*n*n+j*n+(k+1)]);
}
}
}
}
// host side validation
bool val(float *a, float *b, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
if(a[i*n*n + j*n + k] != b[i*n*n+j*n+k]){
//printf("%d,%d,%d expect %lf, actual %lf\n",i,j,k,a[i*n*n + j*n + k],b[i*n*n+j*n+k]);
return false;
}
}
}
}
return true;
}
double h_sum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += data[i*n*n + j*n + k]*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
double h_rsum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += roundf(data[i*n*n + j*n + k]*100)/100*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
__device__ void globalToShared(float *sm, float *b, int l, int n, int smx, int smy, int ix, int iy){
sm[smx+smy*(blockDim.x+2)] = b[ix + iy*n + l*n*n];
if(smx==1){
sm[0+smy*(blockDim.x+2)] = b[ix-1 + iy*n + l*n*n];
}
if(smx==blockDim.x || ix==n-2){
sm[smx+1+smy*(blockDim.x+2)] = b[ix+1 + iy*n + l*n*n];
}
if(smy==1){
sm[smx] = b[ix + (iy-1)*n + l*n*n];
}
if(smy==blockDim.y || iy==n-2){
sm[smx+(smy+1)*(blockDim.x+2)] = b[ix + (iy+1)*n + l*n*n];
}
}
__global__ void kernal( float *a, float *b, int n, int height){
extern __shared__ float sm[];
int ix = threadIdx.x + 1;
int iy = threadIdx.y + 1;
int gx = threadIdx.x + 1 + blockIdx.x*blockDim.x;
int gy = threadIdx.y + 1 + blockIdx.y*blockDim.y;
float down,up,self;
float l1,l2,l3,l4;
if(gx<n-1&&gy<n-1){
down = b[gx+gy*n];
globalToShared(sm, b, 1, n, ix, iy, gx, gy);
__syncthreads();
self = sm[ix + iy*(blockDim.x+2)];
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
int layer;
#pragma unroll
for(layer = 2; layer < height; layer++){
globalToShared(sm, b, layer, n, ix, iy, gx, gy);
__syncthreads();
up = sm[ix + iy*(blockDim.x+2)];
a[gx + gy*n + (layer-1)*n*n] = ((float)0.8)*(down+up+l1+l2+l3+l4);
down = self;
self = up;
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
}
}
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 2) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int n = atoi( argv[1] );
//int pad_n = n + 32 - (n-2)%32;
int noElems = n*n*n ;
int bytes = noElems * sizeof(float) ;
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
//float *h_B = (float *) malloc( bytes ) ;
//float *h_dA = (float *) malloc( bytes ) ;
float *h_B;
float *h_dA;
cudaMallocHost((void**)&h_B,bytes);
cudaMallocHost((void**)&h_dA,bytes);
// init matrices with random data
initData(h_B, n);
memset(h_A, 0.0, bytes);
memset(h_dA, 0.0, bytes);
// alloc memory dev-side
float *d_A, *d_B ;
cudaMalloc( (void **) &d_A, bytes ) ;
cudaMalloc( (void **) &d_B, bytes ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
double timeStampA = getTimeStamp() ;
double timeStampD = getTimeStamp() ;
if(n>=250){
//transfer data to dev
//stream creation
int batch_h = (n+NUM_STREAMS-1)/NUM_STREAMS;
int batch_size = n*n*batch_h;
int last_batch = noElems-(NUM_STREAMS-1)*batch_size;
int b_size[NUM_STREAMS];
b_size[0] = batch_h;
b_size[NUM_STREAMS-1] = n-(NUM_STREAMS-1)*batch_h + 2;
for(int k = 1; k < NUM_STREAMS-1; k++){
b_size[k] = batch_h+2;
}
int offset[NUM_STREAMS];
offset[0] = 0;
for(int k = 1; k < NUM_STREAMS; k++){
offset[k] = k*batch_h-2;
}
//for(int k = 0; k < NUM_STREAMS; k++){
// printf("b_size %d is %d\n",k,b_size[k]);
// printf("off %d is %d\n",k,offset[k]);
//}
timeStampA = getTimeStamp() ;
cudaStream_t stream[NUM_STREAMS+1];
for (int i = 1; i < NUM_STREAMS; i++){
cudaStreamCreate(&(stream[i]));
cudaMemcpyAsync(&d_B[(i-1)*batch_size],&h_B[(i-1)*batch_size],batch_size*sizeof(float),cudaMemcpyHostToDevice,stream[i]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[i-1],d_B+n*n*offset[i-1],n,b_size[i-1]);
cudaMemcpyAsync(&h_dA[n*n*(1+offset[i-1])],&d_A[n*n*(1+offset[i-1])],(b_size[i-1]-2)*n*n*sizeof(float),cudaMemcpyDeviceToHost,stream[i]);
}
cudaStreamCreate(&(stream[NUM_STREAMS]));
cudaMemcpyAsync(&d_B[(NUM_STREAMS-1)*batch_size],&h_B[(NUM_STREAMS-1)*batch_size],last_batch*sizeof(float),cudaMemcpyHostToDevice,stream[NUM_STREAMS]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[NUM_STREAMS-1],d_B+n*n*offset[NUM_STREAMS-1],n,b_size[NUM_STREAMS-1]);
cudaMemcpyAsync(&h_dA[n*n*(1+offset[NUM_STREAMS-1])],&d_A[n*n*(1+offset[NUM_STREAMS-1])],(b_size[NUM_STREAMS-1]-2)*n*n*sizeof(float),cudaMemcpyDeviceToHost,stream[NUM_STREAMS]);
//sync all streams and done
for(int i = 1; i < NUM_STREAMS+1; i++){
cudaStreamSynchronize(stream[i]);
}
timeStampD = getTimeStamp() ;
}else{
timeStampA = getTimeStamp() ;
//transfer data to dev
cudaMemcpy( d_B, h_B, bytes, cudaMemcpyHostToDevice ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A,d_B,n,n);
cudaDeviceSynchronize() ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
//copy data back
cudaMemcpy( h_dA, d_A, bytes, cudaMemcpyDeviceToHost ) ;
timeStampD = getTimeStamp() ;
}
h_stencil(h_A,h_B,n);
//h_dA = h_A;
bool match = val(h_A,h_dA,n);
//float h_Result = h_rsum(h_A,n);
float h_dResult = h_sum(h_dA,n);
// print out results
//if(!memcmp(h_A,h_dA,n*n*n*sizeof(float))){
if(match){
//debugPrint(h_A, n);
//debugPrint(h_dC, nx, ny);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d: %lf %.6f\n", n, h_dResult, timeStampD-timeStampA);
//fclose(fptr);
//printf("%lf %lf %d\n", h_dResult, h_Result, (int)round(timeStampD-timeStampA));
printf("%lf %d\n", h_dResult, (int)round(timeStampD-timeStampA));
}else{
//debugPrint(h_A, n);
//debugPrint(h_dA, n);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d Error: function failed.\n", n);
//fclose(fptr);
printf("Error: function failed.\n");
}
// free GPU resources
cudaFree(d_A);
cudaFree(d_B);
cudaDeviceReset();
} | #include <sys/time.h>
#include <stdio.h>
#include<math.h>
//TODO for writing to file, will be deleted
//#include <stdlib.h>
#include <hip/hip_runtime.h>
#define NUM_STREAMS 16
// time stamp function in ms
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000 + tv.tv_sec*1000 ;
}
void initData(float* data, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
data[i*n*n + j*n + k] = (float) (i+j+k)*(float)1.1;
}
}
}
}
void debugPrint(float* data, int n){
int i,j,k;
for(i = 0; i < 3; i++){
printf("--------layer %d--------\n",i);
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
printf("%lf ",data[i*n*n + j*n + k]);
}
printf("\n");
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_stencil(float *a, float *b, int n){
int i,j,k;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
a[i*n*n + j*n + k] = ((float)0.8)*(b[(i-1)*n*n+j*n+k]+b[(i+1)*n*n+j*n+k]+b[i*n*n+(j-1)*n+k]+b[i*n*n+(j+1)*n+k]+b[i*n*n+j*n+(k-1)]+b[i*n*n+j*n+(k+1)]);
}
}
}
}
// host side validation
bool val(float *a, float *b, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
if(a[i*n*n + j*n + k] != b[i*n*n+j*n+k]){
//printf("%d,%d,%d expect %lf, actual %lf\n",i,j,k,a[i*n*n + j*n + k],b[i*n*n+j*n+k]);
return false;
}
}
}
}
return true;
}
double h_sum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += data[i*n*n + j*n + k]*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
double h_rsum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += roundf(data[i*n*n + j*n + k]*100)/100*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
__device__ void globalToShared(float *sm, float *b, int l, int n, int smx, int smy, int ix, int iy){
sm[smx+smy*(blockDim.x+2)] = b[ix + iy*n + l*n*n];
if(smx==1){
sm[0+smy*(blockDim.x+2)] = b[ix-1 + iy*n + l*n*n];
}
if(smx==blockDim.x || ix==n-2){
sm[smx+1+smy*(blockDim.x+2)] = b[ix+1 + iy*n + l*n*n];
}
if(smy==1){
sm[smx] = b[ix + (iy-1)*n + l*n*n];
}
if(smy==blockDim.y || iy==n-2){
sm[smx+(smy+1)*(blockDim.x+2)] = b[ix + (iy+1)*n + l*n*n];
}
}
__global__ void kernal( float *a, float *b, int n, int height){
extern __shared__ float sm[];
int ix = threadIdx.x + 1;
int iy = threadIdx.y + 1;
int gx = threadIdx.x + 1 + blockIdx.x*blockDim.x;
int gy = threadIdx.y + 1 + blockIdx.y*blockDim.y;
float down,up,self;
float l1,l2,l3,l4;
if(gx<n-1&&gy<n-1){
down = b[gx+gy*n];
globalToShared(sm, b, 1, n, ix, iy, gx, gy);
__syncthreads();
self = sm[ix + iy*(blockDim.x+2)];
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
int layer;
#pragma unroll
for(layer = 2; layer < height; layer++){
globalToShared(sm, b, layer, n, ix, iy, gx, gy);
__syncthreads();
up = sm[ix + iy*(blockDim.x+2)];
a[gx + gy*n + (layer-1)*n*n] = ((float)0.8)*(down+up+l1+l2+l3+l4);
down = self;
self = up;
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
}
}
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 2) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int n = atoi( argv[1] );
//int pad_n = n + 32 - (n-2)%32;
int noElems = n*n*n ;
int bytes = noElems * sizeof(float) ;
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
//float *h_B = (float *) malloc( bytes ) ;
//float *h_dA = (float *) malloc( bytes ) ;
float *h_B;
float *h_dA;
hipHostMalloc((void**)&h_B,bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_dA,bytes, hipHostMallocDefault);
// init matrices with random data
initData(h_B, n);
memset(h_A, 0.0, bytes);
memset(h_dA, 0.0, bytes);
// alloc memory dev-side
float *d_A, *d_B ;
hipMalloc( (void **) &d_A, bytes ) ;
hipMalloc( (void **) &d_B, bytes ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
double timeStampA = getTimeStamp() ;
double timeStampD = getTimeStamp() ;
if(n>=250){
//transfer data to dev
//stream creation
int batch_h = (n+NUM_STREAMS-1)/NUM_STREAMS;
int batch_size = n*n*batch_h;
int last_batch = noElems-(NUM_STREAMS-1)*batch_size;
int b_size[NUM_STREAMS];
b_size[0] = batch_h;
b_size[NUM_STREAMS-1] = n-(NUM_STREAMS-1)*batch_h + 2;
for(int k = 1; k < NUM_STREAMS-1; k++){
b_size[k] = batch_h+2;
}
int offset[NUM_STREAMS];
offset[0] = 0;
for(int k = 1; k < NUM_STREAMS; k++){
offset[k] = k*batch_h-2;
}
//for(int k = 0; k < NUM_STREAMS; k++){
// printf("b_size %d is %d\n",k,b_size[k]);
// printf("off %d is %d\n",k,offset[k]);
//}
timeStampA = getTimeStamp() ;
hipStream_t stream[NUM_STREAMS+1];
for (int i = 1; i < NUM_STREAMS; i++){
hipStreamCreate(&(stream[i]));
hipMemcpyAsync(&d_B[(i-1)*batch_size],&h_B[(i-1)*batch_size],batch_size*sizeof(float),hipMemcpyHostToDevice,stream[i]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[i-1],d_B+n*n*offset[i-1],n,b_size[i-1]);
hipMemcpyAsync(&h_dA[n*n*(1+offset[i-1])],&d_A[n*n*(1+offset[i-1])],(b_size[i-1]-2)*n*n*sizeof(float),hipMemcpyDeviceToHost,stream[i]);
}
hipStreamCreate(&(stream[NUM_STREAMS]));
hipMemcpyAsync(&d_B[(NUM_STREAMS-1)*batch_size],&h_B[(NUM_STREAMS-1)*batch_size],last_batch*sizeof(float),hipMemcpyHostToDevice,stream[NUM_STREAMS]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[NUM_STREAMS-1],d_B+n*n*offset[NUM_STREAMS-1],n,b_size[NUM_STREAMS-1]);
hipMemcpyAsync(&h_dA[n*n*(1+offset[NUM_STREAMS-1])],&d_A[n*n*(1+offset[NUM_STREAMS-1])],(b_size[NUM_STREAMS-1]-2)*n*n*sizeof(float),hipMemcpyDeviceToHost,stream[NUM_STREAMS]);
//sync all streams and done
for(int i = 1; i < NUM_STREAMS+1; i++){
hipStreamSynchronize(stream[i]);
}
timeStampD = getTimeStamp() ;
}else{
timeStampA = getTimeStamp() ;
//transfer data to dev
hipMemcpy( d_B, h_B, bytes, hipMemcpyHostToDevice ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A,d_B,n,n);
hipDeviceSynchronize() ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
//copy data back
hipMemcpy( h_dA, d_A, bytes, hipMemcpyDeviceToHost ) ;
timeStampD = getTimeStamp() ;
}
h_stencil(h_A,h_B,n);
//h_dA = h_A;
bool match = val(h_A,h_dA,n);
//float h_Result = h_rsum(h_A,n);
float h_dResult = h_sum(h_dA,n);
// print out results
//if(!memcmp(h_A,h_dA,n*n*n*sizeof(float))){
if(match){
//debugPrint(h_A, n);
//debugPrint(h_dC, nx, ny);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d: %lf %.6f\n", n, h_dResult, timeStampD-timeStampA);
//fclose(fptr);
//printf("%lf %lf %d\n", h_dResult, h_Result, (int)round(timeStampD-timeStampA));
printf("%lf %d\n", h_dResult, (int)round(timeStampD-timeStampA));
}else{
//debugPrint(h_A, n);
//debugPrint(h_dA, n);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d Error: function failed.\n", n);
//fclose(fptr);
printf("Error: function failed.\n");
}
// free GPU resources
hipFree(d_A);
hipFree(d_B);
hipDeviceReset();
} |
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