system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <sys/time.h>
#include <stdio.h>
#include<math.h>
//TODO for writing to file, will be deleted
//#include <stdlib.h>
#include <hip/hip_runtime.h>
#define NUM_STREAMS 16
// time stamp function in ms
double getTimeStamp() {
struct timeval tv ;
gettimeofday( &tv, NULL ) ;
return (double) tv.tv_usec/1000 + tv.tv_sec*1000 ;
}
void initData(float* data, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
data[i*n*n + j*n + k] = (float) (i+j+k)*(float)1.1;
}
}
}
}
void debugPrint(float* data, int n){
int i,j,k;
for(i = 0; i < 3; i++){
printf("--------layer %d--------\n",i);
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
printf("%lf ",data[i*n*n + j*n + k]);
}
printf("\n");
}
printf("\n");
}
printf("\n");
}
// host side matrix addition
void h_stencil(float *a, float *b, int n){
int i,j,k;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
a[i*n*n + j*n + k] = ((float)0.8)*(b[(i-1)*n*n+j*n+k]+b[(i+1)*n*n+j*n+k]+b[i*n*n+(j-1)*n+k]+b[i*n*n+(j+1)*n+k]+b[i*n*n+j*n+(k-1)]+b[i*n*n+j*n+(k+1)]);
}
}
}
}
// host side validation
bool val(float *a, float *b, int n){
int i,j,k;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
for(k = 0; k < n; k++){
if(a[i*n*n + j*n + k] != b[i*n*n+j*n+k]){
//printf("%d,%d,%d expect %lf, actual %lf\n",i,j,k,a[i*n*n + j*n + k],b[i*n*n+j*n+k]);
return false;
}
}
}
}
return true;
}
double h_sum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += data[i*n*n + j*n + k]*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
double h_rsum(float *data, int n){
int i,j,k;
double ret=0;
for(i = 1; i < n-1; i++){
for(j = 1; j < n-1; j++){
for(k = 1; k < n-1; k++){
ret += roundf(data[i*n*n + j*n + k]*100)/100*(((i+j+k)%2)?1:-1);
}
}
}
return ret;
}
__device__ void globalToShared(float *sm, float *b, int l, int n, int smx, int smy, int ix, int iy){
sm[smx+smy*(blockDim.x+2)] = b[ix + iy*n + l*n*n];
if(smx==1){
sm[0+smy*(blockDim.x+2)] = b[ix-1 + iy*n + l*n*n];
}
if(smx==blockDim.x || ix==n-2){
sm[smx+1+smy*(blockDim.x+2)] = b[ix+1 + iy*n + l*n*n];
}
if(smy==1){
sm[smx] = b[ix + (iy-1)*n + l*n*n];
}
if(smy==blockDim.y || iy==n-2){
sm[smx+(smy+1)*(blockDim.x+2)] = b[ix + (iy+1)*n + l*n*n];
}
}
__global__ void kernal( float *a, float *b, int n, int height){
extern __shared__ float sm[];
int ix = threadIdx.x + 1;
int iy = threadIdx.y + 1;
int gx = threadIdx.x + 1 + blockIdx.x*blockDim.x;
int gy = threadIdx.y + 1 + blockIdx.y*blockDim.y;
float down,up,self;
float l1,l2,l3,l4;
if(gx<n-1&&gy<n-1){
down = b[gx+gy*n];
globalToShared(sm, b, 1, n, ix, iy, gx, gy);
__syncthreads();
self = sm[ix + iy*(blockDim.x+2)];
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
int layer;
#pragma unroll
for(layer = 2; layer < height; layer++){
globalToShared(sm, b, layer, n, ix, iy, gx, gy);
__syncthreads();
up = sm[ix + iy*(blockDim.x+2)];
a[gx + gy*n + (layer-1)*n*n] = ((float)0.8)*(down+up+l1+l2+l3+l4);
down = self;
self = up;
l1 = sm[ix-1 + iy*(blockDim.x+2)];
l2 = sm[ix+1 + iy*(blockDim.x+2)];
l3 = sm[ix + (iy-1)*(blockDim.x+2)];
l4 = sm[ix + (iy+1)*(blockDim.x+2)];
__syncthreads();
}
}
}
int main( int argc, char *argv[] ) {
// get program arguments
if( argc != 2) {
printf("Error: wrong number of args\n") ;
exit(1) ;
}
int n = atoi( argv[1] );
//int pad_n = n + 32 - (n-2)%32;
int noElems = n*n*n ;
int bytes = noElems * sizeof(float) ;
// alloc memory host-side
float *h_A = (float *) malloc( bytes ) ;
//float *h_B = (float *) malloc( bytes ) ;
//float *h_dA = (float *) malloc( bytes ) ;
float *h_B;
float *h_dA;
hipHostMalloc((void**)&h_B,bytes, hipHostMallocDefault);
hipHostMalloc((void**)&h_dA,bytes, hipHostMallocDefault);
// init matrices with random data
initData(h_B, n);
memset(h_A, 0.0, bytes);
memset(h_dA, 0.0, bytes);
// alloc memory dev-side
float *d_A, *d_B ;
hipMalloc( (void **) &d_A, bytes ) ;
hipMalloc( (void **) &d_B, bytes ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
double timeStampA = getTimeStamp() ;
double timeStampD = getTimeStamp() ;
if(n>=250){
//transfer data to dev
//stream creation
int batch_h = (n+NUM_STREAMS-1)/NUM_STREAMS;
int batch_size = n*n*batch_h;
int last_batch = noElems-(NUM_STREAMS-1)*batch_size;
int b_size[NUM_STREAMS];
b_size[0] = batch_h;
b_size[NUM_STREAMS-1] = n-(NUM_STREAMS-1)*batch_h + 2;
for(int k = 1; k < NUM_STREAMS-1; k++){
b_size[k] = batch_h+2;
}
int offset[NUM_STREAMS];
offset[0] = 0;
for(int k = 1; k < NUM_STREAMS; k++){
offset[k] = k*batch_h-2;
}
//for(int k = 0; k < NUM_STREAMS; k++){
// printf("b_size %d is %d\n",k,b_size[k]);
// printf("off %d is %d\n",k,offset[k]);
//}
timeStampA = getTimeStamp() ;
hipStream_t stream[NUM_STREAMS+1];
for (int i = 1; i < NUM_STREAMS; i++){
hipStreamCreate(&(stream[i]));
hipMemcpyAsync(&d_B[(i-1)*batch_size],&h_B[(i-1)*batch_size],batch_size*sizeof(float),hipMemcpyHostToDevice,stream[i]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[i-1],d_B+n*n*offset[i-1],n,b_size[i-1]);
hipMemcpyAsync(&h_dA[n*n*(1+offset[i-1])],&d_A[n*n*(1+offset[i-1])],(b_size[i-1]-2)*n*n*sizeof(float),hipMemcpyDeviceToHost,stream[i]);
}
hipStreamCreate(&(stream[NUM_STREAMS]));
hipMemcpyAsync(&d_B[(NUM_STREAMS-1)*batch_size],&h_B[(NUM_STREAMS-1)*batch_size],last_batch*sizeof(float),hipMemcpyHostToDevice,stream[NUM_STREAMS]);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A+n*n*offset[NUM_STREAMS-1],d_B+n*n*offset[NUM_STREAMS-1],n,b_size[NUM_STREAMS-1]);
hipMemcpyAsync(&h_dA[n*n*(1+offset[NUM_STREAMS-1])],&d_A[n*n*(1+offset[NUM_STREAMS-1])],(b_size[NUM_STREAMS-1]-2)*n*n*sizeof(float),hipMemcpyDeviceToHost,stream[NUM_STREAMS]);
//sync all streams and done
for(int i = 1; i < NUM_STREAMS+1; i++){
hipStreamSynchronize(stream[i]);
}
timeStampD = getTimeStamp() ;
}else{
timeStampA = getTimeStamp() ;
//transfer data to dev
hipMemcpy( d_B, h_B, bytes, hipMemcpyHostToDevice ) ;
//debugPrint(h_B, n);
// invoke Kernel
dim3 block(32, 32);
dim3 grid((n-2+block.x-1)/block.x,(n-2+block.y-1)/block.y);
kernal<<<grid,block,(1024+33*4)*sizeof(float)>>>(d_A,d_B,n,n);
hipDeviceSynchronize() ;
//cudaDeviceProp GPUprop;
//cudaGetDeviceProperties(&GPUprop,0);
//printf("maxgridsize x is %d\n",GPUprop.maxGridSize[0]);
//copy data back
hipMemcpy( h_dA, d_A, bytes, hipMemcpyDeviceToHost ) ;
timeStampD = getTimeStamp() ;
}
h_stencil(h_A,h_B,n);
//h_dA = h_A;
bool match = val(h_A,h_dA,n);
//float h_Result = h_rsum(h_A,n);
float h_dResult = h_sum(h_dA,n);
// print out results
//if(!memcmp(h_A,h_dA,n*n*n*sizeof(float))){
if(match){
//debugPrint(h_A, n);
//debugPrint(h_dC, nx, ny);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d: %lf %.6f\n", n, h_dResult, timeStampD-timeStampA);
//fclose(fptr);
//printf("%lf %lf %d\n", h_dResult, h_Result, (int)round(timeStampD-timeStampA));
printf("%lf %d\n", h_dResult, (int)round(timeStampD-timeStampA));
}else{
//debugPrint(h_A, n);
//debugPrint(h_dA, n);
//FILE* fptr;
//fptr = fopen("time.log","a");
//fprintf(fptr,"%d Error: function failed.\n", n);
//fclose(fptr);
printf("Error: function failed.\n");
}
// free GPU resources
hipFree(d_A);
hipFree(d_B);
hipDeviceReset();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernalPfS_ii
.globl _Z6kernalPfS_ii
.p2align 8
.type _Z6kernalPfS_ii,@function
_Z6kernalPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v10, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, 1, v6
v_add_nc_u32_e32 v7, 1, v10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s4, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s11, s15, s4
v_add_nc_u32_e32 v2, s14, v11
v_add_nc_u32_e32 v8, s11, v7
s_add_i32 s2, s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v2, v8
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_20
v_mul_lo_u32 v9, v8, s8
v_mad_u64_u32 v[0:1], null, s8, s8, v[2:3]
s_load_b64 s[6:7], s[0:1], 0x8
s_add_i32 s12, s3, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v14, s12, v7
v_add_nc_u32_e32 v12, v9, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v9, v0
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v5, v[12:13], off
v_lshl_add_u32 v3, v14, 2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v11, 2, v3
s_waitcnt vmcnt(1)
ds_store_b32 v4, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_3
v_add3_u32 v12, v9, v0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v1, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s5, s8, -2
v_cmp_eq_u32_e64 s2, s3, v11
v_cmp_eq_u32_e64 s3, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s2, s3
s_and_saveexec_b32 s3, s9
s_cbranch_execz .LBB0_5
v_add3_u32 v1, v9, v0, 1
v_lshlrev_b32_e32 v12, 2, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s6, v1
v_add_co_ci_u32_e64 v2, s2, s7, v2, s2
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v11
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v12
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1 offset:4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s2, 0, v10
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[1:2], null, s11, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s3, s6, v1
v_add_co_ci_u32_e64 v2, s3, s7, v2, s3
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v11, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
v_cmp_eq_u32_e64 s3, s4, v7
v_cmp_eq_u32_e64 s4, s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s10, s3, s4
s_and_saveexec_b32 s4, s10
s_cbranch_execz .LBB0_9
v_add3_u32 v0, v9, s8, v0
v_lshlrev_b32_e32 v2, 2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s3, s6, v0
v_add_co_ci_u32_e64 v1, s3, s7, v1, s3
global_load_b32 v0, v[0:1], off
v_add_nc_u32_e32 v1, 2, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, s12, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v1, 0, v1, v2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v15, 2, v10
v_add_nc_u32_e32 v0, v14, v6
v_add_nc_u32_e32 v1, v14, v11
v_mad_u32_u24 v8, s12, v10, v11
s_load_b32 s3, s[0:1], 0x14
v_mad_u32_u24 v9, s12, v15, v11
v_lshl_add_u32 v2, v0, 2, 0
v_lshl_add_u32 v7, v1, 2, 0
v_lshl_add_u32 v8, v8, 2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_lshl_add_u32 v9, v9, 2, 0
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v2 offset1:2
ds_load_b32 v19, v7
ds_load_b32 v13, v8
ds_load_b32 v12, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s3, 3
s_cbranch_scc1 .LBB0_20
s_lshl_b32 s4, s8, 1
v_lshl_add_u32 v11, v11, 2, 0
s_add_i32 s13, s11, s4
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v18, s13, v10
v_add3_u32 v10, s11, s8, v10
v_lshlrev_b32_e32 v14, 2, v14
v_mul_u32_u24_e32 v15, s12, v15
s_mul_i32 s0, s8, s13
v_add_nc_u32_e32 v20, 2, v18
v_mad_u64_u32 v[16:17], null, s8, v10, s[8:9]
v_mul_lo_u32 v17, s8, v18
v_add_nc_u32_e32 v10, 8, v2
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v18, s8, v20
v_add3_u32 v14, v11, v14, 4
v_lshl_add_u32 v15, v15, 2, v11
s_add_i32 s1, s3, -2
v_add3_u32 v16, v6, v16, 1
s_mul_i32 s3, s8, s8
v_add3_u32 v17, v17, s8, v6
v_add3_u32 v18, v6, v18, 1
v_add3_u32 v6, v6, s0, 1
s_branch .LBB0_12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v19, v7
v_add_nc_u32_e32 v17, s3, v17
s_add_i32 s1, s1, -1
v_add_nc_u32_e32 v18, s3, v18
s_cmp_lg_u32 s1, 0
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v5, v5, v19 :: v_dual_add_nc_u32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v0, v5 :: v_dual_add_nc_u32 v0, s14, v16
v_dual_add_f32 v5, v1, v5 :: v_dual_add_nc_u32 v16, s3, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_f32_e32 v5, v13, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[21:22], 2, v[0:1]
v_add_f32_e32 v5, v12, v5
ds_load_b32 v0, v2
ds_load_b32 v1, v10
ds_load_b32 v13, v8
ds_load_b32 v12, v9
v_add_co_u32 v21, s0, s4, v21
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s0, s5, v22, s0
v_mul_f32_e32 v5, 0x3f4ccccd, v5
global_store_b32 v[21:22], v5, off
v_mov_b32_e32 v5, v20
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_20
.LBB0_12:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v20, s14, v17, 1
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[20:21], 2, v[20:21]
v_add_co_u32 v20, s0, s6, v20
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v21, s0, s7, v21, s0
global_load_b32 v21, v[20:21], off
v_mov_b32_e32 v20, v19
s_waitcnt vmcnt(0)
ds_store_b32 v4, v21
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v21, s14, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v19
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s9
s_cbranch_execz .LBB0_16
v_add3_u32 v21, s14, v17, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v14, v19
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_18
v_add_nc_u32_e32 v21, s14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v19
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s10
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v21, s14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v15, v19
s_branch .LBB0_11
.LBB0_20:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernalPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernalPfS_ii, .Lfunc_end0-_Z6kernalPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernalPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernalPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernalPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR8, -0x1, URZ ; /* 0xffffffff08047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R20, SR_TID.Y ; /* 0x0000000000147919 */
/* 0x000e680000002200 */
/*0050*/ S2R R21, SR_TID.X ; /* 0x0000000000157919 */
/* 0x000ea80000002100 */
/*0060*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000ee20000002500 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], RZ ; /* 0x0000010011117a24 */
/* 0x001fe200078e02ff */
/*0080*/ IADD3 R22, R20, 0x1, RZ ; /* 0x0000000114167810 */
/* 0x002fc40007ffe0ff */
/*0090*/ IADD3 R0, R21, 0x1, RZ ; /* 0x0000000115007810 */
/* 0x004fe40007ffe0ff */
/*00a0*/ IADD3 R19, R22, R17, RZ ; /* 0x0000001116137210 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD R2, R18, c[0x0][0x0], R0 ; /* 0x0000000012027a24 */
/* 0x008fe200078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R19, UR4, PT ; /* 0x0000000413007c0c */
/* 0x000fc8000bf06270 */
/*00d0*/ ISETP.GE.OR P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fda0008706670 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ UIADD3 UR4, UR8, -0x2, URZ ; /* 0xfffffffe08047890 */
/* 0x000fe2000fffe03f */
/*0100*/ ISETP.NE.AND P2, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe20003f45270 */
/*0110*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0120*/ ISETP.NE.AND P3, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f65270 */
/*0130*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R16, R18.reuse, c[0x0][0x0], R21 ; /* 0x0000000012107a24 */
/* 0x040fe200078e0215 */
/*0150*/ ISETP.NE.AND P0, PT, R19.reuse, UR4, PT ; /* 0x0000000413007c0c */
/* 0x040fe2000bf05270 */
/*0160*/ IMAD R18, R18, c[0x0][0x0], RZ ; /* 0x0000000012127a24 */
/* 0x000fe200078e02ff */
/*0170*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf25270 */
/*0180*/ UIMAD UR4, UR8, UR6, URZ ; /* 0x00000006080472a4 */
/* 0x000fe2000f8e023f */
/*0190*/ ISETP.EQ.OR P0, PT, R22, c[0x0][0x4], !P0 ; /* 0x0000010016007a0c */
/* 0x000fe20004702670 */
/*01a0*/ IMAD R2, R19.reuse, c[0x0][0x170], R16 ; /* 0x00005c0013027a24 */
/* 0x040fe200078e0210 */
/*01b0*/ ISETP.EQ.OR P1, PT, R0, c[0x0][0x0], !P1 ; /* 0x0000000000007a0c */
/* 0x000fe20004f22670 */
/*01c0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*01d0*/ @!P2 IMAD R3, R19, c[0x0][0x170], R18 ; /* 0x00005c001303aa24 */
/* 0x000fe200078e0212 */
/*01e0*/ MOV R11, UR4 ; /* 0x00000004000b7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ @!P3 IMAD R4, R17, c[0x0][0x170], R16 ; /* 0x00005c001104ba24 */
/* 0x000fe200078e0210 */
/*0200*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x000fe20008000f00 */
/*0210*/ IMAD.WIDE R8, R2, R25, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fe200078e0219 */
/*0220*/ @!P2 IADD3 R6, R3, UR4, RZ ; /* 0x000000040306ac10 */
/* 0x000fc4000fffe0ff */
/*0230*/ @!P3 IADD3 R12, R4, UR4, RZ ; /* 0x00000004040cbc10 */
/* 0x000fe4000fffe0ff */
/*0240*/ @P0 IADD3 R5, R19, 0x1, RZ ; /* 0x0000000113050810 */
/* 0x000fe20007ffe0ff */
/*0250*/ UMOV UR5, 0x2 ; /* 0x0000000200057882 */
/* 0x000fe20000000000 */
/*0260*/ @P1 IADD3 R10, R2, 0x1, R11 ; /* 0x00000001020a1810 */
/* 0x000fe20007ffe00b */
/*0270*/ @!P3 IMAD.WIDE R12, R12, R25.reuse, c[0x0][0x168] ; /* 0x00005a000c0cb625 */
/* 0x080fe200078e0219 */
/*0280*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000800 */
/*0290*/ LDG.E R27, [R8.64+0x4] ; /* 0x0000040a081b7981 */
/* 0x000164000c1e1900 */
/*02a0*/ @P0 IMAD R5, R5, c[0x0][0x170], R16 ; /* 0x00005c0005050a24 */
/* 0x000fe400078e0210 */
/*02b0*/ @P1 IMAD.WIDE R10, R10, R25.reuse, c[0x0][0x168] ; /* 0x00005a000a0a1625 */
/* 0x080fe200078e0219 */
/*02c0*/ @!P3 LDG.E R13, [R12.64+0x4] ; /* 0x0000040a0c0db981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ @P0 IADD3 R14, R5, UR4, RZ ; /* 0x00000004050e0c10 */
/* 0x000fe2000fffe0ff */
/*02e0*/ IMAD.WIDE R4, R7, 0x4, R8 ; /* 0x0000000407047825 */
/* 0x000fe200078e0208 */
/*02f0*/ @P1 LDG.E R29, [R10.64+0x4] ; /* 0x0000040a0a1d1981 */
/* 0x000ee6000c1e1900 */
/*0300*/ @!P2 IMAD.WIDE R6, R6, R25.reuse, c[0x0][0x168] ; /* 0x00005a000606a625 */
/* 0x080fe200078e0219 */
/*0310*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040a04177981 */
/* 0x000326000c1e1900 */
/*0320*/ @P0 IMAD.WIDE R14, R14, R25, c[0x0][0x168] ; /* 0x00005a000e0e0625 */
/* 0x000fe200078e0219 */
/*0330*/ @!P2 LDG.E R24, [R6.64] ; /* 0x0000000a0618a981 */
/* 0x0000aa000c1e1900 */
/*0340*/ @P0 LDG.E R14, [R14.64+0x4] ; /* 0x0000040a0e0e0981 */
/* 0x000ee2000c1e1900 */
/*0350*/ UIADD3 UR5, UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fcc000fffe03f */
/*0360*/ IMAD R3, R22, UR5, RZ ; /* 0x0000000516037c24 */
/* 0x000fe2000f8e02ff */
/*0370*/ IADD3 R22, R20, 0x2, RZ ; /* 0x0000000214167810 */
/* 0x000fc80007ffe0ff */
/*0380*/ IADD3 R4, R3, R21, RZ ; /* 0x0000001503047210 */
/* 0x002fe20007ffe0ff */
/*0390*/ IMAD R5, R22, UR5, R21.reuse ; /* 0x0000000516057c24 */
/* 0x100fe4000f8e0215 */
/*03a0*/ IMAD R6, R20, UR5, R21 ; /* 0x0000000514067c24 */
/* 0x001fe2000f8e0215 */
/*03b0*/ UISETP.GE.AND UP0, UPT, UR7, 0x3, UPT ; /* 0x000000030700788c */
/* 0x000fcc000bf06270 */
/*03c0*/ PLOP3.LUT P4, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f8f008 */
/*03d0*/ STS [R4.X4+0x4], R23 ; /* 0x0000041704007388 */
/* 0x0101e80000004800 */
/*03e0*/ @!P2 STS [R3.X4], R24 ; /* 0x000000180300a388 */
/* 0x0041e80000004800 */
/*03f0*/ @P1 STS [R4.X4+0x8], R29 ; /* 0x0000081d04001388 */
/* 0x0081e80000004800 */
/*0400*/ @!P3 STS [R0.X4], R13 ; /* 0x0000000d0000b388 */
/* 0x0001e80000004800 */
/*0410*/ @P0 STS [R5.X4+0x4], R14 ; /* 0x0000040e05000388 */
/* 0x0001e80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ LDS R21, [R4.X4] ; /* 0x0000000004157984 */
/* 0x0000680000004800 */
/*0440*/ LDS R20, [R4.X4+0x8] ; /* 0x0000080004147984 */
/* 0x0000a80000004800 */
/*0450*/ LDS R26, [R6.X4+0x4] ; /* 0x00000400061a7984 */
/* 0x0000e80000004800 */
/*0460*/ LDS R10, [R5.X4+0x4] ; /* 0x00000400050a7984 */
/* 0x0001280000004800 */
/*0470*/ LDS R11, [R4.X4+0x4] ; /* 0x00000400040b7984 */
/* 0x0000280000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P4 EXIT ; /* 0x000000000000c94d */
/* 0x000fea0003800000 */
/*04a0*/ UISETP.NE.AND UP0, UPT, UR7, 0x3, UPT ; /* 0x000000030700788c */
/* 0x006fe2000bf05270 */
/*04b0*/ IADD3 R9, R19.reuse, 0x1, RZ ; /* 0x0000000113097810 */
/* 0x040fe20007ffe0ff */
/*04c0*/ UIADD3 UR5, UR7, -0x2, URZ ; /* 0xfffffffe07057890 */
/* 0x000fe2000fffe03f */
/*04d0*/ SHF.R.S32.HI R13, RZ, 0x1f, R2 ; /* 0x0000001fff0d7819 */
/* 0x001fe20000011402 */
/*04e0*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe20000000000 */
/*04f0*/ LEA R12, P4, R2.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a00020c7a11 */
/* 0x040fe200078810ff */
/*0500*/ ULOP3.LUT UR8, UR5, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000105087892 */
/* 0x000fe2000f8ec03f */
/*0510*/ PLOP3.LUT P5, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003faf008 */
/*0520*/ IMAD.MOV.U32 R29, RZ, RZ, R10 ; /* 0x000000ffff1d7224 */
/* 0x010fe200078e000a */
/*0530*/ LEA.HI.X R13, R2.reuse, c[0x0][0x16c], R13, 0x2, P4 ; /* 0x00005b00020d7a11 */
/* 0x040fe200020f140d */
/*0540*/ IMAD R7, R19, c[0x0][0x170], R18 ; /* 0x00005c0013077a24 */
/* 0x000fe200078e0212 */
/*0550*/ IADD3 R10, R2, 0x1, RZ ; /* 0x00000001020a7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD R8, R17, c[0x0][0x170], R16 ; /* 0x00005c0011087a24 */
/* 0x000fc400078e0210 */
/*0570*/ IMAD R9, R9, c[0x0][0x170], R16 ; /* 0x00005c0009097a24 */
/* 0x000fcc00078e0210 */
/*0580*/ @!P5 BRA 0xb10 ; /* 0x000005800000d947 */
/* 0x000fea0003800000 */
/*0590*/ UIADD3 UR5, UR5, -UR8, URZ ; /* 0x8000000805057290 */
/* 0x000fe4000fffe03f */
/*05a0*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe40000000000 */
/*05b0*/ UIMAD UR9, UR4, UR6, URZ ; /* 0x00000006040972a4 */
/* 0x000fe2000f8e023f */
/*05c0*/ @!P2 MOV R23, 0x4 ; /* 0x000000040017a802 */
/* 0x000fe40000000f00 */
/*05d0*/ @P1 MOV R14, 0x4 ; /* 0x00000004000e1802 */
/* 0x001fc60000000f00 */
/*05e0*/ MOV R25, UR9 ; /* 0x0000000900197c02 */
/* 0x000fe40008000f00 */
/*05f0*/ @!P2 IADD3 R22, R7, UR9, RZ ; /* 0x000000090716ac10 */
/* 0x000fe4000fffe0ff */
/*0600*/ @P1 IADD3 R15, R10, UR9, RZ ; /* 0x000000090a0f1c10 */
/* 0x000fe2000fffe0ff */
/*0610*/ IMAD.WIDE R24, R25, 0x4, R12 ; /* 0x0000000419187825 */
/* 0x000fe200078e020c */
/*0620*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fe40000000f00 */
/*0630*/ @!P3 IADD3 R16, R8, UR9, RZ ; /* 0x000000090810bc10 */
/* 0x000fe2000fffe0ff */
/*0640*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff120424 */
/* 0x000fe200078e00ff */
/*0650*/ @P0 IADD3 R19, R9, UR9, RZ ; /* 0x0000000909130c10 */
/* 0x000fe2000fffe0ff */
/*0660*/ @!P2 IMAD.WIDE R22, R22, R23, c[0x0][0x168] ; /* 0x00005a001616a625 */
/* 0x000fe200078e0217 */
/*0670*/ LDG.E R25, [R24.64+0x4] ; /* 0x0000040a18197981 */
/* 0x004ea6000c1e1900 */
/*0680*/ @P1 IMAD.WIDE R14, R15, R14, c[0x0][0x168] ; /* 0x00005a000f0e1625 */
/* 0x000fc400078e020e */
/*0690*/ @!P2 LDG.E R22, [R22.64] ; /* 0x0000000a1616a981 */
/* 0x010f24000c1e1900 */
/*06a0*/ @!P3 IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a001010b625 */
/* 0x000fe400078e0211 */
/*06b0*/ @P1 LDG.E R15, [R14.64+0x4] ; /* 0x0000040a0e0f1981 */
/* 0x008ee4000c1e1900 */
/*06c0*/ @P0 IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013120625 */
/* 0x000fe400078e0212 */
/*06d0*/ @!P3 LDG.E R17, [R16.64+0x4] ; /* 0x0000040a1011b981 */
/* 0x000ee8000c1e1900 */
/*06e0*/ @P0 LDG.E R18, [R18.64+0x4] ; /* 0x0000040a12120981 */
/* 0x000ee2000c1e1900 */
/*06f0*/ UIADD3 UR7, -UR4, UR9, URZ ; /* 0x0000000904077290 */
/* 0x000fc6000fffe13f */
/*0700*/ STS [R4.X4+0x4], R25 ; /* 0x0000041904007388 */
/* 0x0041e80000004800 */
/*0710*/ @!P2 STS [R3.X4], R22 ; /* 0x000000160300a388 */
/* 0x010fe80000004800 */
/*0720*/ @P1 STS [R4.X4+0x8], R15 ; /* 0x0000080f04001388 */
/* 0x008fe80000004800 */
/*0730*/ @!P3 STS [R0.X4], R17 ; /* 0x000000110000b388 */
/* 0x000fe80000004800 */
/*0740*/ @P0 STS [R5.X4+0x4], R18 ; /* 0x0000041205000388 */
/* 0x000fe80000004800 */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ LDS R24, [R4.X4+0x4] ; /* 0x0000040004187984 */
/* 0x000e620000004800 */
/*0770*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x001fe200000001ff */
/*0780*/ FADD R28, R24, R27 ; /* 0x0000001b181c7221 */
/* 0x022fc40000000000 */
/*0790*/ LDS R27, [R6.X4+0x4] ; /* 0x00000400061b7984 */
/* 0x000fe40000004800 */
/*07a0*/ FADD R21, R28, R21 ; /* 0x000000151c157221 */
/* 0x000fe40000000000 */
/*07b0*/ LDS R28, [R5.X4+0x4] ; /* 0x00000400051c7984 */
/* 0x000fe40000004800 */
/*07c0*/ FADD R21, R21, R20 ; /* 0x0000001415157221 */
/* 0x000fe20000000000 */
/*07d0*/ IADD3 R20, R2, UR7, RZ ; /* 0x0000000702147c10 */
/* 0x000fc6000fffe0ff */
/*07e0*/ FADD R26, R21, R26 ; /* 0x0000001a151a7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R26, R26, R29 ; /* 0x0000001d1a1a7221 */
/* 0x000fe40000000000 */
/*0800*/ IMAD.WIDE R20, R20, R25, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fe200078e0219 */
/*0810*/ LDS R29, [R4.X4] ; /* 0x00000000041d7984 */
/* 0x000fe60000004800 */
/*0820*/ FMUL R23, R26, 0.80000001192092895508 ; /* 0x3f4ccccd1a177820 */
/* 0x000fe40000400000 */
/*0830*/ LDS R26, [R4.X4+0x8] ; /* 0x00000800041a7984 */
/* 0x000fe80000004800 */
/*0840*/ STG.E [R20.64+0x4], R23 ; /* 0x0000041714007986 */
/* 0x0001e2000c10190a */
/*0850*/ ULEA UR7, UR4, UR7, 0x1 ; /* 0x0000000704077291 */
/* 0x000fcc000f8e083f */
/*0860*/ MOV R17, UR7 ; /* 0x0000000700117c02 */
/* 0x000fe40008000f00 */
/*0870*/ @!P2 IADD3 R14, R7, UR7, RZ ; /* 0x00000007070eac10 */
/* 0x000fe4000fffe0ff */
/*0880*/ @P1 IADD3 R18, R10, UR7, RZ ; /* 0x000000070a121c10 */
/* 0x000fe2000fffe0ff */
/*0890*/ IMAD.WIDE R16, R17, 0x4, R12 ; /* 0x0000000411107825 */
/* 0x000fe200078e020c */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08b0*/ @!P3 IADD3 R20, R8, UR7, RZ ; /* 0x000000070814bc10 */
/* 0x001fe4000fffe0ff */
/*08c0*/ @P0 IADD3 R22, R9, UR7, RZ ; /* 0x0000000709160c10 */
/* 0x000fe2000fffe0ff */
/*08d0*/ @!P2 IMAD.WIDE R14, R14, R25, c[0x0][0x168] ; /* 0x00005a000e0ea625 */
/* 0x000fc800078e0219 */
/*08e0*/ @P1 IMAD.WIDE R18, R18, R25, c[0x0][0x168] ; /* 0x00005a0012121625 */
/* 0x000fc800078e0219 */
/*08f0*/ @!P3 IMAD.WIDE R20, R20, R25, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x000fc800078e0219 */
/*0900*/ @P0 IMAD.WIDE R22, R22, R25, c[0x0][0x168] ; /* 0x00005a0016160625 */
/* 0x000fe200078e0219 */
/*0910*/ LDG.E R17, [R16.64+0x4] ; /* 0x0000040a10117981 */
/* 0x000ea8000c1e1900 */
/*0920*/ @!P2 LDG.E R14, [R14.64] ; /* 0x0000000a0e0ea981 */
/* 0x0000e8000c1e1900 */
/*0930*/ @P1 LDG.E R19, [R18.64+0x4] ; /* 0x0000040a12131981 */
/* 0x000f28000c1e1900 */
/*0940*/ @P0 LDG.E R22, [R22.64+0x4] ; /* 0x0000040a16160981 */
/* 0x000f28000c1e1900 */
/*0950*/ @!P3 LDG.E R15, [R20.64+0x4] ; /* 0x0000040a140fb981 */
/* 0x001f22000c1e1900 */
/*0960*/ UIADD3 UR5, UR5, -0x2, URZ ; /* 0xfffffffe05057890 */
/* 0x000fcc000fffe03f */
/*0970*/ ISETP.NE.AND P4, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf85270 */
/*0980*/ UIADD3 UR6, UR6, 0x2, URZ ; /* 0x0000000206067890 */
/* 0x000fe2000fffe03f */
/*0990*/ STS [R4.X4+0x4], R17 ; /* 0x0000041104007388 */
/* 0x004fe80000004800 */
/*09a0*/ @!P2 STS [R3.X4], R14 ; /* 0x0000000e0300a388 */
/* 0x0081e80000004800 */
/*09b0*/ @P1 STS [R4.X4+0x8], R19 ; /* 0x0000081304001388 */
/* 0x010fe80000004800 */
/*09c0*/ @!P3 STS [R0.X4], R15 ; /* 0x0000000f0000b388 */
/* 0x0003e80000004800 */
/*09d0*/ @P0 STS [R5.X4+0x4], R22 ; /* 0x0000041605000388 */
/* 0x000fe80000004800 */
/*09e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09f0*/ LDS R16, [R4.X4+0x4] ; /* 0x0000040004107984 */
/* 0x000ea20000004800 */
/*0a00*/ IADD3 R14, R2, UR9, RZ ; /* 0x00000009020e7c10 */
/* 0x001fc6000fffe0ff */
/*0a10*/ LDS R21, [R4.X4] ; /* 0x0000000004157984 */
/* 0x0000e40000004800 */
/*0a20*/ IMAD.WIDE R14, R14, R25, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x002fe400078e0219 */
/*0a30*/ LDS R20, [R4.X4+0x8] ; /* 0x0000080004147984 */
/* 0x0000640000004800 */
/*0a40*/ FADD R18, R16, R11 ; /* 0x0000000b10127221 */
/* 0x004fc80000000000 */
/*0a50*/ FADD R29, R29, R18 ; /* 0x000000121d1d7221 */
/* 0x000fc80000000000 */
/*0a60*/ FADD R18, R26, R29 ; /* 0x0000001d1a127221 */
/* 0x000fe40000000000 */
/*0a70*/ LDS R26, [R6.X4+0x4] ; /* 0x00000400061a7984 */
/* 0x0000a40000004800 */
/*0a80*/ FADD R27, R27, R18 ; /* 0x000000121b1b7221 */
/* 0x000fe40000000000 */
/*0a90*/ LDS R29, [R5.X4+0x4] ; /* 0x00000400051d7984 */
/* 0x0001240000004800 */
/*0aa0*/ FADD R27, R28, R27 ; /* 0x0000001b1c1b7221 */
/* 0x000fc80000000000 */
/*0ab0*/ FMUL R17, R27, 0.80000001192092895508 ; /* 0x3f4ccccd1b117820 */
/* 0x000fe20000400000 */
/*0ac0*/ MOV R27, R24 ; /* 0x00000018001b7202 */
/* 0x000fc80000000f00 */
/*0ad0*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0001e2000c10190a */
/*0ae0*/ MOV R11, R16 ; /* 0x00000010000b7202 */
/* 0x000fc60000000f00 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ @P4 BRA 0x5b0 ; /* 0xfffffaa000004947 */
/* 0x00afea000383ffff */
/*0b10*/ ISETP.NE.AND P4, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fda000bf85270 */
/*0b20*/ @!P4 EXIT ; /* 0x000000000000c94d */
/* 0x000fea0003800000 */
/*0b30*/ UIMAD UR6, UR4, UR6, URZ ; /* 0x00000006040672a4 */
/* 0x000fcc000f8e023f */
/*0b40*/ MOV R11, UR6 ; /* 0x00000006000b7c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.U32 R15, RZ, RZ, UR6 ; /* 0x00000006ff0f7e24 */
/* 0x001fe2000f8e00ff */
/*0b60*/ MOV R17, UR6 ; /* 0x0000000600117c02 */
/* 0x000fe40008000f00 */
/*0b70*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe20008000f00 */
/*0b80*/ IMAD.WIDE R14, R15, 0x4, R12 ; /* 0x000000040f0e7825 */
/* 0x000fe200078e020c */
/*0b90*/ @!P2 IADD3 R6, R7, UR6, RZ ; /* 0x000000060706ac10 */
/* 0x000fe4000fffe0ff */
/*0ba0*/ @P1 IADD3 R10, R10, 0x1, R11 ; /* 0x000000010a0a1810 */
/* 0x000fe40007ffe00b */
/*0bb0*/ @!P3 IADD3 R8, R8, 0x1, R17 ; /* 0x000000010808b810 */
/* 0x000fe20007ffe011 */
/*0bc0*/ @!P2 IMAD.WIDE R12, R6, R25.reuse, c[0x0][0x168] ; /* 0x00005a00060ca625 */
/* 0x080fe200078e0219 */
/*0bd0*/ @P0 IADD3 R16, R9, 0x1, R16 ; /* 0x0000000109100810 */
/* 0x000fe20007ffe010 */
/*0be0*/ LDG.E R15, [R14.64+0x4] ; /* 0x0000040a0e0f7981 */
/* 0x010f24000c1e1900 */
/*0bf0*/ @P1 IMAD.WIDE R6, R10, R25, c[0x0][0x168] ; /* 0x00005a000a061625 */
/* 0x000fc400078e0219 */
/*0c00*/ @!P2 LDG.E R12, [R12.64] ; /* 0x0000000a0c0ca981 */
/* 0x0080e4000c1e1900 */
/*0c10*/ @!P3 IMAD.WIDE R8, R8, R25.reuse, c[0x0][0x168] ; /* 0x00005a000808b625 */
/* 0x080fe400078e0219 */
/*0c20*/ @P1 LDG.E R7, [R6.64] ; /* 0x0000000a06071981 */
/* 0x004ea4000c1e1900 */
/*0c30*/ @P0 IMAD.WIDE R10, R16, R25, c[0x0][0x168] ; /* 0x00005a00100a0625 */
/* 0x000fe400078e0219 */
/*0c40*/ @!P3 LDG.E R9, [R8.64] ; /* 0x0000000a0809b981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ @P0 LDG.E R10, [R10.64] ; /* 0x0000000a0a0a0981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ MOV R13, UR4 ; /* 0x00000004000d7c02 */
/* 0x001fc80008000f00 */
/*0c70*/ IADD3 R2, R2, UR6, -R13 ; /* 0x0000000602027c10 */
/* 0x000fc8000fffe80d */
/*0c80*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ STS [R4.X4+0x4], R15 ; /* 0x0000040f04007388 */
/* 0x010fe80000004800 */
/*0ca0*/ @!P2 STS [R3.X4], R12 ; /* 0x0000000c0300a388 */
/* 0x0081e80000004800 */
/*0cb0*/ @P1 STS [R4.X4+0x8], R7 ; /* 0x0000080704001388 */
/* 0x004fe80000004800 */
/*0cc0*/ @!P3 STS [R0.X4], R9 ; /* 0x000000090000b388 */
/* 0x000fe80000004800 */
/*0cd0*/ @P0 STS [R5.X4+0x4], R10 ; /* 0x0000040a05000388 */
/* 0x000fe80000004800 */
/*0ce0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0cf0*/ LDS R14, [R4.X4+0x4] ; /* 0x00000400040e7984 */
/* 0x000e620000004800 */
/*0d00*/ IMAD.WIDE R2, R2, R25, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fc800078e0219 */
/*0d10*/ FADD R14, R14, R27 ; /* 0x0000001b0e0e7221 */
/* 0x022fc80000000000 */
/*0d20*/ FADD R21, R14, R21 ; /* 0x000000150e157221 */
/* 0x000fc80000000000 */
/*0d30*/ FADD R21, R21, R20 ; /* 0x0000001415157221 */
/* 0x000fc80000000000 */
/*0d40*/ FADD R26, R21, R26 ; /* 0x0000001a151a7221 */
/* 0x000fc80000000000 */
/*0d50*/ FADD R26, R26, R29 ; /* 0x0000001d1a1a7221 */
/* 0x000fc80000000000 */
/*0d60*/ FMUL R5, R26, 0.80000001192092895508 ; /* 0x3f4ccccd1a057820 */
/* 0x000fca0000400000 */
/*0d70*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c10190a */
/*0d80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0d90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0da0*/ BRA 0xda0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernalPfS_ii
.globl _Z6kernalPfS_ii
.p2align 8
.type _Z6kernalPfS_ii,@function
_Z6kernalPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v10, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, 1, v6
v_add_nc_u32_e32 v7, 1, v10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s4, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s11, s15, s4
v_add_nc_u32_e32 v2, s14, v11
v_add_nc_u32_e32 v8, s11, v7
s_add_i32 s2, s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v2, v8
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_20
v_mul_lo_u32 v9, v8, s8
v_mad_u64_u32 v[0:1], null, s8, s8, v[2:3]
s_load_b64 s[6:7], s[0:1], 0x8
s_add_i32 s12, s3, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v14, s12, v7
v_add_nc_u32_e32 v12, v9, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v9, v0
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v5, v[12:13], off
v_lshl_add_u32 v3, v14, 2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v11, 2, v3
s_waitcnt vmcnt(1)
ds_store_b32 v4, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_3
v_add3_u32 v12, v9, v0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v1, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s5, s8, -2
v_cmp_eq_u32_e64 s2, s3, v11
v_cmp_eq_u32_e64 s3, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s2, s3
s_and_saveexec_b32 s3, s9
s_cbranch_execz .LBB0_5
v_add3_u32 v1, v9, v0, 1
v_lshlrev_b32_e32 v12, 2, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s6, v1
v_add_co_ci_u32_e64 v2, s2, s7, v2, s2
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v11
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, 0, v2, v12
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1 offset:4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e64 s2, 0, v10
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[1:2], null, s11, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s3, s6, v1
v_add_co_ci_u32_e64 v2, s3, s7, v2, s3
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v11, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
v_cmp_eq_u32_e64 s3, s4, v7
v_cmp_eq_u32_e64 s4, s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s10, s3, s4
s_and_saveexec_b32 s4, s10
s_cbranch_execz .LBB0_9
v_add3_u32 v0, v9, s8, v0
v_lshlrev_b32_e32 v2, 2, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s3, s6, v0
v_add_co_ci_u32_e64 v1, s3, s7, v1, s3
global_load_b32 v0, v[0:1], off
v_add_nc_u32_e32 v1, 2, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, s12, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v1, 0, v1, v2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v15, 2, v10
v_add_nc_u32_e32 v0, v14, v6
v_add_nc_u32_e32 v1, v14, v11
v_mad_u32_u24 v8, s12, v10, v11
s_load_b32 s3, s[0:1], 0x14
v_mad_u32_u24 v9, s12, v15, v11
v_lshl_add_u32 v2, v0, 2, 0
v_lshl_add_u32 v7, v1, 2, 0
v_lshl_add_u32 v8, v8, 2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_lshl_add_u32 v9, v9, 2, 0
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v2 offset1:2
ds_load_b32 v19, v7
ds_load_b32 v13, v8
ds_load_b32 v12, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s3, 3
s_cbranch_scc1 .LBB0_20
s_lshl_b32 s4, s8, 1
v_lshl_add_u32 v11, v11, 2, 0
s_add_i32 s13, s11, s4
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v18, s13, v10
v_add3_u32 v10, s11, s8, v10
v_lshlrev_b32_e32 v14, 2, v14
v_mul_u32_u24_e32 v15, s12, v15
s_mul_i32 s0, s8, s13
v_add_nc_u32_e32 v20, 2, v18
v_mad_u64_u32 v[16:17], null, s8, v10, s[8:9]
v_mul_lo_u32 v17, s8, v18
v_add_nc_u32_e32 v10, 8, v2
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v18, s8, v20
v_add3_u32 v14, v11, v14, 4
v_lshl_add_u32 v15, v15, 2, v11
s_add_i32 s1, s3, -2
v_add3_u32 v16, v6, v16, 1
s_mul_i32 s3, s8, s8
v_add3_u32 v17, v17, s8, v6
v_add3_u32 v18, v6, v18, 1
v_add3_u32 v6, v6, s0, 1
s_branch .LBB0_12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v19, v7
v_add_nc_u32_e32 v17, s3, v17
s_add_i32 s1, s1, -1
v_add_nc_u32_e32 v18, s3, v18
s_cmp_lg_u32 s1, 0
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v5, v5, v19 :: v_dual_add_nc_u32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v0, v5 :: v_dual_add_nc_u32 v0, s14, v16
v_dual_add_f32 v5, v1, v5 :: v_dual_add_nc_u32 v16, s3, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_f32_e32 v5, v13, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[21:22], 2, v[0:1]
v_add_f32_e32 v5, v12, v5
ds_load_b32 v0, v2
ds_load_b32 v1, v10
ds_load_b32 v13, v8
ds_load_b32 v12, v9
v_add_co_u32 v21, s0, s4, v21
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v22, s0, s5, v22, s0
v_mul_f32_e32 v5, 0x3f4ccccd, v5
global_store_b32 v[21:22], v5, off
v_mov_b32_e32 v5, v20
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_20
.LBB0_12:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v20, s14, v17, 1
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[20:21], 2, v[20:21]
v_add_co_u32 v20, s0, s6, v20
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v21, s0, s7, v21, s0
global_load_b32 v21, v[20:21], off
v_mov_b32_e32 v20, v19
s_waitcnt vmcnt(0)
ds_store_b32 v4, v21
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v21, s14, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v19
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s9
s_cbranch_execz .LBB0_16
v_add3_u32 v21, s14, v17, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v14, v19
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_18
v_add_nc_u32_e32 v21, s14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v19
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s10
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v21, s14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v22, 31, v21
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s0, s6, v21
v_add_co_ci_u32_e64 v22, s0, s7, v22, s0
global_load_b32 v19, v[21:22], off
s_waitcnt vmcnt(0)
ds_store_b32 v15, v19
s_branch .LBB0_11
.LBB0_20:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernalPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernalPfS_ii, .Lfunc_end0-_Z6kernalPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernalPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernalPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define ALLOC_SIZE 1024
#define ACCESS_DIR 1
__global__ void access_from_min_into_max_kernel(int *min, int *max) {
#ifdef R
volatile int i = min[max-min];
#elif W
min[max-min] = 42;
#endif
}
__global__ void access_from_max_into_min_kernel(int *min, int *max) {
#ifdef R
volatile int i = max[-1*(max-(min+(ALLOC_SIZE-1)))];
#elif W
max[-1*(max-(min+(ALLOC_SIZE-1)))] = 42;
#endif
}
int main(int argc, char** argv) {
int *x, *y, *min, *max;
cudaMalloc((void**)&x, ALLOC_SIZE*sizeof(int));
cudaMalloc((void**)&y, ALLOC_SIZE*sizeof(int));
min = (x < y) ? x : y;
max = (x < y) ? y : x;
if (ACCESS_DIR == 0)
access_from_min_into_max_kernel<<<1,1>>>(min,max);
else
access_from_max_into_min_kernel<<<1,1>>>(min,max);
cudaFree(x);
cudaFree(y);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z31access_from_max_into_min_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z31access_from_min_into_max_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define ALLOC_SIZE 1024
#define ACCESS_DIR 1
__global__ void access_from_min_into_max_kernel(int *min, int *max) {
#ifdef R
volatile int i = min[max-min];
#elif W
min[max-min] = 42;
#endif
}
__global__ void access_from_max_into_min_kernel(int *min, int *max) {
#ifdef R
volatile int i = max[-1*(max-(min+(ALLOC_SIZE-1)))];
#elif W
max[-1*(max-(min+(ALLOC_SIZE-1)))] = 42;
#endif
}
int main(int argc, char** argv) {
int *x, *y, *min, *max;
cudaMalloc((void**)&x, ALLOC_SIZE*sizeof(int));
cudaMalloc((void**)&y, ALLOC_SIZE*sizeof(int));
min = (x < y) ? x : y;
max = (x < y) ? y : x;
if (ACCESS_DIR == 0)
access_from_min_into_max_kernel<<<1,1>>>(min,max);
else
access_from_max_into_min_kernel<<<1,1>>>(min,max);
cudaFree(x);
cudaFree(y);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000d411a_00000000-6_two_array_global.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
.type _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_, @function
_Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z31access_from_min_into_max_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_, .-_Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
.globl _Z31access_from_min_into_max_kernelPiS_
.type _Z31access_from_min_into_max_kernelPiS_, @function
_Z31access_from_min_into_max_kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z31access_from_min_into_max_kernelPiS_, .-_Z31access_from_min_into_max_kernelPiS_
.globl _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
.type _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_, @function
_Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z31access_from_max_into_min_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_, .-_Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.type _Z31access_from_max_into_min_kernelPiS_, @function
_Z31access_from_max_into_min_kernelPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z31access_from_max_into_min_kernelPiS_, .-_Z31access_from_max_into_min_kernelPiS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movq (%rsp), %rbx
movq 8(%rsp), %rbp
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
cmpq %rbp, %rbx
movq %rbp, %rsi
cmovnb %rbx, %rsi
movq %rbp, %rdi
cmovbe %rbx, %rdi
call _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31access_from_max_into_min_kernelPiS_"
.align 8
.LC1:
.string "_Z31access_from_min_into_max_kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31access_from_max_into_min_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z31access_from_min_into_max_kernelPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define ALLOC_SIZE 1024
#define ACCESS_DIR 1
__global__ void access_from_min_into_max_kernel(int *min, int *max) {
#ifdef R
volatile int i = min[max-min];
#elif W
min[max-min] = 42;
#endif
}
__global__ void access_from_max_into_min_kernel(int *min, int *max) {
#ifdef R
volatile int i = max[-1*(max-(min+(ALLOC_SIZE-1)))];
#elif W
max[-1*(max-(min+(ALLOC_SIZE-1)))] = 42;
#endif
}
int main(int argc, char** argv) {
int *x, *y, *min, *max;
cudaMalloc((void**)&x, ALLOC_SIZE*sizeof(int));
cudaMalloc((void**)&y, ALLOC_SIZE*sizeof(int));
min = (x < y) ? x : y;
max = (x < y) ? y : x;
if (ACCESS_DIR == 0)
access_from_min_into_max_kernel<<<1,1>>>(min,max);
else
access_from_max_into_min_kernel<<<1,1>>>(min,max);
cudaFree(x);
cudaFree(y);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ALLOC_SIZE 1024
#define ACCESS_DIR 1
__global__ void access_from_min_into_max_kernel(int *min, int *max) {
#ifdef R
volatile int i = min[max-min];
#elif W
min[max-min] = 42;
#endif
}
__global__ void access_from_max_into_min_kernel(int *min, int *max) {
#ifdef R
volatile int i = max[-1*(max-(min+(ALLOC_SIZE-1)))];
#elif W
max[-1*(max-(min+(ALLOC_SIZE-1)))] = 42;
#endif
}
int main(int argc, char** argv) {
int *x, *y, *min, *max;
hipMalloc((void**)&x, ALLOC_SIZE*sizeof(int));
hipMalloc((void**)&y, ALLOC_SIZE*sizeof(int));
min = (x < y) ? x : y;
max = (x < y) ? y : x;
if (ACCESS_DIR == 0)
access_from_min_into_max_kernel<<<1,1>>>(min,max);
else
access_from_max_into_min_kernel<<<1,1>>>(min,max);
hipFree(x);
hipFree(y);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ALLOC_SIZE 1024
#define ACCESS_DIR 1
__global__ void access_from_min_into_max_kernel(int *min, int *max) {
#ifdef R
volatile int i = min[max-min];
#elif W
min[max-min] = 42;
#endif
}
__global__ void access_from_max_into_min_kernel(int *min, int *max) {
#ifdef R
volatile int i = max[-1*(max-(min+(ALLOC_SIZE-1)))];
#elif W
max[-1*(max-(min+(ALLOC_SIZE-1)))] = 42;
#endif
}
int main(int argc, char** argv) {
int *x, *y, *min, *max;
hipMalloc((void**)&x, ALLOC_SIZE*sizeof(int));
hipMalloc((void**)&y, ALLOC_SIZE*sizeof(int));
min = (x < y) ? x : y;
max = (x < y) ? y : x;
if (ACCESS_DIR == 0)
access_from_min_into_max_kernel<<<1,1>>>(min,max);
else
access_from_max_into_min_kernel<<<1,1>>>(min,max);
hipFree(x);
hipFree(y);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31access_from_min_into_max_kernelPiS_
.globl _Z31access_from_min_into_max_kernelPiS_
.p2align 8
.type _Z31access_from_min_into_max_kernelPiS_,@function
_Z31access_from_min_into_max_kernelPiS_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31access_from_min_into_max_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31access_from_min_into_max_kernelPiS_, .Lfunc_end0-_Z31access_from_min_into_max_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z31access_from_max_into_min_kernelPiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.p2align 8
.type _Z31access_from_max_into_min_kernelPiS_,@function
_Z31access_from_max_into_min_kernelPiS_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31access_from_max_into_min_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z31access_from_max_into_min_kernelPiS_, .Lfunc_end1-_Z31access_from_max_into_min_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31access_from_min_into_max_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z31access_from_min_into_max_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31access_from_max_into_min_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z31access_from_max_into_min_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ALLOC_SIZE 1024
#define ACCESS_DIR 1
__global__ void access_from_min_into_max_kernel(int *min, int *max) {
#ifdef R
volatile int i = min[max-min];
#elif W
min[max-min] = 42;
#endif
}
__global__ void access_from_max_into_min_kernel(int *min, int *max) {
#ifdef R
volatile int i = max[-1*(max-(min+(ALLOC_SIZE-1)))];
#elif W
max[-1*(max-(min+(ALLOC_SIZE-1)))] = 42;
#endif
}
int main(int argc, char** argv) {
int *x, *y, *min, *max;
hipMalloc((void**)&x, ALLOC_SIZE*sizeof(int));
hipMalloc((void**)&y, ALLOC_SIZE*sizeof(int));
min = (x < y) ? x : y;
max = (x < y) ? y : x;
if (ACCESS_DIR == 0)
access_from_min_into_max_kernel<<<1,1>>>(min,max);
else
access_from_max_into_min_kernel<<<1,1>>>(min,max);
hipFree(x);
hipFree(y);
hipDeviceReset();
return 0;
} | .text
.file "two_array_global.hip"
.globl _Z46__device_stub__access_from_min_into_max_kernelPiS_ # -- Begin function _Z46__device_stub__access_from_min_into_max_kernelPiS_
.p2align 4, 0x90
.type _Z46__device_stub__access_from_min_into_max_kernelPiS_,@function
_Z46__device_stub__access_from_min_into_max_kernelPiS_: # @_Z46__device_stub__access_from_min_into_max_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z31access_from_min_into_max_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z46__device_stub__access_from_min_into_max_kernelPiS_, .Lfunc_end0-_Z46__device_stub__access_from_min_into_max_kernelPiS_
.cfi_endproc
# -- End function
.globl _Z46__device_stub__access_from_max_into_min_kernelPiS_ # -- Begin function _Z46__device_stub__access_from_max_into_min_kernelPiS_
.p2align 4, 0x90
.type _Z46__device_stub__access_from_max_into_min_kernelPiS_,@function
_Z46__device_stub__access_from_max_into_min_kernelPiS_: # @_Z46__device_stub__access_from_max_into_min_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z31access_from_max_into_min_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z46__device_stub__access_from_max_into_min_kernelPiS_, .Lfunc_end1-_Z46__device_stub__access_from_max_into_min_kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rbx
movq (%rsp), %r14
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
cmpq %r14, %rbx
movq %rbx, %rax
cmovbq %r14, %rax
cmovbq %rbx, %r14
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31access_from_max_into_min_kernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31access_from_min_into_max_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31access_from_max_into_min_kernelPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31access_from_min_into_max_kernelPiS_,@object # @_Z31access_from_min_into_max_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z31access_from_min_into_max_kernelPiS_
.p2align 3, 0x0
_Z31access_from_min_into_max_kernelPiS_:
.quad _Z46__device_stub__access_from_min_into_max_kernelPiS_
.size _Z31access_from_min_into_max_kernelPiS_, 8
.type _Z31access_from_max_into_min_kernelPiS_,@object # @_Z31access_from_max_into_min_kernelPiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.p2align 3, 0x0
_Z31access_from_max_into_min_kernelPiS_:
.quad _Z46__device_stub__access_from_max_into_min_kernelPiS_
.size _Z31access_from_max_into_min_kernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31access_from_min_into_max_kernelPiS_"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z31access_from_max_into_min_kernelPiS_"
.size .L__unnamed_2, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__access_from_min_into_max_kernelPiS_
.addrsig_sym _Z46__device_stub__access_from_max_into_min_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31access_from_min_into_max_kernelPiS_
.addrsig_sym _Z31access_from_max_into_min_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31access_from_max_into_min_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z31access_from_min_into_max_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31access_from_min_into_max_kernelPiS_
.globl _Z31access_from_min_into_max_kernelPiS_
.p2align 8
.type _Z31access_from_min_into_max_kernelPiS_,@function
_Z31access_from_min_into_max_kernelPiS_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31access_from_min_into_max_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31access_from_min_into_max_kernelPiS_, .Lfunc_end0-_Z31access_from_min_into_max_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z31access_from_max_into_min_kernelPiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.p2align 8
.type _Z31access_from_max_into_min_kernelPiS_,@function
_Z31access_from_max_into_min_kernelPiS_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31access_from_max_into_min_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z31access_from_max_into_min_kernelPiS_, .Lfunc_end1-_Z31access_from_max_into_min_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31access_from_min_into_max_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z31access_from_min_into_max_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31access_from_max_into_min_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z31access_from_max_into_min_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d411a_00000000-6_two_array_global.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
.type _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_, @function
_Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z31access_from_min_into_max_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_, .-_Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
.globl _Z31access_from_min_into_max_kernelPiS_
.type _Z31access_from_min_into_max_kernelPiS_, @function
_Z31access_from_min_into_max_kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z31access_from_min_into_max_kernelPiS_, .-_Z31access_from_min_into_max_kernelPiS_
.globl _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
.type _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_, @function
_Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z31access_from_max_into_min_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_, .-_Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.type _Z31access_from_max_into_min_kernelPiS_, @function
_Z31access_from_max_into_min_kernelPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z31access_from_max_into_min_kernelPiS_, .-_Z31access_from_max_into_min_kernelPiS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movq (%rsp), %rbx
movq 8(%rsp), %rbp
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
cmpq %rbp, %rbx
movq %rbp, %rsi
cmovnb %rbx, %rsi
movq %rbp, %rdi
cmovbe %rbx, %rdi
call _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31access_from_max_into_min_kernelPiS_"
.align 8
.LC1:
.string "_Z31access_from_min_into_max_kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31access_from_max_into_min_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z31access_from_min_into_max_kernelPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "two_array_global.hip"
.globl _Z46__device_stub__access_from_min_into_max_kernelPiS_ # -- Begin function _Z46__device_stub__access_from_min_into_max_kernelPiS_
.p2align 4, 0x90
.type _Z46__device_stub__access_from_min_into_max_kernelPiS_,@function
_Z46__device_stub__access_from_min_into_max_kernelPiS_: # @_Z46__device_stub__access_from_min_into_max_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z31access_from_min_into_max_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z46__device_stub__access_from_min_into_max_kernelPiS_, .Lfunc_end0-_Z46__device_stub__access_from_min_into_max_kernelPiS_
.cfi_endproc
# -- End function
.globl _Z46__device_stub__access_from_max_into_min_kernelPiS_ # -- Begin function _Z46__device_stub__access_from_max_into_min_kernelPiS_
.p2align 4, 0x90
.type _Z46__device_stub__access_from_max_into_min_kernelPiS_,@function
_Z46__device_stub__access_from_max_into_min_kernelPiS_: # @_Z46__device_stub__access_from_max_into_min_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z31access_from_max_into_min_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z46__device_stub__access_from_max_into_min_kernelPiS_, .Lfunc_end1-_Z46__device_stub__access_from_max_into_min_kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rbx
movq (%rsp), %r14
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
cmpq %r14, %rbx
movq %rbx, %rax
cmovbq %r14, %rax
cmovbq %rbx, %r14
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31access_from_max_into_min_kernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31access_from_min_into_max_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31access_from_max_into_min_kernelPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31access_from_min_into_max_kernelPiS_,@object # @_Z31access_from_min_into_max_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z31access_from_min_into_max_kernelPiS_
.p2align 3, 0x0
_Z31access_from_min_into_max_kernelPiS_:
.quad _Z46__device_stub__access_from_min_into_max_kernelPiS_
.size _Z31access_from_min_into_max_kernelPiS_, 8
.type _Z31access_from_max_into_min_kernelPiS_,@object # @_Z31access_from_max_into_min_kernelPiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.p2align 3, 0x0
_Z31access_from_max_into_min_kernelPiS_:
.quad _Z46__device_stub__access_from_max_into_min_kernelPiS_
.size _Z31access_from_max_into_min_kernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31access_from_min_into_max_kernelPiS_"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z31access_from_max_into_min_kernelPiS_"
.size .L__unnamed_2, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__access_from_min_into_max_kernelPiS_
.addrsig_sym _Z46__device_stub__access_from_max_into_min_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31access_from_min_into_max_kernelPiS_
.addrsig_sym _Z31access_from_max_into_min_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ShortestPath1(float *Arr1,float *Arr2,int N,int rows, int rank){ //rowNum is number of rows for each process (full assigned to process)
//Arr1 input array,Holds of (u,v) //Arr2 output array
int k;
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int offset=rows*rank;
int index=row*N+col;
int index_ik,index_kj;
Arr2[index]=Arr1[index];
for(k=rank*rows; k<((rank+1)*rows); k++){
index_ik = row*N+k;
index_kj = (k-offset)*N+col;
if(Arr1[index]>(Arr1[index_ik]+Arr1[index_kj])){
Arr2[index]=Arr1[index_ik]+Arr1[index_kj];
}
__syncthreads();
}
} | code for sm_80
Function : _Z13ShortestPath1PfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R10, R10, c[0x0][0x4], R3 ; /* 0x000001000a0a7a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R6, R8, c[0x0][0x0], R7 ; /* 0x0000000008067a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R2, R10, c[0x0][0x170], R6 ; /* 0x00005c000a027a24 */
/* 0x000fc800078e0206 */
/*00a0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0209 */
/*00b0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R14, c[0x0][0x174] ; /* 0x00005d00000e7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R13, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0d7a24 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R0, R13, c[0x0][0x174], RZ ; /* 0x00005d000d007a10 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fe20003f06270 */
/*0110*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0041d8000c101904 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ LOP3.LUT P1, R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe2000782c0ff */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x001fca00078e00ff */
/*0150*/ IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fe40003f06070 */
/*0170*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe20000000f00 */
/*0180*/ @!P1 BRA 0x300 ; /* 0x0000017000009947 */
/* 0x000ff40003800000 */
/*0190*/ IMAD R12, R10, c[0x0][0x170], R11 ; /* 0x00005c000a0c7a24 */
/* 0x000fe200078e020b */
/*01a0*/ MOV R18, R6 ; /* 0x0000000600127202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000e */
/*01c0*/ IMAD.WIDE R12, R12, R9, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0209 */
/*01d0*/ IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000d */
/*01e0*/ MOV R14, R12 ; /* 0x0000000c000e7202 */
/* 0x000fc60000000f00 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R15, R19 ; /* 0x00000013000f7202 */
/* 0x000fe20000000f00 */
/*0210*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.WIDE R12, R18, R9, c[0x0][0x160] ; /* 0x00005800120c7625 */
/* 0x000fc600078e0209 */
/*0230*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0250*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.NE.AND P2, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f45270 */
/*0270*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R18, R18, c[0x0][0x170], RZ ; /* 0x00005c0012127a10 */
/* 0x000fe20007ffe0ff */
/*0290*/ FADD R20, R12, R15 ; /* 0x0000000f0c147221 */
/* 0x009fca0000000000 */
/*02a0*/ FSETP.GT.AND P1, PT, R17, R20, PT ; /* 0x000000141100720b */
/* 0x004fda0003f24000 */
/*02b0*/ @P1 STG.E [R2.64], R20 ; /* 0x0000001402001986 */
/* 0x0001e8000c101904 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fca0007f3e0ff */
/*02e0*/ IMAD.X R19, RZ, RZ, R19, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0613 */
/*02f0*/ @P2 BRA 0x1f0 ; /* 0xfffffef000002947 */
/* 0x000fea000383ffff */
/*0300*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0310*/ IMAD R12, R10, c[0x0][0x170], R11 ; /* 0x00005c000a0c7a24 */
/* 0x000fe200078e020b */
/*0320*/ IADD3 R10, RZ, -c[0x0][0x178], RZ ; /* 0x80005e00ff0a7a10 */
/* 0x000fe20007ffe0ff */
/*0330*/ IMAD R14, R8, c[0x0][0x0], R7 ; /* 0x00000000080e7a24 */
/* 0x000fe200078e0207 */
/*0340*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0350*/ IMAD.WIDE R8, R12, R9, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e0209 */
/*0360*/ IMAD R7, R10, c[0x0][0x174], R11.reuse ; /* 0x00005d000a077a24 */
/* 0x100fe400078e020b */
/*0370*/ IMAD.IADD R10, R14, 0x1, -R11 ; /* 0x000000010e0a7824 */
/* 0x000fe400078e0a0b */
/*0380*/ IMAD R14, R7, c[0x0][0x170], R6 ; /* 0x00005c00070e7a24 */
/* 0x000fe200078e0206 */
/*0390*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*03b0*/ SHF.R.S32.HI R20, RZ, 0x1f, R10 ; /* 0x0000001fff147819 */
/* 0x001fe2000001140a */
/*03c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe400078e00ff */
/*03d0*/ MOV R19, 0x4 ; /* 0x0000000400137802 */
/* 0x000fe20000000f00 */
/*03e0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ IMAD.WIDE R12, R14, R19, c[0x0][0x160] ; /* 0x000058000e0c7625 */
/* 0x000fe200078e0213 */
/*0400*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea2000c1e1900 */
/*0420*/ SHF.L.U64.HI R21, R15, 0x2, R18 ; /* 0x000000020f157819 */
/* 0x000fe20000010212 */
/*0430*/ FADD R23, R8, R9 ; /* 0x0000000908177221 */
/* 0x004fca0000000000 */
/*0440*/ FSETP.GT.AND P0, PT, R16, R23, PT ; /* 0x000000171000720b */
/* 0x008fda0003f04000 */
/*0450*/ @P0 STG.E [R2.64], R23 ; /* 0x0000001702000986 */
/* 0x0001e8000c101904 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0470*/ LEA R9, P1, -R15, R10, 0x2 ; /* 0x0000000a0f097211 */
/* 0x000fe200078211ff */
/*0480*/ IMAD.WIDE R16, R19, c[0x0][0x170], R12 ; /* 0x00005c0013107a25 */
/* 0x000fc800078e020c */
/*0490*/ IMAD.X R21, R20, 0x1, ~R21, P1 ; /* 0x0000000114157824 */
/* 0x000fe200008e0e15 */
/*04a0*/ LEA R8, P1, R9, R6, 0x2 ; /* 0x0000000609087211 */
/* 0x000fc800078210ff */
/*04b0*/ LEA.HI.X R9, R9, R7, R21, 0x2, P1 ; /* 0x0000000709097211 */
/* 0x000fe200008f1415 */
/*04c0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R13, [R6.64+0x4] ; /* 0x00000404060d7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ FADD R24, R12, R13 ; /* 0x0000000d0c187221 */
/* 0x004fca0000000000 */
/*0500*/ FSETP.GT.AND P0, PT, R21, R24, PT ; /* 0x000000181500720b */
/* 0x008fda0003f04000 */
/*0510*/ @P0 STG.E [R2.64], R24 ; /* 0x0000001802000986 */
/* 0x0003e8000c101904 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0530*/ IMAD.WIDE R12, R19, c[0x0][0x170], R16 ; /* 0x00005c00130c7a25 */
/* 0x000fca00078e0210 */
/*0540*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R22, [R6.64+0x8] ; /* 0x0000080406167981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD.WIDE R16, R19, c[0x0][0x170], R12 ; /* 0x00005c0013107a25 */
/* 0x000fc800078e020c */
/*0580*/ FADD R25, R21, R22 ; /* 0x0000001615197221 */
/* 0x004fca0000000000 */
/*0590*/ FSETP.GT.AND P0, PT, R23, R25, PT ; /* 0x000000191700720b */
/* 0x008fda0003f04000 */
/*05a0*/ @P0 STG.E [R2.64], R25 ; /* 0x0000001902000986 */
/* 0x0003e8000c101904 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R21, [R6.64+0xc] ; /* 0x00000c0406157981 */
/* 0x0000a8000c1e1900 */
/*05e0*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ee2000c1e1900 */
/*05f0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ IADD3 R15, P2, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007f5e0ff */
/*0610*/ IADD3 R6, P1, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x001fe20007f3e0ff */
/*0620*/ IMAD R14, R19, c[0x0][0x170], R14 ; /* 0x00005c00130e7a24 */
/* 0x000fe200078e020e */
/*0630*/ IADD3.X R18, RZ, R18, RZ, P2, !PT ; /* 0x00000012ff127210 */
/* 0x000fe400017fe4ff */
/*0640*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0650*/ FADD R21, R16, R21 ; /* 0x0000001510157221 */
/* 0x004fca0000000000 */
/*0660*/ FSETP.GT.AND P0, PT, R22, R21, PT ; /* 0x000000151600720b */
/* 0x008fda0003f04000 */
/*0670*/ @P0 STG.E [R2.64], R21 ; /* 0x0000001502000986 */
/* 0x0003e8000c101904 */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0690*/ ISETP.GE.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f06270 */
/*06a0*/ @!P0 BRA 0x3d0 ; /* 0xfffffd2000008947 */
/* 0x002fea000383ffff */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ShortestPath1(float *Arr1,float *Arr2,int N,int rows, int rank){ //rowNum is number of rows for each process (full assigned to process)
//Arr1 input array,Holds of (u,v) //Arr2 output array
int k;
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int offset=rows*rank;
int index=row*N+col;
int index_ik,index_kj;
Arr2[index]=Arr1[index];
for(k=rank*rows; k<((rank+1)*rows); k++){
index_ik = row*N+k;
index_kj = (k-offset)*N+col;
if(Arr1[index]>(Arr1[index_ik]+Arr1[index_kj])){
Arr2[index]=Arr1[index_ik]+Arr1[index_kj];
}
__syncthreads();
}
} | .file "tmpxft_00147626_00000000-6_ShortestPath1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii
.type _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii, @function
_Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13ShortestPath1PfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii, .-_Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii
.globl _Z13ShortestPath1PfS_iii
.type _Z13ShortestPath1PfS_iii, @function
_Z13ShortestPath1PfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13ShortestPath1PfS_iii, .-_Z13ShortestPath1PfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13ShortestPath1PfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13ShortestPath1PfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ShortestPath1(float *Arr1,float *Arr2,int N,int rows, int rank){ //rowNum is number of rows for each process (full assigned to process)
//Arr1 input array,Holds of (u,v) //Arr2 output array
int k;
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int offset=rows*rank;
int index=row*N+col;
int index_ik,index_kj;
Arr2[index]=Arr1[index];
for(k=rank*rows; k<((rank+1)*rows); k++){
index_ik = row*N+k;
index_kj = (k-offset)*N+col;
if(Arr1[index]>(Arr1[index_ik]+Arr1[index_kj])){
Arr2[index]=Arr1[index_ik]+Arr1[index_kj];
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ShortestPath1(float *Arr1,float *Arr2,int N,int rows, int rank){ //rowNum is number of rows for each process (full assigned to process)
//Arr1 input array,Holds of (u,v) //Arr2 output array
int k;
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int offset=rows*rank;
int index=row*N+col;
int index_ik,index_kj;
Arr2[index]=Arr1[index];
for(k=rank*rows; k<((rank+1)*rows); k++){
index_ik = row*N+k;
index_kj = (k-offset)*N+col;
if(Arr1[index]>(Arr1[index_ik]+Arr1[index_kj])){
Arr2[index]=Arr1[index_ik]+Arr1[index_kj];
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ShortestPath1(float *Arr1,float *Arr2,int N,int rows, int rank){ //rowNum is number of rows for each process (full assigned to process)
//Arr1 input array,Holds of (u,v) //Arr2 output array
int k;
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int offset=rows*rank;
int index=row*N+col;
int index_ik,index_kj;
Arr2[index]=Arr1[index];
for(k=rank*rows; k<((rank+1)*rows); k++){
index_ik = row*N+k;
index_kj = (k-offset)*N+col;
if(Arr1[index]>(Arr1[index_ik]+Arr1[index_kj])){
Arr2[index]=Arr1[index_ik]+Arr1[index_kj];
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13ShortestPath1PfS_iii
.globl _Z13ShortestPath1PfS_iii
.p2align 8
.type _Z13ShortestPath1PfS_iii,@function
_Z13ShortestPath1PfS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, s14, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
v_add_nc_u32_e32 v2, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s1, s3
s_add_i32 s1, s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v6, v[2:3], off
s_mul_i32 s1, s1, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s0, s1
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_5
v_add_nc_u32_e32 v6, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_nc_u32_e32 v0, s2, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s3, s3, -1
s_waitcnt_vscnt null, 0x0
s_cmp_lg_u32 s3, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[0:1]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v1, v[6:7], off
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[2:3], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v9, v1
s_cbranch_execz .LBB0_2
global_store_b32 v[4:5], v1, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13ShortestPath1PfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13ShortestPath1PfS_iii, .Lfunc_end0-_Z13ShortestPath1PfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13ShortestPath1PfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13ShortestPath1PfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ShortestPath1(float *Arr1,float *Arr2,int N,int rows, int rank){ //rowNum is number of rows for each process (full assigned to process)
//Arr1 input array,Holds of (u,v) //Arr2 output array
int k;
int col=blockIdx.x * blockDim.x + threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
int offset=rows*rank;
int index=row*N+col;
int index_ik,index_kj;
Arr2[index]=Arr1[index];
for(k=rank*rows; k<((rank+1)*rows); k++){
index_ik = row*N+k;
index_kj = (k-offset)*N+col;
if(Arr1[index]>(Arr1[index_ik]+Arr1[index_kj])){
Arr2[index]=Arr1[index_ik]+Arr1[index_kj];
}
__syncthreads();
}
} | .text
.file "ShortestPath1.hip"
.globl _Z28__device_stub__ShortestPath1PfS_iii # -- Begin function _Z28__device_stub__ShortestPath1PfS_iii
.p2align 4, 0x90
.type _Z28__device_stub__ShortestPath1PfS_iii,@function
_Z28__device_stub__ShortestPath1PfS_iii: # @_Z28__device_stub__ShortestPath1PfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13ShortestPath1PfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__ShortestPath1PfS_iii, .Lfunc_end0-_Z28__device_stub__ShortestPath1PfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13ShortestPath1PfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13ShortestPath1PfS_iii,@object # @_Z13ShortestPath1PfS_iii
.section .rodata,"a",@progbits
.globl _Z13ShortestPath1PfS_iii
.p2align 3, 0x0
_Z13ShortestPath1PfS_iii:
.quad _Z28__device_stub__ShortestPath1PfS_iii
.size _Z13ShortestPath1PfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13ShortestPath1PfS_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__ShortestPath1PfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13ShortestPath1PfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13ShortestPath1PfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R10, R10, c[0x0][0x4], R3 ; /* 0x000001000a0a7a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R6, R8, c[0x0][0x0], R7 ; /* 0x0000000008067a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R2, R10, c[0x0][0x170], R6 ; /* 0x00005c000a027a24 */
/* 0x000fc800078e0206 */
/*00a0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0209 */
/*00b0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R14, c[0x0][0x174] ; /* 0x00005d00000e7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R13, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0d7a24 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R0, R13, c[0x0][0x174], RZ ; /* 0x00005d000d007a10 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fe20003f06270 */
/*0110*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0041d8000c101904 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ LOP3.LUT P1, R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe2000782c0ff */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x001fca00078e00ff */
/*0150*/ IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fe40003f06070 */
/*0170*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe20000000f00 */
/*0180*/ @!P1 BRA 0x300 ; /* 0x0000017000009947 */
/* 0x000ff40003800000 */
/*0190*/ IMAD R12, R10, c[0x0][0x170], R11 ; /* 0x00005c000a0c7a24 */
/* 0x000fe200078e020b */
/*01a0*/ MOV R18, R6 ; /* 0x0000000600127202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000e */
/*01c0*/ IMAD.WIDE R12, R12, R9, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0209 */
/*01d0*/ IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000d */
/*01e0*/ MOV R14, R12 ; /* 0x0000000c000e7202 */
/* 0x000fc60000000f00 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R15, R19 ; /* 0x00000013000f7202 */
/* 0x000fe20000000f00 */
/*0210*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.WIDE R12, R18, R9, c[0x0][0x160] ; /* 0x00005800120c7625 */
/* 0x000fc600078e0209 */
/*0230*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0250*/ IADD3 R16, R16, -0x1, RZ ; /* 0xffffffff10107810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.NE.AND P2, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f45270 */
/*0270*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R18, R18, c[0x0][0x170], RZ ; /* 0x00005c0012127a10 */
/* 0x000fe20007ffe0ff */
/*0290*/ FADD R20, R12, R15 ; /* 0x0000000f0c147221 */
/* 0x009fca0000000000 */
/*02a0*/ FSETP.GT.AND P1, PT, R17, R20, PT ; /* 0x000000141100720b */
/* 0x004fda0003f24000 */
/*02b0*/ @P1 STG.E [R2.64], R20 ; /* 0x0000001402001986 */
/* 0x0001e8000c101904 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fca0007f3e0ff */
/*02e0*/ IMAD.X R19, RZ, RZ, R19, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0613 */
/*02f0*/ @P2 BRA 0x1f0 ; /* 0xfffffef000002947 */
/* 0x000fea000383ffff */
/*0300*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0310*/ IMAD R12, R10, c[0x0][0x170], R11 ; /* 0x00005c000a0c7a24 */
/* 0x000fe200078e020b */
/*0320*/ IADD3 R10, RZ, -c[0x0][0x178], RZ ; /* 0x80005e00ff0a7a10 */
/* 0x000fe20007ffe0ff */
/*0330*/ IMAD R14, R8, c[0x0][0x0], R7 ; /* 0x00000000080e7a24 */
/* 0x000fe200078e0207 */
/*0340*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0350*/ IMAD.WIDE R8, R12, R9, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e0209 */
/*0360*/ IMAD R7, R10, c[0x0][0x174], R11.reuse ; /* 0x00005d000a077a24 */
/* 0x100fe400078e020b */
/*0370*/ IMAD.IADD R10, R14, 0x1, -R11 ; /* 0x000000010e0a7824 */
/* 0x000fe400078e0a0b */
/*0380*/ IMAD R14, R7, c[0x0][0x170], R6 ; /* 0x00005c00070e7a24 */
/* 0x000fe200078e0206 */
/*0390*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*03b0*/ SHF.R.S32.HI R20, RZ, 0x1f, R10 ; /* 0x0000001fff147819 */
/* 0x001fe2000001140a */
/*03c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe400078e00ff */
/*03d0*/ MOV R19, 0x4 ; /* 0x0000000400137802 */
/* 0x000fe20000000f00 */
/*03e0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ IMAD.WIDE R12, R14, R19, c[0x0][0x160] ; /* 0x000058000e0c7625 */
/* 0x000fe200078e0213 */
/*0400*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea2000c1e1900 */
/*0420*/ SHF.L.U64.HI R21, R15, 0x2, R18 ; /* 0x000000020f157819 */
/* 0x000fe20000010212 */
/*0430*/ FADD R23, R8, R9 ; /* 0x0000000908177221 */
/* 0x004fca0000000000 */
/*0440*/ FSETP.GT.AND P0, PT, R16, R23, PT ; /* 0x000000171000720b */
/* 0x008fda0003f04000 */
/*0450*/ @P0 STG.E [R2.64], R23 ; /* 0x0000001702000986 */
/* 0x0001e8000c101904 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0470*/ LEA R9, P1, -R15, R10, 0x2 ; /* 0x0000000a0f097211 */
/* 0x000fe200078211ff */
/*0480*/ IMAD.WIDE R16, R19, c[0x0][0x170], R12 ; /* 0x00005c0013107a25 */
/* 0x000fc800078e020c */
/*0490*/ IMAD.X R21, R20, 0x1, ~R21, P1 ; /* 0x0000000114157824 */
/* 0x000fe200008e0e15 */
/*04a0*/ LEA R8, P1, R9, R6, 0x2 ; /* 0x0000000609087211 */
/* 0x000fc800078210ff */
/*04b0*/ LEA.HI.X R9, R9, R7, R21, 0x2, P1 ; /* 0x0000000709097211 */
/* 0x000fe200008f1415 */
/*04c0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R13, [R6.64+0x4] ; /* 0x00000404060d7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ FADD R24, R12, R13 ; /* 0x0000000d0c187221 */
/* 0x004fca0000000000 */
/*0500*/ FSETP.GT.AND P0, PT, R21, R24, PT ; /* 0x000000181500720b */
/* 0x008fda0003f04000 */
/*0510*/ @P0 STG.E [R2.64], R24 ; /* 0x0000001802000986 */
/* 0x0003e8000c101904 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0530*/ IMAD.WIDE R12, R19, c[0x0][0x170], R16 ; /* 0x00005c00130c7a25 */
/* 0x000fca00078e0210 */
/*0540*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R22, [R6.64+0x8] ; /* 0x0000080406167981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD.WIDE R16, R19, c[0x0][0x170], R12 ; /* 0x00005c0013107a25 */
/* 0x000fc800078e020c */
/*0580*/ FADD R25, R21, R22 ; /* 0x0000001615197221 */
/* 0x004fca0000000000 */
/*0590*/ FSETP.GT.AND P0, PT, R23, R25, PT ; /* 0x000000191700720b */
/* 0x008fda0003f04000 */
/*05a0*/ @P0 STG.E [R2.64], R25 ; /* 0x0000001902000986 */
/* 0x0003e8000c101904 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R21, [R6.64+0xc] ; /* 0x00000c0406157981 */
/* 0x0000a8000c1e1900 */
/*05e0*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ee2000c1e1900 */
/*05f0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ IADD3 R15, P2, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007f5e0ff */
/*0610*/ IADD3 R6, P1, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x001fe20007f3e0ff */
/*0620*/ IMAD R14, R19, c[0x0][0x170], R14 ; /* 0x00005c00130e7a24 */
/* 0x000fe200078e020e */
/*0630*/ IADD3.X R18, RZ, R18, RZ, P2, !PT ; /* 0x00000012ff127210 */
/* 0x000fe400017fe4ff */
/*0640*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0650*/ FADD R21, R16, R21 ; /* 0x0000001510157221 */
/* 0x004fca0000000000 */
/*0660*/ FSETP.GT.AND P0, PT, R22, R21, PT ; /* 0x000000151600720b */
/* 0x008fda0003f04000 */
/*0670*/ @P0 STG.E [R2.64], R21 ; /* 0x0000001502000986 */
/* 0x0003e8000c101904 */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0690*/ ISETP.GE.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f06270 */
/*06a0*/ @!P0 BRA 0x3d0 ; /* 0xfffffd2000008947 */
/* 0x002fea000383ffff */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13ShortestPath1PfS_iii
.globl _Z13ShortestPath1PfS_iii
.p2align 8
.type _Z13ShortestPath1PfS_iii,@function
_Z13ShortestPath1PfS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, s14, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
v_add_nc_u32_e32 v2, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s1, s3
s_add_i32 s1, s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v6, v[2:3], off
s_mul_i32 s1, s1, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s0, s1
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_5
v_add_nc_u32_e32 v6, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_nc_u32_e32 v0, s2, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s3, s3, -1
s_waitcnt_vscnt null, 0x0
s_cmp_lg_u32 s3, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[0:1]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v1, v[6:7], off
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[2:3], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v9, v1
s_cbranch_execz .LBB0_2
global_store_b32 v[4:5], v1, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13ShortestPath1PfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13ShortestPath1PfS_iii, .Lfunc_end0-_Z13ShortestPath1PfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13ShortestPath1PfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13ShortestPath1PfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00147626_00000000-6_ShortestPath1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii
.type _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii, @function
_Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13ShortestPath1PfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii, .-_Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii
.globl _Z13ShortestPath1PfS_iii
.type _Z13ShortestPath1PfS_iii, @function
_Z13ShortestPath1PfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13ShortestPath1PfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13ShortestPath1PfS_iii, .-_Z13ShortestPath1PfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13ShortestPath1PfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13ShortestPath1PfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ShortestPath1.hip"
.globl _Z28__device_stub__ShortestPath1PfS_iii # -- Begin function _Z28__device_stub__ShortestPath1PfS_iii
.p2align 4, 0x90
.type _Z28__device_stub__ShortestPath1PfS_iii,@function
_Z28__device_stub__ShortestPath1PfS_iii: # @_Z28__device_stub__ShortestPath1PfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13ShortestPath1PfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__ShortestPath1PfS_iii, .Lfunc_end0-_Z28__device_stub__ShortestPath1PfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13ShortestPath1PfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13ShortestPath1PfS_iii,@object # @_Z13ShortestPath1PfS_iii
.section .rodata,"a",@progbits
.globl _Z13ShortestPath1PfS_iii
.p2align 3, 0x0
_Z13ShortestPath1PfS_iii:
.quad _Z28__device_stub__ShortestPath1PfS_iii
.size _Z13ShortestPath1PfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13ShortestPath1PfS_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__ShortestPath1PfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13ShortestPath1PfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define BLOCKDIM 1024
#define RSIZE 1024
//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening
__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{
__shared__ double dist_array[BLOCKDIM];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//advantage of register
double a0 = maskCenter[0];
double a1 = maskCenter[1];
double a2 = maskCenter[2];
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
int sIndex = mol*NAtoms*3 + atom*3;
double x = a0 - SolventMols_[sIndex + 0];
double y = a1 - SolventMols_[sIndex + 1];
double z = a2 - SolventMols_[sIndex + 2];
//Dist = x*x + y*y + z*z;
dist_array[threadIdx.x] = x*x + y*y + z*z;
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
int i;
double min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
}
// int i;
// double min_val = maxD;
// if( atom ==0 )
// {
// for(i = 0 ; i < NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
// }
// D_[mol] = min_val;
// }
// double min_val = maxD;
// if( threadIdx.x < active_size/NAtoms )
// {
// for(i = threadIdx.x*NAtoms ; i <threadIdx.x*NAtoms + NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[i] < min_val)
// min_val = dist_array[i] ;
// }
// D_[blockIdx.x * active_size/NAtoms + threadIdx.x ] = min_val;
// }
//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{
__shared__ double dist_array[BLOCKDIM];
__shared__ double sAtom_shared[RSIZE];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//handling the chunks for solute_atoms
int chunksize,start,end, NChunks,i,j;
if(NSAtoms*3 > RSIZE)
{
chunksize = (RSIZE/3)*3;
NChunks = ceil(double(NSAtoms*3)/chunksize);
start = 0;
end = chunksize;
}
else
{
chunksize = NSAtoms*3;
NChunks = 1;
start = 0;
end = NSAtoms*3;
}
// if(threadIdx.x == 0 && blockIdx.x == 0 )
// printf("chunkszize = %d ; Nchunk = %d; start = %d; end = %d\n ",
// chunksize,NChunks,start,end);
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
double min_val = maxD;
double dist;
int sIndex = mol*NAtoms*3 + atom*3;
double a0 = SolventMols_[sIndex + 0];
double a1 = SolventMols_[sIndex + 1];
double a2 = SolventMols_[sIndex + 2];
for(i = 0 ; i < NChunks ; i++)
{
//copying to shared
//if (threadIdx.x < (end - start))
// sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];
//__syncthreads();
//TODO - add skew per thread
for (j = start ; j < end; j+=3 )
{
//int offset = start + (j + threadIdx.x)%(end - start);
double x = Solute_atoms[j + 0] - a0;
double y = Solute_atoms[j + 1] - a1;
double z = Solute_atoms[j + 2] - a2;
dist = x*x + y*y + z*z;
//if (mol == 11)
// printf("min = %f\n",min_val);
min_val = min(min_val,dist);
}
start = end;
end = min(end + chunksize, NSAtoms*3);
}
dist_array[threadIdx.x] = min_val;
//if (threadIdx.x == 0)
// printf("min_val = %f\n",min_val);
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
//min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
} | .file "tmpxft_00038744_00000000-6_core_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
.type _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii, @function
_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii:
.LFB2081:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z25Action_noImage_center_GPUPdS_S_diii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii, .-_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
.globl _Z25Action_noImage_center_GPUPdS_S_diii
.type _Z25Action_noImage_center_GPUPdS_S_diii, @function
_Z25Action_noImage_center_GPUPdS_S_diii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z25Action_noImage_center_GPUPdS_S_diii, .-_Z25Action_noImage_center_GPUPdS_S_diii
.globl _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
.type _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii, @function
_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28Action_noImage_no_center_GPUPdS_S_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii, .-_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
.globl _Z28Action_noImage_no_center_GPUPdS_S_diiii
.type _Z28Action_noImage_no_center_GPUPdS_S_diiii, @function
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z28Action_noImage_no_center_GPUPdS_S_diiii, .-_Z28Action_noImage_no_center_GPUPdS_S_diiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28Action_noImage_no_center_GPUPdS_S_diiii"
.align 8
.LC1:
.string "_Z25Action_noImage_center_GPUPdS_S_diii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28Action_noImage_no_center_GPUPdS_S_diiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z25Action_noImage_center_GPUPdS_S_diii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define BLOCKDIM 1024
#define RSIZE 1024
//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening
__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{
__shared__ double dist_array[BLOCKDIM];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//advantage of register
double a0 = maskCenter[0];
double a1 = maskCenter[1];
double a2 = maskCenter[2];
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
int sIndex = mol*NAtoms*3 + atom*3;
double x = a0 - SolventMols_[sIndex + 0];
double y = a1 - SolventMols_[sIndex + 1];
double z = a2 - SolventMols_[sIndex + 2];
//Dist = x*x + y*y + z*z;
dist_array[threadIdx.x] = x*x + y*y + z*z;
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
int i;
double min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
}
// int i;
// double min_val = maxD;
// if( atom ==0 )
// {
// for(i = 0 ; i < NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
// }
// D_[mol] = min_val;
// }
// double min_val = maxD;
// if( threadIdx.x < active_size/NAtoms )
// {
// for(i = threadIdx.x*NAtoms ; i <threadIdx.x*NAtoms + NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[i] < min_val)
// min_val = dist_array[i] ;
// }
// D_[blockIdx.x * active_size/NAtoms + threadIdx.x ] = min_val;
// }
//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{
__shared__ double dist_array[BLOCKDIM];
__shared__ double sAtom_shared[RSIZE];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//handling the chunks for solute_atoms
int chunksize,start,end, NChunks,i,j;
if(NSAtoms*3 > RSIZE)
{
chunksize = (RSIZE/3)*3;
NChunks = ceil(double(NSAtoms*3)/chunksize);
start = 0;
end = chunksize;
}
else
{
chunksize = NSAtoms*3;
NChunks = 1;
start = 0;
end = NSAtoms*3;
}
// if(threadIdx.x == 0 && blockIdx.x == 0 )
// printf("chunkszize = %d ; Nchunk = %d; start = %d; end = %d\n ",
// chunksize,NChunks,start,end);
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
double min_val = maxD;
double dist;
int sIndex = mol*NAtoms*3 + atom*3;
double a0 = SolventMols_[sIndex + 0];
double a1 = SolventMols_[sIndex + 1];
double a2 = SolventMols_[sIndex + 2];
for(i = 0 ; i < NChunks ; i++)
{
//copying to shared
//if (threadIdx.x < (end - start))
// sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];
//__syncthreads();
//TODO - add skew per thread
for (j = start ; j < end; j+=3 )
{
//int offset = start + (j + threadIdx.x)%(end - start);
double x = Solute_atoms[j + 0] - a0;
double y = Solute_atoms[j + 1] - a1;
double z = Solute_atoms[j + 2] - a2;
dist = x*x + y*y + z*z;
//if (mol == 11)
// printf("min = %f\n",min_val);
min_val = min(min_val,dist);
}
start = end;
end = min(end + chunksize, NSAtoms*3);
}
dist_array[threadIdx.x] = min_val;
//if (threadIdx.x == 0)
// printf("min_val = %f\n",min_val);
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
//min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKDIM 1024
#define RSIZE 1024
//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening
__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{
__shared__ double dist_array[BLOCKDIM];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//advantage of register
double a0 = maskCenter[0];
double a1 = maskCenter[1];
double a2 = maskCenter[2];
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
int sIndex = mol*NAtoms*3 + atom*3;
double x = a0 - SolventMols_[sIndex + 0];
double y = a1 - SolventMols_[sIndex + 1];
double z = a2 - SolventMols_[sIndex + 2];
//Dist = x*x + y*y + z*z;
dist_array[threadIdx.x] = x*x + y*y + z*z;
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
int i;
double min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
}
// int i;
// double min_val = maxD;
// if( atom ==0 )
// {
// for(i = 0 ; i < NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
// }
// D_[mol] = min_val;
// }
// double min_val = maxD;
// if( threadIdx.x < active_size/NAtoms )
// {
// for(i = threadIdx.x*NAtoms ; i <threadIdx.x*NAtoms + NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[i] < min_val)
// min_val = dist_array[i] ;
// }
// D_[blockIdx.x * active_size/NAtoms + threadIdx.x ] = min_val;
// }
//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{
__shared__ double dist_array[BLOCKDIM];
__shared__ double sAtom_shared[RSIZE];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//handling the chunks for solute_atoms
int chunksize,start,end, NChunks,i,j;
if(NSAtoms*3 > RSIZE)
{
chunksize = (RSIZE/3)*3;
NChunks = ceil(double(NSAtoms*3)/chunksize);
start = 0;
end = chunksize;
}
else
{
chunksize = NSAtoms*3;
NChunks = 1;
start = 0;
end = NSAtoms*3;
}
// if(threadIdx.x == 0 && blockIdx.x == 0 )
// printf("chunkszize = %d ; Nchunk = %d; start = %d; end = %d\n ",
// chunksize,NChunks,start,end);
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
double min_val = maxD;
double dist;
int sIndex = mol*NAtoms*3 + atom*3;
double a0 = SolventMols_[sIndex + 0];
double a1 = SolventMols_[sIndex + 1];
double a2 = SolventMols_[sIndex + 2];
for(i = 0 ; i < NChunks ; i++)
{
//copying to shared
//if (threadIdx.x < (end - start))
// sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];
//__syncthreads();
//TODO - add skew per thread
for (j = start ; j < end; j+=3 )
{
//int offset = start + (j + threadIdx.x)%(end - start);
double x = Solute_atoms[j + 0] - a0;
double y = Solute_atoms[j + 1] - a1;
double z = Solute_atoms[j + 2] - a2;
dist = x*x + y*y + z*z;
//if (mol == 11)
// printf("min = %f\n",min_val);
min_val = min(min_val,dist);
}
start = end;
end = min(end + chunksize, NSAtoms*3);
}
dist_array[threadIdx.x] = min_val;
//if (threadIdx.x == 0)
// printf("min_val = %f\n",min_val);
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
//min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKDIM 1024
#define RSIZE 1024
//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening
__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{
__shared__ double dist_array[BLOCKDIM];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//advantage of register
double a0 = maskCenter[0];
double a1 = maskCenter[1];
double a2 = maskCenter[2];
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
int sIndex = mol*NAtoms*3 + atom*3;
double x = a0 - SolventMols_[sIndex + 0];
double y = a1 - SolventMols_[sIndex + 1];
double z = a2 - SolventMols_[sIndex + 2];
//Dist = x*x + y*y + z*z;
dist_array[threadIdx.x] = x*x + y*y + z*z;
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
int i;
double min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
}
// int i;
// double min_val = maxD;
// if( atom ==0 )
// {
// for(i = 0 ; i < NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
// }
// D_[mol] = min_val;
// }
// double min_val = maxD;
// if( threadIdx.x < active_size/NAtoms )
// {
// for(i = threadIdx.x*NAtoms ; i <threadIdx.x*NAtoms + NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[i] < min_val)
// min_val = dist_array[i] ;
// }
// D_[blockIdx.x * active_size/NAtoms + threadIdx.x ] = min_val;
// }
//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{
__shared__ double dist_array[BLOCKDIM];
__shared__ double sAtom_shared[RSIZE];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//handling the chunks for solute_atoms
int chunksize,start,end, NChunks,i,j;
if(NSAtoms*3 > RSIZE)
{
chunksize = (RSIZE/3)*3;
NChunks = ceil(double(NSAtoms*3)/chunksize);
start = 0;
end = chunksize;
}
else
{
chunksize = NSAtoms*3;
NChunks = 1;
start = 0;
end = NSAtoms*3;
}
// if(threadIdx.x == 0 && blockIdx.x == 0 )
// printf("chunkszize = %d ; Nchunk = %d; start = %d; end = %d\n ",
// chunksize,NChunks,start,end);
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
double min_val = maxD;
double dist;
int sIndex = mol*NAtoms*3 + atom*3;
double a0 = SolventMols_[sIndex + 0];
double a1 = SolventMols_[sIndex + 1];
double a2 = SolventMols_[sIndex + 2];
for(i = 0 ; i < NChunks ; i++)
{
//copying to shared
//if (threadIdx.x < (end - start))
// sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];
//__syncthreads();
//TODO - add skew per thread
for (j = start ; j < end; j+=3 )
{
//int offset = start + (j + threadIdx.x)%(end - start);
double x = Solute_atoms[j + 0] - a0;
double y = Solute_atoms[j + 1] - a1;
double z = Solute_atoms[j + 2] - a2;
dist = x*x + y*y + z*z;
//if (mol == 11)
// printf("min = %f\n",min_val);
min_val = min(min_val,dist);
}
start = end;
end = min(end + chunksize, NSAtoms*3);
}
dist_array[threadIdx.x] = min_val;
//if (threadIdx.x == 0)
// printf("min_val = %f\n",min_val);
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
//min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25Action_noImage_center_GPUPdS_S_diii
.globl _Z25Action_noImage_center_GPUPdS_S_diii
.p2align 8
.type _Z25Action_noImage_center_GPUPdS_S_diii,@function
_Z25Action_noImage_center_GPUPdS_S_diii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s2, s3, s2
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
v_lshl_add_u32 v2, v1, 1, v1
v_cvt_f32_u32_e32 v8, s3
s_sub_i32 s2, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_rcp_iflag_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, 0x4f7ffffe, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
s_clause 0x1
global_load_b128 v[2:5], v[6:7], off
global_load_b64 v[6:7], v[6:7], off offset:16
s_clause 0x1
s_load_b128 s[8:11], s[4:5], 0x0
s_load_b64 s[4:5], s[4:5], 0x10
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_f64 v[4:5], s[10:11], -v[4:5]
v_add_f64 v[2:3], s[8:9], -v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], s[4:5], -v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[4:5]
v_fma_f64 v[2:3], v[2:3], v[2:3], v[4:5]
v_cvt_u32_f32_e32 v4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s2, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v4, v5
v_mad_u64_u32 v[4:5], null, v1, v8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, v5, s3
v_fma_f64 v[3:4], v[6:7], v[6:7], v[2:3]
v_add_nc_u32_e32 v6, 1, v5
v_sub_nc_u32_e32 v2, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v5
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v5, v6, vcc_lo
v_lshlrev_b32_e32 v6, 3, v0
v_mul_lo_u32 v5, v2, s3
ds_store_b64 v6, v[3:4]
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v1, v5
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x18
s_cmp_lt_i32 s3, 1
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
s_cbranch_scc1 .LBB0_5
v_mov_b32_e32 v4, s4
v_dual_mov_b32 v5, s5 :: v_dual_lshlrev_b32 v0, 3, v0
.LBB0_4:
ds_load_b64 v[6:7], v0
v_max_f64 v[3:4], v[4:5], v[4:5]
v_add_nc_u32_e32 v0, 8, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
s_waitcnt lgkmcnt(0)
v_max_f64 v[5:6], v[6:7], v[6:7]
v_min_f64 v[4:5], v[3:4], v[5:6]
s_cbranch_scc1 .LBB0_4
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25Action_noImage_center_GPUPdS_S_diii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25Action_noImage_center_GPUPdS_S_diii, .Lfunc_end0-_Z25Action_noImage_center_GPUPdS_S_diii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z28Action_noImage_no_center_GPUPdS_S_diiii
.globl _Z28Action_noImage_no_center_GPUPdS_S_diiii
.p2align 8
.type _Z28Action_noImage_no_center_GPUPdS_S_diiii,@function
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x24
s_mov_b32 s9, 1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_mul_i32 s8, s5, 3
s_cmpk_lt_i32 s5, 0x156
s_mov_b32 s5, s8
s_cbranch_scc1 .LBB1_2
v_cvt_f64_i32_e32 v[1:2], s8
s_movk_i32 s5, 0x3ff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[3:4], null, 0x408ff800, 0x408ff800, v[1:2]
v_rcp_f64_e32 v[6:7], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[1:2], 0x408ff800, v[1:2]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[3:4], v[10:11], v[8:9]
v_div_fmas_f64 v[3:4], v[3:4], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[3:4], 0x408ff800, v[1:2]
v_ceil_f64_e32 v[1:2], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v1, v[1:2]
v_readfirstlane_b32 s9, v1
.LBB1_2:
s_load_b32 s3, s[0:1], 0x20
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_14
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s2, 0, s4
s_cmp_lt_i32 s9, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v1
s_load_b64 s[2:3], s[0:1], 0x18
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mad_u64_u32 v[7:8], null, v5, v1, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_cbranch_scc1 .LBB1_9
s_load_b128 s[12:15], s[0:1], 0x8
v_lshl_add_u32 v1, v5, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s12, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v2, vcc_lo
s_add_u32 s10, s14, 8
s_addc_u32 s11, s15, 0
s_mov_b32 s12, s5
s_clause 0x1
global_load_b128 v[1:4], v[6:7], off
global_load_b64 v[9:10], v[6:7], off offset:16
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_mov_b32 s2, 0
s_mov_b32 s13, 0
s_cmp_ge_i32 s2, s12
s_cbranch_scc1 .LBB1_7
.p2align 6
.LBB1_5:
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[2:3], 3
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
.p2align 6
.LBB1_6:
s_add_u32 s14, s6, -8
s_addc_u32 s15, s7, -1
s_clause 0x1
s_load_b128 s[16:19], s[6:7], 0x0
s_load_b64 s[14:15], s[14:15], 0x0
s_delay_alu instid0(VALU_DEP_1)
v_max_f64 v[6:7], v[6:7], v[6:7]
s_add_i32 s2, s2, 3
s_add_u32 s6, s6, 24
s_addc_u32 s7, s7, 0
s_cmp_lt_i32 s2, s12
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_f64 v[11:12], s[16:17], -v[3:4]
v_add_f64 v[13:14], s[14:15], -v[1:2]
s_waitcnt vmcnt(0)
v_add_f64 v[15:16], s[18:19], -v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[11:12], v[11:12]
v_fma_f64 v[11:12], v[13:14], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[15:16], v[15:16], v[11:12]
v_min_f64 v[6:7], v[6:7], v[11:12]
s_cbranch_scc1 .LBB1_6
.LBB1_7:
s_add_i32 s2, s12, s5
s_add_i32 s13, s13, 1
s_min_i32 s3, s2, s8
s_cmp_lg_u32 s13, s9
s_cbranch_scc0 .LBB1_9
s_mov_b32 s2, s12
s_mov_b32 s12, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s2, s12
s_cbranch_scc0 .LBB1_5
s_branch .LBB1_7
.LBB1_9:
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v8, s4
v_sub_nc_u32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, v1, v3 :: v_dual_add_nc_u32 v2, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v8, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v2
v_cndmask_b32_e32 v1, v2, v3, vcc_lo
v_lshlrev_b32_e32 v3, 3, v0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
ds_store_b64 v3, v[6:7]
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_eq_u32_e32 vcc_lo, v5, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_14
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_13
v_lshlrev_b32_e32 v0, 3, v0
.LBB1_12:
ds_load_b64 v[2:3], v0
v_max_f64 v[4:5], v[6:7], v[6:7]
v_add_nc_u32_e32 v0, 8, v0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_max_f64 v[2:3], v[2:3], v[2:3]
v_min_f64 v[6:7], v[4:5], v[2:3]
s_cbranch_scc1 .LBB1_12
.LBB1_13:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[6:7], off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28Action_noImage_no_center_GPUPdS_S_diiii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z28Action_noImage_no_center_GPUPdS_S_diiii, .Lfunc_end1-_Z28Action_noImage_no_center_GPUPdS_S_diiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25Action_noImage_center_GPUPdS_S_diii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25Action_noImage_center_GPUPdS_S_diii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28Action_noImage_no_center_GPUPdS_S_diiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z28Action_noImage_no_center_GPUPdS_S_diiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKDIM 1024
#define RSIZE 1024
//------------------------------------------------------------------------------------------------------------------------------------------------
//try thread coarsening
__global__ void Action_noImage_center_GPU(double *D_,double *maskCenter,double *SolventMols_,double maxD, int Nmols , int NAtoms, int active_size)
{
__shared__ double dist_array[BLOCKDIM];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//advantage of register
double a0 = maskCenter[0];
double a1 = maskCenter[1];
double a2 = maskCenter[2];
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
int sIndex = mol*NAtoms*3 + atom*3;
double x = a0 - SolventMols_[sIndex + 0];
double y = a1 - SolventMols_[sIndex + 1];
double z = a2 - SolventMols_[sIndex + 2];
//Dist = x*x + y*y + z*z;
dist_array[threadIdx.x] = x*x + y*y + z*z;
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
int i;
double min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
}
// int i;
// double min_val = maxD;
// if( atom ==0 )
// {
// for(i = 0 ; i < NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
// }
// D_[mol] = min_val;
// }
// double min_val = maxD;
// if( threadIdx.x < active_size/NAtoms )
// {
// for(i = threadIdx.x*NAtoms ; i <threadIdx.x*NAtoms + NAtoms ; i++ ){
// //sIndex = mol*NAtoms*3 + i*3;
// if (dist_array[i] < min_val)
// min_val = dist_array[i] ;
// }
// D_[blockIdx.x * active_size/NAtoms + threadIdx.x ] = min_val;
// }
//------------------------------------------------------------------------------------------------------------------------------------------------
__global__ void Action_noImage_no_center_GPU(double *D_,double *SolventMols_,double *Solute_atoms ,double maxD, int Nmols , int NAtoms,int NSAtoms , int active_size)
{
__shared__ double dist_array[BLOCKDIM];
__shared__ double sAtom_shared[RSIZE];
int mol = (blockIdx.x * active_size + threadIdx.x)/NAtoms;
int atom = (blockIdx.x * active_size + threadIdx.x) - (mol * NAtoms);
//int mol_in_block = threadIdx.x/NAtoms;
//handling the chunks for solute_atoms
int chunksize,start,end, NChunks,i,j;
if(NSAtoms*3 > RSIZE)
{
chunksize = (RSIZE/3)*3;
NChunks = ceil(double(NSAtoms*3)/chunksize);
start = 0;
end = chunksize;
}
else
{
chunksize = NSAtoms*3;
NChunks = 1;
start = 0;
end = NSAtoms*3;
}
// if(threadIdx.x == 0 && blockIdx.x == 0 )
// printf("chunkszize = %d ; Nchunk = %d; start = %d; end = %d\n ",
// chunksize,NChunks,start,end);
if ( threadIdx.x < active_size && mol*NAtoms + atom < Nmols*NAtoms )
{
// if(atom == 0 )
// D_[mol] = maxD;
//__syncthreads();
double min_val = maxD;
double dist;
int sIndex = mol*NAtoms*3 + atom*3;
double a0 = SolventMols_[sIndex + 0];
double a1 = SolventMols_[sIndex + 1];
double a2 = SolventMols_[sIndex + 2];
for(i = 0 ; i < NChunks ; i++)
{
//copying to shared
//if (threadIdx.x < (end - start))
// sAtom_shared[threadIdx.x] = Solute_atoms[start + threadIdx.x];
//__syncthreads();
//TODO - add skew per thread
for (j = start ; j < end; j+=3 )
{
//int offset = start + (j + threadIdx.x)%(end - start);
double x = Solute_atoms[j + 0] - a0;
double y = Solute_atoms[j + 1] - a1;
double z = Solute_atoms[j + 2] - a2;
dist = x*x + y*y + z*z;
//if (mol == 11)
// printf("min = %f\n",min_val);
min_val = min(min_val,dist);
}
start = end;
end = min(end + chunksize, NSAtoms*3);
}
dist_array[threadIdx.x] = min_val;
//if (threadIdx.x == 0)
// printf("min_val = %f\n",min_val);
//printf(" dist = %f\n", Dist);
__syncthreads();
//first thread
//naive approach to a reduction algorithm
//this works if NAtoms is small other wise you need split
//and do some of log(n) parallel reduction
//min_val = maxD;
if( atom ==0 )
{
for(i = 0 ; i < NAtoms ; i++ ){
//sIndex = mol*NAtoms*3 + i*3;
//if (dist_array[threadIdx.x + i] < min_val)
// min_val = dist_array[threadIdx.x + i] ;
min_val = min(min_val, dist_array[threadIdx.x + i]);
}
D_[mol] = min_val;
}
//if(tx == 0 && bx == 0 )
// printf("end of kernel");
}
} | .text
.file "core_kernels.hip"
.globl _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii # -- Begin function _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.p2align 4, 0x90
.type _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii,@function
_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii: # @_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25Action_noImage_center_GPUPdS_S_diii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii, .Lfunc_end0-_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii # -- Begin function _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.p2align 4, 0x90
.type _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii,@function
_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii: # @_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28Action_noImage_no_center_GPUPdS_S_diiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii, .Lfunc_end1-_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25Action_noImage_center_GPUPdS_S_diii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28Action_noImage_no_center_GPUPdS_S_diiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25Action_noImage_center_GPUPdS_S_diii,@object # @_Z25Action_noImage_center_GPUPdS_S_diii
.section .rodata,"a",@progbits
.globl _Z25Action_noImage_center_GPUPdS_S_diii
.p2align 3, 0x0
_Z25Action_noImage_center_GPUPdS_S_diii:
.quad _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.size _Z25Action_noImage_center_GPUPdS_S_diii, 8
.type _Z28Action_noImage_no_center_GPUPdS_S_diiii,@object # @_Z28Action_noImage_no_center_GPUPdS_S_diiii
.globl _Z28Action_noImage_no_center_GPUPdS_S_diiii
.p2align 3, 0x0
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
.quad _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.size _Z28Action_noImage_no_center_GPUPdS_S_diiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25Action_noImage_center_GPUPdS_S_diii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z28Action_noImage_no_center_GPUPdS_S_diiii"
.size .L__unnamed_2, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.addrsig_sym _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25Action_noImage_center_GPUPdS_S_diii
.addrsig_sym _Z28Action_noImage_no_center_GPUPdS_S_diiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00038744_00000000-6_core_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
.type _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii, @function
_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii:
.LFB2081:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z25Action_noImage_center_GPUPdS_S_diii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii, .-_Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
.globl _Z25Action_noImage_center_GPUPdS_S_diii
.type _Z25Action_noImage_center_GPUPdS_S_diii, @function
_Z25Action_noImage_center_GPUPdS_S_diii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z25Action_noImage_center_GPUPdS_S_diiiPdS_S_diii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z25Action_noImage_center_GPUPdS_S_diii, .-_Z25Action_noImage_center_GPUPdS_S_diii
.globl _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
.type _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii, @function
_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28Action_noImage_no_center_GPUPdS_S_diiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii, .-_Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
.globl _Z28Action_noImage_no_center_GPUPdS_S_diiii
.type _Z28Action_noImage_no_center_GPUPdS_S_diiii, @function
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z28Action_noImage_no_center_GPUPdS_S_diiiiPdS_S_diiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z28Action_noImage_no_center_GPUPdS_S_diiii, .-_Z28Action_noImage_no_center_GPUPdS_S_diiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28Action_noImage_no_center_GPUPdS_S_diiii"
.align 8
.LC1:
.string "_Z25Action_noImage_center_GPUPdS_S_diii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28Action_noImage_no_center_GPUPdS_S_diiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z25Action_noImage_center_GPUPdS_S_diii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "core_kernels.hip"
.globl _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii # -- Begin function _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.p2align 4, 0x90
.type _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii,@function
_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii: # @_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25Action_noImage_center_GPUPdS_S_diii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii, .Lfunc_end0-_Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii # -- Begin function _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.p2align 4, 0x90
.type _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii,@function
_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii: # @_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28Action_noImage_no_center_GPUPdS_S_diiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii, .Lfunc_end1-_Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25Action_noImage_center_GPUPdS_S_diii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28Action_noImage_no_center_GPUPdS_S_diiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25Action_noImage_center_GPUPdS_S_diii,@object # @_Z25Action_noImage_center_GPUPdS_S_diii
.section .rodata,"a",@progbits
.globl _Z25Action_noImage_center_GPUPdS_S_diii
.p2align 3, 0x0
_Z25Action_noImage_center_GPUPdS_S_diii:
.quad _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.size _Z25Action_noImage_center_GPUPdS_S_diii, 8
.type _Z28Action_noImage_no_center_GPUPdS_S_diiii,@object # @_Z28Action_noImage_no_center_GPUPdS_S_diiii
.globl _Z28Action_noImage_no_center_GPUPdS_S_diiii
.p2align 3, 0x0
_Z28Action_noImage_no_center_GPUPdS_S_diiii:
.quad _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.size _Z28Action_noImage_no_center_GPUPdS_S_diiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25Action_noImage_center_GPUPdS_S_diii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z28Action_noImage_no_center_GPUPdS_S_diiii"
.size .L__unnamed_2, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__Action_noImage_center_GPUPdS_S_diii
.addrsig_sym _Z43__device_stub__Action_noImage_no_center_GPUPdS_S_diiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25Action_noImage_center_GPUPdS_S_diii
.addrsig_sym _Z28Action_noImage_no_center_GPUPdS_S_diiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stack>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
using namespace std;
struct Point {
/* it will represent a point */
int x, y;
};
__constant__ Point d_p0[1];
__device__ int distSq(Point p1, Point p2)
{
return (p1.x - p2.x)*(p1.x - p2.x) +
(p1.y - p2.y)*(p1.y - p2.y);
}
// To find orientation of ordered triplet (p, q, r).
// The function returns following values
// 0 --> p, q and r are colinear
// 1 --> Clockwise
// 2 --> Counterclockwise
__device__ int d_orientation(Point p, Point q, Point r)
{
int val = (q.y - p.y) * (r.x - q.x) -
(q.x - p.x) * (r.y - q.y);
if (val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
__device__ int compare(Point p1,Point p2){
// Find orientation with respect to the first point
int o = d_orientation(d_p0[0], p1, p2);
if(o == 0)
return (distSq(d_p0[0], p2) >= distSq(d_p0[0],p1))? -1 : 1;
return (o == 2)? -1: 1;
}
__device__ void swap(Point *points,uint lowIndex,uint upIndex){
/* it will swap two points */
Point aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(Point* points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
Point p1 = points[lowG1];
Point p2 = points[lowG2];
if(compare(p1,p2) == 1){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
Point p1 = points[lowG1];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
Point p1 = points[lowG2];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void checkCudaState(cudaError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != cudaSuccess) cout << message;
}
__host__ Point nextToTop(stack<Point> &S){
/* it will find next to top in a stack */
Point p = S.top();
S.pop();
Point res = S.top();
S.push(p);
return res;
}
__host__ void swap(Point &p1, Point &p2){
/* it will swap two points */
Point temp = p1;
p1 = p2;
p2 = temp;
}
__host__ int h_orientation(Point p, Point q, Point r){
/* it will determine orientation between three points */
int val = (q.y - p.y) * (r.x - q.x) - (q.x - p.x) * (r.y - q.y);
if(val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
// Prints convex hull of a set of n points.
__host__ void convexHull(Point *h_points, int n){
/* it will find convex hull of a set of points */
cudaError_t cudaState = cudaSuccess;
size_t size = n*sizeof(Point);
Point *h_result = NULL, *d_points = NULL;
h_result = (Point *) malloc(size);
cudaState = cudaMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data for d_points\n");
if(d_points != NULL){
// Find the bottommost point
int ymin = h_points[0].y, min = 0;
for(int i = 1; i < n; i++){
int y = h_points[i].y;
// Pick the bottom-most or chose the left
// most point in case of tie
if((y < ymin) || (ymin == y && h_points[i].x < h_points[min].x))
ymin = h_points[i].y, min = i;
}
// Place the bottom-most point at first position
swap(h_points[0], h_points[min]);
// Sort n-1 points with respect to the first point.
// A point p1 comes before p2 in sorted ouput if p2
// has larger polar angle (in counterclockwise
// direction) than p1
cudaState = cudaMemcpyToSymbol(d_p0,h_points,sizeof(Point));
checkCudaState(cudaState,"Impossible copy data from host to device\n");
cudaState = cudaMemcpy(d_points,h_points,size,cudaMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
dim3 gridSize((int)(ceil(n/1024.0)),1,1);
dim3 blockSize(1024,1,1);
uint i = 1;
while(pow(2,i) <= n){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),n);
cudaDeviceSynchronize();
i++;
}
cudaState = cudaMemcpy(h_result,d_points,size,cudaMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
h_result[0] = h_points[0];
// If two or more points make same angle with p0,
// Remove all but the one that is farthest from p0
// Remember that, in above sorting, our criteria was
// to keep the farthest point at the end when more than
// one points have same angle.
int m = 1; // Initialize size of modified array
for(int i=1; i<n; i++){
// Keep removing i while angle of i and i+1 is same
// with respect to p0
while(i < n-1 && h_orientation(h_points[0],h_result[i],h_result[i+1]) == 0)
i++;
h_result[m] = h_result[i];
m++; // Update size of modified array
}
// If modified array of points has less than 3 points,
// convex hull is not possible
if (m < 3) return;
// Create an empty stack and push first three points
// to it.
stack<Point> S;
S.push(h_result[0]);
S.push(h_result[1]);
S.push(h_result[2]);
// Process remaining n-3 points
for(int i = 3; i < m; i++){
// Keep removing top while the angle formed by
// points next-to-top, top, and h_result[i] makes
// a non-left turn
while(h_orientation(nextToTop(S), S.top(), h_result[i]) != 2)
S.pop();
S.push(h_result[i]);
}
// Now stack has the output points, print contents of stack
while(!S.empty()){
Point p = S.top();
cout << "(" << p.x << ", " << p.y <<")" << endl;
S.pop();
}
}
if(h_result != NULL) free(h_result);
if(d_points != NULL) cudaFree(d_points);
}
// Driver program to test above functions
int main() {
uint n = 9;
size_t size = n*sizeof(Point);
Point *h_points = NULL;
h_points = (Point *) malloc(size);
if(h_points != NULL){
h_points[0].x = 0; h_points[0].y = 3;
h_points[1].x = 1; h_points[1].y = 1;
h_points[2].x = 2; h_points[2].y = 2;
h_points[3].x = 4; h_points[3].y = 4;
h_points[4].x = 0; h_points[4].y = 0;
h_points[5].x = 1; h_points[5].y = 2;
h_points[6].x = 3; h_points[6].y = 1;
h_points[7].x = 3; h_points[7].y = 3;
h_points[8].x = 2; h_points[8].y = 1;
convexHull(h_points, n);
}
if(h_points != NULL) free(h_points);
return 0;
} | code for sm_80
Function : _Z4sortP5Pointjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0080*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f25070 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0160*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff039a12 */
/* 0x000fc800078e33ff */
/*0180*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01b0*/ IADD3 R9, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000097a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*01d0*/ IADD3 R6, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fc60007ffe0ff */
/*01e0*/ IADD3 R9, R9, UR4, RZ ; /* 0x0000000409097c10 */
/* 0x000fe4000fffe0ff */
/*01f0*/ IADD3 R7, R6.reuse, UR4, RZ ; /* 0x0000000406077c10 */
/* 0x040fe4000fffe0ff */
/*0200*/ ISETP.GT.U32.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600720c */
/* 0x0c0fe40003f44070 */
/*0210*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f24070 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fd60003f04070 */
/*0230*/ @P1 EXIT P2 ; /* 0x000000000000194d */
/* 0x000fea0001000000 */
/*0240*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0250*/ ISETP.GT.U32.AND P2, PT, R7.reuse, R0, PT ; /* 0x000000000700720c */
/* 0x040fe20003f44070 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.LE.U32.AND P3, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe20003f63070 */
/*0280*/ BSSY B0, 0xa80 ; /* 0x000007f000007945 */
/* 0x000fe40003800000 */
/*0290*/ IMAD.WIDE.U32 R4, R7, R8, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x001fc800078e0008 */
/*02a0*/ IMAD.WIDE.U32 R2, R6, R8, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0008 */
/*02b0*/ @!P2 BRA P3, 0x840 ; /* 0x000005800000a947 */
/* 0x000fea0001800000 */
/*02c0*/ ISETP.LT.U32.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f41070 */
/*02d0*/ @P1 BRA P2, 0x5f0 ; /* 0x0000031000001947 */
/* 0x000fea0001000000 */
/*02e0*/ ISETP.LT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f21070 */
/*02f0*/ @P0 BRA P1, 0x3a0 ; /* 0x000000a000000947 */
/* 0x000fea0000800000 */
/*0300*/ ISETP.NE.AND P0, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600720c */
/* 0x0c0fe40003f05270 */
/*0310*/ ISETP.NE.AND P1, PT, R6.reuse, R9, PT ; /* 0x000000090600720c */
/* 0x040fe40003f25270 */
/*0320*/ ISETP.EQ.AND P0, PT, R7.reuse, R0, P0 ; /* 0x000000000700720c */
/* 0x040fe40000702270 */
/*0330*/ IADD3 R2, R6, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R3, R7, 0x1, RZ ; /* 0x0000000107037810 */
/* 0x000fce0007ffe0ff */
/*0350*/ @P1 IMAD.MOV R2, RZ, RZ, R6 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0206 */
/*0360*/ @!P0 IMAD.MOV R3, RZ, RZ, R7 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0207 */
/*0370*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0380*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0390*/ BRA 0xa70 ; /* 0x000006d000007947 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ IMAD.WIDE.U32 R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe200078e0007 */
/*03d0*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000f62000c1e1900 */
/*0400*/ BSSY B1, 0x580 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0410*/ IADD3 R10, R12, -c[0x3][0x0], RZ ; /* 0x80c000000c0a7a10 */
/* 0x004fc40007ffe0ff */
/*0420*/ IADD3 R8, R15, -c[0x3][0x4], RZ ; /* 0x80c001000f087a10 */
/* 0x008fe20007ffe0ff */
/*0430*/ IMAD.IADD R13, R14, 0x1, -R15 ; /* 0x000000010e0d7824 */
/* 0x010fe400078e0a0f */
/*0440*/ IMAD.IADD R11, R17, 0x1, -R12 ; /* 0x00000001110b7824 */
/* 0x020fe400078e0a0c */
/*0450*/ IMAD R10, R10, R13, RZ ; /* 0x0000000d0a0a7224 */
/* 0x000fc800078e02ff */
/*0460*/ IMAD R8, R8, R11, -R10 ; /* 0x0000000b08087224 */
/* 0x000fca00078e0a0a */
/*0470*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0480*/ @P0 ISETP.GE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800080c */
/* 0x000fe20003f26270 */
/*0490*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff080424 */
/* 0x000fca00078e00ff */
/*04a0*/ @P0 SEL R8, R8, 0x1, !P1 ; /* 0x0000000108080807 */
/* 0x000fe20004800000 */
/*04b0*/ @P0 BRA 0x570 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R8, -R17, c[0x3][0x0], RZ ; /* 0x00c0000011087a10 */
/* 0x000fe40007ffe1ff */
/*04d0*/ IADD3 R10, -R12, c[0x3][0x0], RZ ; /* 0x00c000000c0a7a10 */
/* 0x000fe40007ffe1ff */
/*04e0*/ IADD3 R11, -R14, c[0x3][0x4], RZ ; /* 0x00c001000e0b7a10 */
/* 0x000fe20007ffe1ff */
/*04f0*/ IMAD R8, R8, R8, RZ ; /* 0x0000000808087224 */
/* 0x000fe200078e02ff */
/*0500*/ IADD3 R13, -R15, c[0x3][0x4], RZ ; /* 0x00c001000f0d7a10 */
/* 0x000fe20007ffe1ff */
/*0510*/ IMAD R10, R10, R10, RZ ; /* 0x0000000a0a0a7224 */
/* 0x000fe400078e02ff */
/*0520*/ IMAD R8, R11, R11, R8 ; /* 0x0000000b0b087224 */
/* 0x000fc400078e0208 */
/*0530*/ IMAD R13, R13, R13, R10 ; /* 0x0000000d0d0d7224 */
/* 0x000fca00078e020a */
/*0540*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06070 */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fca00078e00ff */
/*0560*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fe40000000000 */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*0590*/ @P0 BRA 0xa70 ; /* 0x000004d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0001e8000c101904 */
/*05b0*/ STG.E [R4.64+0x4], R14 ; /* 0x0000040e04007986 */
/* 0x0001e8000c101904 */
/*05c0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0001e8000c101904 */
/*05d0*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0001e2000c101904 */
/*05e0*/ BRA 0xa70 ; /* 0x0000048000007947 */
/* 0x000fea0003800000 */
/*05f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0600*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ IMAD.WIDE.U32 R4, R8, R6, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe200078e0006 */
/*0620*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee8000c1e1900 */
/*0630*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000f62000c1e1900 */
/*0650*/ BSSY B1, 0x7d0 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0660*/ IADD3 R10, R12, -c[0x3][0x0], RZ ; /* 0x80c000000c0a7a10 */
/* 0x004fc40007ffe0ff */
/*0670*/ IADD3 R8, R15, -c[0x3][0x4], RZ ; /* 0x80c001000f087a10 */
/* 0x008fe20007ffe0ff */
/*0680*/ IMAD.IADD R13, R14, 0x1, -R15 ; /* 0x000000010e0d7824 */
/* 0x010fe400078e0a0f */
/*0690*/ IMAD.IADD R11, R17, 0x1, -R12 ; /* 0x00000001110b7824 */
/* 0x020fe400078e0a0c */
/*06a0*/ IMAD R10, R10, R13, RZ ; /* 0x0000000d0a0a7224 */
/* 0x000fc800078e02ff */
/*06b0*/ IMAD R8, R8, R11, -R10 ; /* 0x0000000b08087224 */
/* 0x000fca00078e0a0a */
/*06c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*06d0*/ @P0 ISETP.GE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800080c */
/* 0x000fe20003f26270 */
/*06e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff080424 */
/* 0x000fca00078e00ff */
/*06f0*/ @P0 SEL R8, R8, 0x1, !P1 ; /* 0x0000000108080807 */
/* 0x000fe20004800000 */
/*0700*/ @P0 BRA 0x7c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R8, -R17, c[0x3][0x0], RZ ; /* 0x00c0000011087a10 */
/* 0x000fe40007ffe1ff */
/*0720*/ IADD3 R10, -R12, c[0x3][0x0], RZ ; /* 0x00c000000c0a7a10 */
/* 0x000fe40007ffe1ff */
/*0730*/ IADD3 R11, -R14, c[0x3][0x4], RZ ; /* 0x00c001000e0b7a10 */
/* 0x000fe20007ffe1ff */
/*0740*/ IMAD R8, R8, R8, RZ ; /* 0x0000000808087224 */
/* 0x000fe200078e02ff */
/*0750*/ IADD3 R13, -R15, c[0x3][0x4], RZ ; /* 0x00c001000f0d7a10 */
/* 0x000fe20007ffe1ff */
/*0760*/ IMAD R10, R10, R10, RZ ; /* 0x0000000a0a0a7224 */
/* 0x000fe400078e02ff */
/*0770*/ IMAD R8, R11, R11, R8 ; /* 0x0000000b0b087224 */
/* 0x000fc400078e0208 */
/*0780*/ IMAD R13, R13, R13, R10 ; /* 0x0000000d0d0d7224 */
/* 0x000fca00078e020a */
/*0790*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06070 */
/*07a0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fca00078e00ff */
/*07b0*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fe40000000000 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*07e0*/ @P0 BRA 0xa70 ; /* 0x0000028000000947 */
/* 0x000fea0003800000 */
/*07f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*0800*/ STG.E [R2.64+0x4], R14 ; /* 0x0000040e02007986 */
/* 0x0001e8000c101904 */
/*0810*/ STG.E [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0001e8000c101904 */
/*0820*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0001e2000c101904 */
/*0830*/ BRA 0xa70 ; /* 0x0000023000007947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000f28000c1e1900 */
/*0870*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000f62000c1e1900 */
/*0880*/ BSSY B1, 0xa00 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0890*/ IADD3 R10, R15, -c[0x3][0x0], RZ ; /* 0x80c000000f0a7a10 */
/* 0x004fc40007ffe0ff */
/*08a0*/ IADD3 R8, R17, -c[0x3][0x4], RZ ; /* 0x80c0010011087a10 */
/* 0x008fe20007ffe0ff */
/*08b0*/ IMAD.IADD R13, R14, 0x1, -R17 ; /* 0x000000010e0d7824 */
/* 0x010fe400078e0a11 */
/*08c0*/ IMAD.IADD R11, R12, 0x1, -R15 ; /* 0x000000010c0b7824 */
/* 0x020fe400078e0a0f */
/*08d0*/ IMAD R10, R10, R13, RZ ; /* 0x0000000d0a0a7224 */
/* 0x000fc800078e02ff */
/*08e0*/ IMAD R8, R8, R11, -R10 ; /* 0x0000000b08087224 */
/* 0x000fca00078e0a0a */
/*08f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0900*/ @P0 ISETP.GE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800080c */
/* 0x000fe20003f26270 */
/*0910*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff080424 */
/* 0x000fca00078e00ff */
/*0920*/ @P0 SEL R8, R8, 0x1, !P1 ; /* 0x0000000108080807 */
/* 0x000fe20004800000 */
/*0930*/ @P0 BRA 0x9f0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0940*/ IADD3 R8, -R12, c[0x3][0x0], RZ ; /* 0x00c000000c087a10 */
/* 0x000fe40007ffe1ff */
/*0950*/ IADD3 R10, -R15, c[0x3][0x0], RZ ; /* 0x00c000000f0a7a10 */
/* 0x000fe40007ffe1ff */
/*0960*/ IADD3 R11, -R14, c[0x3][0x4], RZ ; /* 0x00c001000e0b7a10 */
/* 0x000fe20007ffe1ff */
/*0970*/ IMAD R8, R8, R8, RZ ; /* 0x0000000808087224 */
/* 0x000fe200078e02ff */
/*0980*/ IADD3 R13, -R17, c[0x3][0x4], RZ ; /* 0x00c00100110d7a10 */
/* 0x000fe20007ffe1ff */
/*0990*/ IMAD R10, R10, R10, RZ ; /* 0x0000000a0a0a7224 */
/* 0x000fe400078e02ff */
/*09a0*/ IMAD R8, R11, R11, R8 ; /* 0x0000000b0b087224 */
/* 0x000fc400078e0208 */
/*09b0*/ IMAD R13, R13, R13, R10 ; /* 0x0000000d0d0d7224 */
/* 0x000fca00078e020a */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06070 */
/*09d0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fca00078e00ff */
/*09e0*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fe40000000000 */
/*09f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*0a10*/ @!P0 STG.E [R2.64], R12 ; /* 0x0000000c02008986 */
/* 0x0001e2000c101904 */
/*0a20*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ @!P0 STG.E [R2.64+0x4], R14 ; /* 0x0000040e02008986 */
/* 0x0001e8000c101904 */
/*0a50*/ @!P0 STG.E [R4.64], R15 ; /* 0x0000000f04008986 */
/* 0x0001e8000c101904 */
/*0a60*/ @!P0 STG.E [R4.64+0x4], R17 ; /* 0x0000041104008986 */
/* 0x0001e4000c101904 */
/*0a70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a80*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f24070 */
/*0a90*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc40003f04070 */
/*0aa0*/ ISETP.GT.U32.AND P2, PT, R6, R9, P1 ; /* 0x000000090600720c */
/* 0x000fda0000f44070 */
/*0ab0*/ @!P2 BRA 0x250 ; /* 0xfffff7900000a947 */
/* 0x000fea000383ffff */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stack>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
using namespace std;
struct Point {
/* it will represent a point */
int x, y;
};
__constant__ Point d_p0[1];
__device__ int distSq(Point p1, Point p2)
{
return (p1.x - p2.x)*(p1.x - p2.x) +
(p1.y - p2.y)*(p1.y - p2.y);
}
// To find orientation of ordered triplet (p, q, r).
// The function returns following values
// 0 --> p, q and r are colinear
// 1 --> Clockwise
// 2 --> Counterclockwise
__device__ int d_orientation(Point p, Point q, Point r)
{
int val = (q.y - p.y) * (r.x - q.x) -
(q.x - p.x) * (r.y - q.y);
if (val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
__device__ int compare(Point p1,Point p2){
// Find orientation with respect to the first point
int o = d_orientation(d_p0[0], p1, p2);
if(o == 0)
return (distSq(d_p0[0], p2) >= distSq(d_p0[0],p1))? -1 : 1;
return (o == 2)? -1: 1;
}
__device__ void swap(Point *points,uint lowIndex,uint upIndex){
/* it will swap two points */
Point aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(Point* points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
Point p1 = points[lowG1];
Point p2 = points[lowG2];
if(compare(p1,p2) == 1){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
Point p1 = points[lowG1];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
Point p1 = points[lowG2];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void checkCudaState(cudaError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != cudaSuccess) cout << message;
}
__host__ Point nextToTop(stack<Point> &S){
/* it will find next to top in a stack */
Point p = S.top();
S.pop();
Point res = S.top();
S.push(p);
return res;
}
__host__ void swap(Point &p1, Point &p2){
/* it will swap two points */
Point temp = p1;
p1 = p2;
p2 = temp;
}
__host__ int h_orientation(Point p, Point q, Point r){
/* it will determine orientation between three points */
int val = (q.y - p.y) * (r.x - q.x) - (q.x - p.x) * (r.y - q.y);
if(val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
// Prints convex hull of a set of n points.
__host__ void convexHull(Point *h_points, int n){
/* it will find convex hull of a set of points */
cudaError_t cudaState = cudaSuccess;
size_t size = n*sizeof(Point);
Point *h_result = NULL, *d_points = NULL;
h_result = (Point *) malloc(size);
cudaState = cudaMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data for d_points\n");
if(d_points != NULL){
// Find the bottommost point
int ymin = h_points[0].y, min = 0;
for(int i = 1; i < n; i++){
int y = h_points[i].y;
// Pick the bottom-most or chose the left
// most point in case of tie
if((y < ymin) || (ymin == y && h_points[i].x < h_points[min].x))
ymin = h_points[i].y, min = i;
}
// Place the bottom-most point at first position
swap(h_points[0], h_points[min]);
// Sort n-1 points with respect to the first point.
// A point p1 comes before p2 in sorted ouput if p2
// has larger polar angle (in counterclockwise
// direction) than p1
cudaState = cudaMemcpyToSymbol(d_p0,h_points,sizeof(Point));
checkCudaState(cudaState,"Impossible copy data from host to device\n");
cudaState = cudaMemcpy(d_points,h_points,size,cudaMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
dim3 gridSize((int)(ceil(n/1024.0)),1,1);
dim3 blockSize(1024,1,1);
uint i = 1;
while(pow(2,i) <= n){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),n);
cudaDeviceSynchronize();
i++;
}
cudaState = cudaMemcpy(h_result,d_points,size,cudaMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
h_result[0] = h_points[0];
// If two or more points make same angle with p0,
// Remove all but the one that is farthest from p0
// Remember that, in above sorting, our criteria was
// to keep the farthest point at the end when more than
// one points have same angle.
int m = 1; // Initialize size of modified array
for(int i=1; i<n; i++){
// Keep removing i while angle of i and i+1 is same
// with respect to p0
while(i < n-1 && h_orientation(h_points[0],h_result[i],h_result[i+1]) == 0)
i++;
h_result[m] = h_result[i];
m++; // Update size of modified array
}
// If modified array of points has less than 3 points,
// convex hull is not possible
if (m < 3) return;
// Create an empty stack and push first three points
// to it.
stack<Point> S;
S.push(h_result[0]);
S.push(h_result[1]);
S.push(h_result[2]);
// Process remaining n-3 points
for(int i = 3; i < m; i++){
// Keep removing top while the angle formed by
// points next-to-top, top, and h_result[i] makes
// a non-left turn
while(h_orientation(nextToTop(S), S.top(), h_result[i]) != 2)
S.pop();
S.push(h_result[i]);
}
// Now stack has the output points, print contents of stack
while(!S.empty()){
Point p = S.top();
cout << "(" << p.x << ", " << p.y <<")" << endl;
S.pop();
}
}
if(h_result != NULL) free(h_result);
if(d_points != NULL) cudaFree(d_points);
}
// Driver program to test above functions
int main() {
uint n = 9;
size_t size = n*sizeof(Point);
Point *h_points = NULL;
h_points = (Point *) malloc(size);
if(h_points != NULL){
h_points[0].x = 0; h_points[0].y = 3;
h_points[1].x = 1; h_points[1].y = 1;
h_points[2].x = 2; h_points[2].y = 2;
h_points[3].x = 4; h_points[3].y = 4;
h_points[4].x = 0; h_points[4].y = 0;
h_points[5].x = 1; h_points[5].y = 2;
h_points[6].x = 3; h_points[6].y = 1;
h_points[7].x = 3; h_points[7].y = 3;
h_points[8].x = 2; h_points[8].y = 1;
convexHull(h_points, n);
}
if(h_points != NULL) free(h_points);
return 0;
} | .file "tmpxft_0010b0a3_00000000-6_graham.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3956:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3956:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6distSq5PointS_
.type _Z6distSq5PointS_, @function
_Z6distSq5PointS_:
.LFB3940:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3940:
.size _Z6distSq5PointS_, .-_Z6distSq5PointS_
.globl _Z13d_orientation5PointS_S_
.type _Z13d_orientation5PointS_S_, @function
_Z13d_orientation5PointS_S_:
.LFB3941:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3941:
.size _Z13d_orientation5PointS_S_, .-_Z13d_orientation5PointS_S_
.globl _Z7compare5PointS_
.type _Z7compare5PointS_, @function
_Z7compare5PointS_:
.LFB3942:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3942:
.size _Z7compare5PointS_, .-_Z7compare5PointS_
.globl _Z4swapP5Pointjj
.type _Z4swapP5Pointjj, @function
_Z4swapP5Pointjj:
.LFB3943:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3943:
.size _Z4swapP5Pointjj, .-_Z4swapP5Pointjj
.globl _Z14checkCudaStateR9cudaErrorPKc
.type _Z14checkCudaStateR9cudaErrorPKc, @function
_Z14checkCudaStateR9cudaErrorPKc:
.LFB3944:
.cfi_startproc
endbr64
cmpl $0, (%rdi)
jne .L18
ret
.L18:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
testq %rsi, %rsi
je .L19
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L11:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L11
.cfi_endproc
.LFE3944:
.size _Z14checkCudaStateR9cudaErrorPKc, .-_Z14checkCudaStateR9cudaErrorPKc
.globl _Z4swapR5PointS0_
.type _Z4swapR5PointS0_, @function
_Z4swapR5PointS0_:
.LFB3946:
.cfi_startproc
endbr64
movl (%rdi), %edx
movl 4(%rdi), %eax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movl %edx, (%rsi)
movl %eax, 4(%rsi)
ret
.cfi_endproc
.LFE3946:
.size _Z4swapR5PointS0_, .-_Z4swapR5PointS0_
.globl _Z13h_orientation5PointS_S_
.type _Z13h_orientation5PointS_S_, @function
_Z13h_orientation5PointS_S_:
.LFB3947:
.cfi_startproc
endbr64
movq %rsi, %rcx
sarq $32, %rcx
movq %rdi, %r8
sarq $32, %r8
movl %ecx, %eax
subl %r8d, %eax
movl %edx, %r8d
subl %esi, %r8d
imull %r8d, %eax
subl %edi, %esi
sarq $32, %rdx
subl %ecx, %edx
imull %edx, %esi
subl %esi, %eax
je .L21
testl %eax, %eax
setle %al
movzbl %al, %eax
addl $1, %eax
.L21:
ret
.cfi_endproc
.LFE3947:
.size _Z13h_orientation5PointS_S_, .-_Z13h_orientation5PointS_S_
.globl _Z30__device_stub__Z4sortP5PointjjP5Pointjj
.type _Z30__device_stub__Z4sortP5PointjjP5Pointjj, @function
_Z30__device_stub__Z4sortP5PointjjP5Pointjj:
.LFB3978:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4sortP5Pointjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3978:
.size _Z30__device_stub__Z4sortP5PointjjP5Pointjj, .-_Z30__device_stub__Z4sortP5PointjjP5Pointjj
.globl _Z4sortP5Pointjj
.type _Z4sortP5Pointjj, @function
_Z4sortP5Pointjj:
.LFB3979:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4sortP5PointjjP5Pointjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3979:
.size _Z4sortP5Pointjj, .-_Z4sortP5Pointjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4sortP5Pointjj"
.LC1:
.string "d_p0"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3981:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortP5Pointjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_p0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3981:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt11_Deque_baseI5PointSaIS0_EED2Ev,"axG",@progbits,_ZNSt11_Deque_baseI5PointSaIS0_EED5Ev,comdat
.align 2
.weak _ZNSt11_Deque_baseI5PointSaIS0_EED2Ev
.type _ZNSt11_Deque_baseI5PointSaIS0_EED2Ev, @function
_ZNSt11_Deque_baseI5PointSaIS0_EED2Ev:
.LFB4452:
.cfi_startproc
endbr64
cmpq $0, (%rdi)
je .L40
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq 72(%rdi), %rax
leaq 8(%rax), %rbp
movq 40(%rdi), %rbx
cmpq %rbp, %rbx
jnb .L36
.L37:
movq (%rbx), %rdi
movl $512, %esi
call _ZdlPvm@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jb .L37
.L36:
movq 8(%r12), %rax
leaq 0(,%rax,8), %rsi
movq (%r12), %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE4452:
.size _ZNSt11_Deque_baseI5PointSaIS0_EED2Ev, .-_ZNSt11_Deque_baseI5PointSaIS0_EED2Ev
.weak _ZNSt11_Deque_baseI5PointSaIS0_EED1Ev
.set _ZNSt11_Deque_baseI5PointSaIS0_EED1Ev,_ZNSt11_Deque_baseI5PointSaIS0_EED2Ev
.section .text._ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv,"axG",@progbits,_ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv,comdat
.align 2
.weak _ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv
.type _ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv, @function
_ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv:
.LFB4553:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 56(%rdi), %rdi
movl $512, %esi
call _ZdlPvm@PLT
movq 72(%rbx), %rax
leaq -8(%rax), %rdx
movq %rdx, 72(%rbx)
movq -8(%rax), %rax
movq %rax, 56(%rbx)
leaq 512(%rax), %rdx
movq %rdx, 64(%rbx)
addq $504, %rax
movq %rax, 48(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4553:
.size _ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv, .-_ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv
.section .rodata._ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cannot create std::deque larger than max_size()"
.section .text._ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_,"axG",@progbits,_ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_,comdat
.align 2
.weak _ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_
.type _ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_, @function
_ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_:
.LFB4555:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbp
movq 72(%rdi), %rdx
movq 40(%rdi), %rsi
movq %rdx, %r12
subq %rsi, %r12
movq %r12, %r13
sarq $3, %r13
movq 48(%rdi), %rax
subq 56(%rdi), %rax
sarq $3, %rax
cmpq $1, %rdx
movq %r13, %rcx
adcq $-1, %rcx
salq $6, %rcx
addq %rcx, %rax
movq 32(%rdi), %rcx
subq 16(%rdi), %rcx
sarq $3, %rcx
addq %rcx, %rax
movabsq $1152921504606846975, %rcx
cmpq %rcx, %rax
je .L58
movq %rdi, %rbx
movq 8(%rdi), %rcx
movq (%rdi), %rdi
movq %rdx, %rax
subq %rdi, %rax
sarq $3, %rax
movq %rcx, %r8
subq %rax, %r8
cmpq $1, %r8
jbe .L59
.L47:
movq 72(%rbx), %r12
movl $512, %edi
call _Znwm@PLT
movq %rax, 8(%r12)
movq 48(%rbx), %rax
movq 0(%rbp), %rdx
movq %rdx, (%rax)
movq 72(%rbx), %rax
leaq 8(%rax), %rdx
movq %rdx, 72(%rbx)
movq 8(%rax), %rax
movq %rax, 56(%rbx)
leaq 512(%rax), %rdx
movq %rdx, 64(%rbx)
movq %rax, 48(%rbx)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L59:
addq $2, %r13
leaq (%r13,%r13), %rax
cmpq %rcx, %rax
jnb .L48
subq %r13, %rcx
shrq %rcx
leaq (%rdi,%rcx,8), %r13
cmpq %rsi, %r13
jnb .L49
addq $8, %rdx
subq %rsi, %rdx
cmpq $8, %rdx
jle .L50
movq %r13, %rdi
call memmove@PLT
jmp .L51
.L50:
jne .L51
movq (%rsi), %rax
movq %rax, 0(%r13)
jmp .L51
.L49:
leaq 8(%r13,%r12), %rdi
addq $8, %rdx
subq %rsi, %rdx
cmpq $8, %rdx
jle .L52
subq %rdx, %rdi
call memmove@PLT
jmp .L51
.L52:
jne .L51
movq (%rsi), %rax
movq %rax, -8(%rdi)
jmp .L51
.L48:
testq %rcx, %rcx
movl $1, %eax
cmovne %rcx, %rax
leaq 2(%rcx,%rax), %r14
movq %r14, %rax
shrq $60, %rax
jne .L60
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r15
movq %r14, %rax
subq %r13, %rax
shrq %rax
leaq (%r15,%rax,8), %r13
movq 40(%rbx), %rsi
movq 72(%rbx), %rax
leaq 8(%rax), %rdx
subq %rsi, %rdx
cmpq $8, %rdx
jle .L55
movq %r13, %rdi
call memmove@PLT
.L56:
movq 8(%rbx), %rax
leaq 0(,%rax,8), %rsi
movq (%rbx), %rdi
call _ZdlPvm@PLT
movq %r15, (%rbx)
movq %r14, 8(%rbx)
.L51:
movq %r13, 40(%rbx)
movq 0(%r13), %rax
movq %rax, 24(%rbx)
addq $512, %rax
movq %rax, 32(%rbx)
addq %r12, %r13
movq %r13, 72(%rbx)
movq 0(%r13), %rax
movq %rax, 56(%rbx)
addq $512, %rax
movq %rax, 64(%rbx)
jmp .L47
.L60:
shrq $61, %r14
je .L54
call _ZSt28__throw_bad_array_new_lengthv@PLT
.L54:
call _ZSt17__throw_bad_allocv@PLT
.L55:
jne .L56
movq (%rsi), %rax
movq %rax, 0(%r13)
jmp .L56
.cfi_endproc
.LFE4555:
.size _ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_, .-_ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_
.text
.globl _Z9nextToTopRSt5stackI5PointSt5dequeIS0_SaIS0_EEE
.type _Z9nextToTopRSt5stackI5PointSt5dequeIS0_SaIS0_EEE, @function
_Z9nextToTopRSt5stackI5PointSt5dequeIS0_SaIS0_EEE:
.LFB3945:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq 48(%rdi), %rax
movq 72(%rdi), %rdx
cmpq 56(%rdi), %rax
je .L71
movq -8(%rax), %rdx
movq %rdx, (%rsp)
subq $8, %rax
movq %rax, 48(%rdi)
.L66:
movq 48(%rbx), %rax
movq 64(%rbx), %rdx
movq 72(%rbx), %rsi
movq %rax, %rcx
cmpq 56(%rbx), %rax
je .L72
.L63:
movl -8(%rcx), %ebp
movl -4(%rcx), %r12d
subq $8, %rdx
cmpq %rdx, %rax
je .L64
movq (%rsp), %rdx
movq %rdx, (%rax)
addq $8, 48(%rbx)
.L65:
salq $32, %r12
movl %ebp, %eax
orq %r12, %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L73
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movq -8(%rdx), %rax
movq 504(%rax), %rax
movq %rax, (%rsp)
call _ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv
jmp .L66
.L72:
movq -8(%rsi), %rcx
addq $512, %rcx
jmp .L63
.L64:
movq %rsp, %rsi
movq %rbx, %rdi
call _ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_
jmp .L65
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3945:
.size _Z9nextToTopRSt5stackI5PointSt5dequeIS0_SaIS0_EEE, .-_Z9nextToTopRSt5stackI5PointSt5dequeIS0_SaIS0_EEE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Impossible allocate data for d_points\n"
.align 8
.LC4:
.string "Impossible copy data from host to device\n"
.align 8
.LC10:
.string "Impossible copy data from device to host\n"
.section .rodata.str1.1
.LC11:
.string "("
.LC12:
.string ", "
.LC13:
.string ")"
.text
.globl _Z10convexHullP5Pointi
.type _Z10convexHullP5Pointi, @function
_Z10convexHullP5Pointi:
.LFB3948:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3948
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, %r12
movl %esi, %ebx
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq %esi, %r13
salq $3, %r13
movq $0, 32(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
leaq 32(%rsp), %rdi
movq %r13, %rsi
.LEHB0:
call cudaMalloc@PLT
movl %eax, 28(%rsp)
leaq 28(%rsp), %rdi
leaq .LC3(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
cmpq $0, 32(%rsp)
je .L75
movl 4(%r12), %r9d
cmpl $1, %ebx
jle .L123
movl %ebx, %r8d
movl %r9d, %ecx
movl $1, %eax
movl $0, %esi
jmp .L78
.L124:
movl %eax, %esi
movl %edx, %ecx
.L77:
addq $1, %rax
cmpq %rax, %r8
je .L76
.L78:
movl 4(%r12,%rax,8), %edx
cmpl %ecx, %edx
jl .L124
jne .L77
movslq %esi, %rdx
movl (%r12,%rdx,8), %edx
cmpl %edx, (%r12,%rax,8)
cmovl %eax, %esi
jmp .L77
.L123:
movl $0, %esi
.L76:
movslq %esi, %rsi
leaq (%r12,%rsi,8), %rax
movl (%r12), %edx
movq (%rax), %rcx
movq %rcx, (%r12)
movl %edx, (%rax)
movl %r9d, 4(%rax)
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
movq %r12, %rsi
leaq _ZL4d_p0(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, 28(%rsp)
leaq 28(%rsp), %rbx
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
movq %rbx, %rdi
call _Z14checkCudaStateR9cudaErrorPKc
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, 28(%rsp)
movq %rbp, %rsi
movq %rbx, %rdi
call _Z14checkCudaStateR9cudaErrorPKc
pxor %xmm7, %xmm7
cvtsi2sdl 12(%rsp), %xmm7
movq %xmm7, %r15
movapd %xmm7, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L79
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L79:
cvttsd2sil %xmm3, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, %ebx
jmp .L80
.L81:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
.L80:
movl %ebx, %eax
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movq %xmm5, %rbp
movapd %xmm5, %xmm1
movsd .LC9(%rip), %xmm0
call pow@PLT
movq %r15, %xmm6
comisd %xmm0, %xmm6
jb .L138
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L81
movq %rbp, %xmm1
movsd .LC9(%rip), %xmm0
call pow@PLT
cvttsd2siq %xmm0, %rsi
movl 12(%rsp), %edx
movq 32(%rsp), %rdi
call _Z30__device_stub__Z4sortP5PointjjP5Pointjj
jmp .L81
.L138:
movl $2, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, 28(%rsp)
leaq 28(%rsp), %rdi
leaq .LC10(%rip), %rsi
call _Z14checkCudaStateR9cudaErrorPKc
movq (%r12), %rax
movq %rax, (%r14)
movl $1, %r15d
movl $1, %ebp
movl 12(%rsp), %eax
leal -1(%rax), %r13d
cmpl $1, %eax
jg .L85
jmp .L74
.L87:
movslq %ebp, %rax
movq (%r14,%rax,8), %rax
movq %rax, (%r14,%r15,8)
addl $1, %ebp
leaq 1(%r15), %rax
cmpl %ebp, 12(%rsp)
jle .L89
movq %rax, %r15
.L85:
movslq %ebp, %rax
leaq (%r14,%rax,8), %rbx
cmpl %r13d, %ebp
jge .L87
.L88:
movq %rbx, %rax
addq $8, %rbx
movq (%rbx), %rdx
movq (%rax), %rsi
movq (%r12), %rdi
call _Z13h_orientation5PointS_S_
testl %eax, %eax
jne .L87
addl $1, %ebp
cmpl %r13d, %ebp
jne .L88
movl %r13d, %ebp
jmp .L87
.L89:
leal 1(%r15), %ebx
cmpl $2, %ebx
jle .L74
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $8, 72(%rsp)
movl $64, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
movq %rax, 64(%rsp)
leaq 24(%rax), %r12
movl $512, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, 24(%rbp)
movq %r12, 104(%rsp)
movq %rax, 88(%rsp)
leaq 512(%rax), %rdx
movq %rdx, 96(%rsp)
movq %r12, 136(%rsp)
movq %rax, 120(%rsp)
movq %rdx, 128(%rsp)
movq %rax, 80(%rsp)
movq (%r14), %rdx
movq %rdx, (%rax)
movq 8(%r14), %rdx
movq %rdx, 8(%rax)
movq 16(%r14), %rdx
movq %rdx, 16(%rax)
addq $24, %rax
movq %rax, 112(%rsp)
movl %r15d, 12(%rsp)
leaq 24(%r14), %r13
movl $3, %r15d
leaq 64(%rsp), %rbp
cmpl $3, %ebx
jg .L101
.L94:
movq 112(%rsp), %rbx
cmpq 80(%rsp), %rbx
je .L109
leaq _ZSt4cout(%rip), %r13
jmp .L117
.L131:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L96
call __stack_chk_fail@PLT
.L96:
.LEHB2:
call __cxa_rethrow@PLT
.LEHE2:
.L130:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq %rbx, %rdi
call __cxa_begin_catch@PLT
movl $64, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L98
call __stack_chk_fail@PLT
.L98:
.LEHB3:
call __cxa_rethrow@PLT
.LEHE3:
.L129:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L100
call __stack_chk_fail@PLT
.L100:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L102:
movq %rbp, %rdi
call _ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv
jmp .L108
.L140:
movq -8(%rax), %rbx
addq $512, %rbx
jmp .L104
.L141:
movq %rax, %rdi
movq (%r12), %rdx
movq -8(%rbx), %rsi
call _Z13h_orientation5PointS_S_
cmpl $2, %eax
je .L139
movq 112(%rsp), %rax
cmpq 120(%rsp), %rax
je .L102
subq $8, %rax
movq %rax, 112(%rsp)
.L108:
movq 112(%rsp), %rbx
movq 136(%rsp), %rax
cmpq 120(%rsp), %rbx
je .L140
.L104:
movq %rbp, %rdi
.LEHB5:
call _Z9nextToTopRSt5stackI5PointSt5dequeIS0_SaIS0_EEE
jmp .L141
.L139:
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
leaq -8(%rcx), %rdx
cmpq %rdx, %rax
je .L106
movq (%r12), %rdx
movq %rdx, (%rax)
addq $8, %rax
movq %rax, 112(%rsp)
.L107:
leal 1(%r15), %eax
addq $8, %r13
movl 12(%rsp), %ecx
cmpl %ecx, %r15d
jge .L94
movl %eax, %r15d
.L101:
movq %r13, %r12
jmp .L108
.L106:
leaq 64(%rsp), %rdi
movq %r12, %rsi
call _ZNSt5dequeI5PointSaIS0_EE16_M_push_back_auxIJRKS0_EEEvDpOT_
jmp .L107
.L145:
movq -8(%rdx), %rax
addq $512, %rax
jmp .L110
.L146:
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC13(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L142
cmpb $0, 56(%r15)
je .L113
movzbl 67(%r15), %esi
.L114:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L143
.L142:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L144
call _ZSt16__throw_bad_castv@PLT
.L128:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt11_Deque_baseI5PointSaIS0_EED2Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L120
call __stack_chk_fail@PLT
.L144:
call __stack_chk_fail@PLT
.L113:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L114
.L143:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpq %r12, %rbx
je .L115
subq $8, %rbx
movq %rbx, 112(%rsp)
.L116:
movq 112(%rsp), %rbx
cmpq 80(%rsp), %rbx
je .L109
.L117:
movq 120(%rsp), %r12
movq 136(%rsp), %rdx
movq %rbx, %rax
cmpq %r12, %rbx
je .L145
.L110:
movl -8(%rax), %ebp
movl -4(%rax), %r15d
movl $1, %edx
leaq .LC11(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE5:
jmp .L146
.L115:
leaq 64(%rsp), %rdi
call _ZNSt5dequeI5PointSaIS0_EE15_M_pop_back_auxEv
jmp .L116
.L109:
leaq 64(%rsp), %rdi
call _ZNSt11_Deque_baseI5PointSaIS0_EED2Ev
jmp .L121
.L120:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.L75:
testq %r14, %r14
je .L74
.L121:
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L74
call cudaFree@PLT
.LEHE6:
.L74:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L147
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L147:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3948:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3948-.LLSDATTD3948
.LLSDATTD3948:
.byte 0x1
.uleb128 .LLSDACSE3948-.LLSDACSB3948
.LLSDACSB3948:
.uleb128 .LEHB0-.LFB3948
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3948
.uleb128 .LEHE1-.LEHB1
.uleb128 .L131-.LFB3948
.uleb128 0x1
.uleb128 .LEHB2-.LFB3948
.uleb128 .LEHE2-.LEHB2
.uleb128 .L130-.LFB3948
.uleb128 0x3
.uleb128 .LEHB3-.LFB3948
.uleb128 .LEHE3-.LEHB3
.uleb128 .L129-.LFB3948
.uleb128 0
.uleb128 .LEHB4-.LFB3948
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3948
.uleb128 .LEHE5-.LEHB5
.uleb128 .L128-.LFB3948
.uleb128 0
.uleb128 .LEHB6-.LFB3948
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3948:
.byte 0x1
.byte 0
.byte 0
.byte 0x7d
.align 4
.long 0
.LLSDATT3948:
.text
.size _Z10convexHullP5Pointi, .-_Z10convexHullP5Pointi
.globl main
.type main, @function
main:
.LFB3953:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $72, %edi
call malloc@PLT
testq %rax, %rax
je .L149
movq %rax, %rbx
movl $0, (%rax)
movl $3, 4(%rax)
movl $1, 8(%rax)
movl $1, 12(%rax)
movl $2, 16(%rax)
movl $2, 20(%rax)
movl $4, 24(%rax)
movl $4, 28(%rax)
movl $0, 32(%rax)
movl $0, 36(%rax)
movl $1, 40(%rax)
movl $2, 44(%rax)
movl $3, 48(%rax)
movl $1, 52(%rax)
movl $3, 56(%rax)
movl $3, 60(%rax)
movl $2, 64(%rax)
movl $1, 68(%rax)
movl $9, %esi
movq %rax, %rdi
call _Z10convexHullP5Pointi
movq %rbx, %rdi
call free@PLT
.L149:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4d_p0
.comm _ZL4d_p0,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1062207488
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC9:
.long 0
.long 1073741824
.align 8
.LC14:
.long -1
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stack>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
using namespace std;
struct Point {
/* it will represent a point */
int x, y;
};
__constant__ Point d_p0[1];
__device__ int distSq(Point p1, Point p2)
{
return (p1.x - p2.x)*(p1.x - p2.x) +
(p1.y - p2.y)*(p1.y - p2.y);
}
// To find orientation of ordered triplet (p, q, r).
// The function returns following values
// 0 --> p, q and r are colinear
// 1 --> Clockwise
// 2 --> Counterclockwise
__device__ int d_orientation(Point p, Point q, Point r)
{
int val = (q.y - p.y) * (r.x - q.x) -
(q.x - p.x) * (r.y - q.y);
if (val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
__device__ int compare(Point p1,Point p2){
// Find orientation with respect to the first point
int o = d_orientation(d_p0[0], p1, p2);
if(o == 0)
return (distSq(d_p0[0], p2) >= distSq(d_p0[0],p1))? -1 : 1;
return (o == 2)? -1: 1;
}
__device__ void swap(Point *points,uint lowIndex,uint upIndex){
/* it will swap two points */
Point aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(Point* points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
Point p1 = points[lowG1];
Point p2 = points[lowG2];
if(compare(p1,p2) == 1){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
Point p1 = points[lowG1];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
Point p1 = points[lowG2];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void checkCudaState(cudaError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != cudaSuccess) cout << message;
}
__host__ Point nextToTop(stack<Point> &S){
/* it will find next to top in a stack */
Point p = S.top();
S.pop();
Point res = S.top();
S.push(p);
return res;
}
__host__ void swap(Point &p1, Point &p2){
/* it will swap two points */
Point temp = p1;
p1 = p2;
p2 = temp;
}
__host__ int h_orientation(Point p, Point q, Point r){
/* it will determine orientation between three points */
int val = (q.y - p.y) * (r.x - q.x) - (q.x - p.x) * (r.y - q.y);
if(val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
// Prints convex hull of a set of n points.
__host__ void convexHull(Point *h_points, int n){
/* it will find convex hull of a set of points */
cudaError_t cudaState = cudaSuccess;
size_t size = n*sizeof(Point);
Point *h_result = NULL, *d_points = NULL;
h_result = (Point *) malloc(size);
cudaState = cudaMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data for d_points\n");
if(d_points != NULL){
// Find the bottommost point
int ymin = h_points[0].y, min = 0;
for(int i = 1; i < n; i++){
int y = h_points[i].y;
// Pick the bottom-most or chose the left
// most point in case of tie
if((y < ymin) || (ymin == y && h_points[i].x < h_points[min].x))
ymin = h_points[i].y, min = i;
}
// Place the bottom-most point at first position
swap(h_points[0], h_points[min]);
// Sort n-1 points with respect to the first point.
// A point p1 comes before p2 in sorted ouput if p2
// has larger polar angle (in counterclockwise
// direction) than p1
cudaState = cudaMemcpyToSymbol(d_p0,h_points,sizeof(Point));
checkCudaState(cudaState,"Impossible copy data from host to device\n");
cudaState = cudaMemcpy(d_points,h_points,size,cudaMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
dim3 gridSize((int)(ceil(n/1024.0)),1,1);
dim3 blockSize(1024,1,1);
uint i = 1;
while(pow(2,i) <= n){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),n);
cudaDeviceSynchronize();
i++;
}
cudaState = cudaMemcpy(h_result,d_points,size,cudaMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
h_result[0] = h_points[0];
// If two or more points make same angle with p0,
// Remove all but the one that is farthest from p0
// Remember that, in above sorting, our criteria was
// to keep the farthest point at the end when more than
// one points have same angle.
int m = 1; // Initialize size of modified array
for(int i=1; i<n; i++){
// Keep removing i while angle of i and i+1 is same
// with respect to p0
while(i < n-1 && h_orientation(h_points[0],h_result[i],h_result[i+1]) == 0)
i++;
h_result[m] = h_result[i];
m++; // Update size of modified array
}
// If modified array of points has less than 3 points,
// convex hull is not possible
if (m < 3) return;
// Create an empty stack and push first three points
// to it.
stack<Point> S;
S.push(h_result[0]);
S.push(h_result[1]);
S.push(h_result[2]);
// Process remaining n-3 points
for(int i = 3; i < m; i++){
// Keep removing top while the angle formed by
// points next-to-top, top, and h_result[i] makes
// a non-left turn
while(h_orientation(nextToTop(S), S.top(), h_result[i]) != 2)
S.pop();
S.push(h_result[i]);
}
// Now stack has the output points, print contents of stack
while(!S.empty()){
Point p = S.top();
cout << "(" << p.x << ", " << p.y <<")" << endl;
S.pop();
}
}
if(h_result != NULL) free(h_result);
if(d_points != NULL) cudaFree(d_points);
}
// Driver program to test above functions
int main() {
uint n = 9;
size_t size = n*sizeof(Point);
Point *h_points = NULL;
h_points = (Point *) malloc(size);
if(h_points != NULL){
h_points[0].x = 0; h_points[0].y = 3;
h_points[1].x = 1; h_points[1].y = 1;
h_points[2].x = 2; h_points[2].y = 2;
h_points[3].x = 4; h_points[3].y = 4;
h_points[4].x = 0; h_points[4].y = 0;
h_points[5].x = 1; h_points[5].y = 2;
h_points[6].x = 3; h_points[6].y = 1;
h_points[7].x = 3; h_points[7].y = 3;
h_points[8].x = 2; h_points[8].y = 1;
convexHull(h_points, n);
}
if(h_points != NULL) free(h_points);
return 0;
} | #include <iostream>
#include <stack>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
struct Point {
/* it will represent a point */
int x, y;
};
__constant__ Point d_p0[1];
__device__ int distSq(Point p1, Point p2)
{
return (p1.x - p2.x)*(p1.x - p2.x) +
(p1.y - p2.y)*(p1.y - p2.y);
}
// To find orientation of ordered triplet (p, q, r).
// The function returns following values
// 0 --> p, q and r are colinear
// 1 --> Clockwise
// 2 --> Counterclockwise
__device__ int d_orientation(Point p, Point q, Point r)
{
int val = (q.y - p.y) * (r.x - q.x) -
(q.x - p.x) * (r.y - q.y);
if (val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
__device__ int compare(Point p1,Point p2){
// Find orientation with respect to the first point
int o = d_orientation(d_p0[0], p1, p2);
if(o == 0)
return (distSq(d_p0[0], p2) >= distSq(d_p0[0],p1))? -1 : 1;
return (o == 2)? -1: 1;
}
__device__ void swap(Point *points,uint lowIndex,uint upIndex){
/* it will swap two points */
Point aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(Point* points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
Point p1 = points[lowG1];
Point p2 = points[lowG2];
if(compare(p1,p2) == 1){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
Point p1 = points[lowG1];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
Point p1 = points[lowG2];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void checkCudaState(hipError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != hipSuccess) cout << message;
}
__host__ Point nextToTop(stack<Point> &S){
/* it will find next to top in a stack */
Point p = S.top();
S.pop();
Point res = S.top();
S.push(p);
return res;
}
__host__ void swap(Point &p1, Point &p2){
/* it will swap two points */
Point temp = p1;
p1 = p2;
p2 = temp;
}
__host__ int h_orientation(Point p, Point q, Point r){
/* it will determine orientation between three points */
int val = (q.y - p.y) * (r.x - q.x) - (q.x - p.x) * (r.y - q.y);
if(val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
// Prints convex hull of a set of n points.
__host__ void convexHull(Point *h_points, int n){
/* it will find convex hull of a set of points */
hipError_t cudaState = hipSuccess;
size_t size = n*sizeof(Point);
Point *h_result = NULL, *d_points = NULL;
h_result = (Point *) malloc(size);
cudaState = hipMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data for d_points\n");
if(d_points != NULL){
// Find the bottommost point
int ymin = h_points[0].y, min = 0;
for(int i = 1; i < n; i++){
int y = h_points[i].y;
// Pick the bottom-most or chose the left
// most point in case of tie
if((y < ymin) || (ymin == y && h_points[i].x < h_points[min].x))
ymin = h_points[i].y, min = i;
}
// Place the bottom-most point at first position
swap(h_points[0], h_points[min]);
// Sort n-1 points with respect to the first point.
// A point p1 comes before p2 in sorted ouput if p2
// has larger polar angle (in counterclockwise
// direction) than p1
cudaState = hipMemcpyToSymbol(HIP_SYMBOL(d_p0),h_points,sizeof(Point));
checkCudaState(cudaState,"Impossible copy data from host to device\n");
cudaState = hipMemcpy(d_points,h_points,size,hipMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
dim3 gridSize((int)(ceil(n/1024.0)),1,1);
dim3 blockSize(1024,1,1);
uint i = 1;
while(pow(2,i) <= n){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),n);
hipDeviceSynchronize();
i++;
}
cudaState = hipMemcpy(h_result,d_points,size,hipMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
h_result[0] = h_points[0];
// If two or more points make same angle with p0,
// Remove all but the one that is farthest from p0
// Remember that, in above sorting, our criteria was
// to keep the farthest point at the end when more than
// one points have same angle.
int m = 1; // Initialize size of modified array
for(int i=1; i<n; i++){
// Keep removing i while angle of i and i+1 is same
// with respect to p0
while(i < n-1 && h_orientation(h_points[0],h_result[i],h_result[i+1]) == 0)
i++;
h_result[m] = h_result[i];
m++; // Update size of modified array
}
// If modified array of points has less than 3 points,
// convex hull is not possible
if (m < 3) return;
// Create an empty stack and push first three points
// to it.
stack<Point> S;
S.push(h_result[0]);
S.push(h_result[1]);
S.push(h_result[2]);
// Process remaining n-3 points
for(int i = 3; i < m; i++){
// Keep removing top while the angle formed by
// points next-to-top, top, and h_result[i] makes
// a non-left turn
while(h_orientation(nextToTop(S), S.top(), h_result[i]) != 2)
S.pop();
S.push(h_result[i]);
}
// Now stack has the output points, print contents of stack
while(!S.empty()){
Point p = S.top();
cout << "(" << p.x << ", " << p.y <<")" << endl;
S.pop();
}
}
if(h_result != NULL) free(h_result);
if(d_points != NULL) hipFree(d_points);
}
// Driver program to test above functions
int main() {
uint n = 9;
size_t size = n*sizeof(Point);
Point *h_points = NULL;
h_points = (Point *) malloc(size);
if(h_points != NULL){
h_points[0].x = 0; h_points[0].y = 3;
h_points[1].x = 1; h_points[1].y = 1;
h_points[2].x = 2; h_points[2].y = 2;
h_points[3].x = 4; h_points[3].y = 4;
h_points[4].x = 0; h_points[4].y = 0;
h_points[5].x = 1; h_points[5].y = 2;
h_points[6].x = 3; h_points[6].y = 1;
h_points[7].x = 3; h_points[7].y = 3;
h_points[8].x = 2; h_points[8].y = 1;
convexHull(h_points, n);
}
if(h_points != NULL) free(h_points);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stack>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
struct Point {
/* it will represent a point */
int x, y;
};
__constant__ Point d_p0[1];
__device__ int distSq(Point p1, Point p2)
{
return (p1.x - p2.x)*(p1.x - p2.x) +
(p1.y - p2.y)*(p1.y - p2.y);
}
// To find orientation of ordered triplet (p, q, r).
// The function returns following values
// 0 --> p, q and r are colinear
// 1 --> Clockwise
// 2 --> Counterclockwise
__device__ int d_orientation(Point p, Point q, Point r)
{
int val = (q.y - p.y) * (r.x - q.x) -
(q.x - p.x) * (r.y - q.y);
if (val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
__device__ int compare(Point p1,Point p2){
// Find orientation with respect to the first point
int o = d_orientation(d_p0[0], p1, p2);
if(o == 0)
return (distSq(d_p0[0], p2) >= distSq(d_p0[0],p1))? -1 : 1;
return (o == 2)? -1: 1;
}
__device__ void swap(Point *points,uint lowIndex,uint upIndex){
/* it will swap two points */
Point aux = points[lowIndex];
points[lowIndex] = points[upIndex];
points[upIndex] = aux;
}
__global__ void sort(Point* points,uint phase,uint n){
/* it will sort with points array with respect to phase*/
uint ti = blockIdx.x*blockDim.x+threadIdx.x;
if(ti >= n || ti == 0) return;
if(ti%phase == 0){ // multiplier phase
uint top = ti, lower = (top - phase) + 1;
uint middle = lower + phase/2;
uint lowG1 = lower, lowG2 = middle, topG1 = middle-1, topG2 = top;
while(true){
if(lowG1 > topG1 && lowG2 > topG2) break;
// --------------------- case 1 ---------------------
if(lowG1 <= topG1 && lowG2 <= topG2){
Point p1 = points[lowG1];
Point p2 = points[lowG2];
if(compare(p1,p2) == 1){
swap(points,lowG1,lowG2);
lowG2++;
}
else lowG1++;
}
// --------------------- case 2 ---------------------
else if(lowG1 < topG1 && lowG2 > topG2){
uint next = lowG1 + 1;
Point p1 = points[lowG1];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG1,next);
lowG1++;
}
// --------------------- case 3 ---------------------
else if(lowG2 < topG2 && lowG1 > topG1){
uint next = lowG2 + 1;
Point p1 = points[lowG2];
Point p2 = points[next];
if(compare(p1,p2) == 1)
swap(points,lowG2,next);
lowG2++;
}
else if(lowG1 == topG1)
lowG1++;
else if(lowG2 == topG2)
lowG2++;
}
}
}
__host__ void checkCudaState(hipError_t& cudaState,const char *message){
/* it will print an error message if there is */
if(cudaState != hipSuccess) cout << message;
}
__host__ Point nextToTop(stack<Point> &S){
/* it will find next to top in a stack */
Point p = S.top();
S.pop();
Point res = S.top();
S.push(p);
return res;
}
__host__ void swap(Point &p1, Point &p2){
/* it will swap two points */
Point temp = p1;
p1 = p2;
p2 = temp;
}
__host__ int h_orientation(Point p, Point q, Point r){
/* it will determine orientation between three points */
int val = (q.y - p.y) * (r.x - q.x) - (q.x - p.x) * (r.y - q.y);
if(val == 0) return 0; // colinear
return (val > 0)? 1: 2; // clock or counterclock wise
}
// Prints convex hull of a set of n points.
__host__ void convexHull(Point *h_points, int n){
/* it will find convex hull of a set of points */
hipError_t cudaState = hipSuccess;
size_t size = n*sizeof(Point);
Point *h_result = NULL, *d_points = NULL;
h_result = (Point *) malloc(size);
cudaState = hipMalloc((void**)&d_points,size);
checkCudaState(cudaState,"Impossible allocate data for d_points\n");
if(d_points != NULL){
// Find the bottommost point
int ymin = h_points[0].y, min = 0;
for(int i = 1; i < n; i++){
int y = h_points[i].y;
// Pick the bottom-most or chose the left
// most point in case of tie
if((y < ymin) || (ymin == y && h_points[i].x < h_points[min].x))
ymin = h_points[i].y, min = i;
}
// Place the bottom-most point at first position
swap(h_points[0], h_points[min]);
// Sort n-1 points with respect to the first point.
// A point p1 comes before p2 in sorted ouput if p2
// has larger polar angle (in counterclockwise
// direction) than p1
cudaState = hipMemcpyToSymbol(HIP_SYMBOL(d_p0),h_points,sizeof(Point));
checkCudaState(cudaState,"Impossible copy data from host to device\n");
cudaState = hipMemcpy(d_points,h_points,size,hipMemcpyHostToDevice);
checkCudaState(cudaState,"Impossible copy data from host to device\n");
dim3 gridSize((int)(ceil(n/1024.0)),1,1);
dim3 blockSize(1024,1,1);
uint i = 1;
while(pow(2,i) <= n){
sort<<<gridSize,blockSize>>>(d_points,pow(2,i),n);
hipDeviceSynchronize();
i++;
}
cudaState = hipMemcpy(h_result,d_points,size,hipMemcpyDeviceToHost);
checkCudaState(cudaState,"Impossible copy data from device to host\n");
h_result[0] = h_points[0];
// If two or more points make same angle with p0,
// Remove all but the one that is farthest from p0
// Remember that, in above sorting, our criteria was
// to keep the farthest point at the end when more than
// one points have same angle.
int m = 1; // Initialize size of modified array
for(int i=1; i<n; i++){
// Keep removing i while angle of i and i+1 is same
// with respect to p0
while(i < n-1 && h_orientation(h_points[0],h_result[i],h_result[i+1]) == 0)
i++;
h_result[m] = h_result[i];
m++; // Update size of modified array
}
// If modified array of points has less than 3 points,
// convex hull is not possible
if (m < 3) return;
// Create an empty stack and push first three points
// to it.
stack<Point> S;
S.push(h_result[0]);
S.push(h_result[1]);
S.push(h_result[2]);
// Process remaining n-3 points
for(int i = 3; i < m; i++){
// Keep removing top while the angle formed by
// points next-to-top, top, and h_result[i] makes
// a non-left turn
while(h_orientation(nextToTop(S), S.top(), h_result[i]) != 2)
S.pop();
S.push(h_result[i]);
}
// Now stack has the output points, print contents of stack
while(!S.empty()){
Point p = S.top();
cout << "(" << p.x << ", " << p.y <<")" << endl;
S.pop();
}
}
if(h_result != NULL) free(h_result);
if(d_points != NULL) hipFree(d_points);
}
// Driver program to test above functions
int main() {
uint n = 9;
size_t size = n*sizeof(Point);
Point *h_points = NULL;
h_points = (Point *) malloc(size);
if(h_points != NULL){
h_points[0].x = 0; h_points[0].y = 3;
h_points[1].x = 1; h_points[1].y = 1;
h_points[2].x = 2; h_points[2].y = 2;
h_points[3].x = 4; h_points[3].y = 4;
h_points[4].x = 0; h_points[4].y = 0;
h_points[5].x = 1; h_points[5].y = 2;
h_points[6].x = 3; h_points[6].y = 1;
h_points[7].x = 3; h_points[7].y = 3;
h_points[8].x = 2; h_points[8].y = 1;
convexHull(h_points, n);
}
if(h_points != NULL) free(h_points);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortP5Pointjj
.globl _Z4sortP5Pointjj
.p2align 8
.type _Z4sortP5Pointjj,@function
_Z4sortP5Pointjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_41
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_41
v_subrev_nc_u32_e32 v0, s2, v1
s_lshr_b32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v0, s2, v0
v_add_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s6, v2, v0
v_cmp_gt_u32_e64 s7, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s6, s7
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_41
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_p0@rel32@lo+4
s_addc_u32 s3, s3, d_p0@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_p0@rel32@lo+8
s_addc_u32 s5, s5, d_p0@rel32@hi+16
s_load_b64 s[0:1], s[0:1], 0x0
s_clause 0x1
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[4:5], 0x0
s_mov_b32 s4, 0
s_branch .LBB0_7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v2, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s6, v2, v0
v_cmp_gt_u32_e64 s7, v4, v1
s_and_b32 s5, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, exec_lo, s5
s_or_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_41
.LBB0_7:
s_or_b32 s5, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, -1
s_and_saveexec_b32 s8, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s8
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_lshlrev_b64 v[8:9], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v9, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[5:6], off
global_load_b64 v[11:12], v[7:8], off
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v3, s2, v9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v10, v12
v_subrev_nc_u32_e32 v15, s3, v10
v_sub_nc_u32_e32 v16, v11, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, v13
v_mad_u64_u32 v[13:14], null, v15, v16, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v13
s_xor_b32 s8, exec_lo, s8
v_cmp_gt_i32_e32 vcc_lo, 1, v13
v_cndmask_b32_e64 v3, 1, -1, vcc_lo
s_and_not1_saveexec_b32 s8, s8
v_sub_nc_u32_e32 v3, s2, v11
v_sub_nc_u32_e32 v9, s2, v9
v_sub_nc_u32_e32 v12, s3, v12
v_sub_nc_u32_e32 v13, s3, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v3, v3, v3
v_mul_lo_u32 v9, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, v12, v[3:4]
v_mad_u64_u32 v[11:12], null, v13, v13, v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v10, v11
v_cndmask_b32_e64 v3, -1, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s8, exec_lo
v_cmpx_ne_u32_e32 1, v3
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v2, 1, v2
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_16
s_clause 0x1
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[5:6], off
v_add_nc_u32_e32 v4, 1, v4
s_waitcnt vmcnt(1)
global_store_b64 v[5:6], v[9:10], off
s_waitcnt vmcnt(0)
global_store_b64 v[7:8], v[11:12], off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_17:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_6
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_xor_b32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s7, vcc_lo, s7
s_and_saveexec_b32 s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s8
s_cbranch_execz .LBB0_34
v_cmp_ge_u32_e32 vcc_lo, v4, v1
s_xor_b32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, vcc_lo, s6
s_and_saveexec_b32 s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s8
s_cbranch_execz .LBB0_25
s_mov_b32 s8, exec_lo
v_cmpx_ne_u32_e64 v2, v0
s_xor_b32 s8, exec_lo, s8
v_cmp_eq_u32_e32 vcc_lo, v4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v2, 1, v2
v_mov_b32_e32 v6, v4
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v2
.LBB0_25:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_33
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v4
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[3:4], 3, v[4:5]
v_lshlrev_b64 v[7:8], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[3:4], off
global_load_b64 v[11:12], v[7:8], off
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v5, s2, v9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v10, v12
v_subrev_nc_u32_e32 v15, s3, v10
v_sub_nc_u32_e32 v16, v11, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, v13
v_mad_u64_u32 v[13:14], null, v15, v16, v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v13
s_xor_b32 s8, exec_lo, s8
v_cmp_gt_i32_e32 vcc_lo, 1, v13
v_cndmask_b32_e64 v5, 1, -1, vcc_lo
s_and_not1_saveexec_b32 s8, s8
v_sub_nc_u32_e32 v5, s2, v11
v_sub_nc_u32_e32 v9, s2, v9
v_sub_nc_u32_e32 v12, s3, v12
v_sub_nc_u32_e32 v13, s3, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v5, v5, v5
v_mul_lo_u32 v9, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, v12, v[5:6]
v_mad_u64_u32 v[11:12], null, v13, v13, v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v10, v11
v_cndmask_b32_e64 v5, -1, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e32 1, v5
s_cbranch_execz .LBB0_32
s_clause 0x1
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[3:4], off
s_waitcnt vmcnt(1)
global_store_b64 v[3:4], v[9:10], off
s_waitcnt vmcnt(0)
global_store_b64 v[7:8], v[11:12], off
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v5, v2
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, v6
.LBB0_34:
s_and_not1_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v5, 1, v2
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[6:7], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[2:3], off
global_load_b64 v[10:11], v[6:7], off
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v12, s2, v8
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v9, v11
v_subrev_nc_u32_e32 v15, s3, v9
v_sub_nc_u32_e32 v16, v10, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v14, v12, v13
v_mad_u64_u32 v[12:13], null, v15, v16, v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v12
s_xor_b32 s7, exec_lo, s7
v_cmp_gt_i32_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v13, 1, -1, vcc_lo
s_and_not1_saveexec_b32 s7, s7
v_sub_nc_u32_e32 v10, s2, v10
v_sub_nc_u32_e32 v12, s2, v8
v_sub_nc_u32_e32 v13, s3, v11
v_sub_nc_u32_e32 v14, s3, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v8, v10, v10
v_mul_lo_u32 v10, v12, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, v13, v[8:9]
v_mad_u64_u32 v[8:9], null, v14, v14, v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v11, v8
v_cndmask_b32_e64 v13, -1, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 1, v13
s_cbranch_execz .LBB0_4
s_clause 0x1
global_load_b64 v[8:9], v[6:7], off
global_load_b64 v[10:11], v[2:3], off
s_waitcnt vmcnt(1)
global_store_b64 v[2:3], v[8:9], off
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[10:11], off
s_branch .LBB0_4
.LBB0_41:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortP5Pointjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortP5Pointjj, .Lfunc_end0-_Z4sortP5Pointjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_p0
.type d_p0,@object
.section .bss,"aw",@nobits
.globl d_p0
.p2align 2, 0x0
d_p0:
.zero 8
.size d_p0, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_p0
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortP5Pointjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortP5Pointjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4sortP5Pointjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0080*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f25070 */
/*0090*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0160*/ @P0 IADD3 R3, R3, -c[0x0][0x168], RZ ; /* 0x80005a0003030a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff039a12 */
/* 0x000fc800078e33ff */
/*0180*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01b0*/ IADD3 R9, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000097a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*01d0*/ IADD3 R6, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fc60007ffe0ff */
/*01e0*/ IADD3 R9, R9, UR4, RZ ; /* 0x0000000409097c10 */
/* 0x000fe4000fffe0ff */
/*01f0*/ IADD3 R7, R6.reuse, UR4, RZ ; /* 0x0000000406077c10 */
/* 0x040fe4000fffe0ff */
/*0200*/ ISETP.GT.U32.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600720c */
/* 0x0c0fe40003f44070 */
/*0210*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f24070 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fd60003f04070 */
/*0230*/ @P1 EXIT P2 ; /* 0x000000000000194d */
/* 0x000fea0001000000 */
/*0240*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0250*/ ISETP.GT.U32.AND P2, PT, R7.reuse, R0, PT ; /* 0x000000000700720c */
/* 0x040fe20003f44070 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.LE.U32.AND P3, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe20003f63070 */
/*0280*/ BSSY B0, 0xa80 ; /* 0x000007f000007945 */
/* 0x000fe40003800000 */
/*0290*/ IMAD.WIDE.U32 R4, R7, R8, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x001fc800078e0008 */
/*02a0*/ IMAD.WIDE.U32 R2, R6, R8, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0008 */
/*02b0*/ @!P2 BRA P3, 0x840 ; /* 0x000005800000a947 */
/* 0x000fea0001800000 */
/*02c0*/ ISETP.LT.U32.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f41070 */
/*02d0*/ @P1 BRA P2, 0x5f0 ; /* 0x0000031000001947 */
/* 0x000fea0001000000 */
/*02e0*/ ISETP.LT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f21070 */
/*02f0*/ @P0 BRA P1, 0x3a0 ; /* 0x000000a000000947 */
/* 0x000fea0000800000 */
/*0300*/ ISETP.NE.AND P0, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600720c */
/* 0x0c0fe40003f05270 */
/*0310*/ ISETP.NE.AND P1, PT, R6.reuse, R9, PT ; /* 0x000000090600720c */
/* 0x040fe40003f25270 */
/*0320*/ ISETP.EQ.AND P0, PT, R7.reuse, R0, P0 ; /* 0x000000000700720c */
/* 0x040fe40000702270 */
/*0330*/ IADD3 R2, R6, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R3, R7, 0x1, RZ ; /* 0x0000000107037810 */
/* 0x000fce0007ffe0ff */
/*0350*/ @P1 IMAD.MOV R2, RZ, RZ, R6 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0206 */
/*0360*/ @!P0 IMAD.MOV R3, RZ, RZ, R7 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0207 */
/*0370*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0380*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0390*/ BRA 0xa70 ; /* 0x000006d000007947 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ IMAD.WIDE.U32 R2, R8, R7, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe200078e0007 */
/*03d0*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000f62000c1e1900 */
/*0400*/ BSSY B1, 0x580 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0410*/ IADD3 R10, R12, -c[0x3][0x0], RZ ; /* 0x80c000000c0a7a10 */
/* 0x004fc40007ffe0ff */
/*0420*/ IADD3 R8, R15, -c[0x3][0x4], RZ ; /* 0x80c001000f087a10 */
/* 0x008fe20007ffe0ff */
/*0430*/ IMAD.IADD R13, R14, 0x1, -R15 ; /* 0x000000010e0d7824 */
/* 0x010fe400078e0a0f */
/*0440*/ IMAD.IADD R11, R17, 0x1, -R12 ; /* 0x00000001110b7824 */
/* 0x020fe400078e0a0c */
/*0450*/ IMAD R10, R10, R13, RZ ; /* 0x0000000d0a0a7224 */
/* 0x000fc800078e02ff */
/*0460*/ IMAD R8, R8, R11, -R10 ; /* 0x0000000b08087224 */
/* 0x000fca00078e0a0a */
/*0470*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0480*/ @P0 ISETP.GE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800080c */
/* 0x000fe20003f26270 */
/*0490*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff080424 */
/* 0x000fca00078e00ff */
/*04a0*/ @P0 SEL R8, R8, 0x1, !P1 ; /* 0x0000000108080807 */
/* 0x000fe20004800000 */
/*04b0*/ @P0 BRA 0x570 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R8, -R17, c[0x3][0x0], RZ ; /* 0x00c0000011087a10 */
/* 0x000fe40007ffe1ff */
/*04d0*/ IADD3 R10, -R12, c[0x3][0x0], RZ ; /* 0x00c000000c0a7a10 */
/* 0x000fe40007ffe1ff */
/*04e0*/ IADD3 R11, -R14, c[0x3][0x4], RZ ; /* 0x00c001000e0b7a10 */
/* 0x000fe20007ffe1ff */
/*04f0*/ IMAD R8, R8, R8, RZ ; /* 0x0000000808087224 */
/* 0x000fe200078e02ff */
/*0500*/ IADD3 R13, -R15, c[0x3][0x4], RZ ; /* 0x00c001000f0d7a10 */
/* 0x000fe20007ffe1ff */
/*0510*/ IMAD R10, R10, R10, RZ ; /* 0x0000000a0a0a7224 */
/* 0x000fe400078e02ff */
/*0520*/ IMAD R8, R11, R11, R8 ; /* 0x0000000b0b087224 */
/* 0x000fc400078e0208 */
/*0530*/ IMAD R13, R13, R13, R10 ; /* 0x0000000d0d0d7224 */
/* 0x000fca00078e020a */
/*0540*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06070 */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fca00078e00ff */
/*0560*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fe40000000000 */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*0590*/ @P0 BRA 0xa70 ; /* 0x000004d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0001e8000c101904 */
/*05b0*/ STG.E [R4.64+0x4], R14 ; /* 0x0000040e04007986 */
/* 0x0001e8000c101904 */
/*05c0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0001e8000c101904 */
/*05d0*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0001e2000c101904 */
/*05e0*/ BRA 0xa70 ; /* 0x0000048000007947 */
/* 0x000fea0003800000 */
/*05f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0600*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ IMAD.WIDE.U32 R4, R8, R6, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fe200078e0006 */
/*0620*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee8000c1e1900 */
/*0630*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000f62000c1e1900 */
/*0650*/ BSSY B1, 0x7d0 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0660*/ IADD3 R10, R12, -c[0x3][0x0], RZ ; /* 0x80c000000c0a7a10 */
/* 0x004fc40007ffe0ff */
/*0670*/ IADD3 R8, R15, -c[0x3][0x4], RZ ; /* 0x80c001000f087a10 */
/* 0x008fe20007ffe0ff */
/*0680*/ IMAD.IADD R13, R14, 0x1, -R15 ; /* 0x000000010e0d7824 */
/* 0x010fe400078e0a0f */
/*0690*/ IMAD.IADD R11, R17, 0x1, -R12 ; /* 0x00000001110b7824 */
/* 0x020fe400078e0a0c */
/*06a0*/ IMAD R10, R10, R13, RZ ; /* 0x0000000d0a0a7224 */
/* 0x000fc800078e02ff */
/*06b0*/ IMAD R8, R8, R11, -R10 ; /* 0x0000000b08087224 */
/* 0x000fca00078e0a0a */
/*06c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*06d0*/ @P0 ISETP.GE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800080c */
/* 0x000fe20003f26270 */
/*06e0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff080424 */
/* 0x000fca00078e00ff */
/*06f0*/ @P0 SEL R8, R8, 0x1, !P1 ; /* 0x0000000108080807 */
/* 0x000fe20004800000 */
/*0700*/ @P0 BRA 0x7c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R8, -R17, c[0x3][0x0], RZ ; /* 0x00c0000011087a10 */
/* 0x000fe40007ffe1ff */
/*0720*/ IADD3 R10, -R12, c[0x3][0x0], RZ ; /* 0x00c000000c0a7a10 */
/* 0x000fe40007ffe1ff */
/*0730*/ IADD3 R11, -R14, c[0x3][0x4], RZ ; /* 0x00c001000e0b7a10 */
/* 0x000fe20007ffe1ff */
/*0740*/ IMAD R8, R8, R8, RZ ; /* 0x0000000808087224 */
/* 0x000fe200078e02ff */
/*0750*/ IADD3 R13, -R15, c[0x3][0x4], RZ ; /* 0x00c001000f0d7a10 */
/* 0x000fe20007ffe1ff */
/*0760*/ IMAD R10, R10, R10, RZ ; /* 0x0000000a0a0a7224 */
/* 0x000fe400078e02ff */
/*0770*/ IMAD R8, R11, R11, R8 ; /* 0x0000000b0b087224 */
/* 0x000fc400078e0208 */
/*0780*/ IMAD R13, R13, R13, R10 ; /* 0x0000000d0d0d7224 */
/* 0x000fca00078e020a */
/*0790*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06070 */
/*07a0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fca00078e00ff */
/*07b0*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fe40000000000 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*07e0*/ @P0 BRA 0xa70 ; /* 0x0000028000000947 */
/* 0x000fea0003800000 */
/*07f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*0800*/ STG.E [R2.64+0x4], R14 ; /* 0x0000040e02007986 */
/* 0x0001e8000c101904 */
/*0810*/ STG.E [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0001e8000c101904 */
/*0820*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0001e2000c101904 */
/*0830*/ BRA 0xa70 ; /* 0x0000023000007947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000f28000c1e1900 */
/*0870*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000f62000c1e1900 */
/*0880*/ BSSY B1, 0xa00 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0890*/ IADD3 R10, R15, -c[0x3][0x0], RZ ; /* 0x80c000000f0a7a10 */
/* 0x004fc40007ffe0ff */
/*08a0*/ IADD3 R8, R17, -c[0x3][0x4], RZ ; /* 0x80c0010011087a10 */
/* 0x008fe20007ffe0ff */
/*08b0*/ IMAD.IADD R13, R14, 0x1, -R17 ; /* 0x000000010e0d7824 */
/* 0x010fe400078e0a11 */
/*08c0*/ IMAD.IADD R11, R12, 0x1, -R15 ; /* 0x000000010c0b7824 */
/* 0x020fe400078e0a0f */
/*08d0*/ IMAD R10, R10, R13, RZ ; /* 0x0000000d0a0a7224 */
/* 0x000fc800078e02ff */
/*08e0*/ IMAD R8, R8, R11, -R10 ; /* 0x0000000b08087224 */
/* 0x000fca00078e0a0a */
/*08f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0900*/ @P0 ISETP.GE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800080c */
/* 0x000fe20003f26270 */
/*0910*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff080424 */
/* 0x000fca00078e00ff */
/*0920*/ @P0 SEL R8, R8, 0x1, !P1 ; /* 0x0000000108080807 */
/* 0x000fe20004800000 */
/*0930*/ @P0 BRA 0x9f0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0940*/ IADD3 R8, -R12, c[0x3][0x0], RZ ; /* 0x00c000000c087a10 */
/* 0x000fe40007ffe1ff */
/*0950*/ IADD3 R10, -R15, c[0x3][0x0], RZ ; /* 0x00c000000f0a7a10 */
/* 0x000fe40007ffe1ff */
/*0960*/ IADD3 R11, -R14, c[0x3][0x4], RZ ; /* 0x00c001000e0b7a10 */
/* 0x000fe20007ffe1ff */
/*0970*/ IMAD R8, R8, R8, RZ ; /* 0x0000000808087224 */
/* 0x000fe200078e02ff */
/*0980*/ IADD3 R13, -R17, c[0x3][0x4], RZ ; /* 0x00c00100110d7a10 */
/* 0x000fe20007ffe1ff */
/*0990*/ IMAD R10, R10, R10, RZ ; /* 0x0000000a0a0a7224 */
/* 0x000fe400078e02ff */
/*09a0*/ IMAD R8, R11, R11, R8 ; /* 0x0000000b0b087224 */
/* 0x000fc400078e0208 */
/*09b0*/ IMAD R13, R13, R13, R10 ; /* 0x0000000d0d0d7224 */
/* 0x000fca00078e020a */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06070 */
/*09d0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fca00078e00ff */
/*09e0*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fe40000000000 */
/*09f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*0a10*/ @!P0 STG.E [R2.64], R12 ; /* 0x0000000c02008986 */
/* 0x0001e2000c101904 */
/*0a20*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ @!P0 STG.E [R2.64+0x4], R14 ; /* 0x0000040e02008986 */
/* 0x0001e8000c101904 */
/*0a50*/ @!P0 STG.E [R4.64], R15 ; /* 0x0000000f04008986 */
/* 0x0001e8000c101904 */
/*0a60*/ @!P0 STG.E [R4.64+0x4], R17 ; /* 0x0000041104008986 */
/* 0x0001e4000c101904 */
/*0a70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a80*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f24070 */
/*0a90*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc40003f04070 */
/*0aa0*/ ISETP.GT.U32.AND P2, PT, R6, R9, P1 ; /* 0x000000090600720c */
/* 0x000fda0000f44070 */
/*0ab0*/ @!P2 BRA 0x250 ; /* 0xfffff7900000a947 */
/* 0x000fea000383ffff */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortP5Pointjj
.globl _Z4sortP5Pointjj
.p2align 8
.type _Z4sortP5Pointjj,@function
_Z4sortP5Pointjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_41
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_41
v_subrev_nc_u32_e32 v0, s2, v1
s_lshr_b32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v0, s2, v0
v_add_nc_u32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s6, v2, v0
v_cmp_gt_u32_e64 s7, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s6, s7
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_41
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_p0@rel32@lo+4
s_addc_u32 s3, s3, d_p0@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_p0@rel32@lo+8
s_addc_u32 s5, s5, d_p0@rel32@hi+16
s_load_b64 s[0:1], s[0:1], 0x0
s_clause 0x1
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[4:5], 0x0
s_mov_b32 s4, 0
s_branch .LBB0_7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v2, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s6, v2, v0
v_cmp_gt_u32_e64 s7, v4, v1
s_and_b32 s5, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, exec_lo, s5
s_or_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_41
.LBB0_7:
s_or_b32 s5, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, -1
s_and_saveexec_b32 s8, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s8
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[6:7], 3, v[2:3]
v_lshlrev_b64 v[8:9], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v9, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[5:6], off
global_load_b64 v[11:12], v[7:8], off
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v3, s2, v9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v10, v12
v_subrev_nc_u32_e32 v15, s3, v10
v_sub_nc_u32_e32 v16, v11, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, v13
v_mad_u64_u32 v[13:14], null, v15, v16, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v13
s_xor_b32 s8, exec_lo, s8
v_cmp_gt_i32_e32 vcc_lo, 1, v13
v_cndmask_b32_e64 v3, 1, -1, vcc_lo
s_and_not1_saveexec_b32 s8, s8
v_sub_nc_u32_e32 v3, s2, v11
v_sub_nc_u32_e32 v9, s2, v9
v_sub_nc_u32_e32 v12, s3, v12
v_sub_nc_u32_e32 v13, s3, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v3, v3, v3
v_mul_lo_u32 v9, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, v12, v[3:4]
v_mad_u64_u32 v[11:12], null, v13, v13, v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v10, v11
v_cndmask_b32_e64 v3, -1, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s8, exec_lo
v_cmpx_ne_u32_e32 1, v3
s_xor_b32 s8, exec_lo, s8
v_add_nc_u32_e32 v2, 1, v2
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_16
s_clause 0x1
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[5:6], off
v_add_nc_u32_e32 v4, 1, v4
s_waitcnt vmcnt(1)
global_store_b64 v[5:6], v[9:10], off
s_waitcnt vmcnt(0)
global_store_b64 v[7:8], v[11:12], off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_17:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_6
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_xor_b32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s7, vcc_lo, s7
s_and_saveexec_b32 s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s8
s_cbranch_execz .LBB0_34
v_cmp_ge_u32_e32 vcc_lo, v4, v1
s_xor_b32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, vcc_lo, s6
s_and_saveexec_b32 s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s8
s_cbranch_execz .LBB0_25
s_mov_b32 s8, exec_lo
v_cmpx_ne_u32_e64 v2, v0
s_xor_b32 s8, exec_lo, s8
v_cmp_eq_u32_e32 vcc_lo, v4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v2, 1, v2
v_mov_b32_e32 v6, v4
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v2
.LBB0_25:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_33
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v4
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[3:4], 3, v[4:5]
v_lshlrev_b64 v[7:8], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[3:4], off
global_load_b64 v[11:12], v[7:8], off
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v5, s2, v9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v10, v12
v_subrev_nc_u32_e32 v15, s3, v10
v_sub_nc_u32_e32 v16, v11, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, v13
v_mad_u64_u32 v[13:14], null, v15, v16, v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v13
s_xor_b32 s8, exec_lo, s8
v_cmp_gt_i32_e32 vcc_lo, 1, v13
v_cndmask_b32_e64 v5, 1, -1, vcc_lo
s_and_not1_saveexec_b32 s8, s8
v_sub_nc_u32_e32 v5, s2, v11
v_sub_nc_u32_e32 v9, s2, v9
v_sub_nc_u32_e32 v12, s3, v12
v_sub_nc_u32_e32 v13, s3, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v5, v5, v5
v_mul_lo_u32 v9, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, v12, v[5:6]
v_mad_u64_u32 v[11:12], null, v13, v13, v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v10, v11
v_cndmask_b32_e64 v5, -1, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s8, exec_lo
v_cmpx_eq_u32_e32 1, v5
s_cbranch_execz .LBB0_32
s_clause 0x1
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[3:4], off
s_waitcnt vmcnt(1)
global_store_b64 v[3:4], v[9:10], off
s_waitcnt vmcnt(0)
global_store_b64 v[7:8], v[11:12], off
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v5, v2
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, v6
.LBB0_34:
s_and_not1_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v5, 1, v2
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[6:7], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[2:3], off
global_load_b64 v[10:11], v[6:7], off
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v12, s2, v8
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v9, v11
v_subrev_nc_u32_e32 v15, s3, v9
v_sub_nc_u32_e32 v16, v10, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v14, v12, v13
v_mad_u64_u32 v[12:13], null, v15, v16, v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v12
s_xor_b32 s7, exec_lo, s7
v_cmp_gt_i32_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v13, 1, -1, vcc_lo
s_and_not1_saveexec_b32 s7, s7
v_sub_nc_u32_e32 v10, s2, v10
v_sub_nc_u32_e32 v12, s2, v8
v_sub_nc_u32_e32 v13, s3, v11
v_sub_nc_u32_e32 v14, s3, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v8, v10, v10
v_mul_lo_u32 v10, v12, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, v13, v[8:9]
v_mad_u64_u32 v[8:9], null, v14, v14, v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, v11, v8
v_cndmask_b32_e64 v13, -1, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 1, v13
s_cbranch_execz .LBB0_4
s_clause 0x1
global_load_b64 v[8:9], v[6:7], off
global_load_b64 v[10:11], v[2:3], off
s_waitcnt vmcnt(1)
global_store_b64 v[2:3], v[8:9], off
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[10:11], off
s_branch .LBB0_4
.LBB0_41:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortP5Pointjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortP5Pointjj, .Lfunc_end0-_Z4sortP5Pointjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_p0
.type d_p0,@object
.section .bss,"aw",@nobits
.globl d_p0
.p2align 2, 0x0
d_p0:
.zero 8
.size d_p0, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_p0
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortP5Pointjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortP5Pointjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
#define MASK_WIDTH 3 //Kx and Ky
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
__global__ void Convolution3D(float *input, float* mask, float *result, int width, int height, int depth)
{
//allocating shared memory for intermediate ops
__shared__ float shared_mem[W][W][W];
// First batch loading
int out = (threadIdx.y * TILE_WIDTH) + threadIdx.x
+ (threadIdx.z * TILE_WIDTH * TILE_WIDTH);
int out_tmp = out;
int outX = out_tmp % W;
out_tmp = out_tmp / W;
int outY = out_tmp % W;
out_tmp = out_tmp / W;
int outZ = out_tmp;
// input's indices
int srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
int srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
int srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
int src = srcX + (srcY * width) + (srcZ * width * height);
// initializing shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
// Second batch loading
out = threadIdx.x + (threadIdx.y * TILE_WIDTH) + (threadIdx.z * TILE_WIDTH * TILE_WIDTH) + TILE_WIDTH * TILE_WIDTH * TILE_WIDTH;
out_tmp = out;
outX = out_tmp % W;
out_tmp = out_tmp / W;
outY = out_tmp % W;
out_tmp = out_tmp / W;
outZ = out_tmp;
srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
src = srcX + (srcY * width) + (srcZ * width * height);
// if within tiling area
if(outZ < W)
{
//transfer data to shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
}
__syncthreads();
//3d convolution
int z;
int y;
int x;
float sum = 0;
for(z = 0; z < MASK_WIDTH; z++)
for(y = 0; y < MASK_WIDTH; y++)
for(x = 0; x < MASK_WIDTH; x++)
sum += shared_mem[threadIdx.z + z][threadIdx.y + y][threadIdx.x + x] * mask[x + (y * MASK_WIDTH) + (z * MASK_WIDTH * MASK_WIDTH)];
//check indices before loading into output
z = threadIdx.z + (blockIdx.z * TILE_WIDTH);
y = threadIdx.y + (blockIdx.y * TILE_WIDTH);
x = threadIdx.x + (blockIdx.x * TILE_WIDTH);
if(z < depth && y < height && x < width)
result[x + (y * width) + (z * width * height)] = sum;
__syncthreads();
}
void init_mat(float *a, const int Nx, const int Ny, const int Ni, const int val) {
int i, j, k;
for(i=0; i<Nx; i++)
for(j=0; j<Ny; j++)
for(k=0; k<Ni; k++)
a[(i*Ny*Ni)+j*Ni+k] = val;
}
int main(int argc, char* argv[])
{
int image_width = 14; //Nx
int image_height = 14; //Ny
int image_depth = 512; //Ni
/*
int image_width = 224; //Nx
int image_height = 224; //Ny
int image_depth = 64; //Ni
*/
// initialize host mem
float *d_in;
float *d_out;
float *d_mask;
float *data = (float*)malloc(sizeof(float)*image_width*image_height*image_depth);
init_mat(data, image_width, image_height, image_depth, 2.0f);
float *mask = (float*)malloc(sizeof(float)*MASK_WIDTH*MASK_WIDTH*MASK_WIDTH);
init_mat(mask, MASK_WIDTH, MASK_WIDTH, MASK_WIDTH, 1.0f);
//allocate device mem
int input_size = image_height * image_width * image_depth;
int output_size = image_height * image_width * image_depth;
cudaMalloc((void **)&d_in, input_size * sizeof(float));
cudaMalloc((void **)&d_out, output_size* sizeof(float));
cudaMalloc((void **)&d_mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float));
cudaMemcpy(d_in, data, image_width * image_height * image_depth * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float), cudaMemcpyHostToDevice);
dim3 dim_block(TILE_WIDTH, TILE_WIDTH, TILE_WIDTH);
dim3 dim_grid((image_width + TILE_WIDTH - 1) / TILE_WIDTH, (image_height + TILE_WIDTH - 1) / TILE_WIDTH, (image_depth + TILE_WIDTH - 1) / TILE_WIDTH);
Convolution3D<<<dim_grid, dim_block>>>(d_in, d_mask, d_out, image_width, image_height, image_depth);
cudaDeviceSynchronize();
//get data from device to host
cudaMemcpy(data, d_out, output_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
cudaFree(d_mask);
free(data);
free(mask);
cudaError_t err = cudaGetLastError(); // add
if (err != cudaSuccess)
printf("CUDA Error: %s;", cudaGetErrorString(err));
cudaProfilerStop();
return 0;
} | code for sm_80
Function : _Z13Convolution3DPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0040*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*0050*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000ee80000002600 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000f220000002500 */
/*0080*/ LEA R3, R5, R0, 0x3 ; /* 0x0000000005037211 */
/* 0x001fc800078e18ff */
/*0090*/ LEA R12, R4, R3, 0x6 ; /* 0x00000003040c7211 */
/* 0x002fca00078e30ff */
/*00a0*/ IMAD.HI R2, R12, 0x66666667, RZ ; /* 0x666666670c027827 */
/* 0x000fe200078e02ff */
/*00b0*/ LEA R10, R6, 0xffffffff, 0x3 ; /* 0xffffffff060a7811 */
/* 0x008fc600078e18ff */
/*00c0*/ IMAD.HI R8, R12, 0x51eb851f, RZ ; /* 0x51eb851f0c087827 */
/* 0x000fe200078e02ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*00e0*/ LEA.HI.SX32 R3, R2, R3, 0x1e ; /* 0x0000000302037211 */
/* 0x000fe400078ff2ff */
/*00f0*/ SHF.R.U32.HI R13, RZ, 0x1f, R8 ; /* 0x0000001fff0d7819 */
/* 0x000fc60000011608 */
/*0100*/ IMAD.HI R2, R3, 0x66666667, RZ ; /* 0x6666666703027827 */
/* 0x000fe200078e02ff */
/*0110*/ LEA.HI.SX32 R16, R8, R13, 0x1b ; /* 0x0000000d08107211 */
/* 0x000fe400078fdaff */
/*0120*/ LEA R8, R9, 0xffffffff, 0x3 ; /* 0xffffffff09087811 */
/* 0x004fe400078e18ff */
/*0130*/ SHF.R.U32.HI R11, RZ, 0x1f, R2 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011602 */
/*0140*/ IADD3 R14, R16, R8, RZ ; /* 0x00000008100e7210 */
/* 0x000fe40007ffe0ff */
/*0150*/ LEA.HI.SX32 R2, R2, R11, 0x1e ; /* 0x0000000b02027211 */
/* 0x000fe400078ff2ff */
/*0160*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x180], PT ; /* 0x000060000e007a0c */
/* 0x000fc40003f06270 */
/*0170*/ LEA R11, R7, 0xffffffff, 0x3 ; /* 0xffffffff070b7811 */
/* 0x010fe200078e18ff */
/*0180*/ IMAD R13, R2, -0xa, R3 ; /* 0xfffffff6020d7824 */
/* 0x000fe400078e0203 */
/*0190*/ IMAD R2, R3, -0xa, R12 ; /* 0xfffffff603027824 */
/* 0x000fc600078e020c */
/*01a0*/ IADD3 R15, R13, R10, RZ ; /* 0x0000000a0d0f7210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R3, R2, R11, RZ ; /* 0x0000000b02037210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LOP3.LUT R17, R15, R14, RZ, 0xfc, !PT ; /* 0x0000000e0f117212 */
/* 0x000fc800078efcff */
/*01d0*/ ISETP.GT.AND P0, PT, R17, -0x1, !P0 ; /* 0xffffffff1100780c */
/* 0x000fc80004704270 */
/*01e0*/ ISETP.LT.AND P0, PT, R15, c[0x0][0x17c], P0 ; /* 0x00005f000f007a0c */
/* 0x000fc80000701270 */
/*01f0*/ ISETP.GT.AND P0, PT, R3, -0x1, P0 ; /* 0xffffffff0300780c */
/* 0x000fc80000704270 */
/*0200*/ ISETP.LT.AND P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000701270 */
/*0210*/ @P0 IMAD R14, R14, c[0x0][0x17c], R15 ; /* 0x00005f000e0e0a24 */
/* 0x000fe200078e020f */
/*0220*/ @P0 MOV R15, 0x4 ; /* 0x00000004000f0802 */
/* 0x000fc60000000f00 */
/*0230*/ @P0 IMAD R14, R14, c[0x0][0x178], R3 ; /* 0x00005e000e0e0a24 */
/* 0x000fc800078e0203 */
/*0240*/ @P0 IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e0625 */
/* 0x000fcc00078e020f */
/*0250*/ @P0 LDG.E R14, [R14.64] ; /* 0x000000040e0e0981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R13, R16, 0xa, R13 ; /* 0x0000000a100d7824 */
/* 0x000fe200078e020d */
/*0270*/ IADD3 R12, R12, 0x200, RZ ; /* 0x000002000c0c7810 */
/* 0x000fe20007ffe0ff */
/*0280*/ BSSY B0, 0x4f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0290*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD R13, R13, 0xa, R2 ; /* 0x0000000a0d0d7824 */
/* 0x000fe200078e0202 */
/*02b0*/ ISETP.GT.AND P1, PT, R12, 0x3e7, PT ; /* 0x000003e70c00780c */
/* 0x000fe40003f24270 */
/*02c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*02d0*/ @!P0 STS [R13.X4], RZ ; /* 0x000000ff0d008388 */
/* 0x0001e80000004800 */
/*02e0*/ @P0 STS [R13.X4], R14 ; /* 0x0000000e0d000388 */
/* 0x0041ea0000004800 */
/*02f0*/ @P1 BRA 0x4e0 ; /* 0x000001e000001947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD.HI R13, R12, 0x66666667, RZ ; /* 0x666666670c0d7827 */
/* 0x001fc800078e02ff */
/*0310*/ IMAD.HI R16, R12, 0x51eb851f, RZ ; /* 0x51eb851f0c107827 */
/* 0x000fe200078e02ff */
/*0320*/ SHF.R.U32.HI R14, RZ, 0x1f, R13 ; /* 0x0000001fff0e7819 */
/* 0x000fc8000001160d */
/*0330*/ LEA.HI.SX32 R13, R13, R14, 0x1e ; /* 0x0000000e0d0d7211 */
/* 0x000fe400078ff2ff */
/*0340*/ SHF.R.U32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fc60000011610 */
/*0350*/ IMAD.HI R14, R13, 0x66666667, RZ ; /* 0x666666670d0e7827 */
/* 0x000fe200078e02ff */
/*0360*/ LEA.HI.SX32 R17, R16, R17, 0x1b ; /* 0x0000001110117211 */
/* 0x000fc600078fdaff */
/*0370*/ IMAD R12, R13, -0xa, R12 ; /* 0xfffffff60d0c7824 */
/* 0x000fe200078e020c */
/*0380*/ SHF.R.U32.HI R15, RZ, 0x1f, R14 ; /* 0x0000001fff0f7819 */
/* 0x000fe4000001160e */
/*0390*/ IADD3 R8, R8, R17, RZ ; /* 0x0000001108087210 */
/* 0x000fe40007ffe0ff */
/*03a0*/ LEA.HI.SX32 R14, R14, R15, 0x1e ; /* 0x0000000f0e0e7211 */
/* 0x000fe400078ff2ff */
/*03b0*/ IADD3 R11, R11, R12, RZ ; /* 0x0000000c0b0b7210 */
/* 0x000fc60007ffe0ff */
/*03c0*/ IMAD R15, R14, -0xa, R13 ; /* 0xfffffff60e0f7824 */
/* 0x000fca00078e020d */
/*03d0*/ IADD3 R19, R10, R15, RZ ; /* 0x0000000f0a137210 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD R15, R17, 0xa, R15 ; /* 0x0000000a110f7824 */
/* 0x000fc600078e020f */
/*03f0*/ LOP3.LUT R10, R19, R8, RZ, 0xfc, !PT ; /* 0x00000008130a7212 */
/* 0x000fe200078efcff */
/*0400*/ IMAD R15, R15, 0xa, R12 ; /* 0x0000000a0f0f7824 */
/* 0x000fc600078e020c */
/*0410*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fc80003f04270 */
/*0420*/ ISETP.LT.AND P0, PT, R8.reuse, c[0x0][0x180], P0 ; /* 0x0000600008007a0c */
/* 0x040fe20000701270 */
/*0430*/ IMAD R8, R8, c[0x0][0x17c], R19 ; /* 0x00005f0008087a24 */
/* 0x000fc600078e0213 */
/*0440*/ ISETP.LT.AND P0, PT, R19, c[0x0][0x17c], P0 ; /* 0x00005f0013007a0c */
/* 0x000fc80000701270 */
/*0450*/ ISETP.GT.AND P0, PT, R11, -0x1, P0 ; /* 0xffffffff0b00780c */
/* 0x000fc80000704270 */
/*0460*/ ISETP.LT.AND P0, PT, R11, c[0x0][0x178], P0 ; /* 0x00005e000b007a0c */
/* 0x000fe20000701270 */
/*0470*/ IMAD R11, R8, c[0x0][0x178], R11 ; /* 0x00005e00080b7a24 */
/* 0x000fd800078e020b */
/*0480*/ @!P0 STS [R15.X4], RZ ; /* 0x000000ff0f008388 */
/* 0x0001e20000004800 */
/*0490*/ @!P0 BRA 0x4e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fd400000001ff */
/*04b0*/ IMAD.WIDE R10, R11, R10, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e020a */
/*04c0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ STS [R15.X4], R10 ; /* 0x0000000a0f007388 */
/* 0x0043e40000004800 */
/*04e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x001ea8000c1e1900 */
/*0510*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x002f68000c1e1900 */
/*0540*/ LDG.E R16, [R2.64+0x10] ; /* 0x0000100402107981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x000f68000c1e1900 */
/*0560*/ LDG.E R18, [R2.64+0x18] ; /* 0x0000180402127981 */
/* 0x000f68000c1e1900 */
/*0570*/ LDG.E R24, [R2.64+0x1c] ; /* 0x00001c0402187981 */
/* 0x000f68000c1e1900 */
/*0580*/ LDG.E R22, [R2.64+0x20] ; /* 0x0000200402167981 */
/* 0x000f68000c1e1900 */
/*0590*/ LDG.E R20, [R2.64+0x24] ; /* 0x0000240402147981 */
/* 0x000f68000c1e1900 */
/*05a0*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280402087981 */
/* 0x000f62000c1e1900 */
/*05b0*/ IMAD R11, R4, 0xa, R5 ; /* 0x0000000a040b7824 */
/* 0x000fc600078e0205 */
/*05c0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000162000c1e1900 */
/*05d0*/ IMAD R11, R11, 0xa, R0 ; /* 0x0000000a0b0b7824 */
/* 0x000fc600078e0200 */
/*05e0*/ LDG.E R12, [R2.64+0x30] ; /* 0x00003004020c7981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDS R26, [R11.X4] ; /* 0x000000000b1a7984 */
/* 0x000ea80000004800 */
/*0600*/ LDS R25, [R11.X4+0x4] ; /* 0x000004000b197984 */
/* 0x000ee80000004800 */
/*0610*/ LDS R19, [R11.X4+0x8] ; /* 0x000008000b137984 */
/* 0x000f280000004800 */
/*0620*/ LDS R28, [R11.X4+0x28] ; /* 0x000028000b1c7984 */
/* 0x000f680000004800 */
/*0630*/ LDS R21, [R11.X4+0x2c] ; /* 0x00002c000b157984 */
/* 0x000e620000004800 */
/*0640*/ FFMA R13, R13, R26, RZ ; /* 0x0000001a0d0d7223 */
/* 0x004fc600000000ff */
/*0650*/ LDS R26, [R11.X4+0x30] ; /* 0x000030000b1a7984 */
/* 0x000ea20000004800 */
/*0660*/ FFMA R23, R23, R25, R13 ; /* 0x0000001917177223 */
/* 0x008fc6000000000d */
/*0670*/ LDG.E R13, [R2.64+0x34] ; /* 0x00003404020d7981 */
/* 0x0000e2000c1e1900 */
/*0680*/ FFMA R23, R14, R19, R23 ; /* 0x000000130e177223 */
/* 0x010fc60000000017 */
/*0690*/ LDS R19, [R11.X4+0x50] ; /* 0x000050000b137984 */
/* 0x000f280000004800 */
/*06a0*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0000e2000c1e1900 */
/*06b0*/ FFMA R23, R15, R28, R23 ; /* 0x0000001c0f177223 */
/* 0x020fc60000000017 */
/*06c0*/ LDS R25, [R11.X4+0x54] ; /* 0x000054000b197984 */
/* 0x000f620000004800 */
/*06d0*/ FFMA R21, R16, R21, R23 ; /* 0x0000001510157223 */
/* 0x002fc60000000017 */
/*06e0*/ LDG.E R15, [R2.64+0x3c] ; /* 0x00003c04020f7981 */
/* 0x0000e8000c1e1900 */
/*06f0*/ LDS R23, [R11.X4+0x58] ; /* 0x000058000b177984 */
/* 0x000e680000004800 */
/*0700*/ LDG.E R16, [R2.64+0x40] ; /* 0x0000400402107981 */
/* 0x0000e8000c1e1900 */
/*0710*/ LDS R28, [R11.X4+0x1c0] ; /* 0x0001c0000b1c7984 */
/* 0x000fe20000004800 */
/*0720*/ FFMA R26, R17, R26, R21 ; /* 0x0000001a111a7223 */
/* 0x004fc60000000015 */
/*0730*/ LDS R21, [R11.X4+0x190] ; /* 0x000190000b157984 */
/* 0x000ea80000004800 */
/*0740*/ LDG.E R17, [R2.64+0x44] ; /* 0x0000440402117981 */
/* 0x0000e2000c1e1900 */
/*0750*/ FFMA R26, R18, R19, R26 ; /* 0x00000013121a7223 */
/* 0x010fc6000000001a */
/*0760*/ LDS R19, [R11.X4+0x194] ; /* 0x000194000b137984 */
/* 0x000f280000004800 */
/*0770*/ LDG.E R18, [R2.64+0x48] ; /* 0x0000480402127981 */
/* 0x0000e2000c1e1900 */
/*0780*/ FFMA R26, R24, R25, R26 ; /* 0x00000019181a7223 */
/* 0x020fc6000000001a */
/*0790*/ LDG.E R25, [R2.64+0x4c] ; /* 0x00004c0402197981 */
/* 0x000168000c1e1900 */
/*07a0*/ LDG.E R24, [R2.64+0x50] ; /* 0x0000500402187981 */
/* 0x000162000c1e1900 */
/*07b0*/ FFMA R26, R22, R23, R26 ; /* 0x00000017161a7223 */
/* 0x002fc6000000001a */
/*07c0*/ LDG.E R23, [R2.64+0x54] ; /* 0x0000540402177981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R22, [R2.64+0x58] ; /* 0x0000580402167981 */
/* 0x000162000c1e1900 */
/*07e0*/ FFMA R26, R20, R21, R26 ; /* 0x00000015141a7223 */
/* 0x004fc6000000001a */
/*07f0*/ LDG.E R21, [R2.64+0x5c] ; /* 0x00005c0402157981 */
/* 0x0000a8000c1e1900 */
/*0800*/ LDG.E R20, [R2.64+0x60] ; /* 0x0000600402147981 */
/* 0x0000a2000c1e1900 */
/*0810*/ FFMA R27, R8, R19, R26 ; /* 0x00000013081b7223 */
/* 0x010fc6000000001a */
/*0820*/ LDG.E R8, [R2.64+0x64] ; /* 0x0000640402087981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R19, [R2.64+0x68] ; /* 0x0000680402137981 */
/* 0x000128000c1e1900 */
/*0840*/ LDS R26, [R11.X4+0x198] ; /* 0x000198000b1a7984 */
/* 0x000e680000004800 */
/*0850*/ LDS R3, [R11.X4+0x320] ; /* 0x000320000b037984 */
/* 0x001fe80000004800 */
/*0860*/ LDS R2, [R11.X4+0x324] ; /* 0x000324000b027984 */
/* 0x000fe20000004800 */
/*0870*/ FFMA R27, R10, R26, R27 ; /* 0x0000001a0a1b7223 */
/* 0x002fc6000000001b */
/*0880*/ LDS R10, [R11.X4+0x1b8] ; /* 0x0001b8000b0a7984 */
/* 0x000e280000004800 */
/*0890*/ LDS R26, [R11.X4+0x1bc] ; /* 0x0001bc000b1a7984 */
/* 0x000ee20000004800 */
/*08a0*/ FFMA R12, R12, R10, R27 ; /* 0x0000000a0c0c7223 */
/* 0x001fc6000000001b */
/*08b0*/ LDS R10, [R11.X4+0x1e0] ; /* 0x0001e0000b0a7984 */
/* 0x000e280000004800 */
/*08c0*/ LDS R27, [R11.X4+0x1e4] ; /* 0x0001e4000b1b7984 */
/* 0x000e620000004800 */
/*08d0*/ LEA R4, R9, R4, 0x3 ; /* 0x0000000409047211 */
/* 0x000fe400078e18ff */
/*08e0*/ LEA R5, R6, R5, 0x3 ; /* 0x0000000506057211 */
/* 0x000fe400078e18ff */
/*08f0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe40003f06270 */
/*0900*/ LEA R0, R7, R0, 0x3 ; /* 0x0000000007007211 */
/* 0x000fc400078e18ff */
/*0910*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fc80000706670 */
/*0920*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0930*/ @!P0 IMAD R5, R4, c[0x0][0x17c], R5 ; /* 0x00005f0004058a24 */
/* 0x000fe200078e0205 */
/*0940*/ @!P0 MOV R4, 0x4 ; /* 0x0000000400048802 */
/* 0x000fe20000000f00 */
/*0950*/ FFMA R13, R13, R26, R12 ; /* 0x0000001a0d0d7223 */
/* 0x008fe4000000000c */
/*0960*/ LDS R12, [R11.X4+0x1e8] ; /* 0x0001e8000b0c7984 */
/* 0x000ee40000004800 */
/*0970*/ FFMA R13, R14, R28, R13 ; /* 0x0000001c0e0d7223 */
/* 0x000fe4000000000d */
/*0980*/ LDS R14, [R11.X4+0x350] ; /* 0x000350000b0e7984 */
/* 0x000fe40000004800 */
/*0990*/ FFMA R15, R15, R10, R13 ; /* 0x0000000a0f0f7223 */
/* 0x001fc4000000000d */
/*09a0*/ LDS R13, [R11.X4+0x328] ; /* 0x000328000b0d7984 */
/* 0x000e280000004800 */
/*09b0*/ LDS R10, [R11.X4+0x348] ; /* 0x000348000b0a7984 */
/* 0x000f620000004800 */
/*09c0*/ FFMA R16, R16, R27, R15 ; /* 0x0000001b10107223 */
/* 0x002fc6000000000f */
/*09d0*/ LDS R15, [R11.X4+0x34c] ; /* 0x00034c000b0f7984 */
/* 0x000e680000004800 */
/*09e0*/ LDS R27, [R11.X4+0x370] ; /* 0x000370000b1b7984 */
/* 0x000ea20000004800 */
/*09f0*/ FFMA R16, R17, R12, R16 ; /* 0x0000000c11107223 */
/* 0x008fc60000000010 */
/*0a00*/ LDS R17, [R11.X4+0x374] ; /* 0x000374000b117984 */
/* 0x000f280000004800 */
/*0a10*/ LDS R12, [R11.X4+0x378] ; /* 0x000378000b0c7984 */
/* 0x000ee20000004800 */
/*0a20*/ FFMA R3, R18, R3, R16 ; /* 0x0000000312037223 */
/* 0x000fc80000000010 */
/*0a30*/ FFMA R2, R25, R2, R3 ; /* 0x0000000219027223 */
/* 0x020fc80000000003 */
/*0a40*/ FFMA R2, R24, R13, R2 ; /* 0x0000000d18027223 */
/* 0x001fc80000000002 */
/*0a50*/ FFMA R2, R23, R10, R2 ; /* 0x0000000a17027223 */
/* 0x000fc80000000002 */
/*0a60*/ FFMA R2, R22, R15, R2 ; /* 0x0000000f16027223 */
/* 0x002fe40000000002 */
/*0a70*/ @!P0 IMAD R3, R5, c[0x0][0x178], R0 ; /* 0x00005e0005038a24 */
/* 0x000fe400078e0200 */
/*0a80*/ FFMA R2, R21, R14, R2 ; /* 0x0000000e15027223 */
/* 0x004fc80000000002 */
/*0a90*/ FFMA R2, R20, R27, R2 ; /* 0x0000001b14027223 */
/* 0x000fc80000000002 */
/*0aa0*/ FFMA R8, R8, R17, R2 ; /* 0x0000001108087223 */
/* 0x010fe40000000002 */
/*0ab0*/ @!P0 IMAD.WIDE R2, R3, R4, c[0x0][0x170] ; /* 0x00005c0003028625 */
/* 0x000fc800078e0204 */
/*0ac0*/ FFMA R19, R19, R12, R8 ; /* 0x0000000c13137223 */
/* 0x008fca0000000008 */
/*0ad0*/ @!P0 STG.E [R2.64], R19 ; /* 0x0000001302008986 */
/* 0x000fe8000c101904 */
/*0ae0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
#define MASK_WIDTH 3 //Kx and Ky
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
__global__ void Convolution3D(float *input, float* mask, float *result, int width, int height, int depth)
{
//allocating shared memory for intermediate ops
__shared__ float shared_mem[W][W][W];
// First batch loading
int out = (threadIdx.y * TILE_WIDTH) + threadIdx.x
+ (threadIdx.z * TILE_WIDTH * TILE_WIDTH);
int out_tmp = out;
int outX = out_tmp % W;
out_tmp = out_tmp / W;
int outY = out_tmp % W;
out_tmp = out_tmp / W;
int outZ = out_tmp;
// input's indices
int srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
int srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
int srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
int src = srcX + (srcY * width) + (srcZ * width * height);
// initializing shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
// Second batch loading
out = threadIdx.x + (threadIdx.y * TILE_WIDTH) + (threadIdx.z * TILE_WIDTH * TILE_WIDTH) + TILE_WIDTH * TILE_WIDTH * TILE_WIDTH;
out_tmp = out;
outX = out_tmp % W;
out_tmp = out_tmp / W;
outY = out_tmp % W;
out_tmp = out_tmp / W;
outZ = out_tmp;
srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
src = srcX + (srcY * width) + (srcZ * width * height);
// if within tiling area
if(outZ < W)
{
//transfer data to shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
}
__syncthreads();
//3d convolution
int z;
int y;
int x;
float sum = 0;
for(z = 0; z < MASK_WIDTH; z++)
for(y = 0; y < MASK_WIDTH; y++)
for(x = 0; x < MASK_WIDTH; x++)
sum += shared_mem[threadIdx.z + z][threadIdx.y + y][threadIdx.x + x] * mask[x + (y * MASK_WIDTH) + (z * MASK_WIDTH * MASK_WIDTH)];
//check indices before loading into output
z = threadIdx.z + (blockIdx.z * TILE_WIDTH);
y = threadIdx.y + (blockIdx.y * TILE_WIDTH);
x = threadIdx.x + (blockIdx.x * TILE_WIDTH);
if(z < depth && y < height && x < width)
result[x + (y * width) + (z * width * height)] = sum;
__syncthreads();
}
void init_mat(float *a, const int Nx, const int Ny, const int Ni, const int val) {
int i, j, k;
for(i=0; i<Nx; i++)
for(j=0; j<Ny; j++)
for(k=0; k<Ni; k++)
a[(i*Ny*Ni)+j*Ni+k] = val;
}
int main(int argc, char* argv[])
{
int image_width = 14; //Nx
int image_height = 14; //Ny
int image_depth = 512; //Ni
/*
int image_width = 224; //Nx
int image_height = 224; //Ny
int image_depth = 64; //Ni
*/
// initialize host mem
float *d_in;
float *d_out;
float *d_mask;
float *data = (float*)malloc(sizeof(float)*image_width*image_height*image_depth);
init_mat(data, image_width, image_height, image_depth, 2.0f);
float *mask = (float*)malloc(sizeof(float)*MASK_WIDTH*MASK_WIDTH*MASK_WIDTH);
init_mat(mask, MASK_WIDTH, MASK_WIDTH, MASK_WIDTH, 1.0f);
//allocate device mem
int input_size = image_height * image_width * image_depth;
int output_size = image_height * image_width * image_depth;
cudaMalloc((void **)&d_in, input_size * sizeof(float));
cudaMalloc((void **)&d_out, output_size* sizeof(float));
cudaMalloc((void **)&d_mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float));
cudaMemcpy(d_in, data, image_width * image_height * image_depth * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float), cudaMemcpyHostToDevice);
dim3 dim_block(TILE_WIDTH, TILE_WIDTH, TILE_WIDTH);
dim3 dim_grid((image_width + TILE_WIDTH - 1) / TILE_WIDTH, (image_height + TILE_WIDTH - 1) / TILE_WIDTH, (image_depth + TILE_WIDTH - 1) / TILE_WIDTH);
Convolution3D<<<dim_grid, dim_block>>>(d_in, d_mask, d_out, image_width, image_height, image_depth);
cudaDeviceSynchronize();
//get data from device to host
cudaMemcpy(data, d_out, output_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
cudaFree(d_mask);
free(data);
free(mask);
cudaError_t err = cudaGetLastError(); // add
if (err != cudaSuccess)
printf("CUDA Error: %s;", cudaGetErrorString(err));
cudaProfilerStop();
return 0;
} | .file "tmpxft_0018ce08_00000000-6_3DConv.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8init_matPfiiii
.type _Z8init_matPfiiii, @function
_Z8init_matPfiiii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r9
movl %esi, %ebx
movl %edx, %r10d
movl %ecx, %edi
movl %edx, %r13d
imull %ecx, %r13d
movl $0, %r12d
movl $0, %ebp
movslq %ecx, %r11
jmp .L5
.L8:
movslq %esi, %rdx
leaq (%r9,%rdx,4), %rax
addq %r11, %rdx
leaq (%r9,%rdx,4), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
.L6:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
.L9:
addl $1, %ecx
addl %edi, %esi
cmpl %ecx, %r10d
je .L7
.L10:
testl %edi, %edi
jg .L8
jmp .L9
.L7:
addl $1, %ebp
addl %r13d, %r12d
cmpl %ebp, %ebx
je .L3
.L5:
movl %r12d, %esi
movl $0, %ecx
testl %r10d, %r10d
jg .L10
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3669:
.size _Z8init_matPfiiii, .-_Z8init_matPfiiii
.globl _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
.type _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii, @function
_Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13Convolution3DPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii, .-_Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
.globl _Z13Convolution3DPfS_S_iii
.type _Z13Convolution3DPfS_S_iii, @function
_Z13Convolution3DPfS_S_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z13Convolution3DPfS_S_iii, .-_Z13Convolution3DPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Error: %s;"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $401408, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %r8d
movl $512, %ecx
movl $14, %edx
movl $14, %esi
movq %rax, %rdi
call _Z8init_matPfiiii
movl $108, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %r8d
movl $3, %ecx
movl $3, %edx
movl $3, %esi
movq %rax, %rdi
call _Z8init_matPfiiii
leaq 8(%rsp), %rdi
movl $401408, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $401408, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $108, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $401408, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $108, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $8, %ecx
movq 44(%rsp), %rdi
movl $64, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $401408, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
.L28:
call cudaProfilerStop@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl $512, %r9d
movl $14, %r8d
movl $14, %ecx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
jmp .L27
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13Convolution3DPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Convolution3DPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
#define MASK_WIDTH 3 //Kx and Ky
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
__global__ void Convolution3D(float *input, float* mask, float *result, int width, int height, int depth)
{
//allocating shared memory for intermediate ops
__shared__ float shared_mem[W][W][W];
// First batch loading
int out = (threadIdx.y * TILE_WIDTH) + threadIdx.x
+ (threadIdx.z * TILE_WIDTH * TILE_WIDTH);
int out_tmp = out;
int outX = out_tmp % W;
out_tmp = out_tmp / W;
int outY = out_tmp % W;
out_tmp = out_tmp / W;
int outZ = out_tmp;
// input's indices
int srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
int srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
int srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
int src = srcX + (srcY * width) + (srcZ * width * height);
// initializing shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
// Second batch loading
out = threadIdx.x + (threadIdx.y * TILE_WIDTH) + (threadIdx.z * TILE_WIDTH * TILE_WIDTH) + TILE_WIDTH * TILE_WIDTH * TILE_WIDTH;
out_tmp = out;
outX = out_tmp % W;
out_tmp = out_tmp / W;
outY = out_tmp % W;
out_tmp = out_tmp / W;
outZ = out_tmp;
srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
src = srcX + (srcY * width) + (srcZ * width * height);
// if within tiling area
if(outZ < W)
{
//transfer data to shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
}
__syncthreads();
//3d convolution
int z;
int y;
int x;
float sum = 0;
for(z = 0; z < MASK_WIDTH; z++)
for(y = 0; y < MASK_WIDTH; y++)
for(x = 0; x < MASK_WIDTH; x++)
sum += shared_mem[threadIdx.z + z][threadIdx.y + y][threadIdx.x + x] * mask[x + (y * MASK_WIDTH) + (z * MASK_WIDTH * MASK_WIDTH)];
//check indices before loading into output
z = threadIdx.z + (blockIdx.z * TILE_WIDTH);
y = threadIdx.y + (blockIdx.y * TILE_WIDTH);
x = threadIdx.x + (blockIdx.x * TILE_WIDTH);
if(z < depth && y < height && x < width)
result[x + (y * width) + (z * width * height)] = sum;
__syncthreads();
}
void init_mat(float *a, const int Nx, const int Ny, const int Ni, const int val) {
int i, j, k;
for(i=0; i<Nx; i++)
for(j=0; j<Ny; j++)
for(k=0; k<Ni; k++)
a[(i*Ny*Ni)+j*Ni+k] = val;
}
int main(int argc, char* argv[])
{
int image_width = 14; //Nx
int image_height = 14; //Ny
int image_depth = 512; //Ni
/*
int image_width = 224; //Nx
int image_height = 224; //Ny
int image_depth = 64; //Ni
*/
// initialize host mem
float *d_in;
float *d_out;
float *d_mask;
float *data = (float*)malloc(sizeof(float)*image_width*image_height*image_depth);
init_mat(data, image_width, image_height, image_depth, 2.0f);
float *mask = (float*)malloc(sizeof(float)*MASK_WIDTH*MASK_WIDTH*MASK_WIDTH);
init_mat(mask, MASK_WIDTH, MASK_WIDTH, MASK_WIDTH, 1.0f);
//allocate device mem
int input_size = image_height * image_width * image_depth;
int output_size = image_height * image_width * image_depth;
cudaMalloc((void **)&d_in, input_size * sizeof(float));
cudaMalloc((void **)&d_out, output_size* sizeof(float));
cudaMalloc((void **)&d_mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float));
cudaMemcpy(d_in, data, image_width * image_height * image_depth * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float), cudaMemcpyHostToDevice);
dim3 dim_block(TILE_WIDTH, TILE_WIDTH, TILE_WIDTH);
dim3 dim_grid((image_width + TILE_WIDTH - 1) / TILE_WIDTH, (image_height + TILE_WIDTH - 1) / TILE_WIDTH, (image_depth + TILE_WIDTH - 1) / TILE_WIDTH);
Convolution3D<<<dim_grid, dim_block>>>(d_in, d_mask, d_out, image_width, image_height, image_depth);
cudaDeviceSynchronize();
//get data from device to host
cudaMemcpy(data, d_out, output_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
cudaFree(d_mask);
free(data);
free(mask);
cudaError_t err = cudaGetLastError(); // add
if (err != cudaSuccess)
printf("CUDA Error: %s;", cudaGetErrorString(err));
cudaProfilerStop();
return 0;
} | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define MASK_WIDTH 3 //Kx and Ky
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
__global__ void Convolution3D(float *input, float* mask, float *result, int width, int height, int depth)
{
//allocating shared memory for intermediate ops
__shared__ float shared_mem[W][W][W];
// First batch loading
int out = (threadIdx.y * TILE_WIDTH) + threadIdx.x
+ (threadIdx.z * TILE_WIDTH * TILE_WIDTH);
int out_tmp = out;
int outX = out_tmp % W;
out_tmp = out_tmp / W;
int outY = out_tmp % W;
out_tmp = out_tmp / W;
int outZ = out_tmp;
// input's indices
int srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
int srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
int srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
int src = srcX + (srcY * width) + (srcZ * width * height);
// initializing shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
// Second batch loading
out = threadIdx.x + (threadIdx.y * TILE_WIDTH) + (threadIdx.z * TILE_WIDTH * TILE_WIDTH) + TILE_WIDTH * TILE_WIDTH * TILE_WIDTH;
out_tmp = out;
outX = out_tmp % W;
out_tmp = out_tmp / W;
outY = out_tmp % W;
out_tmp = out_tmp / W;
outZ = out_tmp;
srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
src = srcX + (srcY * width) + (srcZ * width * height);
// if within tiling area
if(outZ < W)
{
//transfer data to shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
}
__syncthreads();
//3d convolution
int z;
int y;
int x;
float sum = 0;
for(z = 0; z < MASK_WIDTH; z++)
for(y = 0; y < MASK_WIDTH; y++)
for(x = 0; x < MASK_WIDTH; x++)
sum += shared_mem[threadIdx.z + z][threadIdx.y + y][threadIdx.x + x] * mask[x + (y * MASK_WIDTH) + (z * MASK_WIDTH * MASK_WIDTH)];
//check indices before loading into output
z = threadIdx.z + (blockIdx.z * TILE_WIDTH);
y = threadIdx.y + (blockIdx.y * TILE_WIDTH);
x = threadIdx.x + (blockIdx.x * TILE_WIDTH);
if(z < depth && y < height && x < width)
result[x + (y * width) + (z * width * height)] = sum;
__syncthreads();
}
void init_mat(float *a, const int Nx, const int Ny, const int Ni, const int val) {
int i, j, k;
for(i=0; i<Nx; i++)
for(j=0; j<Ny; j++)
for(k=0; k<Ni; k++)
a[(i*Ny*Ni)+j*Ni+k] = val;
}
int main(int argc, char* argv[])
{
int image_width = 14; //Nx
int image_height = 14; //Ny
int image_depth = 512; //Ni
/*
int image_width = 224; //Nx
int image_height = 224; //Ny
int image_depth = 64; //Ni
*/
// initialize host mem
float *d_in;
float *d_out;
float *d_mask;
float *data = (float*)malloc(sizeof(float)*image_width*image_height*image_depth);
init_mat(data, image_width, image_height, image_depth, 2.0f);
float *mask = (float*)malloc(sizeof(float)*MASK_WIDTH*MASK_WIDTH*MASK_WIDTH);
init_mat(mask, MASK_WIDTH, MASK_WIDTH, MASK_WIDTH, 1.0f);
//allocate device mem
int input_size = image_height * image_width * image_depth;
int output_size = image_height * image_width * image_depth;
hipMalloc((void **)&d_in, input_size * sizeof(float));
hipMalloc((void **)&d_out, output_size* sizeof(float));
hipMalloc((void **)&d_mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float));
hipMemcpy(d_in, data, image_width * image_height * image_depth * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_mask, mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float), hipMemcpyHostToDevice);
dim3 dim_block(TILE_WIDTH, TILE_WIDTH, TILE_WIDTH);
dim3 dim_grid((image_width + TILE_WIDTH - 1) / TILE_WIDTH, (image_height + TILE_WIDTH - 1) / TILE_WIDTH, (image_depth + TILE_WIDTH - 1) / TILE_WIDTH);
Convolution3D<<<dim_grid, dim_block>>>(d_in, d_mask, d_out, image_width, image_height, image_depth);
hipDeviceSynchronize();
//get data from device to host
hipMemcpy(data, d_out, output_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
hipFree(d_mask);
free(data);
free(mask);
hipError_t err = hipGetLastError(); // add
if (err != hipSuccess)
printf("CUDA Error: %s;", hipGetErrorString(err));
hipProfilerStop();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define MASK_WIDTH 3 //Kx and Ky
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
__global__ void Convolution3D(float *input, float* mask, float *result, int width, int height, int depth)
{
//allocating shared memory for intermediate ops
__shared__ float shared_mem[W][W][W];
// First batch loading
int out = (threadIdx.y * TILE_WIDTH) + threadIdx.x
+ (threadIdx.z * TILE_WIDTH * TILE_WIDTH);
int out_tmp = out;
int outX = out_tmp % W;
out_tmp = out_tmp / W;
int outY = out_tmp % W;
out_tmp = out_tmp / W;
int outZ = out_tmp;
// input's indices
int srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
int srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
int srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
int src = srcX + (srcY * width) + (srcZ * width * height);
// initializing shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
// Second batch loading
out = threadIdx.x + (threadIdx.y * TILE_WIDTH) + (threadIdx.z * TILE_WIDTH * TILE_WIDTH) + TILE_WIDTH * TILE_WIDTH * TILE_WIDTH;
out_tmp = out;
outX = out_tmp % W;
out_tmp = out_tmp / W;
outY = out_tmp % W;
out_tmp = out_tmp / W;
outZ = out_tmp;
srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
src = srcX + (srcY * width) + (srcZ * width * height);
// if within tiling area
if(outZ < W)
{
//transfer data to shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
}
__syncthreads();
//3d convolution
int z;
int y;
int x;
float sum = 0;
for(z = 0; z < MASK_WIDTH; z++)
for(y = 0; y < MASK_WIDTH; y++)
for(x = 0; x < MASK_WIDTH; x++)
sum += shared_mem[threadIdx.z + z][threadIdx.y + y][threadIdx.x + x] * mask[x + (y * MASK_WIDTH) + (z * MASK_WIDTH * MASK_WIDTH)];
//check indices before loading into output
z = threadIdx.z + (blockIdx.z * TILE_WIDTH);
y = threadIdx.y + (blockIdx.y * TILE_WIDTH);
x = threadIdx.x + (blockIdx.x * TILE_WIDTH);
if(z < depth && y < height && x < width)
result[x + (y * width) + (z * width * height)] = sum;
__syncthreads();
}
void init_mat(float *a, const int Nx, const int Ny, const int Ni, const int val) {
int i, j, k;
for(i=0; i<Nx; i++)
for(j=0; j<Ny; j++)
for(k=0; k<Ni; k++)
a[(i*Ny*Ni)+j*Ni+k] = val;
}
int main(int argc, char* argv[])
{
int image_width = 14; //Nx
int image_height = 14; //Ny
int image_depth = 512; //Ni
/*
int image_width = 224; //Nx
int image_height = 224; //Ny
int image_depth = 64; //Ni
*/
// initialize host mem
float *d_in;
float *d_out;
float *d_mask;
float *data = (float*)malloc(sizeof(float)*image_width*image_height*image_depth);
init_mat(data, image_width, image_height, image_depth, 2.0f);
float *mask = (float*)malloc(sizeof(float)*MASK_WIDTH*MASK_WIDTH*MASK_WIDTH);
init_mat(mask, MASK_WIDTH, MASK_WIDTH, MASK_WIDTH, 1.0f);
//allocate device mem
int input_size = image_height * image_width * image_depth;
int output_size = image_height * image_width * image_depth;
hipMalloc((void **)&d_in, input_size * sizeof(float));
hipMalloc((void **)&d_out, output_size* sizeof(float));
hipMalloc((void **)&d_mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float));
hipMemcpy(d_in, data, image_width * image_height * image_depth * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_mask, mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float), hipMemcpyHostToDevice);
dim3 dim_block(TILE_WIDTH, TILE_WIDTH, TILE_WIDTH);
dim3 dim_grid((image_width + TILE_WIDTH - 1) / TILE_WIDTH, (image_height + TILE_WIDTH - 1) / TILE_WIDTH, (image_depth + TILE_WIDTH - 1) / TILE_WIDTH);
Convolution3D<<<dim_grid, dim_block>>>(d_in, d_mask, d_out, image_width, image_height, image_depth);
hipDeviceSynchronize();
//get data from device to host
hipMemcpy(data, d_out, output_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
hipFree(d_mask);
free(data);
free(mask);
hipError_t err = hipGetLastError(); // add
if (err != hipSuccess)
printf("CUDA Error: %s;", hipGetErrorString(err));
hipProfilerStop();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Convolution3DPfS_S_iii
.globl _Z13Convolution3DPfS_S_iii
.p2align 8
.type _Z13Convolution3DPfS_S_iii,@function
_Z13Convolution3DPfS_S_iii:
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v4, v0, 20, 10
v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_lshlrev_b32_e32 v0, 3, v2
v_lshlrev_b32_e32 v1, 6, v4
s_lshl_b32 s11, s15, 3
s_lshl_b32 s12, s14, 3
s_lshl_b32 s13, s13, 3
s_mov_b32 s8, exec_lo
v_add3_u32 v5, v0, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v5, 0xcccccccd
v_mul_hi_u32 v6, v5, 0x28f5c29
v_lshrrev_b32_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v9, s11, -1, v6
v_mul_hi_u32 v1, v0, 0x1999999a
v_mul_u32_u24_e32 v7, 10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v7, v5, v7
v_mul_lo_u32 v1, v1, 10
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v0, v1
v_cmpx_lt_i32_e32 -1, v9
s_cbranch_execz .LBB0_6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v0, s12, -1, v8
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s10, v9
v_mov_b32_e32 v10, 0
v_cmp_lt_i32_e64 s2, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_5
v_add3_u32 v1, s13, -1, v7
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v1
v_cmp_lt_i32_e64 s3, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[10:11], null, v9, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v10, s4, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[11:12]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v10, v[0:1], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s8
v_mul_lo_u32 v0, v8, 40
v_lshlrev_b32_e32 v1, 2, v7
v_mul_u32_u24_e32 v6, 0x190, v6
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v6, v0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v0, v10
v_cmpx_gt_u32_e32 0x1e8, v5
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v0, 0x200, v5
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, 0xcccccccd
v_lshrrev_b32_e32 v1, 3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v1, 0x1999999a
v_mul_lo_u32 v7, v1, 10
v_mul_lo_u32 v9, v6, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v0, v7
v_sub_nc_u32_e32 v7, v1, v9
v_mov_b32_e32 v9, 0
v_mul_hi_u32 v5, v0, 0x28f5c29
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v8, s11, -1, v5
v_cmpx_lt_i32_e32 -1, v8
s_cbranch_execz .LBB0_13
v_add3_u32 v0, s12, -1, v7
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s10, v8
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s2, -1, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_12
v_add3_u32 v1, s13, -1, v6
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v1
v_cmp_lt_i32_e64 s3, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_11
v_mad_u64_u32 v[9:10], null, v8, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v9, s4, v[1:2]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[10:11]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v9, v[0:1], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s9
v_mul_lo_u32 v0, v7, 40
v_lshlrev_b32_e32 v1, 2, v6
v_mul_u32_u24_e32 v5, 0x190, v5
v_add3_u32 v0, v5, v0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v0, v9
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_u32_u24_e32 v0, 0x190, v4
v_mul_u32_u24_e32 v1, 40, v2
v_lshlrev_b32_e32 v5, 2, v3
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add3_u32 v0, v0, v1, v5
v_mov_b32_e32 v5, 0
.p2align 6
.LBB0_15:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v1, v0
s_mov_b64 s[6:7], s[2:3]
s_mov_b32 s15, 0
.p2align 6
.LBB0_16:
s_mov_b32 s16, 0
s_mov_b64 s[8:9], s[6:7]
.LBB0_17:
v_add_nc_u32_e32 v6, s16, v1
s_load_b32 s17, s[8:9], 0x0
s_add_i32 s16, s16, 4
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
ds_load_b32 v6, v6
s_cmp_lg_u32 s16, 12
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, s17, v6
s_cbranch_scc1 .LBB0_17
s_add_i32 s15, s15, 1
v_add_nc_u32_e32 v1, 40, v1
s_add_u32 s6, s6, 12
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s15, 3
s_cbranch_scc1 .LBB0_16
s_add_i32 s14, s14, 1
v_add_nc_u32_e32 v0, 0x190, v0
s_add_u32 s2, s2, 36
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s14, 3
s_cbranch_scc1 .LBB0_15
v_add_nc_u32_e32 v4, s11, v4
v_add_nc_u32_e32 v1, s12, v2
v_add_nc_u32_e32 v0, s13, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s10, v4
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s4, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_22
v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Convolution3DPfS_S_iii
.amdhsa_group_segment_fixed_size 4000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Convolution3DPfS_S_iii, .Lfunc_end0-_Z13Convolution3DPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4000
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Convolution3DPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13Convolution3DPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define MASK_WIDTH 3 //Kx and Ky
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
__global__ void Convolution3D(float *input, float* mask, float *result, int width, int height, int depth)
{
//allocating shared memory for intermediate ops
__shared__ float shared_mem[W][W][W];
// First batch loading
int out = (threadIdx.y * TILE_WIDTH) + threadIdx.x
+ (threadIdx.z * TILE_WIDTH * TILE_WIDTH);
int out_tmp = out;
int outX = out_tmp % W;
out_tmp = out_tmp / W;
int outY = out_tmp % W;
out_tmp = out_tmp / W;
int outZ = out_tmp;
// input's indices
int srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
int srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
int srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
int src = srcX + (srcY * width) + (srcZ * width * height);
// initializing shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
// Second batch loading
out = threadIdx.x + (threadIdx.y * TILE_WIDTH) + (threadIdx.z * TILE_WIDTH * TILE_WIDTH) + TILE_WIDTH * TILE_WIDTH * TILE_WIDTH;
out_tmp = out;
outX = out_tmp % W;
out_tmp = out_tmp / W;
outY = out_tmp % W;
out_tmp = out_tmp / W;
outZ = out_tmp;
srcZ = outZ + (blockIdx.z * TILE_WIDTH) - MASK_RADIUS;
srcY = outY + (blockIdx.y * TILE_WIDTH) - MASK_RADIUS;
srcX = outX + (blockIdx.x * TILE_WIDTH) - MASK_RADIUS;
src = srcX + (srcY * width) + (srcZ * width * height);
// if within tiling area
if(outZ < W)
{
//transfer data to shared memory
if(srcZ >= 0 && srcZ < depth && srcY >= 0 && srcY < height && srcX >= 0 && srcX < width)
shared_mem[outZ][outY][outX] = input[src];
else
shared_mem[outZ][outY][outX] = 0;
}
__syncthreads();
//3d convolution
int z;
int y;
int x;
float sum = 0;
for(z = 0; z < MASK_WIDTH; z++)
for(y = 0; y < MASK_WIDTH; y++)
for(x = 0; x < MASK_WIDTH; x++)
sum += shared_mem[threadIdx.z + z][threadIdx.y + y][threadIdx.x + x] * mask[x + (y * MASK_WIDTH) + (z * MASK_WIDTH * MASK_WIDTH)];
//check indices before loading into output
z = threadIdx.z + (blockIdx.z * TILE_WIDTH);
y = threadIdx.y + (blockIdx.y * TILE_WIDTH);
x = threadIdx.x + (blockIdx.x * TILE_WIDTH);
if(z < depth && y < height && x < width)
result[x + (y * width) + (z * width * height)] = sum;
__syncthreads();
}
void init_mat(float *a, const int Nx, const int Ny, const int Ni, const int val) {
int i, j, k;
for(i=0; i<Nx; i++)
for(j=0; j<Ny; j++)
for(k=0; k<Ni; k++)
a[(i*Ny*Ni)+j*Ni+k] = val;
}
int main(int argc, char* argv[])
{
int image_width = 14; //Nx
int image_height = 14; //Ny
int image_depth = 512; //Ni
/*
int image_width = 224; //Nx
int image_height = 224; //Ny
int image_depth = 64; //Ni
*/
// initialize host mem
float *d_in;
float *d_out;
float *d_mask;
float *data = (float*)malloc(sizeof(float)*image_width*image_height*image_depth);
init_mat(data, image_width, image_height, image_depth, 2.0f);
float *mask = (float*)malloc(sizeof(float)*MASK_WIDTH*MASK_WIDTH*MASK_WIDTH);
init_mat(mask, MASK_WIDTH, MASK_WIDTH, MASK_WIDTH, 1.0f);
//allocate device mem
int input_size = image_height * image_width * image_depth;
int output_size = image_height * image_width * image_depth;
hipMalloc((void **)&d_in, input_size * sizeof(float));
hipMalloc((void **)&d_out, output_size* sizeof(float));
hipMalloc((void **)&d_mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float));
hipMemcpy(d_in, data, image_width * image_height * image_depth * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_mask, mask, MASK_WIDTH * MASK_WIDTH * MASK_WIDTH * sizeof(float), hipMemcpyHostToDevice);
dim3 dim_block(TILE_WIDTH, TILE_WIDTH, TILE_WIDTH);
dim3 dim_grid((image_width + TILE_WIDTH - 1) / TILE_WIDTH, (image_height + TILE_WIDTH - 1) / TILE_WIDTH, (image_depth + TILE_WIDTH - 1) / TILE_WIDTH);
Convolution3D<<<dim_grid, dim_block>>>(d_in, d_mask, d_out, image_width, image_height, image_depth);
hipDeviceSynchronize();
//get data from device to host
hipMemcpy(data, d_out, output_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
hipFree(d_mask);
free(data);
free(mask);
hipError_t err = hipGetLastError(); // add
if (err != hipSuccess)
printf("CUDA Error: %s;", hipGetErrorString(err));
hipProfilerStop();
return 0;
} | .text
.file "3DConv.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__Convolution3DPfS_S_iii # -- Begin function _Z28__device_stub__Convolution3DPfS_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__Convolution3DPfS_S_iii,@function
_Z28__device_stub__Convolution3DPfS_S_iii: # @_Z28__device_stub__Convolution3DPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Convolution3DPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__Convolution3DPfS_S_iii, .Lfunc_end0-_Z28__device_stub__Convolution3DPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z8init_matPfiiii # -- Begin function _Z8init_matPfiiii
.p2align 4, 0x90
.type _Z8init_matPfiiii,@function
_Z8init_matPfiiii: # @_Z8init_matPfiiii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_10
# %bb.1: # %.preheader20.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cvtsi2ss %r8d, %xmm0
movl %esi, %eax
movl %edx, %esi
movl %ecx, %r8d
movl %ecx, %r9d
imull %edx, %r9d
xorl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge23
# in Loop: Header=BB1_2 Depth=1
incq %r11
addl %r9d, %r10d
cmpq %rax, %r11
je .LBB1_9
.LBB1_2: # %.preheader20
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %edx, %edx
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r10d, %ebx
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incq %r14
addl %ecx, %ebx
cmpq %rsi, %r14
je .LBB1_8
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
testl %ecx, %ecx
jle .LBB1_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=2
movslq %ebx, %r15
leaq (%rdi,%r15,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r8
jne .LBB1_6
jmp .LBB1_7
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_10: # %._crit_edge25
retq
.Lfunc_end1:
.size _Z8init_matPfiiii, .Lfunc_end1-_Z8init_matPfiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $401408, %edi # imm = 0x62000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader20.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
movq %rcx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movl $1073741824, (%rdx,%rdi,4) # imm = 0x40000000
incq %rdi
cmpq $512, %rdi # imm = 0x200
jne .LBB2_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB2_2 Depth=2
incq %rsi
addq $2048, %rdx # imm = 0x800
cmpq $14, %rsi
jne .LBB2_2
# %bb.5: # %._crit_edge23.i
# in Loop: Header=BB2_1 Depth=1
incq %rax
addq $28672, %rcx # imm = 0x7000
cmpq $14, %rax
jne .LBB2_1
# %bb.6: # %_Z8init_matPfiiii.exit
movl $108, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB2_7: # %.preheader20.i39
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
# Child Loop BB2_9 Depth 3
movq %rcx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_8: # %.preheader.i41
# Parent Loop BB2_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_9 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_7 Depth=1
# Parent Loop BB2_8 Depth=2
# => This Inner Loop Header: Depth=3
movl $1065353216, (%rdx,%rdi,4) # imm = 0x3F800000
incq %rdi
cmpq $3, %rdi
jne .LBB2_9
# %bb.10: # %._crit_edge.i46
# in Loop: Header=BB2_8 Depth=2
incq %rsi
addq $12, %rdx
cmpq $3, %rsi
jne .LBB2_8
# %bb.11: # %._crit_edge23.i49
# in Loop: Header=BB2_7 Depth=1
incq %rax
addq $36, %rcx
cmpq $3, %rax
jne .LBB2_7
# %bb.12: # %_Z8init_matPfiiii.exit52
leaq 16(%rsp), %rdi
movl $401408, %esi # imm = 0x62000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $401408, %esi # imm = 0x62000
callq hipMalloc
movq %rsp, %rdi
movl $108, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $401408, %edx # imm = 0x62000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $108, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $64, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $14, 36(%rsp)
movl $14, 32(%rsp)
movl $512, 28(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13Convolution3DPfS_S_iii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $401408, %edx # imm = 0x62000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
callq hipGetLastError
testl %eax, %eax
je .LBB2_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_16:
callq hipProfilerStop
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Convolution3DPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Convolution3DPfS_S_iii,@object # @_Z13Convolution3DPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z13Convolution3DPfS_S_iii
.p2align 3, 0x0
_Z13Convolution3DPfS_S_iii:
.quad _Z28__device_stub__Convolution3DPfS_S_iii
.size _Z13Convolution3DPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error: %s
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13Convolution3DPfS_S_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Convolution3DPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Convolution3DPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13Convolution3DPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0040*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*0050*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000ee80000002600 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000f220000002500 */
/*0080*/ LEA R3, R5, R0, 0x3 ; /* 0x0000000005037211 */
/* 0x001fc800078e18ff */
/*0090*/ LEA R12, R4, R3, 0x6 ; /* 0x00000003040c7211 */
/* 0x002fca00078e30ff */
/*00a0*/ IMAD.HI R2, R12, 0x66666667, RZ ; /* 0x666666670c027827 */
/* 0x000fe200078e02ff */
/*00b0*/ LEA R10, R6, 0xffffffff, 0x3 ; /* 0xffffffff060a7811 */
/* 0x008fc600078e18ff */
/*00c0*/ IMAD.HI R8, R12, 0x51eb851f, RZ ; /* 0x51eb851f0c087827 */
/* 0x000fe200078e02ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*00e0*/ LEA.HI.SX32 R3, R2, R3, 0x1e ; /* 0x0000000302037211 */
/* 0x000fe400078ff2ff */
/*00f0*/ SHF.R.U32.HI R13, RZ, 0x1f, R8 ; /* 0x0000001fff0d7819 */
/* 0x000fc60000011608 */
/*0100*/ IMAD.HI R2, R3, 0x66666667, RZ ; /* 0x6666666703027827 */
/* 0x000fe200078e02ff */
/*0110*/ LEA.HI.SX32 R16, R8, R13, 0x1b ; /* 0x0000000d08107211 */
/* 0x000fe400078fdaff */
/*0120*/ LEA R8, R9, 0xffffffff, 0x3 ; /* 0xffffffff09087811 */
/* 0x004fe400078e18ff */
/*0130*/ SHF.R.U32.HI R11, RZ, 0x1f, R2 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011602 */
/*0140*/ IADD3 R14, R16, R8, RZ ; /* 0x00000008100e7210 */
/* 0x000fe40007ffe0ff */
/*0150*/ LEA.HI.SX32 R2, R2, R11, 0x1e ; /* 0x0000000b02027211 */
/* 0x000fe400078ff2ff */
/*0160*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x180], PT ; /* 0x000060000e007a0c */
/* 0x000fc40003f06270 */
/*0170*/ LEA R11, R7, 0xffffffff, 0x3 ; /* 0xffffffff070b7811 */
/* 0x010fe200078e18ff */
/*0180*/ IMAD R13, R2, -0xa, R3 ; /* 0xfffffff6020d7824 */
/* 0x000fe400078e0203 */
/*0190*/ IMAD R2, R3, -0xa, R12 ; /* 0xfffffff603027824 */
/* 0x000fc600078e020c */
/*01a0*/ IADD3 R15, R13, R10, RZ ; /* 0x0000000a0d0f7210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R3, R2, R11, RZ ; /* 0x0000000b02037210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LOP3.LUT R17, R15, R14, RZ, 0xfc, !PT ; /* 0x0000000e0f117212 */
/* 0x000fc800078efcff */
/*01d0*/ ISETP.GT.AND P0, PT, R17, -0x1, !P0 ; /* 0xffffffff1100780c */
/* 0x000fc80004704270 */
/*01e0*/ ISETP.LT.AND P0, PT, R15, c[0x0][0x17c], P0 ; /* 0x00005f000f007a0c */
/* 0x000fc80000701270 */
/*01f0*/ ISETP.GT.AND P0, PT, R3, -0x1, P0 ; /* 0xffffffff0300780c */
/* 0x000fc80000704270 */
/*0200*/ ISETP.LT.AND P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000701270 */
/*0210*/ @P0 IMAD R14, R14, c[0x0][0x17c], R15 ; /* 0x00005f000e0e0a24 */
/* 0x000fe200078e020f */
/*0220*/ @P0 MOV R15, 0x4 ; /* 0x00000004000f0802 */
/* 0x000fc60000000f00 */
/*0230*/ @P0 IMAD R14, R14, c[0x0][0x178], R3 ; /* 0x00005e000e0e0a24 */
/* 0x000fc800078e0203 */
/*0240*/ @P0 IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e0625 */
/* 0x000fcc00078e020f */
/*0250*/ @P0 LDG.E R14, [R14.64] ; /* 0x000000040e0e0981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R13, R16, 0xa, R13 ; /* 0x0000000a100d7824 */
/* 0x000fe200078e020d */
/*0270*/ IADD3 R12, R12, 0x200, RZ ; /* 0x000002000c0c7810 */
/* 0x000fe20007ffe0ff */
/*0280*/ BSSY B0, 0x4f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0290*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD R13, R13, 0xa, R2 ; /* 0x0000000a0d0d7824 */
/* 0x000fe200078e0202 */
/*02b0*/ ISETP.GT.AND P1, PT, R12, 0x3e7, PT ; /* 0x000003e70c00780c */
/* 0x000fe40003f24270 */
/*02c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*02d0*/ @!P0 STS [R13.X4], RZ ; /* 0x000000ff0d008388 */
/* 0x0001e80000004800 */
/*02e0*/ @P0 STS [R13.X4], R14 ; /* 0x0000000e0d000388 */
/* 0x0041ea0000004800 */
/*02f0*/ @P1 BRA 0x4e0 ; /* 0x000001e000001947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD.HI R13, R12, 0x66666667, RZ ; /* 0x666666670c0d7827 */
/* 0x001fc800078e02ff */
/*0310*/ IMAD.HI R16, R12, 0x51eb851f, RZ ; /* 0x51eb851f0c107827 */
/* 0x000fe200078e02ff */
/*0320*/ SHF.R.U32.HI R14, RZ, 0x1f, R13 ; /* 0x0000001fff0e7819 */
/* 0x000fc8000001160d */
/*0330*/ LEA.HI.SX32 R13, R13, R14, 0x1e ; /* 0x0000000e0d0d7211 */
/* 0x000fe400078ff2ff */
/*0340*/ SHF.R.U32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fc60000011610 */
/*0350*/ IMAD.HI R14, R13, 0x66666667, RZ ; /* 0x666666670d0e7827 */
/* 0x000fe200078e02ff */
/*0360*/ LEA.HI.SX32 R17, R16, R17, 0x1b ; /* 0x0000001110117211 */
/* 0x000fc600078fdaff */
/*0370*/ IMAD R12, R13, -0xa, R12 ; /* 0xfffffff60d0c7824 */
/* 0x000fe200078e020c */
/*0380*/ SHF.R.U32.HI R15, RZ, 0x1f, R14 ; /* 0x0000001fff0f7819 */
/* 0x000fe4000001160e */
/*0390*/ IADD3 R8, R8, R17, RZ ; /* 0x0000001108087210 */
/* 0x000fe40007ffe0ff */
/*03a0*/ LEA.HI.SX32 R14, R14, R15, 0x1e ; /* 0x0000000f0e0e7211 */
/* 0x000fe400078ff2ff */
/*03b0*/ IADD3 R11, R11, R12, RZ ; /* 0x0000000c0b0b7210 */
/* 0x000fc60007ffe0ff */
/*03c0*/ IMAD R15, R14, -0xa, R13 ; /* 0xfffffff60e0f7824 */
/* 0x000fca00078e020d */
/*03d0*/ IADD3 R19, R10, R15, RZ ; /* 0x0000000f0a137210 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD R15, R17, 0xa, R15 ; /* 0x0000000a110f7824 */
/* 0x000fc600078e020f */
/*03f0*/ LOP3.LUT R10, R19, R8, RZ, 0xfc, !PT ; /* 0x00000008130a7212 */
/* 0x000fe200078efcff */
/*0400*/ IMAD R15, R15, 0xa, R12 ; /* 0x0000000a0f0f7824 */
/* 0x000fc600078e020c */
/*0410*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fc80003f04270 */
/*0420*/ ISETP.LT.AND P0, PT, R8.reuse, c[0x0][0x180], P0 ; /* 0x0000600008007a0c */
/* 0x040fe20000701270 */
/*0430*/ IMAD R8, R8, c[0x0][0x17c], R19 ; /* 0x00005f0008087a24 */
/* 0x000fc600078e0213 */
/*0440*/ ISETP.LT.AND P0, PT, R19, c[0x0][0x17c], P0 ; /* 0x00005f0013007a0c */
/* 0x000fc80000701270 */
/*0450*/ ISETP.GT.AND P0, PT, R11, -0x1, P0 ; /* 0xffffffff0b00780c */
/* 0x000fc80000704270 */
/*0460*/ ISETP.LT.AND P0, PT, R11, c[0x0][0x178], P0 ; /* 0x00005e000b007a0c */
/* 0x000fe20000701270 */
/*0470*/ IMAD R11, R8, c[0x0][0x178], R11 ; /* 0x00005e00080b7a24 */
/* 0x000fd800078e020b */
/*0480*/ @!P0 STS [R15.X4], RZ ; /* 0x000000ff0f008388 */
/* 0x0001e20000004800 */
/*0490*/ @!P0 BRA 0x4e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fd400000001ff */
/*04b0*/ IMAD.WIDE R10, R11, R10, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e020a */
/*04c0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ STS [R15.X4], R10 ; /* 0x0000000a0f007388 */
/* 0x0043e40000004800 */
/*04e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x001ea8000c1e1900 */
/*0510*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x002f68000c1e1900 */
/*0540*/ LDG.E R16, [R2.64+0x10] ; /* 0x0000100402107981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x000f68000c1e1900 */
/*0560*/ LDG.E R18, [R2.64+0x18] ; /* 0x0000180402127981 */
/* 0x000f68000c1e1900 */
/*0570*/ LDG.E R24, [R2.64+0x1c] ; /* 0x00001c0402187981 */
/* 0x000f68000c1e1900 */
/*0580*/ LDG.E R22, [R2.64+0x20] ; /* 0x0000200402167981 */
/* 0x000f68000c1e1900 */
/*0590*/ LDG.E R20, [R2.64+0x24] ; /* 0x0000240402147981 */
/* 0x000f68000c1e1900 */
/*05a0*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280402087981 */
/* 0x000f62000c1e1900 */
/*05b0*/ IMAD R11, R4, 0xa, R5 ; /* 0x0000000a040b7824 */
/* 0x000fc600078e0205 */
/*05c0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000162000c1e1900 */
/*05d0*/ IMAD R11, R11, 0xa, R0 ; /* 0x0000000a0b0b7824 */
/* 0x000fc600078e0200 */
/*05e0*/ LDG.E R12, [R2.64+0x30] ; /* 0x00003004020c7981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDS R26, [R11.X4] ; /* 0x000000000b1a7984 */
/* 0x000ea80000004800 */
/*0600*/ LDS R25, [R11.X4+0x4] ; /* 0x000004000b197984 */
/* 0x000ee80000004800 */
/*0610*/ LDS R19, [R11.X4+0x8] ; /* 0x000008000b137984 */
/* 0x000f280000004800 */
/*0620*/ LDS R28, [R11.X4+0x28] ; /* 0x000028000b1c7984 */
/* 0x000f680000004800 */
/*0630*/ LDS R21, [R11.X4+0x2c] ; /* 0x00002c000b157984 */
/* 0x000e620000004800 */
/*0640*/ FFMA R13, R13, R26, RZ ; /* 0x0000001a0d0d7223 */
/* 0x004fc600000000ff */
/*0650*/ LDS R26, [R11.X4+0x30] ; /* 0x000030000b1a7984 */
/* 0x000ea20000004800 */
/*0660*/ FFMA R23, R23, R25, R13 ; /* 0x0000001917177223 */
/* 0x008fc6000000000d */
/*0670*/ LDG.E R13, [R2.64+0x34] ; /* 0x00003404020d7981 */
/* 0x0000e2000c1e1900 */
/*0680*/ FFMA R23, R14, R19, R23 ; /* 0x000000130e177223 */
/* 0x010fc60000000017 */
/*0690*/ LDS R19, [R11.X4+0x50] ; /* 0x000050000b137984 */
/* 0x000f280000004800 */
/*06a0*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0000e2000c1e1900 */
/*06b0*/ FFMA R23, R15, R28, R23 ; /* 0x0000001c0f177223 */
/* 0x020fc60000000017 */
/*06c0*/ LDS R25, [R11.X4+0x54] ; /* 0x000054000b197984 */
/* 0x000f620000004800 */
/*06d0*/ FFMA R21, R16, R21, R23 ; /* 0x0000001510157223 */
/* 0x002fc60000000017 */
/*06e0*/ LDG.E R15, [R2.64+0x3c] ; /* 0x00003c04020f7981 */
/* 0x0000e8000c1e1900 */
/*06f0*/ LDS R23, [R11.X4+0x58] ; /* 0x000058000b177984 */
/* 0x000e680000004800 */
/*0700*/ LDG.E R16, [R2.64+0x40] ; /* 0x0000400402107981 */
/* 0x0000e8000c1e1900 */
/*0710*/ LDS R28, [R11.X4+0x1c0] ; /* 0x0001c0000b1c7984 */
/* 0x000fe20000004800 */
/*0720*/ FFMA R26, R17, R26, R21 ; /* 0x0000001a111a7223 */
/* 0x004fc60000000015 */
/*0730*/ LDS R21, [R11.X4+0x190] ; /* 0x000190000b157984 */
/* 0x000ea80000004800 */
/*0740*/ LDG.E R17, [R2.64+0x44] ; /* 0x0000440402117981 */
/* 0x0000e2000c1e1900 */
/*0750*/ FFMA R26, R18, R19, R26 ; /* 0x00000013121a7223 */
/* 0x010fc6000000001a */
/*0760*/ LDS R19, [R11.X4+0x194] ; /* 0x000194000b137984 */
/* 0x000f280000004800 */
/*0770*/ LDG.E R18, [R2.64+0x48] ; /* 0x0000480402127981 */
/* 0x0000e2000c1e1900 */
/*0780*/ FFMA R26, R24, R25, R26 ; /* 0x00000019181a7223 */
/* 0x020fc6000000001a */
/*0790*/ LDG.E R25, [R2.64+0x4c] ; /* 0x00004c0402197981 */
/* 0x000168000c1e1900 */
/*07a0*/ LDG.E R24, [R2.64+0x50] ; /* 0x0000500402187981 */
/* 0x000162000c1e1900 */
/*07b0*/ FFMA R26, R22, R23, R26 ; /* 0x00000017161a7223 */
/* 0x002fc6000000001a */
/*07c0*/ LDG.E R23, [R2.64+0x54] ; /* 0x0000540402177981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R22, [R2.64+0x58] ; /* 0x0000580402167981 */
/* 0x000162000c1e1900 */
/*07e0*/ FFMA R26, R20, R21, R26 ; /* 0x00000015141a7223 */
/* 0x004fc6000000001a */
/*07f0*/ LDG.E R21, [R2.64+0x5c] ; /* 0x00005c0402157981 */
/* 0x0000a8000c1e1900 */
/*0800*/ LDG.E R20, [R2.64+0x60] ; /* 0x0000600402147981 */
/* 0x0000a2000c1e1900 */
/*0810*/ FFMA R27, R8, R19, R26 ; /* 0x00000013081b7223 */
/* 0x010fc6000000001a */
/*0820*/ LDG.E R8, [R2.64+0x64] ; /* 0x0000640402087981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R19, [R2.64+0x68] ; /* 0x0000680402137981 */
/* 0x000128000c1e1900 */
/*0840*/ LDS R26, [R11.X4+0x198] ; /* 0x000198000b1a7984 */
/* 0x000e680000004800 */
/*0850*/ LDS R3, [R11.X4+0x320] ; /* 0x000320000b037984 */
/* 0x001fe80000004800 */
/*0860*/ LDS R2, [R11.X4+0x324] ; /* 0x000324000b027984 */
/* 0x000fe20000004800 */
/*0870*/ FFMA R27, R10, R26, R27 ; /* 0x0000001a0a1b7223 */
/* 0x002fc6000000001b */
/*0880*/ LDS R10, [R11.X4+0x1b8] ; /* 0x0001b8000b0a7984 */
/* 0x000e280000004800 */
/*0890*/ LDS R26, [R11.X4+0x1bc] ; /* 0x0001bc000b1a7984 */
/* 0x000ee20000004800 */
/*08a0*/ FFMA R12, R12, R10, R27 ; /* 0x0000000a0c0c7223 */
/* 0x001fc6000000001b */
/*08b0*/ LDS R10, [R11.X4+0x1e0] ; /* 0x0001e0000b0a7984 */
/* 0x000e280000004800 */
/*08c0*/ LDS R27, [R11.X4+0x1e4] ; /* 0x0001e4000b1b7984 */
/* 0x000e620000004800 */
/*08d0*/ LEA R4, R9, R4, 0x3 ; /* 0x0000000409047211 */
/* 0x000fe400078e18ff */
/*08e0*/ LEA R5, R6, R5, 0x3 ; /* 0x0000000506057211 */
/* 0x000fe400078e18ff */
/*08f0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe40003f06270 */
/*0900*/ LEA R0, R7, R0, 0x3 ; /* 0x0000000007007211 */
/* 0x000fc400078e18ff */
/*0910*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fc80000706670 */
/*0920*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0930*/ @!P0 IMAD R5, R4, c[0x0][0x17c], R5 ; /* 0x00005f0004058a24 */
/* 0x000fe200078e0205 */
/*0940*/ @!P0 MOV R4, 0x4 ; /* 0x0000000400048802 */
/* 0x000fe20000000f00 */
/*0950*/ FFMA R13, R13, R26, R12 ; /* 0x0000001a0d0d7223 */
/* 0x008fe4000000000c */
/*0960*/ LDS R12, [R11.X4+0x1e8] ; /* 0x0001e8000b0c7984 */
/* 0x000ee40000004800 */
/*0970*/ FFMA R13, R14, R28, R13 ; /* 0x0000001c0e0d7223 */
/* 0x000fe4000000000d */
/*0980*/ LDS R14, [R11.X4+0x350] ; /* 0x000350000b0e7984 */
/* 0x000fe40000004800 */
/*0990*/ FFMA R15, R15, R10, R13 ; /* 0x0000000a0f0f7223 */
/* 0x001fc4000000000d */
/*09a0*/ LDS R13, [R11.X4+0x328] ; /* 0x000328000b0d7984 */
/* 0x000e280000004800 */
/*09b0*/ LDS R10, [R11.X4+0x348] ; /* 0x000348000b0a7984 */
/* 0x000f620000004800 */
/*09c0*/ FFMA R16, R16, R27, R15 ; /* 0x0000001b10107223 */
/* 0x002fc6000000000f */
/*09d0*/ LDS R15, [R11.X4+0x34c] ; /* 0x00034c000b0f7984 */
/* 0x000e680000004800 */
/*09e0*/ LDS R27, [R11.X4+0x370] ; /* 0x000370000b1b7984 */
/* 0x000ea20000004800 */
/*09f0*/ FFMA R16, R17, R12, R16 ; /* 0x0000000c11107223 */
/* 0x008fc60000000010 */
/*0a00*/ LDS R17, [R11.X4+0x374] ; /* 0x000374000b117984 */
/* 0x000f280000004800 */
/*0a10*/ LDS R12, [R11.X4+0x378] ; /* 0x000378000b0c7984 */
/* 0x000ee20000004800 */
/*0a20*/ FFMA R3, R18, R3, R16 ; /* 0x0000000312037223 */
/* 0x000fc80000000010 */
/*0a30*/ FFMA R2, R25, R2, R3 ; /* 0x0000000219027223 */
/* 0x020fc80000000003 */
/*0a40*/ FFMA R2, R24, R13, R2 ; /* 0x0000000d18027223 */
/* 0x001fc80000000002 */
/*0a50*/ FFMA R2, R23, R10, R2 ; /* 0x0000000a17027223 */
/* 0x000fc80000000002 */
/*0a60*/ FFMA R2, R22, R15, R2 ; /* 0x0000000f16027223 */
/* 0x002fe40000000002 */
/*0a70*/ @!P0 IMAD R3, R5, c[0x0][0x178], R0 ; /* 0x00005e0005038a24 */
/* 0x000fe400078e0200 */
/*0a80*/ FFMA R2, R21, R14, R2 ; /* 0x0000000e15027223 */
/* 0x004fc80000000002 */
/*0a90*/ FFMA R2, R20, R27, R2 ; /* 0x0000001b14027223 */
/* 0x000fc80000000002 */
/*0aa0*/ FFMA R8, R8, R17, R2 ; /* 0x0000001108087223 */
/* 0x010fe40000000002 */
/*0ab0*/ @!P0 IMAD.WIDE R2, R3, R4, c[0x0][0x170] ; /* 0x00005c0003028625 */
/* 0x000fc800078e0204 */
/*0ac0*/ FFMA R19, R19, R12, R8 ; /* 0x0000000c13137223 */
/* 0x008fca0000000008 */
/*0ad0*/ @!P0 STG.E [R2.64], R19 ; /* 0x0000001302008986 */
/* 0x000fe8000c101904 */
/*0ae0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Convolution3DPfS_S_iii
.globl _Z13Convolution3DPfS_S_iii
.p2align 8
.type _Z13Convolution3DPfS_S_iii,@function
_Z13Convolution3DPfS_S_iii:
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v4, v0, 20, 10
v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_lshlrev_b32_e32 v0, 3, v2
v_lshlrev_b32_e32 v1, 6, v4
s_lshl_b32 s11, s15, 3
s_lshl_b32 s12, s14, 3
s_lshl_b32 s13, s13, 3
s_mov_b32 s8, exec_lo
v_add3_u32 v5, v0, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v5, 0xcccccccd
v_mul_hi_u32 v6, v5, 0x28f5c29
v_lshrrev_b32_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v9, s11, -1, v6
v_mul_hi_u32 v1, v0, 0x1999999a
v_mul_u32_u24_e32 v7, 10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v7, v5, v7
v_mul_lo_u32 v1, v1, 10
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v0, v1
v_cmpx_lt_i32_e32 -1, v9
s_cbranch_execz .LBB0_6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v0, s12, -1, v8
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s10, v9
v_mov_b32_e32 v10, 0
v_cmp_lt_i32_e64 s2, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_5
v_add3_u32 v1, s13, -1, v7
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v1
v_cmp_lt_i32_e64 s3, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[10:11], null, v9, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v10, s4, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[11:12]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v10, v[0:1], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s8
v_mul_lo_u32 v0, v8, 40
v_lshlrev_b32_e32 v1, 2, v7
v_mul_u32_u24_e32 v6, 0x190, v6
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v6, v0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v0, v10
v_cmpx_gt_u32_e32 0x1e8, v5
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v0, 0x200, v5
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, 0xcccccccd
v_lshrrev_b32_e32 v1, 3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v1, 0x1999999a
v_mul_lo_u32 v7, v1, 10
v_mul_lo_u32 v9, v6, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v0, v7
v_sub_nc_u32_e32 v7, v1, v9
v_mov_b32_e32 v9, 0
v_mul_hi_u32 v5, v0, 0x28f5c29
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v8, s11, -1, v5
v_cmpx_lt_i32_e32 -1, v8
s_cbranch_execz .LBB0_13
v_add3_u32 v0, s12, -1, v7
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s10, v8
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s2, -1, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_12
v_add3_u32 v1, s13, -1, v6
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v1
v_cmp_lt_i32_e64 s3, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_11
v_mad_u64_u32 v[9:10], null, v8, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v9, s4, v[1:2]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[10:11]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v9, v[0:1], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s9
v_mul_lo_u32 v0, v7, 40
v_lshlrev_b32_e32 v1, 2, v6
v_mul_u32_u24_e32 v5, 0x190, v5
v_add3_u32 v0, v5, v0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v0, v9
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_u32_u24_e32 v0, 0x190, v4
v_mul_u32_u24_e32 v1, 40, v2
v_lshlrev_b32_e32 v5, 2, v3
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add3_u32 v0, v0, v1, v5
v_mov_b32_e32 v5, 0
.p2align 6
.LBB0_15:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v1, v0
s_mov_b64 s[6:7], s[2:3]
s_mov_b32 s15, 0
.p2align 6
.LBB0_16:
s_mov_b32 s16, 0
s_mov_b64 s[8:9], s[6:7]
.LBB0_17:
v_add_nc_u32_e32 v6, s16, v1
s_load_b32 s17, s[8:9], 0x0
s_add_i32 s16, s16, 4
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
ds_load_b32 v6, v6
s_cmp_lg_u32 s16, 12
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, s17, v6
s_cbranch_scc1 .LBB0_17
s_add_i32 s15, s15, 1
v_add_nc_u32_e32 v1, 40, v1
s_add_u32 s6, s6, 12
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s15, 3
s_cbranch_scc1 .LBB0_16
s_add_i32 s14, s14, 1
v_add_nc_u32_e32 v0, 0x190, v0
s_add_u32 s2, s2, 36
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s14, 3
s_cbranch_scc1 .LBB0_15
v_add_nc_u32_e32 v4, s11, v4
v_add_nc_u32_e32 v1, s12, v2
v_add_nc_u32_e32 v0, s13, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s10, v4
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s4, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_22
v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Convolution3DPfS_S_iii
.amdhsa_group_segment_fixed_size 4000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Convolution3DPfS_S_iii, .Lfunc_end0-_Z13Convolution3DPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4000
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Convolution3DPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13Convolution3DPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018ce08_00000000-6_3DConv.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8init_matPfiiii
.type _Z8init_matPfiiii, @function
_Z8init_matPfiiii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r9
movl %esi, %ebx
movl %edx, %r10d
movl %ecx, %edi
movl %edx, %r13d
imull %ecx, %r13d
movl $0, %r12d
movl $0, %ebp
movslq %ecx, %r11
jmp .L5
.L8:
movslq %esi, %rdx
leaq (%r9,%rdx,4), %rax
addq %r11, %rdx
leaq (%r9,%rdx,4), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
.L6:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
.L9:
addl $1, %ecx
addl %edi, %esi
cmpl %ecx, %r10d
je .L7
.L10:
testl %edi, %edi
jg .L8
jmp .L9
.L7:
addl $1, %ebp
addl %r13d, %r12d
cmpl %ebp, %ebx
je .L3
.L5:
movl %r12d, %esi
movl $0, %ecx
testl %r10d, %r10d
jg .L10
jmp .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3669:
.size _Z8init_matPfiiii, .-_Z8init_matPfiiii
.globl _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
.type _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii, @function
_Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13Convolution3DPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii, .-_Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
.globl _Z13Convolution3DPfS_S_iii
.type _Z13Convolution3DPfS_S_iii, @function
_Z13Convolution3DPfS_S_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z13Convolution3DPfS_S_iii, .-_Z13Convolution3DPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Error: %s;"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $401408, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %r8d
movl $512, %ecx
movl $14, %edx
movl $14, %esi
movq %rax, %rdi
call _Z8init_matPfiiii
movl $108, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %r8d
movl $3, %ecx
movl $3, %edx
movl $3, %esi
movq %rax, %rdi
call _Z8init_matPfiiii
leaq 8(%rsp), %rdi
movl $401408, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $401408, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $108, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $401408, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $108, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 32(%rsp)
movl $8, 36(%rsp)
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $8, %ecx
movq 44(%rsp), %rdi
movl $64, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $401408, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
.L28:
call cudaProfilerStop@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl $512, %r9d
movl $14, %r8d
movl $14, %ecx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z13Convolution3DPfS_S_iiiPfS_S_iii
jmp .L27
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13Convolution3DPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Convolution3DPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "3DConv.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__Convolution3DPfS_S_iii # -- Begin function _Z28__device_stub__Convolution3DPfS_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__Convolution3DPfS_S_iii,@function
_Z28__device_stub__Convolution3DPfS_S_iii: # @_Z28__device_stub__Convolution3DPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Convolution3DPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__Convolution3DPfS_S_iii, .Lfunc_end0-_Z28__device_stub__Convolution3DPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z8init_matPfiiii # -- Begin function _Z8init_matPfiiii
.p2align 4, 0x90
.type _Z8init_matPfiiii,@function
_Z8init_matPfiiii: # @_Z8init_matPfiiii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_10
# %bb.1: # %.preheader20.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cvtsi2ss %r8d, %xmm0
movl %esi, %eax
movl %edx, %esi
movl %ecx, %r8d
movl %ecx, %r9d
imull %edx, %r9d
xorl %r10d, %r10d
xorl %r11d, %r11d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge23
# in Loop: Header=BB1_2 Depth=1
incq %r11
addl %r9d, %r10d
cmpq %rax, %r11
je .LBB1_9
.LBB1_2: # %.preheader20
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %edx, %edx
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r10d, %ebx
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incq %r14
addl %ecx, %ebx
cmpq %rsi, %r14
je .LBB1_8
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
testl %ecx, %ecx
jle .LBB1_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=2
movslq %ebx, %r15
leaq (%rdi,%r15,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r8
jne .LBB1_6
jmp .LBB1_7
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_10: # %._crit_edge25
retq
.Lfunc_end1:
.size _Z8init_matPfiiii, .Lfunc_end1-_Z8init_matPfiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $401408, %edi # imm = 0x62000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB2_1: # %.preheader20.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
movq %rcx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # %.preheader.i
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movl $1073741824, (%rdx,%rdi,4) # imm = 0x40000000
incq %rdi
cmpq $512, %rdi # imm = 0x200
jne .LBB2_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB2_2 Depth=2
incq %rsi
addq $2048, %rdx # imm = 0x800
cmpq $14, %rsi
jne .LBB2_2
# %bb.5: # %._crit_edge23.i
# in Loop: Header=BB2_1 Depth=1
incq %rax
addq $28672, %rcx # imm = 0x7000
cmpq $14, %rax
jne .LBB2_1
# %bb.6: # %_Z8init_matPfiiii.exit
movl $108, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB2_7: # %.preheader20.i39
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
# Child Loop BB2_9 Depth 3
movq %rcx, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_8: # %.preheader.i41
# Parent Loop BB2_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_9 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_9: # Parent Loop BB2_7 Depth=1
# Parent Loop BB2_8 Depth=2
# => This Inner Loop Header: Depth=3
movl $1065353216, (%rdx,%rdi,4) # imm = 0x3F800000
incq %rdi
cmpq $3, %rdi
jne .LBB2_9
# %bb.10: # %._crit_edge.i46
# in Loop: Header=BB2_8 Depth=2
incq %rsi
addq $12, %rdx
cmpq $3, %rsi
jne .LBB2_8
# %bb.11: # %._crit_edge23.i49
# in Loop: Header=BB2_7 Depth=1
incq %rax
addq $36, %rcx
cmpq $3, %rax
jne .LBB2_7
# %bb.12: # %_Z8init_matPfiiii.exit52
leaq 16(%rsp), %rdi
movl $401408, %esi # imm = 0x62000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $401408, %esi # imm = 0x62000
callq hipMalloc
movq %rsp, %rdi
movl $108, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $401408, %edx # imm = 0x62000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $108, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $64, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $14, 36(%rsp)
movl $14, 32(%rsp)
movl $512, 28(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13Convolution3DPfS_S_iii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $401408, %edx # imm = 0x62000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
callq hipGetLastError
testl %eax, %eax
je .LBB2_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_16:
callq hipProfilerStop
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Convolution3DPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Convolution3DPfS_S_iii,@object # @_Z13Convolution3DPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z13Convolution3DPfS_S_iii
.p2align 3, 0x0
_Z13Convolution3DPfS_S_iii:
.quad _Z28__device_stub__Convolution3DPfS_S_iii
.size _Z13Convolution3DPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error: %s
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13Convolution3DPfS_S_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Convolution3DPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Convolution3DPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
__global__ void Mirror(unsigned int *Da, unsigned int *Dc, int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
Dc[id] = Da[bx * bn + bn - 1 - tx];
}
__global__ void Filter_func(unsigned int *Da, unsigned int *Dc, int high,int width, unsigned int *Filter, int filtersum)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
__shared__ unsigned int share[512 * 3];
if(bx == 0 || bx == bn - 1){
if(bx == 0){
share[tx + bn] = Da[id];
share[tx + 2* bn] = Da[id + bn];
}else{
share[tx + bn] = Da[id];
share[tx] = Da[id - bn];
}
}else{
share[tx] = Da[id - bn];
share[tx + bn] = Da[id];
share[tx + 2 * bn] = Da[id + bn];
}
__syncthreads();
int sum = 0;
if(bx != 0 && tx % 512 != 0) // ¥ª¤W¨S¶W¥X½d³ò
sum += Filter[0] * share[tx - 1];
if(bx != 0) // ¤W±¨S¶W¥X½d³ò
sum += Filter[1] * share[tx];
if(bx != 0 && (tx + 1) % 512 != 0) // ¥k¤W¨S¶W¥X½d³ò
sum += Filter[2] * share[tx + 1];
if(tx % 512 != 0) // ¥ªÃä¨S¶W¥X½d³ò
sum += Filter[3] * share[tx + bn - 1];
sum += Filter[4] * share[tx + bn];
if((tx + 1) % 512 != 0) // ¥kÃä¨S¶W¥X½d³ò
sum += Filter[5] * share[tx + bn + 1];
if(bx != bn - 1 && tx % 512 != 0) // ¥ª¤U¨S¶W¥X½d³ò
sum += Filter[6] * share[tx + 2 * bn - 1];
if(bx != bn - 1) // ¤U±¨S¶W¥X½d³ò
sum += Filter[7] * share[tx + 2 * bn];
if(bx != bn - 1 && (tx + 1) % 512 != 0) // ¥k¤U¨S¶W¥X½d³ò
sum += Filter[8] * share[tx + 2 * bn + 1];
Dc[id] = sum / filtersum;
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset, nthread, nblock;
unsigned char *head;
unsigned char *img;
unsigned int *da;
unsigned int filter[9] = {1,2,1,2,4,2,1,2,1};
char c, sel;
printf("What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n");
scanf("%c", &sel);
getchar();
if(sel == 'A' || sel == 'a'){
printf("Do you want to input filter values by yourself? (Y/N)\n");
scanf("%c", &c);
getchar();
if(c == 'Y' || c == 'y'){
printf("Please input 9 filter values:\n");
for(int i = 0; i < 9; ++i)
scanf("%d", &filter[i]);
getchar();
}
}
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb"); // rb¬Oread binary
fseek(fp, 10, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä10Óbyte¡A¦]¬°offset©ñ¦bheaderªº²Ä10~13Óbyte
fread(&offset, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìoffset
fseek(fp, 18, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä18Óbyte¡A¦]¬°width©ñ¦bheaderªº²Ä18~21Óbyte
fread(&width, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìwidth
fseek(fp, 22, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä22Óbyte¡A¦]¬°high©ñ¦bheaderªº²Ä22~25Óbyte
fread(&high, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìhigh
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high)); // °t¸m¤@Ówidth*highªºbyte¼Æ¤j¤pµ¹img(unsigned char¬O1byte)
da = (unsigned int*)malloc(sizeof(unsigned int)*(width*high));
fseek(fp, offset, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâoffsetÓbyteªº¦ì¸m¡A¦]¬°offset¦sªº¦ì¸m¬O¶}©l¦spixelªº¦ì¸m
fread(img, sizeof(char), (width*high), fp); // ±qfpŪwidth*highÓcharªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìimg
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset)); // °t¸m¤@Óoffsetªºbyte¼Æ¤j¤pµ¹img
fseek(fp, 0, SEEK_SET); // §â´å¼Ð²¾¨ìfpªº¤@¶}©l¡A±qÀYªº¦ì¸m¨ìoffsetªº¦ì¸m¬O©ñ¼ÐÀYÀÉ
fread(head, sizeof(unsigned char), offset, fp); // ±qfpŪoffsetÓunsigned charªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìhead
if(width > 1024){ // ¼°_¨Ónµ¥©ówidth*high¡Athreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = high * width / 1024;
}else{
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1);
dim3 grid(nblock, 1, 1);
for(int i = 0; i < high * width; ++i)
da[i] = img[i];
int filtersum = 0;
for(int i = 0; i < 9; ++i)
filtersum += filter[i];
unsigned int *Da;
cudaMalloc((void**)&Da, (sizeof(unsigned int)*(width*high)));
unsigned int *Dc;
cudaMalloc((void**)&Dc, (sizeof(unsigned int)*(width*high)));
unsigned int *Filter;
cudaMalloc((void**)&Filter, (sizeof(unsigned int)*9));
cudaMemcpy(Da, da, (sizeof(unsigned int)*(width*high)), cudaMemcpyHostToDevice);
if(sel == 'A' || sel == 'a'){
Filter_func <<< nblock, nthread >>> (Da,Dc,high,width,Filter,filtersum);
cudaMemcpy(Filter, filter, (sizeof(unsigned int)*9), cudaMemcpyHostToDevice);
}else if(sel == 'B' || sel == 'b'){
Mirror <<< nblock, nthread >>> (Da,Dc,high,width);
}
cudaThreadSynchronize();
cudaMemcpy(da, Dc, (sizeof(unsigned int)*(width*high)), cudaMemcpyDeviceToHost);
for(int i = 0; i < high * width; ++i)
img[i] = da[i];
fp = fopen("lena3.bmp","wb+");
fwrite(head, sizeof(unsigned char), offset, fp);
fwrite(img, sizeof(unsigned int), (width*high), fp);
fclose(fp);
} | code for sm_80
Function : _Z11Filter_funcPjS_iiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e640000002100 */
/*0050*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.NE.AND P0, PT, R0.reuse, R5, PT ; /* 0x000000050000720c */
/* 0x041fe40003f05270 */
/*0070*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f25270 */
/*0080*/ ISETP.EQ.OR P2, PT, R0.reuse, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x040fe20004742670 */
/*0090*/ IMAD R6, R0, c[0x0][0x0], R7 ; /* 0x0000000000067a24 */
/* 0x002fd800078e0207 */
/*00a0*/ @P2 BRA 0x1a0 ; /* 0x000000f000002947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R2, R6, -c[0x0][0x0], RZ ; /* 0x8000000006027a10 */
/* 0x000fd20007ffe0ff */
/*00d0*/ IMAD.WIDE R10, R6, R9, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fe400078e020a */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1900 */
/*0130*/ IMAD.SHL.U32 R15, R7, 0x4, RZ ; /* 0x00000004070f7824 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R15, R4, 0x4, R15 ; /* 0x00000004040f7824 */
/* 0x000fca00078e020f */
/*0150*/ LEA R17, R4, R15, 0x2 ; /* 0x0000000f04117211 */
/* 0x000fe200078e10ff */
/*0160*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*0170*/ STS [R15], R10 ; /* 0x0000000a0f007388 */
/* 0x0081e80000000800 */
/*0180*/ STS [R17], R12 ; /* 0x0000000c11007388 */
/* 0x0101e20000000800 */
/*0190*/ BRA 0x280 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*01b0*/ @P1 IADD3 R10, R6, -c[0x0][0x0], RZ ; /* 0x80000000060a1a10 */
/* 0x000fc60007ffe0ff */
/*01c0*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0209 */
/*01d0*/ @P1 IMAD.WIDE R10, R10, R9, c[0x0][0x160] ; /* 0x000058000a0a1625 */
/* 0x000fc800078e0209 */
/*01e0*/ @!P1 IMAD.WIDE R12, R4, 0x4, R2 ; /* 0x00000004040c9825 */
/* 0x000fe400078e0202 */
/*01f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0200*/ @P1 LDG.E R10, [R10.64] ; /* 0x000000040a0a1981 */
/* 0x000ee8000c1e1900 */
/*0210*/ @!P1 LDG.E R12, [R12.64] ; /* 0x000000040c0c9981 */
/* 0x000f22000c1e1900 */
/*0220*/ IADD3 R8, R7, c[0x0][0x0], RZ ; /* 0x0000000007087a10 */
/* 0x000fca0007ffe0ff */
/*0230*/ IMAD.SHL.U32 R15, R8, 0x4, RZ ; /* 0x00000004080f7824 */
/* 0x000fca00078e00ff */
/*0240*/ @!P1 LEA R15, R4, R15, 0x2 ; /* 0x0000000f040f9211 */
/* 0x000fe200078e10ff */
/*0250*/ STS [R8.X4], R3 ; /* 0x0000000308007388 */
/* 0x0041e80000004800 */
/*0260*/ @P1 STS [R7.X4], R10 ; /* 0x0000000a07001388 */
/* 0x0081e80000004800 */
/*0270*/ @!P1 STS [R15], R12 ; /* 0x0000000c0f009388 */
/* 0x0101e40000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x001fc40007ffe0ff */
/*02a0*/ LOP3.LUT P2, RZ, R7, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff07ff7812 */
/* 0x000fe4000784c0ff */
/*02b0*/ LOP3.LUT P3, RZ, R2, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff02ff7812 */
/* 0x000fe2000786c0ff */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.EQ.OR P4, PT, R0, R5, !P2 ; /* 0x000000050000720c */
/* 0x000fe40005782670 */
/*02e0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fce0000000f00 */
/*02f0*/ @P2 LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d2981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000168000c1e1900 */
/*0310*/ @P3 LDG.E R8, [R2.64+0x14] ; /* 0x0000140402083981 */
/* 0x000168000c1e1900 */
/*0320*/ @!P4 LDG.E R10, [R2.64+0x18] ; /* 0x00001804020ac981 */
/* 0x000162000c1e1900 */
/*0330*/ IABS R11, c[0x0][0x180] ; /* 0x00006000000b7a13 */
/* 0x000fe20000000000 */
/*0340*/ @P2 IMAD.IADD R16, R5, 0x1, R7 ; /* 0x0000000105102824 */
/* 0x000fe200078e0207 */
/*0350*/ @!P4 LEA R19, R4, R7, 0x1 ; /* 0x000000070413c211 */
/* 0x000fe200078e08ff */
/*0360*/ BSSY B0, 0x470 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0370*/ I2F.RP R18, R11 ; /* 0x0000000b00127306 */
/* 0x000e620000209400 */
/*0380*/ IADD3 R12, R7, c[0x0][0x0], RZ ; /* 0x00000000070c7a10 */
/* 0x000fc40007ffe0ff */
/*0390*/ @P2 LDS R16, [R16.X4] ; /* 0x0000000010102984 */
/* 0x000ea20000004800 */
/*03a0*/ ISETP.EQ.OR P5, PT, R0, RZ, !P2 ; /* 0x000000ff0000720c */
/* 0x000fe200057a2670 */
/*03b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*03c0*/ LDS R15, [R12.X4] ; /* 0x000000000c0f7984 */
/* 0x0000e80000004800 */
/*03d0*/ @P3 LDS R17, [R12.X4+0x4] ; /* 0x000004000c113984 */
/* 0x0001280000004800 */
/*03e0*/ @!P4 LDS R19, [R19.X4+-0x4] ; /* 0xfffffc001313c984 */
/* 0x000e220000004800 */
/*03f0*/ MUFU.RCP R18, R18 ; /* 0x0000001200127308 */
/* 0x002e640000001000 */
/*0400*/ IADD3 R5, R18, 0xffffffe, RZ ; /* 0x0ffffffe12057810 */
/* 0x002fcc0007ffe0ff */
/*0410*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e62000021f000 */
/*0420*/ @P5 BRA 0x460 ; /* 0x0000003000005947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x010f28000c1e1900 */
/*0440*/ LDS R21, [R7.X4+-0x4] ; /* 0xfffffc0007157984 */
/* 0x000f240000004800 */
/*0450*/ IMAD R0, R0, R21, RZ ; /* 0x0000001500007224 */
/* 0x010fe400078e02ff */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ @!P1 BRA 0x500 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R18, R7, 0x1, RZ ; /* 0x0000000107127810 */
/* 0x000fe20007ffe0ff */
/*0490*/ LDS R21, [R7.X4] ; /* 0x0000000007157984 */
/* 0x000f260000004800 */
/*04a0*/ LOP3.LUT P1, RZ, R18, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff12ff7812 */
/* 0x000fc4000782c0ff */
/*04b0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000f36000c1e1900 */
/*04c0*/ @P1 LDG.E R20, [R2.64+0x8] ; /* 0x0000080402141981 */
/* 0x008ee8000c1e1900 */
/*04d0*/ @P1 LDS R23, [R7.X4+0x4] ; /* 0x0000040007171984 */
/* 0x000ee20000004800 */
/*04e0*/ IMAD R0, R21, R18, R0 ; /* 0x0000001215007224 */
/* 0x010fc800078e0200 */
/*04f0*/ @P1 IMAD R0, R23, R20, R0 ; /* 0x0000001417001224 */
/* 0x008fc800078e0200 */
/*0500*/ @P2 IMAD R0, R16, R13, R0 ; /* 0x0000000d10002224 */
/* 0x024fe200078e0200 */
/*0510*/ IADD3 R13, RZ, -R5, RZ ; /* 0x80000005ff0d7210 */
/* 0x002fc60007ffe0ff */
/*0520*/ IMAD R14, R15, R14, R0 ; /* 0x0000000e0f0e7224 */
/* 0x008fe400078e0200 */
/*0530*/ IMAD.MOV.U32 R0, RZ, RZ, R13 ; /* 0x000000ffff007224 */
/* 0x000fe400078e000d */
/*0540*/ @P3 IMAD R14, R17, R8, R14 ; /* 0x00000008110e3224 */
/* 0x010fe400078e020e */
/*0550*/ IMAD R15, R0, R11, RZ ; /* 0x0000000b000f7224 */
/* 0x000fe400078e02ff */
/*0560*/ @!P4 IMAD R14, R19, R10, R14 ; /* 0x0000000a130ec224 */
/* 0x001fe200078e020e */
/*0570*/ @!P0 BRA 0x610 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E R0, [R2.64+0x1c] ; /* 0x00001c0402007981 */
/* 0x000ea8000c1e1900 */
/*0590*/ @P3 LDG.E R8, [R2.64+0x20] ; /* 0x0000200402083981 */
/* 0x000ee2000c1e1900 */
/*05a0*/ SHF.L.U32 R13, R12, 0x2, RZ ; /* 0x000000020c0d7819 */
/* 0x000fca00000006ff */
/*05b0*/ IMAD R10, R4.reuse, 0x4, R13 ; /* 0x00000004040a7824 */
/* 0x040fe200078e020d */
/*05c0*/ @P3 LEA R13, R4, R7, 0x1 ; /* 0x00000007040d3211 */
/* 0x000fc800078e08ff */
/*05d0*/ LDS R7, [R10] ; /* 0x000000000a077984 */
/* 0x000ea80000000800 */
/*05e0*/ @P3 LDS R13, [R13.X4+0x4] ; /* 0x000004000d0d3984 */
/* 0x000ee20000004800 */
/*05f0*/ IMAD R14, R7, R0, R14 ; /* 0x00000000070e7224 */
/* 0x004fc800078e020e */
/*0600*/ @P3 IMAD R14, R13, R8, R14 ; /* 0x000000080d0e3224 */
/* 0x008fc800078e020e */
/*0610*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0620*/ IABS R0, R14 ; /* 0x0000000e00007213 */
/* 0x000fe20000000000 */
/*0630*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0209 */
/*0640*/ LOP3.LUT R14, R14, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x000060000e0e7a12 */
/* 0x000fc600078e3cff */
/*0650*/ IMAD.HI.U32 R4, R5, R15, R4 ; /* 0x0000000f05047227 */
/* 0x000fe200078e0004 */
/*0660*/ ISETP.GE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fca0003f46270 */
/*0670*/ IMAD.HI.U32 R4, R4, R0, RZ ; /* 0x0000000004047227 */
/* 0x000fca00078e00ff */
/*0680*/ IADD3 R2, -R4, RZ, RZ ; /* 0x000000ff04027210 */
/* 0x000fca0007ffe1ff */
/*0690*/ IMAD R0, R11, R2, R0 ; /* 0x000000020b007224 */
/* 0x000fca00078e0200 */
/*06a0*/ ISETP.GT.U32.AND P1, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f24070 */
/*06b0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R11 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a0b */
/*06c0*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*06e0*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fda0003f06070 */
/*06f0*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc80007ffe0ff */
/*0700*/ @!P2 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404a210 */
/* 0x000fe40007ffe1ff */
/*0710*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff049a12 */
/* 0x000fca00078e33ff */
/*0720*/ STG.E [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x000fe2000c101904 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6MirrorPjS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff007212 */
/* 0x001fc800078e33ff */
/*0060*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fc800078e0200 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fc800078e0204 */
/*00b0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
__global__ void Mirror(unsigned int *Da, unsigned int *Dc, int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
Dc[id] = Da[bx * bn + bn - 1 - tx];
}
__global__ void Filter_func(unsigned int *Da, unsigned int *Dc, int high,int width, unsigned int *Filter, int filtersum)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
__shared__ unsigned int share[512 * 3];
if(bx == 0 || bx == bn - 1){
if(bx == 0){
share[tx + bn] = Da[id];
share[tx + 2* bn] = Da[id + bn];
}else{
share[tx + bn] = Da[id];
share[tx] = Da[id - bn];
}
}else{
share[tx] = Da[id - bn];
share[tx + bn] = Da[id];
share[tx + 2 * bn] = Da[id + bn];
}
__syncthreads();
int sum = 0;
if(bx != 0 && tx % 512 != 0) // ¥ª¤W¨S¶W¥X½d³ò
sum += Filter[0] * share[tx - 1];
if(bx != 0) // ¤W±¨S¶W¥X½d³ò
sum += Filter[1] * share[tx];
if(bx != 0 && (tx + 1) % 512 != 0) // ¥k¤W¨S¶W¥X½d³ò
sum += Filter[2] * share[tx + 1];
if(tx % 512 != 0) // ¥ªÃä¨S¶W¥X½d³ò
sum += Filter[3] * share[tx + bn - 1];
sum += Filter[4] * share[tx + bn];
if((tx + 1) % 512 != 0) // ¥kÃä¨S¶W¥X½d³ò
sum += Filter[5] * share[tx + bn + 1];
if(bx != bn - 1 && tx % 512 != 0) // ¥ª¤U¨S¶W¥X½d³ò
sum += Filter[6] * share[tx + 2 * bn - 1];
if(bx != bn - 1) // ¤U±¨S¶W¥X½d³ò
sum += Filter[7] * share[tx + 2 * bn];
if(bx != bn - 1 && (tx + 1) % 512 != 0) // ¥k¤U¨S¶W¥X½d³ò
sum += Filter[8] * share[tx + 2 * bn + 1];
Dc[id] = sum / filtersum;
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset, nthread, nblock;
unsigned char *head;
unsigned char *img;
unsigned int *da;
unsigned int filter[9] = {1,2,1,2,4,2,1,2,1};
char c, sel;
printf("What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n");
scanf("%c", &sel);
getchar();
if(sel == 'A' || sel == 'a'){
printf("Do you want to input filter values by yourself? (Y/N)\n");
scanf("%c", &c);
getchar();
if(c == 'Y' || c == 'y'){
printf("Please input 9 filter values:\n");
for(int i = 0; i < 9; ++i)
scanf("%d", &filter[i]);
getchar();
}
}
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb"); // rb¬Oread binary
fseek(fp, 10, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä10Óbyte¡A¦]¬°offset©ñ¦bheaderªº²Ä10~13Óbyte
fread(&offset, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìoffset
fseek(fp, 18, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä18Óbyte¡A¦]¬°width©ñ¦bheaderªº²Ä18~21Óbyte
fread(&width, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìwidth
fseek(fp, 22, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä22Óbyte¡A¦]¬°high©ñ¦bheaderªº²Ä22~25Óbyte
fread(&high, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìhigh
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high)); // °t¸m¤@Ówidth*highªºbyte¼Æ¤j¤pµ¹img(unsigned char¬O1byte)
da = (unsigned int*)malloc(sizeof(unsigned int)*(width*high));
fseek(fp, offset, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâoffsetÓbyteªº¦ì¸m¡A¦]¬°offset¦sªº¦ì¸m¬O¶}©l¦spixelªº¦ì¸m
fread(img, sizeof(char), (width*high), fp); // ±qfpŪwidth*highÓcharªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìimg
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset)); // °t¸m¤@Óoffsetªºbyte¼Æ¤j¤pµ¹img
fseek(fp, 0, SEEK_SET); // §â´å¼Ð²¾¨ìfpªº¤@¶}©l¡A±qÀYªº¦ì¸m¨ìoffsetªº¦ì¸m¬O©ñ¼ÐÀYÀÉ
fread(head, sizeof(unsigned char), offset, fp); // ±qfpŪoffsetÓunsigned charªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìhead
if(width > 1024){ // ¼°_¨Ónµ¥©ówidth*high¡Athreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = high * width / 1024;
}else{
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1);
dim3 grid(nblock, 1, 1);
for(int i = 0; i < high * width; ++i)
da[i] = img[i];
int filtersum = 0;
for(int i = 0; i < 9; ++i)
filtersum += filter[i];
unsigned int *Da;
cudaMalloc((void**)&Da, (sizeof(unsigned int)*(width*high)));
unsigned int *Dc;
cudaMalloc((void**)&Dc, (sizeof(unsigned int)*(width*high)));
unsigned int *Filter;
cudaMalloc((void**)&Filter, (sizeof(unsigned int)*9));
cudaMemcpy(Da, da, (sizeof(unsigned int)*(width*high)), cudaMemcpyHostToDevice);
if(sel == 'A' || sel == 'a'){
Filter_func <<< nblock, nthread >>> (Da,Dc,high,width,Filter,filtersum);
cudaMemcpy(Filter, filter, (sizeof(unsigned int)*9), cudaMemcpyHostToDevice);
}else if(sel == 'B' || sel == 'b'){
Mirror <<< nblock, nthread >>> (Da,Dc,high,width);
}
cudaThreadSynchronize();
cudaMemcpy(da, Dc, (sizeof(unsigned int)*(width*high)), cudaMemcpyDeviceToHost);
for(int i = 0; i < high * width; ++i)
img[i] = da[i];
fp = fopen("lena3.bmp","wb+");
fwrite(head, sizeof(unsigned char), offset, fp);
fwrite(img, sizeof(unsigned int), (width*high), fp);
fclose(fp);
} | .file "tmpxft_00112e9c_00000000-6_project.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6MirrorPjS_iiPjS_ii
.type _Z29__device_stub__Z6MirrorPjS_iiPjS_ii, @function
_Z29__device_stub__Z6MirrorPjS_iiPjS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MirrorPjS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6MirrorPjS_iiPjS_ii, .-_Z29__device_stub__Z6MirrorPjS_iiPjS_ii
.globl _Z6MirrorPjS_ii
.type _Z6MirrorPjS_ii, @function
_Z6MirrorPjS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6MirrorPjS_iiPjS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MirrorPjS_ii, .-_Z6MirrorPjS_ii
.globl _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
.type _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i, @function
_Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Filter_funcPjS_iiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i, .-_Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
.globl _Z11Filter_funcPjS_iiS_i
.type _Z11Filter_funcPjS_iiS_i, @function
_Z11Filter_funcPjS_iiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11Filter_funcPjS_iiS_i, .-_Z11Filter_funcPjS_iiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%c"
.section .rodata.str1.8
.align 8
.LC2:
.string "Do you want to input filter values by yourself? (Y/N)\n"
.align 8
.LC3:
.string "Please input 9 filter values:\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.LC5:
.string "rb"
.LC6:
.string "lena.bmp"
.LC7:
.string "wb+"
.LC8:
.string "lena3.bmp"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1, 64(%rsp)
movl $2, 68(%rsp)
movl $1, 72(%rsp)
movl $2, 76(%rsp)
movl $4, 80(%rsp)
movl $2, 84(%rsp)
movl $1, 88(%rsp)
movl $2, 92(%rsp)
movl $1, 96(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 3(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq stdin(%rip), %rdi
call getc@PLT
movzbl 3(%rsp), %eax
andl $-33, %eax
cmpb $65, %al
je .L39
.L20:
movl $0, 4(%rsp)
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %edx
movl $10, %esi
movq %rax, %rdi
call fseek@PLT
leaq 12(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $18, %esi
movq %r13, %rdi
call fseek@PLT
leaq 8(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $22, %esi
movq %r13, %rdi
call fseek@PLT
leaq 4(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 8(%rsp), %r12d
imull 4(%rsp), %r12d
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 0(,%r12,4), %rdi
call malloc@PLT
movq %rax, %rbp
movl 12(%rsp), %esi
movl $0, %edx
movq %r13, %rdi
call fseek@PLT
movl 8(%rsp), %ecx
imull 4(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %r12, %rsi
movq %rbx, %rdi
call __fread_chk@PLT
movl 12(%rsp), %r14d
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
movl 12(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call __fread_chk@PLT
movl 8(%rsp), %esi
cmpl $1024, %esi
jbe .L22
movl %esi, %r13d
imull 4(%rsp), %r13d
shrl $10, %r13d
movl $1024, %r14d
.L23:
imull 4(%rsp), %esi
testl %esi, %esi
je .L24
movl %esi, %ecx
movl $0, %eax
.L25:
movzbl (%rbx,%rax), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %rcx
jne .L25
.L24:
leaq 64(%rsp), %rax
leaq 100(%rsp), %rcx
movl $0, %edx
.L26:
addl (%rax), %edx
movl %edx, %r15d
addq $4, %rax
cmpq %rax, %rcx
jne .L26
movl %esi, %esi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %esi
imull 4(%rsp), %esi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl 8(%rsp), %edx
imull 4(%rsp), %edx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movzbl 3(%rsp), %eax
andl $-33, %eax
cmpb $65, %al
je .L40
cmpb $66, %al
jne .L29
movl %r14d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r13d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl 8(%rsp), %ecx
movl 4(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6MirrorPjS_iiPjS_ii
jmp .L29
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq stdin(%rip), %rdi
call getc@PLT
movzbl 2(%rsp), %eax
andl $-33, %eax
cmpb $89, %al
jne .L20
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
leaq 100(%rsp), %r12
leaq .LC4(%rip), %rbp
.L21:
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L21
movq stdin(%rip), %rdi
call getc@PLT
jmp .L20
.L22:
movl 4(%rsp), %r13d
movl %esi, %r14d
jmp .L23
.L40:
movl %r14d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r13d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L28:
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $36, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
.L29:
call cudaThreadSynchronize@PLT
movl 8(%rsp), %edx
imull 4(%rsp), %edx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %ecx
imull 8(%rsp), %ecx
testl %ecx, %ecx
je .L31
movl %ecx, %ecx
movl $0, %eax
.L32:
movl 0(%rbp,%rax,4), %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L32
.L31:
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl 12(%rsp), %edx
movq %rax, %rcx
movl $1, %esi
movq %r12, %rdi
call fwrite@PLT
movl 8(%rsp), %edx
imull 4(%rsp), %edx
movq %rbp, %rcx
movl $4, %esi
movq %rbx, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %r15d, %r9d
movq 32(%rsp), %r8
movl 8(%rsp), %ecx
movl 4(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
jmp .L28
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11Filter_funcPjS_iiS_i"
.LC10:
.string "_Z6MirrorPjS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Filter_funcPjS_iiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MirrorPjS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
__global__ void Mirror(unsigned int *Da, unsigned int *Dc, int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
Dc[id] = Da[bx * bn + bn - 1 - tx];
}
__global__ void Filter_func(unsigned int *Da, unsigned int *Dc, int high,int width, unsigned int *Filter, int filtersum)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
__shared__ unsigned int share[512 * 3];
if(bx == 0 || bx == bn - 1){
if(bx == 0){
share[tx + bn] = Da[id];
share[tx + 2* bn] = Da[id + bn];
}else{
share[tx + bn] = Da[id];
share[tx] = Da[id - bn];
}
}else{
share[tx] = Da[id - bn];
share[tx + bn] = Da[id];
share[tx + 2 * bn] = Da[id + bn];
}
__syncthreads();
int sum = 0;
if(bx != 0 && tx % 512 != 0) // ¥ª¤W¨S¶W¥X½d³ò
sum += Filter[0] * share[tx - 1];
if(bx != 0) // ¤W±¨S¶W¥X½d³ò
sum += Filter[1] * share[tx];
if(bx != 0 && (tx + 1) % 512 != 0) // ¥k¤W¨S¶W¥X½d³ò
sum += Filter[2] * share[tx + 1];
if(tx % 512 != 0) // ¥ªÃä¨S¶W¥X½d³ò
sum += Filter[3] * share[tx + bn - 1];
sum += Filter[4] * share[tx + bn];
if((tx + 1) % 512 != 0) // ¥kÃä¨S¶W¥X½d³ò
sum += Filter[5] * share[tx + bn + 1];
if(bx != bn - 1 && tx % 512 != 0) // ¥ª¤U¨S¶W¥X½d³ò
sum += Filter[6] * share[tx + 2 * bn - 1];
if(bx != bn - 1) // ¤U±¨S¶W¥X½d³ò
sum += Filter[7] * share[tx + 2 * bn];
if(bx != bn - 1 && (tx + 1) % 512 != 0) // ¥k¤U¨S¶W¥X½d³ò
sum += Filter[8] * share[tx + 2 * bn + 1];
Dc[id] = sum / filtersum;
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset, nthread, nblock;
unsigned char *head;
unsigned char *img;
unsigned int *da;
unsigned int filter[9] = {1,2,1,2,4,2,1,2,1};
char c, sel;
printf("What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n");
scanf("%c", &sel);
getchar();
if(sel == 'A' || sel == 'a'){
printf("Do you want to input filter values by yourself? (Y/N)\n");
scanf("%c", &c);
getchar();
if(c == 'Y' || c == 'y'){
printf("Please input 9 filter values:\n");
for(int i = 0; i < 9; ++i)
scanf("%d", &filter[i]);
getchar();
}
}
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb"); // rb¬Oread binary
fseek(fp, 10, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä10Óbyte¡A¦]¬°offset©ñ¦bheaderªº²Ä10~13Óbyte
fread(&offset, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìoffset
fseek(fp, 18, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä18Óbyte¡A¦]¬°width©ñ¦bheaderªº²Ä18~21Óbyte
fread(&width, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìwidth
fseek(fp, 22, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä22Óbyte¡A¦]¬°high©ñ¦bheaderªº²Ä22~25Óbyte
fread(&high, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìhigh
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high)); // °t¸m¤@Ówidth*highªºbyte¼Æ¤j¤pµ¹img(unsigned char¬O1byte)
da = (unsigned int*)malloc(sizeof(unsigned int)*(width*high));
fseek(fp, offset, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâoffsetÓbyteªº¦ì¸m¡A¦]¬°offset¦sªº¦ì¸m¬O¶}©l¦spixelªº¦ì¸m
fread(img, sizeof(char), (width*high), fp); // ±qfpŪwidth*highÓcharªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìimg
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset)); // °t¸m¤@Óoffsetªºbyte¼Æ¤j¤pµ¹img
fseek(fp, 0, SEEK_SET); // §â´å¼Ð²¾¨ìfpªº¤@¶}©l¡A±qÀYªº¦ì¸m¨ìoffsetªº¦ì¸m¬O©ñ¼ÐÀYÀÉ
fread(head, sizeof(unsigned char), offset, fp); // ±qfpŪoffsetÓunsigned charªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìhead
if(width > 1024){ // ¼°_¨Ónµ¥©ówidth*high¡Athreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = high * width / 1024;
}else{
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1);
dim3 grid(nblock, 1, 1);
for(int i = 0; i < high * width; ++i)
da[i] = img[i];
int filtersum = 0;
for(int i = 0; i < 9; ++i)
filtersum += filter[i];
unsigned int *Da;
cudaMalloc((void**)&Da, (sizeof(unsigned int)*(width*high)));
unsigned int *Dc;
cudaMalloc((void**)&Dc, (sizeof(unsigned int)*(width*high)));
unsigned int *Filter;
cudaMalloc((void**)&Filter, (sizeof(unsigned int)*9));
cudaMemcpy(Da, da, (sizeof(unsigned int)*(width*high)), cudaMemcpyHostToDevice);
if(sel == 'A' || sel == 'a'){
Filter_func <<< nblock, nthread >>> (Da,Dc,high,width,Filter,filtersum);
cudaMemcpy(Filter, filter, (sizeof(unsigned int)*9), cudaMemcpyHostToDevice);
}else if(sel == 'B' || sel == 'b'){
Mirror <<< nblock, nthread >>> (Da,Dc,high,width);
}
cudaThreadSynchronize();
cudaMemcpy(da, Dc, (sizeof(unsigned int)*(width*high)), cudaMemcpyDeviceToHost);
for(int i = 0; i < high * width; ++i)
img[i] = da[i];
fp = fopen("lena3.bmp","wb+");
fwrite(head, sizeof(unsigned char), offset, fp);
fwrite(img, sizeof(unsigned int), (width*high), fp);
fclose(fp);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
__global__ void Mirror(unsigned int *Da, unsigned int *Dc, int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
Dc[id] = Da[bx * bn + bn - 1 - tx];
}
__global__ void Filter_func(unsigned int *Da, unsigned int *Dc, int high,int width, unsigned int *Filter, int filtersum)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
__shared__ unsigned int share[512 * 3];
if(bx == 0 || bx == bn - 1){
if(bx == 0){
share[tx + bn] = Da[id];
share[tx + 2* bn] = Da[id + bn];
}else{
share[tx + bn] = Da[id];
share[tx] = Da[id - bn];
}
}else{
share[tx] = Da[id - bn];
share[tx + bn] = Da[id];
share[tx + 2 * bn] = Da[id + bn];
}
__syncthreads();
int sum = 0;
if(bx != 0 && tx % 512 != 0) // ¥ª¤W¨S¶W¥X½d³ò
sum += Filter[0] * share[tx - 1];
if(bx != 0) // ¤W±¨S¶W¥X½d³ò
sum += Filter[1] * share[tx];
if(bx != 0 && (tx + 1) % 512 != 0) // ¥k¤W¨S¶W¥X½d³ò
sum += Filter[2] * share[tx + 1];
if(tx % 512 != 0) // ¥ªÃä¨S¶W¥X½d³ò
sum += Filter[3] * share[tx + bn - 1];
sum += Filter[4] * share[tx + bn];
if((tx + 1) % 512 != 0) // ¥kÃä¨S¶W¥X½d³ò
sum += Filter[5] * share[tx + bn + 1];
if(bx != bn - 1 && tx % 512 != 0) // ¥ª¤U¨S¶W¥X½d³ò
sum += Filter[6] * share[tx + 2 * bn - 1];
if(bx != bn - 1) // ¤U±¨S¶W¥X½d³ò
sum += Filter[7] * share[tx + 2 * bn];
if(bx != bn - 1 && (tx + 1) % 512 != 0) // ¥k¤U¨S¶W¥X½d³ò
sum += Filter[8] * share[tx + 2 * bn + 1];
Dc[id] = sum / filtersum;
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset, nthread, nblock;
unsigned char *head;
unsigned char *img;
unsigned int *da;
unsigned int filter[9] = {1,2,1,2,4,2,1,2,1};
char c, sel;
printf("What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n");
scanf("%c", &sel);
getchar();
if(sel == 'A' || sel == 'a'){
printf("Do you want to input filter values by yourself? (Y/N)\n");
scanf("%c", &c);
getchar();
if(c == 'Y' || c == 'y'){
printf("Please input 9 filter values:\n");
for(int i = 0; i < 9; ++i)
scanf("%d", &filter[i]);
getchar();
}
}
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb"); // rb¬Oread binary
fseek(fp, 10, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä10Óbyte¡A¦]¬°offset©ñ¦bheaderªº²Ä10~13Óbyte
fread(&offset, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìoffset
fseek(fp, 18, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä18Óbyte¡A¦]¬°width©ñ¦bheaderªº²Ä18~21Óbyte
fread(&width, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìwidth
fseek(fp, 22, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä22Óbyte¡A¦]¬°high©ñ¦bheaderªº²Ä22~25Óbyte
fread(&high, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìhigh
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high)); // °t¸m¤@Ówidth*highªºbyte¼Æ¤j¤pµ¹img(unsigned char¬O1byte)
da = (unsigned int*)malloc(sizeof(unsigned int)*(width*high));
fseek(fp, offset, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâoffsetÓbyteªº¦ì¸m¡A¦]¬°offset¦sªº¦ì¸m¬O¶}©l¦spixelªº¦ì¸m
fread(img, sizeof(char), (width*high), fp); // ±qfpŪwidth*highÓcharªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìimg
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset)); // °t¸m¤@Óoffsetªºbyte¼Æ¤j¤pµ¹img
fseek(fp, 0, SEEK_SET); // §â´å¼Ð²¾¨ìfpªº¤@¶}©l¡A±qÀYªº¦ì¸m¨ìoffsetªº¦ì¸m¬O©ñ¼ÐÀYÀÉ
fread(head, sizeof(unsigned char), offset, fp); // ±qfpŪoffsetÓunsigned charªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìhead
if(width > 1024){ // ¼°_¨Ónµ¥©ówidth*high¡Athreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = high * width / 1024;
}else{
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1);
dim3 grid(nblock, 1, 1);
for(int i = 0; i < high * width; ++i)
da[i] = img[i];
int filtersum = 0;
for(int i = 0; i < 9; ++i)
filtersum += filter[i];
unsigned int *Da;
hipMalloc((void**)&Da, (sizeof(unsigned int)*(width*high)));
unsigned int *Dc;
hipMalloc((void**)&Dc, (sizeof(unsigned int)*(width*high)));
unsigned int *Filter;
hipMalloc((void**)&Filter, (sizeof(unsigned int)*9));
hipMemcpy(Da, da, (sizeof(unsigned int)*(width*high)), hipMemcpyHostToDevice);
if(sel == 'A' || sel == 'a'){
Filter_func <<< nblock, nthread >>> (Da,Dc,high,width,Filter,filtersum);
hipMemcpy(Filter, filter, (sizeof(unsigned int)*9), hipMemcpyHostToDevice);
}else if(sel == 'B' || sel == 'b'){
Mirror <<< nblock, nthread >>> (Da,Dc,high,width);
}
hipDeviceSynchronize();
hipMemcpy(da, Dc, (sizeof(unsigned int)*(width*high)), hipMemcpyDeviceToHost);
for(int i = 0; i < high * width; ++i)
img[i] = da[i];
fp = fopen("lena3.bmp","wb+");
fwrite(head, sizeof(unsigned char), offset, fp);
fwrite(img, sizeof(unsigned int), (width*high), fp);
fclose(fp);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
__global__ void Mirror(unsigned int *Da, unsigned int *Dc, int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
Dc[id] = Da[bx * bn + bn - 1 - tx];
}
__global__ void Filter_func(unsigned int *Da, unsigned int *Dc, int high,int width, unsigned int *Filter, int filtersum)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
__shared__ unsigned int share[512 * 3];
if(bx == 0 || bx == bn - 1){
if(bx == 0){
share[tx + bn] = Da[id];
share[tx + 2* bn] = Da[id + bn];
}else{
share[tx + bn] = Da[id];
share[tx] = Da[id - bn];
}
}else{
share[tx] = Da[id - bn];
share[tx + bn] = Da[id];
share[tx + 2 * bn] = Da[id + bn];
}
__syncthreads();
int sum = 0;
if(bx != 0 && tx % 512 != 0) // ¥ª¤W¨S¶W¥X½d³ò
sum += Filter[0] * share[tx - 1];
if(bx != 0) // ¤W±¨S¶W¥X½d³ò
sum += Filter[1] * share[tx];
if(bx != 0 && (tx + 1) % 512 != 0) // ¥k¤W¨S¶W¥X½d³ò
sum += Filter[2] * share[tx + 1];
if(tx % 512 != 0) // ¥ªÃä¨S¶W¥X½d³ò
sum += Filter[3] * share[tx + bn - 1];
sum += Filter[4] * share[tx + bn];
if((tx + 1) % 512 != 0) // ¥kÃä¨S¶W¥X½d³ò
sum += Filter[5] * share[tx + bn + 1];
if(bx != bn - 1 && tx % 512 != 0) // ¥ª¤U¨S¶W¥X½d³ò
sum += Filter[6] * share[tx + 2 * bn - 1];
if(bx != bn - 1) // ¤U±¨S¶W¥X½d³ò
sum += Filter[7] * share[tx + 2 * bn];
if(bx != bn - 1 && (tx + 1) % 512 != 0) // ¥k¤U¨S¶W¥X½d³ò
sum += Filter[8] * share[tx + 2 * bn + 1];
Dc[id] = sum / filtersum;
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset, nthread, nblock;
unsigned char *head;
unsigned char *img;
unsigned int *da;
unsigned int filter[9] = {1,2,1,2,4,2,1,2,1};
char c, sel;
printf("What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n");
scanf("%c", &sel);
getchar();
if(sel == 'A' || sel == 'a'){
printf("Do you want to input filter values by yourself? (Y/N)\n");
scanf("%c", &c);
getchar();
if(c == 'Y' || c == 'y'){
printf("Please input 9 filter values:\n");
for(int i = 0; i < 9; ++i)
scanf("%d", &filter[i]);
getchar();
}
}
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb"); // rb¬Oread binary
fseek(fp, 10, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä10Óbyte¡A¦]¬°offset©ñ¦bheaderªº²Ä10~13Óbyte
fread(&offset, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìoffset
fseek(fp, 18, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä18Óbyte¡A¦]¬°width©ñ¦bheaderªº²Ä18~21Óbyte
fread(&width, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìwidth
fseek(fp, 22, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä22Óbyte¡A¦]¬°high©ñ¦bheaderªº²Ä22~25Óbyte
fread(&high, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìhigh
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high)); // °t¸m¤@Ówidth*highªºbyte¼Æ¤j¤pµ¹img(unsigned char¬O1byte)
da = (unsigned int*)malloc(sizeof(unsigned int)*(width*high));
fseek(fp, offset, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâoffsetÓbyteªº¦ì¸m¡A¦]¬°offset¦sªº¦ì¸m¬O¶}©l¦spixelªº¦ì¸m
fread(img, sizeof(char), (width*high), fp); // ±qfpŪwidth*highÓcharªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìimg
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset)); // °t¸m¤@Óoffsetªºbyte¼Æ¤j¤pµ¹img
fseek(fp, 0, SEEK_SET); // §â´å¼Ð²¾¨ìfpªº¤@¶}©l¡A±qÀYªº¦ì¸m¨ìoffsetªº¦ì¸m¬O©ñ¼ÐÀYÀÉ
fread(head, sizeof(unsigned char), offset, fp); // ±qfpŪoffsetÓunsigned charªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìhead
if(width > 1024){ // ¼°_¨Ónµ¥©ówidth*high¡Athreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = high * width / 1024;
}else{
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1);
dim3 grid(nblock, 1, 1);
for(int i = 0; i < high * width; ++i)
da[i] = img[i];
int filtersum = 0;
for(int i = 0; i < 9; ++i)
filtersum += filter[i];
unsigned int *Da;
hipMalloc((void**)&Da, (sizeof(unsigned int)*(width*high)));
unsigned int *Dc;
hipMalloc((void**)&Dc, (sizeof(unsigned int)*(width*high)));
unsigned int *Filter;
hipMalloc((void**)&Filter, (sizeof(unsigned int)*9));
hipMemcpy(Da, da, (sizeof(unsigned int)*(width*high)), hipMemcpyHostToDevice);
if(sel == 'A' || sel == 'a'){
Filter_func <<< nblock, nthread >>> (Da,Dc,high,width,Filter,filtersum);
hipMemcpy(Filter, filter, (sizeof(unsigned int)*9), hipMemcpyHostToDevice);
}else if(sel == 'B' || sel == 'b'){
Mirror <<< nblock, nthread >>> (Da,Dc,high,width);
}
hipDeviceSynchronize();
hipMemcpy(da, Dc, (sizeof(unsigned int)*(width*high)), hipMemcpyDeviceToHost);
for(int i = 0; i < high * width; ++i)
img[i] = da[i];
fp = fopen("lena3.bmp","wb+");
fwrite(head, sizeof(unsigned char), offset, fp);
fwrite(img, sizeof(unsigned int), (width*high), fp);
fclose(fp);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MirrorPjS_ii
.globl _Z6MirrorPjS_ii
.p2align 8
.type _Z6MirrorPjS_ii,@function
_Z6MirrorPjS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
v_not_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, s15, s4, v1
v_add_nc_u32_e32 v0, s15, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MirrorPjS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MirrorPjS_ii, .Lfunc_end0-_Z6MirrorPjS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11Filter_funcPjS_iiS_i
.globl _Z11Filter_funcPjS_iiS_i
.p2align 8
.type _Z11Filter_funcPjS_iiS_i,@function
_Z11Filter_funcPjS_iiS_i:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
s_cmp_eq_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_cselect_b32 s10, -1, 0
s_cmp_lg_u32 s15, 0
s_cselect_b32 s9, -1, 0
s_add_i32 s4, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s15, s4
v_ashrrev_i32_e32 v5, 31, v1
s_cselect_b32 s7, -1, 0
s_cmp_lg_u32 s15, s4
s_cselect_b32 s8, -1, 0
s_or_b32 s4, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_mov_b32 s4, -1
s_cbranch_vccz .LBB1_2
v_subrev_nc_u32_e32 v3, s6, v1
v_mov_b32_e32 v2, v5
v_lshlrev_b32_e32 v8, 2, v0
v_add_lshl_u32 v9, v0, s6, 2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v7, v[6:7], off
v_add_nc_u32_e32 v2, s6, v1
v_lshl_add_u32 v6, s6, 1, v0
s_waitcnt vmcnt(1)
ds_store_b32 v8, v4
s_waitcnt vmcnt(0)
ds_store_b32 v9, v7
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_cbranch_execz .LBB1_3
s_branch .LBB1_7
.LBB1_2:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_7
.LBB1_3:
v_add_lshl_u32 v4, v0, s6, 2
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB1_5
v_mov_b32_e32 v2, v5
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v7, v[2:3], off
v_subrev_nc_u32_e32 v2, s6, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v7
s_cbranch_execz .LBB1_6
s_branch .LBB1_7
.LBB1_5:
.LBB1_6:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v8, v[6:7], off
v_dual_mov_b32 v7, v2 :: v_dual_add_nc_u32 v6, s6, v1
v_lshlrev_b64 v[2:3], 2, v[6:7]
v_lshl_add_u32 v6, s6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v8
.LBB1_7:
global_load_b32 v3, v[2:3], off
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v4, 0x1ff, v0
v_lshlrev_b32_e32 v6, 2, v6
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 0, v4
v_cmp_ne_u32_e64 s3, 0, v4
s_or_b32 s10, s10, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s11, s10, -1
s_waitcnt vmcnt(0)
ds_store_b32 v6, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s10, s11
s_cbranch_execz .LBB1_9
v_lshl_add_u32 v2, v0, 2, -4
s_load_b32 s11, s[4:5], 0x0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v2, s11
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s10
v_cndmask_b32_e64 v3, 0, 1, s9
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_11
v_lshlrev_b32_e32 v4, 2, v0
s_load_b32 s9, s[4:5], 0x4
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v4, s9, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v6
.LBB1_11:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 1, v3
s_cbranch_vccnz .LBB1_15
v_add_nc_u32_e32 v3, 1, v0
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, 0x1ff, v3
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB1_14
v_lshlrev_b32_e32 v3, 2, v3
s_load_b32 s10, s[4:5], 0x8
ds_load_b32 v6, v3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v6, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s9
.LBB1_15:
v_add_nc_u32_e32 v3, s6, v0
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB1_17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v3, 2, -4
s_load_b32 s3, s[4:5], 0xc
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v4, s3, v[2:3]
v_mov_b32_e32 v2, v6
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 2, v3
s_load_b32 s3, s[4:5], 0x10
v_add_nc_u32_e32 v3, 1, v0
s_mov_b32 s9, exec_lo
ds_load_b32 v7, v6
v_and_b32_e32 v8, 0x1ff, v3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v7, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cmp_eq_u32_e64 s3, 0, v8
v_cmpx_ne_u32_e32 0, v8
s_cbranch_execz .LBB1_19
s_load_b32 s10, s[4:5], 0x14
ds_load_b32 v2, v6 offset:4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v2, s10, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v6
.LBB1_19:
s_or_b32 exec_lo, exec_lo, s9
s_or_b32 s2, s2, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s9, s2, -1
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB1_21
v_lshl_add_u32 v2, s6, 1, v0
s_load_b32 s9, s[4:5], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, -4
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v2, s9, v[3:4]
v_mov_b32_e32 v3, v6
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB1_23
s_lshl_b32 s2, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_lshl_u32 v2, s2, v0, 2
s_load_b32 s2, s[4:5], 0x1c
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v2, s2, v[3:4]
v_mov_b32_e32 v3, v6
.LBB1_23:
s_or_b32 s2, s3, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_25
s_lshl_b32 s3, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_lshl_u32 v0, v0, s3, 2
s_load_b32 s3, s[4:5], 0x20
ds_load_b32 v0, v0 offset:4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v0, s3, v[3:4]
v_mov_b32_e32 v3, v6
.LBB1_25:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s2, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v3, v3, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_add_i32 s2, s2, s3
v_xor_b32_e32 v4, s3, v4
s_xor_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s4, 0, s2
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v3, v0
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v2
v_add_nc_u32_e32 v3, 1, v0
v_subrev_nc_u32_e32 v6, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_mov_b32_e32 v2, v5
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v0, v4
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Filter_funcPjS_iiS_i
.amdhsa_group_segment_fixed_size 6144
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11Filter_funcPjS_iiS_i, .Lfunc_end1-_Z11Filter_funcPjS_iiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MirrorPjS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MirrorPjS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 6144
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Filter_funcPjS_iiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11Filter_funcPjS_iiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
__global__ void Mirror(unsigned int *Da, unsigned int *Dc, int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
Dc[id] = Da[bx * bn + bn - 1 - tx];
}
__global__ void Filter_func(unsigned int *Da, unsigned int *Dc, int high,int width, unsigned int *Filter, int filtersum)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
int id = bx*bn+tx;
__shared__ unsigned int share[512 * 3];
if(bx == 0 || bx == bn - 1){
if(bx == 0){
share[tx + bn] = Da[id];
share[tx + 2* bn] = Da[id + bn];
}else{
share[tx + bn] = Da[id];
share[tx] = Da[id - bn];
}
}else{
share[tx] = Da[id - bn];
share[tx + bn] = Da[id];
share[tx + 2 * bn] = Da[id + bn];
}
__syncthreads();
int sum = 0;
if(bx != 0 && tx % 512 != 0) // ¥ª¤W¨S¶W¥X½d³ò
sum += Filter[0] * share[tx - 1];
if(bx != 0) // ¤W±¨S¶W¥X½d³ò
sum += Filter[1] * share[tx];
if(bx != 0 && (tx + 1) % 512 != 0) // ¥k¤W¨S¶W¥X½d³ò
sum += Filter[2] * share[tx + 1];
if(tx % 512 != 0) // ¥ªÃä¨S¶W¥X½d³ò
sum += Filter[3] * share[tx + bn - 1];
sum += Filter[4] * share[tx + bn];
if((tx + 1) % 512 != 0) // ¥kÃä¨S¶W¥X½d³ò
sum += Filter[5] * share[tx + bn + 1];
if(bx != bn - 1 && tx % 512 != 0) // ¥ª¤U¨S¶W¥X½d³ò
sum += Filter[6] * share[tx + 2 * bn - 1];
if(bx != bn - 1) // ¤U±¨S¶W¥X½d³ò
sum += Filter[7] * share[tx + 2 * bn];
if(bx != bn - 1 && (tx + 1) % 512 != 0) // ¥k¤U¨S¶W¥X½d³ò
sum += Filter[8] * share[tx + 2 * bn + 1];
Dc[id] = sum / filtersum;
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset, nthread, nblock;
unsigned char *head;
unsigned char *img;
unsigned int *da;
unsigned int filter[9] = {1,2,1,2,4,2,1,2,1};
char c, sel;
printf("What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n");
scanf("%c", &sel);
getchar();
if(sel == 'A' || sel == 'a'){
printf("Do you want to input filter values by yourself? (Y/N)\n");
scanf("%c", &c);
getchar();
if(c == 'Y' || c == 'y'){
printf("Please input 9 filter values:\n");
for(int i = 0; i < 9; ++i)
scanf("%d", &filter[i]);
getchar();
}
}
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb"); // rb¬Oread binary
fseek(fp, 10, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä10Óbyte¡A¦]¬°offset©ñ¦bheaderªº²Ä10~13Óbyte
fread(&offset, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìoffset
fseek(fp, 18, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä18Óbyte¡A¦]¬°width©ñ¦bheaderªº²Ä18~21Óbyte
fread(&width, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìwidth
fseek(fp, 22, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâªº²Ä22Óbyte¡A¦]¬°high©ñ¦bheaderªº²Ä22~25Óbyte
fread(&high, sizeof(unsigned int), 1, fp); // ±qfpŪ1Óunsigned intªº¤j¤p¦s¨ìhigh
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high)); // °t¸m¤@Ówidth*highªºbyte¼Æ¤j¤pµ¹img(unsigned char¬O1byte)
da = (unsigned int*)malloc(sizeof(unsigned int)*(width*high));
fseek(fp, offset, SEEK_SET); // §â´å¼Ð²¾¨ìfp±qÀYºâoffsetÓbyteªº¦ì¸m¡A¦]¬°offset¦sªº¦ì¸m¬O¶}©l¦spixelªº¦ì¸m
fread(img, sizeof(char), (width*high), fp); // ±qfpŪwidth*highÓcharªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìimg
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset)); // °t¸m¤@Óoffsetªºbyte¼Æ¤j¤pµ¹img
fseek(fp, 0, SEEK_SET); // §â´å¼Ð²¾¨ìfpªº¤@¶}©l¡A±qÀYªº¦ì¸m¨ìoffsetªº¦ì¸m¬O©ñ¼ÐÀYÀÉ
fread(head, sizeof(unsigned char), offset, fp); // ±qfpŪoffsetÓunsigned charªº¤j¤p(=unsigned charªº¤j¤p)¦s¨ìhead
if(width > 1024){ // ¼°_¨Ónµ¥©ówidth*high¡Athreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = high * width / 1024;
}else{
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1);
dim3 grid(nblock, 1, 1);
for(int i = 0; i < high * width; ++i)
da[i] = img[i];
int filtersum = 0;
for(int i = 0; i < 9; ++i)
filtersum += filter[i];
unsigned int *Da;
hipMalloc((void**)&Da, (sizeof(unsigned int)*(width*high)));
unsigned int *Dc;
hipMalloc((void**)&Dc, (sizeof(unsigned int)*(width*high)));
unsigned int *Filter;
hipMalloc((void**)&Filter, (sizeof(unsigned int)*9));
hipMemcpy(Da, da, (sizeof(unsigned int)*(width*high)), hipMemcpyHostToDevice);
if(sel == 'A' || sel == 'a'){
Filter_func <<< nblock, nthread >>> (Da,Dc,high,width,Filter,filtersum);
hipMemcpy(Filter, filter, (sizeof(unsigned int)*9), hipMemcpyHostToDevice);
}else if(sel == 'B' || sel == 'b'){
Mirror <<< nblock, nthread >>> (Da,Dc,high,width);
}
hipDeviceSynchronize();
hipMemcpy(da, Dc, (sizeof(unsigned int)*(width*high)), hipMemcpyDeviceToHost);
for(int i = 0; i < high * width; ++i)
img[i] = da[i];
fp = fopen("lena3.bmp","wb+");
fwrite(head, sizeof(unsigned char), offset, fp);
fwrite(img, sizeof(unsigned int), (width*high), fp);
fclose(fp);
} | .text
.file "project.hip"
.globl _Z21__device_stub__MirrorPjS_ii # -- Begin function _Z21__device_stub__MirrorPjS_ii
.p2align 4, 0x90
.type _Z21__device_stub__MirrorPjS_ii,@function
_Z21__device_stub__MirrorPjS_ii: # @_Z21__device_stub__MirrorPjS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MirrorPjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__MirrorPjS_ii, .Lfunc_end0-_Z21__device_stub__MirrorPjS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__Filter_funcPjS_iiS_i # -- Begin function _Z26__device_stub__Filter_funcPjS_iiS_i
.p2align 4, 0x90
.type _Z26__device_stub__Filter_funcPjS_iiS_i,@function
_Z26__device_stub__Filter_funcPjS_iiS_i: # @_Z26__device_stub__Filter_funcPjS_iiS_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Filter_funcPjS_iiS_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z26__device_stub__Filter_funcPjS_iiS_i, .Lfunc_end1-_Z26__device_stub__Filter_funcPjS_iiS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 1 # 0x1
.long 2 # 0x2
.LCPI2_1:
.long 4 # 0x4
.long 2 # 0x2
.long 1 # 0x1
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,1,2]
movaps %xmm0, 224(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [4,2,1,2]
movaps %xmm0, 240(%rsp)
movl $1, 256(%rsp)
movl $.Lstr, %edi
callq puts@PLT
leaq 14(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq stdin(%rip), %rdi
callq getc
movzbl 14(%rsp), %eax
andb $-33, %al
cmpb $65, %al
jne .LBB2_5
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 15(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq stdin(%rip), %rdi
callq getc
movzbl 15(%rsp), %eax
andb $-33, %al
cmpb $89, %al
jne .LBB2_5
# %bb.2:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rsi
addq $224, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbx
cmpq $36, %rbx
jne .LBB2_3
# %bb.4:
movq stdin(%rip), %rdi
callq getc
.LBB2_5:
movl $0, 32(%rsp)
movl $0, 28(%rsp)
movl $0, 24(%rsp)
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r13
xorl %r12d, %r12d
movl $10, %esi
movq %rax, %rdi
xorl %edx, %edx
callq fseek
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl $18, %esi
movq %r13, %rdi
xorl %edx, %edx
callq fseek
leaq 28(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl $22, %esi
movq %r13, %rdi
xorl %edx, %edx
callq fseek
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 28(%rsp), %eax
movl %eax, 20(%rsp) # 4-byte Spill
movl 32(%rsp), %ecx
movl %ecx, 16(%rsp) # 4-byte Spill
movl %ecx, %ebp
imull %eax, %ebp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
leaq (,%rbp,4), %rdi
movq %rdi, 208(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r14
movl 24(%rsp), %r15d
movq %r13, %rdi
movq %r15, %rsi
movq %r15, 200(%rsp) # 8-byte Spill
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %rbx, %rdi
movq %rbp, %rdx
movq %r13, %rcx
callq fread
movq %r15, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %r15, 216(%rsp) # 8-byte Spill
movq %r15, %rdi
movq 200(%rsp), %rdx # 8-byte Reload
movq %r13, %rcx
callq fread
movl %ebp, %r13d
shrl $10, %r13d
movl 20(%rsp), %eax # 4-byte Reload
cmpl $1025, %eax # imm = 0x401
cmovbl 16(%rsp), %r13d # 4-byte Folded Reload
cmpl $1024, %eax # imm = 0x400
movl $1024, %r15d # imm = 0x400
cmovbl %eax, %r15d
testl %ebp, %ebp
je .LBB2_6
# %bb.12: # %.lr.ph.preheader
movl %ebp, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_13
.LBB2_6: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Inner Loop Header: Depth=1
addl 224(%rsp,%rax,4), %r12d
incq %rax
cmpq $9, %rax
jne .LBB2_7
# %bb.8:
leaq 48(%rsp), %rdi
movq 208(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 136(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movzbl 14(%rsp), %eax
andl $-33, %eax
cmpl $65, %eax
je .LBB2_14
# %bb.9:
cmpl $66, %eax
jne .LBB2_17
# %bb.10:
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.11:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6MirrorPjS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_17
.LBB2_14:
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 136(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 132(%rsp)
movq %rdx, 72(%rsp)
movl %r12d, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 132(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z11Filter_funcPjS_iiS_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
movq 136(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $36, %edx
movl $1, %ecx
callq hipMemcpy
.LBB2_17:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl 32(%rsp), %r12d
imull 28(%rsp), %r12d
leaq (,%r12,4), %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
je .LBB2_20
# %bb.18: # %.lr.ph98.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_19: # %.lr.ph98
# =>This Inner Loop Header: Depth=1
movzbl (%r14,%rax,4), %ecx
movb %cl, (%rbx,%rax)
incq %rax
cmpq %rax, %r12
jne .LBB2_19
.LBB2_20: # %._crit_edge
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r14
movl 24(%rsp), %edx
movl $1, %esi
movq 216(%rsp), %rdi # 8-byte Reload
movq %rax, %rcx
callq fwrite
movl $4, %esi
movq %rbx, %rdi
movq %r12, %rdx
movq %r14, %rcx
callq fwrite
movq %r14, %rdi
callq fclose
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MirrorPjS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Filter_funcPjS_iiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MirrorPjS_ii,@object # @_Z6MirrorPjS_ii
.section .rodata,"a",@progbits
.globl _Z6MirrorPjS_ii
.p2align 3, 0x0
_Z6MirrorPjS_ii:
.quad _Z21__device_stub__MirrorPjS_ii
.size _Z6MirrorPjS_ii, 8
.type _Z11Filter_funcPjS_iiS_i,@object # @_Z11Filter_funcPjS_iiS_i
.globl _Z11Filter_funcPjS_iiS_i
.p2align 3, 0x0
_Z11Filter_funcPjS_iiS_i:
.quad _Z26__device_stub__Filter_funcPjS_iiS_i
.size _Z11Filter_funcPjS_iiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%c"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "lena.bmp"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "rb"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "lena3.bmp"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "wb+"
.size .L.str.8, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MirrorPjS_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11Filter_funcPjS_iiS_i"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture"
.size .Lstr, 68
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Do you want to input filter values by yourself? (Y/N)"
.size .Lstr.1, 54
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Please input 9 filter values:"
.size .Lstr.2, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MirrorPjS_ii
.addrsig_sym _Z26__device_stub__Filter_funcPjS_iiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MirrorPjS_ii
.addrsig_sym _Z11Filter_funcPjS_iiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11Filter_funcPjS_iiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e640000002100 */
/*0050*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.NE.AND P0, PT, R0.reuse, R5, PT ; /* 0x000000050000720c */
/* 0x041fe40003f05270 */
/*0070*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f25270 */
/*0080*/ ISETP.EQ.OR P2, PT, R0.reuse, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x040fe20004742670 */
/*0090*/ IMAD R6, R0, c[0x0][0x0], R7 ; /* 0x0000000000067a24 */
/* 0x002fd800078e0207 */
/*00a0*/ @P2 BRA 0x1a0 ; /* 0x000000f000002947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R2, R6, -c[0x0][0x0], RZ ; /* 0x8000000006027a10 */
/* 0x000fd20007ffe0ff */
/*00d0*/ IMAD.WIDE R10, R6, R9, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R12, R4, 0x4, R10 ; /* 0x00000004040c7825 */
/* 0x000fe400078e020a */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1900 */
/*0130*/ IMAD.SHL.U32 R15, R7, 0x4, RZ ; /* 0x00000004070f7824 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R15, R4, 0x4, R15 ; /* 0x00000004040f7824 */
/* 0x000fca00078e020f */
/*0150*/ LEA R17, R4, R15, 0x2 ; /* 0x0000000f04117211 */
/* 0x000fe200078e10ff */
/*0160*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*0170*/ STS [R15], R10 ; /* 0x0000000a0f007388 */
/* 0x0081e80000000800 */
/*0180*/ STS [R17], R12 ; /* 0x0000000c11007388 */
/* 0x0101e20000000800 */
/*0190*/ BRA 0x280 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*01b0*/ @P1 IADD3 R10, R6, -c[0x0][0x0], RZ ; /* 0x80000000060a1a10 */
/* 0x000fc60007ffe0ff */
/*01c0*/ IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0209 */
/*01d0*/ @P1 IMAD.WIDE R10, R10, R9, c[0x0][0x160] ; /* 0x000058000a0a1625 */
/* 0x000fc800078e0209 */
/*01e0*/ @!P1 IMAD.WIDE R12, R4, 0x4, R2 ; /* 0x00000004040c9825 */
/* 0x000fe400078e0202 */
/*01f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0200*/ @P1 LDG.E R10, [R10.64] ; /* 0x000000040a0a1981 */
/* 0x000ee8000c1e1900 */
/*0210*/ @!P1 LDG.E R12, [R12.64] ; /* 0x000000040c0c9981 */
/* 0x000f22000c1e1900 */
/*0220*/ IADD3 R8, R7, c[0x0][0x0], RZ ; /* 0x0000000007087a10 */
/* 0x000fca0007ffe0ff */
/*0230*/ IMAD.SHL.U32 R15, R8, 0x4, RZ ; /* 0x00000004080f7824 */
/* 0x000fca00078e00ff */
/*0240*/ @!P1 LEA R15, R4, R15, 0x2 ; /* 0x0000000f040f9211 */
/* 0x000fe200078e10ff */
/*0250*/ STS [R8.X4], R3 ; /* 0x0000000308007388 */
/* 0x0041e80000004800 */
/*0260*/ @P1 STS [R7.X4], R10 ; /* 0x0000000a07001388 */
/* 0x0081e80000004800 */
/*0270*/ @!P1 STS [R15], R12 ; /* 0x0000000c0f009388 */
/* 0x0101e40000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x001fc40007ffe0ff */
/*02a0*/ LOP3.LUT P2, RZ, R7, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff07ff7812 */
/* 0x000fe4000784c0ff */
/*02b0*/ LOP3.LUT P3, RZ, R2, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff02ff7812 */
/* 0x000fe2000786c0ff */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.EQ.OR P4, PT, R0, R5, !P2 ; /* 0x000000050000720c */
/* 0x000fe40005782670 */
/*02e0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fce0000000f00 */
/*02f0*/ @P2 LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d2981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000168000c1e1900 */
/*0310*/ @P3 LDG.E R8, [R2.64+0x14] ; /* 0x0000140402083981 */
/* 0x000168000c1e1900 */
/*0320*/ @!P4 LDG.E R10, [R2.64+0x18] ; /* 0x00001804020ac981 */
/* 0x000162000c1e1900 */
/*0330*/ IABS R11, c[0x0][0x180] ; /* 0x00006000000b7a13 */
/* 0x000fe20000000000 */
/*0340*/ @P2 IMAD.IADD R16, R5, 0x1, R7 ; /* 0x0000000105102824 */
/* 0x000fe200078e0207 */
/*0350*/ @!P4 LEA R19, R4, R7, 0x1 ; /* 0x000000070413c211 */
/* 0x000fe200078e08ff */
/*0360*/ BSSY B0, 0x470 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0370*/ I2F.RP R18, R11 ; /* 0x0000000b00127306 */
/* 0x000e620000209400 */
/*0380*/ IADD3 R12, R7, c[0x0][0x0], RZ ; /* 0x00000000070c7a10 */
/* 0x000fc40007ffe0ff */
/*0390*/ @P2 LDS R16, [R16.X4] ; /* 0x0000000010102984 */
/* 0x000ea20000004800 */
/*03a0*/ ISETP.EQ.OR P5, PT, R0, RZ, !P2 ; /* 0x000000ff0000720c */
/* 0x000fe200057a2670 */
/*03b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*03c0*/ LDS R15, [R12.X4] ; /* 0x000000000c0f7984 */
/* 0x0000e80000004800 */
/*03d0*/ @P3 LDS R17, [R12.X4+0x4] ; /* 0x000004000c113984 */
/* 0x0001280000004800 */
/*03e0*/ @!P4 LDS R19, [R19.X4+-0x4] ; /* 0xfffffc001313c984 */
/* 0x000e220000004800 */
/*03f0*/ MUFU.RCP R18, R18 ; /* 0x0000001200127308 */
/* 0x002e640000001000 */
/*0400*/ IADD3 R5, R18, 0xffffffe, RZ ; /* 0x0ffffffe12057810 */
/* 0x002fcc0007ffe0ff */
/*0410*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e62000021f000 */
/*0420*/ @P5 BRA 0x460 ; /* 0x0000003000005947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x010f28000c1e1900 */
/*0440*/ LDS R21, [R7.X4+-0x4] ; /* 0xfffffc0007157984 */
/* 0x000f240000004800 */
/*0450*/ IMAD R0, R0, R21, RZ ; /* 0x0000001500007224 */
/* 0x010fe400078e02ff */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ @!P1 BRA 0x500 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R18, R7, 0x1, RZ ; /* 0x0000000107127810 */
/* 0x000fe20007ffe0ff */
/*0490*/ LDS R21, [R7.X4] ; /* 0x0000000007157984 */
/* 0x000f260000004800 */
/*04a0*/ LOP3.LUT P1, RZ, R18, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff12ff7812 */
/* 0x000fc4000782c0ff */
/*04b0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000f36000c1e1900 */
/*04c0*/ @P1 LDG.E R20, [R2.64+0x8] ; /* 0x0000080402141981 */
/* 0x008ee8000c1e1900 */
/*04d0*/ @P1 LDS R23, [R7.X4+0x4] ; /* 0x0000040007171984 */
/* 0x000ee20000004800 */
/*04e0*/ IMAD R0, R21, R18, R0 ; /* 0x0000001215007224 */
/* 0x010fc800078e0200 */
/*04f0*/ @P1 IMAD R0, R23, R20, R0 ; /* 0x0000001417001224 */
/* 0x008fc800078e0200 */
/*0500*/ @P2 IMAD R0, R16, R13, R0 ; /* 0x0000000d10002224 */
/* 0x024fe200078e0200 */
/*0510*/ IADD3 R13, RZ, -R5, RZ ; /* 0x80000005ff0d7210 */
/* 0x002fc60007ffe0ff */
/*0520*/ IMAD R14, R15, R14, R0 ; /* 0x0000000e0f0e7224 */
/* 0x008fe400078e0200 */
/*0530*/ IMAD.MOV.U32 R0, RZ, RZ, R13 ; /* 0x000000ffff007224 */
/* 0x000fe400078e000d */
/*0540*/ @P3 IMAD R14, R17, R8, R14 ; /* 0x00000008110e3224 */
/* 0x010fe400078e020e */
/*0550*/ IMAD R15, R0, R11, RZ ; /* 0x0000000b000f7224 */
/* 0x000fe400078e02ff */
/*0560*/ @!P4 IMAD R14, R19, R10, R14 ; /* 0x0000000a130ec224 */
/* 0x001fe200078e020e */
/*0570*/ @!P0 BRA 0x610 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E R0, [R2.64+0x1c] ; /* 0x00001c0402007981 */
/* 0x000ea8000c1e1900 */
/*0590*/ @P3 LDG.E R8, [R2.64+0x20] ; /* 0x0000200402083981 */
/* 0x000ee2000c1e1900 */
/*05a0*/ SHF.L.U32 R13, R12, 0x2, RZ ; /* 0x000000020c0d7819 */
/* 0x000fca00000006ff */
/*05b0*/ IMAD R10, R4.reuse, 0x4, R13 ; /* 0x00000004040a7824 */
/* 0x040fe200078e020d */
/*05c0*/ @P3 LEA R13, R4, R7, 0x1 ; /* 0x00000007040d3211 */
/* 0x000fc800078e08ff */
/*05d0*/ LDS R7, [R10] ; /* 0x000000000a077984 */
/* 0x000ea80000000800 */
/*05e0*/ @P3 LDS R13, [R13.X4+0x4] ; /* 0x000004000d0d3984 */
/* 0x000ee20000004800 */
/*05f0*/ IMAD R14, R7, R0, R14 ; /* 0x00000000070e7224 */
/* 0x004fc800078e020e */
/*0600*/ @P3 IMAD R14, R13, R8, R14 ; /* 0x000000080d0e3224 */
/* 0x008fc800078e020e */
/*0610*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0620*/ IABS R0, R14 ; /* 0x0000000e00007213 */
/* 0x000fe20000000000 */
/*0630*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0209 */
/*0640*/ LOP3.LUT R14, R14, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x000060000e0e7a12 */
/* 0x000fc600078e3cff */
/*0650*/ IMAD.HI.U32 R4, R5, R15, R4 ; /* 0x0000000f05047227 */
/* 0x000fe200078e0004 */
/*0660*/ ISETP.GE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fca0003f46270 */
/*0670*/ IMAD.HI.U32 R4, R4, R0, RZ ; /* 0x0000000004047227 */
/* 0x000fca00078e00ff */
/*0680*/ IADD3 R2, -R4, RZ, RZ ; /* 0x000000ff04027210 */
/* 0x000fca0007ffe1ff */
/*0690*/ IMAD R0, R11, R2, R0 ; /* 0x000000020b007224 */
/* 0x000fca00078e0200 */
/*06a0*/ ISETP.GT.U32.AND P1, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f24070 */
/*06b0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R11 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a0b */
/*06c0*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*06e0*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fda0003f06070 */
/*06f0*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc80007ffe0ff */
/*0700*/ @!P2 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff0404a210 */
/* 0x000fe40007ffe1ff */
/*0710*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff049a12 */
/* 0x000fca00078e33ff */
/*0720*/ STG.E [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x000fe2000c101904 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6MirrorPjS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff007212 */
/* 0x001fc800078e33ff */
/*0060*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fc800078e0200 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fc800078e0204 */
/*00b0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MirrorPjS_ii
.globl _Z6MirrorPjS_ii
.p2align 8
.type _Z6MirrorPjS_ii,@function
_Z6MirrorPjS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
v_not_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, s15, s4, v1
v_add_nc_u32_e32 v0, s15, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MirrorPjS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MirrorPjS_ii, .Lfunc_end0-_Z6MirrorPjS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11Filter_funcPjS_iiS_i
.globl _Z11Filter_funcPjS_iiS_i
.p2align 8
.type _Z11Filter_funcPjS_iiS_i,@function
_Z11Filter_funcPjS_iiS_i:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
s_cmp_eq_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_cselect_b32 s10, -1, 0
s_cmp_lg_u32 s15, 0
s_cselect_b32 s9, -1, 0
s_add_i32 s4, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s15, s4
v_ashrrev_i32_e32 v5, 31, v1
s_cselect_b32 s7, -1, 0
s_cmp_lg_u32 s15, s4
s_cselect_b32 s8, -1, 0
s_or_b32 s4, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_mov_b32 s4, -1
s_cbranch_vccz .LBB1_2
v_subrev_nc_u32_e32 v3, s6, v1
v_mov_b32_e32 v2, v5
v_lshlrev_b32_e32 v8, 2, v0
v_add_lshl_u32 v9, v0, s6, 2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v7, v[6:7], off
v_add_nc_u32_e32 v2, s6, v1
v_lshl_add_u32 v6, s6, 1, v0
s_waitcnt vmcnt(1)
ds_store_b32 v8, v4
s_waitcnt vmcnt(0)
ds_store_b32 v9, v7
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_cbranch_execz .LBB1_3
s_branch .LBB1_7
.LBB1_2:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_7
.LBB1_3:
v_add_lshl_u32 v4, v0, s6, 2
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB1_5
v_mov_b32_e32 v2, v5
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v7, v[2:3], off
v_subrev_nc_u32_e32 v2, s6, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v7
s_cbranch_execz .LBB1_6
s_branch .LBB1_7
.LBB1_5:
.LBB1_6:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v8, v[6:7], off
v_dual_mov_b32 v7, v2 :: v_dual_add_nc_u32 v6, s6, v1
v_lshlrev_b64 v[2:3], 2, v[6:7]
v_lshl_add_u32 v6, s6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v4, v8
.LBB1_7:
global_load_b32 v3, v[2:3], off
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v4, 0x1ff, v0
v_lshlrev_b32_e32 v6, 2, v6
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 0, v4
v_cmp_ne_u32_e64 s3, 0, v4
s_or_b32 s10, s10, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s11, s10, -1
s_waitcnt vmcnt(0)
ds_store_b32 v6, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s10, s11
s_cbranch_execz .LBB1_9
v_lshl_add_u32 v2, v0, 2, -4
s_load_b32 s11, s[4:5], 0x0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v2, s11
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s10
v_cndmask_b32_e64 v3, 0, 1, s9
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_11
v_lshlrev_b32_e32 v4, 2, v0
s_load_b32 s9, s[4:5], 0x4
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v4, s9, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v6
.LBB1_11:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 1, v3
s_cbranch_vccnz .LBB1_15
v_add_nc_u32_e32 v3, 1, v0
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, 0x1ff, v3
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB1_14
v_lshlrev_b32_e32 v3, 2, v3
s_load_b32 s10, s[4:5], 0x8
ds_load_b32 v6, v3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v6, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v3
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s9
.LBB1_15:
v_add_nc_u32_e32 v3, s6, v0
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB1_17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v3, 2, -4
s_load_b32 s3, s[4:5], 0xc
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v4, s3, v[2:3]
v_mov_b32_e32 v2, v6
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 2, v3
s_load_b32 s3, s[4:5], 0x10
v_add_nc_u32_e32 v3, 1, v0
s_mov_b32 s9, exec_lo
ds_load_b32 v7, v6
v_and_b32_e32 v8, 0x1ff, v3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v7, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cmp_eq_u32_e64 s3, 0, v8
v_cmpx_ne_u32_e32 0, v8
s_cbranch_execz .LBB1_19
s_load_b32 s10, s[4:5], 0x14
ds_load_b32 v2, v6 offset:4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v2, s10, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v6
.LBB1_19:
s_or_b32 exec_lo, exec_lo, s9
s_or_b32 s2, s2, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s9, s2, -1
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB1_21
v_lshl_add_u32 v2, s6, 1, v0
s_load_b32 s9, s[4:5], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, -4
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v2, s9, v[3:4]
v_mov_b32_e32 v3, v6
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB1_23
s_lshl_b32 s2, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_lshl_u32 v2, s2, v0, 2
s_load_b32 s2, s[4:5], 0x1c
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v2, s2, v[3:4]
v_mov_b32_e32 v3, v6
.LBB1_23:
s_or_b32 s2, s3, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_25
s_lshl_b32 s3, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_lshl_u32 v0, v0, s3, 2
s_load_b32 s3, s[4:5], 0x20
ds_load_b32 v0, v0 offset:4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v0, s3, v[3:4]
v_mov_b32_e32 v3, v6
.LBB1_25:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s2, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v3, v3, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_add_i32 s2, s2, s3
v_xor_b32_e32 v4, s3, v4
s_xor_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s4, 0, s2
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v3, v0
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v2
v_add_nc_u32_e32 v3, 1, v0
v_subrev_nc_u32_e32 v6, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_mov_b32_e32 v2, v5
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v0, v4
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Filter_funcPjS_iiS_i
.amdhsa_group_segment_fixed_size 6144
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11Filter_funcPjS_iiS_i, .Lfunc_end1-_Z11Filter_funcPjS_iiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MirrorPjS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MirrorPjS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 6144
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Filter_funcPjS_iiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11Filter_funcPjS_iiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112e9c_00000000-6_project.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6MirrorPjS_iiPjS_ii
.type _Z29__device_stub__Z6MirrorPjS_iiPjS_ii, @function
_Z29__device_stub__Z6MirrorPjS_iiPjS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MirrorPjS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6MirrorPjS_iiPjS_ii, .-_Z29__device_stub__Z6MirrorPjS_iiPjS_ii
.globl _Z6MirrorPjS_ii
.type _Z6MirrorPjS_ii, @function
_Z6MirrorPjS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6MirrorPjS_iiPjS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MirrorPjS_ii, .-_Z6MirrorPjS_ii
.globl _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
.type _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i, @function
_Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Filter_funcPjS_iiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i, .-_Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
.globl _Z11Filter_funcPjS_iiS_i
.type _Z11Filter_funcPjS_iiS_i, @function
_Z11Filter_funcPjS_iiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11Filter_funcPjS_iiS_i, .-_Z11Filter_funcPjS_iiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%c"
.section .rodata.str1.8
.align 8
.LC2:
.string "Do you want to input filter values by yourself? (Y/N)\n"
.align 8
.LC3:
.string "Please input 9 filter values:\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.LC5:
.string "rb"
.LC6:
.string "lena.bmp"
.LC7:
.string "wb+"
.LC8:
.string "lena3.bmp"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1, 64(%rsp)
movl $2, 68(%rsp)
movl $1, 72(%rsp)
movl $2, 76(%rsp)
movl $4, 80(%rsp)
movl $2, 84(%rsp)
movl $1, 88(%rsp)
movl $2, 92(%rsp)
movl $1, 96(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 3(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq stdin(%rip), %rdi
call getc@PLT
movzbl 3(%rsp), %eax
andl $-33, %eax
cmpb $65, %al
je .L39
.L20:
movl $0, 4(%rsp)
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %edx
movl $10, %esi
movq %rax, %rdi
call fseek@PLT
leaq 12(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $18, %esi
movq %r13, %rdi
call fseek@PLT
leaq 8(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $22, %esi
movq %r13, %rdi
call fseek@PLT
leaq 4(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 8(%rsp), %r12d
imull 4(%rsp), %r12d
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 0(,%r12,4), %rdi
call malloc@PLT
movq %rax, %rbp
movl 12(%rsp), %esi
movl $0, %edx
movq %r13, %rdi
call fseek@PLT
movl 8(%rsp), %ecx
imull 4(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %r12, %rsi
movq %rbx, %rdi
call __fread_chk@PLT
movl 12(%rsp), %r14d
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
movl 12(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call __fread_chk@PLT
movl 8(%rsp), %esi
cmpl $1024, %esi
jbe .L22
movl %esi, %r13d
imull 4(%rsp), %r13d
shrl $10, %r13d
movl $1024, %r14d
.L23:
imull 4(%rsp), %esi
testl %esi, %esi
je .L24
movl %esi, %ecx
movl $0, %eax
.L25:
movzbl (%rbx,%rax), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %rcx
jne .L25
.L24:
leaq 64(%rsp), %rax
leaq 100(%rsp), %rcx
movl $0, %edx
.L26:
addl (%rax), %edx
movl %edx, %r15d
addq $4, %rax
cmpq %rax, %rcx
jne .L26
movl %esi, %esi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %esi
imull 4(%rsp), %esi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl 8(%rsp), %edx
imull 4(%rsp), %edx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movzbl 3(%rsp), %eax
andl $-33, %eax
cmpb $65, %al
je .L40
cmpb $66, %al
jne .L29
movl %r14d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r13d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl 8(%rsp), %ecx
movl 4(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6MirrorPjS_iiPjS_ii
jmp .L29
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq stdin(%rip), %rdi
call getc@PLT
movzbl 2(%rsp), %eax
andl $-33, %eax
cmpb $89, %al
jne .L20
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
leaq 100(%rsp), %r12
leaq .LC4(%rip), %rbp
.L21:
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L21
movq stdin(%rip), %rdi
call getc@PLT
jmp .L20
.L22:
movl 4(%rsp), %r13d
movl %esi, %r14d
jmp .L23
.L40:
movl %r14d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r13d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L28:
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $36, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
.L29:
call cudaThreadSynchronize@PLT
movl 8(%rsp), %edx
imull 4(%rsp), %edx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %ecx
imull 8(%rsp), %ecx
testl %ecx, %ecx
je .L31
movl %ecx, %ecx
movl $0, %eax
.L32:
movl 0(%rbp,%rax,4), %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L32
.L31:
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl 12(%rsp), %edx
movq %rax, %rcx
movl $1, %esi
movq %r12, %rdi
call fwrite@PLT
movl 8(%rsp), %edx
imull 4(%rsp), %edx
movq %rbp, %rcx
movl $4, %esi
movq %rbx, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %r15d, %r9d
movq 32(%rsp), %r8
movl 8(%rsp), %ecx
movl 4(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z11Filter_funcPjS_iiS_iPjS_iiS_i
jmp .L28
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11Filter_funcPjS_iiS_i"
.LC10:
.string "_Z6MirrorPjS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Filter_funcPjS_iiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MirrorPjS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "project.hip"
.globl _Z21__device_stub__MirrorPjS_ii # -- Begin function _Z21__device_stub__MirrorPjS_ii
.p2align 4, 0x90
.type _Z21__device_stub__MirrorPjS_ii,@function
_Z21__device_stub__MirrorPjS_ii: # @_Z21__device_stub__MirrorPjS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MirrorPjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__MirrorPjS_ii, .Lfunc_end0-_Z21__device_stub__MirrorPjS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__Filter_funcPjS_iiS_i # -- Begin function _Z26__device_stub__Filter_funcPjS_iiS_i
.p2align 4, 0x90
.type _Z26__device_stub__Filter_funcPjS_iiS_i,@function
_Z26__device_stub__Filter_funcPjS_iiS_i: # @_Z26__device_stub__Filter_funcPjS_iiS_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Filter_funcPjS_iiS_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z26__device_stub__Filter_funcPjS_iiS_i, .Lfunc_end1-_Z26__device_stub__Filter_funcPjS_iiS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 1 # 0x1
.long 2 # 0x2
.LCPI2_1:
.long 4 # 0x4
.long 2 # 0x2
.long 1 # 0x1
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,1,2]
movaps %xmm0, 224(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [4,2,1,2]
movaps %xmm0, 240(%rsp)
movl $1, 256(%rsp)
movl $.Lstr, %edi
callq puts@PLT
leaq 14(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq stdin(%rip), %rdi
callq getc
movzbl 14(%rsp), %eax
andb $-33, %al
cmpb $65, %al
jne .LBB2_5
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 15(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq stdin(%rip), %rdi
callq getc
movzbl 15(%rsp), %eax
andb $-33, %al
cmpb $89, %al
jne .LBB2_5
# %bb.2:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rsi
addq $224, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbx
cmpq $36, %rbx
jne .LBB2_3
# %bb.4:
movq stdin(%rip), %rdi
callq getc
.LBB2_5:
movl $0, 32(%rsp)
movl $0, 28(%rsp)
movl $0, 24(%rsp)
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r13
xorl %r12d, %r12d
movl $10, %esi
movq %rax, %rdi
xorl %edx, %edx
callq fseek
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl $18, %esi
movq %r13, %rdi
xorl %edx, %edx
callq fseek
leaq 28(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl $22, %esi
movq %r13, %rdi
xorl %edx, %edx
callq fseek
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 28(%rsp), %eax
movl %eax, 20(%rsp) # 4-byte Spill
movl 32(%rsp), %ecx
movl %ecx, 16(%rsp) # 4-byte Spill
movl %ecx, %ebp
imull %eax, %ebp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
leaq (,%rbp,4), %rdi
movq %rdi, 208(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r14
movl 24(%rsp), %r15d
movq %r13, %rdi
movq %r15, %rsi
movq %r15, 200(%rsp) # 8-byte Spill
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %rbx, %rdi
movq %rbp, %rdx
movq %r13, %rcx
callq fread
movq %r15, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %r15, 216(%rsp) # 8-byte Spill
movq %r15, %rdi
movq 200(%rsp), %rdx # 8-byte Reload
movq %r13, %rcx
callq fread
movl %ebp, %r13d
shrl $10, %r13d
movl 20(%rsp), %eax # 4-byte Reload
cmpl $1025, %eax # imm = 0x401
cmovbl 16(%rsp), %r13d # 4-byte Folded Reload
cmpl $1024, %eax # imm = 0x400
movl $1024, %r15d # imm = 0x400
cmovbl %eax, %r15d
testl %ebp, %ebp
je .LBB2_6
# %bb.12: # %.lr.ph.preheader
movl %ebp, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_13
.LBB2_6: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Inner Loop Header: Depth=1
addl 224(%rsp,%rax,4), %r12d
incq %rax
cmpq $9, %rax
jne .LBB2_7
# %bb.8:
leaq 48(%rsp), %rdi
movq 208(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 136(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movzbl 14(%rsp), %eax
andl $-33, %eax
cmpl $65, %eax
je .LBB2_14
# %bb.9:
cmpl $66, %eax
jne .LBB2_17
# %bb.10:
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.11:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6MirrorPjS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_17
.LBB2_14:
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 136(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 132(%rsp)
movq %rdx, 72(%rsp)
movl %r12d, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 132(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z11Filter_funcPjS_iiS_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
movq 136(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $36, %edx
movl $1, %ecx
callq hipMemcpy
.LBB2_17:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl 32(%rsp), %r12d
imull 28(%rsp), %r12d
leaq (,%r12,4), %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
je .LBB2_20
# %bb.18: # %.lr.ph98.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_19: # %.lr.ph98
# =>This Inner Loop Header: Depth=1
movzbl (%r14,%rax,4), %ecx
movb %cl, (%rbx,%rax)
incq %rax
cmpq %rax, %r12
jne .LBB2_19
.LBB2_20: # %._crit_edge
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r14
movl 24(%rsp), %edx
movl $1, %esi
movq 216(%rsp), %rdi # 8-byte Reload
movq %rax, %rcx
callq fwrite
movl $4, %esi
movq %rbx, %rdi
movq %r12, %rdx
movq %r14, %rcx
callq fwrite
movq %r14, %rdi
callq fclose
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MirrorPjS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Filter_funcPjS_iiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MirrorPjS_ii,@object # @_Z6MirrorPjS_ii
.section .rodata,"a",@progbits
.globl _Z6MirrorPjS_ii
.p2align 3, 0x0
_Z6MirrorPjS_ii:
.quad _Z21__device_stub__MirrorPjS_ii
.size _Z6MirrorPjS_ii, 8
.type _Z11Filter_funcPjS_iiS_i,@object # @_Z11Filter_funcPjS_iiS_i
.globl _Z11Filter_funcPjS_iiS_i
.p2align 3, 0x0
_Z11Filter_funcPjS_iiS_i:
.quad _Z26__device_stub__Filter_funcPjS_iiS_i
.size _Z11Filter_funcPjS_iiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%c"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "lena.bmp"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "rb"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "lena3.bmp"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "wb+"
.size .L.str.8, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MirrorPjS_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11Filter_funcPjS_iiS_i"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "What do you want to do?\n(a)Filter the picture\n(b)Mirror the picture"
.size .Lstr, 68
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Do you want to input filter values by yourself? (Y/N)"
.size .Lstr.1, 54
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Please input 9 filter values:"
.size .Lstr.2, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MirrorPjS_ii
.addrsig_sym _Z26__device_stub__Filter_funcPjS_iiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MirrorPjS_ii
.addrsig_sym _Z11Filter_funcPjS_iiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | template<int block_size, int elements_per_thread, int tiling_strategy>
__global__ void vector_add(int n, float* C, const float* A, const float* B) {
static_assert(
tiling_strategy >= 0 && tiling_strategy < 3,
"invalid tiling strategy");
for (int k = 0; k < elements_per_thread; k++) {
int i;
// contiguous. thread processes element i, i+1, i+2, ...
if (tiling_strategy == 0) {
i = (blockIdx.x * block_size + threadIdx.x) * elements_per_thread
+ k;
}
// block-strided. thread processes elements i, i + block_size, i + 2*block_size
else if (tiling_strategy == 1) {
i = blockIdx.x * elements_per_thread * block_size + threadIdx.x
+ k * block_size;
}
// grid-strided. thread processes elements i, i + grid_size, i + 2 * grid_size
else if (tiling_strategy == 2) {
i = blockIdx.x * block_size + threadIdx.x
+ k * (gridDim.x * block_size);
}
if (i < n) {
C[i] = A[i] + B[i];
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | template<int block_size, int elements_per_thread, int tiling_strategy>
__global__ void vector_add(int n, float* C, const float* A, const float* B) {
static_assert(
tiling_strategy >= 0 && tiling_strategy < 3,
"invalid tiling strategy");
for (int k = 0; k < elements_per_thread; k++) {
int i;
// contiguous. thread processes element i, i+1, i+2, ...
if (tiling_strategy == 0) {
i = (blockIdx.x * block_size + threadIdx.x) * elements_per_thread
+ k;
}
// block-strided. thread processes elements i, i + block_size, i + 2*block_size
else if (tiling_strategy == 1) {
i = blockIdx.x * elements_per_thread * block_size + threadIdx.x
+ k * block_size;
}
// grid-strided. thread processes elements i, i + grid_size, i + 2 * grid_size
else if (tiling_strategy == 2) {
i = blockIdx.x * block_size + threadIdx.x
+ k * (gridDim.x * block_size);
}
if (i < n) {
C[i] = A[i] + B[i];
}
}
} | .file "tmpxft_001976b4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | template<int block_size, int elements_per_thread, int tiling_strategy>
__global__ void vector_add(int n, float* C, const float* A, const float* B) {
static_assert(
tiling_strategy >= 0 && tiling_strategy < 3,
"invalid tiling strategy");
for (int k = 0; k < elements_per_thread; k++) {
int i;
// contiguous. thread processes element i, i+1, i+2, ...
if (tiling_strategy == 0) {
i = (blockIdx.x * block_size + threadIdx.x) * elements_per_thread
+ k;
}
// block-strided. thread processes elements i, i + block_size, i + 2*block_size
else if (tiling_strategy == 1) {
i = blockIdx.x * elements_per_thread * block_size + threadIdx.x
+ k * block_size;
}
// grid-strided. thread processes elements i, i + grid_size, i + 2 * grid_size
else if (tiling_strategy == 2) {
i = blockIdx.x * block_size + threadIdx.x
+ k * (gridDim.x * block_size);
}
if (i < n) {
C[i] = A[i] + B[i];
}
}
} | #include <hip/hip_runtime.h>
template<int block_size, int elements_per_thread, int tiling_strategy>
__global__ void vector_add(int n, float* C, const float* A, const float* B) {
static_assert(
tiling_strategy >= 0 && tiling_strategy < 3,
"invalid tiling strategy");
for (int k = 0; k < elements_per_thread; k++) {
int i;
// contiguous. thread processes element i, i+1, i+2, ...
if (tiling_strategy == 0) {
i = (blockIdx.x * block_size + threadIdx.x) * elements_per_thread
+ k;
}
// block-strided. thread processes elements i, i + block_size, i + 2*block_size
else if (tiling_strategy == 1) {
i = blockIdx.x * elements_per_thread * block_size + threadIdx.x
+ k * block_size;
}
// grid-strided. thread processes elements i, i + grid_size, i + 2 * grid_size
else if (tiling_strategy == 2) {
i = blockIdx.x * block_size + threadIdx.x
+ k * (gridDim.x * block_size);
}
if (i < n) {
C[i] = A[i] + B[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
template<int block_size, int elements_per_thread, int tiling_strategy>
__global__ void vector_add(int n, float* C, const float* A, const float* B) {
static_assert(
tiling_strategy >= 0 && tiling_strategy < 3,
"invalid tiling strategy");
for (int k = 0; k < elements_per_thread; k++) {
int i;
// contiguous. thread processes element i, i+1, i+2, ...
if (tiling_strategy == 0) {
i = (blockIdx.x * block_size + threadIdx.x) * elements_per_thread
+ k;
}
// block-strided. thread processes elements i, i + block_size, i + 2*block_size
else if (tiling_strategy == 1) {
i = blockIdx.x * elements_per_thread * block_size + threadIdx.x
+ k * block_size;
}
// grid-strided. thread processes elements i, i + grid_size, i + 2 * grid_size
else if (tiling_strategy == 2) {
i = blockIdx.x * block_size + threadIdx.x
+ k * (gridDim.x * block_size);
}
if (i < n) {
C[i] = A[i] + B[i];
}
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
template<int block_size, int elements_per_thread, int tiling_strategy>
__global__ void vector_add(int n, float* C, const float* A, const float* B) {
static_assert(
tiling_strategy >= 0 && tiling_strategy < 3,
"invalid tiling strategy");
for (int k = 0; k < elements_per_thread; k++) {
int i;
// contiguous. thread processes element i, i+1, i+2, ...
if (tiling_strategy == 0) {
i = (blockIdx.x * block_size + threadIdx.x) * elements_per_thread
+ k;
}
// block-strided. thread processes elements i, i + block_size, i + 2*block_size
else if (tiling_strategy == 1) {
i = blockIdx.x * elements_per_thread * block_size + threadIdx.x
+ k * block_size;
}
// grid-strided. thread processes elements i, i + grid_size, i + 2 * grid_size
else if (tiling_strategy == 2) {
i = blockIdx.x * block_size + threadIdx.x
+ k * (gridDim.x * block_size);
}
if (i < n) {
C[i] = A[i] + B[i];
}
}
} | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001976b4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/** Modifed version of knn-CUDA from https://github.com/vincentfpgarcia/kNN-CUDA
* The modifications are
* removed texture memory usage
* removed split query KNN computation
* added feature extraction with bilinear interpolation
*
* Last modified by Christopher B. Choy <chrischoy@ai.stanford.edu> 12/23/2016
*/
// Includes
// Constants used by the program
#define BLOCK_DIM 16
//-----------------------------------------------------------------------------------------------//
// KERNELS //
//-----------------------------------------------------------------------------------------------//
/**
* Computes the distance between two matrix A (reference points) and
* B (query points) containing respectively wA and wB points.
*
* @param A pointer on the matrix A
* @param wA width of the matrix A = number of points in A
* @param B pointer on the matrix B
* @param wB width of the matrix B = number of points in B
* @param dim dimension of points = height of matrices A and B
* @param AB pointer on the matrix containing the wA*wB distances computed
*/
/**
* Gathers k-th smallest distances for each column of the distance matrix in the top.
*
* @param dist distance matrix
* @param ind index matrix
* @param width width of the distance matrix and of the index matrix
* @param height height of the distance matrix and of the index matrix
* @param k number of neighbors to consider
*/
/**
* Computes the square root of the first line (width-th first element)
* of the distance matrix.
*
* @param dist distance matrix
* @param width width of the distance matrix
* @param k number of neighbors to consider
*/
//-----------------------------------------------------------------------------------------------//
// K-th NEAREST NEIGHBORS //
//-----------------------------------------------------------------------------------------------//
/**
* Prints the error message return during the memory allocation.
*
* @param error error value return by the memory allocation function
* @param memorySize size of memory tried to be allocated
*/
__global__ void extract_with_interpolation( int nthreads, float *data, float *n_xy_coords, float *extracted_data, int n_max_coord, int channels, int height, int width) {
int x0, x1, y0, y1, nc;
float wx0, wx1, wy0, wy1;
int n, nd;
float x, y;
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < (nthreads);
index += blockDim.x * gridDim.x) {
n = (index / n_max_coord);
nd = n * n_max_coord * channels;
x = n_xy_coords[index * 2];
y = n_xy_coords[index * 2 + 1];
x0 = static_cast<int>(floor(x));
x1 = x0 + 1;
y0 = static_cast<int>(floor(y));
y1 = y0 + 1;
x0 = x0 <= 0 ? 0 : (x0 >= (width - 1) ? (width - 1) : x0);
y0 = y0 <= 0 ? 0 : (y0 >= (height - 1) ? (height - 1) : y0);
x1 = x1 <= 0 ? 0 : (x1 >= (width - 1) ? (width - 1) : x1);
y1 = y1 <= 0 ? 0 : (y1 >= (height - 1) ? (height - 1) : y1);
wx0 = static_cast<float>(x1) - x;
wx1 = x - x0;
wy0 = static_cast<float>(y1) - y;
wy1 = y - y0;
if(x0 == x1){ wx0 = 1; wx1 = 0; }
if(y0 == y1){ wy0 = 1; wy1 = 0; }
for(int c=0; c < channels; c++) {
nc = (n * channels + c) * height;
// extracted_data[index * channels + c] = wy0 * wx0 * data[(nc + y0) * width + x0]
// extracted_data[nd + index % n_max_coord + n_max_coord * c] = index;
extracted_data[nd + index % n_max_coord + n_max_coord * c] = wy0 * wx0 * data[(nc + y0) * width + x0]
+ wy1 * wx0 * data[(nc + y1) * width + x0]
+ wy0 * wx1 * data[(nc + y0) * width + x1]
+ wy1 * wx1 * data[(nc + y1) * width + x1];
}
}
} | code for sm_80
Function : _Z26extract_with_interpolationiPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fda0003f01270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe40000000800 */
/*0090*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x188] ; /* 0x0000620000067ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ ULOP3.LUT UR10, UR5, 0x3, URZ, 0xc0, !UPT ; /* 0x00000003050a7892 */
/* 0x000fe4000f8ec03f */
/*00c0*/ UIADD3 UR8, -UR4, UR7, URZ ; /* 0x0000000704087290 */
/* 0x000fe4000fffe13f */
/*00d0*/ UIADD3 UR9, -UR4, UR6, URZ ; /* 0x0000000604097290 */
/* 0x000fc4000fffe13f */
/*00e0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe4000fffe13f */
/*00f0*/ UIMAD UR6, UR7, UR6, URZ ; /* 0x00000006070672a4 */
/* 0x000fe4000f8e023f */
/*0100*/ UIADD3 UR5, -UR10, UR5, URZ ; /* 0x000000050a057290 */
/* 0x000fe4000fffe13f */
/*0110*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe40000000a00 */
/*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0130*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x000fd200000006ff */
/*0140*/ IMAD.WIDE R4, R5, R2, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0202 */
/*0150*/ LDG.E R7, [R4.64] ; /* 0x0000000c04077981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040c04087981 */
/* 0x0000e2000c1e1900 */
/*0170*/ IABS R9, c[0x0][0x180] ; /* 0x0000600000097a13 */
/* 0x000fe20000000000 */
/*0180*/ UISETP.GE.U32.AND UP0, UPT, UR4, 0x3, UPT ; /* 0x000000030400788c */
/* 0x000fe2000bf06070 */
/*0190*/ IABS R12, R0 ; /* 0x00000000000c7213 */
/* 0x000fe20000000000 */
/*01a0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*01b0*/ I2F.RP R3, R9 ; /* 0x0000000900037306 */
/* 0x000e700000209400 */
/*01c0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x002e640000001000 */
/*01d0*/ IADD3 R11, R3, 0xffffffe, RZ ; /* 0x0ffffffe030b7810 */
/* 0x002fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e64000021f000 */
/*01f0*/ IADD3 R10, RZ, -R11, RZ ; /* 0x8000000bff0a7210 */
/* 0x002fca0007ffe0ff */
/*0200*/ IMAD R13, R10, R9, RZ ; /* 0x000000090a0d7224 */
/* 0x000fe200078e02ff */
/*0210*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fca0000000f00 */
/*0220*/ IMAD.HI.U32 R10, R11, R13, R10 ; /* 0x0000000d0b0a7227 */
/* 0x000fcc00078e000a */
/*0230*/ IMAD.HI.U32 R10, R10, R12, RZ ; /* 0x0000000c0a0a7227 */
/* 0x000fca00078e00ff */
/*0240*/ IADD3 R4, -R10, RZ, RZ ; /* 0x000000ff0a047210 */
/* 0x001fca0007ffe1ff */
/*0250*/ IMAD R12, R9, R4, R12 ; /* 0x00000004090c7224 */
/* 0x000fe200078e020c */
/*0260*/ F2I.FLOOR.NTZ R6, R7 ; /* 0x0000000700067305 */
/* 0x004e300000207100 */
/*0270*/ F2I.FLOOR.NTZ R13, R8 ; /* 0x00000008000d7305 */
/* 0x008e620000207100 */
/*0280*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x001fc40003f06270 */
/*0290*/ IMNMX R3, R6.reuse, UR8, PT ; /* 0x0000000806037c17 */
/* 0x040fe4000b800200 */
/*02a0*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ SEL R3, R3, RZ, P0 ; /* 0x000000ff03037207 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R9, R12, PT ; /* 0x0000000c0900720c */
/* 0x000fe40003f04070 */
/*02d0*/ ISETP.GE.AND P1, PT, R13.reuse, 0x1, PT ; /* 0x000000010d00780c */
/* 0x042fe20003f26270 */
/*02e0*/ I2F R16, R3 ; /* 0x0000000300107306 */
/* 0x000e220000201400 */
/*02f0*/ IMNMX R4, R13, UR9, PT ; /* 0x000000090d047c17 */
/* 0x000fc8000b800200 */
/*0300*/ SEL R4, R4, RZ, P1 ; /* 0x000000ff04047207 */
/* 0x000fe40000800000 */
/*0310*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f26270 */
/*0320*/ IMNMX R6, R5, UR8, PT ; /* 0x0000000805067c17 */
/* 0x000fe2000b800200 */
/*0330*/ I2F R15, R4 ; /* 0x00000004000f7306 */
/* 0x000e620000201400 */
/*0340*/ IADD3 R5, R13, 0x1, RZ ; /* 0x000000010d057810 */
/* 0x000fe40007ffe0ff */
/*0350*/ SEL R6, R6, RZ, P1 ; /* 0x000000ff06067207 */
/* 0x000fe40000800000 */
/*0360*/ @!P0 IADD3 R12, R12, -R9, RZ ; /* 0x800000090c0c8210 */
/* 0x000fe20007ffe0ff */
/*0370*/ FADD R16, R7, -R16 ; /* 0x8000001007107221 */
/* 0x001fe20000000000 */
/*0380*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f26270 */
/*0390*/ I2F R14, R6 ; /* 0x00000006000e7306 */
/* 0x000e220000201400 */
/*03a0*/ IMNMX R5, R5, UR9, PT ; /* 0x0000000905057c17 */
/* 0x000fc4000b800200 */
/*03b0*/ ISETP.GE.U32.AND P2, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fe40003f46070 */
/*03c0*/ SEL R5, R5, RZ, P1 ; /* 0x000000ff05057207 */
/* 0x000fe40000800000 */
/*03d0*/ LOP3.LUT R9, R0, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600000097a12 */
/* 0x000fe200078e3cff */
/*03e0*/ FADD R15, R8, -R15 ; /* 0x8000000f080f7221 */
/* 0x002fe20000000000 */
/*03f0*/ I2F R11, R5 ; /* 0x00000005000b7306 */
/* 0x000e620000201400 */
/*0400*/ @!P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a8810 */
/* 0x000fe40007ffe0ff */
/*0410*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f26270 */
/*0420*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc40003f05270 */
/*0430*/ @P2 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a2810 */
/* 0x000fe20007ffe0ff */
/*0440*/ FADD R14, -R7, R14 ; /* 0x0000000e070e7221 */
/* 0x001fe20000000100 */
/*0450*/ PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f4f008 */
/*0460*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fe40000000f00 */
/*0470*/ ISETP.NE.AND P3, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f65270 */
/*0480*/ ISETP.NE.AND P4, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe20003f85270 */
/*0490*/ FADD R11, -R8, R11 ; /* 0x0000000b080b7221 */
/* 0x002fe20000000100 */
/*04a0*/ @!P1 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07079210 */
/* 0x000fc40007ffe1ff */
/*04b0*/ @!P0 LOP3.LUT R7, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff078a12 */
/* 0x000fe400078e33ff */
/*04c0*/ FSEL R16, R16, RZ, P3 ; /* 0x000000ff10107208 */
/* 0x000fe40001800000 */
/*04d0*/ FSEL R15, R15, RZ, P4 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40002000000 */
/*04e0*/ FSEL R14, R14, 1, P3 ; /* 0x3f8000000e0e7808 */
/* 0x000fe40001800000 */
/*04f0*/ FSEL R11, R11, 1, P4 ; /* 0x3f8000000b0b7808 */
/* 0x000fe20002000000 */
/*0500*/ FMUL R8, R16, R15.reuse ; /* 0x0000000f10087220 */
/* 0x080fe20000400000 */
/*0510*/ IADD3 R25, -R7, RZ, RZ ; /* 0x000000ff07197210 */
/* 0x000fe20007ffe1ff */
/*0520*/ FMUL R9, R14.reuse, R15 ; /* 0x0000000f0e097220 */
/* 0x040fe20000400000 */
/*0530*/ ISETP.NE.AND P1, PT, RZ, UR10, PT ; /* 0x0000000aff007c0c */
/* 0x000fe2000bf25270 */
/*0540*/ FMUL R22, R14, R11 ; /* 0x0000000b0e167220 */
/* 0x000fc40000400000 */
/*0550*/ FMUL R23, R16, R11 ; /* 0x0000000b10177220 */
/* 0x000fe40000400000 */
/*0560*/ IMAD R25, R25, c[0x0][0x180], R0 ; /* 0x0000600019197a24 */
/* 0x000fe200078e0200 */
/*0570*/ @!P2 BRA 0xa60 ; /* 0x000004e00000a947 */
/* 0x000fee0003800000 */
/*0580*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0590*/ MOV R26, UR5 ; /* 0x00000005001a7c02 */
/* 0x000fc60008000f00 */
/*05a0*/ IMAD R12, R7, c[0x0][0x184], R24 ; /* 0x00006100070c7a24 */
/* 0x000fc800078e0218 */
/*05b0*/ IMAD R13, R12.reuse, c[0x0][0x188], R5 ; /* 0x000062000c0d7a24 */
/* 0x040fe400078e0205 */
/*05c0*/ IMAD R10, R12, c[0x0][0x188], R4 ; /* 0x000062000c0a7a24 */
/* 0x001fe400078e0204 */
/*05d0*/ IMAD R17, R13, c[0x0][0x18c], R3.reuse ; /* 0x000063000d117a24 */
/* 0x100fe400078e0203 */
/*05e0*/ IMAD R11, R10, c[0x0][0x18c], R3 ; /* 0x000063000a0b7a24 */
/* 0x000fe400078e0203 */
/*05f0*/ IMAD.WIDE R16, R17, R2, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc800078e0202 */
/*0600*/ IMAD R19, R10, c[0x0][0x18c], R6 ; /* 0x000063000a137a24 */
/* 0x000fe200078e0206 */
/*0610*/ LDG.E R28, [R16.64] ; /* 0x0000000c101c7981 */
/* 0x0000a2000c1e1900 */
/*0620*/ IMAD.WIDE R10, R11, R2, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc800078e0202 */
/*0630*/ IMAD.WIDE R18, R19, R2, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fe200078e0202 */
/*0640*/ LDG.E R21, [R10.64] ; /* 0x0000000c0a157981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R20, [R18.64] ; /* 0x0000000c12147981 */
/* 0x000f22000c1e1900 */
/*0660*/ IMAD R15, R13, c[0x0][0x18c], R6 ; /* 0x000063000d0f7a24 */
/* 0x000fc800078e0206 */
/*0670*/ IMAD.WIDE R14, R15, R2, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fca00078e0202 */
/*0680*/ LDG.E R13, [R14.64] ; /* 0x0000000c0e0d7981 */
/* 0x000f62000c1e1900 */
/*0690*/ MOV R29, UR6 ; /* 0x00000006001d7c02 */
/* 0x000fca0008000f00 */
/*06a0*/ IMAD.WIDE R16, R29, 0x4, R16 ; /* 0x000000041d107825 */
/* 0x001fc800078e0210 */
/*06b0*/ FMUL R28, R9, R28 ; /* 0x0000001c091c7220 */
/* 0x004fc80000400000 */
/*06c0*/ FFMA R21, R22, R21, R28 ; /* 0x0000001516157223 */
/* 0x008fc8000000001c */
/*06d0*/ FFMA R27, R23, R20, R21 ; /* 0x00000014171b7223 */
/* 0x010fe20000000015 */
/*06e0*/ MOV R21, UR6 ; /* 0x0000000600157c02 */
/* 0x000fca0008000f00 */
/*06f0*/ IMAD.WIDE R20, R21, 0x4, R10 ; /* 0x0000000415147825 */
/* 0x000fc800078e020a */
/*0700*/ IMAD R11, R12, c[0x0][0x180], R25 ; /* 0x000060000c0b7a24 */
/* 0x000fe400078e0219 */
/*0710*/ FFMA R27, R8, R13, R27 ; /* 0x0000000d081b7223 */
/* 0x020fe4000000001b */
/*0720*/ IMAD.WIDE R10, R11, R2, c[0x0][0x178] ; /* 0x00005e000b0a7625 */
/* 0x000fe200078e0202 */
/*0730*/ MOV R13, UR6 ; /* 0x00000006000d7c02 */
/* 0x000fc80008000f00 */
/*0740*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0001e2000c10190c */
/*0750*/ IMAD.WIDE R18, R13, 0x4, R18 ; /* 0x000000040d127825 */
/* 0x000fc600078e0212 */
/*0760*/ LDG.E R12, [R16.64] ; /* 0x0000000c100c7981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R13, 0x4, R14 ; /* 0x000000040d0e7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R29, [R20.64] ; /* 0x0000000c141d7981 */
/* 0x000ee8000c1e1900 */
/*0790*/ LDG.E R28, [R18.64] ; /* 0x0000000c121c7981 */
/* 0x000328000c1e1900 */
/*07a0*/ LDG.E R13, [R14.64] ; /* 0x0000000c0e0d7981 */
/* 0x000f62000c1e1900 */
/*07b0*/ IMAD.WIDE R10, R2, c[0x0][0x180], R10 ; /* 0x00006000020a7a25 */
/* 0x001fe200078e020a */
/*07c0*/ MOV R27, UR6 ; /* 0x00000006001b7c02 */
/* 0x000fca0008000f00 */
/*07d0*/ IMAD.WIDE R18, R27, 0x4, R18 ; /* 0x000000041b127825 */
/* 0x002fc800078e0212 */
/*07e0*/ FMUL R12, R9, R12 ; /* 0x0000000c090c7220 */
/* 0x004fc80000400000 */
/*07f0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x008fc8000000000c */
/*0800*/ FFMA R12, R23, R28, R12 ; /* 0x0000001c170c7223 */
/* 0x010fc8000000000c */
/*0810*/ FFMA R29, R8, R13, R12 ; /* 0x0000000d081d7223 */
/* 0x020fe2000000000c */
/*0820*/ MOV R13, UR6 ; /* 0x00000006000d7c02 */
/* 0x000fca0008000f00 */
/*0830*/ IMAD.WIDE R12, R13, 0x4, R20 ; /* 0x000000040d0c7825 */
/* 0x000fe200078e0214 */
/*0840*/ MOV R21, UR6 ; /* 0x0000000600157c02 */
/* 0x000fe20008000f00 */
/*0850*/ STG.E [R10.64], R29 ; /* 0x0000001d0a007986 */
/* 0x0001e8000c10190c */
/*0860*/ IMAD.WIDE R16, R21.reuse, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x040fe200078e0210 */
/*0870*/ LDG.E R27, [R12.64] ; /* 0x0000000c0c1b7981 */
/* 0x0002a8000c1e1900 */
/*0880*/ LDG.E R28, [R16.64] ; /* 0x0000000c101c7981 */
/* 0x000722000c1e1900 */
/*0890*/ MOV R20, UR6 ; /* 0x0000000600147c02 */
/* 0x000fe20008000f00 */
/*08a0*/ IMAD.WIDE R14, R21, 0x4, R14 ; /* 0x00000004150e7825 */
/* 0x000fc400078e020e */
/*08b0*/ LDG.E R29, [R18.64] ; /* 0x0000000c121d7981 */
/* 0x001164000c1e1900 */
/*08c0*/ IMAD.WIDE R12, R20, 0x4, R12 ; /* 0x00000004140c7825 */
/* 0x002fc800078e020c */
/*08d0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x008fc800078e0210 */
/*08e0*/ IMAD.WIDE R20, R21, 0x4, R18 ; /* 0x0000000415147825 */
/* 0x000fe400078e0212 */
/*08f0*/ LDG.E R19, [R14.64] ; /* 0x0000000c0e137981 */
/* 0x001ee4000c1e1900 */
/*0900*/ IMAD.WIDE R10, R2, c[0x0][0x180], R10 ; /* 0x00006000020a7a25 */
/* 0x000fc800078e020a */
/*0910*/ FMUL R28, R9, R28 ; /* 0x0000001c091c7220 */
/* 0x010fc80000400000 */
/*0920*/ FFMA R28, R22, R27, R28 ; /* 0x0000001b161c7223 */
/* 0x004fc8000000001c */
/*0930*/ FFMA R28, R23, R29, R28 ; /* 0x0000001d171c7223 */
/* 0x020fe2000000001c */
/*0940*/ MOV R29, UR6 ; /* 0x00000006001d7c02 */
/* 0x000fc60008000f00 */
/*0950*/ FFMA R27, R8, R19, R28 ; /* 0x00000013081b7223 */
/* 0x008fca000000001c */
/*0960*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0001e8000c10190c */
/*0970*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000ea2000c1e1900 */
/*0980*/ IMAD.WIDE R18, R29, 0x4, R14 ; /* 0x000000041d127825 */
/* 0x000fc600078e020e */
/*0990*/ LDG.E R13, [R12.64] ; /* 0x0000000c0c0d7981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R20, [R20.64] ; /* 0x0000000c14147981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R18, [R18.64] ; /* 0x0000000c12127981 */
/* 0x000f62000c1e1900 */
/*09c0*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ FMUL R14, R9, R16 ; /* 0x00000010090e7220 */
/* 0x004fc80000400000 */
/*0a00*/ FFMA R14, R22, R13, R14 ; /* 0x0000000d160e7223 */
/* 0x008fc8000000000e */
/*0a10*/ FFMA R29, R23, R20, R14 ; /* 0x00000014171d7223 */
/* 0x010fe4000000000e */
/*0a20*/ IMAD.WIDE R14, R2, c[0x0][0x180], R10 ; /* 0x00006000020e7a25 */
/* 0x000fc800078e020a */
/*0a30*/ FFMA R29, R8, R18, R29 ; /* 0x00000012081d7223 */
/* 0x020fca000000001d */
/*0a40*/ STG.E [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0001e2000c10190c */
/*0a50*/ @P0 BRA 0x5a0 ; /* 0xfffffb4000000947 */
/* 0x000fea000383ffff */
/*0a60*/ @!P1 BRA 0xef0 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD R24, R7, c[0x0][0x184], R24 ; /* 0x0000610007187a24 */
/* 0x000fc800078e0218 */
/*0a80*/ IMAD R12, R24.reuse, c[0x0][0x188], R5 ; /* 0x00006200180c7a24 */
/* 0x040fe400078e0205 */
/*0a90*/ IMAD R7, R24, c[0x0][0x188], R4 ; /* 0x0000620018077a24 */
/* 0x000fe400078e0204 */
/*0aa0*/ IMAD R15, R12, c[0x0][0x18c], R3.reuse ; /* 0x000063000c0f7a24 */
/* 0x101fe400078e0203 */
/*0ab0*/ IMAD R11, R7, c[0x0][0x18c], R3 ; /* 0x00006300070b7a24 */
/* 0x000fe400078e0203 */
/*0ac0*/ IMAD.WIDE R14, R15, R2, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e0202 */
/*0ad0*/ IMAD R13, R7, c[0x0][0x18c], R6.reuse ; /* 0x00006300070d7a24 */
/* 0x100fe400078e0206 */
/*0ae0*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe200078e0202 */
/*0af0*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000ea6000c1e1900 */
/*0b00*/ IMAD R17, R12, c[0x0][0x18c], R6 ; /* 0x000063000c117a24 */
/* 0x000fe400078e0206 */
/*0b10*/ IMAD.WIDE R12, R13, R2.reuse, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x080fe200078e0202 */
/*0b20*/ LDG.E R11, [R10.64] ; /* 0x0000000c0a0b7981 */
/* 0x000ee6000c1e1900 */
/*0b30*/ IMAD.WIDE R16, R17, R2, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc400078e0202 */
/*0b40*/ LDG.E R12, [R12.64] ; /* 0x0000000c0c0c7981 */
/* 0x000f28000c1e1900 */
/*0b50*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f62000c1e1900 */
/*0b60*/ IMAD R19, R24, c[0x0][0x180], R25 ; /* 0x0000600018137a24 */
/* 0x000fe200078e0219 */
/*0b70*/ UISETP.NE.AND UP0, UPT, UR10, 0x1, UPT ; /* 0x000000010a00788c */
/* 0x000fcc000bf05270 */
/*0b80*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0b90*/ FMUL R7, R9, R14 ; /* 0x0000000e09077220 */
/* 0x004fe40000400000 */
/*0ba0*/ IMAD.WIDE R14, R19, R2, c[0x0][0x178] ; /* 0x00005e00130e7625 */
/* 0x000fc800078e0202 */
/*0bb0*/ FFMA R18, R22, R11, R7 ; /* 0x0000000b16127223 */
/* 0x008fc80000000007 */
/*0bc0*/ FFMA R7, R23, R12, R18 ; /* 0x0000000c17077223 */
/* 0x010fc80000000012 */
/*0bd0*/ FFMA R7, R8, R16, R7 ; /* 0x0000001008077223 */
/* 0x020fca0000000007 */
/*0be0*/ STG.E [R14.64], R7 ; /* 0x000000070e007986 */
/* 0x0001e2000c10190c */
/*0bf0*/ @!P0 BRA 0xef0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0c00*/ IADD3 R18, R24, 0x1, RZ ; /* 0x0000000118127810 */
/* 0x000fca0007ffe0ff */
/*0c10*/ IMAD R12, R18.reuse, c[0x0][0x188], R5 ; /* 0x00006200120c7a24 */
/* 0x040fe400078e0205 */
/*0c20*/ IMAD R7, R18, c[0x0][0x188], R4 ; /* 0x0000620012077a24 */
/* 0x001fe400078e0204 */
/*0c30*/ IMAD R15, R12, c[0x0][0x18c], R3.reuse ; /* 0x000063000c0f7a24 */
/* 0x100fe400078e0203 */
/*0c40*/ IMAD R11, R7, c[0x0][0x18c], R3 ; /* 0x00006300070b7a24 */
/* 0x000fe400078e0203 */
/*0c50*/ IMAD.WIDE R14, R15, R2, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e0202 */
/*0c60*/ IMAD R13, R7, c[0x0][0x18c], R6.reuse ; /* 0x00006300070d7a24 */
/* 0x100fe400078e0206 */
/*0c70*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe200078e0202 */
/*0c80*/ LDG.E R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000ea6000c1e1900 */
/*0c90*/ IMAD R17, R12, c[0x0][0x18c], R6 ; /* 0x000063000c117a24 */
/* 0x000fe400078e0206 */
/*0ca0*/ IMAD.WIDE R12, R13, R2.reuse, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x080fe200078e0202 */
/*0cb0*/ LDG.E R11, [R10.64] ; /* 0x0000000c0a0b7981 */
/* 0x000ee6000c1e1900 */
/*0cc0*/ IMAD.WIDE R16, R17, R2, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc400078e0202 */
/*0cd0*/ LDG.E R12, [R12.64] ; /* 0x0000000c0c0c7981 */
/* 0x000f28000c1e1900 */
/*0ce0*/ LDG.E R16, [R16.64] ; /* 0x0000000c10107981 */
/* 0x000f62000c1e1900 */
/*0cf0*/ IMAD R19, R18, c[0x0][0x180], R25 ; /* 0x0000600012137a24 */
/* 0x000fe200078e0219 */
/*0d00*/ UISETP.NE.AND UP0, UPT, UR10, 0x2, UPT ; /* 0x000000020a00788c */
/* 0x000fcc000bf05270 */
/*0d10*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*0d20*/ FMUL R7, R9, R14 ; /* 0x0000000e09077220 */
/* 0x004fe40000400000 */
/*0d30*/ IMAD.WIDE R14, R19, R2, c[0x0][0x178] ; /* 0x00005e00130e7625 */
/* 0x000fc800078e0202 */
/*0d40*/ FFMA R20, R22, R11, R7 ; /* 0x0000000b16147223 */
/* 0x008fc80000000007 */
/*0d50*/ FFMA R7, R23, R12, R20 ; /* 0x0000000c17077223 */
/* 0x010fc80000000014 */
/*0d60*/ FFMA R7, R8, R16, R7 ; /* 0x0000001008077223 */
/* 0x020fca0000000007 */
/*0d70*/ STG.E [R14.64], R7 ; /* 0x000000070e007986 */
/* 0x0001e2000c10190c */
/*0d80*/ @!P0 BRA 0xef0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0d90*/ IADD3 R24, R24, 0x2, RZ ; /* 0x0000000218187810 */
/* 0x000fca0007ffe0ff */
/*0da0*/ IMAD R12, R24.reuse, c[0x0][0x188], R5 ; /* 0x00006200180c7a24 */
/* 0x040fe400078e0205 */
/*0db0*/ IMAD R7, R24, c[0x0][0x188], R4 ; /* 0x0000620018077a24 */
/* 0x001fe400078e0204 */
/*0dc0*/ IMAD R5, R12, c[0x0][0x18c], R3.reuse ; /* 0x000063000c057a24 */
/* 0x100fe400078e0203 */
/*0dd0*/ IMAD R11, R7, c[0x0][0x18c], R3 ; /* 0x00006300070b7a24 */
/* 0x000fe400078e0203 */
/*0de0*/ IMAD.WIDE R4, R5, R2, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0202 */
/*0df0*/ IMAD R7, R7, c[0x0][0x18c], R6.reuse ; /* 0x0000630007077a24 */
/* 0x100fe400078e0206 */
/*0e00*/ IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe200078e0202 */
/*0e10*/ LDG.E R4, [R4.64] ; /* 0x0000000c04047981 */
/* 0x000ea6000c1e1900 */
/*0e20*/ IMAD R13, R12, c[0x0][0x18c], R6 ; /* 0x000063000c0d7a24 */
/* 0x000fe400078e0206 */
/*0e30*/ IMAD.WIDE R6, R7, R2.reuse, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x080fe200078e0202 */
/*0e40*/ LDG.E R11, [R10.64] ; /* 0x0000000c0a0b7981 */
/* 0x000ee6000c1e1900 */
/*0e50*/ IMAD.WIDE R12, R13, R2, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fc400078e0202 */
/*0e60*/ LDG.E R6, [R6.64] ; /* 0x0000000c06067981 */
/* 0x000f28000c1e1900 */
/*0e70*/ LDG.E R12, [R12.64] ; /* 0x0000000c0c0c7981 */
/* 0x000f62000c1e1900 */
/*0e80*/ IMAD R3, R24, c[0x0][0x180], R25 ; /* 0x0000600018037a24 */
/* 0x000fc800078e0219 */
/*0e90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fc800078e0202 */
/*0ea0*/ FMUL R9, R9, R4 ; /* 0x0000000409097220 */
/* 0x004fc80000400000 */
/*0eb0*/ FFMA R22, R22, R11, R9 ; /* 0x0000000b16167223 */
/* 0x008fc80000000009 */
/*0ec0*/ FFMA R23, R23, R6, R22 ; /* 0x0000000617177223 */
/* 0x010fc80000000016 */
/*0ed0*/ FFMA R23, R8, R12, R23 ; /* 0x0000000c08177223 */
/* 0x020fca0000000017 */
/*0ee0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e4000c10190c */
/*0ef0*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x001fca0000000f00 */
/*0f00*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0f10*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0f20*/ @!P0 BRA 0x120 ; /* 0xfffff1f000008947 */
/* 0x000fea000383ffff */
/*0f30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f40*/ BRA 0xf40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/** Modifed version of knn-CUDA from https://github.com/vincentfpgarcia/kNN-CUDA
* The modifications are
* removed texture memory usage
* removed split query KNN computation
* added feature extraction with bilinear interpolation
*
* Last modified by Christopher B. Choy <chrischoy@ai.stanford.edu> 12/23/2016
*/
// Includes
// Constants used by the program
#define BLOCK_DIM 16
//-----------------------------------------------------------------------------------------------//
// KERNELS //
//-----------------------------------------------------------------------------------------------//
/**
* Computes the distance between two matrix A (reference points) and
* B (query points) containing respectively wA and wB points.
*
* @param A pointer on the matrix A
* @param wA width of the matrix A = number of points in A
* @param B pointer on the matrix B
* @param wB width of the matrix B = number of points in B
* @param dim dimension of points = height of matrices A and B
* @param AB pointer on the matrix containing the wA*wB distances computed
*/
/**
* Gathers k-th smallest distances for each column of the distance matrix in the top.
*
* @param dist distance matrix
* @param ind index matrix
* @param width width of the distance matrix and of the index matrix
* @param height height of the distance matrix and of the index matrix
* @param k number of neighbors to consider
*/
/**
* Computes the square root of the first line (width-th first element)
* of the distance matrix.
*
* @param dist distance matrix
* @param width width of the distance matrix
* @param k number of neighbors to consider
*/
//-----------------------------------------------------------------------------------------------//
// K-th NEAREST NEIGHBORS //
//-----------------------------------------------------------------------------------------------//
/**
* Prints the error message return during the memory allocation.
*
* @param error error value return by the memory allocation function
* @param memorySize size of memory tried to be allocated
*/
__global__ void extract_with_interpolation( int nthreads, float *data, float *n_xy_coords, float *extracted_data, int n_max_coord, int channels, int height, int width) {
int x0, x1, y0, y1, nc;
float wx0, wx1, wy0, wy1;
int n, nd;
float x, y;
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < (nthreads);
index += blockDim.x * gridDim.x) {
n = (index / n_max_coord);
nd = n * n_max_coord * channels;
x = n_xy_coords[index * 2];
y = n_xy_coords[index * 2 + 1];
x0 = static_cast<int>(floor(x));
x1 = x0 + 1;
y0 = static_cast<int>(floor(y));
y1 = y0 + 1;
x0 = x0 <= 0 ? 0 : (x0 >= (width - 1) ? (width - 1) : x0);
y0 = y0 <= 0 ? 0 : (y0 >= (height - 1) ? (height - 1) : y0);
x1 = x1 <= 0 ? 0 : (x1 >= (width - 1) ? (width - 1) : x1);
y1 = y1 <= 0 ? 0 : (y1 >= (height - 1) ? (height - 1) : y1);
wx0 = static_cast<float>(x1) - x;
wx1 = x - x0;
wy0 = static_cast<float>(y1) - y;
wy1 = y - y0;
if(x0 == x1){ wx0 = 1; wx1 = 0; }
if(y0 == y1){ wy0 = 1; wy1 = 0; }
for(int c=0; c < channels; c++) {
nc = (n * channels + c) * height;
// extracted_data[index * channels + c] = wy0 * wx0 * data[(nc + y0) * width + x0]
// extracted_data[nd + index % n_max_coord + n_max_coord * c] = index;
extracted_data[nd + index % n_max_coord + n_max_coord * c] = wy0 * wx0 * data[(nc + y0) * width + x0]
+ wy1 * wx0 * data[(nc + y1) * width + x0]
+ wy0 * wx1 * data[(nc + y0) * width + x1]
+ wy1 * wx1 * data[(nc + y1) * width + x1];
}
}
} | .file "tmpxft_001bbba2_00000000-6_extract_with_interpolation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii
.type _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii, @function
_Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26extract_with_interpolationiPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii, .-_Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii
.globl _Z26extract_with_interpolationiPfS_S_iiii
.type _Z26extract_with_interpolationiPfS_S_iiii, @function
_Z26extract_with_interpolationiPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26extract_with_interpolationiPfS_S_iiii, .-_Z26extract_with_interpolationiPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26extract_with_interpolationiPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26extract_with_interpolationiPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/** Modifed version of knn-CUDA from https://github.com/vincentfpgarcia/kNN-CUDA
* The modifications are
* removed texture memory usage
* removed split query KNN computation
* added feature extraction with bilinear interpolation
*
* Last modified by Christopher B. Choy <chrischoy@ai.stanford.edu> 12/23/2016
*/
// Includes
// Constants used by the program
#define BLOCK_DIM 16
//-----------------------------------------------------------------------------------------------//
// KERNELS //
//-----------------------------------------------------------------------------------------------//
/**
* Computes the distance between two matrix A (reference points) and
* B (query points) containing respectively wA and wB points.
*
* @param A pointer on the matrix A
* @param wA width of the matrix A = number of points in A
* @param B pointer on the matrix B
* @param wB width of the matrix B = number of points in B
* @param dim dimension of points = height of matrices A and B
* @param AB pointer on the matrix containing the wA*wB distances computed
*/
/**
* Gathers k-th smallest distances for each column of the distance matrix in the top.
*
* @param dist distance matrix
* @param ind index matrix
* @param width width of the distance matrix and of the index matrix
* @param height height of the distance matrix and of the index matrix
* @param k number of neighbors to consider
*/
/**
* Computes the square root of the first line (width-th first element)
* of the distance matrix.
*
* @param dist distance matrix
* @param width width of the distance matrix
* @param k number of neighbors to consider
*/
//-----------------------------------------------------------------------------------------------//
// K-th NEAREST NEIGHBORS //
//-----------------------------------------------------------------------------------------------//
/**
* Prints the error message return during the memory allocation.
*
* @param error error value return by the memory allocation function
* @param memorySize size of memory tried to be allocated
*/
__global__ void extract_with_interpolation( int nthreads, float *data, float *n_xy_coords, float *extracted_data, int n_max_coord, int channels, int height, int width) {
int x0, x1, y0, y1, nc;
float wx0, wx1, wy0, wy1;
int n, nd;
float x, y;
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < (nthreads);
index += blockDim.x * gridDim.x) {
n = (index / n_max_coord);
nd = n * n_max_coord * channels;
x = n_xy_coords[index * 2];
y = n_xy_coords[index * 2 + 1];
x0 = static_cast<int>(floor(x));
x1 = x0 + 1;
y0 = static_cast<int>(floor(y));
y1 = y0 + 1;
x0 = x0 <= 0 ? 0 : (x0 >= (width - 1) ? (width - 1) : x0);
y0 = y0 <= 0 ? 0 : (y0 >= (height - 1) ? (height - 1) : y0);
x1 = x1 <= 0 ? 0 : (x1 >= (width - 1) ? (width - 1) : x1);
y1 = y1 <= 0 ? 0 : (y1 >= (height - 1) ? (height - 1) : y1);
wx0 = static_cast<float>(x1) - x;
wx1 = x - x0;
wy0 = static_cast<float>(y1) - y;
wy1 = y - y0;
if(x0 == x1){ wx0 = 1; wx1 = 0; }
if(y0 == y1){ wy0 = 1; wy1 = 0; }
for(int c=0; c < channels; c++) {
nc = (n * channels + c) * height;
// extracted_data[index * channels + c] = wy0 * wx0 * data[(nc + y0) * width + x0]
// extracted_data[nd + index % n_max_coord + n_max_coord * c] = index;
extracted_data[nd + index % n_max_coord + n_max_coord * c] = wy0 * wx0 * data[(nc + y0) * width + x0]
+ wy1 * wx0 * data[(nc + y1) * width + x0]
+ wy0 * wx1 * data[(nc + y0) * width + x1]
+ wy1 * wx1 * data[(nc + y1) * width + x1];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/** Modifed version of knn-CUDA from https://github.com/vincentfpgarcia/kNN-CUDA
* The modifications are
* removed texture memory usage
* removed split query KNN computation
* added feature extraction with bilinear interpolation
*
* Last modified by Christopher B. Choy <chrischoy@ai.stanford.edu> 12/23/2016
*/
// Includes
// Constants used by the program
#define BLOCK_DIM 16
//-----------------------------------------------------------------------------------------------//
// KERNELS //
//-----------------------------------------------------------------------------------------------//
/**
* Computes the distance between two matrix A (reference points) and
* B (query points) containing respectively wA and wB points.
*
* @param A pointer on the matrix A
* @param wA width of the matrix A = number of points in A
* @param B pointer on the matrix B
* @param wB width of the matrix B = number of points in B
* @param dim dimension of points = height of matrices A and B
* @param AB pointer on the matrix containing the wA*wB distances computed
*/
/**
* Gathers k-th smallest distances for each column of the distance matrix in the top.
*
* @param dist distance matrix
* @param ind index matrix
* @param width width of the distance matrix and of the index matrix
* @param height height of the distance matrix and of the index matrix
* @param k number of neighbors to consider
*/
/**
* Computes the square root of the first line (width-th first element)
* of the distance matrix.
*
* @param dist distance matrix
* @param width width of the distance matrix
* @param k number of neighbors to consider
*/
//-----------------------------------------------------------------------------------------------//
// K-th NEAREST NEIGHBORS //
//-----------------------------------------------------------------------------------------------//
/**
* Prints the error message return during the memory allocation.
*
* @param error error value return by the memory allocation function
* @param memorySize size of memory tried to be allocated
*/
__global__ void extract_with_interpolation( int nthreads, float *data, float *n_xy_coords, float *extracted_data, int n_max_coord, int channels, int height, int width) {
int x0, x1, y0, y1, nc;
float wx0, wx1, wy0, wy1;
int n, nd;
float x, y;
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < (nthreads);
index += blockDim.x * gridDim.x) {
n = (index / n_max_coord);
nd = n * n_max_coord * channels;
x = n_xy_coords[index * 2];
y = n_xy_coords[index * 2 + 1];
x0 = static_cast<int>(floor(x));
x1 = x0 + 1;
y0 = static_cast<int>(floor(y));
y1 = y0 + 1;
x0 = x0 <= 0 ? 0 : (x0 >= (width - 1) ? (width - 1) : x0);
y0 = y0 <= 0 ? 0 : (y0 >= (height - 1) ? (height - 1) : y0);
x1 = x1 <= 0 ? 0 : (x1 >= (width - 1) ? (width - 1) : x1);
y1 = y1 <= 0 ? 0 : (y1 >= (height - 1) ? (height - 1) : y1);
wx0 = static_cast<float>(x1) - x;
wx1 = x - x0;
wy0 = static_cast<float>(y1) - y;
wy1 = y - y0;
if(x0 == x1){ wx0 = 1; wx1 = 0; }
if(y0 == y1){ wy0 = 1; wy1 = 0; }
for(int c=0; c < channels; c++) {
nc = (n * channels + c) * height;
// extracted_data[index * channels + c] = wy0 * wx0 * data[(nc + y0) * width + x0]
// extracted_data[nd + index % n_max_coord + n_max_coord * c] = index;
extracted_data[nd + index % n_max_coord + n_max_coord * c] = wy0 * wx0 * data[(nc + y0) * width + x0]
+ wy1 * wx0 * data[(nc + y1) * width + x0]
+ wy0 * wx1 * data[(nc + y0) * width + x1]
+ wy1 * wx1 * data[(nc + y1) * width + x1];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/** Modifed version of knn-CUDA from https://github.com/vincentfpgarcia/kNN-CUDA
* The modifications are
* removed texture memory usage
* removed split query KNN computation
* added feature extraction with bilinear interpolation
*
* Last modified by Christopher B. Choy <chrischoy@ai.stanford.edu> 12/23/2016
*/
// Includes
// Constants used by the program
#define BLOCK_DIM 16
//-----------------------------------------------------------------------------------------------//
// KERNELS //
//-----------------------------------------------------------------------------------------------//
/**
* Computes the distance between two matrix A (reference points) and
* B (query points) containing respectively wA and wB points.
*
* @param A pointer on the matrix A
* @param wA width of the matrix A = number of points in A
* @param B pointer on the matrix B
* @param wB width of the matrix B = number of points in B
* @param dim dimension of points = height of matrices A and B
* @param AB pointer on the matrix containing the wA*wB distances computed
*/
/**
* Gathers k-th smallest distances for each column of the distance matrix in the top.
*
* @param dist distance matrix
* @param ind index matrix
* @param width width of the distance matrix and of the index matrix
* @param height height of the distance matrix and of the index matrix
* @param k number of neighbors to consider
*/
/**
* Computes the square root of the first line (width-th first element)
* of the distance matrix.
*
* @param dist distance matrix
* @param width width of the distance matrix
* @param k number of neighbors to consider
*/
//-----------------------------------------------------------------------------------------------//
// K-th NEAREST NEIGHBORS //
//-----------------------------------------------------------------------------------------------//
/**
* Prints the error message return during the memory allocation.
*
* @param error error value return by the memory allocation function
* @param memorySize size of memory tried to be allocated
*/
__global__ void extract_with_interpolation( int nthreads, float *data, float *n_xy_coords, float *extracted_data, int n_max_coord, int channels, int height, int width) {
int x0, x1, y0, y1, nc;
float wx0, wx1, wy0, wy1;
int n, nd;
float x, y;
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < (nthreads);
index += blockDim.x * gridDim.x) {
n = (index / n_max_coord);
nd = n * n_max_coord * channels;
x = n_xy_coords[index * 2];
y = n_xy_coords[index * 2 + 1];
x0 = static_cast<int>(floor(x));
x1 = x0 + 1;
y0 = static_cast<int>(floor(y));
y1 = y0 + 1;
x0 = x0 <= 0 ? 0 : (x0 >= (width - 1) ? (width - 1) : x0);
y0 = y0 <= 0 ? 0 : (y0 >= (height - 1) ? (height - 1) : y0);
x1 = x1 <= 0 ? 0 : (x1 >= (width - 1) ? (width - 1) : x1);
y1 = y1 <= 0 ? 0 : (y1 >= (height - 1) ? (height - 1) : y1);
wx0 = static_cast<float>(x1) - x;
wx1 = x - x0;
wy0 = static_cast<float>(y1) - y;
wy1 = y - y0;
if(x0 == x1){ wx0 = 1; wx1 = 0; }
if(y0 == y1){ wy0 = 1; wy1 = 0; }
for(int c=0; c < channels; c++) {
nc = (n * channels + c) * height;
// extracted_data[index * channels + c] = wy0 * wx0 * data[(nc + y0) * width + x0]
// extracted_data[nd + index % n_max_coord + n_max_coord * c] = index;
extracted_data[nd + index % n_max_coord + n_max_coord * c] = wy0 * wx0 * data[(nc + y0) * width + x0]
+ wy1 * wx0 * data[(nc + y1) * width + x0]
+ wy0 * wx1 * data[(nc + y0) * width + x1]
+ wy1 * wx1 * data[(nc + y1) * width + x1];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26extract_with_interpolationiPfS_S_iiii
.globl _Z26extract_with_interpolationiPfS_S_iiii
.p2align 8
.type _Z26extract_with_interpolationiPfS_S_iiii,@function
_Z26extract_with_interpolationiPfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s14, s[0:1], 0x0
s_add_u32 s12, s0, 48
s_addc_u32 s13, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s19, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s14, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s13, s[12:13], 0x0
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s3, -1
s_add_i32 s15, s2, -1
s_cmp_gt_i32 s11, 0
s_mul_i32 s13, s13, s19
s_cselect_b32 s16, -1, 0
s_ashr_i32 s17, s10, 31
s_mul_i32 s19, s2, s11
s_add_i32 s0, s10, s17
s_mul_i32 s2, s3, s2
s_xor_b32 s18, s0, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s18
s_sub_i32 s0, 0, s18
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s0, v0
s_add_i32 s0, s11, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s20, s10, s0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s14, v1
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_2
v_lshlrev_b32_e32 v2, 1, v1
s_mov_b32 s21, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_ashrrev_i32_e32 v5, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v5
v_xor_b32_e32 v7, v2, v5
v_xor_b32_e32 v5, s17, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, v0, 0
v_mul_lo_u32 v2, v3, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v7, v2
v_subrev_nc_u32_e32 v8, s18, v2
v_cmp_le_u32_e32 vcc_lo, s18, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v8 :: v_dual_add_nc_u32 v7, 1, v3
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s18, v2
v_add_nc_u32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v7, vcc_lo
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v2, v5
s_waitcnt vmcnt(1)
v_floor_f32_e32 v3, v6
s_waitcnt vmcnt(0)
v_floor_f32_e32 v7, v4
v_cvt_i32_f32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v7
v_mul_lo_u32 v7, s19, v5
v_min_i32_e32 v8, s1, v2
v_cmp_lt_i32_e32 vcc_lo, 0, v2
v_add_nc_u32_e32 v9, 1, v2
v_min_i32_e32 v11, s15, v3
v_add_nc_u32_e32 v10, 1, v3
v_cndmask_b32_e32 v12, 0, v8, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v3
v_min_i32_e32 v8, s1, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, s15, v10
v_cndmask_b32_e32 v9, 0, v11, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cvt_f32_i32_e32 v11, v12
v_cvt_f32_i32_e32 v2, v9
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_sub_f32 v2, v4, v2 :: v_dual_add_nc_u32 v13, v9, v7
v_dual_cndmask_b32 v3, 0, v10 :: v_dual_sub_f32 v10, v6, v11
v_cvt_f32_i32_e32 v11, v8
v_cmp_eq_u32_e32 vcc_lo, v12, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v14, v3
v_cmp_eq_u32_e64 s0, v9, v3
v_sub_f32_e32 v6, v11, v6
v_mul_lo_u32 v11, s3, v13
v_cndmask_b32_e64 v10, v10, 0, vcc_lo
v_sub_f32_e32 v13, v14, v4
v_cndmask_b32_e64 v9, v2, 0, s0
v_add_nc_u32_e32 v7, v3, v7
v_mad_u64_u32 v[2:3], null, s20, v5, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v13, 1.0, s0
v_add_nc_u32_e32 v5, v12, v11
v_cndmask_b32_e64 v14, v6, 1.0, vcc_lo
v_add_nc_u32_e32 v4, v8, v11
s_mov_b32 s0, 0
v_mul_f32_e32 v6, v9, v14
v_mul_lo_u32 v15, s3, v7
v_mul_f32_e32 v7, v10, v9
v_mul_f32_e32 v9, v14, v3
v_mul_f32_e32 v10, v10, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v8, v8, v15
v_add_nc_u32_e32 v11, v12, v15
.LBB0_5:
v_add_nc_u32_e32 v12, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v14, s0, v11
v_add_nc_u32_e32 v16, s0, v4
v_add_nc_u32_e32 v18, s0, v8
s_add_i32 s21, s21, -1
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v19, 31, v18
s_add_i32 s0, s0, s2
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_lshlrev_b64 v[16:17], 2, v[16:17]
s_cmp_eq_u32 s21, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
s_clause 0x1
global_load_b32 v20, v[12:13], off
global_load_b32 v3, v[14:15], off
v_lshlrev_b64 v[12:13], 2, v[18:19]
v_add_co_u32 v14, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_clause 0x1
global_load_b32 v14, v[14:15], off
global_load_b32 v15, v[12:13], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v16, v6, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v16, v9, v20
v_lshlrev_b64 v[12:13], 2, v[2:3]
v_add_nc_u32_e32 v2, s10, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v16, v10, v14
v_add_co_u32 v12, vcc_lo, s8, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v16, v7, v15
global_store_b32 v[12:13], v16, off
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26extract_with_interpolationiPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26extract_with_interpolationiPfS_S_iiii, .Lfunc_end0-_Z26extract_with_interpolationiPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26extract_with_interpolationiPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z26extract_with_interpolationiPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/** Modifed version of knn-CUDA from https://github.com/vincentfpgarcia/kNN-CUDA
* The modifications are
* removed texture memory usage
* removed split query KNN computation
* added feature extraction with bilinear interpolation
*
* Last modified by Christopher B. Choy <chrischoy@ai.stanford.edu> 12/23/2016
*/
// Includes
// Constants used by the program
#define BLOCK_DIM 16
//-----------------------------------------------------------------------------------------------//
// KERNELS //
//-----------------------------------------------------------------------------------------------//
/**
* Computes the distance between two matrix A (reference points) and
* B (query points) containing respectively wA and wB points.
*
* @param A pointer on the matrix A
* @param wA width of the matrix A = number of points in A
* @param B pointer on the matrix B
* @param wB width of the matrix B = number of points in B
* @param dim dimension of points = height of matrices A and B
* @param AB pointer on the matrix containing the wA*wB distances computed
*/
/**
* Gathers k-th smallest distances for each column of the distance matrix in the top.
*
* @param dist distance matrix
* @param ind index matrix
* @param width width of the distance matrix and of the index matrix
* @param height height of the distance matrix and of the index matrix
* @param k number of neighbors to consider
*/
/**
* Computes the square root of the first line (width-th first element)
* of the distance matrix.
*
* @param dist distance matrix
* @param width width of the distance matrix
* @param k number of neighbors to consider
*/
//-----------------------------------------------------------------------------------------------//
// K-th NEAREST NEIGHBORS //
//-----------------------------------------------------------------------------------------------//
/**
* Prints the error message return during the memory allocation.
*
* @param error error value return by the memory allocation function
* @param memorySize size of memory tried to be allocated
*/
__global__ void extract_with_interpolation( int nthreads, float *data, float *n_xy_coords, float *extracted_data, int n_max_coord, int channels, int height, int width) {
int x0, x1, y0, y1, nc;
float wx0, wx1, wy0, wy1;
int n, nd;
float x, y;
for (int index = blockIdx.x * blockDim.x + threadIdx.x;
index < (nthreads);
index += blockDim.x * gridDim.x) {
n = (index / n_max_coord);
nd = n * n_max_coord * channels;
x = n_xy_coords[index * 2];
y = n_xy_coords[index * 2 + 1];
x0 = static_cast<int>(floor(x));
x1 = x0 + 1;
y0 = static_cast<int>(floor(y));
y1 = y0 + 1;
x0 = x0 <= 0 ? 0 : (x0 >= (width - 1) ? (width - 1) : x0);
y0 = y0 <= 0 ? 0 : (y0 >= (height - 1) ? (height - 1) : y0);
x1 = x1 <= 0 ? 0 : (x1 >= (width - 1) ? (width - 1) : x1);
y1 = y1 <= 0 ? 0 : (y1 >= (height - 1) ? (height - 1) : y1);
wx0 = static_cast<float>(x1) - x;
wx1 = x - x0;
wy0 = static_cast<float>(y1) - y;
wy1 = y - y0;
if(x0 == x1){ wx0 = 1; wx1 = 0; }
if(y0 == y1){ wy0 = 1; wy1 = 0; }
for(int c=0; c < channels; c++) {
nc = (n * channels + c) * height;
// extracted_data[index * channels + c] = wy0 * wx0 * data[(nc + y0) * width + x0]
// extracted_data[nd + index % n_max_coord + n_max_coord * c] = index;
extracted_data[nd + index % n_max_coord + n_max_coord * c] = wy0 * wx0 * data[(nc + y0) * width + x0]
+ wy1 * wx0 * data[(nc + y1) * width + x0]
+ wy0 * wx1 * data[(nc + y0) * width + x1]
+ wy1 * wx1 * data[(nc + y1) * width + x1];
}
}
} | .text
.file "extract_with_interpolation.hip"
.globl _Z41__device_stub__extract_with_interpolationiPfS_S_iiii # -- Begin function _Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.p2align 4, 0x90
.type _Z41__device_stub__extract_with_interpolationiPfS_S_iiii,@function
_Z41__device_stub__extract_with_interpolationiPfS_S_iiii: # @_Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26extract_with_interpolationiPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__extract_with_interpolationiPfS_S_iiii, .Lfunc_end0-_Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26extract_with_interpolationiPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26extract_with_interpolationiPfS_S_iiii,@object # @_Z26extract_with_interpolationiPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z26extract_with_interpolationiPfS_S_iiii
.p2align 3, 0x0
_Z26extract_with_interpolationiPfS_S_iiii:
.quad _Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.size _Z26extract_with_interpolationiPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26extract_with_interpolationiPfS_S_iiii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26extract_with_interpolationiPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bbba2_00000000-6_extract_with_interpolation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii
.type _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii, @function
_Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26extract_with_interpolationiPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii, .-_Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii
.globl _Z26extract_with_interpolationiPfS_S_iiii
.type _Z26extract_with_interpolationiPfS_S_iiii, @function
_Z26extract_with_interpolationiPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26extract_with_interpolationiPfS_S_iiiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26extract_with_interpolationiPfS_S_iiii, .-_Z26extract_with_interpolationiPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26extract_with_interpolationiPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26extract_with_interpolationiPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "extract_with_interpolation.hip"
.globl _Z41__device_stub__extract_with_interpolationiPfS_S_iiii # -- Begin function _Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.p2align 4, 0x90
.type _Z41__device_stub__extract_with_interpolationiPfS_S_iiii,@function
_Z41__device_stub__extract_with_interpolationiPfS_S_iiii: # @_Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26extract_with_interpolationiPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__extract_with_interpolationiPfS_S_iiii, .Lfunc_end0-_Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26extract_with_interpolationiPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26extract_with_interpolationiPfS_S_iiii,@object # @_Z26extract_with_interpolationiPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z26extract_with_interpolationiPfS_S_iiii
.p2align 3, 0x0
_Z26extract_with_interpolationiPfS_S_iiii:
.quad _Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.size _Z26extract_with_interpolationiPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26extract_with_interpolationiPfS_S_iiii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__extract_with_interpolationiPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26extract_with_interpolationiPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <iostream>
#include <time.h>
using namespace std;
#define BLOCK_SIZE 256
#define SEED 1337
#define ARR_LENGTH 5000
__global__ void sum_cud(float * in, float * out, int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int th_num = threadIdx.x;
unsigned int pointer = blockIdx.x * blockDim.x;
if (pointer + th_num < len)
sum[th_num] = in[pointer + th_num];
else
sum[th_num] = 0;
for (unsigned int stride = blockDim.x/2; stride >= 1; stride >>= 1) {
if (th_num < stride)
sum[th_num] += sum[th_num+stride];
__syncthreads();
}
if (th_num == 0)
out[blockIdx.x] = sum[0];
}
float randInRange(float min, float max)
{
return min + (float) (rand() / (double) (RAND_MAX + 1) * (max - min + 1));
}
int main(int argc, char ** argv) {
srand(SEED);
float * input;
float * output;
float * d_input;
float * d_output;
int lenInput = ARR_LENGTH;
int lenOutput;
input = (float*) malloc(lenInput * sizeof(float));
for (int i = 0; i < lenInput; ++i)
{
input[i] = randInRange(0.0, 10.0);
}
clock_t Time;
Time = clock();
float sum = 0.0;
for (int i = 0; i < lenInput; i++) {
sum += input[i];
}
cout << "CPU result: " << sum << endl;
Time = clock() - Time;
float Time_ = (float) Time / CLOCKS_PER_SEC;
cout << "CPU time is: " << Time_ << endl;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float time_;
cudaEventRecord(start, 0);
do
{
lenOutput = lenInput / (BLOCK_SIZE);
if (lenInput % (BLOCK_SIZE)) {
lenOutput++;
}
output = (float*) malloc(lenOutput * sizeof(float));
cudaMalloc(&d_input, sizeof(float) * lenInput);
cudaMalloc(&d_output, sizeof(float) * lenInput);
cudaMemcpy(d_input, input, sizeof(float) * lenInput, cudaMemcpyHostToDevice);
dim3 dimGrid(lenOutput);
dim3 dimBlock(BLOCK_SIZE);
sum_cud<<<dimGrid, dimBlock>>>(d_input, d_output, lenInput);
cudaMemcpy(output, d_output, sizeof(float) * lenOutput, cudaMemcpyDeviceToHost);
input = output;
lenInput = lenOutput;
} while (lenOutput > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_, start, stop);
printf("GPU ime is: %f\n", time_/1000);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cout << "Cuda result: " << output[0] << endl;
cudaFree(d_input);
cudaFree(d_output);
free(input);
free(output);
return 0;
} | code for sm_80
Function : _Z7sum_cudPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26070 */
/*0060*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*0070*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fcc00078e0003 */
/*0080*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000602029981 */
/* 0x000ea2000c1e1900 */
/*0090*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00c0*/ @P1 STS [R7.X4], RZ ; /* 0x000000ff07001388 */
/* 0x0001ea0000004800 */
/*00d0*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*00e0*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0041d80000004800 */
/*00f0*/ @!P2 BRA 0x1c0 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x000fe200000006ff */
/*0110*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0130*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x001fe200078e10ff */
/*0140*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0150*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0160*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0170*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0180*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01b0*/ @P1 BRA 0x120 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e0003 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <iostream>
#include <time.h>
using namespace std;
#define BLOCK_SIZE 256
#define SEED 1337
#define ARR_LENGTH 5000
__global__ void sum_cud(float * in, float * out, int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int th_num = threadIdx.x;
unsigned int pointer = blockIdx.x * blockDim.x;
if (pointer + th_num < len)
sum[th_num] = in[pointer + th_num];
else
sum[th_num] = 0;
for (unsigned int stride = blockDim.x/2; stride >= 1; stride >>= 1) {
if (th_num < stride)
sum[th_num] += sum[th_num+stride];
__syncthreads();
}
if (th_num == 0)
out[blockIdx.x] = sum[0];
}
float randInRange(float min, float max)
{
return min + (float) (rand() / (double) (RAND_MAX + 1) * (max - min + 1));
}
int main(int argc, char ** argv) {
srand(SEED);
float * input;
float * output;
float * d_input;
float * d_output;
int lenInput = ARR_LENGTH;
int lenOutput;
input = (float*) malloc(lenInput * sizeof(float));
for (int i = 0; i < lenInput; ++i)
{
input[i] = randInRange(0.0, 10.0);
}
clock_t Time;
Time = clock();
float sum = 0.0;
for (int i = 0; i < lenInput; i++) {
sum += input[i];
}
cout << "CPU result: " << sum << endl;
Time = clock() - Time;
float Time_ = (float) Time / CLOCKS_PER_SEC;
cout << "CPU time is: " << Time_ << endl;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float time_;
cudaEventRecord(start, 0);
do
{
lenOutput = lenInput / (BLOCK_SIZE);
if (lenInput % (BLOCK_SIZE)) {
lenOutput++;
}
output = (float*) malloc(lenOutput * sizeof(float));
cudaMalloc(&d_input, sizeof(float) * lenInput);
cudaMalloc(&d_output, sizeof(float) * lenInput);
cudaMemcpy(d_input, input, sizeof(float) * lenInput, cudaMemcpyHostToDevice);
dim3 dimGrid(lenOutput);
dim3 dimBlock(BLOCK_SIZE);
sum_cud<<<dimGrid, dimBlock>>>(d_input, d_output, lenInput);
cudaMemcpy(output, d_output, sizeof(float) * lenOutput, cudaMemcpyDeviceToHost);
input = output;
lenInput = lenOutput;
} while (lenOutput > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_, start, stop);
printf("GPU ime is: %f\n", time_/1000);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cout << "Cuda result: " << output[0] << endl;
cudaFree(d_input);
cudaFree(d_output);
free(input);
free(output);
return 0;
} | .file "tmpxft_0016c85e_00000000-6_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11randInRangeff
.type _Z11randInRangeff, @function
_Z11randInRangeff:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm2
subss %xmm2, %xmm1
addss .LC1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
addss %xmm2, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z11randInRangeff, .-_Z11randInRangeff
.globl _Z29__device_stub__Z7sum_cudPfS_iPfS_i
.type _Z29__device_stub__Z7sum_cudPfS_iPfS_i, @function
_Z29__device_stub__Z7sum_cudPfS_iPfS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sum_cudPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z7sum_cudPfS_iPfS_i, .-_Z29__device_stub__Z7sum_cudPfS_iPfS_i
.globl _Z7sum_cudPfS_i
.type _Z7sum_cudPfS_i, @function
_Z7sum_cudPfS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sum_cudPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7sum_cudPfS_i, .-_Z7sum_cudPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU result: "
.LC6:
.string "CPU time is: "
.LC8:
.string "GPU ime is: %f\n"
.LC9:
.string "Cuda result: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1337, %edi
call srand@PLT
movl $20000, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rbx
leaq 20000(%rax), %r12
movq %rax, %rbp
.L14:
movss .LC3(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z11randInRangeff
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L14
call clock@PLT
movq %rax, %rbp
movl $0x00000000, 8(%rsp)
.L15:
movss 8(%rsp), %xmm2
addss (%rbx), %xmm2
movss %xmm2, 8(%rsp)
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, 8(%rsp)
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $5000, %ebp
leaq 16(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L18
.L17:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $1, %ebx
jle .L24
movl %ebx, %ebp
movq %r13, %r15
.L18:
leal 255(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $8, %ebx
cmpb $1, %bpl
sbbl $-1, %ebx
movslq %ebx, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movslq %ebp, %r12
salq $2, %r12
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z7sum_cudPfS_iPfS_i
jmp .L17
.L24:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 60(%rsp), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z7sum_cudPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sum_cudPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1107296256
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC3:
.long 1092616192
.align 4
.LC5:
.long 1232348160
.align 4
.LC7:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <iostream>
#include <time.h>
using namespace std;
#define BLOCK_SIZE 256
#define SEED 1337
#define ARR_LENGTH 5000
__global__ void sum_cud(float * in, float * out, int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int th_num = threadIdx.x;
unsigned int pointer = blockIdx.x * blockDim.x;
if (pointer + th_num < len)
sum[th_num] = in[pointer + th_num];
else
sum[th_num] = 0;
for (unsigned int stride = blockDim.x/2; stride >= 1; stride >>= 1) {
if (th_num < stride)
sum[th_num] += sum[th_num+stride];
__syncthreads();
}
if (th_num == 0)
out[blockIdx.x] = sum[0];
}
float randInRange(float min, float max)
{
return min + (float) (rand() / (double) (RAND_MAX + 1) * (max - min + 1));
}
int main(int argc, char ** argv) {
srand(SEED);
float * input;
float * output;
float * d_input;
float * d_output;
int lenInput = ARR_LENGTH;
int lenOutput;
input = (float*) malloc(lenInput * sizeof(float));
for (int i = 0; i < lenInput; ++i)
{
input[i] = randInRange(0.0, 10.0);
}
clock_t Time;
Time = clock();
float sum = 0.0;
for (int i = 0; i < lenInput; i++) {
sum += input[i];
}
cout << "CPU result: " << sum << endl;
Time = clock() - Time;
float Time_ = (float) Time / CLOCKS_PER_SEC;
cout << "CPU time is: " << Time_ << endl;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float time_;
cudaEventRecord(start, 0);
do
{
lenOutput = lenInput / (BLOCK_SIZE);
if (lenInput % (BLOCK_SIZE)) {
lenOutput++;
}
output = (float*) malloc(lenOutput * sizeof(float));
cudaMalloc(&d_input, sizeof(float) * lenInput);
cudaMalloc(&d_output, sizeof(float) * lenInput);
cudaMemcpy(d_input, input, sizeof(float) * lenInput, cudaMemcpyHostToDevice);
dim3 dimGrid(lenOutput);
dim3 dimBlock(BLOCK_SIZE);
sum_cud<<<dimGrid, dimBlock>>>(d_input, d_output, lenInput);
cudaMemcpy(output, d_output, sizeof(float) * lenOutput, cudaMemcpyDeviceToHost);
input = output;
lenInput = lenOutput;
} while (lenOutput > 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_, start, stop);
printf("GPU ime is: %f\n", time_/1000);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cout << "Cuda result: " << output[0] << endl;
cudaFree(d_input);
cudaFree(d_output);
free(input);
free(output);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <iostream>
#include <time.h>
using namespace std;
#define BLOCK_SIZE 256
#define SEED 1337
#define ARR_LENGTH 5000
__global__ void sum_cud(float * in, float * out, int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int th_num = threadIdx.x;
unsigned int pointer = blockIdx.x * blockDim.x;
if (pointer + th_num < len)
sum[th_num] = in[pointer + th_num];
else
sum[th_num] = 0;
for (unsigned int stride = blockDim.x/2; stride >= 1; stride >>= 1) {
if (th_num < stride)
sum[th_num] += sum[th_num+stride];
__syncthreads();
}
if (th_num == 0)
out[blockIdx.x] = sum[0];
}
float randInRange(float min, float max)
{
return min + (float) (rand() / (double) (RAND_MAX + 1) * (max - min + 1));
}
int main(int argc, char ** argv) {
srand(SEED);
float * input;
float * output;
float * d_input;
float * d_output;
int lenInput = ARR_LENGTH;
int lenOutput;
input = (float*) malloc(lenInput * sizeof(float));
for (int i = 0; i < lenInput; ++i)
{
input[i] = randInRange(0.0, 10.0);
}
clock_t Time;
Time = clock();
float sum = 0.0;
for (int i = 0; i < lenInput; i++) {
sum += input[i];
}
cout << "CPU result: " << sum << endl;
Time = clock() - Time;
float Time_ = (float) Time / CLOCKS_PER_SEC;
cout << "CPU time is: " << Time_ << endl;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float time_;
hipEventRecord(start, 0);
do
{
lenOutput = lenInput / (BLOCK_SIZE);
if (lenInput % (BLOCK_SIZE)) {
lenOutput++;
}
output = (float*) malloc(lenOutput * sizeof(float));
hipMalloc(&d_input, sizeof(float) * lenInput);
hipMalloc(&d_output, sizeof(float) * lenInput);
hipMemcpy(d_input, input, sizeof(float) * lenInput, hipMemcpyHostToDevice);
dim3 dimGrid(lenOutput);
dim3 dimBlock(BLOCK_SIZE);
sum_cud<<<dimGrid, dimBlock>>>(d_input, d_output, lenInput);
hipMemcpy(output, d_output, sizeof(float) * lenOutput, hipMemcpyDeviceToHost);
input = output;
lenInput = lenOutput;
} while (lenOutput > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_, start, stop);
printf("GPU ime is: %f\n", time_/1000);
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
cout << "Cuda result: " << output[0] << endl;
hipFree(d_input);
hipFree(d_output);
free(input);
free(output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <iostream>
#include <time.h>
using namespace std;
#define BLOCK_SIZE 256
#define SEED 1337
#define ARR_LENGTH 5000
__global__ void sum_cud(float * in, float * out, int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int th_num = threadIdx.x;
unsigned int pointer = blockIdx.x * blockDim.x;
if (pointer + th_num < len)
sum[th_num] = in[pointer + th_num];
else
sum[th_num] = 0;
for (unsigned int stride = blockDim.x/2; stride >= 1; stride >>= 1) {
if (th_num < stride)
sum[th_num] += sum[th_num+stride];
__syncthreads();
}
if (th_num == 0)
out[blockIdx.x] = sum[0];
}
float randInRange(float min, float max)
{
return min + (float) (rand() / (double) (RAND_MAX + 1) * (max - min + 1));
}
int main(int argc, char ** argv) {
srand(SEED);
float * input;
float * output;
float * d_input;
float * d_output;
int lenInput = ARR_LENGTH;
int lenOutput;
input = (float*) malloc(lenInput * sizeof(float));
for (int i = 0; i < lenInput; ++i)
{
input[i] = randInRange(0.0, 10.0);
}
clock_t Time;
Time = clock();
float sum = 0.0;
for (int i = 0; i < lenInput; i++) {
sum += input[i];
}
cout << "CPU result: " << sum << endl;
Time = clock() - Time;
float Time_ = (float) Time / CLOCKS_PER_SEC;
cout << "CPU time is: " << Time_ << endl;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float time_;
hipEventRecord(start, 0);
do
{
lenOutput = lenInput / (BLOCK_SIZE);
if (lenInput % (BLOCK_SIZE)) {
lenOutput++;
}
output = (float*) malloc(lenOutput * sizeof(float));
hipMalloc(&d_input, sizeof(float) * lenInput);
hipMalloc(&d_output, sizeof(float) * lenInput);
hipMemcpy(d_input, input, sizeof(float) * lenInput, hipMemcpyHostToDevice);
dim3 dimGrid(lenOutput);
dim3 dimBlock(BLOCK_SIZE);
sum_cud<<<dimGrid, dimBlock>>>(d_input, d_output, lenInput);
hipMemcpy(output, d_output, sizeof(float) * lenOutput, hipMemcpyDeviceToHost);
input = output;
lenInput = lenOutput;
} while (lenOutput > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_, start, stop);
printf("GPU ime is: %f\n", time_/1000);
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
cout << "Cuda result: " << output[0] << endl;
hipFree(d_input);
hipFree(d_output);
free(input);
free(output);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sum_cudPfS_i
.globl _Z7sum_cudPfS_i
.p2align 8
.type _Z7sum_cudPfS_i,@function
_Z7sum_cudPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
.LBB0_7:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sum_cudPfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sum_cudPfS_i, .Lfunc_end0-_Z7sum_cudPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sum_cudPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sum_cudPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <iostream>
#include <time.h>
using namespace std;
#define BLOCK_SIZE 256
#define SEED 1337
#define ARR_LENGTH 5000
__global__ void sum_cud(float * in, float * out, int len) {
__shared__ float sum[2*BLOCK_SIZE];
unsigned int th_num = threadIdx.x;
unsigned int pointer = blockIdx.x * blockDim.x;
if (pointer + th_num < len)
sum[th_num] = in[pointer + th_num];
else
sum[th_num] = 0;
for (unsigned int stride = blockDim.x/2; stride >= 1; stride >>= 1) {
if (th_num < stride)
sum[th_num] += sum[th_num+stride];
__syncthreads();
}
if (th_num == 0)
out[blockIdx.x] = sum[0];
}
float randInRange(float min, float max)
{
return min + (float) (rand() / (double) (RAND_MAX + 1) * (max - min + 1));
}
int main(int argc, char ** argv) {
srand(SEED);
float * input;
float * output;
float * d_input;
float * d_output;
int lenInput = ARR_LENGTH;
int lenOutput;
input = (float*) malloc(lenInput * sizeof(float));
for (int i = 0; i < lenInput; ++i)
{
input[i] = randInRange(0.0, 10.0);
}
clock_t Time;
Time = clock();
float sum = 0.0;
for (int i = 0; i < lenInput; i++) {
sum += input[i];
}
cout << "CPU result: " << sum << endl;
Time = clock() - Time;
float Time_ = (float) Time / CLOCKS_PER_SEC;
cout << "CPU time is: " << Time_ << endl;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float time_;
hipEventRecord(start, 0);
do
{
lenOutput = lenInput / (BLOCK_SIZE);
if (lenInput % (BLOCK_SIZE)) {
lenOutput++;
}
output = (float*) malloc(lenOutput * sizeof(float));
hipMalloc(&d_input, sizeof(float) * lenInput);
hipMalloc(&d_output, sizeof(float) * lenInput);
hipMemcpy(d_input, input, sizeof(float) * lenInput, hipMemcpyHostToDevice);
dim3 dimGrid(lenOutput);
dim3 dimBlock(BLOCK_SIZE);
sum_cud<<<dimGrid, dimBlock>>>(d_input, d_output, lenInput);
hipMemcpy(output, d_output, sizeof(float) * lenOutput, hipMemcpyDeviceToHost);
input = output;
lenInput = lenOutput;
} while (lenOutput > 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_, start, stop);
printf("GPU ime is: %f\n", time_/1000);
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
cout << "Cuda result: " << output[0] << endl;
hipFree(d_input);
hipFree(d_output);
free(input);
free(output);
return 0;
} | .text
.file "sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__sum_cudPfS_i # -- Begin function _Z22__device_stub__sum_cudPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__sum_cudPfS_i,@function
_Z22__device_stub__sum_cudPfS_i: # @_Z22__device_stub__sum_cudPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sum_cudPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__sum_cudPfS_i, .Lfunc_end0-_Z22__device_stub__sum_cudPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11randInRangeff
.LCPI1_0:
.quad 0xbe00000000000000 # double -4.6566128730773926E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl _Z11randInRangeff
.p2align 4, 0x90
.type _Z11randInRangeff,@function
_Z11randInRangeff: # @_Z11randInRangeff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movss (%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
subss %xmm2, %xmm1
addss .LCPI1_1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
addss %xmm2, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11randInRangeff, .Lfunc_end1-_Z11randInRangeff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0xbe00000000000000 # double -4.6566128730773926E-10
.LCPI2_1:
.quad 0x4026000000000000 # double 11
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x49742400 # float 1.0E+6
.LCPI2_3:
.long 0x447a0000 # float 1000
.LCPI2_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1337, %edi # imm = 0x539
callq srand
movl $20000, %edi # imm = 0x4E20
callq malloc
movq %rax, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
addss .LCPI2_4(%rip), %xmm0
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $5000, %rbx # imm = 0x1388
jne .LBB2_1
# %bb.2:
xorl %ebx, %ebx
callq clock
xorps %xmm0, %xmm0
movq %rax, %r14
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
addss (%r13,%rbx,4), %xmm0
incq %rbx
cmpq $5000, %rbx # imm = 0x1388
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
movss %xmm0, (%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI2_2(%rip), %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%rbx)
je .LBB2_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB2_12
.LBB2_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movabsq $4294967296, %rbx # imm = 0x100000000
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $5000, %r12d # imm = 0x1388
leaq 256(%rbx), %rax
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
movq 24(%rsp), %rsi
movq %r13, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r15d, %r12d
cmpl $1, %r15d
jbe .LBB2_16
.LBB2_13: # =>This Inner Loop Header: Depth=1
movq %r13, %rbx
movl %r12d, %r15d
shrl $8, %r15d
cmpb $1, %r12b
sbbl $-1, %r15d
leal (,%r15,4), %ebp
movq %rbp, %rdi
callq malloc
movq %rax, %r13
movl %r12d, %r14d
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq (%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl %r12d, 44(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z7sum_cudPfS_i, %edi
leaq 48(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_15
.LBB2_16:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%rbx)
je .LBB2_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB2_20
.LBB2_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sum_cudPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sum_cudPfS_i,@object # @_Z7sum_cudPfS_i
.section .rodata,"a",@progbits
.globl _Z7sum_cudPfS_i
.p2align 3, 0x0
_Z7sum_cudPfS_i:
.quad _Z22__device_stub__sum_cudPfS_i
.size _Z7sum_cudPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU result: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU time is: "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU ime is: %f\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda result: "
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sum_cudPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sum_cudPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sum_cudPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sum_cudPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26070 */
/*0060*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*0070*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fcc00078e0003 */
/*0080*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000602029981 */
/* 0x000ea2000c1e1900 */
/*0090*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*00c0*/ @P1 STS [R7.X4], RZ ; /* 0x000000ff07001388 */
/* 0x0001ea0000004800 */
/*00d0*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*00e0*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0041d80000004800 */
/*00f0*/ @!P2 BRA 0x1c0 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x000fe200000006ff */
/*0110*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0130*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x001fe200078e10ff */
/*0140*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0150*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0160*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0170*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0180*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01b0*/ @P1 BRA 0x120 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e0003 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sum_cudPfS_i
.globl _Z7sum_cudPfS_i
.p2align 8
.type _Z7sum_cudPfS_i,@function
_Z7sum_cudPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
.LBB0_7:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sum_cudPfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sum_cudPfS_i, .Lfunc_end0-_Z7sum_cudPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sum_cudPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sum_cudPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c85e_00000000-6_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11randInRangeff
.type _Z11randInRangeff, @function
_Z11randInRangeff:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm2
subss %xmm2, %xmm1
addss .LC1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
addss %xmm2, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z11randInRangeff, .-_Z11randInRangeff
.globl _Z29__device_stub__Z7sum_cudPfS_iPfS_i
.type _Z29__device_stub__Z7sum_cudPfS_iPfS_i, @function
_Z29__device_stub__Z7sum_cudPfS_iPfS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sum_cudPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z7sum_cudPfS_iPfS_i, .-_Z29__device_stub__Z7sum_cudPfS_iPfS_i
.globl _Z7sum_cudPfS_i
.type _Z7sum_cudPfS_i, @function
_Z7sum_cudPfS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sum_cudPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7sum_cudPfS_i, .-_Z7sum_cudPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU result: "
.LC6:
.string "CPU time is: "
.LC8:
.string "GPU ime is: %f\n"
.LC9:
.string "Cuda result: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1337, %edi
call srand@PLT
movl $20000, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rbx
leaq 20000(%rax), %r12
movq %rax, %rbp
.L14:
movss .LC3(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z11randInRangeff
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L14
call clock@PLT
movq %rax, %rbp
movl $0x00000000, 8(%rsp)
.L15:
movss 8(%rsp), %xmm2
addss (%rbx), %xmm2
movss %xmm2, 8(%rsp)
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, 8(%rsp)
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $5000, %ebp
leaq 16(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L18
.L17:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $1, %ebx
jle .L24
movl %ebx, %ebp
movq %r13, %r15
.L18:
leal 255(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $8, %ebx
cmpb $1, %bpl
sbbl $-1, %ebx
movslq %ebx, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movslq %ebp, %r12
salq $2, %r12
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z7sum_cudPfS_iPfS_i
jmp .L17
.L24:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 60(%rsp), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z7sum_cudPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sum_cudPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1107296256
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC3:
.long 1092616192
.align 4
.LC5:
.long 1232348160
.align 4
.LC7:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__sum_cudPfS_i # -- Begin function _Z22__device_stub__sum_cudPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__sum_cudPfS_i,@function
_Z22__device_stub__sum_cudPfS_i: # @_Z22__device_stub__sum_cudPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sum_cudPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__sum_cudPfS_i, .Lfunc_end0-_Z22__device_stub__sum_cudPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11randInRangeff
.LCPI1_0:
.quad 0xbe00000000000000 # double -4.6566128730773926E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl _Z11randInRangeff
.p2align 4, 0x90
.type _Z11randInRangeff,@function
_Z11randInRangeff: # @_Z11randInRangeff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movss (%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
subss %xmm2, %xmm1
addss .LCPI1_1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
addss %xmm2, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11randInRangeff, .Lfunc_end1-_Z11randInRangeff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0xbe00000000000000 # double -4.6566128730773926E-10
.LCPI2_1:
.quad 0x4026000000000000 # double 11
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x49742400 # float 1.0E+6
.LCPI2_3:
.long 0x447a0000 # float 1000
.LCPI2_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1337, %edi # imm = 0x539
callq srand
movl $20000, %edi # imm = 0x4E20
callq malloc
movq %rax, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
addss .LCPI2_4(%rip), %xmm0
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $5000, %rbx # imm = 0x1388
jne .LBB2_1
# %bb.2:
xorl %ebx, %ebx
callq clock
xorps %xmm0, %xmm0
movq %rax, %r14
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
addss (%r13,%rbx,4), %xmm0
incq %rbx
cmpq $5000, %rbx # imm = 0x1388
jne .LBB2_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
movss %xmm0, (%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI2_2(%rip), %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%rbx)
je .LBB2_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB2_12
.LBB2_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movabsq $4294967296, %rbx # imm = 0x100000000
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $5000, %r12d # imm = 0x1388
leaq 256(%rbx), %rax
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
movq 24(%rsp), %rsi
movq %r13, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r15d, %r12d
cmpl $1, %r15d
jbe .LBB2_16
.LBB2_13: # =>This Inner Loop Header: Depth=1
movq %r13, %rbx
movl %r12d, %r15d
shrl $8, %r15d
cmpb $1, %r12b
sbbl $-1, %r15d
leal (,%r15,4), %ebp
movq %rbp, %rdi
callq malloc
movq %rax, %r13
movl %r12d, %r14d
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq (%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl %r12d, 44(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z7sum_cudPfS_i, %edi
leaq 48(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_15
.LBB2_16:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%rbx)
je .LBB2_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB2_20
.LBB2_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sum_cudPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sum_cudPfS_i,@object # @_Z7sum_cudPfS_i
.section .rodata,"a",@progbits
.globl _Z7sum_cudPfS_i
.p2align 3, 0x0
_Z7sum_cudPfS_i:
.quad _Z22__device_stub__sum_cudPfS_i
.size _Z7sum_cudPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU result: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU time is: "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU ime is: %f\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda result: "
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sum_cudPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sum_cudPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sum_cudPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void memSetKernel(
int nBatch,int rbs,int nDegree,int nDScale, int dbStopIdx,int dBaseScale, float regularize,
float *data,float *dataRev, // array of data and reverse data
float *R, // array of range
// arrays pointer
float *DA, float *RA,
float *AA, float *BA,
float *IA, float *CA,
float *EA, float *SA
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
,float **DP, float **RP,
float **AP, float **BP,
float **IP, float **CP,
float **EP, float **SP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch)
{
// initialize domain arrays
int nCoeff = ((nDegree - 1) * nDScale + 1);
int dpOffset = (taskIdx * rbs * nCoeff);
for(int i = 0; i < rbs; i++){
DA[dpOffset + i] = 1.0f; // power 0
}
for(int i = 0; i < rbs; i++){
DA[dpOffset + i + rbs] = 0.0f; // power 1
}
int dStartIdx = taskIdx % (nBatch/2);
for(int ds = 1; ds <= nDScale; ds++){
// vec sumation
int mapDStart = dStartIdx + (nDScale - ds) * (rbs/2);
int dScale = dBaseScale * ds; // base_scale * current_scale
for(int i = 0; i < dScale; i++){
for(int j = 0; j < rbs; j++){
if(taskIdx < (nBatch/2)){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + data[mapDStart + j*dScale + i];
}else{ // gen reverse domain
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + dataRev[mapDStart + j*dScale+ i];
}
}
}
// vec scalig
for(int j = 0; j < rbs; j++){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j]/dScale;
}
}
// calculate next degree
for(int j = 2; j < nDegree; j++){
int degreePad = (j * rbs * nDScale );
for(int i = 0; i < rbs * nDScale; i++){
DA[i + dpOffset + rbs + degreePad] = DA[j + dpOffset + rbs] * DA[j + dpOffset + rbs + degreePad - rbs] ; // power n>=2
}
}
// initialize range and error arrays
int rpOffset = (taskIdx * rbs);
for(int j = 0; j < rbs; j++){
RA[rpOffset + j] = R[j];
EA[rpOffset + j] = R[j];
}
// initialize covariance matrix with regularization
int apOffset = (taskIdx * nCoeff * nCoeff);
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
AA[apOffset + i] = regularize * regularize; // power 0
}
// pointing section
DP[taskIdx] = (DA + taskIdx * rbs * nCoeff);
RP[taskIdx] = (RA + taskIdx * rbs);
AP[taskIdx] = (AA + taskIdx * nCoeff * nCoeff);
BP[taskIdx] = (BA + taskIdx * nCoeff);
IP[taskIdx] = (IA + taskIdx * nCoeff * nCoeff);
CP[taskIdx] = (CA + taskIdx * nCoeff);
EP[taskIdx] = (EA + taskIdx * rbs);
SP[taskIdx] = (SA + taskIdx);
}
} | .file "tmpxft_000c6dee_00000000-6_memSetKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_
.type _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_, @function
_Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $488, %rsp
.cfi_def_cfa_offset 496
movl %edi, 188(%rsp)
movl %esi, 184(%rsp)
movl %edx, 180(%rsp)
movl %ecx, 176(%rsp)
movl %r8d, 172(%rsp)
movl %r9d, 168(%rsp)
movss %xmm0, 164(%rsp)
movq 496(%rsp), %rax
movq %rax, 152(%rsp)
movq 504(%rsp), %rax
movq %rax, 144(%rsp)
movq 512(%rsp), %rax
movq %rax, 136(%rsp)
movq 520(%rsp), %rax
movq %rax, 128(%rsp)
movq 528(%rsp), %rax
movq %rax, 120(%rsp)
movq 536(%rsp), %rax
movq %rax, 112(%rsp)
movq 544(%rsp), %rax
movq %rax, 104(%rsp)
movq 552(%rsp), %rax
movq %rax, 96(%rsp)
movq 560(%rsp), %rax
movq %rax, 88(%rsp)
movq 568(%rsp), %rax
movq %rax, 80(%rsp)
movq 576(%rsp), %rax
movq %rax, 72(%rsp)
movq 584(%rsp), %rax
movq %rax, 64(%rsp)
movq 592(%rsp), %rax
movq %rax, 56(%rsp)
movq 600(%rsp), %rax
movq %rax, 48(%rsp)
movq 608(%rsp), %rax
movq %rax, 40(%rsp)
movq 616(%rsp), %rax
movq %rax, 32(%rsp)
movq 624(%rsp), %rax
movq %rax, 24(%rsp)
movq 632(%rsp), %rax
movq %rax, 16(%rsp)
movq 640(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
leaq 188(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 180(%rsp), %rax
movq %rax, 272(%rsp)
leaq 176(%rsp), %rax
movq %rax, 280(%rsp)
leaq 172(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 164(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 136(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rax
movq %rax, 336(%rsp)
leaq 120(%rsp), %rax
movq %rax, 344(%rsp)
leaq 112(%rsp), %rax
movq %rax, 352(%rsp)
leaq 104(%rsp), %rax
movq %rax, 360(%rsp)
leaq 96(%rsp), %rax
movq %rax, 368(%rsp)
leaq 88(%rsp), %rax
movq %rax, 376(%rsp)
leaq 80(%rsp), %rax
movq %rax, 384(%rsp)
leaq 72(%rsp), %rax
movq %rax, 392(%rsp)
leaq 64(%rsp), %rax
movq %rax, 400(%rsp)
leaq 56(%rsp), %rax
movq %rax, 408(%rsp)
leaq 48(%rsp), %rax
movq %rax, 416(%rsp)
leaq 40(%rsp), %rax
movq %rax, 424(%rsp)
leaq 32(%rsp), %rax
movq %rax, 432(%rsp)
leaq 24(%rsp), %rax
movq %rax, 440(%rsp)
leaq 16(%rsp), %rax
movq %rax, 448(%rsp)
leaq 8(%rsp), %rax
movq %rax, 456(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 504
pushq 200(%rsp)
.cfi_def_cfa_offset 512
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq memSetKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 496
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_, .-_Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_
.globl memSetKernel
.type memSetKernel, @function
memSetKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 168(%rsp)
.cfi_def_cfa_offset 32
pushq 168(%rsp)
.cfi_def_cfa_offset 40
pushq 168(%rsp)
.cfi_def_cfa_offset 48
pushq 168(%rsp)
.cfi_def_cfa_offset 56
pushq 168(%rsp)
.cfi_def_cfa_offset 64
pushq 168(%rsp)
.cfi_def_cfa_offset 72
pushq 168(%rsp)
.cfi_def_cfa_offset 80
pushq 168(%rsp)
.cfi_def_cfa_offset 88
pushq 168(%rsp)
.cfi_def_cfa_offset 96
pushq 168(%rsp)
.cfi_def_cfa_offset 104
pushq 168(%rsp)
.cfi_def_cfa_offset 112
pushq 168(%rsp)
.cfi_def_cfa_offset 120
pushq 168(%rsp)
.cfi_def_cfa_offset 128
pushq 168(%rsp)
.cfi_def_cfa_offset 136
pushq 168(%rsp)
.cfi_def_cfa_offset 144
pushq 168(%rsp)
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
call _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size memSetKernel, .-memSetKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "memSetKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq memSetKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void memSetKernel(
int nBatch,int rbs,int nDegree,int nDScale, int dbStopIdx,int dBaseScale, float regularize,
float *data,float *dataRev, // array of data and reverse data
float *R, // array of range
// arrays pointer
float *DA, float *RA,
float *AA, float *BA,
float *IA, float *CA,
float *EA, float *SA
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
,float **DP, float **RP,
float **AP, float **BP,
float **IP, float **CP,
float **EP, float **SP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch)
{
// initialize domain arrays
int nCoeff = ((nDegree - 1) * nDScale + 1);
int dpOffset = (taskIdx * rbs * nCoeff);
for(int i = 0; i < rbs; i++){
DA[dpOffset + i] = 1.0f; // power 0
}
for(int i = 0; i < rbs; i++){
DA[dpOffset + i + rbs] = 0.0f; // power 1
}
int dStartIdx = taskIdx % (nBatch/2);
for(int ds = 1; ds <= nDScale; ds++){
// vec sumation
int mapDStart = dStartIdx + (nDScale - ds) * (rbs/2);
int dScale = dBaseScale * ds; // base_scale * current_scale
for(int i = 0; i < dScale; i++){
for(int j = 0; j < rbs; j++){
if(taskIdx < (nBatch/2)){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + data[mapDStart + j*dScale + i];
}else{ // gen reverse domain
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + dataRev[mapDStart + j*dScale+ i];
}
}
}
// vec scalig
for(int j = 0; j < rbs; j++){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j]/dScale;
}
}
// calculate next degree
for(int j = 2; j < nDegree; j++){
int degreePad = (j * rbs * nDScale );
for(int i = 0; i < rbs * nDScale; i++){
DA[i + dpOffset + rbs + degreePad] = DA[j + dpOffset + rbs] * DA[j + dpOffset + rbs + degreePad - rbs] ; // power n>=2
}
}
// initialize range and error arrays
int rpOffset = (taskIdx * rbs);
for(int j = 0; j < rbs; j++){
RA[rpOffset + j] = R[j];
EA[rpOffset + j] = R[j];
}
// initialize covariance matrix with regularization
int apOffset = (taskIdx * nCoeff * nCoeff);
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
AA[apOffset + i] = regularize * regularize; // power 0
}
// pointing section
DP[taskIdx] = (DA + taskIdx * rbs * nCoeff);
RP[taskIdx] = (RA + taskIdx * rbs);
AP[taskIdx] = (AA + taskIdx * nCoeff * nCoeff);
BP[taskIdx] = (BA + taskIdx * nCoeff);
IP[taskIdx] = (IA + taskIdx * nCoeff * nCoeff);
CP[taskIdx] = (CA + taskIdx * nCoeff);
EP[taskIdx] = (EA + taskIdx * rbs);
SP[taskIdx] = (SA + taskIdx);
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void memSetKernel(
int nBatch,int rbs,int nDegree,int nDScale, int dbStopIdx,int dBaseScale, float regularize,
float *data,float *dataRev, // array of data and reverse data
float *R, // array of range
// arrays pointer
float *DA, float *RA,
float *AA, float *BA,
float *IA, float *CA,
float *EA, float *SA
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
,float **DP, float **RP,
float **AP, float **BP,
float **IP, float **CP,
float **EP, float **SP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch)
{
// initialize domain arrays
int nCoeff = ((nDegree - 1) * nDScale + 1);
int dpOffset = (taskIdx * rbs * nCoeff);
for(int i = 0; i < rbs; i++){
DA[dpOffset + i] = 1.0f; // power 0
}
for(int i = 0; i < rbs; i++){
DA[dpOffset + i + rbs] = 0.0f; // power 1
}
int dStartIdx = taskIdx % (nBatch/2);
for(int ds = 1; ds <= nDScale; ds++){
// vec sumation
int mapDStart = dStartIdx + (nDScale - ds) * (rbs/2);
int dScale = dBaseScale * ds; // base_scale * current_scale
for(int i = 0; i < dScale; i++){
for(int j = 0; j < rbs; j++){
if(taskIdx < (nBatch/2)){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + data[mapDStart + j*dScale + i];
}else{ // gen reverse domain
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + dataRev[mapDStart + j*dScale+ i];
}
}
}
// vec scalig
for(int j = 0; j < rbs; j++){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j]/dScale;
}
}
// calculate next degree
for(int j = 2; j < nDegree; j++){
int degreePad = (j * rbs * nDScale );
for(int i = 0; i < rbs * nDScale; i++){
DA[i + dpOffset + rbs + degreePad] = DA[j + dpOffset + rbs] * DA[j + dpOffset + rbs + degreePad - rbs] ; // power n>=2
}
}
// initialize range and error arrays
int rpOffset = (taskIdx * rbs);
for(int j = 0; j < rbs; j++){
RA[rpOffset + j] = R[j];
EA[rpOffset + j] = R[j];
}
// initialize covariance matrix with regularization
int apOffset = (taskIdx * nCoeff * nCoeff);
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
AA[apOffset + i] = regularize * regularize; // power 0
}
// pointing section
DP[taskIdx] = (DA + taskIdx * rbs * nCoeff);
RP[taskIdx] = (RA + taskIdx * rbs);
AP[taskIdx] = (AA + taskIdx * nCoeff * nCoeff);
BP[taskIdx] = (BA + taskIdx * nCoeff);
IP[taskIdx] = (IA + taskIdx * nCoeff * nCoeff);
CP[taskIdx] = (CA + taskIdx * nCoeff);
EP[taskIdx] = (EA + taskIdx * rbs);
SP[taskIdx] = (SA + taskIdx);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void memSetKernel(
int nBatch,int rbs,int nDegree,int nDScale, int dbStopIdx,int dBaseScale, float regularize,
float *data,float *dataRev, // array of data and reverse data
float *R, // array of range
// arrays pointer
float *DA, float *RA,
float *AA, float *BA,
float *IA, float *CA,
float *EA, float *SA
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
,float **DP, float **RP,
float **AP, float **BP,
float **IP, float **CP,
float **EP, float **SP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch)
{
// initialize domain arrays
int nCoeff = ((nDegree - 1) * nDScale + 1);
int dpOffset = (taskIdx * rbs * nCoeff);
for(int i = 0; i < rbs; i++){
DA[dpOffset + i] = 1.0f; // power 0
}
for(int i = 0; i < rbs; i++){
DA[dpOffset + i + rbs] = 0.0f; // power 1
}
int dStartIdx = taskIdx % (nBatch/2);
for(int ds = 1; ds <= nDScale; ds++){
// vec sumation
int mapDStart = dStartIdx + (nDScale - ds) * (rbs/2);
int dScale = dBaseScale * ds; // base_scale * current_scale
for(int i = 0; i < dScale; i++){
for(int j = 0; j < rbs; j++){
if(taskIdx < (nBatch/2)){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + data[mapDStart + j*dScale + i];
}else{ // gen reverse domain
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + dataRev[mapDStart + j*dScale+ i];
}
}
}
// vec scalig
for(int j = 0; j < rbs; j++){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j]/dScale;
}
}
// calculate next degree
for(int j = 2; j < nDegree; j++){
int degreePad = (j * rbs * nDScale );
for(int i = 0; i < rbs * nDScale; i++){
DA[i + dpOffset + rbs + degreePad] = DA[j + dpOffset + rbs] * DA[j + dpOffset + rbs + degreePad - rbs] ; // power n>=2
}
}
// initialize range and error arrays
int rpOffset = (taskIdx * rbs);
for(int j = 0; j < rbs; j++){
RA[rpOffset + j] = R[j];
EA[rpOffset + j] = R[j];
}
// initialize covariance matrix with regularization
int apOffset = (taskIdx * nCoeff * nCoeff);
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
AA[apOffset + i] = regularize * regularize; // power 0
}
// pointing section
DP[taskIdx] = (DA + taskIdx * rbs * nCoeff);
RP[taskIdx] = (RA + taskIdx * rbs);
AP[taskIdx] = (AA + taskIdx * nCoeff * nCoeff);
BP[taskIdx] = (BA + taskIdx * nCoeff);
IP[taskIdx] = (IA + taskIdx * nCoeff * nCoeff);
CP[taskIdx] = (CA + taskIdx * nCoeff);
EP[taskIdx] = (EA + taskIdx * rbs);
SP[taskIdx] = (SA + taskIdx);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected memSetKernel
.globl memSetKernel
.p2align 8
.type memSetKernel,@function
memSetKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc4
s_load_b32 s10, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_31
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x4
s_load_b32 s6, s[0:1], 0xc
s_load_b64 s[2:3], s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, v1, s4
s_add_i32 s9, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s6
s_add_i32 s8, s9, 1
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v3, s8
v_ashrrev_i32_e32 v7, 31, v6
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_mov_b32_e32 v0, 1.0
s_mov_b32 s7, s4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
.LBB0_3:
global_store_b32 v[4:5], v0, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 0
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_mul_lo_u32 v5, v1, s8
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_7
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, s4, v5, s[4:5]
v_mov_b32_e32 v0, 0
s_mov_b32 s7, s4
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v9, 31, v8
s_add_i32 s7, s7, -1
s_cmp_eq_u32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[8:9]
v_add_nc_u32_e32 v8, 1, v8
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_store_b32 v[9:10], v0, off
s_cbranch_scc0 .LBB0_6
.LBB0_7:
s_cmp_lt_i32 s6, 1
s_mov_b32 s7, 1
s_cbranch_scc1 .LBB0_18
s_lshr_b32 s11, s10, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s10, s10, s11
s_load_b128 s[16:19], s[0:1], 0x20
s_ashr_i32 s13, s10, 1
s_ashr_i32 s10, s10, 31
v_add_nc_u32_e32 v8, v1, v4
s_add_i32 s11, s13, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s14, s11, s10
v_cvt_f32_u32_e32 v0, s14
s_sub_i32 s10, 0, s14
v_xor_b32_e32 v10, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s10, v0
s_lshr_b32 s10, s4, 31
s_add_i32 s11, s4, s10
s_load_b32 s10, s[0:1], 0x14
s_ashr_i32 s11, s11, 1
s_cmp_gt_i32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
s_cselect_b32 s12, -1, 0
s_add_i32 s15, s6, -1
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v10, v0, 0
v_mul_lo_u32 v0, v9, s14
v_mad_u64_u32 v[8:9], null, s4, v5, s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v10, v0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v10, s16
v_subrev_nc_u32_e32 v2, s14, v0
v_cmp_le_u32_e32 vcc_lo, s14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s14, v0
v_cmp_le_u32_e32 vcc_lo, s14, v0
s_mul_i32 s14, s11, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_mov_b32_e32 v2, s17
v_cmp_gt_i32_e32 vcc_lo, s13, v1
s_mov_b32 s13, s10
v_xad_u32 v11, v0, v4, s14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, s19, v2, vcc_lo
v_cndmask_b32_e32 v2, s18, v10, vcc_lo
v_sub_nc_u32_e32 v4, v11, v4
s_branch .LBB0_10
.LBB0_9:
v_add_nc_u32_e32 v8, s4, v8
v_subrev_nc_u32_e32 v4, s11, v4
s_add_i32 s14, s7, 1
s_add_i32 s13, s13, s10
s_cmp_eq_u32 s7, s6
s_mov_b32 s7, s14
s_cbranch_scc1 .LBB0_18
.LBB0_10:
v_ashrrev_i32_e32 v9, 31, v8
s_mul_i32 s14, s7, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[8:9]
v_mov_b32_e32 v16, v4
s_mov_b32 s15, 0
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
v_add_nc_u32_e32 v16, 1, v16
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB0_15
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v16 :: v_dual_mov_b32 v15, v11
v_mov_b32_e32 v14, v10
s_and_not1_b32 vcc_lo, exec_lo, s12
s_mov_b32 s16, s4
s_cbranch_vccnz .LBB0_12
.p2align 6
.LBB0_14:
v_ashrrev_i32_e32 v13, 31, v12
global_load_b32 v19, v[14:15], off
s_add_i32 s16, s16, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s16, 0
v_lshlrev_b64 v[17:18], 2, v[12:13]
v_add_co_u32 v17, vcc_lo, v2, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, v0, v18, vcc_lo
global_load_b32 v13, v[17:18], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v13, v19, v13 :: v_dual_add_nc_u32 v12, s13, v12
global_store_b32 v[14:15], v13, off
v_add_co_u32 v14, vcc_lo, v14, 4
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
s_cbranch_scc0 .LBB0_14
s_branch .LBB0_12
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_9
v_lshlrev_b64 v[9:10], 2, v[8:9]
v_cvt_f32_i32_e32 v11, s14
s_mov_b32 s14, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
.p2align 6
.LBB0_17:
global_load_b32 v12, v[9:10], off
s_add_i32 s14, s14, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s14, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v13, null, v11, v11, v12
v_div_scale_f32 v16, vcc_lo, v12, v11, v12
v_rcp_f32_e32 v14, v13
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v13, v14, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v15, v14
v_mul_f32_e32 v15, v16, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, -v13, v15, v16
v_fmac_f32_e32 v15, v17, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v13, v15, v16
v_div_fmas_f32 v13, v13, v14, v15
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v12, v13, v11, v12
global_store_b32 v[9:10], v12, off
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_cbranch_scc0 .LBB0_17
s_branch .LBB0_9
.LBB0_18:
s_cmp_lt_i32 s5, 3
s_cbranch_scc1 .LBB0_24
v_lshl_add_u32 v0, s6, 1, v5
s_mul_i32 s6, s6, s4
s_mov_b32 s10, 2
s_cmp_gt_i32 s6, 0
s_cselect_b32 s7, -1, 0
v_mad_u64_u32 v[8:9], null, s4, v0, s[4:5]
v_add_nc_u32_e32 v0, s4, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_21
.p2align 6
.LBB0_20:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v8, s6, v8
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s10, s5
s_cbranch_scc1 .LBB0_24
.LBB0_21:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_20
v_add_nc_u32_e32 v9, s10, v0
s_mul_i32 s11, s6, s10
v_mov_b32_e32 v13, v8
s_sub_i32 s11, s11, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, s11, v9
v_ashrrev_i32_e32 v10, 31, v9
s_mov_b32 s11, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
.p2align 6
.LBB0_23:
s_clause 0x1
global_load_b32 v2, v[9:10], off
global_load_b32 v4, v[11:12], off
v_ashrrev_i32_e32 v14, 31, v13
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s11, 0
v_lshlrev_b64 v[14:15], 2, v[13:14]
v_add_nc_u32_e32 v13, 1, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v4
global_store_b32 v[14:15], v2, off
s_cbranch_scc0 .LBB0_23
s_branch .LBB0_20
.LBB0_24:
s_set_inst_prefetch_distance 0x2
s_clause 0x1
s_load_b64 s[26:27], s[0:1], 0x40
s_load_b64 s[24:25], s[0:1], 0x68
v_ashrrev_i32_e32 v4, 31, v3
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_27
s_load_b64 s[6:7], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s26, v10
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s27, v11, vcc_lo
v_add_co_u32 v10, vcc_lo, s24, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s25, v11, vcc_lo
.p2align 6
.LBB0_26:
global_load_b32 v2, v0, s[6:7]
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v2, off
global_load_b32 v2, v0, s[6:7]
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
global_store_b32 v[10:11], v2, off
v_add_co_u32 v10, vcc_lo, v10, 4
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_cbranch_scc0 .LBB0_26
.LBB0_27:
s_load_b64 s[28:29], s[0:1], 0x48
v_mul_lo_u32 v8, v5, s8
s_cmp_eq_u32 s8, 0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
s_cbranch_scc1 .LBB0_30
s_load_b32 s5, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[8:9]
s_add_i32 s4, s9, 2
s_mul_i32 s8, s8, s8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s28, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v11, vcc_lo, s29, v11, vcc_lo
v_mul_f32_e64 v0, s5, s5
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
.LBB0_29:
global_store_b32 v[10:11], v0, off
v_add_co_u32 v10, vcc_lo, v10, s6
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_add_i32 s10, s10, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s10, s8
s_cbranch_scc0 .LBB0_29
.LBB0_30:
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x70
s_load_b128 s[20:23], s[0:1], 0x50
s_load_b64 s[30:31], s[0:1], 0x60
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_load_b256 s[12:19], s[0:1], 0x90
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_load_b64 s[0:1], s[0:1], 0xb0
v_lshlrev_b64 v[10:11], 3, v[1:2]
v_add_co_u32 v12, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v7, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, s26, v3
v_add_co_ci_u32_e32 v15, vcc_lo, s27, v4, vcc_lo
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v16, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v18, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v19, vcc_lo, s9, v11, vcc_lo
v_add_co_u32 v20, vcc_lo, s28, v8
v_add_co_ci_u32_e32 v21, vcc_lo, s29, v9, vcc_lo
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v22, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v23, vcc_lo, s11, v11, vcc_lo
global_store_b64 v[16:17], v[12:13], off
global_store_b64 v[18:19], v[14:15], off
global_store_b64 v[22:23], v[20:21], off
v_add_co_u32 v12, vcc_lo, s20, v5
v_add_co_ci_u32_e32 v13, vcc_lo, s21, v6, vcc_lo
v_add_co_u32 v14, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v15, vcc_lo, s13, v11, vcc_lo
v_add_co_u32 v7, vcc_lo, s22, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s23, v9, vcc_lo
v_add_co_u32 v16, vcc_lo, s14, v10
v_add_co_ci_u32_e32 v17, vcc_lo, s15, v11, vcc_lo
v_add_co_u32 v5, vcc_lo, s30, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s31, v6, vcc_lo
v_add_co_u32 v18, vcc_lo, s16, v10
v_add_co_ci_u32_e32 v19, vcc_lo, s17, v11, vcc_lo
v_add_co_u32 v3, vcc_lo, s24, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s25, v4, vcc_lo
v_add_co_u32 v20, vcc_lo, s18, v10
v_add_co_ci_u32_e32 v21, vcc_lo, s19, v11, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v11, vcc_lo
global_store_b64 v[14:15], v[12:13], off
global_store_b64 v[16:17], v[7:8], off
global_store_b64 v[18:19], v[5:6], off
global_store_b64 v[20:21], v[3:4], off
global_store_b64 v[9:10], v[0:1], off
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel memSetKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 440
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size memSetKernel, .Lfunc_end0-memSetKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 128
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 136
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 144
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 152
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 160
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 168
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 176
.size: 8
.value_kind: global_buffer
- .offset: 184
.size: 4
.value_kind: hidden_block_count_x
- .offset: 188
.size: 4
.value_kind: hidden_block_count_y
- .offset: 192
.size: 4
.value_kind: hidden_block_count_z
- .offset: 196
.size: 2
.value_kind: hidden_group_size_x
- .offset: 198
.size: 2
.value_kind: hidden_group_size_y
- .offset: 200
.size: 2
.value_kind: hidden_group_size_z
- .offset: 202
.size: 2
.value_kind: hidden_remainder_x
- .offset: 204
.size: 2
.value_kind: hidden_remainder_y
- .offset: 206
.size: 2
.value_kind: hidden_remainder_z
- .offset: 224
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 232
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 240
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 248
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 440
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: memSetKernel
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: memSetKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void memSetKernel(
int nBatch,int rbs,int nDegree,int nDScale, int dbStopIdx,int dBaseScale, float regularize,
float *data,float *dataRev, // array of data and reverse data
float *R, // array of range
// arrays pointer
float *DA, float *RA,
float *AA, float *BA,
float *IA, float *CA,
float *EA, float *SA
// pointer of array of pointer to pointer of array in arrays, nevermind i just stun you.
// p(i) = data(i + size(data))
,float **DP, float **RP,
float **AP, float **BP,
float **IP, float **CP,
float **EP, float **SP
)
{
int taskIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (taskIdx < nBatch)
{
// initialize domain arrays
int nCoeff = ((nDegree - 1) * nDScale + 1);
int dpOffset = (taskIdx * rbs * nCoeff);
for(int i = 0; i < rbs; i++){
DA[dpOffset + i] = 1.0f; // power 0
}
for(int i = 0; i < rbs; i++){
DA[dpOffset + i + rbs] = 0.0f; // power 1
}
int dStartIdx = taskIdx % (nBatch/2);
for(int ds = 1; ds <= nDScale; ds++){
// vec sumation
int mapDStart = dStartIdx + (nDScale - ds) * (rbs/2);
int dScale = dBaseScale * ds; // base_scale * current_scale
for(int i = 0; i < dScale; i++){
for(int j = 0; j < rbs; j++){
if(taskIdx < (nBatch/2)){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + data[mapDStart + j*dScale + i];
}else{ // gen reverse domain
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j] + dataRev[mapDStart + j*dScale+ i];
}
}
}
// vec scalig
for(int j = 0; j < rbs; j++){
DA[dpOffset + rbs*ds + j] = DA[dpOffset + rbs*ds + j]/dScale;
}
}
// calculate next degree
for(int j = 2; j < nDegree; j++){
int degreePad = (j * rbs * nDScale );
for(int i = 0; i < rbs * nDScale; i++){
DA[i + dpOffset + rbs + degreePad] = DA[j + dpOffset + rbs] * DA[j + dpOffset + rbs + degreePad - rbs] ; // power n>=2
}
}
// initialize range and error arrays
int rpOffset = (taskIdx * rbs);
for(int j = 0; j < rbs; j++){
RA[rpOffset + j] = R[j];
EA[rpOffset + j] = R[j];
}
// initialize covariance matrix with regularization
int apOffset = (taskIdx * nCoeff * nCoeff);
for(int i = 0; i < nCoeff * nCoeff; i+= nCoeff+1){
AA[apOffset + i] = regularize * regularize; // power 0
}
// pointing section
DP[taskIdx] = (DA + taskIdx * rbs * nCoeff);
RP[taskIdx] = (RA + taskIdx * rbs);
AP[taskIdx] = (AA + taskIdx * nCoeff * nCoeff);
BP[taskIdx] = (BA + taskIdx * nCoeff);
IP[taskIdx] = (IA + taskIdx * nCoeff * nCoeff);
CP[taskIdx] = (CA + taskIdx * nCoeff);
EP[taskIdx] = (EA + taskIdx * rbs);
SP[taskIdx] = (SA + taskIdx);
}
} | .text
.file "memSetKernel.hip"
.globl __device_stub__memSetKernel # -- Begin function __device_stub__memSetKernel
.p2align 4, 0x90
.type __device_stub__memSetKernel,@function
__device_stub__memSetKernel: # @__device_stub__memSetKernel
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 304(%rsp), %rax
movq %rax, 136(%rsp)
leaq 312(%rsp), %rax
movq %rax, 144(%rsp)
leaq 320(%rsp), %rax
movq %rax, 152(%rsp)
leaq 328(%rsp), %rax
movq %rax, 160(%rsp)
leaq 336(%rsp), %rax
movq %rax, 168(%rsp)
leaq 344(%rsp), %rax
movq %rax, 176(%rsp)
leaq 352(%rsp), %rax
movq %rax, 184(%rsp)
leaq 360(%rsp), %rax
movq %rax, 192(%rsp)
leaq 368(%rsp), %rax
movq %rax, 200(%rsp)
leaq 376(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 448(%rsp), %rax
movq %rax, 280(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $memSetKernel, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size __device_stub__memSetKernel, .Lfunc_end0-__device_stub__memSetKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $memSetKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type memSetKernel,@object # @memSetKernel
.section .rodata,"a",@progbits
.globl memSetKernel
.p2align 3, 0x0
memSetKernel:
.quad __device_stub__memSetKernel
.size memSetKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "memSetKernel"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__memSetKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym memSetKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6dee_00000000-6_memSetKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_
.type _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_, @function
_Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $488, %rsp
.cfi_def_cfa_offset 496
movl %edi, 188(%rsp)
movl %esi, 184(%rsp)
movl %edx, 180(%rsp)
movl %ecx, 176(%rsp)
movl %r8d, 172(%rsp)
movl %r9d, 168(%rsp)
movss %xmm0, 164(%rsp)
movq 496(%rsp), %rax
movq %rax, 152(%rsp)
movq 504(%rsp), %rax
movq %rax, 144(%rsp)
movq 512(%rsp), %rax
movq %rax, 136(%rsp)
movq 520(%rsp), %rax
movq %rax, 128(%rsp)
movq 528(%rsp), %rax
movq %rax, 120(%rsp)
movq 536(%rsp), %rax
movq %rax, 112(%rsp)
movq 544(%rsp), %rax
movq %rax, 104(%rsp)
movq 552(%rsp), %rax
movq %rax, 96(%rsp)
movq 560(%rsp), %rax
movq %rax, 88(%rsp)
movq 568(%rsp), %rax
movq %rax, 80(%rsp)
movq 576(%rsp), %rax
movq %rax, 72(%rsp)
movq 584(%rsp), %rax
movq %rax, 64(%rsp)
movq 592(%rsp), %rax
movq %rax, 56(%rsp)
movq 600(%rsp), %rax
movq %rax, 48(%rsp)
movq 608(%rsp), %rax
movq %rax, 40(%rsp)
movq 616(%rsp), %rax
movq %rax, 32(%rsp)
movq 624(%rsp), %rax
movq %rax, 24(%rsp)
movq 632(%rsp), %rax
movq %rax, 16(%rsp)
movq 640(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
leaq 188(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 180(%rsp), %rax
movq %rax, 272(%rsp)
leaq 176(%rsp), %rax
movq %rax, 280(%rsp)
leaq 172(%rsp), %rax
movq %rax, 288(%rsp)
leaq 168(%rsp), %rax
movq %rax, 296(%rsp)
leaq 164(%rsp), %rax
movq %rax, 304(%rsp)
leaq 152(%rsp), %rax
movq %rax, 312(%rsp)
leaq 144(%rsp), %rax
movq %rax, 320(%rsp)
leaq 136(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rax
movq %rax, 336(%rsp)
leaq 120(%rsp), %rax
movq %rax, 344(%rsp)
leaq 112(%rsp), %rax
movq %rax, 352(%rsp)
leaq 104(%rsp), %rax
movq %rax, 360(%rsp)
leaq 96(%rsp), %rax
movq %rax, 368(%rsp)
leaq 88(%rsp), %rax
movq %rax, 376(%rsp)
leaq 80(%rsp), %rax
movq %rax, 384(%rsp)
leaq 72(%rsp), %rax
movq %rax, 392(%rsp)
leaq 64(%rsp), %rax
movq %rax, 400(%rsp)
leaq 56(%rsp), %rax
movq %rax, 408(%rsp)
leaq 48(%rsp), %rax
movq %rax, 416(%rsp)
leaq 40(%rsp), %rax
movq %rax, 424(%rsp)
leaq 32(%rsp), %rax
movq %rax, 432(%rsp)
leaq 24(%rsp), %rax
movq %rax, 440(%rsp)
leaq 16(%rsp), %rax
movq %rax, 448(%rsp)
leaq 8(%rsp), %rax
movq %rax, 456(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 504
pushq 200(%rsp)
.cfi_def_cfa_offset 512
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq memSetKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 496
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_, .-_Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_
.globl memSetKernel
.type memSetKernel, @function
memSetKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 168(%rsp)
.cfi_def_cfa_offset 32
pushq 168(%rsp)
.cfi_def_cfa_offset 40
pushq 168(%rsp)
.cfi_def_cfa_offset 48
pushq 168(%rsp)
.cfi_def_cfa_offset 56
pushq 168(%rsp)
.cfi_def_cfa_offset 64
pushq 168(%rsp)
.cfi_def_cfa_offset 72
pushq 168(%rsp)
.cfi_def_cfa_offset 80
pushq 168(%rsp)
.cfi_def_cfa_offset 88
pushq 168(%rsp)
.cfi_def_cfa_offset 96
pushq 168(%rsp)
.cfi_def_cfa_offset 104
pushq 168(%rsp)
.cfi_def_cfa_offset 112
pushq 168(%rsp)
.cfi_def_cfa_offset 120
pushq 168(%rsp)
.cfi_def_cfa_offset 128
pushq 168(%rsp)
.cfi_def_cfa_offset 136
pushq 168(%rsp)
.cfi_def_cfa_offset 144
pushq 168(%rsp)
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
call _Z83__device_stub__Z12memSetKerneliiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_iiiiiifPfS_S_S_S_S_S_S_S_S_S_PS_S0_S0_S0_S0_S0_S0_S0_
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size memSetKernel, .-memSetKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "memSetKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq memSetKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memSetKernel.hip"
.globl __device_stub__memSetKernel # -- Begin function __device_stub__memSetKernel
.p2align 4, 0x90
.type __device_stub__memSetKernel,@function
__device_stub__memSetKernel: # @__device_stub__memSetKernel
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 304(%rsp), %rax
movq %rax, 136(%rsp)
leaq 312(%rsp), %rax
movq %rax, 144(%rsp)
leaq 320(%rsp), %rax
movq %rax, 152(%rsp)
leaq 328(%rsp), %rax
movq %rax, 160(%rsp)
leaq 336(%rsp), %rax
movq %rax, 168(%rsp)
leaq 344(%rsp), %rax
movq %rax, 176(%rsp)
leaq 352(%rsp), %rax
movq %rax, 184(%rsp)
leaq 360(%rsp), %rax
movq %rax, 192(%rsp)
leaq 368(%rsp), %rax
movq %rax, 200(%rsp)
leaq 376(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 448(%rsp), %rax
movq %rax, 280(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $memSetKernel, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size __device_stub__memSetKernel, .Lfunc_end0-__device_stub__memSetKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $memSetKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type memSetKernel,@object # @memSetKernel
.section .rodata,"a",@progbits
.globl memSetKernel
.p2align 3, 0x0
memSetKernel:
.quad __device_stub__memSetKernel
.size memSetKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "memSetKernel"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__memSetKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym memSetKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //nvcc -o gol gol.cu
#define NEPOCHS 1000
#define DIMENSIONX 100
#define DIMENSIONY 100
#include <stdio.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
__global__
void Evolve(bool *u, int n, int dx, int dy)
{
int n_next = n + 1;
bool active_pre, active_post;
__shared__ bool shared_u[DIMENSIONX*DIMENSIONY];
//__shared__ bool shared_u_next[DIMENSIONX*DIMENSIONY];
//copy state in shared memory
for (int i=threadIdx.x; i<DIMENSIONX*DIMENSIONY; i+=blockDim.x) {
shared_u[i] = u[n*dx*dy+i];
}
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
//get number of neighbors
size_t NActiveNeighbors = 0;
int nmin_x = max(0, i - 1);
int nmax_x = min(i + 1, dx - 1);
int nmin_y = max(0, j - 1);
int nmax_y = min(j + 1, dy - 1);
for (int ii = nmin_x; ii <= nmax_x; ii++)
for (int jj = nmin_y; jj <= nmax_y; jj++)
{
if ((i == ii) && (j == jj))
continue;
if (shared_u[ii*dy+jj]) NActiveNeighbors += 1;
}
active_pre = shared_u[i*dy+j];
active_post = false;
if (active_pre && (NActiveNeighbors == 2))
active_post = true;
else if (active_pre && (NActiveNeighbors == 3))
active_post = true;
else if ((!active_pre) && (NActiveNeighbors == 3))
active_post = true;
u[n_next*dx*dy+i*dy+j] = active_post;
}
/*
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
u[n_next*dx*dy+i*dy+j] = shared_u_next[i*dy+j];
}
__syncthreads();
*/
return;
}
bool *allocate_universe(int n, int dx, int dy)
{
int Nelements = n*dx*dy;
bool *universe = new bool[Nelements];
for (int i = 0; i < Nelements; i++)
{
universe[i] = false;
}
return universe;
}
bool glider_gun_field(int i, int j) {
if (((i%40)==1)&&((j%30)==5)) return true;
if (((i%40)==1)&&((j%30)==6)) return true;
if (((i%40)==2)&&((j%30)==5)) return true;
if (((i%40)==2)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==5)) return true;
if (((i%40)==11)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==7)) return true;
if (((i%40)==12)&&((j%30)==4)) return true;
if (((i%40)==12)&&((j%30)==8)) return true;
if (((i%40)==13)&&((j%30)==3)) return true;
if (((i%40)==13)&&((j%30)==9)) return true;
if (((i%40)==14)&&((j%30)==3)) return true;
if (((i%40)==14)&&((j%30)==9)) return true;
if (((i%40)==15)&&((j%30)==6)) return true;
if (((i%40)==16)&&((j%30)==4)) return true;
if (((i%40)==16)&&((j%30)==8)) return true;
if (((i%40)==17)&&((j%30)==5)) return true;
if (((i%40)==17)&&((j%30)==6)) return true;
if (((i%40)==17)&&((j%30)==7)) return true;
if (((i%40)==18)&&((j%30)==6)) return true;
if (((i%40)==21)&&((j%30)==3)) return true;
if (((i%40)==21)&&((j%30)==4)) return true;
if (((i%40)==21)&&((j%30)==5)) return true;
if (((i%40)==22)&&((j%30)==3)) return true;
if (((i%40)==22)&&((j%30)==4)) return true;
if (((i%40)==22)&&((j%30)==5)) return true;
if (((i%40)==23)&&((j%30)==2)) return true;
if (((i%40)==23)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==1)) return true;
if (((i%40)==25)&&((j%30)==2)) return true;
if (((i%40)==25)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==7)) return true;
if (((i%40)==35)&&((j%30)==3)) return true;
if (((i%40)==35)&&((j%30)==4)) return true;
if (((i%40)==36)&&((j%30)==3)) return true;
if (((i%40)==36)&&((j%30)==4)) return true;
return false;
}
void set_initial_conditions(bool *u, int dx, int dy, float p)
{
for (int i = 0; i < dx; i++)
for (int j = 0; j < dy; j++)
{
//float _value = (rand() % 10000)/10000.;//((i*173+j*51) % 100) / 100.;
//if (_value < p)
if (glider_gun_field(i, j))
{
u[i*dy+j] = true;
}
}
rand();
}
int main(void)
{
long int NENTRIES = NEPOCHS*DIMENSIONX*DIMENSIONY;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
std::cout << "Defining the universe and creating the initial conditions" << std::endl;
bool *universe = allocate_universe(NEPOCHS, DIMENSIONX, DIMENSIONY);
set_initial_conditions(universe, DIMENSIONX, DIMENSIONY, 0.25);
bool *cuda_universe;
cudaMalloc((void**)&cuda_universe, NENTRIES*sizeof(bool));
cudaMemcpy(cuda_universe, universe, NENTRIES*sizeof(bool), cudaMemcpyHostToDevice);
cudaEventRecord(start);
for (int n=0; n<NEPOCHS-1; n++) {
Evolve<<<32, 64>>>(cuda_universe, n, DIMENSIONX, DIMENSIONY);
cudaDeviceSynchronize();
}
cudaEventRecord(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Total execution time (ms): %f\n ", milliseconds);
cudaMemcpy(universe, cuda_universe, NENTRIES*sizeof(bool), cudaMemcpyDeviceToHost);
//write everything to file
std::ofstream outfile;
outfile.open ("evolution.txt");
outfile << NEPOCHS << " , " << DIMENSIONX << " , " << DIMENSIONY << "\n";
int nepoch, nx, ny;
for (int i=0; i<NENTRIES; i++) {
if (universe[i]) {
nepoch = i/(DIMENSIONX*DIMENSIONY);
nx = (i % (DIMENSIONX*DIMENSIONY)) / DIMENSIONY;
ny = i % DIMENSIONY;
outfile << nepoch << " , " << nx << " , " << ny << "\n";
}
}
outfile.close();
//clean up
cudaFree(cuda_universe);
free(universe);
} | code for sm_80
Function : _Z6EvolvePbiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x140 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P0, PT, R5, 0x2710, PT ; /* 0x000027100500780c */
/* 0x001fe20003f06270 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x002fca00078e0205 */
/*0070*/ ISETP.GT.AND P1, PT, R4, 0x270f, PT ; /* 0x0000270f0400780c */
/* 0x000fce0003f24270 */
/*0080*/ @P0 BRA 0x130 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD R3, R0, c[0x0][0x170], R5 ; /* 0x00005c0000037a24 */
/* 0x000fca00078e0205 */
/*00c0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea8000c1e1100 */
/*00f0*/ STS.U8 [R5], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000000000 */
/*0100*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x001fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P0, PT, R5, 0x2710, PT ; /* 0x000027100500780c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 BRA 0xb0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0180*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0190*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*01a0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc4000fffe03f */
/*01c0*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*01d0*/ IABS R6, c[0x0][0x170] ; /* 0x00005c0000067a13 */
/* 0x000fe20000000000 */
/*01e0*/ BSSY B0, 0xa00 ; /* 0x0000081000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0200*/ I2F.RP R3, R6 ; /* 0x0000000600037306 */
/* 0x000e300000209400 */
/*0210*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0250*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0260*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0280*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fc600078e3cff */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*02a0*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f46270 */
/*02b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.HI.U32 R3, R5, R7, RZ ; /* 0x0000000705037227 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*02e0*/ IMAD R5, R6, R5, R7 ; /* 0x0000000506057224 */
/* 0x000fca00078e0207 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fda0003f24070 */
/*0300*/ @!P1 IMAD.IADD R5, R5, 0x1, -R6 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a06 */
/*0310*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fda0003f06070 */
/*0340*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0350*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0360*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff039a12 */
/* 0x000fc800078e33ff */
/*0370*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x040fe20007ffe0ff */
/*0380*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a03 */
/*0390*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ IMNMX R10, RZ, R4, !PT ; /* 0x00000004ff0a7217 */
/* 0x000fe20007800200 */
/*03b0*/ IMAD R6, R7, c[0x0][0x170], R0 ; /* 0x00005c0007067a24 */
/* 0x000fe200078e0200 */
/*03c0*/ IMNMX R4, R5, UR4, PT ; /* 0x0000000405047c17 */
/* 0x000fe2000b800200 */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*03e0*/ ISETP.GT.AND P0, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fe40003f04270 */
/*03f0*/ IADD3 R5, R6, -0x1, RZ ; /* 0xffffffff06057810 */
/* 0x000fc80007ffe0ff */
/*0400*/ IMNMX R5, RZ, R5, !PT ; /* 0x00000005ff057217 */
/* 0x000fce0007800200 */
/*0410*/ @P0 BRA 0x9f0 ; /* 0x000005d000000947 */
/* 0x000fea0003800000 */
/*0420*/ ULDC UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000800 */
/*0430*/ IADD3 R7, -R6.reuse, -0x2, RZ ; /* 0xfffffffe06077810 */
/* 0x040fe20007ffe1ff */
/*0440*/ UIADD3 UR6, -UR6, URZ, URZ ; /* 0x0000003f06067290 */
/* 0x000fe2000fffe13f */
/*0450*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */
/* 0x000fe400078e33ff */
/*0460*/ IADD3 R14, R6, 0x1, RZ ; /* 0x00000001060e7810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R11, R5, 0x2, RZ ; /* 0x00000002050b7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ IMNMX R8, R7, UR6, !PT ; /* 0x0000000607087c17 */
/* 0x000fe2000f800200 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*04a0*/ IADD3 R12, R5, 0x3, RZ ; /* 0x00000003050c7810 */
/* 0x000fc40007ffe0ff */
/*04b0*/ IADD3 R13, RZ, -R5, -R8.reuse ; /* 0x80000005ff0d7210 */
/* 0x100fe20007ffe808 */
/*04c0*/ IMAD.IADD R9, R9, 0x1, -R8 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a08 */
/*04d0*/ IMNMX R14, R14, UR5, PT ; /* 0x000000050e0e7c17 */
/* 0x000fe2000b800200 */
/*04e0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*04f0*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d0d7812 */
/* 0x000fe400078ec0ff */
/*0500*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f26070 */
/*0510*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fe40007ffe0ff */
/*0520*/ ISETP.GT.AND P0, PT, R5, R14, PT ; /* 0x0000000e0500720c */
/* 0x000fe20003f04270 */
/*0530*/ BSSY B1, 0x9c0 ; /* 0x0000048000017945 */
/* 0x000fd80003800000 */
/*0540*/ @P0 BRA 0x9b0 ; /* 0x0000046000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0560*/ BSSY B2, 0x760 ; /* 0x000001f000027945 */
/* 0x000fe20003800000 */
/*0570*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fd600078e0005 */
/*0580*/ @!P0 BRA 0x750 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.NE.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe20003f05270 */
/*05a0*/ IMAD R16, R10, c[0x0][0x170], R5 ; /* 0x00005c000a107a24 */
/* 0x000fc600078e0205 */
/*05b0*/ ISETP.EQ.AND P2, PT, R6, R5, !P0 ; /* 0x000000050600720c */
/* 0x000fda0004742270 */
/*05c0*/ @!P2 LDS.U8 R15, [R16] ; /* 0x00000000100fa984 */
/* 0x000e240000000000 */
/*05d0*/ @!P2 ISETP.NE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00a20c */
/* 0x001fc80003f65270 */
/*05e0*/ @!P2 SEL R15, RZ, 0x1, !P3 ; /* 0x00000001ff0fa807 */
/* 0x000fe40005800000 */
/*05f0*/ ISETP.NE.AND P3, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe40003f65270 */
/*0600*/ @!P2 IADD3 R8, P4, R15, R8, RZ ; /* 0x000000080f08a210 */
/* 0x000fe20007f9e0ff */
/*0610*/ IMAD.MOV.U32 R15, RZ, RZ, R9 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0009 */
/*0620*/ @!P2 IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff07a224 */
/* 0x000fcc00020e0607 */
/*0630*/ @!P3 BRA 0x750 ; /* 0x000001100000b947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.EQ.AND P2, PT, R6, R9, !P0 ; /* 0x000000090600720c */
/* 0x000fda0004742270 */
/*0650*/ @!P2 LDS.U8 R15, [R16+0x1] ; /* 0x00000100100fa984 */
/* 0x000e240000000000 */
/*0660*/ @!P2 ISETP.NE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00a20c */
/* 0x001fc80003f65270 */
/*0670*/ @!P2 SEL R15, RZ, 0x1, !P3 ; /* 0x00000001ff0fa807 */
/* 0x000fe40005800000 */
/*0680*/ ISETP.NE.AND P3, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x000fe40003f65270 */
/*0690*/ @!P2 IADD3 R8, P4, R15, R8, RZ ; /* 0x000000080f08a210 */
/* 0x000fe20007f9e0ff */
/*06a0*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000b */
/*06b0*/ @!P2 IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff07a224 */
/* 0x000fcc00020e0607 */
/*06c0*/ @!P3 BRA 0x750 ; /* 0x000000800000b947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.EQ.AND P0, PT, R6, R11, !P0 ; /* 0x0000000b0600720c */
/* 0x000fda0004702270 */
/*06e0*/ @!P0 LDS.U8 R15, [R16+0x2] ; /* 0x00000200100f8984 */
/* 0x000e240000000000 */
/*06f0*/ @!P0 ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00820c */
/* 0x001fc80003f45270 */
/*0700*/ @!P0 SEL R15, RZ, 0x1, !P2 ; /* 0x00000001ff0f8807 */
/* 0x000fc80005000000 */
/*0710*/ @!P0 IADD3 R8, P2, R15, R8, RZ ; /* 0x000000080f088210 */
/* 0x000fe20007f5e0ff */
/*0720*/ IMAD.MOV.U32 R15, RZ, RZ, R12.reuse ; /* 0x000000ffff0f7224 */
/* 0x100fe400078e000c */
/*0730*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f8224 */
/* 0x000fe400078e000c */
/*0740*/ @!P0 IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff078224 */
/* 0x000fc600010e0607 */
/*0750*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0760*/ @!P1 BRA 0x9b0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD R16, R10, c[0x0][0x170], R15 ; /* 0x00005c000a107a24 */
/* 0x000fe200078e020f */
/*0780*/ ISETP.NE.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe20003f05270 */
/*0790*/ IMAD.IADD R20, R15, 0x1, -R6 ; /* 0x000000010f147824 */
/* 0x000fc600078e0a06 */
/*07a0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ ISETP.EQ.AND P5, PT, R20, RZ, !P0 ; /* 0x000000ff1400720c */
/* 0x000fe400047a2270 */
/*07c0*/ IADD3 R17, R15.reuse, 0x1, RZ ; /* 0x000000010f117810 */
/* 0x040fe40007ffe0ff */
/*07d0*/ IADD3 R19, R15.reuse, 0x2, RZ ; /* 0x000000020f137810 */
/* 0x040fe40007ffe0ff */
/*07e0*/ ISETP.EQ.AND P2, PT, R6.reuse, R17, !P0 ; /* 0x000000110600720c */
/* 0x040fe40004742270 */
/*07f0*/ IADD3 R23, R15, 0x3, RZ ; /* 0x000000030f177810 */
/* 0x000fe40007ffe0ff */
/*0800*/ ISETP.EQ.AND P3, PT, R6, R19, !P0 ; /* 0x000000130600720c */
/* 0x000fc40004762270 */
/*0810*/ ISETP.EQ.AND P4, PT, R6, R23, !P0 ; /* 0x000000170600720c */
/* 0x000fe20004782270 */
/*0820*/ @!P5 LDS.U8 R21, [R16+-0x1] ; /* 0xffffff001015d984 */
/* 0x000e220000000000 */
/*0830*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*0840*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fc60007ffe0ff */
/*0850*/ @!P2 LDS.U8 R17, [R16] ; /* 0x000000001011a984 */
/* 0x000e680000000000 */
/*0860*/ @!P3 LDS.U8 R18, [R16+0x1] ; /* 0x000001001012b984 */
/* 0x000ea80000000000 */
/*0870*/ @!P4 LDS.U8 R19, [R16+0x2] ; /* 0x000002001013c984 */
/* 0x0007240000000000 */
/*0880*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x008fc40007ffe0ff */
/*0890*/ @!P5 ISETP.NE.AND P6, PT, R21, RZ, PT ; /* 0x000000ff1500d20c */
/* 0x001fc80003fc5270 */
/*08a0*/ @!P5 SEL R21, RZ, 0x1, !P6 ; /* 0x00000001ff15d807 */
/* 0x000fc80007000000 */
/*08b0*/ @!P5 IADD3 R8, P6, R21, R8, RZ ; /* 0x000000081508d210 */
/* 0x000fca0007fde0ff */
/*08c0*/ @!P5 IMAD.X R7, RZ, RZ, R7, P6 ; /* 0x000000ffff07d224 */
/* 0x000fe200030e0607 */
/*08d0*/ @!P2 ISETP.NE.AND P5, PT, R17, RZ, PT ; /* 0x000000ff1100a20c */
/* 0x002fe40003fa5270 */
/*08e0*/ @!P3 ISETP.NE.AND P6, PT, R18, RZ, PT ; /* 0x000000ff1200b20c */
/* 0x004fe40003fc5270 */
/*08f0*/ @!P2 SEL R17, RZ, 0x1, !P5 ; /* 0x00000001ff11a807 */
/* 0x000fe40006800000 */
/*0900*/ @!P4 ISETP.NE.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300c20c */
/* 0x010fe40003fa5270 */
/*0910*/ @!P3 SEL R19, RZ, 0x1, !P6 ; /* 0x00000001ff13b807 */
/* 0x000fe40007000000 */
/*0920*/ @!P2 IADD3 R8, P6, R17, R8, RZ ; /* 0x000000081108a210 */
/* 0x000fc40007fde0ff */
/*0930*/ @!P4 SEL R17, RZ, 0x1, !P5 ; /* 0x00000001ff11c807 */
/* 0x000fe40006800000 */
/*0940*/ @!P3 IADD3 R8, P5, R19, R8, RZ ; /* 0x000000081308b210 */
/* 0x000fe20007fbe0ff */
/*0950*/ @!P2 IMAD.X R7, RZ, RZ, R7, P6 ; /* 0x000000ffff07a224 */
/* 0x000fe200030e0607 */
/*0960*/ ISETP.GE.AND P2, PT, R23, R14, PT ; /* 0x0000000e1700720c */
/* 0x000fe40003f46270 */
/*0970*/ @!P4 IADD3 R8, P6, R17, R8, RZ ; /* 0x000000081108c210 */
/* 0x000fe20007fde0ff */
/*0980*/ @!P3 IMAD.X R7, RZ, RZ, R7, P5 ; /* 0x000000ffff07b224 */
/* 0x000fc800028e0607 */
/*0990*/ @!P4 IMAD.X R7, RZ, RZ, R7, P6 ; /* 0x000000ffff07c224 */
/* 0x000fcc00030e0607 */
/*09a0*/ @!P2 BRA 0x7b0 ; /* 0xfffffe000000a947 */
/* 0x000fea000383ffff */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ ISETP.GE.AND P0, PT, R10.reuse, R4, PT ; /* 0x000000040a00720c */
/* 0x040fe40003f06270 */
/*09d0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fd60007ffe0ff */
/*09e0*/ @!P0 BRA 0x520 ; /* 0xfffffb3000008947 */
/* 0x000fea000383ffff */
/*09f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a00*/ IMAD R9, R3, c[0x0][0x170], R6 ; /* 0x00005c0003097a24 */
/* 0x000fe200078e0206 */
/*0a10*/ ISETP.EQ.U32.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f22070 */
/*0a20*/ IMAD R3, R2, c[0x0][0x16c], R3 ; /* 0x00005b0002037a24 */
/* 0x000fe200078e0203 */
/*0a30*/ ISETP.EQ.U32.AND P2, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fc60003f42070 */
/*0a40*/ LDS.U8 R9, [R9] ; /* 0x0000000009097984 */
/* 0x000e220000000000 */
/*0a50*/ IMAD R3, R3, c[0x0][0x170], R6 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0206 */
/*0a60*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fc80003f05270 */
/*0a70*/ ISETP.EQ.AND.EX P0, PT, R7, RZ, P0, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000702310 */
/*0a80*/ IADD3 R4, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fe40007f3e0ff */
/*0a90*/ ISETP.EQ.OR.EX P0, PT, R7, RZ, P0, P2 ; /* 0x000000ff0700720c */
/* 0x000fe20000702720 */
/*0aa0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0ab0*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003057a11 */
/* 0x000fe400008f0eff */
/*0ac0*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fe20004000000 */
/*0ad0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fc800078e0200 */
/*0ae0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e2000c101108 */
/*0af0*/ ISETP.GE.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fda0003f06270 */
/*0b00*/ @!P0 BRA 0x1d0 ; /* 0xfffff6c000008947 */
/* 0x001fea000383ffff */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ BRA 0xb20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //nvcc -o gol gol.cu
#define NEPOCHS 1000
#define DIMENSIONX 100
#define DIMENSIONY 100
#include <stdio.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
__global__
void Evolve(bool *u, int n, int dx, int dy)
{
int n_next = n + 1;
bool active_pre, active_post;
__shared__ bool shared_u[DIMENSIONX*DIMENSIONY];
//__shared__ bool shared_u_next[DIMENSIONX*DIMENSIONY];
//copy state in shared memory
for (int i=threadIdx.x; i<DIMENSIONX*DIMENSIONY; i+=blockDim.x) {
shared_u[i] = u[n*dx*dy+i];
}
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
//get number of neighbors
size_t NActiveNeighbors = 0;
int nmin_x = max(0, i - 1);
int nmax_x = min(i + 1, dx - 1);
int nmin_y = max(0, j - 1);
int nmax_y = min(j + 1, dy - 1);
for (int ii = nmin_x; ii <= nmax_x; ii++)
for (int jj = nmin_y; jj <= nmax_y; jj++)
{
if ((i == ii) && (j == jj))
continue;
if (shared_u[ii*dy+jj]) NActiveNeighbors += 1;
}
active_pre = shared_u[i*dy+j];
active_post = false;
if (active_pre && (NActiveNeighbors == 2))
active_post = true;
else if (active_pre && (NActiveNeighbors == 3))
active_post = true;
else if ((!active_pre) && (NActiveNeighbors == 3))
active_post = true;
u[n_next*dx*dy+i*dy+j] = active_post;
}
/*
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
u[n_next*dx*dy+i*dy+j] = shared_u_next[i*dy+j];
}
__syncthreads();
*/
return;
}
bool *allocate_universe(int n, int dx, int dy)
{
int Nelements = n*dx*dy;
bool *universe = new bool[Nelements];
for (int i = 0; i < Nelements; i++)
{
universe[i] = false;
}
return universe;
}
bool glider_gun_field(int i, int j) {
if (((i%40)==1)&&((j%30)==5)) return true;
if (((i%40)==1)&&((j%30)==6)) return true;
if (((i%40)==2)&&((j%30)==5)) return true;
if (((i%40)==2)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==5)) return true;
if (((i%40)==11)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==7)) return true;
if (((i%40)==12)&&((j%30)==4)) return true;
if (((i%40)==12)&&((j%30)==8)) return true;
if (((i%40)==13)&&((j%30)==3)) return true;
if (((i%40)==13)&&((j%30)==9)) return true;
if (((i%40)==14)&&((j%30)==3)) return true;
if (((i%40)==14)&&((j%30)==9)) return true;
if (((i%40)==15)&&((j%30)==6)) return true;
if (((i%40)==16)&&((j%30)==4)) return true;
if (((i%40)==16)&&((j%30)==8)) return true;
if (((i%40)==17)&&((j%30)==5)) return true;
if (((i%40)==17)&&((j%30)==6)) return true;
if (((i%40)==17)&&((j%30)==7)) return true;
if (((i%40)==18)&&((j%30)==6)) return true;
if (((i%40)==21)&&((j%30)==3)) return true;
if (((i%40)==21)&&((j%30)==4)) return true;
if (((i%40)==21)&&((j%30)==5)) return true;
if (((i%40)==22)&&((j%30)==3)) return true;
if (((i%40)==22)&&((j%30)==4)) return true;
if (((i%40)==22)&&((j%30)==5)) return true;
if (((i%40)==23)&&((j%30)==2)) return true;
if (((i%40)==23)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==1)) return true;
if (((i%40)==25)&&((j%30)==2)) return true;
if (((i%40)==25)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==7)) return true;
if (((i%40)==35)&&((j%30)==3)) return true;
if (((i%40)==35)&&((j%30)==4)) return true;
if (((i%40)==36)&&((j%30)==3)) return true;
if (((i%40)==36)&&((j%30)==4)) return true;
return false;
}
void set_initial_conditions(bool *u, int dx, int dy, float p)
{
for (int i = 0; i < dx; i++)
for (int j = 0; j < dy; j++)
{
//float _value = (rand() % 10000)/10000.;//((i*173+j*51) % 100) / 100.;
//if (_value < p)
if (glider_gun_field(i, j))
{
u[i*dy+j] = true;
}
}
rand();
}
int main(void)
{
long int NENTRIES = NEPOCHS*DIMENSIONX*DIMENSIONY;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
std::cout << "Defining the universe and creating the initial conditions" << std::endl;
bool *universe = allocate_universe(NEPOCHS, DIMENSIONX, DIMENSIONY);
set_initial_conditions(universe, DIMENSIONX, DIMENSIONY, 0.25);
bool *cuda_universe;
cudaMalloc((void**)&cuda_universe, NENTRIES*sizeof(bool));
cudaMemcpy(cuda_universe, universe, NENTRIES*sizeof(bool), cudaMemcpyHostToDevice);
cudaEventRecord(start);
for (int n=0; n<NEPOCHS-1; n++) {
Evolve<<<32, 64>>>(cuda_universe, n, DIMENSIONX, DIMENSIONY);
cudaDeviceSynchronize();
}
cudaEventRecord(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Total execution time (ms): %f\n ", milliseconds);
cudaMemcpy(universe, cuda_universe, NENTRIES*sizeof(bool), cudaMemcpyDeviceToHost);
//write everything to file
std::ofstream outfile;
outfile.open ("evolution.txt");
outfile << NEPOCHS << " , " << DIMENSIONX << " , " << DIMENSIONY << "\n";
int nepoch, nx, ny;
for (int i=0; i<NENTRIES; i++) {
if (universe[i]) {
nepoch = i/(DIMENSIONX*DIMENSIONY);
nx = (i % (DIMENSIONX*DIMENSIONY)) / DIMENSIONY;
ny = i % DIMENSIONY;
outfile << nepoch << " , " << nx << " , " << ny << "\n";
}
}
outfile.close();
//clean up
cudaFree(cuda_universe);
free(universe);
} | .file "tmpxft_000f0cf3_00000000-6_gol.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17allocate_universeiii
.type _Z17allocate_universeiii, @function
_Z17allocate_universeiii:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
imull %esi, %edi
imull %edx, %edi
movl %edi, %ebp
movslq %edi, %rbx
movq %rbx, %rdi
call _Znam@PLT
testl %ebp, %ebp
jle .L3
movq %rax, %rdx
leaq (%rbx,%rax), %rcx
.L5:
movb $0, (%rdx)
addq $1, %rdx
cmpq %rcx, %rdx
jne .L5
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _Z17allocate_universeiii, .-_Z17allocate_universeiii
.globl _Z16glider_gun_fieldii
.type _Z16glider_gun_fieldii, @function
_Z16glider_gun_fieldii:
.LFB3801:
.cfi_startproc
endbr64
movl %esi, %edx
movslq %edi, %rax
imulq $1717986919, %rax, %rax
sarq $36, %rax
movl %edi, %ecx
sarl $31, %ecx
subl %ecx, %eax
leal (%rax,%rax,4), %ecx
sall $3, %ecx
movl %edi, %eax
subl %ecx, %eax
cmpl $1, %eax
je .L46
cmpl $2, %eax
je .L47
cmpl $11, %eax
je .L48
cmpl $12, %eax
je .L49
cmpl $13, %eax
je .L50
cmpl $14, %eax
je .L51
cmpl $15, %eax
je .L52
cmpl $16, %eax
je .L53
cmpl $17, %eax
je .L54
cmpl $18, %eax
je .L55
cmpl $21, %eax
je .L56
cmpl $22, %eax
je .L57
cmpl $23, %eax
je .L58
cmpl $25, %eax
je .L59
cmpl $35, %eax
je .L60
movl $0, %ecx
cmpl $36, %eax
jne .L8
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
sete %cl
jmp .L8
.L46:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
sete %cl
.L8:
movl %ecx, %eax
ret
.L47:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
sete %cl
jmp .L8
.L48:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
je .L8
cmpl $7, %eax
sete %cl
jmp .L8
.L49:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $4, %eax
je .L8
cmpl $8, %eax
sete %cl
jmp .L8
.L50:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $9, %eax
sete %cl
jmp .L8
.L51:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $9, %eax
sete %cl
jmp .L8
.L52:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %eax
subl %eax, %edx
cmpl $6, %edx
sete %cl
jmp .L8
.L53:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $4, %eax
je .L8
cmpl $8, %eax
sete %cl
jmp .L8
.L54:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
je .L8
cmpl $7, %eax
sete %cl
jmp .L8
.L55:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %eax
subl %eax, %edx
cmpl $6, %edx
sete %cl
jmp .L8
.L56:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
je .L8
cmpl $5, %eax
sete %cl
jmp .L8
.L57:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
je .L8
cmpl $5, %eax
sete %cl
jmp .L8
.L58:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $2, %eax
je .L8
cmpl $6, %eax
sete %cl
jmp .L8
.L59:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $1, %eax
je .L8
cmpl $2, %eax
je .L8
cmpl $6, %eax
je .L8
cmpl $7, %eax
sete %cl
jmp .L8
.L60:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
sete %cl
jmp .L8
.cfi_endproc
.LFE3801:
.size _Z16glider_gun_fieldii, .-_Z16glider_gun_fieldii
.globl _Z22set_initial_conditionsPbiif
.type _Z22set_initial_conditionsPbiif, @function
_Z22set_initial_conditionsPbiif:
.LFB3802:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %esi, %esi
jle .L62
movq %rdi, %r14
movl %esi, %r15d
movl %edx, %r12d
movl $0, %r13d
movl $0, %ebp
jmp .L63
.L64:
addl $1, %ebx
cmpl %ebx, %r12d
je .L66
.L65:
movl %ebx, %esi
movl %ebp, %edi
call _Z16glider_gun_fieldii
testb %al, %al
je .L64
leal (%rbx,%r13), %eax
cltq
movb $1, (%r14,%rax)
jmp .L64
.L66:
addl $1, %ebp
addl %r12d, %r13d
cmpl %ebp, %r15d
je .L62
.L63:
movl $0, %ebx
testl %r12d, %r12d
jg .L65
jmp .L66
.L62:
call rand@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3802:
.size _Z22set_initial_conditionsPbiif, .-_Z22set_initial_conditionsPbiif
.globl _Z28__device_stub__Z6EvolvePbiiiPbiii
.type _Z28__device_stub__Z6EvolvePbiiiPbiii, @function
_Z28__device_stub__Z6EvolvePbiiiPbiii:
.LFB3828:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6EvolvePbiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z28__device_stub__Z6EvolvePbiiiPbiii, .-_Z28__device_stub__Z6EvolvePbiiiPbiii
.globl _Z6EvolvePbiii
.type _Z6EvolvePbiii, @function
_Z6EvolvePbiii:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6EvolvePbiiiPbiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z6EvolvePbiii, .-_Z6EvolvePbiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6EvolvePbiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6EvolvePbiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Defining the universe and creating the initial conditions"
.align 8
.LC4:
.string "Total execution time (ms): %f\n "
.section .rodata.str1.1
.LC5:
.string "evolution.txt"
.LC6:
.string " , "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3803:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3803
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
.LEHB0:
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $100, %edx
movl $100, %esi
movl $1000, %edi
call _Z17allocate_universeiii
movq %rax, %r14
movss .LC2(%rip), %xmm0
movl $100, %edx
movl $100, %esi
movq %rax, %rdi
call _Z22set_initial_conditionsPbiif
leaq 32(%rsp), %rdi
movl $10000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $10000000, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L83
.L82:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
cmpl $999, %ebx
je .L94
.L83:
movl $64, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L82
movl $100, %ecx
movl $100, %edx
movl %ebx, %esi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6EvolvePbiiiPbiii
jmp .L82
.L94:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $10000000, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq %rbx, %rdi
movl $1000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $100, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $100, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %ebx
leaq 64(%rsp), %rax
movq %rax, 8(%rsp)
leaq .LC6(%rip), %r15
jmp .L85
.L96:
movq %rax, %r13
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L84:
addq $1, %rbx
cmpq $10000000, %rbx
je .L95
.L85:
cmpb $0, (%r14,%rbx)
je .L84
movslq %ebx, %rbp
imulq $1759218605, %rbp, %rsi
sarq $44, %rsi
movl %ebx, %edx
sarl $31, %edx
subl %edx, %esi
imull $10000, %esi, %ecx
movl %ebx, %eax
subl %ecx, %eax
movslq %eax, %r12
imulq $1374389535, %r12, %r12
sarq $37, %r12
sarl $31, %eax
subl %eax, %r12d
imulq $1374389535, %rbp, %rbp
sarq $37, %rbp
subl %edx, %ebp
imull $100, %ebp, %eax
movl %ebx, %ebp
subl %eax, %ebp
movq 8(%rsp), %rdi
call _ZNSolsEi@PLT
jmp .L96
.L95:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
movq %r14, %rdi
call free@PLT
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L97
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L87
call __stack_chk_fail@PLT
.L87:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3803:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3803-.LLSDACSB3803
.LLSDACSB3803:
.uleb128 .LEHB0-.LFB3803
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3803
.uleb128 .LEHE1-.LEHB1
.uleb128 .L89-.LFB3803
.uleb128 0
.uleb128 .LEHB2-.LFB3803
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3803:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1048576000
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //nvcc -o gol gol.cu
#define NEPOCHS 1000
#define DIMENSIONX 100
#define DIMENSIONY 100
#include <stdio.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
__global__
void Evolve(bool *u, int n, int dx, int dy)
{
int n_next = n + 1;
bool active_pre, active_post;
__shared__ bool shared_u[DIMENSIONX*DIMENSIONY];
//__shared__ bool shared_u_next[DIMENSIONX*DIMENSIONY];
//copy state in shared memory
for (int i=threadIdx.x; i<DIMENSIONX*DIMENSIONY; i+=blockDim.x) {
shared_u[i] = u[n*dx*dy+i];
}
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
//get number of neighbors
size_t NActiveNeighbors = 0;
int nmin_x = max(0, i - 1);
int nmax_x = min(i + 1, dx - 1);
int nmin_y = max(0, j - 1);
int nmax_y = min(j + 1, dy - 1);
for (int ii = nmin_x; ii <= nmax_x; ii++)
for (int jj = nmin_y; jj <= nmax_y; jj++)
{
if ((i == ii) && (j == jj))
continue;
if (shared_u[ii*dy+jj]) NActiveNeighbors += 1;
}
active_pre = shared_u[i*dy+j];
active_post = false;
if (active_pre && (NActiveNeighbors == 2))
active_post = true;
else if (active_pre && (NActiveNeighbors == 3))
active_post = true;
else if ((!active_pre) && (NActiveNeighbors == 3))
active_post = true;
u[n_next*dx*dy+i*dy+j] = active_post;
}
/*
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
u[n_next*dx*dy+i*dy+j] = shared_u_next[i*dy+j];
}
__syncthreads();
*/
return;
}
bool *allocate_universe(int n, int dx, int dy)
{
int Nelements = n*dx*dy;
bool *universe = new bool[Nelements];
for (int i = 0; i < Nelements; i++)
{
universe[i] = false;
}
return universe;
}
bool glider_gun_field(int i, int j) {
if (((i%40)==1)&&((j%30)==5)) return true;
if (((i%40)==1)&&((j%30)==6)) return true;
if (((i%40)==2)&&((j%30)==5)) return true;
if (((i%40)==2)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==5)) return true;
if (((i%40)==11)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==7)) return true;
if (((i%40)==12)&&((j%30)==4)) return true;
if (((i%40)==12)&&((j%30)==8)) return true;
if (((i%40)==13)&&((j%30)==3)) return true;
if (((i%40)==13)&&((j%30)==9)) return true;
if (((i%40)==14)&&((j%30)==3)) return true;
if (((i%40)==14)&&((j%30)==9)) return true;
if (((i%40)==15)&&((j%30)==6)) return true;
if (((i%40)==16)&&((j%30)==4)) return true;
if (((i%40)==16)&&((j%30)==8)) return true;
if (((i%40)==17)&&((j%30)==5)) return true;
if (((i%40)==17)&&((j%30)==6)) return true;
if (((i%40)==17)&&((j%30)==7)) return true;
if (((i%40)==18)&&((j%30)==6)) return true;
if (((i%40)==21)&&((j%30)==3)) return true;
if (((i%40)==21)&&((j%30)==4)) return true;
if (((i%40)==21)&&((j%30)==5)) return true;
if (((i%40)==22)&&((j%30)==3)) return true;
if (((i%40)==22)&&((j%30)==4)) return true;
if (((i%40)==22)&&((j%30)==5)) return true;
if (((i%40)==23)&&((j%30)==2)) return true;
if (((i%40)==23)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==1)) return true;
if (((i%40)==25)&&((j%30)==2)) return true;
if (((i%40)==25)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==7)) return true;
if (((i%40)==35)&&((j%30)==3)) return true;
if (((i%40)==35)&&((j%30)==4)) return true;
if (((i%40)==36)&&((j%30)==3)) return true;
if (((i%40)==36)&&((j%30)==4)) return true;
return false;
}
void set_initial_conditions(bool *u, int dx, int dy, float p)
{
for (int i = 0; i < dx; i++)
for (int j = 0; j < dy; j++)
{
//float _value = (rand() % 10000)/10000.;//((i*173+j*51) % 100) / 100.;
//if (_value < p)
if (glider_gun_field(i, j))
{
u[i*dy+j] = true;
}
}
rand();
}
int main(void)
{
long int NENTRIES = NEPOCHS*DIMENSIONX*DIMENSIONY;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
std::cout << "Defining the universe and creating the initial conditions" << std::endl;
bool *universe = allocate_universe(NEPOCHS, DIMENSIONX, DIMENSIONY);
set_initial_conditions(universe, DIMENSIONX, DIMENSIONY, 0.25);
bool *cuda_universe;
cudaMalloc((void**)&cuda_universe, NENTRIES*sizeof(bool));
cudaMemcpy(cuda_universe, universe, NENTRIES*sizeof(bool), cudaMemcpyHostToDevice);
cudaEventRecord(start);
for (int n=0; n<NEPOCHS-1; n++) {
Evolve<<<32, 64>>>(cuda_universe, n, DIMENSIONX, DIMENSIONY);
cudaDeviceSynchronize();
}
cudaEventRecord(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Total execution time (ms): %f\n ", milliseconds);
cudaMemcpy(universe, cuda_universe, NENTRIES*sizeof(bool), cudaMemcpyDeviceToHost);
//write everything to file
std::ofstream outfile;
outfile.open ("evolution.txt");
outfile << NEPOCHS << " , " << DIMENSIONX << " , " << DIMENSIONY << "\n";
int nepoch, nx, ny;
for (int i=0; i<NENTRIES; i++) {
if (universe[i]) {
nepoch = i/(DIMENSIONX*DIMENSIONY);
nx = (i % (DIMENSIONX*DIMENSIONY)) / DIMENSIONY;
ny = i % DIMENSIONY;
outfile << nepoch << " , " << nx << " , " << ny << "\n";
}
}
outfile.close();
//clean up
cudaFree(cuda_universe);
free(universe);
} | //nvcc -o gol gol.cu
#define NEPOCHS 1000
#define DIMENSIONX 100
#define DIMENSIONY 100
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
__global__
void Evolve(bool *u, int n, int dx, int dy)
{
int n_next = n + 1;
bool active_pre, active_post;
__shared__ bool shared_u[DIMENSIONX*DIMENSIONY];
//__shared__ bool shared_u_next[DIMENSIONX*DIMENSIONY];
//copy state in shared memory
for (int i=threadIdx.x; i<DIMENSIONX*DIMENSIONY; i+=blockDim.x) {
shared_u[i] = u[n*dx*dy+i];
}
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
//get number of neighbors
size_t NActiveNeighbors = 0;
int nmin_x = max(0, i - 1);
int nmax_x = min(i + 1, dx - 1);
int nmin_y = max(0, j - 1);
int nmax_y = min(j + 1, dy - 1);
for (int ii = nmin_x; ii <= nmax_x; ii++)
for (int jj = nmin_y; jj <= nmax_y; jj++)
{
if ((i == ii) && (j == jj))
continue;
if (shared_u[ii*dy+jj]) NActiveNeighbors += 1;
}
active_pre = shared_u[i*dy+j];
active_post = false;
if (active_pre && (NActiveNeighbors == 2))
active_post = true;
else if (active_pre && (NActiveNeighbors == 3))
active_post = true;
else if ((!active_pre) && (NActiveNeighbors == 3))
active_post = true;
u[n_next*dx*dy+i*dy+j] = active_post;
}
/*
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
u[n_next*dx*dy+i*dy+j] = shared_u_next[i*dy+j];
}
__syncthreads();
*/
return;
}
bool *allocate_universe(int n, int dx, int dy)
{
int Nelements = n*dx*dy;
bool *universe = new bool[Nelements];
for (int i = 0; i < Nelements; i++)
{
universe[i] = false;
}
return universe;
}
bool glider_gun_field(int i, int j) {
if (((i%40)==1)&&((j%30)==5)) return true;
if (((i%40)==1)&&((j%30)==6)) return true;
if (((i%40)==2)&&((j%30)==5)) return true;
if (((i%40)==2)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==5)) return true;
if (((i%40)==11)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==7)) return true;
if (((i%40)==12)&&((j%30)==4)) return true;
if (((i%40)==12)&&((j%30)==8)) return true;
if (((i%40)==13)&&((j%30)==3)) return true;
if (((i%40)==13)&&((j%30)==9)) return true;
if (((i%40)==14)&&((j%30)==3)) return true;
if (((i%40)==14)&&((j%30)==9)) return true;
if (((i%40)==15)&&((j%30)==6)) return true;
if (((i%40)==16)&&((j%30)==4)) return true;
if (((i%40)==16)&&((j%30)==8)) return true;
if (((i%40)==17)&&((j%30)==5)) return true;
if (((i%40)==17)&&((j%30)==6)) return true;
if (((i%40)==17)&&((j%30)==7)) return true;
if (((i%40)==18)&&((j%30)==6)) return true;
if (((i%40)==21)&&((j%30)==3)) return true;
if (((i%40)==21)&&((j%30)==4)) return true;
if (((i%40)==21)&&((j%30)==5)) return true;
if (((i%40)==22)&&((j%30)==3)) return true;
if (((i%40)==22)&&((j%30)==4)) return true;
if (((i%40)==22)&&((j%30)==5)) return true;
if (((i%40)==23)&&((j%30)==2)) return true;
if (((i%40)==23)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==1)) return true;
if (((i%40)==25)&&((j%30)==2)) return true;
if (((i%40)==25)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==7)) return true;
if (((i%40)==35)&&((j%30)==3)) return true;
if (((i%40)==35)&&((j%30)==4)) return true;
if (((i%40)==36)&&((j%30)==3)) return true;
if (((i%40)==36)&&((j%30)==4)) return true;
return false;
}
void set_initial_conditions(bool *u, int dx, int dy, float p)
{
for (int i = 0; i < dx; i++)
for (int j = 0; j < dy; j++)
{
//float _value = (rand() % 10000)/10000.;//((i*173+j*51) % 100) / 100.;
//if (_value < p)
if (glider_gun_field(i, j))
{
u[i*dy+j] = true;
}
}
rand();
}
int main(void)
{
long int NENTRIES = NEPOCHS*DIMENSIONX*DIMENSIONY;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
std::cout << "Defining the universe and creating the initial conditions" << std::endl;
bool *universe = allocate_universe(NEPOCHS, DIMENSIONX, DIMENSIONY);
set_initial_conditions(universe, DIMENSIONX, DIMENSIONY, 0.25);
bool *cuda_universe;
hipMalloc((void**)&cuda_universe, NENTRIES*sizeof(bool));
hipMemcpy(cuda_universe, universe, NENTRIES*sizeof(bool), hipMemcpyHostToDevice);
hipEventRecord(start);
for (int n=0; n<NEPOCHS-1; n++) {
Evolve<<<32, 64>>>(cuda_universe, n, DIMENSIONX, DIMENSIONY);
hipDeviceSynchronize();
}
hipEventRecord(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Total execution time (ms): %f\n ", milliseconds);
hipMemcpy(universe, cuda_universe, NENTRIES*sizeof(bool), hipMemcpyDeviceToHost);
//write everything to file
std::ofstream outfile;
outfile.open ("evolution.txt");
outfile << NEPOCHS << " , " << DIMENSIONX << " , " << DIMENSIONY << "\n";
int nepoch, nx, ny;
for (int i=0; i<NENTRIES; i++) {
if (universe[i]) {
nepoch = i/(DIMENSIONX*DIMENSIONY);
nx = (i % (DIMENSIONX*DIMENSIONY)) / DIMENSIONY;
ny = i % DIMENSIONY;
outfile << nepoch << " , " << nx << " , " << ny << "\n";
}
}
outfile.close();
//clean up
hipFree(cuda_universe);
free(universe);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //nvcc -o gol gol.cu
#define NEPOCHS 1000
#define DIMENSIONX 100
#define DIMENSIONY 100
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
__global__
void Evolve(bool *u, int n, int dx, int dy)
{
int n_next = n + 1;
bool active_pre, active_post;
__shared__ bool shared_u[DIMENSIONX*DIMENSIONY];
//__shared__ bool shared_u_next[DIMENSIONX*DIMENSIONY];
//copy state in shared memory
for (int i=threadIdx.x; i<DIMENSIONX*DIMENSIONY; i+=blockDim.x) {
shared_u[i] = u[n*dx*dy+i];
}
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
//get number of neighbors
size_t NActiveNeighbors = 0;
int nmin_x = max(0, i - 1);
int nmax_x = min(i + 1, dx - 1);
int nmin_y = max(0, j - 1);
int nmax_y = min(j + 1, dy - 1);
for (int ii = nmin_x; ii <= nmax_x; ii++)
for (int jj = nmin_y; jj <= nmax_y; jj++)
{
if ((i == ii) && (j == jj))
continue;
if (shared_u[ii*dy+jj]) NActiveNeighbors += 1;
}
active_pre = shared_u[i*dy+j];
active_post = false;
if (active_pre && (NActiveNeighbors == 2))
active_post = true;
else if (active_pre && (NActiveNeighbors == 3))
active_post = true;
else if ((!active_pre) && (NActiveNeighbors == 3))
active_post = true;
u[n_next*dx*dy+i*dy+j] = active_post;
}
/*
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
u[n_next*dx*dy+i*dy+j] = shared_u_next[i*dy+j];
}
__syncthreads();
*/
return;
}
bool *allocate_universe(int n, int dx, int dy)
{
int Nelements = n*dx*dy;
bool *universe = new bool[Nelements];
for (int i = 0; i < Nelements; i++)
{
universe[i] = false;
}
return universe;
}
bool glider_gun_field(int i, int j) {
if (((i%40)==1)&&((j%30)==5)) return true;
if (((i%40)==1)&&((j%30)==6)) return true;
if (((i%40)==2)&&((j%30)==5)) return true;
if (((i%40)==2)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==5)) return true;
if (((i%40)==11)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==7)) return true;
if (((i%40)==12)&&((j%30)==4)) return true;
if (((i%40)==12)&&((j%30)==8)) return true;
if (((i%40)==13)&&((j%30)==3)) return true;
if (((i%40)==13)&&((j%30)==9)) return true;
if (((i%40)==14)&&((j%30)==3)) return true;
if (((i%40)==14)&&((j%30)==9)) return true;
if (((i%40)==15)&&((j%30)==6)) return true;
if (((i%40)==16)&&((j%30)==4)) return true;
if (((i%40)==16)&&((j%30)==8)) return true;
if (((i%40)==17)&&((j%30)==5)) return true;
if (((i%40)==17)&&((j%30)==6)) return true;
if (((i%40)==17)&&((j%30)==7)) return true;
if (((i%40)==18)&&((j%30)==6)) return true;
if (((i%40)==21)&&((j%30)==3)) return true;
if (((i%40)==21)&&((j%30)==4)) return true;
if (((i%40)==21)&&((j%30)==5)) return true;
if (((i%40)==22)&&((j%30)==3)) return true;
if (((i%40)==22)&&((j%30)==4)) return true;
if (((i%40)==22)&&((j%30)==5)) return true;
if (((i%40)==23)&&((j%30)==2)) return true;
if (((i%40)==23)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==1)) return true;
if (((i%40)==25)&&((j%30)==2)) return true;
if (((i%40)==25)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==7)) return true;
if (((i%40)==35)&&((j%30)==3)) return true;
if (((i%40)==35)&&((j%30)==4)) return true;
if (((i%40)==36)&&((j%30)==3)) return true;
if (((i%40)==36)&&((j%30)==4)) return true;
return false;
}
void set_initial_conditions(bool *u, int dx, int dy, float p)
{
for (int i = 0; i < dx; i++)
for (int j = 0; j < dy; j++)
{
//float _value = (rand() % 10000)/10000.;//((i*173+j*51) % 100) / 100.;
//if (_value < p)
if (glider_gun_field(i, j))
{
u[i*dy+j] = true;
}
}
rand();
}
int main(void)
{
long int NENTRIES = NEPOCHS*DIMENSIONX*DIMENSIONY;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
std::cout << "Defining the universe and creating the initial conditions" << std::endl;
bool *universe = allocate_universe(NEPOCHS, DIMENSIONX, DIMENSIONY);
set_initial_conditions(universe, DIMENSIONX, DIMENSIONY, 0.25);
bool *cuda_universe;
hipMalloc((void**)&cuda_universe, NENTRIES*sizeof(bool));
hipMemcpy(cuda_universe, universe, NENTRIES*sizeof(bool), hipMemcpyHostToDevice);
hipEventRecord(start);
for (int n=0; n<NEPOCHS-1; n++) {
Evolve<<<32, 64>>>(cuda_universe, n, DIMENSIONX, DIMENSIONY);
hipDeviceSynchronize();
}
hipEventRecord(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Total execution time (ms): %f\n ", milliseconds);
hipMemcpy(universe, cuda_universe, NENTRIES*sizeof(bool), hipMemcpyDeviceToHost);
//write everything to file
std::ofstream outfile;
outfile.open ("evolution.txt");
outfile << NEPOCHS << " , " << DIMENSIONX << " , " << DIMENSIONY << "\n";
int nepoch, nx, ny;
for (int i=0; i<NENTRIES; i++) {
if (universe[i]) {
nepoch = i/(DIMENSIONX*DIMENSIONY);
nx = (i % (DIMENSIONX*DIMENSIONY)) / DIMENSIONY;
ny = i % DIMENSIONY;
outfile << nepoch << " , " << nx << " , " << ny << "\n";
}
}
outfile.close();
//clean up
hipFree(cuda_universe);
free(universe);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6EvolvePbiii
.globl _Z6EvolvePbiii
.p2align 8
.type _Z6EvolvePbiii,@function
_Z6EvolvePbiii:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v3, v0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s9, s8, s3
s_and_b32 s8, s2, 0xffff
s_ashr_i32 s2, s9, 31
s_add_u32 s9, s4, s9
s_addc_u32 s2, s5, s2
v_add_co_u32 v1, s9, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s2, 0, s9
s_mov_b32 s9, s10
.LBB0_1:
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, s2, v1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s10, v2, s2
s_waitcnt vmcnt(0)
ds_store_b8 v3, v4
v_add_nc_u32_e32 v3, s8, v3
v_cmp_lt_u32_e32 vcc_lo, 0x270f, v3
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x24
s_add_u32 s0, s0, 24
s_addc_u32 s1, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2710, v1
s_cbranch_execz .LBB0_19
s_ashr_i32 s2, s3, 31
s_load_b32 s0, s[0:1], 0x0
s_add_i32 s8, s3, s2
s_add_i32 s9, s3, -1
s_xor_b32 s8, s8, s2
s_mov_b32 s11, 0
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s1, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s0, s10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s1, v0
s_add_i32 s1, s6, 1
s_add_i32 s6, s7, -1
s_mul_i32 s7, s1, s7
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v2
s_branch .LBB0_6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s1, s1, exec_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v5, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, s3, v[0:1]
v_add_nc_u32_e32 v1, s10, v1
v_cmp_lt_i32_e32 vcc_lo, 0x270f, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v2
v_add_co_u32 v2, s0, s4, v2
s_or_b32 s11, vcc_lo, s11
v_add_co_ci_u32_e64 v3, s0, s5, v0, s0
v_cndmask_b32_e64 v0, 0, 1, s1
global_store_b8 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_19
.LBB0_6:
v_ashrrev_i32_e32 v0, 31, v1
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
v_xor_b32_e32 v2, v2, v0
v_xor_b32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v4
v_mul_lo_u32 v5, v3, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_subrev_nc_u32_e32 v6, s8, v2
v_cmp_le_u32_e32 vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v2
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v5, vcc_lo
v_xor_b32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v0
v_mul_lo_u32 v3, v5, s3
v_max_i32_e32 v0, 1, v5
v_add_nc_u32_e32 v2, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, -1, v0
v_min_i32_e32 v6, s6, v2
v_sub_nc_u32_e32 v0, v1, v3
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_4)
v_cmpx_le_i32_e64 v7, v6
s_cbranch_execz .LBB0_16
v_max_i32_e32 v2, 1, v0
v_add_nc_u32_e32 v3, 1, v0
v_mul_lo_u32 v10, s3, v7
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, -1, v2
v_min_i32_e32 v9, s9, v3
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, v8, v9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v11, 1, v7
v_cmp_ge_i32_e64 s0, v7, v6
v_dual_mov_b32 v7, v11 :: v_dual_add_nc_u32 v10, s3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s12, s0, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_15
.LBB0_10:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_9
v_cmp_eq_u32_e64 s0, v5, v7
v_mov_b32_e32 v11, v8
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_2)
s_xor_b32 s15, s0, -1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v12, 1, v11
v_cmp_ge_i32_e64 s0, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v12
s_or_b32 s14, s0, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_8
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, v0, v11
s_or_b32 s0, s15, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v12, v10, v11
ds_load_u8 v12, v12
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v12, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, v2, v12
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_branch .LBB0_12
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s12
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mad_u64_u32 v[6:7], null, v5, s3, v[0:1]
v_cmp_ne_u64_e64 s0, 2, v[2:3]
ds_load_u8 v6, v6
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s1, 0, v6
v_cmp_ne_u16_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s0, s1, s0
s_mov_b32 s1, -1
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_5
v_cmp_eq_u64_e64 s0, 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, vcc_lo, s0
s_xor_b32 s14, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_4
s_xor_b32 s1, vcc_lo, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_or_not1_b32 s1, s0, exec_lo
s_branch .LBB0_4
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6EvolvePbiii
.amdhsa_group_segment_fixed_size 10000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6EvolvePbiii, .Lfunc_end0-_Z6EvolvePbiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 10000
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6EvolvePbiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z6EvolvePbiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //nvcc -o gol gol.cu
#define NEPOCHS 1000
#define DIMENSIONX 100
#define DIMENSIONY 100
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
__global__
void Evolve(bool *u, int n, int dx, int dy)
{
int n_next = n + 1;
bool active_pre, active_post;
__shared__ bool shared_u[DIMENSIONX*DIMENSIONY];
//__shared__ bool shared_u_next[DIMENSIONX*DIMENSIONY];
//copy state in shared memory
for (int i=threadIdx.x; i<DIMENSIONX*DIMENSIONY; i+=blockDim.x) {
shared_u[i] = u[n*dx*dy+i];
}
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
//get number of neighbors
size_t NActiveNeighbors = 0;
int nmin_x = max(0, i - 1);
int nmax_x = min(i + 1, dx - 1);
int nmin_y = max(0, j - 1);
int nmax_y = min(j + 1, dy - 1);
for (int ii = nmin_x; ii <= nmax_x; ii++)
for (int jj = nmin_y; jj <= nmax_y; jj++)
{
if ((i == ii) && (j == jj))
continue;
if (shared_u[ii*dy+jj]) NActiveNeighbors += 1;
}
active_pre = shared_u[i*dy+j];
active_post = false;
if (active_pre && (NActiveNeighbors == 2))
active_post = true;
else if (active_pre && (NActiveNeighbors == 3))
active_post = true;
else if ((!active_pre) && (NActiveNeighbors == 3))
active_post = true;
u[n_next*dx*dy+i*dy+j] = active_post;
}
/*
__syncthreads();
for (int entry_index=threadIdx.x+blockIdx.x*blockDim.x; entry_index<DIMENSIONX*DIMENSIONY; entry_index+=blockDim.x*gridDim.x) {
int i = entry_index / dy;
int j = entry_index % dy;
u[n_next*dx*dy+i*dy+j] = shared_u_next[i*dy+j];
}
__syncthreads();
*/
return;
}
bool *allocate_universe(int n, int dx, int dy)
{
int Nelements = n*dx*dy;
bool *universe = new bool[Nelements];
for (int i = 0; i < Nelements; i++)
{
universe[i] = false;
}
return universe;
}
bool glider_gun_field(int i, int j) {
if (((i%40)==1)&&((j%30)==5)) return true;
if (((i%40)==1)&&((j%30)==6)) return true;
if (((i%40)==2)&&((j%30)==5)) return true;
if (((i%40)==2)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==5)) return true;
if (((i%40)==11)&&((j%30)==6)) return true;
if (((i%40)==11)&&((j%30)==7)) return true;
if (((i%40)==12)&&((j%30)==4)) return true;
if (((i%40)==12)&&((j%30)==8)) return true;
if (((i%40)==13)&&((j%30)==3)) return true;
if (((i%40)==13)&&((j%30)==9)) return true;
if (((i%40)==14)&&((j%30)==3)) return true;
if (((i%40)==14)&&((j%30)==9)) return true;
if (((i%40)==15)&&((j%30)==6)) return true;
if (((i%40)==16)&&((j%30)==4)) return true;
if (((i%40)==16)&&((j%30)==8)) return true;
if (((i%40)==17)&&((j%30)==5)) return true;
if (((i%40)==17)&&((j%30)==6)) return true;
if (((i%40)==17)&&((j%30)==7)) return true;
if (((i%40)==18)&&((j%30)==6)) return true;
if (((i%40)==21)&&((j%30)==3)) return true;
if (((i%40)==21)&&((j%30)==4)) return true;
if (((i%40)==21)&&((j%30)==5)) return true;
if (((i%40)==22)&&((j%30)==3)) return true;
if (((i%40)==22)&&((j%30)==4)) return true;
if (((i%40)==22)&&((j%30)==5)) return true;
if (((i%40)==23)&&((j%30)==2)) return true;
if (((i%40)==23)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==1)) return true;
if (((i%40)==25)&&((j%30)==2)) return true;
if (((i%40)==25)&&((j%30)==6)) return true;
if (((i%40)==25)&&((j%30)==7)) return true;
if (((i%40)==35)&&((j%30)==3)) return true;
if (((i%40)==35)&&((j%30)==4)) return true;
if (((i%40)==36)&&((j%30)==3)) return true;
if (((i%40)==36)&&((j%30)==4)) return true;
return false;
}
void set_initial_conditions(bool *u, int dx, int dy, float p)
{
for (int i = 0; i < dx; i++)
for (int j = 0; j < dy; j++)
{
//float _value = (rand() % 10000)/10000.;//((i*173+j*51) % 100) / 100.;
//if (_value < p)
if (glider_gun_field(i, j))
{
u[i*dy+j] = true;
}
}
rand();
}
int main(void)
{
long int NENTRIES = NEPOCHS*DIMENSIONX*DIMENSIONY;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
std::cout << "Defining the universe and creating the initial conditions" << std::endl;
bool *universe = allocate_universe(NEPOCHS, DIMENSIONX, DIMENSIONY);
set_initial_conditions(universe, DIMENSIONX, DIMENSIONY, 0.25);
bool *cuda_universe;
hipMalloc((void**)&cuda_universe, NENTRIES*sizeof(bool));
hipMemcpy(cuda_universe, universe, NENTRIES*sizeof(bool), hipMemcpyHostToDevice);
hipEventRecord(start);
for (int n=0; n<NEPOCHS-1; n++) {
Evolve<<<32, 64>>>(cuda_universe, n, DIMENSIONX, DIMENSIONY);
hipDeviceSynchronize();
}
hipEventRecord(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Total execution time (ms): %f\n ", milliseconds);
hipMemcpy(universe, cuda_universe, NENTRIES*sizeof(bool), hipMemcpyDeviceToHost);
//write everything to file
std::ofstream outfile;
outfile.open ("evolution.txt");
outfile << NEPOCHS << " , " << DIMENSIONX << " , " << DIMENSIONY << "\n";
int nepoch, nx, ny;
for (int i=0; i<NENTRIES; i++) {
if (universe[i]) {
nepoch = i/(DIMENSIONX*DIMENSIONY);
nx = (i % (DIMENSIONX*DIMENSIONY)) / DIMENSIONY;
ny = i % DIMENSIONY;
outfile << nepoch << " , " << nx << " , " << ny << "\n";
}
}
outfile.close();
//clean up
hipFree(cuda_universe);
free(universe);
} | .text
.file "gol.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__EvolvePbiii # -- Begin function _Z21__device_stub__EvolvePbiii
.p2align 4, 0x90
.type _Z21__device_stub__EvolvePbiii,@function
_Z21__device_stub__EvolvePbiii: # @_Z21__device_stub__EvolvePbiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6EvolvePbiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__EvolvePbiii, .Lfunc_end0-_Z21__device_stub__EvolvePbiii
.cfi_endproc
# -- End function
.globl _Z17allocate_universeiii # -- Begin function _Z17allocate_universeiii
.p2align 4, 0x90
.type _Z17allocate_universeiii,@function
_Z17allocate_universeiii: # @_Z17allocate_universeiii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
imull %esi, %ebx
imull %edx, %ebx
movslq %ebx, %r14
movq %r14, %rdi
callq _Znam
testl %r14d, %r14d
jle .LBB1_2
# %bb.1: # %.lr.ph.preheader
movl %ebx, %edx
movq %rax, %rdi
xorl %esi, %esi
movq %rax, %rbx
callq memset@PLT
movq %rbx, %rax
.LBB1_2: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17allocate_universeiii, .Lfunc_end1-_Z17allocate_universeiii
.cfi_endproc
# -- End function
.globl _Z16glider_gun_fieldii # -- Begin function _Z16glider_gun_fieldii
.p2align 4, 0x90
.type _Z16glider_gun_fieldii,@function
_Z16glider_gun_fieldii: # @_Z16glider_gun_fieldii
.cfi_startproc
# %bb.0:
movslq %edi, %rcx
imulq $1717986919, %rcx, %rax # imm = 0x66666667
movq %rax, %rdx
shrq $63, %rdx
shrq $32, %rax
sarl $4, %eax
addl %edx, %eax
shll $3, %eax
leal (%rax,%rax,4), %eax
subl %eax, %ecx
movslq %esi, %rax
imulq $-2004318071, %rax, %rdx # imm = 0x88888889
shrq $32, %rdx
addl %eax, %edx
movl %edx, %esi
shrl $31, %esi
sarl $4, %edx
addl %esi, %edx
movl %edx, %esi
shll $5, %esi
addl %edx, %edx
subl %esi, %edx
addl %eax, %edx
movb $1, %al
cmpl $1, %ecx
jne .LBB2_2
# %bb.1:
cmpl $5, %edx
jne .LBB2_2
.LBB2_33:
retq
.LBB2_2:
cmpl $1, %ecx
jne .LBB2_4
# %bb.3:
cmpl $6, %edx
je .LBB2_33
.LBB2_4:
leal -5(%rdx), %esi
cmpl $2, %ecx
jne .LBB2_6
# %bb.5:
cmpl $2, %esi
jb .LBB2_33
.LBB2_6:
cmpl $11, %ecx
jne .LBB2_8
# %bb.7:
cmpl $3, %esi
jb .LBB2_33
.LBB2_8:
cmpl $12, %ecx
jne .LBB2_10
# %bb.9:
cmpl $4, %edx
je .LBB2_33
.LBB2_10:
cmpl $12, %ecx
jne .LBB2_12
# %bb.11:
cmpl $8, %edx
je .LBB2_33
.LBB2_12:
cmpl $13, %ecx
jne .LBB2_14
# %bb.13:
cmpl $3, %edx
je .LBB2_33
.LBB2_14:
cmpl $13, %ecx
jne .LBB2_16
# %bb.15:
cmpl $9, %edx
je .LBB2_33
.LBB2_16:
cmpl $9, %edx
sete %r8b
cmpl $3, %edx
sete %r9b
movl %edx, %edi
xorl $6, %edi
cmpl $14, %ecx
sete %r10b
movl %ecx, %r11d
xorl $15, %r11d
orl %edi, %r11d
je .LBB2_33
# %bb.17:
orb %r8b, %r9b
andb %r9b, %r10b
jne .LBB2_33
# %bb.18:
leal -4(%rdx), %r8d
testl $-5, %r8d
sete %r8b
cmpl $16, %ecx
jne .LBB2_20
# %bb.19:
testb %r8b, %r8b
jne .LBB2_33
.LBB2_20:
cmpl $17, %ecx
sete %r8b
cmpl $3, %esi
setb %sil
movl %ecx, %r9d
xorl $18, %r9d
orl %edi, %r9d
je .LBB2_33
# %bb.21:
andb %sil, %r8b
jne .LBB2_33
# %bb.22:
leal -3(%rdx), %esi
cmpl $21, %ecx
jne .LBB2_24
# %bb.23:
cmpl $3, %esi
jb .LBB2_33
.LBB2_24:
cmpl $22, %ecx
jne .LBB2_26
# %bb.25:
cmpl $3, %esi
jb .LBB2_33
.LBB2_26:
leal -2(%rdx), %edi
testl $-5, %edi
sete %dil
cmpl $23, %ecx
jne .LBB2_28
# %bb.27:
testb %dil, %dil
jne .LBB2_33
.LBB2_28:
leal -1(%rdx), %edi
cmpl $2, %edi
setb %dil
andl $-2, %edx
cmpl $6, %edx
sete %dl
cmpl $25, %ecx
jne .LBB2_30
# %bb.29:
orb %dl, %dil
jne .LBB2_33
.LBB2_30:
cmpl $35, %ecx
jne .LBB2_32
# %bb.31:
cmpl $2, %esi
jb .LBB2_33
.LBB2_32:
cmpl $36, %ecx
sete %cl
cmpl $2, %esi
setb %al
andb %cl, %al
retq
.Lfunc_end2:
.size _Z16glider_gun_fieldii, .Lfunc_end2-_Z16glider_gun_fieldii
.cfi_endproc
# -- End function
.globl _Z22set_initial_conditionsPbiif # -- Begin function _Z22set_initial_conditionsPbiif
.p2align 4, 0x90
.type _Z22set_initial_conditionsPbiif,@function
_Z22set_initial_conditionsPbiif: # @_Z22set_initial_conditionsPbiif
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_8
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %ebp
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r15
addl %ebx, %r14d
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %r13d
addq 8(%rsp), %r13 # 8-byte Folded Reload
xorl %r12d, %r12d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %r12
cmpq %r12, %rbp
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r15d, %edi
movl %r12d, %esi
callq _Z16glider_gun_fieldii
testb %al, %al
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movb $1, (%r13,%r12)
jmp .LBB3_6
.LBB3_8: # %._crit_edge15
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp rand # TAILCALL
.Lfunc_end3:
.size _Z22set_initial_conditionsPbiif, .Lfunc_end3-_Z22set_initial_conditionsPbiif
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 672
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $57, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_42
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB4_4
.LBB4_3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $10000000, %edi # imm = 0x989680
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $10000000, %edx # imm = 0x989680
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %r12
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_9: # %._crit_edge.i
# in Loop: Header=BB4_5 Depth=1
incq %r14
addq $100, %r12
cmpq $100, %r14
je .LBB4_10
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
xorl %r15d, %r15d
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_8: # in Loop: Header=BB4_6 Depth=2
incq %r15
cmpq $100, %r15
je .LBB4_9
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
movl %r14d, %edi
movl %r15d, %esi
callq _Z16glider_gun_fieldii
testb %al, %al
je .LBB4_8
# %bb.7: # in Loop: Header=BB4_6 Depth=2
movb $1, (%r12,%r15)
jmp .LBB4_8
.LBB4_10: # %_Z22set_initial_conditionsPbiif.exit
movabsq $4294967328, %r14 # imm = 0x100000020
.cfi_escape 0x2e, 0x00
callq rand
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $10000000, %esi # imm = 0x989680
callq hipMalloc
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $10000000, %edx # imm = 0x989680
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
leaq 32(%r14), %r15
leaq 56(%rsp), %r12
leaq 96(%rsp), %r13
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_11 Depth=1
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
incl %ebp
cmpl $999, %ebp # imm = 0x3E7
je .LBB4_14
.LBB4_11: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_11 Depth=1
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl %ebp, 36(%rsp)
movl $100, 32(%rsp)
movl $100, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
movl $_Z6EvolvePbiii, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_13
.LBB4_14:
movq 40(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movl $0, 16(%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $10000000, %edx # imm = 0x989680
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %r12
movq %r12, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 104(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.15: # %.noexc
movq 96(%rsp), %rcx
addq -24(%rcx), %r12
testq %rax, %rax
jne .LBB4_17
# %bb.16:
movl 32(%r12), %r15d
orl $4, %r15d
.LBB4_17: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl %r15d, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.18: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $1000, %esi # imm = 0x3E8
callq _ZNSolsEi
.Ltmp5:
# %bb.19:
.Ltmp6:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $100, %esi
callq _ZNSolsEi
.Ltmp9:
# %bb.21:
.Ltmp10:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $100, %esi
callq _ZNSolsEi
.Ltmp13:
# %bb.23:
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit39.preheader.preheader
xorl %r13d, %r13d
movl $3518437209, %ebp # imm = 0xD1B71759
leaq 96(%rsp), %r15
jmp .LBB4_25
.p2align 4, 0x90
.LBB4_32: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit48
# in Loop: Header=BB4_25 Depth=1
incq %r13
cmpq $10000000, %r13 # imm = 0x989680
je .LBB4_33
.LBB4_25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit39.preheader
# =>This Inner Loop Header: Depth=1
cmpb $0, (%rbx,%r13)
je .LBB4_32
# %bb.26: # in Loop: Header=BB4_25 Depth=1
movl %r13d, %esi
imulq %rbp, %rsi
shrq $45, %rsi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
.Ltmp18:
# %bb.27: # in Loop: Header=BB4_25 Depth=1
.Ltmp19:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
# in Loop: Header=BB4_25 Depth=1
.Ltmp21:
movl %r13d, %r14d
movq %r14, %rax
imulq %rbp, %rax
shrq $45, %rax
imull $-10000, %eax, %eax # imm = 0xD8F0
addl %r13d, %eax
imulq $1374389535, %rax, %rsi # imm = 0x51EB851F
shrq $37, %rsi
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
.Ltmp22:
# %bb.29: # in Loop: Header=BB4_25 Depth=1
.Ltmp23:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp24:
# %bb.30: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit46
# in Loop: Header=BB4_25 Depth=1
imulq $1374389535, %r14, %rax # imm = 0x51EB851F
shrq $37, %rax
imull $-100, %eax, %esi
addq %r13, %rsi
.Ltmp25:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
.Ltmp26:
# %bb.31: # in Loop: Header=BB4_25 Depth=1
.Ltmp27:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
jmp .LBB4_32
.LBB4_33:
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp31:
# %bb.34: # %.noexc41
testq %rax, %rax
jne .LBB4_36
# %bb.35:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $96, %rdi
movl 128(%rsp,%rax), %esi
orl $4, %esi
.Ltmp32:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp33:
.LBB4_36: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq 8(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.37:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_42:
.cfi_def_cfa_offset 672
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB4_40:
.Ltmp36:
jmp .LBB4_41
.LBB4_38:
.Ltmp16:
jmp .LBB4_41
.LBB4_39:
.Ltmp29:
.LBB4_41:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp0 # Call between .Ltmp0 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp28-.Ltmp17 # Call between .Ltmp17 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end4-.Ltmp35 # Call between .Ltmp35 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6EvolvePbiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6EvolvePbiii,@object # @_Z6EvolvePbiii
.section .rodata,"a",@progbits
.globl _Z6EvolvePbiii
.p2align 3, 0x0
_Z6EvolvePbiii:
.quad _Z21__device_stub__EvolvePbiii
.size _Z6EvolvePbiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Defining the universe and creating the initial conditions"
.size .L.str, 58
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total execution time (ms): %f\n "
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "evolution.txt"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " , "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n"
.size .L.str.4, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6EvolvePbiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__EvolvePbiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6EvolvePbiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6EvolvePbiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x140 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P0, PT, R5, 0x2710, PT ; /* 0x000027100500780c */
/* 0x001fe20003f06270 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x002fca00078e0205 */
/*0070*/ ISETP.GT.AND P1, PT, R4, 0x270f, PT ; /* 0x0000270f0400780c */
/* 0x000fce0003f24270 */
/*0080*/ @P0 BRA 0x130 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD R3, R0, c[0x0][0x170], R5 ; /* 0x00005c0000037a24 */
/* 0x000fca00078e0205 */
/*00c0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea8000c1e1100 */
/*00f0*/ STS.U8 [R5], R2 ; /* 0x0000000205007388 */
/* 0x0041e40000000000 */
/*0100*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x001fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P0, PT, R5, 0x2710, PT ; /* 0x000027100500780c */
/* 0x000fda0003f06270 */
/*0120*/ @!P0 BRA 0xb0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0180*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0190*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*01a0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc4000fffe03f */
/*01c0*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*01d0*/ IABS R6, c[0x0][0x170] ; /* 0x00005c0000067a13 */
/* 0x000fe20000000000 */
/*01e0*/ BSSY B0, 0xa00 ; /* 0x0000081000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0200*/ I2F.RP R3, R6 ; /* 0x0000000600037306 */
/* 0x000e300000209400 */
/*0210*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0250*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0260*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0280*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fc600078e3cff */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*02a0*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f46270 */
/*02b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.HI.U32 R3, R5, R7, RZ ; /* 0x0000000705037227 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*02e0*/ IMAD R5, R6, R5, R7 ; /* 0x0000000506057224 */
/* 0x000fca00078e0207 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fda0003f24070 */
/*0300*/ @!P1 IMAD.IADD R5, R5, 0x1, -R6 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a06 */
/*0310*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fda0003f06070 */
/*0340*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0350*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0360*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff039a12 */
/* 0x000fc800078e33ff */
/*0370*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x040fe20007ffe0ff */
/*0380*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a03 */
/*0390*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ IMNMX R10, RZ, R4, !PT ; /* 0x00000004ff0a7217 */
/* 0x000fe20007800200 */
/*03b0*/ IMAD R6, R7, c[0x0][0x170], R0 ; /* 0x00005c0007067a24 */
/* 0x000fe200078e0200 */
/*03c0*/ IMNMX R4, R5, UR4, PT ; /* 0x0000000405047c17 */
/* 0x000fe2000b800200 */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*03e0*/ ISETP.GT.AND P0, PT, R10, R4, PT ; /* 0x000000040a00720c */
/* 0x000fe40003f04270 */
/*03f0*/ IADD3 R5, R6, -0x1, RZ ; /* 0xffffffff06057810 */
/* 0x000fc80007ffe0ff */
/*0400*/ IMNMX R5, RZ, R5, !PT ; /* 0x00000005ff057217 */
/* 0x000fce0007800200 */
/*0410*/ @P0 BRA 0x9f0 ; /* 0x000005d000000947 */
/* 0x000fea0003800000 */
/*0420*/ ULDC UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000800 */
/*0430*/ IADD3 R7, -R6.reuse, -0x2, RZ ; /* 0xfffffffe06077810 */
/* 0x040fe20007ffe1ff */
/*0440*/ UIADD3 UR6, -UR6, URZ, URZ ; /* 0x0000003f06067290 */
/* 0x000fe2000fffe13f */
/*0450*/ LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff097212 */
/* 0x000fe400078e33ff */
/*0460*/ IADD3 R14, R6, 0x1, RZ ; /* 0x00000001060e7810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R11, R5, 0x2, RZ ; /* 0x00000002050b7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ IMNMX R8, R7, UR6, !PT ; /* 0x0000000607087c17 */
/* 0x000fe2000f800200 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*04a0*/ IADD3 R12, R5, 0x3, RZ ; /* 0x00000003050c7810 */
/* 0x000fc40007ffe0ff */
/*04b0*/ IADD3 R13, RZ, -R5, -R8.reuse ; /* 0x80000005ff0d7210 */
/* 0x100fe20007ffe808 */
/*04c0*/ IMAD.IADD R9, R9, 0x1, -R8 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a08 */
/*04d0*/ IMNMX R14, R14, UR5, PT ; /* 0x000000050e0e7c17 */
/* 0x000fe2000b800200 */
/*04e0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*04f0*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d0d7812 */
/* 0x000fe400078ec0ff */
/*0500*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f26070 */
/*0510*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fe40007ffe0ff */
/*0520*/ ISETP.GT.AND P0, PT, R5, R14, PT ; /* 0x0000000e0500720c */
/* 0x000fe20003f04270 */
/*0530*/ BSSY B1, 0x9c0 ; /* 0x0000048000017945 */
/* 0x000fd80003800000 */
/*0540*/ @P0 BRA 0x9b0 ; /* 0x0000046000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0560*/ BSSY B2, 0x760 ; /* 0x000001f000027945 */
/* 0x000fe20003800000 */
/*0570*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fd600078e0005 */
/*0580*/ @!P0 BRA 0x750 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.NE.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe20003f05270 */
/*05a0*/ IMAD R16, R10, c[0x0][0x170], R5 ; /* 0x00005c000a107a24 */
/* 0x000fc600078e0205 */
/*05b0*/ ISETP.EQ.AND P2, PT, R6, R5, !P0 ; /* 0x000000050600720c */
/* 0x000fda0004742270 */
/*05c0*/ @!P2 LDS.U8 R15, [R16] ; /* 0x00000000100fa984 */
/* 0x000e240000000000 */
/*05d0*/ @!P2 ISETP.NE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00a20c */
/* 0x001fc80003f65270 */
/*05e0*/ @!P2 SEL R15, RZ, 0x1, !P3 ; /* 0x00000001ff0fa807 */
/* 0x000fe40005800000 */
/*05f0*/ ISETP.NE.AND P3, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe40003f65270 */
/*0600*/ @!P2 IADD3 R8, P4, R15, R8, RZ ; /* 0x000000080f08a210 */
/* 0x000fe20007f9e0ff */
/*0610*/ IMAD.MOV.U32 R15, RZ, RZ, R9 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0009 */
/*0620*/ @!P2 IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff07a224 */
/* 0x000fcc00020e0607 */
/*0630*/ @!P3 BRA 0x750 ; /* 0x000001100000b947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.EQ.AND P2, PT, R6, R9, !P0 ; /* 0x000000090600720c */
/* 0x000fda0004742270 */
/*0650*/ @!P2 LDS.U8 R15, [R16+0x1] ; /* 0x00000100100fa984 */
/* 0x000e240000000000 */
/*0660*/ @!P2 ISETP.NE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00a20c */
/* 0x001fc80003f65270 */
/*0670*/ @!P2 SEL R15, RZ, 0x1, !P3 ; /* 0x00000001ff0fa807 */
/* 0x000fe40005800000 */
/*0680*/ ISETP.NE.AND P3, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x000fe40003f65270 */
/*0690*/ @!P2 IADD3 R8, P4, R15, R8, RZ ; /* 0x000000080f08a210 */
/* 0x000fe20007f9e0ff */
/*06a0*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000b */
/*06b0*/ @!P2 IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff07a224 */
/* 0x000fcc00020e0607 */
/*06c0*/ @!P3 BRA 0x750 ; /* 0x000000800000b947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.EQ.AND P0, PT, R6, R11, !P0 ; /* 0x0000000b0600720c */
/* 0x000fda0004702270 */
/*06e0*/ @!P0 LDS.U8 R15, [R16+0x2] ; /* 0x00000200100f8984 */
/* 0x000e240000000000 */
/*06f0*/ @!P0 ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00820c */
/* 0x001fc80003f45270 */
/*0700*/ @!P0 SEL R15, RZ, 0x1, !P2 ; /* 0x00000001ff0f8807 */
/* 0x000fc80005000000 */
/*0710*/ @!P0 IADD3 R8, P2, R15, R8, RZ ; /* 0x000000080f088210 */
/* 0x000fe20007f5e0ff */
/*0720*/ IMAD.MOV.U32 R15, RZ, RZ, R12.reuse ; /* 0x000000ffff0f7224 */
/* 0x100fe400078e000c */
/*0730*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f8224 */
/* 0x000fe400078e000c */
/*0740*/ @!P0 IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff078224 */
/* 0x000fc600010e0607 */
/*0750*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0760*/ @!P1 BRA 0x9b0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD R16, R10, c[0x0][0x170], R15 ; /* 0x00005c000a107a24 */
/* 0x000fe200078e020f */
/*0780*/ ISETP.NE.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe20003f05270 */
/*0790*/ IMAD.IADD R20, R15, 0x1, -R6 ; /* 0x000000010f147824 */
/* 0x000fc600078e0a06 */
/*07a0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ ISETP.EQ.AND P5, PT, R20, RZ, !P0 ; /* 0x000000ff1400720c */
/* 0x000fe400047a2270 */
/*07c0*/ IADD3 R17, R15.reuse, 0x1, RZ ; /* 0x000000010f117810 */
/* 0x040fe40007ffe0ff */
/*07d0*/ IADD3 R19, R15.reuse, 0x2, RZ ; /* 0x000000020f137810 */
/* 0x040fe40007ffe0ff */
/*07e0*/ ISETP.EQ.AND P2, PT, R6.reuse, R17, !P0 ; /* 0x000000110600720c */
/* 0x040fe40004742270 */
/*07f0*/ IADD3 R23, R15, 0x3, RZ ; /* 0x000000030f177810 */
/* 0x000fe40007ffe0ff */
/*0800*/ ISETP.EQ.AND P3, PT, R6, R19, !P0 ; /* 0x000000130600720c */
/* 0x000fc40004762270 */
/*0810*/ ISETP.EQ.AND P4, PT, R6, R23, !P0 ; /* 0x000000170600720c */
/* 0x000fe20004782270 */
/*0820*/ @!P5 LDS.U8 R21, [R16+-0x1] ; /* 0xffffff001015d984 */
/* 0x000e220000000000 */
/*0830*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*0840*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fc60007ffe0ff */
/*0850*/ @!P2 LDS.U8 R17, [R16] ; /* 0x000000001011a984 */
/* 0x000e680000000000 */
/*0860*/ @!P3 LDS.U8 R18, [R16+0x1] ; /* 0x000001001012b984 */
/* 0x000ea80000000000 */
/*0870*/ @!P4 LDS.U8 R19, [R16+0x2] ; /* 0x000002001013c984 */
/* 0x0007240000000000 */
/*0880*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x008fc40007ffe0ff */
/*0890*/ @!P5 ISETP.NE.AND P6, PT, R21, RZ, PT ; /* 0x000000ff1500d20c */
/* 0x001fc80003fc5270 */
/*08a0*/ @!P5 SEL R21, RZ, 0x1, !P6 ; /* 0x00000001ff15d807 */
/* 0x000fc80007000000 */
/*08b0*/ @!P5 IADD3 R8, P6, R21, R8, RZ ; /* 0x000000081508d210 */
/* 0x000fca0007fde0ff */
/*08c0*/ @!P5 IMAD.X R7, RZ, RZ, R7, P6 ; /* 0x000000ffff07d224 */
/* 0x000fe200030e0607 */
/*08d0*/ @!P2 ISETP.NE.AND P5, PT, R17, RZ, PT ; /* 0x000000ff1100a20c */
/* 0x002fe40003fa5270 */
/*08e0*/ @!P3 ISETP.NE.AND P6, PT, R18, RZ, PT ; /* 0x000000ff1200b20c */
/* 0x004fe40003fc5270 */
/*08f0*/ @!P2 SEL R17, RZ, 0x1, !P5 ; /* 0x00000001ff11a807 */
/* 0x000fe40006800000 */
/*0900*/ @!P4 ISETP.NE.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300c20c */
/* 0x010fe40003fa5270 */
/*0910*/ @!P3 SEL R19, RZ, 0x1, !P6 ; /* 0x00000001ff13b807 */
/* 0x000fe40007000000 */
/*0920*/ @!P2 IADD3 R8, P6, R17, R8, RZ ; /* 0x000000081108a210 */
/* 0x000fc40007fde0ff */
/*0930*/ @!P4 SEL R17, RZ, 0x1, !P5 ; /* 0x00000001ff11c807 */
/* 0x000fe40006800000 */
/*0940*/ @!P3 IADD3 R8, P5, R19, R8, RZ ; /* 0x000000081308b210 */
/* 0x000fe20007fbe0ff */
/*0950*/ @!P2 IMAD.X R7, RZ, RZ, R7, P6 ; /* 0x000000ffff07a224 */
/* 0x000fe200030e0607 */
/*0960*/ ISETP.GE.AND P2, PT, R23, R14, PT ; /* 0x0000000e1700720c */
/* 0x000fe40003f46270 */
/*0970*/ @!P4 IADD3 R8, P6, R17, R8, RZ ; /* 0x000000081108c210 */
/* 0x000fe20007fde0ff */
/*0980*/ @!P3 IMAD.X R7, RZ, RZ, R7, P5 ; /* 0x000000ffff07b224 */
/* 0x000fc800028e0607 */
/*0990*/ @!P4 IMAD.X R7, RZ, RZ, R7, P6 ; /* 0x000000ffff07c224 */
/* 0x000fcc00030e0607 */
/*09a0*/ @!P2 BRA 0x7b0 ; /* 0xfffffe000000a947 */
/* 0x000fea000383ffff */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ ISETP.GE.AND P0, PT, R10.reuse, R4, PT ; /* 0x000000040a00720c */
/* 0x040fe40003f06270 */
/*09d0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fd60007ffe0ff */
/*09e0*/ @!P0 BRA 0x520 ; /* 0xfffffb3000008947 */
/* 0x000fea000383ffff */
/*09f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a00*/ IMAD R9, R3, c[0x0][0x170], R6 ; /* 0x00005c0003097a24 */
/* 0x000fe200078e0206 */
/*0a10*/ ISETP.EQ.U32.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f22070 */
/*0a20*/ IMAD R3, R2, c[0x0][0x16c], R3 ; /* 0x00005b0002037a24 */
/* 0x000fe200078e0203 */
/*0a30*/ ISETP.EQ.U32.AND P2, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fc60003f42070 */
/*0a40*/ LDS.U8 R9, [R9] ; /* 0x0000000009097984 */
/* 0x000e220000000000 */
/*0a50*/ IMAD R3, R3, c[0x0][0x170], R6 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0206 */
/*0a60*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fc80003f05270 */
/*0a70*/ ISETP.EQ.AND.EX P0, PT, R7, RZ, P0, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000702310 */
/*0a80*/ IADD3 R4, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fe40007f3e0ff */
/*0a90*/ ISETP.EQ.OR.EX P0, PT, R7, RZ, P0, P2 ; /* 0x000000ff0700720c */
/* 0x000fe20000702720 */
/*0aa0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0ab0*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003057a11 */
/* 0x000fe400008f0eff */
/*0ac0*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fe20004000000 */
/*0ad0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fc800078e0200 */
/*0ae0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e2000c101108 */
/*0af0*/ ISETP.GE.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fda0003f06270 */
/*0b00*/ @!P0 BRA 0x1d0 ; /* 0xfffff6c000008947 */
/* 0x001fea000383ffff */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ BRA 0xb20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6EvolvePbiii
.globl _Z6EvolvePbiii
.p2align 8
.type _Z6EvolvePbiii,@function
_Z6EvolvePbiii:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v3, v0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s9, s8, s3
s_and_b32 s8, s2, 0xffff
s_ashr_i32 s2, s9, 31
s_add_u32 s9, s4, s9
s_addc_u32 s2, s5, s2
v_add_co_u32 v1, s9, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s2, 0, s9
s_mov_b32 s9, s10
.LBB0_1:
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, s2, v1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s10, v2, s2
s_waitcnt vmcnt(0)
ds_store_b8 v3, v4
v_add_nc_u32_e32 v3, s8, v3
v_cmp_lt_u32_e32 vcc_lo, 0x270f, v3
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x24
s_add_u32 s0, s0, 24
s_addc_u32 s1, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2710, v1
s_cbranch_execz .LBB0_19
s_ashr_i32 s2, s3, 31
s_load_b32 s0, s[0:1], 0x0
s_add_i32 s8, s3, s2
s_add_i32 s9, s3, -1
s_xor_b32 s8, s8, s2
s_mov_b32 s11, 0
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s1, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s0, s10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s1, v0
s_add_i32 s1, s6, 1
s_add_i32 s6, s7, -1
s_mul_i32 s7, s1, s7
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v2
s_branch .LBB0_6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s1, s1, exec_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v5, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, s3, v[0:1]
v_add_nc_u32_e32 v1, s10, v1
v_cmp_lt_i32_e32 vcc_lo, 0x270f, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v2
v_add_co_u32 v2, s0, s4, v2
s_or_b32 s11, vcc_lo, s11
v_add_co_ci_u32_e64 v3, s0, s5, v0, s0
v_cndmask_b32_e64 v0, 0, 1, s1
global_store_b8 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_19
.LBB0_6:
v_ashrrev_i32_e32 v0, 31, v1
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
v_xor_b32_e32 v2, v2, v0
v_xor_b32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v4
v_mul_lo_u32 v5, v3, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_subrev_nc_u32_e32 v6, s8, v2
v_cmp_le_u32_e32 vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v2
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v5, vcc_lo
v_xor_b32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v0
v_mul_lo_u32 v3, v5, s3
v_max_i32_e32 v0, 1, v5
v_add_nc_u32_e32 v2, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, -1, v0
v_min_i32_e32 v6, s6, v2
v_sub_nc_u32_e32 v0, v1, v3
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_4)
v_cmpx_le_i32_e64 v7, v6
s_cbranch_execz .LBB0_16
v_max_i32_e32 v2, 1, v0
v_add_nc_u32_e32 v3, 1, v0
v_mul_lo_u32 v10, s3, v7
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, -1, v2
v_min_i32_e32 v9, s9, v3
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, v8, v9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v11, 1, v7
v_cmp_ge_i32_e64 s0, v7, v6
v_dual_mov_b32 v7, v11 :: v_dual_add_nc_u32 v10, s3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s12, s0, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_15
.LBB0_10:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_9
v_cmp_eq_u32_e64 s0, v5, v7
v_mov_b32_e32 v11, v8
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_2)
s_xor_b32 s15, s0, -1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v12, 1, v11
v_cmp_ge_i32_e64 s0, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v12
s_or_b32 s14, s0, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_8
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, v0, v11
s_or_b32 s0, s15, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v12, v10, v11
ds_load_u8 v12, v12
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v12, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, v2, v12
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_branch .LBB0_12
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s12
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mad_u64_u32 v[6:7], null, v5, s3, v[0:1]
v_cmp_ne_u64_e64 s0, 2, v[2:3]
ds_load_u8 v6, v6
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s1, 0, v6
v_cmp_ne_u16_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s0, s1, s0
s_mov_b32 s1, -1
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_5
v_cmp_eq_u64_e64 s0, 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, vcc_lo, s0
s_xor_b32 s14, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_4
s_xor_b32 s1, vcc_lo, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_or_not1_b32 s1, s0, exec_lo
s_branch .LBB0_4
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6EvolvePbiii
.amdhsa_group_segment_fixed_size 10000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6EvolvePbiii, .Lfunc_end0-_Z6EvolvePbiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 10000
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6EvolvePbiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z6EvolvePbiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f0cf3_00000000-6_gol.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17allocate_universeiii
.type _Z17allocate_universeiii, @function
_Z17allocate_universeiii:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
imull %esi, %edi
imull %edx, %edi
movl %edi, %ebp
movslq %edi, %rbx
movq %rbx, %rdi
call _Znam@PLT
testl %ebp, %ebp
jle .L3
movq %rax, %rdx
leaq (%rbx,%rax), %rcx
.L5:
movb $0, (%rdx)
addq $1, %rdx
cmpq %rcx, %rdx
jne .L5
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _Z17allocate_universeiii, .-_Z17allocate_universeiii
.globl _Z16glider_gun_fieldii
.type _Z16glider_gun_fieldii, @function
_Z16glider_gun_fieldii:
.LFB3801:
.cfi_startproc
endbr64
movl %esi, %edx
movslq %edi, %rax
imulq $1717986919, %rax, %rax
sarq $36, %rax
movl %edi, %ecx
sarl $31, %ecx
subl %ecx, %eax
leal (%rax,%rax,4), %ecx
sall $3, %ecx
movl %edi, %eax
subl %ecx, %eax
cmpl $1, %eax
je .L46
cmpl $2, %eax
je .L47
cmpl $11, %eax
je .L48
cmpl $12, %eax
je .L49
cmpl $13, %eax
je .L50
cmpl $14, %eax
je .L51
cmpl $15, %eax
je .L52
cmpl $16, %eax
je .L53
cmpl $17, %eax
je .L54
cmpl $18, %eax
je .L55
cmpl $21, %eax
je .L56
cmpl $22, %eax
je .L57
cmpl $23, %eax
je .L58
cmpl $25, %eax
je .L59
cmpl $35, %eax
je .L60
movl $0, %ecx
cmpl $36, %eax
jne .L8
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
sete %cl
jmp .L8
.L46:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
sete %cl
.L8:
movl %ecx, %eax
ret
.L47:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
sete %cl
jmp .L8
.L48:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
je .L8
cmpl $7, %eax
sete %cl
jmp .L8
.L49:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $4, %eax
je .L8
cmpl $8, %eax
sete %cl
jmp .L8
.L50:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $9, %eax
sete %cl
jmp .L8
.L51:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $9, %eax
sete %cl
jmp .L8
.L52:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %eax
subl %eax, %edx
cmpl $6, %edx
sete %cl
jmp .L8
.L53:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $4, %eax
je .L8
cmpl $8, %eax
sete %cl
jmp .L8
.L54:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $5, %eax
je .L8
cmpl $6, %eax
je .L8
cmpl $7, %eax
sete %cl
jmp .L8
.L55:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %eax
subl %eax, %edx
cmpl $6, %edx
sete %cl
jmp .L8
.L56:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
je .L8
cmpl $5, %eax
sete %cl
jmp .L8
.L57:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
je .L8
cmpl $5, %eax
sete %cl
jmp .L8
.L58:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $2, %eax
je .L8
cmpl $6, %eax
sete %cl
jmp .L8
.L59:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $1, %eax
je .L8
cmpl $2, %eax
je .L8
cmpl $6, %eax
je .L8
cmpl $7, %eax
sete %cl
jmp .L8
.L60:
movslq %esi, %rax
imulq $-2004318071, %rax, %rax
shrq $32, %rax
addl %esi, %eax
sarl $4, %eax
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $30, %eax, %ecx
movl %esi, %eax
subl %ecx, %eax
movl $1, %ecx
cmpl $3, %eax
je .L8
cmpl $4, %eax
sete %cl
jmp .L8
.cfi_endproc
.LFE3801:
.size _Z16glider_gun_fieldii, .-_Z16glider_gun_fieldii
.globl _Z22set_initial_conditionsPbiif
.type _Z22set_initial_conditionsPbiif, @function
_Z22set_initial_conditionsPbiif:
.LFB3802:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %esi, %esi
jle .L62
movq %rdi, %r14
movl %esi, %r15d
movl %edx, %r12d
movl $0, %r13d
movl $0, %ebp
jmp .L63
.L64:
addl $1, %ebx
cmpl %ebx, %r12d
je .L66
.L65:
movl %ebx, %esi
movl %ebp, %edi
call _Z16glider_gun_fieldii
testb %al, %al
je .L64
leal (%rbx,%r13), %eax
cltq
movb $1, (%r14,%rax)
jmp .L64
.L66:
addl $1, %ebp
addl %r12d, %r13d
cmpl %ebp, %r15d
je .L62
.L63:
movl $0, %ebx
testl %r12d, %r12d
jg .L65
jmp .L66
.L62:
call rand@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3802:
.size _Z22set_initial_conditionsPbiif, .-_Z22set_initial_conditionsPbiif
.globl _Z28__device_stub__Z6EvolvePbiiiPbiii
.type _Z28__device_stub__Z6EvolvePbiiiPbiii, @function
_Z28__device_stub__Z6EvolvePbiiiPbiii:
.LFB3828:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6EvolvePbiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z28__device_stub__Z6EvolvePbiiiPbiii, .-_Z28__device_stub__Z6EvolvePbiiiPbiii
.globl _Z6EvolvePbiii
.type _Z6EvolvePbiii, @function
_Z6EvolvePbiii:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6EvolvePbiiiPbiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z6EvolvePbiii, .-_Z6EvolvePbiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6EvolvePbiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6EvolvePbiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Defining the universe and creating the initial conditions"
.align 8
.LC4:
.string "Total execution time (ms): %f\n "
.section .rodata.str1.1
.LC5:
.string "evolution.txt"
.LC6:
.string " , "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3803:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3803
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
.LEHB0:
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $100, %edx
movl $100, %esi
movl $1000, %edi
call _Z17allocate_universeiii
movq %rax, %r14
movss .LC2(%rip), %xmm0
movl $100, %edx
movl $100, %esi
movq %rax, %rdi
call _Z22set_initial_conditionsPbiif
leaq 32(%rsp), %rdi
movl $10000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $10000000, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L83
.L82:
call cudaDeviceSynchronize@PLT
addl $1, %ebx
cmpl $999, %ebx
je .L94
.L83:
movl $64, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L82
movl $100, %ecx
movl $100, %edx
movl %ebx, %esi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6EvolvePbiiiPbiii
jmp .L82
.L94:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $10000000, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq %rbx, %rdi
movl $1000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $100, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $100, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %ebx
leaq 64(%rsp), %rax
movq %rax, 8(%rsp)
leaq .LC6(%rip), %r15
jmp .L85
.L96:
movq %rax, %r13
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $3, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L84:
addq $1, %rbx
cmpq $10000000, %rbx
je .L95
.L85:
cmpb $0, (%r14,%rbx)
je .L84
movslq %ebx, %rbp
imulq $1759218605, %rbp, %rsi
sarq $44, %rsi
movl %ebx, %edx
sarl $31, %edx
subl %edx, %esi
imull $10000, %esi, %ecx
movl %ebx, %eax
subl %ecx, %eax
movslq %eax, %r12
imulq $1374389535, %r12, %r12
sarq $37, %r12
sarl $31, %eax
subl %eax, %r12d
imulq $1374389535, %rbp, %rbp
sarq $37, %rbp
subl %edx, %ebp
imull $100, %ebp, %eax
movl %ebx, %ebp
subl %eax, %ebp
movq 8(%rsp), %rdi
call _ZNSolsEi@PLT
jmp .L96
.L95:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
movq %r14, %rdi
call free@PLT
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L97
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L87
call __stack_chk_fail@PLT
.L87:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3803:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3803-.LLSDACSB3803
.LLSDACSB3803:
.uleb128 .LEHB0-.LFB3803
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3803
.uleb128 .LEHE1-.LEHB1
.uleb128 .L89-.LFB3803
.uleb128 0
.uleb128 .LEHB2-.LFB3803
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3803:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1048576000
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gol.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__EvolvePbiii # -- Begin function _Z21__device_stub__EvolvePbiii
.p2align 4, 0x90
.type _Z21__device_stub__EvolvePbiii,@function
_Z21__device_stub__EvolvePbiii: # @_Z21__device_stub__EvolvePbiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6EvolvePbiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__EvolvePbiii, .Lfunc_end0-_Z21__device_stub__EvolvePbiii
.cfi_endproc
# -- End function
.globl _Z17allocate_universeiii # -- Begin function _Z17allocate_universeiii
.p2align 4, 0x90
.type _Z17allocate_universeiii,@function
_Z17allocate_universeiii: # @_Z17allocate_universeiii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
imull %esi, %ebx
imull %edx, %ebx
movslq %ebx, %r14
movq %r14, %rdi
callq _Znam
testl %r14d, %r14d
jle .LBB1_2
# %bb.1: # %.lr.ph.preheader
movl %ebx, %edx
movq %rax, %rdi
xorl %esi, %esi
movq %rax, %rbx
callq memset@PLT
movq %rbx, %rax
.LBB1_2: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17allocate_universeiii, .Lfunc_end1-_Z17allocate_universeiii
.cfi_endproc
# -- End function
.globl _Z16glider_gun_fieldii # -- Begin function _Z16glider_gun_fieldii
.p2align 4, 0x90
.type _Z16glider_gun_fieldii,@function
_Z16glider_gun_fieldii: # @_Z16glider_gun_fieldii
.cfi_startproc
# %bb.0:
movslq %edi, %rcx
imulq $1717986919, %rcx, %rax # imm = 0x66666667
movq %rax, %rdx
shrq $63, %rdx
shrq $32, %rax
sarl $4, %eax
addl %edx, %eax
shll $3, %eax
leal (%rax,%rax,4), %eax
subl %eax, %ecx
movslq %esi, %rax
imulq $-2004318071, %rax, %rdx # imm = 0x88888889
shrq $32, %rdx
addl %eax, %edx
movl %edx, %esi
shrl $31, %esi
sarl $4, %edx
addl %esi, %edx
movl %edx, %esi
shll $5, %esi
addl %edx, %edx
subl %esi, %edx
addl %eax, %edx
movb $1, %al
cmpl $1, %ecx
jne .LBB2_2
# %bb.1:
cmpl $5, %edx
jne .LBB2_2
.LBB2_33:
retq
.LBB2_2:
cmpl $1, %ecx
jne .LBB2_4
# %bb.3:
cmpl $6, %edx
je .LBB2_33
.LBB2_4:
leal -5(%rdx), %esi
cmpl $2, %ecx
jne .LBB2_6
# %bb.5:
cmpl $2, %esi
jb .LBB2_33
.LBB2_6:
cmpl $11, %ecx
jne .LBB2_8
# %bb.7:
cmpl $3, %esi
jb .LBB2_33
.LBB2_8:
cmpl $12, %ecx
jne .LBB2_10
# %bb.9:
cmpl $4, %edx
je .LBB2_33
.LBB2_10:
cmpl $12, %ecx
jne .LBB2_12
# %bb.11:
cmpl $8, %edx
je .LBB2_33
.LBB2_12:
cmpl $13, %ecx
jne .LBB2_14
# %bb.13:
cmpl $3, %edx
je .LBB2_33
.LBB2_14:
cmpl $13, %ecx
jne .LBB2_16
# %bb.15:
cmpl $9, %edx
je .LBB2_33
.LBB2_16:
cmpl $9, %edx
sete %r8b
cmpl $3, %edx
sete %r9b
movl %edx, %edi
xorl $6, %edi
cmpl $14, %ecx
sete %r10b
movl %ecx, %r11d
xorl $15, %r11d
orl %edi, %r11d
je .LBB2_33
# %bb.17:
orb %r8b, %r9b
andb %r9b, %r10b
jne .LBB2_33
# %bb.18:
leal -4(%rdx), %r8d
testl $-5, %r8d
sete %r8b
cmpl $16, %ecx
jne .LBB2_20
# %bb.19:
testb %r8b, %r8b
jne .LBB2_33
.LBB2_20:
cmpl $17, %ecx
sete %r8b
cmpl $3, %esi
setb %sil
movl %ecx, %r9d
xorl $18, %r9d
orl %edi, %r9d
je .LBB2_33
# %bb.21:
andb %sil, %r8b
jne .LBB2_33
# %bb.22:
leal -3(%rdx), %esi
cmpl $21, %ecx
jne .LBB2_24
# %bb.23:
cmpl $3, %esi
jb .LBB2_33
.LBB2_24:
cmpl $22, %ecx
jne .LBB2_26
# %bb.25:
cmpl $3, %esi
jb .LBB2_33
.LBB2_26:
leal -2(%rdx), %edi
testl $-5, %edi
sete %dil
cmpl $23, %ecx
jne .LBB2_28
# %bb.27:
testb %dil, %dil
jne .LBB2_33
.LBB2_28:
leal -1(%rdx), %edi
cmpl $2, %edi
setb %dil
andl $-2, %edx
cmpl $6, %edx
sete %dl
cmpl $25, %ecx
jne .LBB2_30
# %bb.29:
orb %dl, %dil
jne .LBB2_33
.LBB2_30:
cmpl $35, %ecx
jne .LBB2_32
# %bb.31:
cmpl $2, %esi
jb .LBB2_33
.LBB2_32:
cmpl $36, %ecx
sete %cl
cmpl $2, %esi
setb %al
andb %cl, %al
retq
.Lfunc_end2:
.size _Z16glider_gun_fieldii, .Lfunc_end2-_Z16glider_gun_fieldii
.cfi_endproc
# -- End function
.globl _Z22set_initial_conditionsPbiif # -- Begin function _Z22set_initial_conditionsPbiif
.p2align 4, 0x90
.type _Z22set_initial_conditionsPbiif,@function
_Z22set_initial_conditionsPbiif: # @_Z22set_initial_conditionsPbiif
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_8
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %ebp
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r15
addl %ebx, %r14d
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %r13d
addq 8(%rsp), %r13 # 8-byte Folded Reload
xorl %r12d, %r12d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %r12
cmpq %r12, %rbp
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r15d, %edi
movl %r12d, %esi
callq _Z16glider_gun_fieldii
testb %al, %al
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movb $1, (%r13,%r12)
jmp .LBB3_6
.LBB3_8: # %._crit_edge15
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp rand # TAILCALL
.Lfunc_end3:
.size _Z22set_initial_conditionsPbiif, .Lfunc_end3-_Z22set_initial_conditionsPbiif
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 672
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $57, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_42
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB4_4
.LBB4_3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $10000000, %edi # imm = 0x989680
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $10000000, %edx # imm = 0x989680
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %r12
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_9: # %._crit_edge.i
# in Loop: Header=BB4_5 Depth=1
incq %r14
addq $100, %r12
cmpq $100, %r14
je .LBB4_10
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
xorl %r15d, %r15d
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_8: # in Loop: Header=BB4_6 Depth=2
incq %r15
cmpq $100, %r15
je .LBB4_9
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
movl %r14d, %edi
movl %r15d, %esi
callq _Z16glider_gun_fieldii
testb %al, %al
je .LBB4_8
# %bb.7: # in Loop: Header=BB4_6 Depth=2
movb $1, (%r12,%r15)
jmp .LBB4_8
.LBB4_10: # %_Z22set_initial_conditionsPbiif.exit
movabsq $4294967328, %r14 # imm = 0x100000020
.cfi_escape 0x2e, 0x00
callq rand
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $10000000, %esi # imm = 0x989680
callq hipMalloc
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $10000000, %edx # imm = 0x989680
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
leaq 32(%r14), %r15
leaq 56(%rsp), %r12
leaq 96(%rsp), %r13
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_11 Depth=1
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
incl %ebp
cmpl $999, %ebp # imm = 0x3E7
je .LBB4_14
.LBB4_11: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_11 Depth=1
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl %ebp, 36(%rsp)
movl $100, 32(%rsp)
movl $100, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
movl $_Z6EvolvePbiii, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_13
.LBB4_14:
movq 40(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movl $0, 16(%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $10000000, %edx # imm = 0x989680
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %r12
movq %r12, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 104(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.15: # %.noexc
movq 96(%rsp), %rcx
addq -24(%rcx), %r12
testq %rax, %rax
jne .LBB4_17
# %bb.16:
movl 32(%r12), %r15d
orl $4, %r15d
.LBB4_17: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl %r15d, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.18: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $1000, %esi # imm = 0x3E8
callq _ZNSolsEi
.Ltmp5:
# %bb.19:
.Ltmp6:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $100, %esi
callq _ZNSolsEi
.Ltmp9:
# %bb.21:
.Ltmp10:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $100, %esi
callq _ZNSolsEi
.Ltmp13:
# %bb.23:
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit39.preheader.preheader
xorl %r13d, %r13d
movl $3518437209, %ebp # imm = 0xD1B71759
leaq 96(%rsp), %r15
jmp .LBB4_25
.p2align 4, 0x90
.LBB4_32: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit48
# in Loop: Header=BB4_25 Depth=1
incq %r13
cmpq $10000000, %r13 # imm = 0x989680
je .LBB4_33
.LBB4_25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit39.preheader
# =>This Inner Loop Header: Depth=1
cmpb $0, (%rbx,%r13)
je .LBB4_32
# %bb.26: # in Loop: Header=BB4_25 Depth=1
movl %r13d, %esi
imulq %rbp, %rsi
shrq $45, %rsi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
.Ltmp18:
# %bb.27: # in Loop: Header=BB4_25 Depth=1
.Ltmp19:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
# in Loop: Header=BB4_25 Depth=1
.Ltmp21:
movl %r13d, %r14d
movq %r14, %rax
imulq %rbp, %rax
shrq $45, %rax
imull $-10000, %eax, %eax # imm = 0xD8F0
addl %r13d, %eax
imulq $1374389535, %rax, %rsi # imm = 0x51EB851F
shrq $37, %rsi
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
.Ltmp22:
# %bb.29: # in Loop: Header=BB4_25 Depth=1
.Ltmp23:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp24:
# %bb.30: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit46
# in Loop: Header=BB4_25 Depth=1
imulq $1374389535, %r14, %rax # imm = 0x51EB851F
shrq $37, %rax
imull $-100, %eax, %esi
addq %r13, %rsi
.Ltmp25:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
.Ltmp26:
# %bb.31: # in Loop: Header=BB4_25 Depth=1
.Ltmp27:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
jmp .LBB4_32
.LBB4_33:
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp31:
# %bb.34: # %.noexc41
testq %rax, %rax
jne .LBB4_36
# %bb.35:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $96, %rdi
movl 128(%rsp,%rax), %esi
orl $4, %esi
.Ltmp32:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp33:
.LBB4_36: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq 8(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.37:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_42:
.cfi_def_cfa_offset 672
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB4_40:
.Ltmp36:
jmp .LBB4_41
.LBB4_38:
.Ltmp16:
jmp .LBB4_41
.LBB4_39:
.Ltmp29:
.LBB4_41:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp0 # Call between .Ltmp0 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp28-.Ltmp17 # Call between .Ltmp17 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end4-.Ltmp35 # Call between .Ltmp35 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6EvolvePbiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6EvolvePbiii,@object # @_Z6EvolvePbiii
.section .rodata,"a",@progbits
.globl _Z6EvolvePbiii
.p2align 3, 0x0
_Z6EvolvePbiii:
.quad _Z21__device_stub__EvolvePbiii
.size _Z6EvolvePbiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Defining the universe and creating the initial conditions"
.size .L.str, 58
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total execution time (ms): %f\n "
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "evolution.txt"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " , "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n"
.size .L.str.4, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6EvolvePbiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__EvolvePbiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6EvolvePbiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* File: Complex.cu
*
* Created on June 24, 2012
*
* Purpose: Simple complex number class for use on GPU
*
* If it works, it was written by Brian Swenson.
* Otherwise, I have no idea who wrote it.
*/
class Complex
{
public:
float r;
float i;
__host__ __device__ Complex( float a, float b ) : r(a), i(b) {}
__device__ Complex(const Complex& x) : r(x.r), i(x.i) {}
__device__ float magnitude2( void ) {
return r * r + i * i;
}
__device__ Complex operator*(const Complex& a) {
return Complex(r*a.r - i*a.i, i*a.r + r*a.i);
}
__device__ Complex operator+(const Complex& a) {
return Complex(r+a.r, i+a.i);
}
}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* File: Complex.cu
*
* Created on June 24, 2012
*
* Purpose: Simple complex number class for use on GPU
*
* If it works, it was written by Brian Swenson.
* Otherwise, I have no idea who wrote it.
*/
class Complex
{
public:
float r;
float i;
__host__ __device__ Complex( float a, float b ) : r(a), i(b) {}
__device__ Complex(const Complex& x) : r(x.r), i(x.i) {}
__device__ float magnitude2( void ) {
return r * r + i * i;
}
__device__ Complex operator*(const Complex& a) {
return Complex(r*a.r - i*a.i, i*a.r + r*a.i);
}
__device__ Complex operator+(const Complex& a) {
return Complex(r+a.r, i+a.i);
}
}; | .file "tmpxft_000de2a7_00000000-6_Complex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* File: Complex.cu
*
* Created on June 24, 2012
*
* Purpose: Simple complex number class for use on GPU
*
* If it works, it was written by Brian Swenson.
* Otherwise, I have no idea who wrote it.
*/
class Complex
{
public:
float r;
float i;
__host__ __device__ Complex( float a, float b ) : r(a), i(b) {}
__device__ Complex(const Complex& x) : r(x.r), i(x.i) {}
__device__ float magnitude2( void ) {
return r * r + i * i;
}
__device__ Complex operator*(const Complex& a) {
return Complex(r*a.r - i*a.i, i*a.r + r*a.i);
}
__device__ Complex operator+(const Complex& a) {
return Complex(r+a.r, i+a.i);
}
}; | #include <hip/hip_runtime.h>
/*
* File: Complex.cu
*
* Created on June 24, 2012
*
* Purpose: Simple complex number class for use on GPU
*
* If it works, it was written by Brian Swenson.
* Otherwise, I have no idea who wrote it.
*/
class Complex
{
public:
float r;
float i;
__host__ __device__ Complex( float a, float b ) : r(a), i(b) {}
__device__ Complex(const Complex& x) : r(x.r), i(x.i) {}
__device__ float magnitude2( void ) {
return r * r + i * i;
}
__device__ Complex operator*(const Complex& a) {
return Complex(r*a.r - i*a.i, i*a.r + r*a.i);
}
__device__ Complex operator+(const Complex& a) {
return Complex(r+a.r, i+a.i);
}
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* File: Complex.cu
*
* Created on June 24, 2012
*
* Purpose: Simple complex number class for use on GPU
*
* If it works, it was written by Brian Swenson.
* Otherwise, I have no idea who wrote it.
*/
class Complex
{
public:
float r;
float i;
__host__ __device__ Complex( float a, float b ) : r(a), i(b) {}
__device__ Complex(const Complex& x) : r(x.r), i(x.i) {}
__device__ float magnitude2( void ) {
return r * r + i * i;
}
__device__ Complex operator*(const Complex& a) {
return Complex(r*a.r - i*a.i, i*a.r + r*a.i);
}
__device__ Complex operator+(const Complex& a) {
return Complex(r+a.r, i+a.i);
}
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* File: Complex.cu
*
* Created on June 24, 2012
*
* Purpose: Simple complex number class for use on GPU
*
* If it works, it was written by Brian Swenson.
* Otherwise, I have no idea who wrote it.
*/
class Complex
{
public:
float r;
float i;
__host__ __device__ Complex( float a, float b ) : r(a), i(b) {}
__device__ Complex(const Complex& x) : r(x.r), i(x.i) {}
__device__ float magnitude2( void ) {
return r * r + i * i;
}
__device__ Complex operator*(const Complex& a) {
return Complex(r*a.r - i*a.i, i*a.r + r*a.i);
}
__device__ Complex operator+(const Complex& a) {
return Complex(r+a.r, i+a.i);
}
}; | .text
.file "Complex.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de2a7_00000000-6_Complex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Complex.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de diferentes streams com cudaMallocHost
para alocar memoria no host nao paginavel e copia assincrona
com cudaMemcpyAsync. Usa tambem o cudaStreamSynchronize para
aguardar toda a stream terminar.
O algoritmo divide "tam" elementos por "streams_nr" e encontra "threadsPerGrid" e "blocksPerGrid"
O vetor no device tem o tamanho de threadsPerGrid.
Caso o nr de streams provoque uma divisao com resto, a ultima grade da stream deve acertar o resto.
Funcionou para teste com stream 03 e tam 16 ou 17 e TPB 2 ou 3
Caso o nr de threads por bloco provoque uma divisao com resto, o algoritmo deve funcionar
com a fitragem do excesso implementada. Funcionou com alguns testes básicos.
Para compilar: nvcc 03-soma-vet-stream.cu -o 03-soma-vet-stream
Para executar: ./03-soma-vet-stream
OBS: os valores de tamanho do vetor e o conteudo do vetor
estao fixos no codigo
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void soma(int *vetorA, int *vetorB,int *vetorC, int tam, int iter)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx < tam)
{
vetorC[idx]=vetorA[idx]+vetorB[idx];
printf("Iter=%d, Blc=%d, Thread=%d, Tam=%d, VetC[%d]=%d \n", iter, blockIdx.x, threadIdx.x, tam, idx, vetorC[idx]);
}
}
int main(int argc,char **argv)
{
int i,*vetorA,*vetorB,*vetorC,threadsPerBlock;
int *vetorA_d,*vetorB_d,*vetorC_d;
//Declaração da variável do tipo cudaStream_t
cudaStream_t stream;
//Criação da stream
cudaStreamCreate(&stream);
//Define o tamanho do vetor, multiplo de 256
int tam = 16; // 16; // 2048;
//Define a quantidade de threads por bloco
threadsPerBlock = 2; //2; //256;
//Define quantas streams usar
int streams_nr = 2;
//Define o nr de threads por grade (uma grade por vez na stream)
int threadsPerGrid=tam/streams_nr; // threadsPerGrid=8 (16/2) // =1024 (2048/2)
//Define a quantidade de blocos por grade
int blocksPerGrid=(threadsPerGrid+threadsPerBlock-1)/threadsPerBlock; // blockPerStream=4 (8/2) // =4 (1024/256)
// (8+1)/2 ==> 4 (4,5)
// (1024+255)/256 ==> 4 (4,9960)
//
//Aloca memoria nao paginavel para os vetores no host
cudaMallocHost((void**)&vetorA,tam*(sizeof(int)));
cudaMallocHost((void**)&vetorB,tam*(sizeof(int)));
cudaMallocHost((void**)&vetorC,tam*(sizeof(int)));
//Aloca os vetores no device
cudaMalloc((void**)&vetorA_d, threadsPerGrid*(sizeof(int)));
cudaMalloc((void**)&vetorB_d, threadsPerGrid*(sizeof(int)));
cudaMalloc((void**)&vetorC_d, threadsPerGrid*(sizeof(int)));
//Preenche os vetores no host
for(i=0;i<tam;i++)
{
vetorA[i]=i;
vetorB[i]=0;
}
printf("Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n", tam, streams_nr, threadsPerGrid, blocksPerGrid, threadsPerBlock);
// a cada iteracao desloca o bloco em threadsPerGrid itens
// equivale a deslocar streams_nr
for(i=0; i<tam; i+=threadsPerGrid) //i+=8 //i+1024
{
// caso tenha mais streams que o necessario, precisa acertar o tamanho do bloco na ultima stream
// essa ultima stream pega apenas o restante para processas; nao o vlr cheios de threadsPerGrid
if((tam-i)< threadsPerGrid)
threadsPerGrid = tam - i;
//copia um bloco de tamanho threadsPerGrid do vetor A do host para o device
cudaMemcpyAsync(vetorA_d,vetorA+i, threadsPerGrid*(sizeof(int)),cudaMemcpyHostToDevice,stream);
//copia um bloco de tamanho threadsPerGrid do vetor B do host para o device
cudaMemcpyAsync(vetorB_d,vetorB+i, threadsPerGrid*(sizeof(int)),cudaMemcpyHostToDevice,stream);
//Invoca o kernel soma passando a stream como argumento
soma <<<blocksPerGrid,threadsPerBlock,0,stream>>> (vetorA_d,vetorB_d,vetorC_d,threadsPerGrid,i);
// <<<4,2>> para alguns dos exemplos acima.
//Copia um bloco de tamanho threadsPerGrid do resultado de volta para o host
cudaMemcpyAsync(vetorC+i,vetorC_d,threadsPerGrid*(sizeof(int)),cudaMemcpyDeviceToHost,stream);
}
//Sincroniza a stream
cudaStreamSynchronize(stream);
//Imprime o resultado no host
for(i=0;i<tam;i++)
{
printf("%d ",vetorC[i]);
}
//Desaloca os vetores no host
cudaFreeHost(vetorA);
cudaFreeHost(vetorB);
cudaFreeHost(vetorC);
//Desaloca os vetores no device
cudaFree(vetorA_d);
cudaFree(vetorB_d);
cudaFree(vetorC_d);
//Destroi a stream
cudaStreamDestroy(stream);
} | code for sm_80
Function : _Z4somaPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R2, R15, c[0x0][0x0], R12 ; /* 0x000000000f027a24 */
/* 0x001fca00078e020c */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0209 */
/*00b0*/ IMAD.WIDE R10, R2.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a00020a7625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000a8000c1e1900 */
/*00d0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0002a2000c1e1900 */
/*00e0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0e7624 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.WIDE R8, R2, R9, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fe200078e0209 */
/*0120*/ STL.64 [R1], R14 ; /* 0x0000000e01007387 */
/* 0x0007e80000100a00 */
/*0130*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0007e20000100a00 */
/*0140*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0026620000000a00 */
/*0150*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0160*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x001fc40000000f00 */
/*0170*/ IADD3 R3, R3, R4, RZ ; /* 0x0000000403037210 */
/* 0x004fca0007ffe0ff */
/*0180*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0007e8000c101904 */
/*0190*/ STL.64 [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0007e20000100a00 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fc600078e00ff */
/*01b0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x00afc80000000000 */
/*01c0*/ MOV R9, 0x230 ; /* 0x0000023000097802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R20, 0x1b0 ; /* 0x000001b000147802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0200*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0210*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0220*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de diferentes streams com cudaMallocHost
para alocar memoria no host nao paginavel e copia assincrona
com cudaMemcpyAsync. Usa tambem o cudaStreamSynchronize para
aguardar toda a stream terminar.
O algoritmo divide "tam" elementos por "streams_nr" e encontra "threadsPerGrid" e "blocksPerGrid"
O vetor no device tem o tamanho de threadsPerGrid.
Caso o nr de streams provoque uma divisao com resto, a ultima grade da stream deve acertar o resto.
Funcionou para teste com stream 03 e tam 16 ou 17 e TPB 2 ou 3
Caso o nr de threads por bloco provoque uma divisao com resto, o algoritmo deve funcionar
com a fitragem do excesso implementada. Funcionou com alguns testes básicos.
Para compilar: nvcc 03-soma-vet-stream.cu -o 03-soma-vet-stream
Para executar: ./03-soma-vet-stream
OBS: os valores de tamanho do vetor e o conteudo do vetor
estao fixos no codigo
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void soma(int *vetorA, int *vetorB,int *vetorC, int tam, int iter)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx < tam)
{
vetorC[idx]=vetorA[idx]+vetorB[idx];
printf("Iter=%d, Blc=%d, Thread=%d, Tam=%d, VetC[%d]=%d \n", iter, blockIdx.x, threadIdx.x, tam, idx, vetorC[idx]);
}
}
int main(int argc,char **argv)
{
int i,*vetorA,*vetorB,*vetorC,threadsPerBlock;
int *vetorA_d,*vetorB_d,*vetorC_d;
//Declaração da variável do tipo cudaStream_t
cudaStream_t stream;
//Criação da stream
cudaStreamCreate(&stream);
//Define o tamanho do vetor, multiplo de 256
int tam = 16; // 16; // 2048;
//Define a quantidade de threads por bloco
threadsPerBlock = 2; //2; //256;
//Define quantas streams usar
int streams_nr = 2;
//Define o nr de threads por grade (uma grade por vez na stream)
int threadsPerGrid=tam/streams_nr; // threadsPerGrid=8 (16/2) // =1024 (2048/2)
//Define a quantidade de blocos por grade
int blocksPerGrid=(threadsPerGrid+threadsPerBlock-1)/threadsPerBlock; // blockPerStream=4 (8/2) // =4 (1024/256)
// (8+1)/2 ==> 4 (4,5)
// (1024+255)/256 ==> 4 (4,9960)
//
//Aloca memoria nao paginavel para os vetores no host
cudaMallocHost((void**)&vetorA,tam*(sizeof(int)));
cudaMallocHost((void**)&vetorB,tam*(sizeof(int)));
cudaMallocHost((void**)&vetorC,tam*(sizeof(int)));
//Aloca os vetores no device
cudaMalloc((void**)&vetorA_d, threadsPerGrid*(sizeof(int)));
cudaMalloc((void**)&vetorB_d, threadsPerGrid*(sizeof(int)));
cudaMalloc((void**)&vetorC_d, threadsPerGrid*(sizeof(int)));
//Preenche os vetores no host
for(i=0;i<tam;i++)
{
vetorA[i]=i;
vetorB[i]=0;
}
printf("Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n", tam, streams_nr, threadsPerGrid, blocksPerGrid, threadsPerBlock);
// a cada iteracao desloca o bloco em threadsPerGrid itens
// equivale a deslocar streams_nr
for(i=0; i<tam; i+=threadsPerGrid) //i+=8 //i+1024
{
// caso tenha mais streams que o necessario, precisa acertar o tamanho do bloco na ultima stream
// essa ultima stream pega apenas o restante para processas; nao o vlr cheios de threadsPerGrid
if((tam-i)< threadsPerGrid)
threadsPerGrid = tam - i;
//copia um bloco de tamanho threadsPerGrid do vetor A do host para o device
cudaMemcpyAsync(vetorA_d,vetorA+i, threadsPerGrid*(sizeof(int)),cudaMemcpyHostToDevice,stream);
//copia um bloco de tamanho threadsPerGrid do vetor B do host para o device
cudaMemcpyAsync(vetorB_d,vetorB+i, threadsPerGrid*(sizeof(int)),cudaMemcpyHostToDevice,stream);
//Invoca o kernel soma passando a stream como argumento
soma <<<blocksPerGrid,threadsPerBlock,0,stream>>> (vetorA_d,vetorB_d,vetorC_d,threadsPerGrid,i);
// <<<4,2>> para alguns dos exemplos acima.
//Copia um bloco de tamanho threadsPerGrid do resultado de volta para o host
cudaMemcpyAsync(vetorC+i,vetorC_d,threadsPerGrid*(sizeof(int)),cudaMemcpyDeviceToHost,stream);
}
//Sincroniza a stream
cudaStreamSynchronize(stream);
//Imprime o resultado no host
for(i=0;i<tam;i++)
{
printf("%d ",vetorC[i]);
}
//Desaloca os vetores no host
cudaFreeHost(vetorA);
cudaFreeHost(vetorB);
cudaFreeHost(vetorC);
//Desaloca os vetores no device
cudaFree(vetorA_d);
cudaFree(vetorB_d);
cudaFree(vetorC_d);
//Destroi a stream
cudaStreamDestroy(stream);
} | .file "tmpxft_001297ac_00000000-6_03-soma-vet-stream.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4somaPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
.globl _Z4somaPiS_S_ii
.type _Z4somaPiS_S_ii, @function
_Z4somaPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4somaPiS_S_ii, .-_Z4somaPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl $0, (%rdx,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq $2
.cfi_def_cfa_offset 160
movl $4, %r9d
movl $8, %r8d
movl $2, %ecx
movl $16, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
movl $8, %r13d
movl $0, %r12d
movl $16, %r14d
jmp .L14
.L13:
movq %rbx, %rdi
addq 24(%rsp), %rdi
movq 56(%rsp), %r8
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
call cudaMemcpyAsync@PLT
addl %r13d, %r12d
cmpl $15, %r12d
jg .L21
.L14:
movl %r14d, %eax
subl %r12d, %eax
cmpl %eax, %r13d
cmovg %eax, %r13d
movslq %r13d, %rbp
salq $2, %rbp
movslq %r12d, %rbx
salq $2, %rbx
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq 56(%rsp), %r8
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq 56(%rsp), %r8
movl $1, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $2, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movq 56(%rsp), %r9
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %r12d, %r8d
movl %r13d, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
jmp .L13
.L21:
movq 56(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
movq 24(%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4somaPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4somaPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de diferentes streams com cudaMallocHost
para alocar memoria no host nao paginavel e copia assincrona
com cudaMemcpyAsync. Usa tambem o cudaStreamSynchronize para
aguardar toda a stream terminar.
O algoritmo divide "tam" elementos por "streams_nr" e encontra "threadsPerGrid" e "blocksPerGrid"
O vetor no device tem o tamanho de threadsPerGrid.
Caso o nr de streams provoque uma divisao com resto, a ultima grade da stream deve acertar o resto.
Funcionou para teste com stream 03 e tam 16 ou 17 e TPB 2 ou 3
Caso o nr de threads por bloco provoque uma divisao com resto, o algoritmo deve funcionar
com a fitragem do excesso implementada. Funcionou com alguns testes básicos.
Para compilar: nvcc 03-soma-vet-stream.cu -o 03-soma-vet-stream
Para executar: ./03-soma-vet-stream
OBS: os valores de tamanho do vetor e o conteudo do vetor
estao fixos no codigo
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void soma(int *vetorA, int *vetorB,int *vetorC, int tam, int iter)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx < tam)
{
vetorC[idx]=vetorA[idx]+vetorB[idx];
printf("Iter=%d, Blc=%d, Thread=%d, Tam=%d, VetC[%d]=%d \n", iter, blockIdx.x, threadIdx.x, tam, idx, vetorC[idx]);
}
}
int main(int argc,char **argv)
{
int i,*vetorA,*vetorB,*vetorC,threadsPerBlock;
int *vetorA_d,*vetorB_d,*vetorC_d;
//Declaração da variável do tipo cudaStream_t
cudaStream_t stream;
//Criação da stream
cudaStreamCreate(&stream);
//Define o tamanho do vetor, multiplo de 256
int tam = 16; // 16; // 2048;
//Define a quantidade de threads por bloco
threadsPerBlock = 2; //2; //256;
//Define quantas streams usar
int streams_nr = 2;
//Define o nr de threads por grade (uma grade por vez na stream)
int threadsPerGrid=tam/streams_nr; // threadsPerGrid=8 (16/2) // =1024 (2048/2)
//Define a quantidade de blocos por grade
int blocksPerGrid=(threadsPerGrid+threadsPerBlock-1)/threadsPerBlock; // blockPerStream=4 (8/2) // =4 (1024/256)
// (8+1)/2 ==> 4 (4,5)
// (1024+255)/256 ==> 4 (4,9960)
//
//Aloca memoria nao paginavel para os vetores no host
cudaMallocHost((void**)&vetorA,tam*(sizeof(int)));
cudaMallocHost((void**)&vetorB,tam*(sizeof(int)));
cudaMallocHost((void**)&vetorC,tam*(sizeof(int)));
//Aloca os vetores no device
cudaMalloc((void**)&vetorA_d, threadsPerGrid*(sizeof(int)));
cudaMalloc((void**)&vetorB_d, threadsPerGrid*(sizeof(int)));
cudaMalloc((void**)&vetorC_d, threadsPerGrid*(sizeof(int)));
//Preenche os vetores no host
for(i=0;i<tam;i++)
{
vetorA[i]=i;
vetorB[i]=0;
}
printf("Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n", tam, streams_nr, threadsPerGrid, blocksPerGrid, threadsPerBlock);
// a cada iteracao desloca o bloco em threadsPerGrid itens
// equivale a deslocar streams_nr
for(i=0; i<tam; i+=threadsPerGrid) //i+=8 //i+1024
{
// caso tenha mais streams que o necessario, precisa acertar o tamanho do bloco na ultima stream
// essa ultima stream pega apenas o restante para processas; nao o vlr cheios de threadsPerGrid
if((tam-i)< threadsPerGrid)
threadsPerGrid = tam - i;
//copia um bloco de tamanho threadsPerGrid do vetor A do host para o device
cudaMemcpyAsync(vetorA_d,vetorA+i, threadsPerGrid*(sizeof(int)),cudaMemcpyHostToDevice,stream);
//copia um bloco de tamanho threadsPerGrid do vetor B do host para o device
cudaMemcpyAsync(vetorB_d,vetorB+i, threadsPerGrid*(sizeof(int)),cudaMemcpyHostToDevice,stream);
//Invoca o kernel soma passando a stream como argumento
soma <<<blocksPerGrid,threadsPerBlock,0,stream>>> (vetorA_d,vetorB_d,vetorC_d,threadsPerGrid,i);
// <<<4,2>> para alguns dos exemplos acima.
//Copia um bloco de tamanho threadsPerGrid do resultado de volta para o host
cudaMemcpyAsync(vetorC+i,vetorC_d,threadsPerGrid*(sizeof(int)),cudaMemcpyDeviceToHost,stream);
}
//Sincroniza a stream
cudaStreamSynchronize(stream);
//Imprime o resultado no host
for(i=0;i<tam;i++)
{
printf("%d ",vetorC[i]);
}
//Desaloca os vetores no host
cudaFreeHost(vetorA);
cudaFreeHost(vetorB);
cudaFreeHost(vetorC);
//Desaloca os vetores no device
cudaFree(vetorA_d);
cudaFree(vetorB_d);
cudaFree(vetorC_d);
//Destroi a stream
cudaStreamDestroy(stream);
} | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de diferentes streams com cudaMallocHost
para alocar memoria no host nao paginavel e copia assincrona
com cudaMemcpyAsync. Usa tambem o cudaStreamSynchronize para
aguardar toda a stream terminar.
O algoritmo divide "tam" elementos por "streams_nr" e encontra "threadsPerGrid" e "blocksPerGrid"
O vetor no device tem o tamanho de threadsPerGrid.
Caso o nr de streams provoque uma divisao com resto, a ultima grade da stream deve acertar o resto.
Funcionou para teste com stream 03 e tam 16 ou 17 e TPB 2 ou 3
Caso o nr de threads por bloco provoque uma divisao com resto, o algoritmo deve funcionar
com a fitragem do excesso implementada. Funcionou com alguns testes básicos.
Para compilar: nvcc 03-soma-vet-stream.cu -o 03-soma-vet-stream
Para executar: ./03-soma-vet-stream
OBS: os valores de tamanho do vetor e o conteudo do vetor
estao fixos no codigo
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void soma(int *vetorA, int *vetorB,int *vetorC, int tam, int iter)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx < tam)
{
vetorC[idx]=vetorA[idx]+vetorB[idx];
printf("Iter=%d, Blc=%d, Thread=%d, Tam=%d, VetC[%d]=%d \n", iter, blockIdx.x, threadIdx.x, tam, idx, vetorC[idx]);
}
}
int main(int argc,char **argv)
{
int i,*vetorA,*vetorB,*vetorC,threadsPerBlock;
int *vetorA_d,*vetorB_d,*vetorC_d;
//Declaração da variável do tipo cudaStream_t
hipStream_t stream;
//Criação da stream
hipStreamCreate(&stream);
//Define o tamanho do vetor, multiplo de 256
int tam = 16; // 16; // 2048;
//Define a quantidade de threads por bloco
threadsPerBlock = 2; //2; //256;
//Define quantas streams usar
int streams_nr = 2;
//Define o nr de threads por grade (uma grade por vez na stream)
int threadsPerGrid=tam/streams_nr; // threadsPerGrid=8 (16/2) // =1024 (2048/2)
//Define a quantidade de blocos por grade
int blocksPerGrid=(threadsPerGrid+threadsPerBlock-1)/threadsPerBlock; // blockPerStream=4 (8/2) // =4 (1024/256)
// (8+1)/2 ==> 4 (4,5)
// (1024+255)/256 ==> 4 (4,9960)
//
//Aloca memoria nao paginavel para os vetores no host
hipHostMalloc((void**)&vetorA,tam*(sizeof(int)), hipHostMallocDefault);
hipHostMalloc((void**)&vetorB,tam*(sizeof(int)), hipHostMallocDefault);
hipHostMalloc((void**)&vetorC,tam*(sizeof(int)), hipHostMallocDefault);
//Aloca os vetores no device
hipMalloc((void**)&vetorA_d, threadsPerGrid*(sizeof(int)));
hipMalloc((void**)&vetorB_d, threadsPerGrid*(sizeof(int)));
hipMalloc((void**)&vetorC_d, threadsPerGrid*(sizeof(int)));
//Preenche os vetores no host
for(i=0;i<tam;i++)
{
vetorA[i]=i;
vetorB[i]=0;
}
printf("Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n", tam, streams_nr, threadsPerGrid, blocksPerGrid, threadsPerBlock);
// a cada iteracao desloca o bloco em threadsPerGrid itens
// equivale a deslocar streams_nr
for(i=0; i<tam; i+=threadsPerGrid) //i+=8 //i+1024
{
// caso tenha mais streams que o necessario, precisa acertar o tamanho do bloco na ultima stream
// essa ultima stream pega apenas o restante para processas; nao o vlr cheios de threadsPerGrid
if((tam-i)< threadsPerGrid)
threadsPerGrid = tam - i;
//copia um bloco de tamanho threadsPerGrid do vetor A do host para o device
hipMemcpyAsync(vetorA_d,vetorA+i, threadsPerGrid*(sizeof(int)),hipMemcpyHostToDevice,stream);
//copia um bloco de tamanho threadsPerGrid do vetor B do host para o device
hipMemcpyAsync(vetorB_d,vetorB+i, threadsPerGrid*(sizeof(int)),hipMemcpyHostToDevice,stream);
//Invoca o kernel soma passando a stream como argumento
soma <<<blocksPerGrid,threadsPerBlock,0,stream>>> (vetorA_d,vetorB_d,vetorC_d,threadsPerGrid,i);
// <<<4,2>> para alguns dos exemplos acima.
//Copia um bloco de tamanho threadsPerGrid do resultado de volta para o host
hipMemcpyAsync(vetorC+i,vetorC_d,threadsPerGrid*(sizeof(int)),hipMemcpyDeviceToHost,stream);
}
//Sincroniza a stream
hipStreamSynchronize(stream);
//Imprime o resultado no host
for(i=0;i<tam;i++)
{
printf("%d ",vetorC[i]);
}
//Desaloca os vetores no host
hipHostFree(vetorA);
hipHostFree(vetorB);
hipHostFree(vetorC);
//Desaloca os vetores no device
hipFree(vetorA_d);
hipFree(vetorB_d);
hipFree(vetorC_d);
//Destroi a stream
hipStreamDestroy(stream);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de diferentes streams com cudaMallocHost
para alocar memoria no host nao paginavel e copia assincrona
com cudaMemcpyAsync. Usa tambem o cudaStreamSynchronize para
aguardar toda a stream terminar.
O algoritmo divide "tam" elementos por "streams_nr" e encontra "threadsPerGrid" e "blocksPerGrid"
O vetor no device tem o tamanho de threadsPerGrid.
Caso o nr de streams provoque uma divisao com resto, a ultima grade da stream deve acertar o resto.
Funcionou para teste com stream 03 e tam 16 ou 17 e TPB 2 ou 3
Caso o nr de threads por bloco provoque uma divisao com resto, o algoritmo deve funcionar
com a fitragem do excesso implementada. Funcionou com alguns testes básicos.
Para compilar: nvcc 03-soma-vet-stream.cu -o 03-soma-vet-stream
Para executar: ./03-soma-vet-stream
OBS: os valores de tamanho do vetor e o conteudo do vetor
estao fixos no codigo
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void soma(int *vetorA, int *vetorB,int *vetorC, int tam, int iter)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx < tam)
{
vetorC[idx]=vetorA[idx]+vetorB[idx];
printf("Iter=%d, Blc=%d, Thread=%d, Tam=%d, VetC[%d]=%d \n", iter, blockIdx.x, threadIdx.x, tam, idx, vetorC[idx]);
}
}
int main(int argc,char **argv)
{
int i,*vetorA,*vetorB,*vetorC,threadsPerBlock;
int *vetorA_d,*vetorB_d,*vetorC_d;
//Declaração da variável do tipo cudaStream_t
hipStream_t stream;
//Criação da stream
hipStreamCreate(&stream);
//Define o tamanho do vetor, multiplo de 256
int tam = 16; // 16; // 2048;
//Define a quantidade de threads por bloco
threadsPerBlock = 2; //2; //256;
//Define quantas streams usar
int streams_nr = 2;
//Define o nr de threads por grade (uma grade por vez na stream)
int threadsPerGrid=tam/streams_nr; // threadsPerGrid=8 (16/2) // =1024 (2048/2)
//Define a quantidade de blocos por grade
int blocksPerGrid=(threadsPerGrid+threadsPerBlock-1)/threadsPerBlock; // blockPerStream=4 (8/2) // =4 (1024/256)
// (8+1)/2 ==> 4 (4,5)
// (1024+255)/256 ==> 4 (4,9960)
//
//Aloca memoria nao paginavel para os vetores no host
hipHostMalloc((void**)&vetorA,tam*(sizeof(int)), hipHostMallocDefault);
hipHostMalloc((void**)&vetorB,tam*(sizeof(int)), hipHostMallocDefault);
hipHostMalloc((void**)&vetorC,tam*(sizeof(int)), hipHostMallocDefault);
//Aloca os vetores no device
hipMalloc((void**)&vetorA_d, threadsPerGrid*(sizeof(int)));
hipMalloc((void**)&vetorB_d, threadsPerGrid*(sizeof(int)));
hipMalloc((void**)&vetorC_d, threadsPerGrid*(sizeof(int)));
//Preenche os vetores no host
for(i=0;i<tam;i++)
{
vetorA[i]=i;
vetorB[i]=0;
}
printf("Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n", tam, streams_nr, threadsPerGrid, blocksPerGrid, threadsPerBlock);
// a cada iteracao desloca o bloco em threadsPerGrid itens
// equivale a deslocar streams_nr
for(i=0; i<tam; i+=threadsPerGrid) //i+=8 //i+1024
{
// caso tenha mais streams que o necessario, precisa acertar o tamanho do bloco na ultima stream
// essa ultima stream pega apenas o restante para processas; nao o vlr cheios de threadsPerGrid
if((tam-i)< threadsPerGrid)
threadsPerGrid = tam - i;
//copia um bloco de tamanho threadsPerGrid do vetor A do host para o device
hipMemcpyAsync(vetorA_d,vetorA+i, threadsPerGrid*(sizeof(int)),hipMemcpyHostToDevice,stream);
//copia um bloco de tamanho threadsPerGrid do vetor B do host para o device
hipMemcpyAsync(vetorB_d,vetorB+i, threadsPerGrid*(sizeof(int)),hipMemcpyHostToDevice,stream);
//Invoca o kernel soma passando a stream como argumento
soma <<<blocksPerGrid,threadsPerBlock,0,stream>>> (vetorA_d,vetorB_d,vetorC_d,threadsPerGrid,i);
// <<<4,2>> para alguns dos exemplos acima.
//Copia um bloco de tamanho threadsPerGrid do resultado de volta para o host
hipMemcpyAsync(vetorC+i,vetorC_d,threadsPerGrid*(sizeof(int)),hipMemcpyDeviceToHost,stream);
}
//Sincroniza a stream
hipStreamSynchronize(stream);
//Imprime o resultado no host
for(i=0;i<tam;i++)
{
printf("%d ",vetorC[i]);
}
//Desaloca os vetores no host
hipHostFree(vetorA);
hipHostFree(vetorB);
hipHostFree(vetorC);
//Desaloca os vetores no device
hipFree(vetorA_d);
hipFree(vetorB_d);
hipFree(vetorC_d);
//Destroi a stream
hipStreamDestroy(stream);
} | .text
.file "03-soma-vet-stream.hip"
.globl _Z19__device_stub__somaPiS_S_ii # -- Begin function _Z19__device_stub__somaPiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__somaPiS_S_ii,@function
_Z19__device_stub__somaPiS_S_ii: # @_Z19__device_stub__somaPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4somaPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__somaPiS_S_ii, .Lfunc_end0-_Z19__device_stub__somaPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
callq hipStreamCreate
leaq 56(%rsp), %rdi
xorl %ebx, %ebx
movl $64, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 48(%rsp), %rdi
movl $64, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movl $64, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl $0, (%rcx,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movabsq $4294967298, %rbx # imm = 0x100000002
xorl %ebp, %ebp
movl $8, %r15d
movl $.L.str, %edi
movl $16, %esi
movl $2, %edx
movl $8, %ecx
movl $4, %r8d
movl $2, %r9d
xorl %eax, %eax
callq printf
leaq 2(%rbx), %r14
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
addq 40(%rsp), %r12
movq 16(%rsp), %rsi
movq 8(%rsp), %r8
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpyAsync
addl %r15d, %ebp
cmpl $16, %ebp
jge .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl %r15d, %eax
movl $16, %r15d
subl %ebp, %r15d
cmpl %eax, %r15d
cmovgel %eax, %r15d
movq 32(%rsp), %rdi
movslq %ebp, %r12
shlq $2, %r12
movq 56(%rsp), %rsi
addq %r12, %rsi
movslq %r15d, %r13
shlq $2, %r13
movq 8(%rsp), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi
addq %r12, %rsi
movq 8(%rsp), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r15d, 68(%rsp)
movl %ebp, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 68(%rsp), %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z4somaPiS_S_ii, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq 8(%rsp), %rdi
callq hipStreamSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_7
# %bb.8:
movq 56(%rsp), %rdi
callq hipHostFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipStreamDestroy
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4somaPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4somaPiS_S_ii,@object # @_Z4somaPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4somaPiS_S_ii
.p2align 3, 0x0
_Z4somaPiS_S_ii:
.quad _Z19__device_stub__somaPiS_S_ii
.size _Z4somaPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4somaPiS_S_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__somaPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4somaPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001297ac_00000000-6_03-soma-vet-stream.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4somaPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
.globl _Z4somaPiS_S_ii
.type _Z4somaPiS_S_ii, @function
_Z4somaPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4somaPiS_S_ii, .-_Z4somaPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl $0, (%rdx,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq $2
.cfi_def_cfa_offset 160
movl $4, %r9d
movl $8, %r8d
movl $2, %ecx
movl $16, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
movl $8, %r13d
movl $0, %r12d
movl $16, %r14d
jmp .L14
.L13:
movq %rbx, %rdi
addq 24(%rsp), %rdi
movq 56(%rsp), %r8
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
call cudaMemcpyAsync@PLT
addl %r13d, %r12d
cmpl $15, %r12d
jg .L21
.L14:
movl %r14d, %eax
subl %r12d, %eax
cmpl %eax, %r13d
cmovg %eax, %r13d
movslq %r13d, %rbp
salq $2, %rbp
movslq %r12d, %rbx
salq $2, %rbx
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq 56(%rsp), %r8
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq 56(%rsp), %r8
movl $1, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $2, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movq 56(%rsp), %r9
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %r12d, %r8d
movl %r13d, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z4somaPiS_S_iiPiS_S_ii
jmp .L13
.L21:
movq 56(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
movq 24(%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4somaPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4somaPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "03-soma-vet-stream.hip"
.globl _Z19__device_stub__somaPiS_S_ii # -- Begin function _Z19__device_stub__somaPiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__somaPiS_S_ii,@function
_Z19__device_stub__somaPiS_S_ii: # @_Z19__device_stub__somaPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4somaPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__somaPiS_S_ii, .Lfunc_end0-_Z19__device_stub__somaPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
callq hipStreamCreate
leaq 56(%rsp), %rdi
xorl %ebx, %ebx
movl $64, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 48(%rsp), %rdi
movl $64, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movl $64, %esi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl $0, (%rcx,%rbx,4)
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movabsq $4294967298, %rbx # imm = 0x100000002
xorl %ebp, %ebp
movl $8, %r15d
movl $.L.str, %edi
movl $16, %esi
movl $2, %edx
movl $8, %ecx
movl $4, %r8d
movl $2, %r9d
xorl %eax, %eax
callq printf
leaq 2(%rbx), %r14
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
addq 40(%rsp), %r12
movq 16(%rsp), %rsi
movq 8(%rsp), %r8
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpyAsync
addl %r15d, %ebp
cmpl $16, %ebp
jge .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl %r15d, %eax
movl $16, %r15d
subl %ebp, %r15d
cmpl %eax, %r15d
cmovgel %eax, %r15d
movq 32(%rsp), %rdi
movslq %ebp, %r12
shlq $2, %r12
movq 56(%rsp), %rsi
addq %r12, %rsi
movslq %r15d, %r13
shlq $2, %r13
movq 8(%rsp), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi
addq %r12, %rsi
movq 8(%rsp), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r15d, 68(%rsp)
movl %ebp, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 68(%rsp), %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z4somaPiS_S_ii, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq 8(%rsp), %rdi
callq hipStreamSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_7
# %bb.8:
movq 56(%rsp), %rdi
callq hipHostFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipStreamDestroy
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4somaPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4somaPiS_S_ii,@object # @_Z4somaPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4somaPiS_S_ii
.p2align 3, 0x0
_Z4somaPiS_S_ii:
.quad _Z19__device_stub__somaPiS_S_ii
.size _Z4somaPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host: tam=%d, streams_nr=%d, TPG=%d, BPG=%d, TPB=%d \n"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4somaPiS_S_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__somaPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4somaPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// INCLUDES
// CUDA
// GIS
/**
* PARS
*/
#define BLOCK_DIM_small 64
#define BLOCK_DIM 256
static const unsigned int threads = 512;
bool print_intermediate_arrays = false;
const char *BASE_PATH = "/home/giuliano/git/cuda/reduction";
/*
* kernel labels
*/
const char *kern_0 = "filter_roi";
const char *kern_1 = "imperviousness_change_histc_sh_4" ;
const char *kern_2 = "imperviousness_change" ;
char buffer[255];
/*
* DEFINE I/O files
*/
// I/–
//const char *FIL_ROI = "/home/giuliano/git/cuda/reduction/data/ROI.tif";
//const char *FIL_BIN1 = "/home/giuliano/git/cuda/reduction/data/BIN1.tif";
//const char *FIL_BIN2 = "/home/giuliano/git/cuda/reduction/data/BIN2.tif";
const char *FIL_ROI = "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif";
const char *FIL_BIN1 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif";
const char *FIL_BIN2 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif";
// –/O
const char *FIL_LTAKE_grid = "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif";
const char *FIL_LTAKE_count= "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt";
/* +++++DEFINEs+++++ */
__global__ void imperviousness_change_char( const unsigned char *dev_BIN1, const unsigned char *dev_BIN2, unsigned int WIDTH, unsigned int HEIGHT, char *dev_LTAKE_map )
{
unsigned long int x = threadIdx.x;
unsigned long int bdx = blockDim.x;
unsigned long int bix = blockIdx.x;
unsigned long int tix = bdx*bix + x; // offset
if( tix < WIDTH*HEIGHT ){
dev_LTAKE_map[tix] = dev_BIN2[tix] - dev_BIN1[tix];
}
} | code for sm_80
Function : _Z26imperviousness_change_charPKhS0_jjPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0050*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a25 */
/* 0x001fca00078e0002 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fc8000bf06070 */
/*0080*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0003f06100 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fe20007f1e0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x000fe400007fe4ff */
/*00d0*/ IADD3 R6, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x000fc60007f1e0ff */
/*00e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IADD3.X R7, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1100 */
/*0110*/ IADD3 R2, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R3, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003037a10 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x004fca00078e0a04 */
/*0140*/ PRMT R9, R9, 0x7710, RZ ; /* 0x0000771009097816 */
/* 0x000fca00000000ff */
/*0150*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x008fca00078e0209 */
/*0160*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101104 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// INCLUDES
// CUDA
// GIS
/**
* PARS
*/
#define BLOCK_DIM_small 64
#define BLOCK_DIM 256
static const unsigned int threads = 512;
bool print_intermediate_arrays = false;
const char *BASE_PATH = "/home/giuliano/git/cuda/reduction";
/*
* kernel labels
*/
const char *kern_0 = "filter_roi";
const char *kern_1 = "imperviousness_change_histc_sh_4" ;
const char *kern_2 = "imperviousness_change" ;
char buffer[255];
/*
* DEFINE I/O files
*/
// I/–
//const char *FIL_ROI = "/home/giuliano/git/cuda/reduction/data/ROI.tif";
//const char *FIL_BIN1 = "/home/giuliano/git/cuda/reduction/data/BIN1.tif";
//const char *FIL_BIN2 = "/home/giuliano/git/cuda/reduction/data/BIN2.tif";
const char *FIL_ROI = "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif";
const char *FIL_BIN1 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif";
const char *FIL_BIN2 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif";
// –/O
const char *FIL_LTAKE_grid = "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif";
const char *FIL_LTAKE_count= "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt";
/* +++++DEFINEs+++++ */
__global__ void imperviousness_change_char( const unsigned char *dev_BIN1, const unsigned char *dev_BIN2, unsigned int WIDTH, unsigned int HEIGHT, char *dev_LTAKE_map )
{
unsigned long int x = threadIdx.x;
unsigned long int bdx = blockDim.x;
unsigned long int bix = blockIdx.x;
unsigned long int tix = bdx*bix + x; // offset
if( tix < WIDTH*HEIGHT ){
dev_LTAKE_map[tix] = dev_BIN2[tix] - dev_BIN1[tix];
}
} | .file "tmpxft_00099ae4_00000000-6_imperviousness_change_char.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc
.type _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc, @function
_Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26imperviousness_change_charPKhS0_jjPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc, .-_Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc
.globl _Z26imperviousness_change_charPKhS0_jjPc
.type _Z26imperviousness_change_charPKhS0_jjPc, @function
_Z26imperviousness_change_charPKhS0_jjPc:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26imperviousness_change_charPKhS0_jjPc, .-_Z26imperviousness_change_charPKhS0_jjPc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26imperviousness_change_charPKhS0_jjPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26imperviousness_change_charPKhS0_jjPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl FIL_LTAKE_count
.section .rodata.str1.8
.align 8
.LC1:
.string "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt"
.section .data.rel.local,"aw"
.align 8
.type FIL_LTAKE_count, @object
.size FIL_LTAKE_count, 8
FIL_LTAKE_count:
.quad .LC1
.globl FIL_LTAKE_grid
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif"
.section .data.rel.local
.align 8
.type FIL_LTAKE_grid, @object
.size FIL_LTAKE_grid, 8
FIL_LTAKE_grid:
.quad .LC2
.globl FIL_BIN2
.section .rodata.str1.8
.align 8
.LC3:
.string "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif"
.section .data.rel.local
.align 8
.type FIL_BIN2, @object
.size FIL_BIN2, 8
FIL_BIN2:
.quad .LC3
.globl FIL_BIN1
.section .rodata.str1.8
.align 8
.LC4:
.string "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif"
.section .data.rel.local
.align 8
.type FIL_BIN1, @object
.size FIL_BIN1, 8
FIL_BIN1:
.quad .LC4
.globl FIL_ROI
.section .rodata.str1.8
.align 8
.LC5:
.string "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif"
.section .data.rel.local
.align 8
.type FIL_ROI, @object
.size FIL_ROI, 8
FIL_ROI:
.quad .LC5
.globl buffer
.bss
.align 32
.type buffer, @object
.size buffer, 255
buffer:
.zero 255
.globl kern_2
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "imperviousness_change"
.section .data.rel.local
.align 8
.type kern_2, @object
.size kern_2, 8
kern_2:
.quad .LC6
.globl kern_1
.section .rodata.str1.8
.align 8
.LC7:
.string "imperviousness_change_histc_sh_4"
.section .data.rel.local
.align 8
.type kern_1, @object
.size kern_1, 8
kern_1:
.quad .LC7
.globl kern_0
.section .rodata.str1.1
.LC8:
.string "filter_roi"
.section .data.rel.local
.align 8
.type kern_0, @object
.size kern_0, 8
kern_0:
.quad .LC8
.globl BASE_PATH
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/giuliano/git/cuda/reduction"
.section .data.rel.local
.align 8
.type BASE_PATH, @object
.size BASE_PATH, 8
BASE_PATH:
.quad .LC9
.globl print_intermediate_arrays
.bss
.type print_intermediate_arrays, @object
.size print_intermediate_arrays, 1
print_intermediate_arrays:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// INCLUDES
// CUDA
// GIS
/**
* PARS
*/
#define BLOCK_DIM_small 64
#define BLOCK_DIM 256
static const unsigned int threads = 512;
bool print_intermediate_arrays = false;
const char *BASE_PATH = "/home/giuliano/git/cuda/reduction";
/*
* kernel labels
*/
const char *kern_0 = "filter_roi";
const char *kern_1 = "imperviousness_change_histc_sh_4" ;
const char *kern_2 = "imperviousness_change" ;
char buffer[255];
/*
* DEFINE I/O files
*/
// I/–
//const char *FIL_ROI = "/home/giuliano/git/cuda/reduction/data/ROI.tif";
//const char *FIL_BIN1 = "/home/giuliano/git/cuda/reduction/data/BIN1.tif";
//const char *FIL_BIN2 = "/home/giuliano/git/cuda/reduction/data/BIN2.tif";
const char *FIL_ROI = "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif";
const char *FIL_BIN1 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif";
const char *FIL_BIN2 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif";
// –/O
const char *FIL_LTAKE_grid = "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif";
const char *FIL_LTAKE_count= "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt";
/* +++++DEFINEs+++++ */
__global__ void imperviousness_change_char( const unsigned char *dev_BIN1, const unsigned char *dev_BIN2, unsigned int WIDTH, unsigned int HEIGHT, char *dev_LTAKE_map )
{
unsigned long int x = threadIdx.x;
unsigned long int bdx = blockDim.x;
unsigned long int bix = blockIdx.x;
unsigned long int tix = bdx*bix + x; // offset
if( tix < WIDTH*HEIGHT ){
dev_LTAKE_map[tix] = dev_BIN2[tix] - dev_BIN1[tix];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// INCLUDES
// CUDA
// GIS
/**
* PARS
*/
#define BLOCK_DIM_small 64
#define BLOCK_DIM 256
static const unsigned int threads = 512;
bool print_intermediate_arrays = false;
const char *BASE_PATH = "/home/giuliano/git/cuda/reduction";
/*
* kernel labels
*/
const char *kern_0 = "filter_roi";
const char *kern_1 = "imperviousness_change_histc_sh_4" ;
const char *kern_2 = "imperviousness_change" ;
char buffer[255];
/*
* DEFINE I/O files
*/
// I/–
//const char *FIL_ROI = "/home/giuliano/git/cuda/reduction/data/ROI.tif";
//const char *FIL_BIN1 = "/home/giuliano/git/cuda/reduction/data/BIN1.tif";
//const char *FIL_BIN2 = "/home/giuliano/git/cuda/reduction/data/BIN2.tif";
const char *FIL_ROI = "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif";
const char *FIL_BIN1 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif";
const char *FIL_BIN2 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif";
// –/O
const char *FIL_LTAKE_grid = "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif";
const char *FIL_LTAKE_count= "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt";
/* +++++DEFINEs+++++ */
__global__ void imperviousness_change_char( const unsigned char *dev_BIN1, const unsigned char *dev_BIN2, unsigned int WIDTH, unsigned int HEIGHT, char *dev_LTAKE_map )
{
unsigned long int x = threadIdx.x;
unsigned long int bdx = blockDim.x;
unsigned long int bix = blockIdx.x;
unsigned long int tix = bdx*bix + x; // offset
if( tix < WIDTH*HEIGHT ){
dev_LTAKE_map[tix] = dev_BIN2[tix] - dev_BIN1[tix];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// INCLUDES
// CUDA
// GIS
/**
* PARS
*/
#define BLOCK_DIM_small 64
#define BLOCK_DIM 256
static const unsigned int threads = 512;
bool print_intermediate_arrays = false;
const char *BASE_PATH = "/home/giuliano/git/cuda/reduction";
/*
* kernel labels
*/
const char *kern_0 = "filter_roi";
const char *kern_1 = "imperviousness_change_histc_sh_4" ;
const char *kern_2 = "imperviousness_change" ;
char buffer[255];
/*
* DEFINE I/O files
*/
// I/–
//const char *FIL_ROI = "/home/giuliano/git/cuda/reduction/data/ROI.tif";
//const char *FIL_BIN1 = "/home/giuliano/git/cuda/reduction/data/BIN1.tif";
//const char *FIL_BIN2 = "/home/giuliano/git/cuda/reduction/data/BIN2.tif";
const char *FIL_ROI = "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif";
const char *FIL_BIN1 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif";
const char *FIL_BIN2 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif";
// –/O
const char *FIL_LTAKE_grid = "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif";
const char *FIL_LTAKE_count= "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt";
/* +++++DEFINEs+++++ */
__global__ void imperviousness_change_char( const unsigned char *dev_BIN1, const unsigned char *dev_BIN2, unsigned int WIDTH, unsigned int HEIGHT, char *dev_LTAKE_map )
{
unsigned long int x = threadIdx.x;
unsigned long int bdx = blockDim.x;
unsigned long int bix = blockIdx.x;
unsigned long int tix = bdx*bix + x; // offset
if( tix < WIDTH*HEIGHT ){
dev_LTAKE_map[tix] = dev_BIN2[tix] - dev_BIN1[tix];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26imperviousness_change_charPKhS0_jjPc
.globl _Z26imperviousness_change_charPKhS0_jjPc
.p2align 8
.type _Z26imperviousness_change_charPKhS0_jjPc,@function
_Z26imperviousness_change_charPKhS0_jjPc:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s4, s15, v[0:1]
s_mul_i32 s4, s3, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[2:3]
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_u8 v0, v[0:1], off
global_load_u8 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_nc_u16 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26imperviousness_change_charPKhS0_jjPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26imperviousness_change_charPKhS0_jjPc, .Lfunc_end0-_Z26imperviousness_change_charPKhS0_jjPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26imperviousness_change_charPKhS0_jjPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26imperviousness_change_charPKhS0_jjPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// INCLUDES
// CUDA
// GIS
/**
* PARS
*/
#define BLOCK_DIM_small 64
#define BLOCK_DIM 256
static const unsigned int threads = 512;
bool print_intermediate_arrays = false;
const char *BASE_PATH = "/home/giuliano/git/cuda/reduction";
/*
* kernel labels
*/
const char *kern_0 = "filter_roi";
const char *kern_1 = "imperviousness_change_histc_sh_4" ;
const char *kern_2 = "imperviousness_change" ;
char buffer[255];
/*
* DEFINE I/O files
*/
// I/–
//const char *FIL_ROI = "/home/giuliano/git/cuda/reduction/data/ROI.tif";
//const char *FIL_BIN1 = "/home/giuliano/git/cuda/reduction/data/BIN1.tif";
//const char *FIL_BIN2 = "/home/giuliano/git/cuda/reduction/data/BIN2.tif";
const char *FIL_ROI = "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif";
const char *FIL_BIN1 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif";
const char *FIL_BIN2 = "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif";
// –/O
const char *FIL_LTAKE_grid = "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif";
const char *FIL_LTAKE_count= "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt";
/* +++++DEFINEs+++++ */
__global__ void imperviousness_change_char( const unsigned char *dev_BIN1, const unsigned char *dev_BIN2, unsigned int WIDTH, unsigned int HEIGHT, char *dev_LTAKE_map )
{
unsigned long int x = threadIdx.x;
unsigned long int bdx = blockDim.x;
unsigned long int bix = blockIdx.x;
unsigned long int tix = bdx*bix + x; // offset
if( tix < WIDTH*HEIGHT ){
dev_LTAKE_map[tix] = dev_BIN2[tix] - dev_BIN1[tix];
}
} | .text
.file "imperviousness_change_char.hip"
.globl _Z41__device_stub__imperviousness_change_charPKhS0_jjPc # -- Begin function _Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.p2align 4, 0x90
.type _Z41__device_stub__imperviousness_change_charPKhS0_jjPc,@function
_Z41__device_stub__imperviousness_change_charPKhS0_jjPc: # @_Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26imperviousness_change_charPKhS0_jjPc, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__imperviousness_change_charPKhS0_jjPc, .Lfunc_end0-_Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26imperviousness_change_charPKhS0_jjPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type print_intermediate_arrays,@object # @print_intermediate_arrays
.bss
.globl print_intermediate_arrays
print_intermediate_arrays:
.byte 0 # 0x0
.size print_intermediate_arrays, 1
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/giuliano/git/cuda/reduction"
.size .L.str, 34
.type BASE_PATH,@object # @BASE_PATH
.data
.globl BASE_PATH
.p2align 3, 0x0
BASE_PATH:
.quad .L.str
.size BASE_PATH, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "filter_roi"
.size .L.str.1, 11
.type kern_0,@object # @kern_0
.data
.globl kern_0
.p2align 3, 0x0
kern_0:
.quad .L.str.1
.size kern_0, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "imperviousness_change_histc_sh_4"
.size .L.str.2, 33
.type kern_1,@object # @kern_1
.data
.globl kern_1
.p2align 3, 0x0
kern_1:
.quad .L.str.2
.size kern_1, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "imperviousness_change"
.size .L.str.3, 22
.type kern_2,@object # @kern_2
.data
.globl kern_2
.p2align 3, 0x0
kern_2:
.quad .L.str.3
.size kern_2, 8
.type buffer,@object # @buffer
.bss
.globl buffer
.p2align 4, 0x0
buffer:
.zero 255
.size buffer, 255
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif"
.size .L.str.4, 55
.type FIL_ROI,@object # @FIL_ROI
.data
.globl FIL_ROI
.p2align 3, 0x0
FIL_ROI:
.quad .L.str.4
.size FIL_ROI, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif"
.size .L.str.5, 55
.type FIL_BIN1,@object # @FIL_BIN1
.data
.globl FIL_BIN1
.p2align 3, 0x0
FIL_BIN1:
.quad .L.str.5
.size FIL_BIN1, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif"
.size .L.str.6, 56
.type FIL_BIN2,@object # @FIL_BIN2
.data
.globl FIL_BIN2
.p2align 3, 0x0
FIL_BIN2:
.quad .L.str.6
.size FIL_BIN2, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif"
.size .L.str.7, 53
.type FIL_LTAKE_grid,@object # @FIL_LTAKE_grid
.data
.globl FIL_LTAKE_grid
.p2align 3, 0x0
FIL_LTAKE_grid:
.quad .L.str.7
.size FIL_LTAKE_grid, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt"
.size .L.str.8, 55
.type FIL_LTAKE_count,@object # @FIL_LTAKE_count
.data
.globl FIL_LTAKE_count
.p2align 3, 0x0
FIL_LTAKE_count:
.quad .L.str.8
.size FIL_LTAKE_count, 8
.type _Z26imperviousness_change_charPKhS0_jjPc,@object # @_Z26imperviousness_change_charPKhS0_jjPc
.section .rodata,"a",@progbits
.globl _Z26imperviousness_change_charPKhS0_jjPc
.p2align 3, 0x0
_Z26imperviousness_change_charPKhS0_jjPc:
.quad _Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.size _Z26imperviousness_change_charPKhS0_jjPc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26imperviousness_change_charPKhS0_jjPc"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26imperviousness_change_charPKhS0_jjPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26imperviousness_change_charPKhS0_jjPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0050*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a25 */
/* 0x001fca00078e0002 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fc8000bf06070 */
/*0080*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0003f06100 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fe20007f1e0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x000fe400007fe4ff */
/*00d0*/ IADD3 R6, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x000fc60007f1e0ff */
/*00e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IADD3.X R7, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1100 */
/*0110*/ IADD3 R2, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R3, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003037a10 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x004fca00078e0a04 */
/*0140*/ PRMT R9, R9, 0x7710, RZ ; /* 0x0000771009097816 */
/* 0x000fca00000000ff */
/*0150*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x008fca00078e0209 */
/*0160*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101104 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26imperviousness_change_charPKhS0_jjPc
.globl _Z26imperviousness_change_charPKhS0_jjPc
.p2align 8
.type _Z26imperviousness_change_charPKhS0_jjPc,@function
_Z26imperviousness_change_charPKhS0_jjPc:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s4, s15, v[0:1]
s_mul_i32 s4, s3, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[2:3]
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_u8 v0, v[0:1], off
global_load_u8 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_nc_u16 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26imperviousness_change_charPKhS0_jjPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26imperviousness_change_charPKhS0_jjPc, .Lfunc_end0-_Z26imperviousness_change_charPKhS0_jjPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26imperviousness_change_charPKhS0_jjPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26imperviousness_change_charPKhS0_jjPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00099ae4_00000000-6_imperviousness_change_char.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc
.type _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc, @function
_Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26imperviousness_change_charPKhS0_jjPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc, .-_Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc
.globl _Z26imperviousness_change_charPKhS0_jjPc
.type _Z26imperviousness_change_charPKhS0_jjPc, @function
_Z26imperviousness_change_charPKhS0_jjPc:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z26imperviousness_change_charPKhS0_jjPcPKhS0_jjPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26imperviousness_change_charPKhS0_jjPc, .-_Z26imperviousness_change_charPKhS0_jjPc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26imperviousness_change_charPKhS0_jjPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26imperviousness_change_charPKhS0_jjPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl FIL_LTAKE_count
.section .rodata.str1.8
.align 8
.LC1:
.string "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt"
.section .data.rel.local,"aw"
.align 8
.type FIL_LTAKE_count, @object
.size FIL_LTAKE_count, 8
FIL_LTAKE_count:
.quad .LC1
.globl FIL_LTAKE_grid
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif"
.section .data.rel.local
.align 8
.type FIL_LTAKE_grid, @object
.size FIL_LTAKE_grid, 8
FIL_LTAKE_grid:
.quad .LC2
.globl FIL_BIN2
.section .rodata.str1.8
.align 8
.LC3:
.string "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif"
.section .data.rel.local
.align 8
.type FIL_BIN2, @object
.size FIL_BIN2, 8
FIL_BIN2:
.quad .LC3
.globl FIL_BIN1
.section .rodata.str1.8
.align 8
.LC4:
.string "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif"
.section .data.rel.local
.align 8
.type FIL_BIN1, @object
.size FIL_BIN1, 8
FIL_BIN1:
.quad .LC4
.globl FIL_ROI
.section .rodata.str1.8
.align 8
.LC5:
.string "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif"
.section .data.rel.local
.align 8
.type FIL_ROI, @object
.size FIL_ROI, 8
FIL_ROI:
.quad .LC5
.globl buffer
.bss
.align 32
.type buffer, @object
.size buffer, 255
buffer:
.zero 255
.globl kern_2
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "imperviousness_change"
.section .data.rel.local
.align 8
.type kern_2, @object
.size kern_2, 8
kern_2:
.quad .LC6
.globl kern_1
.section .rodata.str1.8
.align 8
.LC7:
.string "imperviousness_change_histc_sh_4"
.section .data.rel.local
.align 8
.type kern_1, @object
.size kern_1, 8
kern_1:
.quad .LC7
.globl kern_0
.section .rodata.str1.1
.LC8:
.string "filter_roi"
.section .data.rel.local
.align 8
.type kern_0, @object
.size kern_0, 8
kern_0:
.quad .LC8
.globl BASE_PATH
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/giuliano/git/cuda/reduction"
.section .data.rel.local
.align 8
.type BASE_PATH, @object
.size BASE_PATH, 8
BASE_PATH:
.quad .LC9
.globl print_intermediate_arrays
.bss
.type print_intermediate_arrays, @object
.size print_intermediate_arrays, 1
print_intermediate_arrays:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "imperviousness_change_char.hip"
.globl _Z41__device_stub__imperviousness_change_charPKhS0_jjPc # -- Begin function _Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.p2align 4, 0x90
.type _Z41__device_stub__imperviousness_change_charPKhS0_jjPc,@function
_Z41__device_stub__imperviousness_change_charPKhS0_jjPc: # @_Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26imperviousness_change_charPKhS0_jjPc, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__imperviousness_change_charPKhS0_jjPc, .Lfunc_end0-_Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26imperviousness_change_charPKhS0_jjPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type print_intermediate_arrays,@object # @print_intermediate_arrays
.bss
.globl print_intermediate_arrays
print_intermediate_arrays:
.byte 0 # 0x0
.size print_intermediate_arrays, 1
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/giuliano/git/cuda/reduction"
.size .L.str, 34
.type BASE_PATH,@object # @BASE_PATH
.data
.globl BASE_PATH
.p2align 3, 0x0
BASE_PATH:
.quad .L.str
.size BASE_PATH, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "filter_roi"
.size .L.str.1, 11
.type kern_0,@object # @kern_0
.data
.globl kern_0
.p2align 3, 0x0
kern_0:
.quad .L.str.1
.size kern_0, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "imperviousness_change_histc_sh_4"
.size .L.str.2, 33
.type kern_1,@object # @kern_1
.data
.globl kern_1
.p2align 3, 0x0
kern_1:
.quad .L.str.2
.size kern_1, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "imperviousness_change"
.size .L.str.3, 22
.type kern_2,@object # @kern_2
.data
.globl kern_2
.p2align 3, 0x0
kern_2:
.quad .L.str.3
.size kern_2, 8
.type buffer,@object # @buffer
.bss
.globl buffer
.p2align 4, 0x0
buffer:
.zero 255
.size buffer, 255
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "/media/DATI/db-backup/ssgci-data/testing/ssgci_roi.tif"
.size .L.str.4, 55
.type FIL_ROI,@object # @FIL_ROI
.data
.globl FIL_ROI
.p2align 3, 0x0
FIL_ROI:
.quad .L.str.4
.size FIL_ROI, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin.tif"
.size .L.str.5, 55
.type FIL_BIN1,@object # @FIL_BIN1
.data
.globl FIL_BIN1
.p2align 3, 0x0
FIL_BIN1:
.quad .L.str.5
.size FIL_BIN1, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "/media/DATI/db-backup/ssgci-data/testing/ssgci_bin2.tif"
.size .L.str.6, 56
.type FIL_BIN2,@object # @FIL_BIN2
.data
.globl FIL_BIN2
.p2align 3, 0x0
FIL_BIN2:
.quad .L.str.6
.size FIL_BIN2, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "/home/giuliano/git/cuda/reduction/data/LTAKE_map.tif"
.size .L.str.7, 53
.type FIL_LTAKE_grid,@object # @FIL_LTAKE_grid
.data
.globl FIL_LTAKE_grid
.p2align 3, 0x0
FIL_LTAKE_grid:
.quad .L.str.7
.size FIL_LTAKE_grid, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "/home/giuliano/git/cuda/reduction/data/LTAKE_count.txt"
.size .L.str.8, 55
.type FIL_LTAKE_count,@object # @FIL_LTAKE_count
.data
.globl FIL_LTAKE_count
.p2align 3, 0x0
FIL_LTAKE_count:
.quad .L.str.8
.size FIL_LTAKE_count, 8
.type _Z26imperviousness_change_charPKhS0_jjPc,@object # @_Z26imperviousness_change_charPKhS0_jjPc
.section .rodata,"a",@progbits
.globl _Z26imperviousness_change_charPKhS0_jjPc
.p2align 3, 0x0
_Z26imperviousness_change_charPKhS0_jjPc:
.quad _Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.size _Z26imperviousness_change_charPKhS0_jjPc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26imperviousness_change_charPKhS0_jjPc"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__imperviousness_change_charPKhS0_jjPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26imperviousness_change_charPKhS0_jjPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void multiply(int a, int b, int *c) {
*c = a * b;
} | code for sm_80
Function : _Z8multiplyiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a24 */
/* 0x000fca00078e02ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void multiply(int a, int b, int *c) {
*c = a * b;
} | .file "tmpxft_00177750_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8multiplyiiPiiiPi
.type _Z29__device_stub__Z8multiplyiiPiiiPi, @function
_Z29__device_stub__Z8multiplyiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8multiplyiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8multiplyiiPiiiPi, .-_Z29__device_stub__Z8multiplyiiPiiiPi
.globl _Z8multiplyiiPi
.type _Z8multiplyiiPi, @function
_Z8multiplyiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8multiplyiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8multiplyiiPi, .-_Z8multiplyiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8multiplyiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void multiply(int a, int b, int *c) {
*c = a * b;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiply(int a, int b, int *c) {
*c = a * b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiply(int a, int b, int *c) {
*c = a * b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyiiPi
.globl _Z8multiplyiiPi
.p2align 8
.type _Z8multiplyiiPi,@function
_Z8multiplyiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyiiPi, .Lfunc_end0-_Z8multiplyiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z8multiplyiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiply(int a, int b, int *c) {
*c = a * b;
} | .text
.file "multiply.hip"
.globl _Z23__device_stub__multiplyiiPi # -- Begin function _Z23__device_stub__multiplyiiPi
.p2align 4, 0x90
.type _Z23__device_stub__multiplyiiPi,@function
_Z23__device_stub__multiplyiiPi: # @_Z23__device_stub__multiplyiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8multiplyiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyiiPi, .Lfunc_end0-_Z23__device_stub__multiplyiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyiiPi,@object # @_Z8multiplyiiPi
.section .rodata,"a",@progbits
.globl _Z8multiplyiiPi
.p2align 3, 0x0
_Z8multiplyiiPi:
.quad _Z23__device_stub__multiplyiiPi
.size _Z8multiplyiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8multiplyiiPi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a24 */
/* 0x000fca00078e02ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyiiPi
.globl _Z8multiplyiiPi
.p2align 8
.type _Z8multiplyiiPi,@function
_Z8multiplyiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyiiPi, .Lfunc_end0-_Z8multiplyiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z8multiplyiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177750_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8multiplyiiPiiiPi
.type _Z29__device_stub__Z8multiplyiiPiiiPi, @function
_Z29__device_stub__Z8multiplyiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8multiplyiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8multiplyiiPiiiPi, .-_Z29__device_stub__Z8multiplyiiPiiiPi
.globl _Z8multiplyiiPi
.type _Z8multiplyiiPi, @function
_Z8multiplyiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8multiplyiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8multiplyiiPi, .-_Z8multiplyiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8multiplyiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiply.hip"
.globl _Z23__device_stub__multiplyiiPi # -- Begin function _Z23__device_stub__multiplyiiPi
.p2align 4, 0x90
.type _Z23__device_stub__multiplyiiPi,@function
_Z23__device_stub__multiplyiiPi: # @_Z23__device_stub__multiplyiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8multiplyiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyiiPi, .Lfunc_end0-_Z23__device_stub__multiplyiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyiiPi,@object # @_Z8multiplyiiPi
.section .rodata,"a",@progbits
.globl _Z8multiplyiiPi
.p2align 3, 0x0
_Z8multiplyiiPi:
.quad _Z23__device_stub__multiplyiiPi
.size _Z8multiplyiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8multiplyiiPi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define BLOCK_SIZE 32
__global__ void opticalFlowKernel(int* o_gx, int* o_gy, int* arr1dI, int* arr1dJ, int rows, int cols, int wx, int wy, int K) {
__shared__ int I_tile[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int J_tile[BLOCK_SIZE][BLOCK_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int xidx = blockIdx.x * blockDim.x + threadIdx.x;
int yidx = blockIdx.y * blockDim.y + threadIdx.y;
I_tile[ty][tx] = arr1dI[yidx * cols + xidx];
J_tile[ty][tx] = arr1dJ[yidx * cols + xidx];
__syncthreads();
// Initialization of pyramidal guess
float gx = 0, gy = 0;
// Spatial gradient matrix
float Gxx = 0, Gxy = 0, Gyy = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
Gxx += Ix * Ix;
Gxy += Ix * Iy;
Gyy += Iy * Iy;
}
}
}
float det = Gxx * Gyy - Gxy * Gxy;
if(det > 0.00001f) {
// Initialization of iterative L-K
float vx = 0, vy = 0;
for(int k = 0; k < K; k++) {
int Jx = tx + gx + vx;
int Jy = ty + gy + vy;
if(Jx - 1 >= 0 && Jx + 1 < BLOCK_SIZE && Jy - 1 >= 0 && Jy + 1 < BLOCK_SIZE) {
// Image mismatch vector
float bkx = 0, bky = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ik = I_tile[ty+dy][tx+dx] - J_tile[Jy][Jx];
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
bkx += Ik * Ix;
bky += Ik * Iy;
}
}
}
// Optical Flow
float eta_x = (-Gyy * bkx + Gxy * bky) / det;
float eta_y = (Gxy * bkx - Gxx * bky) / det;
// Guess for next iteration
vx += eta_x;
vy += eta_y;
}
}
// Guess for next level
gx += vx;
gy += vy;
}
o_gx[yidx * cols + xidx] = gx;
o_gy[yidx * cols + xidx] = gy;
} | .file "tmpxft_000af738_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii
.type _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii, @function
_Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17opticalFlowKernelPiS_S_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii, .-_Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii
.globl _Z17opticalFlowKernelPiS_S_S_iiiii
.type _Z17opticalFlowKernelPiS_S_S_iiiii, @function
_Z17opticalFlowKernelPiS_S_S_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17opticalFlowKernelPiS_S_S_iiiii, .-_Z17opticalFlowKernelPiS_S_S_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17opticalFlowKernelPiS_S_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17opticalFlowKernelPiS_S_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define BLOCK_SIZE 32
__global__ void opticalFlowKernel(int* o_gx, int* o_gy, int* arr1dI, int* arr1dJ, int rows, int cols, int wx, int wy, int K) {
__shared__ int I_tile[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int J_tile[BLOCK_SIZE][BLOCK_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int xidx = blockIdx.x * blockDim.x + threadIdx.x;
int yidx = blockIdx.y * blockDim.y + threadIdx.y;
I_tile[ty][tx] = arr1dI[yidx * cols + xidx];
J_tile[ty][tx] = arr1dJ[yidx * cols + xidx];
__syncthreads();
// Initialization of pyramidal guess
float gx = 0, gy = 0;
// Spatial gradient matrix
float Gxx = 0, Gxy = 0, Gyy = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
Gxx += Ix * Ix;
Gxy += Ix * Iy;
Gyy += Iy * Iy;
}
}
}
float det = Gxx * Gyy - Gxy * Gxy;
if(det > 0.00001f) {
// Initialization of iterative L-K
float vx = 0, vy = 0;
for(int k = 0; k < K; k++) {
int Jx = tx + gx + vx;
int Jy = ty + gy + vy;
if(Jx - 1 >= 0 && Jx + 1 < BLOCK_SIZE && Jy - 1 >= 0 && Jy + 1 < BLOCK_SIZE) {
// Image mismatch vector
float bkx = 0, bky = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ik = I_tile[ty+dy][tx+dx] - J_tile[Jy][Jx];
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
bkx += Ik * Ix;
bky += Ik * Iy;
}
}
}
// Optical Flow
float eta_x = (-Gyy * bkx + Gxy * bky) / det;
float eta_y = (Gxy * bkx - Gxx * bky) / det;
// Guess for next iteration
vx += eta_x;
vy += eta_y;
}
}
// Guess for next level
gx += vx;
gy += vy;
}
o_gx[yidx * cols + xidx] = gx;
o_gy[yidx * cols + xidx] = gy;
} | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 32
__global__ void opticalFlowKernel(int* o_gx, int* o_gy, int* arr1dI, int* arr1dJ, int rows, int cols, int wx, int wy, int K) {
__shared__ int I_tile[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int J_tile[BLOCK_SIZE][BLOCK_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int xidx = blockIdx.x * blockDim.x + threadIdx.x;
int yidx = blockIdx.y * blockDim.y + threadIdx.y;
I_tile[ty][tx] = arr1dI[yidx * cols + xidx];
J_tile[ty][tx] = arr1dJ[yidx * cols + xidx];
__syncthreads();
// Initialization of pyramidal guess
float gx = 0, gy = 0;
// Spatial gradient matrix
float Gxx = 0, Gxy = 0, Gyy = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
Gxx += Ix * Ix;
Gxy += Ix * Iy;
Gyy += Iy * Iy;
}
}
}
float det = Gxx * Gyy - Gxy * Gxy;
if(det > 0.00001f) {
// Initialization of iterative L-K
float vx = 0, vy = 0;
for(int k = 0; k < K; k++) {
int Jx = tx + gx + vx;
int Jy = ty + gy + vy;
if(Jx - 1 >= 0 && Jx + 1 < BLOCK_SIZE && Jy - 1 >= 0 && Jy + 1 < BLOCK_SIZE) {
// Image mismatch vector
float bkx = 0, bky = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ik = I_tile[ty+dy][tx+dx] - J_tile[Jy][Jx];
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
bkx += Ik * Ix;
bky += Ik * Iy;
}
}
}
// Optical Flow
float eta_x = (-Gyy * bkx + Gxy * bky) / det;
float eta_y = (Gxy * bkx - Gxx * bky) / det;
// Guess for next iteration
vx += eta_x;
vy += eta_y;
}
}
// Guess for next level
gx += vx;
gy += vy;
}
o_gx[yidx * cols + xidx] = gx;
o_gy[yidx * cols + xidx] = gy;
} |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.