system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 32
__global__ void opticalFlowKernel(int* o_gx, int* o_gy, int* arr1dI, int* arr1dJ, int rows, int cols, int wx, int wy, int K) {
__shared__ int I_tile[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int J_tile[BLOCK_SIZE][BLOCK_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int xidx = blockIdx.x * blockDim.x + threadIdx.x;
int yidx = blockIdx.y * blockDim.y + threadIdx.y;
I_tile[ty][tx] = arr1dI[yidx * cols + xidx];
J_tile[ty][tx] = arr1dJ[yidx * cols + xidx];
__syncthreads();
// Initialization of pyramidal guess
float gx = 0, gy = 0;
// Spatial gradient matrix
float Gxx = 0, Gxy = 0, Gyy = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
Gxx += Ix * Ix;
Gxy += Ix * Iy;
Gyy += Iy * Iy;
}
}
}
float det = Gxx * Gyy - Gxy * Gxy;
if(det > 0.00001f) {
// Initialization of iterative L-K
float vx = 0, vy = 0;
for(int k = 0; k < K; k++) {
int Jx = tx + gx + vx;
int Jy = ty + gy + vy;
if(Jx - 1 >= 0 && Jx + 1 < BLOCK_SIZE && Jy - 1 >= 0 && Jy + 1 < BLOCK_SIZE) {
// Image mismatch vector
float bkx = 0, bky = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ik = I_tile[ty+dy][tx+dx] - J_tile[Jy][Jx];
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
bkx += Ik * Ix;
bky += Ik * Iy;
}
}
}
// Optical Flow
float eta_x = (-Gyy * bkx + Gxy * bky) / det;
float eta_y = (Gxy * bkx - Gxx * bky) / det;
// Guess for next iteration
vx += eta_x;
vy += eta_y;
}
}
// Guess for next level
gx += vx;
gy += vy;
}
o_gx[yidx * cols + xidx] = gx;
o_gy[yidx * cols + xidx] = gy;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17opticalFlowKernelPiS_S_S_iiiii
.globl _Z17opticalFlowKernelPiS_S_S_iiiii
.p2align 8
.type _Z17opticalFlowKernelPiS_S_S_iiiii,@function
_Z17opticalFlowKernelPiS_S_S_iiiii:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v9, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s8, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s4, v[2:3]
s_load_b128 s[4:7], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v1, v3, s2
s_and_b32 s2, s8, 0xffff
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s14, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_load_b32 s4, s[0:1], 0x2c
global_load_b32 v7, v[5:6], off
global_load_b32 v8, v[3:4], off
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v4, 2, v9
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v6, v2, 7, v4
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s5, 0, s4
s_cmp_lt_i32 s4, 0
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v6, v7, v8 offset1:16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
s_cmp_gt_i32 s3, -1
s_mov_b32 s8, s5
s_cselect_b32 s6, -1, 0
s_lshl_b32 s2, s3, 2
v_mov_b32_e32 v4, 0
v_subrev_nc_u32_e32 v3, s2, v6
s_lshl_b32 s2, s4, 7
v_xad_u32 v6, s3, -1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v5, s2, v3
v_mov_b32_e32 v3, 0
s_lshl_b32 s2, s3, 1
s_or_b32 s7, s2, 1
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0xffffff80, v5
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_8
.LBB0_2:
v_add3_u32 v10, s8, v2, 0xffffffe1
v_mov_b32_e32 v8, v6
s_mov_b32 s9, s7
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 0xffffffe1, v10
v_mov_b32_e32 v10, v7
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v8, 1, v8
s_add_i32 s9, s9, -1
s_cmp_eq_u32 s9, 0
s_cbranch_scc1 .LBB0_8
.LBB0_5:
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_4
s_mov_b32 s11, exec_lo
v_cmpx_gt_u32_e32 30, v8
s_cbranch_execz .LBB0_3
ds_load_2addr_b32 v[11:12], v10 offset0:33 offset1:64
ds_load_2addr_b32 v[13:14], v10 offset1:31
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v11, v11, v14
v_sub_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v13, 31, v11
v_lshrrev_b32_e32 v14, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v11, v13
v_ashrrev_i32_e32 v11, 1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v11, v11
v_cvt_f32_i32_e32 v13, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v13 :: v_dual_add_nc_u32 v12, v12, v14
v_ashrrev_i32_e32 v12, 1, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v11, v12, v11
v_mul_lo_u32 v12, v12, v12
v_cvt_f32_i32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_dual_add_f32 v4, v4, v11 :: v_dual_add_f32 v5, v5, v12
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v7, 0x80, v7
s_add_i32 s2, s8, 1
s_cmp_eq_u32 s8, s4
s_cbranch_scc1 .LBB0_10
s_mov_b32 s8, s2
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccz .LBB0_2
s_branch .LBB0_8
.LBB0_10:
s_load_b32 s6, s[0:1], 0x30
v_dual_mul_f32 v6, v4, v4 :: v_dual_mov_b32 v7, 0
v_mov_b32_e32 v8, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v5, v3, -v6
v_cmp_lt_f32_e32 vcc_lo, 0x3727c5ac, v6
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s6, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB0_26
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v7, 2, v9
s_cmp_gt_i32 s4, -1
v_cvt_f32_i32_e32 v8, v2
s_cselect_b32 s9, -1, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v7, v2, 7, v7
s_cmp_gt_i32 s3, -1
s_cselect_b32 s10, -1, 0
s_lshl_b32 s2, s3, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v10, s2, v7
s_lshl_b32 s2, s4, 7
v_cvt_f32_i32_e32 v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v11, s2, v10
v_xad_u32 v10, s3, -1, v9
v_mov_b32_e32 v9, 0
s_lshl_b32 s2, s3, 1
v_add_nc_u32_e32 v11, 0xffffff80, v11
s_or_b32 s11, s2, 1
s_branch .LBB0_14
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v15, v5, v14 :: v_dual_mul_f32 v16, v3, v13
v_fma_f32 v13, v4, v13, -v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, v4, v14, -v16
v_div_scale_f32 v15, null, v6, v6, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v16, null, v6, v6, v14
v_div_scale_f32 v21, vcc_lo, v13, v6, v13
v_rcp_f32_e32 v17, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v18, v16
s_waitcnt_depctr 0xfff
v_fma_f32 v19, -v15, v17, 1.0
v_fma_f32 v20, -v16, v18, 1.0
v_dual_fmac_f32 v17, v19, v17 :: v_dual_fmac_f32 v18, v20, v18
v_div_scale_f32 v19, s2, v14, v6, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v20, v21, v17
v_mul_f32_e32 v22, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v23, -v15, v20, v21
v_fma_f32 v24, -v16, v22, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v20, v23, v17
v_fmac_f32_e32 v22, v24, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v15, v20, v21
v_fma_f32 v16, -v16, v22, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v15, v15, v17, v20
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v16, v16, v18, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v13, v15, v6, v13
v_div_fixup_f32 v14, v16, v6, v14
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v12, v12, v13 :: v_dual_add_f32 v9, v9, v14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s6
s_cbranch_scc1 .LBB0_25
.LBB0_14:
v_add_f32_e32 v13, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v15, v13
v_dual_add_f32 v13, v9, v8 :: v_dual_add_nc_u32 v14, -1, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v16, v13
v_cmp_gt_u32_e32 vcc_lo, 30, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s2, 0, v16
v_cmp_gt_i32_e64 s3, 31, v16
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_12
v_dual_mov_b32 v13, 0 :: v_dual_lshlrev_b32 v14, 2, v15
v_dual_mov_b32 v15, v11 :: v_dual_lshlrev_b32 v16, 7, v16
s_mov_b32 s12, s5
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v16, v16, v14, 0x1000
v_mov_b32_e32 v14, 0
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_23
.LBB0_17:
v_add3_u32 v18, s12, v2, 0xffffffe1
v_mov_b32_e32 v17, v10
s_mov_b32 s13, s11
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 0xffffffe1, v18
v_mov_b32_e32 v18, v15
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_20
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s15
.LBB0_19:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v18, 4, v18
v_add_nc_u32_e32 v17, 1, v17
s_add_i32 s13, s13, -1
s_cmp_eq_u32 s13, 0
s_cbranch_scc1 .LBB0_23
.LBB0_20:
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_19
s_mov_b32 s15, exec_lo
v_cmpx_gt_u32_e32 30, v17
s_cbranch_execz .LBB0_18
ds_load_2addr_b32 v[19:20], v18 offset1:31
ds_load_2addr_b32 v[21:22], v18 offset0:32 offset1:33
ds_load_b32 v23, v18 offset:256
ds_load_b32 v24, v16
s_waitcnt lgkmcnt(2)
v_sub_nc_u32_e32 v20, v22, v20
s_waitcnt lgkmcnt(1)
v_sub_nc_u32_e32 v19, v23, v19
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v21, v21, v24
v_lshrrev_b32_e32 v22, 31, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v23, 31, v19
v_add_nc_u32_e32 v19, v19, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v19, 1, v19
v_mul_lo_u32 v19, v19, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v19, v19
v_dual_add_f32 v13, v13, v19 :: v_dual_add_nc_u32 v20, v20, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v20, 1, v20
v_mul_lo_u32 v20, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v20, v20
v_add_f32_e32 v14, v14, v20
s_branch .LBB0_18
.LBB0_23:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v15, 0x80, v15
s_add_i32 s2, s12, 1
s_cmp_eq_u32 s12, s4
s_cbranch_scc1 .LBB0_12
s_mov_b32 s12, s2
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz .LBB0_17
s_branch .LBB0_23
.LBB0_25:
v_dual_add_f32 v2, 0, v12 :: v_dual_add_f32 v3, 0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v7, v2
v_cvt_i32_f32_e32 v8, v3
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s7
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v7, off
global_store_b32 v[0:1], v8, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17opticalFlowKernelPiS_S_S_iiiii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17opticalFlowKernelPiS_S_S_iiiii, .Lfunc_end0-_Z17opticalFlowKernelPiS_S_S_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17opticalFlowKernelPiS_S_S_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17opticalFlowKernelPiS_S_S_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 32
__global__ void opticalFlowKernel(int* o_gx, int* o_gy, int* arr1dI, int* arr1dJ, int rows, int cols, int wx, int wy, int K) {
__shared__ int I_tile[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int J_tile[BLOCK_SIZE][BLOCK_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int xidx = blockIdx.x * blockDim.x + threadIdx.x;
int yidx = blockIdx.y * blockDim.y + threadIdx.y;
I_tile[ty][tx] = arr1dI[yidx * cols + xidx];
J_tile[ty][tx] = arr1dJ[yidx * cols + xidx];
__syncthreads();
// Initialization of pyramidal guess
float gx = 0, gy = 0;
// Spatial gradient matrix
float Gxx = 0, Gxy = 0, Gyy = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
Gxx += Ix * Ix;
Gxy += Ix * Iy;
Gyy += Iy * Iy;
}
}
}
float det = Gxx * Gyy - Gxy * Gxy;
if(det > 0.00001f) {
// Initialization of iterative L-K
float vx = 0, vy = 0;
for(int k = 0; k < K; k++) {
int Jx = tx + gx + vx;
int Jy = ty + gy + vy;
if(Jx - 1 >= 0 && Jx + 1 < BLOCK_SIZE && Jy - 1 >= 0 && Jy + 1 < BLOCK_SIZE) {
// Image mismatch vector
float bkx = 0, bky = 0;
for(int dy = -wy; dy <= wy; dy++) {
for(int dx = -wx; dx <= wx; dx++) {
if(ty + dy - 1 >= 0 && ty + dy + 1 < BLOCK_SIZE && tx + dx - 1 >= 0 && tx + dx + 1 < BLOCK_SIZE) {
int Ik = I_tile[ty+dy][tx+dx] - J_tile[Jy][Jx];
int Ix = (I_tile[ty+dy][tx+dx+1] - I_tile[ty+dy][tx+dx-1]) / 2;
int Iy = (I_tile[ty+dy+1][tx+dx] - I_tile[ty+dy-1][tx+dx]) / 2;
bkx += Ik * Ix;
bky += Ik * Iy;
}
}
}
// Optical Flow
float eta_x = (-Gyy * bkx + Gxy * bky) / det;
float eta_y = (Gxy * bkx - Gxx * bky) / det;
// Guess for next iteration
vx += eta_x;
vy += eta_y;
}
}
// Guess for next level
gx += vx;
gy += vy;
}
o_gx[yidx * cols + xidx] = gx;
o_gy[yidx * cols + xidx] = gy;
} | .text
.file "kernel.hip"
.globl _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii # -- Begin function _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.p2align 4, 0x90
.type _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii,@function
_Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii: # @_Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17opticalFlowKernelPiS_S_S_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii, .Lfunc_end0-_Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17opticalFlowKernelPiS_S_S_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17opticalFlowKernelPiS_S_S_iiiii,@object # @_Z17opticalFlowKernelPiS_S_S_iiiii
.section .rodata,"a",@progbits
.globl _Z17opticalFlowKernelPiS_S_S_iiiii
.p2align 3, 0x0
_Z17opticalFlowKernelPiS_S_S_iiiii:
.quad _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.size _Z17opticalFlowKernelPiS_S_S_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17opticalFlowKernelPiS_S_S_iiiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17opticalFlowKernelPiS_S_S_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000af738_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii
.type _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii, @function
_Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17opticalFlowKernelPiS_S_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii, .-_Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii
.globl _Z17opticalFlowKernelPiS_S_S_iiiii
.type _Z17opticalFlowKernelPiS_S_S_iiiii, @function
_Z17opticalFlowKernelPiS_S_S_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z17opticalFlowKernelPiS_S_S_iiiiiPiS_S_S_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17opticalFlowKernelPiS_S_S_iiiii, .-_Z17opticalFlowKernelPiS_S_S_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17opticalFlowKernelPiS_S_S_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17opticalFlowKernelPiS_S_S_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii # -- Begin function _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.p2align 4, 0x90
.type _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii,@function
_Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii: # @_Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17opticalFlowKernelPiS_S_S_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii, .Lfunc_end0-_Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17opticalFlowKernelPiS_S_S_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17opticalFlowKernelPiS_S_S_iiiii,@object # @_Z17opticalFlowKernelPiS_S_S_iiiii
.section .rodata,"a",@progbits
.globl _Z17opticalFlowKernelPiS_S_S_iiiii
.p2align 3, 0x0
_Z17opticalFlowKernelPiS_S_S_iiiii:
.quad _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.size _Z17opticalFlowKernelPiS_S_S_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17opticalFlowKernelPiS_S_S_iiiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__opticalFlowKernelPiS_S_S_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17opticalFlowKernelPiS_S_S_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#define LIST_SIZE 100000
__device__ unsigned long long instCountList[LIST_SIZE];
__device__ int init_flag = 0;
extern "C" __device__ void profileCount(long index){
if(init_flag == 0){
int i = 0;
for(i=0;i<LIST_SIZE;i++){
instCountList[i] = 0;
}
//init_flag = 1;
atomicAdd(&init_flag, 1);
}
atomicAdd(&instCountList[index], 1);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#define LIST_SIZE 100000
__device__ unsigned long long instCountList[LIST_SIZE];
__device__ int init_flag = 0;
extern "C" __device__ void profileCount(long index){
if(init_flag == 0){
int i = 0;
for(i=0;i<LIST_SIZE;i++){
instCountList[i] = 0;
}
//init_flag = 1;
atomicAdd(&init_flag, 1);
}
atomicAdd(&instCountList[index], 1);
} | .file "tmpxft_00042364_00000000-6_instCount.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl profileCount
.type profileCount, @function
profileCount:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size profileCount, .-profileCount
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "instCountList"
.LC1:
.string "init_flag"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $800000, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13instCountList(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9init_flag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9init_flag
.comm _ZL9init_flag,4,4
.local _ZL13instCountList
.comm _ZL13instCountList,800000,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#define LIST_SIZE 100000
__device__ unsigned long long instCountList[LIST_SIZE];
__device__ int init_flag = 0;
extern "C" __device__ void profileCount(long index){
if(init_flag == 0){
int i = 0;
for(i=0;i<LIST_SIZE;i++){
instCountList[i] = 0;
}
//init_flag = 1;
atomicAdd(&init_flag, 1);
}
atomicAdd(&instCountList[index], 1);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#define LIST_SIZE 100000
__device__ unsigned long long instCountList[LIST_SIZE];
__device__ int init_flag = 0;
extern "C" __device__ void profileCount(long index){
if(init_flag == 0){
int i = 0;
for(i=0;i<LIST_SIZE;i++){
instCountList[i] = 0;
}
//init_flag = 1;
atomicAdd(&init_flag, 1);
}
atomicAdd(&instCountList[index], 1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#define LIST_SIZE 100000
__device__ unsigned long long instCountList[LIST_SIZE];
__device__ int init_flag = 0;
extern "C" __device__ void profileCount(long index){
if(init_flag == 0){
int i = 0;
for(i=0;i<LIST_SIZE;i++){
instCountList[i] = 0;
}
//init_flag = 1;
atomicAdd(&init_flag, 1);
}
atomicAdd(&instCountList[index], 1);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected instCountList
.type instCountList,@object
.section .bss,"aw",@nobits
.globl instCountList
.p2align 4, 0x0
instCountList:
.zero 800000
.size instCountList, 800000
.protected init_flag
.type init_flag,@object
.globl init_flag
.p2align 2, 0x0
init_flag:
.long 0
.size init_flag, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym instCountList
.addrsig_sym init_flag
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#define LIST_SIZE 100000
__device__ unsigned long long instCountList[LIST_SIZE];
__device__ int init_flag = 0;
extern "C" __device__ void profileCount(long index){
if(init_flag == 0){
int i = 0;
for(i=0;i<LIST_SIZE;i++){
instCountList[i] = 0;
}
//init_flag = 1;
atomicAdd(&init_flag, 1);
}
atomicAdd(&instCountList[index], 1);
} | .text
.file "instCount.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rbx
movl $instCountList, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $800000, %r9d # imm = 0xC3500
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $init_flag, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type instCountList,@object # @instCountList
.local instCountList
.comm instCountList,800000,16
.type init_flag,@object # @init_flag
.local init_flag
.comm init_flag,4,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "instCountList"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "init_flag"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym instCountList
.addrsig_sym init_flag
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected instCountList
.type instCountList,@object
.section .bss,"aw",@nobits
.globl instCountList
.p2align 4, 0x0
instCountList:
.zero 800000
.size instCountList, 800000
.protected init_flag
.type init_flag,@object
.globl init_flag
.p2align 2, 0x0
init_flag:
.long 0
.size init_flag, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym instCountList
.addrsig_sym init_flag
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00042364_00000000-6_instCount.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl profileCount
.type profileCount, @function
profileCount:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size profileCount, .-profileCount
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "instCountList"
.LC1:
.string "init_flag"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $800000, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13instCountList(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9init_flag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9init_flag
.comm _ZL9init_flag,4,4
.local _ZL13instCountList
.comm _ZL13instCountList,800000,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "instCount.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rbx
movl $instCountList, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $800000, %r9d # imm = 0xC3500
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $init_flag, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type instCountList,@object # @instCountList
.local instCountList
.comm instCountList,800000,16
.type init_flag,@object # @init_flag
.local init_flag
.comm init_flag,4,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "instCountList"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "init_flag"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym instCountList
.addrsig_sym init_flag
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define EMPTY 0
#define RED 1
#define BLUE 2
__global__ void init_kernel(int * domain, int domain_x)
{
// Dummy initialization
domain[blockIdx.y * domain_x + blockIdx.x * blockDim.x + threadIdx.x]
= ((blockIdx.x+threadIdx.x) == 0 ? 1 : 0);
//= (1664525ul * (blockIdx.x + threadIdx.y + threadIdx.x) + 1013904223ul) % 3;
}
// Reads a cell at (x+dx, y+dy)
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y)
{
x = (unsigned int)(x + dx) % domain_x; // Wrap around
y = (unsigned int)(y + dy) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void inc_color(int cell, int *nb_blue, int *nb_red) {
if (cell == BLUE) (*nb_blue)++;
else if (cell == RED) (*nb_red)++;
}
// Compute kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y)
{
int ty = blockIdx.y * blockDim.y + threadIdx.y;
int pos_y = threadIdx.y + 1;
__shared__ int shared_bloc[18][10];
for (int i = 0, pos_x = 1, tx = blockIdx.x * blockDim.x; i < 16; i++, tx++, pos_x++) {
// Read cell
shared_bloc[pos_x][pos_y] = read_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y);
if (pos_x == 1)
shared_bloc[pos_x-1][pos_y] = read_cell(source_domain, tx, ty, -1, 0, domain_x, domain_y);
else if (pos_x == 16)
shared_bloc[pos_x+1][pos_y] = read_cell(source_domain, tx, ty, 1, 0, domain_x, domain_y);
if (pos_y == 1)
shared_bloc[pos_x][pos_y-1] = read_cell(source_domain, tx, ty, 0, -1, domain_x, domain_y);
else if (pos_y == 8)
shared_bloc[pos_x][pos_y+1] = read_cell(source_domain, tx, ty, 0, 1, domain_x, domain_y);
if (pos_x == 1 && pos_y == 1)
shared_bloc[pos_x-1][pos_y-1] = read_cell(source_domain, tx, ty, -1, -1, domain_x, domain_y);
else if (pos_x == 1 && pos_y == 8)
shared_bloc[pos_x-1][pos_y+1] = read_cell(source_domain, tx, ty, -1, 1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 1)
shared_bloc[pos_x+1][pos_y-1] = read_cell(source_domain, tx, ty, 1, -1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 8)
shared_bloc[pos_x+1][pos_y+1] = read_cell(source_domain, tx, ty, 1, 1, domain_x, domain_y);
// Read the 8 neighbors and count number of blue and red
int nb_blue = 0, nb_red = 0;
__syncthreads();
inc_color(shared_bloc[pos_x][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y+1], &nb_blue, &nb_red);
// Compute new value
int res = 0;
if (shared_bloc[pos_x][pos_y] != 0 && (nb_blue + nb_red == 2 || nb_blue + nb_red == 3))
res = shared_bloc[pos_x][pos_y];
else if (shared_bloc[pos_x][pos_y] == 0 && nb_blue + nb_red == 3) {
if (nb_blue > nb_red)
res = BLUE;
else
res = RED;
}
// Write it in dest_domain
dest_domain[ty * domain_x + tx] = res;
}
} | .file "tmpxft_000dd7b3_00000000-6_life_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9read_cellPiiiiijj
.type _Z9read_cellPiiiiijj, @function
_Z9read_cellPiiiiijj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9read_cellPiiiiijj, .-_Z9read_cellPiiiiijj
.globl _Z9inc_coloriPiS_
.type _Z9inc_coloriPiS_, @function
_Z9inc_coloriPiS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z9inc_coloriPiS_, .-_Z9inc_coloriPiS_
.globl _Z32__device_stub__Z11init_kernelPiiPii
.type _Z32__device_stub__Z11init_kernelPiiPii, @function
_Z32__device_stub__Z11init_kernelPiiPii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11init_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z11init_kernelPiiPii, .-_Z32__device_stub__Z11init_kernelPiiPii
.globl _Z11init_kernelPii
.type _Z11init_kernelPii, @function
_Z11init_kernelPii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11init_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11init_kernelPii, .-_Z11init_kernelPii
.globl _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.type _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, @function
_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11life_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, .-_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.globl _Z11life_kernelPiS_ii
.type _Z11life_kernelPiS_ii, @function
_Z11life_kernelPiS_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z11life_kernelPiS_ii, .-_Z11life_kernelPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11life_kernelPiS_ii"
.LC1:
.string "_Z11init_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11life_kernelPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_kernelPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define EMPTY 0
#define RED 1
#define BLUE 2
__global__ void init_kernel(int * domain, int domain_x)
{
// Dummy initialization
domain[blockIdx.y * domain_x + blockIdx.x * blockDim.x + threadIdx.x]
= ((blockIdx.x+threadIdx.x) == 0 ? 1 : 0);
//= (1664525ul * (blockIdx.x + threadIdx.y + threadIdx.x) + 1013904223ul) % 3;
}
// Reads a cell at (x+dx, y+dy)
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y)
{
x = (unsigned int)(x + dx) % domain_x; // Wrap around
y = (unsigned int)(y + dy) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void inc_color(int cell, int *nb_blue, int *nb_red) {
if (cell == BLUE) (*nb_blue)++;
else if (cell == RED) (*nb_red)++;
}
// Compute kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y)
{
int ty = blockIdx.y * blockDim.y + threadIdx.y;
int pos_y = threadIdx.y + 1;
__shared__ int shared_bloc[18][10];
for (int i = 0, pos_x = 1, tx = blockIdx.x * blockDim.x; i < 16; i++, tx++, pos_x++) {
// Read cell
shared_bloc[pos_x][pos_y] = read_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y);
if (pos_x == 1)
shared_bloc[pos_x-1][pos_y] = read_cell(source_domain, tx, ty, -1, 0, domain_x, domain_y);
else if (pos_x == 16)
shared_bloc[pos_x+1][pos_y] = read_cell(source_domain, tx, ty, 1, 0, domain_x, domain_y);
if (pos_y == 1)
shared_bloc[pos_x][pos_y-1] = read_cell(source_domain, tx, ty, 0, -1, domain_x, domain_y);
else if (pos_y == 8)
shared_bloc[pos_x][pos_y+1] = read_cell(source_domain, tx, ty, 0, 1, domain_x, domain_y);
if (pos_x == 1 && pos_y == 1)
shared_bloc[pos_x-1][pos_y-1] = read_cell(source_domain, tx, ty, -1, -1, domain_x, domain_y);
else if (pos_x == 1 && pos_y == 8)
shared_bloc[pos_x-1][pos_y+1] = read_cell(source_domain, tx, ty, -1, 1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 1)
shared_bloc[pos_x+1][pos_y-1] = read_cell(source_domain, tx, ty, 1, -1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 8)
shared_bloc[pos_x+1][pos_y+1] = read_cell(source_domain, tx, ty, 1, 1, domain_x, domain_y);
// Read the 8 neighbors and count number of blue and red
int nb_blue = 0, nb_red = 0;
__syncthreads();
inc_color(shared_bloc[pos_x][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y+1], &nb_blue, &nb_red);
// Compute new value
int res = 0;
if (shared_bloc[pos_x][pos_y] != 0 && (nb_blue + nb_red == 2 || nb_blue + nb_red == 3))
res = shared_bloc[pos_x][pos_y];
else if (shared_bloc[pos_x][pos_y] == 0 && nb_blue + nb_red == 3) {
if (nb_blue > nb_red)
res = BLUE;
else
res = RED;
}
// Write it in dest_domain
dest_domain[ty * domain_x + tx] = res;
}
} | #include <hip/hip_runtime.h>
#define EMPTY 0
#define RED 1
#define BLUE 2
__global__ void init_kernel(int * domain, int domain_x)
{
// Dummy initialization
domain[blockIdx.y * domain_x + blockIdx.x * blockDim.x + threadIdx.x]
= ((blockIdx.x+threadIdx.x) == 0 ? 1 : 0);
//= (1664525ul * (blockIdx.x + threadIdx.y + threadIdx.x) + 1013904223ul) % 3;
}
// Reads a cell at (x+dx, y+dy)
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y)
{
x = (unsigned int)(x + dx) % domain_x; // Wrap around
y = (unsigned int)(y + dy) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void inc_color(int cell, int *nb_blue, int *nb_red) {
if (cell == BLUE) (*nb_blue)++;
else if (cell == RED) (*nb_red)++;
}
// Compute kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y)
{
int ty = blockIdx.y * blockDim.y + threadIdx.y;
int pos_y = threadIdx.y + 1;
__shared__ int shared_bloc[18][10];
for (int i = 0, pos_x = 1, tx = blockIdx.x * blockDim.x; i < 16; i++, tx++, pos_x++) {
// Read cell
shared_bloc[pos_x][pos_y] = read_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y);
if (pos_x == 1)
shared_bloc[pos_x-1][pos_y] = read_cell(source_domain, tx, ty, -1, 0, domain_x, domain_y);
else if (pos_x == 16)
shared_bloc[pos_x+1][pos_y] = read_cell(source_domain, tx, ty, 1, 0, domain_x, domain_y);
if (pos_y == 1)
shared_bloc[pos_x][pos_y-1] = read_cell(source_domain, tx, ty, 0, -1, domain_x, domain_y);
else if (pos_y == 8)
shared_bloc[pos_x][pos_y+1] = read_cell(source_domain, tx, ty, 0, 1, domain_x, domain_y);
if (pos_x == 1 && pos_y == 1)
shared_bloc[pos_x-1][pos_y-1] = read_cell(source_domain, tx, ty, -1, -1, domain_x, domain_y);
else if (pos_x == 1 && pos_y == 8)
shared_bloc[pos_x-1][pos_y+1] = read_cell(source_domain, tx, ty, -1, 1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 1)
shared_bloc[pos_x+1][pos_y-1] = read_cell(source_domain, tx, ty, 1, -1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 8)
shared_bloc[pos_x+1][pos_y+1] = read_cell(source_domain, tx, ty, 1, 1, domain_x, domain_y);
// Read the 8 neighbors and count number of blue and red
int nb_blue = 0, nb_red = 0;
__syncthreads();
inc_color(shared_bloc[pos_x][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y+1], &nb_blue, &nb_red);
// Compute new value
int res = 0;
if (shared_bloc[pos_x][pos_y] != 0 && (nb_blue + nb_red == 2 || nb_blue + nb_red == 3))
res = shared_bloc[pos_x][pos_y];
else if (shared_bloc[pos_x][pos_y] == 0 && nb_blue + nb_red == 3) {
if (nb_blue > nb_red)
res = BLUE;
else
res = RED;
}
// Write it in dest_domain
dest_domain[ty * domain_x + tx] = res;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define EMPTY 0
#define RED 1
#define BLUE 2
__global__ void init_kernel(int * domain, int domain_x)
{
// Dummy initialization
domain[blockIdx.y * domain_x + blockIdx.x * blockDim.x + threadIdx.x]
= ((blockIdx.x+threadIdx.x) == 0 ? 1 : 0);
//= (1664525ul * (blockIdx.x + threadIdx.y + threadIdx.x) + 1013904223ul) % 3;
}
// Reads a cell at (x+dx, y+dy)
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y)
{
x = (unsigned int)(x + dx) % domain_x; // Wrap around
y = (unsigned int)(y + dy) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void inc_color(int cell, int *nb_blue, int *nb_red) {
if (cell == BLUE) (*nb_blue)++;
else if (cell == RED) (*nb_red)++;
}
// Compute kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y)
{
int ty = blockIdx.y * blockDim.y + threadIdx.y;
int pos_y = threadIdx.y + 1;
__shared__ int shared_bloc[18][10];
for (int i = 0, pos_x = 1, tx = blockIdx.x * blockDim.x; i < 16; i++, tx++, pos_x++) {
// Read cell
shared_bloc[pos_x][pos_y] = read_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y);
if (pos_x == 1)
shared_bloc[pos_x-1][pos_y] = read_cell(source_domain, tx, ty, -1, 0, domain_x, domain_y);
else if (pos_x == 16)
shared_bloc[pos_x+1][pos_y] = read_cell(source_domain, tx, ty, 1, 0, domain_x, domain_y);
if (pos_y == 1)
shared_bloc[pos_x][pos_y-1] = read_cell(source_domain, tx, ty, 0, -1, domain_x, domain_y);
else if (pos_y == 8)
shared_bloc[pos_x][pos_y+1] = read_cell(source_domain, tx, ty, 0, 1, domain_x, domain_y);
if (pos_x == 1 && pos_y == 1)
shared_bloc[pos_x-1][pos_y-1] = read_cell(source_domain, tx, ty, -1, -1, domain_x, domain_y);
else if (pos_x == 1 && pos_y == 8)
shared_bloc[pos_x-1][pos_y+1] = read_cell(source_domain, tx, ty, -1, 1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 1)
shared_bloc[pos_x+1][pos_y-1] = read_cell(source_domain, tx, ty, 1, -1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 8)
shared_bloc[pos_x+1][pos_y+1] = read_cell(source_domain, tx, ty, 1, 1, domain_x, domain_y);
// Read the 8 neighbors and count number of blue and red
int nb_blue = 0, nb_red = 0;
__syncthreads();
inc_color(shared_bloc[pos_x][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y+1], &nb_blue, &nb_red);
// Compute new value
int res = 0;
if (shared_bloc[pos_x][pos_y] != 0 && (nb_blue + nb_red == 2 || nb_blue + nb_red == 3))
res = shared_bloc[pos_x][pos_y];
else if (shared_bloc[pos_x][pos_y] == 0 && nb_blue + nb_red == 3) {
if (nb_blue > nb_red)
res = BLUE;
else
res = RED;
}
// Write it in dest_domain
dest_domain[ty * domain_x + tx] = res;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_kernelPii
.globl _Z11init_kernelPii
.p2align 8
.type _Z11init_kernelPii,@function
_Z11init_kernelPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_sub_nc_u32_e32 v3, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s14, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s2, s14, s2
v_add3_u32 v1, s2, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_kernelPii, .Lfunc_end0-_Z11init_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11life_kernelPiS_ii
.globl _Z11life_kernelPiS_ii
.p2align 8
.type _Z11life_kernelPiS_ii,@function
_Z11life_kernelPiS_ii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x24
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v7, 2, v0
v_mov_b32_e32 v15, v7
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s9
s_sub_i32 s2, 0, s9
s_sub_i32 s3, 0, s8
s_and_b32 s0, s10, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_mul_i32 s0, s14, s0
v_rcp_iflag_f32_e32 v1, v1
s_mov_b32 s13, s0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v1
s_lshr_b32 s2, s10, 16
v_mul_hi_u32 v4, v1, v2
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, 1, -1, s2
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v1, s8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v11, v2, v6
v_mul_hi_u32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v1, v1
v_mul_hi_u32 v9, v11, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v5, v4, s9
v_cndmask_b32_e64 v4, 0x4c, 40, s2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_lo_u32 v12, v9, s9
v_add_nc_u32_e32 v9, 1, v2
v_sub_nc_u32_e32 v8, v2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_u32_f32_e32 v6, v1
v_add_nc_u32_e32 v5, 1, v0
v_sub_nc_u32_e32 v11, v11, v12
v_subrev_nc_u32_e32 v1, s9, v8
v_cmp_le_u32_e32 vcc_lo, s9, v8
v_mul_lo_u32 v0, s3, v6
v_cmp_eq_u32_e64 s1, 8, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v1, v8, v1 :: v_dual_add_nc_u32 v8, 0x2a8, v7
s_or_b32 s12, s2, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v14, v6, v0
v_subrev_nc_u32_e32 v10, s9, v1
v_cmp_le_u32_e32 vcc_lo, s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v13, v1, v10, vcc_lo
v_mad_u64_u32 v[0:1], null, v2, s8, s[0:1]
v_add_nc_u32_e32 v10, -1, v2
v_mov_b32_e32 v2, 0
v_mul_lo_u32 v12, v13, s8
v_subrev_nc_u32_e32 v13, s9, v11
v_add_nc_u32_e32 v14, v6, v14
s_branch .LBB1_3
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s14
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v18, s11, v0
v_add_nc_u32_e32 v4, 40, v4
v_add_nc_u32_e32 v15, 40, v15
s_add_i32 s11, s11, 1
s_add_i32 s13, s13, 1
v_ashrrev_i32_e32 v19, 31, v18
s_cmp_eq_u32 s11, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_add_co_u32 v18, vcc_lo, s6, v18
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
global_store_b32 v[18:19], v17, off
s_cbranch_scc1 .LBB1_86
.LBB1_3:
v_readfirstlane_b32 s10, v6
s_mov_b32 s15, 0
s_mov_b32 s16, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s14, s3, s10
s_mul_hi_u32 s14, s10, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s10, s14
s_mul_hi_u32 s10, s13, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_not_b32 s14, s10
s_mul_i32 s10, s3, s10
s_mul_i32 s14, s8, s14
s_add_i32 s10, s13, s10
s_add_i32 s14, s13, s14
s_cmp_ge_u32 s10, s8
s_cselect_b32 s10, s14, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s14, s10, s8
s_cmp_ge_u32 s10, s8
s_cselect_b32 s10, s14, s10
s_cmp_eq_u32 s11, 0
v_add_nc_u32_e32 v1, s10, v12
s_cselect_b32 s14, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s17, s14
v_lshlrev_b64 v[16:17], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
s_and_b32 vcc_lo, exec_lo, s14
global_load_b32 v1, v[16:17], off
s_waitcnt vmcnt(0)
ds_store_b32 v15, v1 offset:44
s_cbranch_vccz .LBB1_84
s_and_not1_b32 vcc_lo, exec_lo, s17
s_cbranch_vccz .LBB1_85
.LBB1_5:
s_and_saveexec_b32 s15, s12
s_cbranch_execz .LBB1_7
.LBB1_6:
v_cmp_le_u32_e32 vcc_lo, s9, v11
v_cndmask_b32_e32 v1, v11, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v16, s9, v1
v_cmp_le_u32_e32 vcc_lo, s9, v1
v_cndmask_b32_e32 v1, v1, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[16:17], null, v1, s8, s[10:11]
v_mov_b32_e32 v17, v2
v_lshlrev_b64 v[16:17], 2, v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b32 v1, v[16:17], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s15
v_dual_mov_b32 v17, -1 :: v_dual_mov_b32 v16, v10
v_mov_b32_e32 v1, v7
s_and_b32 s10, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s16, s10, -1
s_and_saveexec_b32 s15, s16
s_cbranch_execz .LBB1_13
v_dual_mov_b32 v1, 36 :: v_dual_mov_b32 v16, v9
v_mov_b32_e32 v17, -1
s_and_b32 s14, s14, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s17, s14, -1
s_and_saveexec_b32 s16, s17
s_cbranch_execz .LBB1_12
s_cmp_eq_u32 s11, 15
v_dual_mov_b32 v1, v8 :: v_dual_mov_b32 v16, v10
s_cselect_b32 s19, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s17, s2, s19
s_xor_b32 s20, s17, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s18, s20
s_and_b32 s19, s19, s1
v_dual_mov_b32 v1, 0x2cc :: v_dual_mov_b32 v16, v9
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s19, s19, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s17, s17, s19
s_or_b32 exec_lo, exec_lo, s18
v_mov_b32_e32 v17, 1
s_and_not1_b32 s14, s14, exec_lo
s_and_b32 s17, s17, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s14, s17
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s10, s10, exec_lo
s_and_b32 s14, s14, exec_lo
s_or_b32 s10, s10, s14
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s14, s10
s_cbranch_execz .LBB1_15
v_add_nc_u32_e32 v18, s13, v17
v_mul_hi_u32 v19, v16, v3
v_add3_u32 v17, s11, s0, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v20, v18, v14
v_mul_lo_u32 v21, v19, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[18:19], null, s3, v20, v[17:18]
v_not_b32_e32 v22, v20
v_sub_nc_u32_e32 v16, v16, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[19:20], null, s8, v22, v[17:18]
v_cmp_le_u32_e32 vcc_lo, s8, v18
v_subrev_nc_u32_e32 v17, s9, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v18, v18, v19, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s9, v16
v_cndmask_b32_e32 v17, v16, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v16, s8, v18
v_cmp_le_u32_e32 vcc_lo, s8, v18
v_subrev_nc_u32_e32 v19, s9, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v16, v18, v16, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s9, v17
v_cndmask_b32_e32 v19, v17, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[17:18], null, v19, s8, v[16:17]
v_mov_b32_e32 v18, v2
v_lshlrev_b64 v[16:17], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b32 v16, v[16:17], off
s_waitcnt vmcnt(0)
ds_store_b32 v1, v16
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v17, v15 offset:40
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_19
v_mov_b32_e32 v1, 0
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_mov_b32_e32 v1, 1
s_or_b32 exec_lo, exec_lo, s14
s_mov_b32 s14, 0
.LBB1_19:
s_or_saveexec_b32 s10, s10
v_mov_b32_e32 v16, s14
s_xor_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB1_23
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v16, 0
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_mov_b32_e32 v16, 1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_23:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15 offset:48
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_27
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_27:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_31
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_31:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15 offset:4
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_35
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_35:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_39
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15 offset:84
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_43
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_43:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_47
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_47:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15 offset:80
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_51
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_51:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_55
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_55:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15 offset:8
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_59
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_59:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_63
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_63:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_67
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_67:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_71
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_71:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v17, v15 offset:88
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 1, v17
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_75
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 2, v17
v_add_nc_u32_e32 v1, 1, v1
s_or_b32 exec_lo, exec_lo, s14
.LBB1_75:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_79
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 1, v17
v_add_nc_u32_e32 v16, 1, v16
s_or_b32 exec_lo, exec_lo, s14
.LBB1_79:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v19, v15 offset:44
v_add_nc_u32_e32 v18, v16, v1
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e32 0, v19
s_xor_b32 s10, exec_lo, s10
v_and_b32_e32 v1, -2, v18
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 2, v1
v_cndmask_b32_e32 v17, 0, v19, vcc_lo
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v17, 0
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e32 3, v18
s_cbranch_execz .LBB1_1
v_cmp_gt_i32_e32 vcc_lo, v1, v16
v_cndmask_b32_e64 v17, 1, 2, vcc_lo
s_branch .LBB1_1
.LBB1_84:
s_cmp_eq_u32 s11, 15
s_movk_i32 s15, 0x2a8
s_mov_b32 s16, 1
s_cselect_b32 s17, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s17
s_cbranch_vccnz .LBB1_5
.LBB1_85:
v_readfirstlane_b32 s17, v6
s_add_i32 s19, s16, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s18, s3, s17
s_mul_hi_u32 s18, s17, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s17, s17, s18
s_add_i32 s18, s0, s11
s_mul_hi_u32 s17, s19, s17
s_add_i32 s16, s18, s16
s_not_b32 s18, s17
s_mul_i32 s17, s3, s17
s_mul_i32 s18, s8, s18
s_add_i32 s17, s16, s17
s_add_i32 s16, s16, s18
s_cmp_ge_u32 s17, s8
s_cselect_b32 s16, s16, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s17, s16, s8
s_cmp_ge_u32 s16, s8
s_cselect_b32 s16, s17, s16
v_add_nc_u32_e32 v1, s16, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[16:17], 2, v[1:2]
v_add_co_u32 v16, vcc_lo, s4, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b32 v1, v[16:17], off
v_lshl_add_u32 v16, v5, 2, s15
s_waitcnt vmcnt(0)
ds_store_b32 v16, v1
s_and_saveexec_b32 s15, s12
s_cbranch_execnz .LBB1_6
s_branch .LBB1_7
.LBB1_86:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11life_kernelPiS_ii
.amdhsa_group_segment_fixed_size 720
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11life_kernelPiS_ii, .Lfunc_end1-_Z11life_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 720
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11life_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z11life_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define EMPTY 0
#define RED 1
#define BLUE 2
__global__ void init_kernel(int * domain, int domain_x)
{
// Dummy initialization
domain[blockIdx.y * domain_x + blockIdx.x * blockDim.x + threadIdx.x]
= ((blockIdx.x+threadIdx.x) == 0 ? 1 : 0);
//= (1664525ul * (blockIdx.x + threadIdx.y + threadIdx.x) + 1013904223ul) % 3;
}
// Reads a cell at (x+dx, y+dy)
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y)
{
x = (unsigned int)(x + dx) % domain_x; // Wrap around
y = (unsigned int)(y + dy) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void inc_color(int cell, int *nb_blue, int *nb_red) {
if (cell == BLUE) (*nb_blue)++;
else if (cell == RED) (*nb_red)++;
}
// Compute kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y)
{
int ty = blockIdx.y * blockDim.y + threadIdx.y;
int pos_y = threadIdx.y + 1;
__shared__ int shared_bloc[18][10];
for (int i = 0, pos_x = 1, tx = blockIdx.x * blockDim.x; i < 16; i++, tx++, pos_x++) {
// Read cell
shared_bloc[pos_x][pos_y] = read_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y);
if (pos_x == 1)
shared_bloc[pos_x-1][pos_y] = read_cell(source_domain, tx, ty, -1, 0, domain_x, domain_y);
else if (pos_x == 16)
shared_bloc[pos_x+1][pos_y] = read_cell(source_domain, tx, ty, 1, 0, domain_x, domain_y);
if (pos_y == 1)
shared_bloc[pos_x][pos_y-1] = read_cell(source_domain, tx, ty, 0, -1, domain_x, domain_y);
else if (pos_y == 8)
shared_bloc[pos_x][pos_y+1] = read_cell(source_domain, tx, ty, 0, 1, domain_x, domain_y);
if (pos_x == 1 && pos_y == 1)
shared_bloc[pos_x-1][pos_y-1] = read_cell(source_domain, tx, ty, -1, -1, domain_x, domain_y);
else if (pos_x == 1 && pos_y == 8)
shared_bloc[pos_x-1][pos_y+1] = read_cell(source_domain, tx, ty, -1, 1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 1)
shared_bloc[pos_x+1][pos_y-1] = read_cell(source_domain, tx, ty, 1, -1, domain_x, domain_y);
else if (pos_x == 16 && pos_y == 8)
shared_bloc[pos_x+1][pos_y+1] = read_cell(source_domain, tx, ty, 1, 1, domain_x, domain_y);
// Read the 8 neighbors and count number of blue and red
int nb_blue = 0, nb_red = 0;
__syncthreads();
inc_color(shared_bloc[pos_x][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y+1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x-1][pos_y-1], &nb_blue, &nb_red);
inc_color(shared_bloc[pos_x+1][pos_y+1], &nb_blue, &nb_red);
// Compute new value
int res = 0;
if (shared_bloc[pos_x][pos_y] != 0 && (nb_blue + nb_red == 2 || nb_blue + nb_red == 3))
res = shared_bloc[pos_x][pos_y];
else if (shared_bloc[pos_x][pos_y] == 0 && nb_blue + nb_red == 3) {
if (nb_blue > nb_red)
res = BLUE;
else
res = RED;
}
// Write it in dest_domain
dest_domain[ty * domain_x + tx] = res;
}
} | .text
.file "life_kernel.hip"
.globl _Z26__device_stub__init_kernelPii # -- Begin function _Z26__device_stub__init_kernelPii
.p2align 4, 0x90
.type _Z26__device_stub__init_kernelPii,@function
_Z26__device_stub__init_kernelPii: # @_Z26__device_stub__init_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11init_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__init_kernelPii, .Lfunc_end0-_Z26__device_stub__init_kernelPii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__life_kernelPiS_ii # -- Begin function _Z26__device_stub__life_kernelPiS_ii
.p2align 4, 0x90
.type _Z26__device_stub__life_kernelPiS_ii,@function
_Z26__device_stub__life_kernelPiS_ii: # @_Z26__device_stub__life_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11life_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub__life_kernelPiS_ii, .Lfunc_end1-_Z26__device_stub__life_kernelPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11life_kernelPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_kernelPii,@object # @_Z11init_kernelPii
.section .rodata,"a",@progbits
.globl _Z11init_kernelPii
.p2align 3, 0x0
_Z11init_kernelPii:
.quad _Z26__device_stub__init_kernelPii
.size _Z11init_kernelPii, 8
.type _Z11life_kernelPiS_ii,@object # @_Z11life_kernelPiS_ii
.globl _Z11life_kernelPiS_ii
.p2align 3, 0x0
_Z11life_kernelPiS_ii:
.quad _Z26__device_stub__life_kernelPiS_ii
.size _Z11life_kernelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11init_kernelPii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11life_kernelPiS_ii"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_kernelPii
.addrsig_sym _Z26__device_stub__life_kernelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_kernelPii
.addrsig_sym _Z11life_kernelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dd7b3_00000000-6_life_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9read_cellPiiiiijj
.type _Z9read_cellPiiiiijj, @function
_Z9read_cellPiiiiijj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9read_cellPiiiiijj, .-_Z9read_cellPiiiiijj
.globl _Z9inc_coloriPiS_
.type _Z9inc_coloriPiS_, @function
_Z9inc_coloriPiS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z9inc_coloriPiS_, .-_Z9inc_coloriPiS_
.globl _Z32__device_stub__Z11init_kernelPiiPii
.type _Z32__device_stub__Z11init_kernelPiiPii, @function
_Z32__device_stub__Z11init_kernelPiiPii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11init_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z11init_kernelPiiPii, .-_Z32__device_stub__Z11init_kernelPiiPii
.globl _Z11init_kernelPii
.type _Z11init_kernelPii, @function
_Z11init_kernelPii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11init_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11init_kernelPii, .-_Z11init_kernelPii
.globl _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.type _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, @function
_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11life_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, .-_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.globl _Z11life_kernelPiS_ii
.type _Z11life_kernelPiS_ii, @function
_Z11life_kernelPiS_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z11life_kernelPiS_ii, .-_Z11life_kernelPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11life_kernelPiS_ii"
.LC1:
.string "_Z11init_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11life_kernelPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_kernelPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "life_kernel.hip"
.globl _Z26__device_stub__init_kernelPii # -- Begin function _Z26__device_stub__init_kernelPii
.p2align 4, 0x90
.type _Z26__device_stub__init_kernelPii,@function
_Z26__device_stub__init_kernelPii: # @_Z26__device_stub__init_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11init_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__init_kernelPii, .Lfunc_end0-_Z26__device_stub__init_kernelPii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__life_kernelPiS_ii # -- Begin function _Z26__device_stub__life_kernelPiS_ii
.p2align 4, 0x90
.type _Z26__device_stub__life_kernelPiS_ii,@function
_Z26__device_stub__life_kernelPiS_ii: # @_Z26__device_stub__life_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11life_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub__life_kernelPiS_ii, .Lfunc_end1-_Z26__device_stub__life_kernelPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11life_kernelPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_kernelPii,@object # @_Z11init_kernelPii
.section .rodata,"a",@progbits
.globl _Z11init_kernelPii
.p2align 3, 0x0
_Z11init_kernelPii:
.quad _Z26__device_stub__init_kernelPii
.size _Z11init_kernelPii, 8
.type _Z11life_kernelPiS_ii,@object # @_Z11life_kernelPiS_ii
.globl _Z11life_kernelPiS_ii
.p2align 3, 0x0
_Z11life_kernelPiS_ii:
.quad _Z26__device_stub__life_kernelPiS_ii
.size _Z11life_kernelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11init_kernelPii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11life_kernelPiS_ii"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_kernelPii
.addrsig_sym _Z26__device_stub__life_kernelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_kernelPii
.addrsig_sym _Z11life_kernelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sumGrad(float* output, float* input1, float* input2, float* input3, float* input4, const int numElem)
{
size_t pos = blockDim.x * blockIdx.x + threadIdx.x;
size_t size = blockDim.x * gridDim.x;
for(int i = numElem * pos / size; i < numElem * (pos+1) / size; i++){
output[i] = input1[i] + input2[i] + input3[i] + input4[i];
}
} | code for sm_80
Function : _Z7sumGradPfS_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x290 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR5 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011405 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0080*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R5, R2.reuse, UR5, RZ ; /* 0x0000000502057c24 */
/* 0x040fe4000f8e02ff */
/*00b0*/ IMAD.WIDE.U32 R2, R2, c[0x0][0x188], RZ ; /* 0x0000620002027a25 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.IADD R10, R3, 0x1, R5 ; /* 0x00000001030a7824 */
/* 0x000fca00078e0205 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*00e0*/ @!P0 BRA 0x160 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*0100*/ MOV R6, 0x140 ; /* 0x0000014000067802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe4000f8e00ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0130*/ CALL.REL.NOINC 0x680 ; /* 0x0000054000007944 */
/* 0x000fea0003c00000 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0150*/ BRA 0x280 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0160*/ I2F.U32.RP R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008209000 */
/*0170*/ IMAD R7, RZ, RZ, -UR4 ; /* 0x80000004ff077e24 */
/* 0x000fe2000f8e02ff */
/*0180*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf45070 */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01d0*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*01f0*/ IMAD.HI.U32 R0, R5, R2, RZ ; /* 0x0000000205007227 */
/* 0x000fca00078e00ff */
/*0200*/ IADD3 R5, -R0, RZ, RZ ; /* 0x000000ff00057210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R5, R5, UR4, R2 ; /* 0x0000000405057c24 */
/* 0x000fca000f8e0202 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf06070 */
/*0230*/ @P0 IADD3 R5, R5, -UR4, RZ ; /* 0x8000000405050c10 */
/* 0x000fe4000fffe0ff */
/*0240*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.GE.U32.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf26070 */
/*0260*/ @P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100001810 */
/* 0x000fe40007ffe0ff */
/*0270*/ @!P2 LOP3.LUT R0, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff00ac12 */
/* 0x000fe4000f8e33ff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R9, P0, R2, c[0x0][0x188], RZ ; /* 0x0000620002097a10 */
/* 0x000fe20007f1e0ff */
/*02a0*/ BSSY B0, 0x480 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*02b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fe40000011400 */
/*02c0*/ IADD3.X R10, R10, UR5, RZ, P0, !PT ; /* 0x000000050a0a7c10 */
/* 0x000fc800087fe4ff */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*02e0*/ @!P0 BRA 0x340 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe2000f8e00ff */
/*0300*/ MOV R6, 0x330 ; /* 0x0000033000067802 */
/* 0x000fe20000000f00 */
/*0310*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0320*/ CALL.REL.NOINC 0x680 ; /* 0x0000035000007944 */
/* 0x000fea0003c00000 */
/*0330*/ BRA 0x470 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0340*/ I2F.U32.RP R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008209000 */
/*0350*/ IMAD R3, RZ, RZ, -UR4 ; /* 0x80000004ff037e24 */
/* 0x000fe2000f8e02ff */
/*0360*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45070 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fca00078e00ff */
/*0380*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0390*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fcc0007ffe0ff */
/*03a0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*03b0*/ IMAD R3, R3, R5, RZ ; /* 0x0000000503037224 */
/* 0x001fc800078e02ff */
/*03c0*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*03e0*/ IMAD.HI.U32 R4, R4, R9, RZ ; /* 0x0000000904047227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0400*/ IMAD R3, R6, UR4, R9 ; /* 0x0000000406037c24 */
/* 0x000fca000f8e0209 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06070 */
/*0420*/ @P0 IADD3 R3, R3, -UR4, RZ ; /* 0x8000000403030c10 */
/* 0x000fe4000fffe0ff */
/*0430*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0440*/ ISETP.GE.U32.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf26070 */
/*0450*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0460*/ @!P2 LOP3.LUT R4, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff04ac12 */
/* 0x000fe4000f8e33ff */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0490*/ ISETP.GT.U32.AND.EX P0, PT, R5, R2, PT, P0 ; /* 0x000000020500720c */
/* 0x000fda0003f04100 */
/*04a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04b0*/ MOV R14, R0 ; /* 0x00000000000e7202 */
/* 0x000fe20000000f00 */
/*04c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*04d0*/ IMAD.SHL.U32 R12, R0.reuse, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x040fe200078e00ff */
/*04e0*/ SHF.L.U64.HI R13, R0, 0x2, R2 ; /* 0x00000002000d7819 */
/* 0x000fc80000010202 */
/*04f0*/ IADD3 R2, P0, R12.reuse, c[0x0][0x170], RZ ; /* 0x00005c000c027a10 */
/* 0x040fe40007f1e0ff */
/*0500*/ IADD3 R6, P1, R12.reuse, c[0x0][0x168], RZ ; /* 0x00005a000c067a10 */
/* 0x040fe40007f3e0ff */
/*0510*/ IADD3.X R3, R13.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d037a10 */
/* 0x040fe400007fe4ff */
/*0520*/ IADD3 R8, P0, R12.reuse, c[0x0][0x178], RZ ; /* 0x00005e000c087a10 */
/* 0x040fe40007f1e0ff */
/*0530*/ IADD3.X R7, R13, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000d077a10 */
/* 0x000fe20000ffe4ff */
/*0540*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R10, P1, R12, c[0x0][0x180], RZ ; /* 0x000060000c0a7a10 */
/* 0x000fc40007f3e0ff */
/*0560*/ IADD3.X R9, R13.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000d097a10 */
/* 0x040fe400007fe4ff */
/*0570*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3.X R11, R13, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061000d0b7a10 */
/* 0x000fc60000ffe4ff */
/*0590*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f22000c1e1900 */
/*05b0*/ IADD3 R12, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*05c0*/ IADD3.X R13, R13, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000d0d7a10 */
/* 0x000fe200007fe4ff */
/*05d0*/ FADD R0, R2, R7 ; /* 0x0000000702007221 */
/* 0x004fc80000000000 */
/*05e0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*05f0*/ FADD R3, R0, R11 ; /* 0x0000000b00037221 */
/* 0x010fe20000000000 */
/*0600*/ IADD3 R0, R14, 0x1, RZ ; /* 0x000000010e007810 */
/* 0x000fc80007ffe0ff */
/*0610*/ STG.E [R12.64], R3 ; /* 0x000000030c007986 */
/* 0x0001e2000c101904 */
/*0620*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fe20003f04070 */
/*0630*/ IMAD.MOV.U32 R14, RZ, RZ, R0.reuse ; /* 0x000000ffff0e7224 */
/* 0x100fe200078e0000 */
/*0640*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0650*/ ISETP.GT.U32.AND.EX P0, PT, R5, R2, PT, P0 ; /* 0x000000020500720c */
/* 0x000fda0003f04100 */
/*0660*/ @P0 BRA 0x4d0 ; /* 0xfffffe6000000947 */
/* 0x001fea000383ffff */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0008 */
/*0690*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0007 */
/*06a0*/ I2F.U64.RP R11, R14 ; /* 0x0000000e000b7312 */
/* 0x000e300000309000 */
/*06b0*/ MUFU.RCP R11, R11 ; /* 0x0000000b000b7308 */
/* 0x001e240000001000 */
/*06c0*/ IADD3 R4, R11, 0x1ffffffe, RZ ; /* 0x1ffffffe0b047810 */
/* 0x001fcc0007ffe0ff */
/*06d0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*06e0*/ IMAD.WIDE.U32 R12, R4, R8, RZ ; /* 0x00000008040c7225 */
/* 0x001fc800078e00ff */
/*06f0*/ IMAD R13, R4, R7, R13 ; /* 0x00000007040d7224 */
/* 0x000fe200078e020d */
/*0700*/ IADD3 R17, P0, RZ, -R12, RZ ; /* 0x8000000cff117210 */
/* 0x000fc60007f1e0ff */
/*0710*/ IMAD R13, R5, R8, R13 ; /* 0x00000008050d7224 */
/* 0x000fe400078e020d */
/*0720*/ IMAD.HI.U32 R12, R4, R17, RZ ; /* 0x00000011040c7227 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.X R19, RZ, RZ, ~R13, P0 ; /* 0x000000ffff137224 */
/* 0x000fe400000e0e0d */
/*0740*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0004 */
/*0750*/ IMAD R15, R5, R19.reuse, RZ ; /* 0x00000013050f7224 */
/* 0x080fe400078e02ff */
/*0760*/ IMAD.WIDE.U32 R12, P0, R4, R19, R12 ; /* 0x00000013040c7225 */
/* 0x000fc8000780000c */
/*0770*/ IMAD.HI.U32 R11, R5, R19, RZ ; /* 0x00000013050b7227 */
/* 0x000fc800078e00ff */
/*0780*/ IMAD.HI.U32 R12, P1, R5, R17, R12 ; /* 0x00000011050c7227 */
/* 0x000fe2000782000c */
/*0790*/ IADD3.X R11, R11, R5, RZ, P0, !PT ; /* 0x000000050b0b7210 */
/* 0x000fc800007fe4ff */
/*07a0*/ IADD3 R13, P2, R15, R12, RZ ; /* 0x0000000c0f0d7210 */
/* 0x000fc80007f5e0ff */
/*07b0*/ IADD3.X R11, RZ, RZ, R11, P2, P1 ; /* 0x000000ffff0b7210 */
/* 0x000fe200017e240b */
/*07c0*/ IMAD.WIDE.U32 R4, R13, R8, RZ ; /* 0x000000080d047225 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD R5, R13, R7, R5 ; /* 0x000000070d057224 */
/* 0x000fe200078e0205 */
/*07e0*/ IADD3 R15, P0, RZ, -R4, RZ ; /* 0x80000004ff0f7210 */
/* 0x000fc60007f1e0ff */
/*07f0*/ IMAD R5, R11, R8, R5 ; /* 0x000000080b057224 */
/* 0x000fe400078e0205 */
/*0800*/ IMAD.HI.U32 R12, R13, R15, RZ ; /* 0x0000000f0d0c7227 */
/* 0x000fc800078e00ff */
/*0810*/ IMAD.X R4, RZ, RZ, ~R5, P0 ; /* 0x000000ffff047224 */
/* 0x000fe400000e0e05 */
/*0820*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0830*/ IMAD.WIDE.U32 R12, P0, R13, R4, R12 ; /* 0x000000040d0c7225 */
/* 0x000fc8000780000c */
/*0840*/ IMAD R14, R11.reuse, R4, RZ ; /* 0x000000040b0e7224 */
/* 0x040fe400078e02ff */
/*0850*/ IMAD.HI.U32 R13, P1, R11, R15, R12 ; /* 0x0000000f0b0d7227 */
/* 0x000fc8000782000c */
/*0860*/ IMAD.HI.U32 R4, R11, R4, RZ ; /* 0x000000040b047227 */
/* 0x000fe200078e00ff */
/*0870*/ IADD3 R13, P2, R14, R13, RZ ; /* 0x0000000d0e0d7210 */
/* 0x000fc60007f5e0ff */
/*0880*/ IMAD.X R11, R4, 0x1, R11, P0 ; /* 0x00000001040b7824 */
/* 0x000fe400000e060b */
/*0890*/ IMAD.HI.U32 R4, R13, R9, RZ ; /* 0x000000090d047227 */
/* 0x000fc600078e00ff */
/*08a0*/ IADD3.X R11, RZ, RZ, R11, P2, P1 ; /* 0x000000ffff0b7210 */
/* 0x000fc600017e240b */
/*08b0*/ IMAD.WIDE.U32 R4, R13, R10, R4 ; /* 0x0000000a0d047225 */
/* 0x000fc800078e0004 */
/*08c0*/ IMAD R13, R11.reuse, R10, RZ ; /* 0x0000000a0b0d7224 */
/* 0x040fe400078e02ff */
/*08d0*/ IMAD.HI.U32 R4, P0, R11, R9, R4 ; /* 0x000000090b047227 */
/* 0x000fc80007800004 */
/*08e0*/ IMAD.HI.U32 R11, R11, R10, RZ ; /* 0x0000000a0b0b7227 */
/* 0x000fe200078e00ff */
/*08f0*/ IADD3 R13, P1, R13, R4, RZ ; /* 0x000000040d0d7210 */
/* 0x000fc60007f3e0ff */
/*0900*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e060b */
/*0910*/ IMAD.WIDE.U32 R4, R13, R8, RZ ; /* 0x000000080d047225 */
/* 0x000fc800078e00ff */
/*0920*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*0930*/ IADD3 R9, P1, -R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x000fe20007f3e1ff */
/*0940*/ IMAD R5, R13, R7, R5 ; /* 0x000000070d057224 */
/* 0x000fc600078e0205 */
/*0950*/ ISETP.GE.U32.AND P0, PT, R9, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x080fe20003f06070 */
/*0960*/ IMAD R5, R11, R8, R5 ; /* 0x000000080b057224 */
/* 0x000fca00078e0205 */
/*0970*/ IADD3.X R16, ~R5, R10, RZ, P1, !PT ; /* 0x0000000a05107210 */
/* 0x000fe40000ffe5ff */
/*0980*/ IADD3 R4, P1, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe40007f3e0ff */
/*0990*/ IADD3 R5, P2, -R8, R9, RZ ; /* 0x0000000908057210 */
/* 0x000fe40007f5e1ff */
/*09a0*/ ISETP.GE.U32.AND.EX P0, PT, R16, R7, PT, P0 ; /* 0x000000071000720c */
/* 0x000fe20003f06100 */
/*09b0*/ IMAD.X R12, RZ, RZ, R11, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe200008e060b */
/*09c0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25070 */
/*09d0*/ IMAD.X R14, R16, 0x1, ~R7, P2 ; /* 0x00000001100e7824 */
/* 0x000fe200010e0e07 */
/*09e0*/ SEL R13, R4, R13, P0 ; /* 0x0000000d040d7207 */
/* 0x000fc40000000000 */
/*09f0*/ SEL R5, R5, R9, P0 ; /* 0x0000000905057207 */
/* 0x000fe40000000000 */
/*0a00*/ SEL R12, R12, R11, P0 ; /* 0x0000000b0c0c7207 */
/* 0x000fe40000000000 */
/*0a10*/ IADD3 R4, P2, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe40007f5e0ff */
/*0a20*/ SEL R14, R14, R16, P0 ; /* 0x000000100e0e7207 */
/* 0x000fe40000000000 */
/*0a30*/ ISETP.GE.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fe20003f06070 */
/*0a40*/ IMAD.X R5, RZ, RZ, R12, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e060c */
/*0a50*/ ISETP.NE.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fc40003f25310 */
/*0a60*/ ISETP.GE.U32.AND.EX P0, PT, R14, R7, PT, P0 ; /* 0x000000070e00720c */
/* 0x000fe20003f06100 */
/*0a70*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc600078e00ff */
/*0a80*/ SEL R4, R4, R13, P0 ; /* 0x0000000d04047207 */
/* 0x000fe40000000000 */
/*0a90*/ SEL R5, R5, R12, P0 ; /* 0x0000000c05057207 */
/* 0x000fe40000000000 */
/*0aa0*/ SEL R4, R4, 0xffffffff, P1 ; /* 0xffffffff04047807 */
/* 0x000fe40000800000 */
/*0ab0*/ SEL R5, R5, 0xffffffff, P1 ; /* 0xffffffff05057807 */
/* 0x000fe20000800000 */
/*0ac0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff53006007950 */
/* 0x000fec0003c3ffff */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sumGrad(float* output, float* input1, float* input2, float* input3, float* input4, const int numElem)
{
size_t pos = blockDim.x * blockIdx.x + threadIdx.x;
size_t size = blockDim.x * gridDim.x;
for(int i = numElem * pos / size; i < numElem * (pos+1) / size; i++){
output[i] = input1[i] + input2[i] + input3[i] + input4[i];
}
} | .file "tmpxft_0019df76_00000000-6_sumGrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i
.type _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i, @function
_Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7sumGradPfS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i, .-_Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i
.globl _Z7sumGradPfS_S_S_S_i
.type _Z7sumGradPfS_S_S_S_i, @function
_Z7sumGradPfS_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sumGradPfS_S_S_S_i, .-_Z7sumGradPfS_S_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sumGradPfS_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sumGradPfS_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sumGrad(float* output, float* input1, float* input2, float* input3, float* input4, const int numElem)
{
size_t pos = blockDim.x * blockIdx.x + threadIdx.x;
size_t size = blockDim.x * gridDim.x;
for(int i = numElem * pos / size; i < numElem * (pos+1) / size; i++){
output[i] = input1[i] + input2[i] + input3[i] + input4[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumGrad(float* output, float* input1, float* input2, float* input3, float* input4, const int numElem)
{
size_t pos = blockDim.x * blockIdx.x + threadIdx.x;
size_t size = blockDim.x * gridDim.x;
for(int i = numElem * pos / size; i < numElem * (pos+1) / size; i++){
output[i] = input1[i] + input2[i] + input3[i] + input4[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumGrad(float* output, float* input1, float* input2, float* input3, float* input4, const int numElem)
{
size_t pos = blockDim.x * blockIdx.x + threadIdx.x;
size_t size = blockDim.x * gridDim.x;
for(int i = numElem * pos / size; i < numElem * (pos+1) / size; i++){
output[i] = input1[i] + input2[i] + input3[i] + input4[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sumGradPfS_S_S_S_i
.globl _Z7sumGradPfS_S_S_S_i
.p2align 8
.type _Z7sumGradPfS_S_S_S_i,@function
_Z7sumGradPfS_S_S_S_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_mul_i32 s4, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, 0
v_mov_b32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v2, s3, v[0:1]
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
s_and_saveexec_b32 s5, vcc_lo
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v0, s4
s_sub_u32 s6, 0, s4
s_subb_u32 s7, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, 0, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x2f800000, v0
v_trunc_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v1, 0xcf800000, v0
v_cvt_u32_f32_e32 v1, v1
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s6, v1
v_mul_hi_u32 v6, s6, v0
v_mul_lo_u32 v7, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v6, v5
v_mul_lo_u32 v6, s6, v0
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v0, v6
v_mul_lo_u32 v8, v0, v5
v_mul_hi_u32 v9, v0, v5
v_mul_hi_u32 v10, v1, v6
v_mul_lo_u32 v6, v1, v6
v_mul_hi_u32 v11, v1, v5
v_mul_lo_u32 v5, v1, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, s6, v0
v_mul_lo_u32 v7, s7, v0
v_mul_lo_u32 v6, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v6
v_mul_lo_u32 v6, s6, v0
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v0, v6
v_mul_lo_u32 v8, v0, v5
v_mul_hi_u32 v9, v0, v5
v_mul_hi_u32 v10, v1, v6
v_mul_lo_u32 v6, v1, v6
v_mul_hi_u32 v11, v1, v5
v_mul_lo_u32 v5, v1, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v9, vcc_lo, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, v3, v7
v_mad_u64_u32 v[5:6], null, v4, v7, 0
v_mad_u64_u32 v[0:1], null, v3, v9, 0
v_mad_u64_u32 v[7:8], null, v4, v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v0, vcc_lo, v1, v6, vcc_lo
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s4, v7, 0
v_mad_u64_u32 v[5:6], null, s4, v8, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v3, v0
v_sub_co_ci_u32_e32 v1, vcc_lo, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v3, vcc_lo, v0, s4
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_add_co_u32 v5, vcc_lo, v7, 2
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v3, -1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v7, 1
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v0, -1, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e32 v1, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e32 v0, v7, v1, vcc_lo
.LBB0_2:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s6, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s6, v0
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s4
v_sub_nc_u32_e32 v1, v3, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_mad_u64_u32 v[3:4], null, s2, v2, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v4
v_mad_u64_u32 v[4:5], null, s3, v2, v[1:2]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v4
v_cmp_ne_u64_e32 vcc_lo, 0, v[1:2]
v_mov_b32_e32 v1, v4
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v2, s4
s_sub_u32 s2, 0, s4
s_subb_u32 s5, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, 0, 0x4f800000, v2
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x2f800000, v2
v_trunc_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v2, v4, 0xcf800000, v2
v_cvt_u32_f32_e32 v4, v4
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s2, v4
v_mul_hi_u32 v6, s2, v2
v_mul_lo_u32 v7, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v6, v5
v_mul_lo_u32 v6, s2, v2
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v2, v6
v_mul_lo_u32 v8, v2, v5
v_mul_hi_u32 v9, v2, v5
v_mul_hi_u32 v10, v4, v6
v_mul_lo_u32 v6, v4, v6
v_mul_hi_u32 v11, v4, v5
v_mul_lo_u32 v5, v4, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, s2, v2
v_mul_lo_u32 v7, s5, v2
v_mul_lo_u32 v6, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v6
v_mul_lo_u32 v6, s2, v2
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v2, v6
v_mul_lo_u32 v8, v2, v5
v_mul_hi_u32 v9, v2, v5
v_mul_hi_u32 v10, v4, v6
v_mul_lo_u32 v6, v4, v6
v_mul_hi_u32 v11, v4, v5
v_mul_lo_u32 v5, v4, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v5
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v11, v3, v2
v_mad_u64_u32 v[6:7], null, v1, v2, 0
v_mad_u64_u32 v[4:5], null, v3, v10, 0
v_mad_u64_u32 v[8:9], null, v1, v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v11, v4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v7, vcc_lo
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v2, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s4, v7, 0
v_mov_b32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s4, v8, v[2:3]
v_sub_co_u32 v2, vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
v_sub_co_u32 v3, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cmp_eq_u32_e64 s2, 0, v1
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_add_co_u32 v5, vcc_lo, v7, 2
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v8, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, -1, v2, s2
v_cndmask_b32_e32 v3, -1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v7, 1
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v8, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v2, v9, v6 :: v_dual_cndmask_b32 v3, v4, v5
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_dual_cndmask_b32 v6, v8, v2 :: v_dual_cndmask_b32 v5, v7, v3
.LBB0_6:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s3, 0, s4
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s4
v_sub_nc_u32_e32 v2, v3, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v5, v1, v3, vcc_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 v[5:6], v[0:1]
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x20
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_10:
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v11, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v3, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v4, v[9:10], off
v_add_co_u32 v7, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v3, vcc_lo
global_load_b32 v9, v[11:12], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(2)
v_add_f32_e32 v4, v1, v4
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v9
v_cmp_le_u64_e64 s0, v[5:6], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v7
s_or_b32 s1, s0, s1
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sumGradPfS_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sumGradPfS_S_S_S_i, .Lfunc_end0-_Z7sumGradPfS_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sumGradPfS_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sumGradPfS_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumGrad(float* output, float* input1, float* input2, float* input3, float* input4, const int numElem)
{
size_t pos = blockDim.x * blockIdx.x + threadIdx.x;
size_t size = blockDim.x * gridDim.x;
for(int i = numElem * pos / size; i < numElem * (pos+1) / size; i++){
output[i] = input1[i] + input2[i] + input3[i] + input4[i];
}
} | .text
.file "sumGrad.hip"
.globl _Z22__device_stub__sumGradPfS_S_S_S_i # -- Begin function _Z22__device_stub__sumGradPfS_S_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__sumGradPfS_S_S_S_i,@function
_Z22__device_stub__sumGradPfS_S_S_S_i: # @_Z22__device_stub__sumGradPfS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7sumGradPfS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__sumGradPfS_S_S_S_i, .Lfunc_end0-_Z22__device_stub__sumGradPfS_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sumGradPfS_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sumGradPfS_S_S_S_i,@object # @_Z7sumGradPfS_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z7sumGradPfS_S_S_S_i
.p2align 3, 0x0
_Z7sumGradPfS_S_S_S_i:
.quad _Z22__device_stub__sumGradPfS_S_S_S_i
.size _Z7sumGradPfS_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sumGradPfS_S_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sumGradPfS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sumGradPfS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sumGradPfS_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x290 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR5 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011405 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0080*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R5, R2.reuse, UR5, RZ ; /* 0x0000000502057c24 */
/* 0x040fe4000f8e02ff */
/*00b0*/ IMAD.WIDE.U32 R2, R2, c[0x0][0x188], RZ ; /* 0x0000620002027a25 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.IADD R10, R3, 0x1, R5 ; /* 0x00000001030a7824 */
/* 0x000fca00078e0205 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*00e0*/ @!P0 BRA 0x160 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*0100*/ MOV R6, 0x140 ; /* 0x0000014000067802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe4000f8e00ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0130*/ CALL.REL.NOINC 0x680 ; /* 0x0000054000007944 */
/* 0x000fea0003c00000 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0150*/ BRA 0x280 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0160*/ I2F.U32.RP R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008209000 */
/*0170*/ IMAD R7, RZ, RZ, -UR4 ; /* 0x80000004ff077e24 */
/* 0x000fe2000f8e02ff */
/*0180*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf45070 */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01d0*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*01f0*/ IMAD.HI.U32 R0, R5, R2, RZ ; /* 0x0000000205007227 */
/* 0x000fca00078e00ff */
/*0200*/ IADD3 R5, -R0, RZ, RZ ; /* 0x000000ff00057210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R5, R5, UR4, R2 ; /* 0x0000000405057c24 */
/* 0x000fca000f8e0202 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf06070 */
/*0230*/ @P0 IADD3 R5, R5, -UR4, RZ ; /* 0x8000000405050c10 */
/* 0x000fe4000fffe0ff */
/*0240*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.GE.U32.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf26070 */
/*0260*/ @P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100001810 */
/* 0x000fe40007ffe0ff */
/*0270*/ @!P2 LOP3.LUT R0, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff00ac12 */
/* 0x000fe4000f8e33ff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R9, P0, R2, c[0x0][0x188], RZ ; /* 0x0000620002097a10 */
/* 0x000fe20007f1e0ff */
/*02a0*/ BSSY B0, 0x480 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*02b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fe40000011400 */
/*02c0*/ IADD3.X R10, R10, UR5, RZ, P0, !PT ; /* 0x000000050a0a7c10 */
/* 0x000fc800087fe4ff */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*02e0*/ @!P0 BRA 0x340 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe2000f8e00ff */
/*0300*/ MOV R6, 0x330 ; /* 0x0000033000067802 */
/* 0x000fe20000000f00 */
/*0310*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0320*/ CALL.REL.NOINC 0x680 ; /* 0x0000035000007944 */
/* 0x000fea0003c00000 */
/*0330*/ BRA 0x470 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0340*/ I2F.U32.RP R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008209000 */
/*0350*/ IMAD R3, RZ, RZ, -UR4 ; /* 0x80000004ff037e24 */
/* 0x000fe2000f8e02ff */
/*0360*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45070 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fca00078e00ff */
/*0380*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0390*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fcc0007ffe0ff */
/*03a0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*03b0*/ IMAD R3, R3, R5, RZ ; /* 0x0000000503037224 */
/* 0x001fc800078e02ff */
/*03c0*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*03e0*/ IMAD.HI.U32 R4, R4, R9, RZ ; /* 0x0000000904047227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0400*/ IMAD R3, R6, UR4, R9 ; /* 0x0000000406037c24 */
/* 0x000fca000f8e0209 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06070 */
/*0420*/ @P0 IADD3 R3, R3, -UR4, RZ ; /* 0x8000000403030c10 */
/* 0x000fe4000fffe0ff */
/*0430*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0440*/ ISETP.GE.U32.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf26070 */
/*0450*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0460*/ @!P2 LOP3.LUT R4, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff04ac12 */
/* 0x000fe4000f8e33ff */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0490*/ ISETP.GT.U32.AND.EX P0, PT, R5, R2, PT, P0 ; /* 0x000000020500720c */
/* 0x000fda0003f04100 */
/*04a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04b0*/ MOV R14, R0 ; /* 0x00000000000e7202 */
/* 0x000fe20000000f00 */
/*04c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*04d0*/ IMAD.SHL.U32 R12, R0.reuse, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x040fe200078e00ff */
/*04e0*/ SHF.L.U64.HI R13, R0, 0x2, R2 ; /* 0x00000002000d7819 */
/* 0x000fc80000010202 */
/*04f0*/ IADD3 R2, P0, R12.reuse, c[0x0][0x170], RZ ; /* 0x00005c000c027a10 */
/* 0x040fe40007f1e0ff */
/*0500*/ IADD3 R6, P1, R12.reuse, c[0x0][0x168], RZ ; /* 0x00005a000c067a10 */
/* 0x040fe40007f3e0ff */
/*0510*/ IADD3.X R3, R13.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d037a10 */
/* 0x040fe400007fe4ff */
/*0520*/ IADD3 R8, P0, R12.reuse, c[0x0][0x178], RZ ; /* 0x00005e000c087a10 */
/* 0x040fe40007f1e0ff */
/*0530*/ IADD3.X R7, R13, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000d077a10 */
/* 0x000fe20000ffe4ff */
/*0540*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R10, P1, R12, c[0x0][0x180], RZ ; /* 0x000060000c0a7a10 */
/* 0x000fc40007f3e0ff */
/*0560*/ IADD3.X R9, R13.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000d097a10 */
/* 0x040fe400007fe4ff */
/*0570*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3.X R11, R13, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061000d0b7a10 */
/* 0x000fc60000ffe4ff */
/*0590*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f22000c1e1900 */
/*05b0*/ IADD3 R12, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*05c0*/ IADD3.X R13, R13, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000d0d7a10 */
/* 0x000fe200007fe4ff */
/*05d0*/ FADD R0, R2, R7 ; /* 0x0000000702007221 */
/* 0x004fc80000000000 */
/*05e0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*05f0*/ FADD R3, R0, R11 ; /* 0x0000000b00037221 */
/* 0x010fe20000000000 */
/*0600*/ IADD3 R0, R14, 0x1, RZ ; /* 0x000000010e007810 */
/* 0x000fc80007ffe0ff */
/*0610*/ STG.E [R12.64], R3 ; /* 0x000000030c007986 */
/* 0x0001e2000c101904 */
/*0620*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fe20003f04070 */
/*0630*/ IMAD.MOV.U32 R14, RZ, RZ, R0.reuse ; /* 0x000000ffff0e7224 */
/* 0x100fe200078e0000 */
/*0640*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0650*/ ISETP.GT.U32.AND.EX P0, PT, R5, R2, PT, P0 ; /* 0x000000020500720c */
/* 0x000fda0003f04100 */
/*0660*/ @P0 BRA 0x4d0 ; /* 0xfffffe6000000947 */
/* 0x001fea000383ffff */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0008 */
/*0690*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0007 */
/*06a0*/ I2F.U64.RP R11, R14 ; /* 0x0000000e000b7312 */
/* 0x000e300000309000 */
/*06b0*/ MUFU.RCP R11, R11 ; /* 0x0000000b000b7308 */
/* 0x001e240000001000 */
/*06c0*/ IADD3 R4, R11, 0x1ffffffe, RZ ; /* 0x1ffffffe0b047810 */
/* 0x001fcc0007ffe0ff */
/*06d0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*06e0*/ IMAD.WIDE.U32 R12, R4, R8, RZ ; /* 0x00000008040c7225 */
/* 0x001fc800078e00ff */
/*06f0*/ IMAD R13, R4, R7, R13 ; /* 0x00000007040d7224 */
/* 0x000fe200078e020d */
/*0700*/ IADD3 R17, P0, RZ, -R12, RZ ; /* 0x8000000cff117210 */
/* 0x000fc60007f1e0ff */
/*0710*/ IMAD R13, R5, R8, R13 ; /* 0x00000008050d7224 */
/* 0x000fe400078e020d */
/*0720*/ IMAD.HI.U32 R12, R4, R17, RZ ; /* 0x00000011040c7227 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.X R19, RZ, RZ, ~R13, P0 ; /* 0x000000ffff137224 */
/* 0x000fe400000e0e0d */
/*0740*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0004 */
/*0750*/ IMAD R15, R5, R19.reuse, RZ ; /* 0x00000013050f7224 */
/* 0x080fe400078e02ff */
/*0760*/ IMAD.WIDE.U32 R12, P0, R4, R19, R12 ; /* 0x00000013040c7225 */
/* 0x000fc8000780000c */
/*0770*/ IMAD.HI.U32 R11, R5, R19, RZ ; /* 0x00000013050b7227 */
/* 0x000fc800078e00ff */
/*0780*/ IMAD.HI.U32 R12, P1, R5, R17, R12 ; /* 0x00000011050c7227 */
/* 0x000fe2000782000c */
/*0790*/ IADD3.X R11, R11, R5, RZ, P0, !PT ; /* 0x000000050b0b7210 */
/* 0x000fc800007fe4ff */
/*07a0*/ IADD3 R13, P2, R15, R12, RZ ; /* 0x0000000c0f0d7210 */
/* 0x000fc80007f5e0ff */
/*07b0*/ IADD3.X R11, RZ, RZ, R11, P2, P1 ; /* 0x000000ffff0b7210 */
/* 0x000fe200017e240b */
/*07c0*/ IMAD.WIDE.U32 R4, R13, R8, RZ ; /* 0x000000080d047225 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD R5, R13, R7, R5 ; /* 0x000000070d057224 */
/* 0x000fe200078e0205 */
/*07e0*/ IADD3 R15, P0, RZ, -R4, RZ ; /* 0x80000004ff0f7210 */
/* 0x000fc60007f1e0ff */
/*07f0*/ IMAD R5, R11, R8, R5 ; /* 0x000000080b057224 */
/* 0x000fe400078e0205 */
/*0800*/ IMAD.HI.U32 R12, R13, R15, RZ ; /* 0x0000000f0d0c7227 */
/* 0x000fc800078e00ff */
/*0810*/ IMAD.X R4, RZ, RZ, ~R5, P0 ; /* 0x000000ffff047224 */
/* 0x000fe400000e0e05 */
/*0820*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0830*/ IMAD.WIDE.U32 R12, P0, R13, R4, R12 ; /* 0x000000040d0c7225 */
/* 0x000fc8000780000c */
/*0840*/ IMAD R14, R11.reuse, R4, RZ ; /* 0x000000040b0e7224 */
/* 0x040fe400078e02ff */
/*0850*/ IMAD.HI.U32 R13, P1, R11, R15, R12 ; /* 0x0000000f0b0d7227 */
/* 0x000fc8000782000c */
/*0860*/ IMAD.HI.U32 R4, R11, R4, RZ ; /* 0x000000040b047227 */
/* 0x000fe200078e00ff */
/*0870*/ IADD3 R13, P2, R14, R13, RZ ; /* 0x0000000d0e0d7210 */
/* 0x000fc60007f5e0ff */
/*0880*/ IMAD.X R11, R4, 0x1, R11, P0 ; /* 0x00000001040b7824 */
/* 0x000fe400000e060b */
/*0890*/ IMAD.HI.U32 R4, R13, R9, RZ ; /* 0x000000090d047227 */
/* 0x000fc600078e00ff */
/*08a0*/ IADD3.X R11, RZ, RZ, R11, P2, P1 ; /* 0x000000ffff0b7210 */
/* 0x000fc600017e240b */
/*08b0*/ IMAD.WIDE.U32 R4, R13, R10, R4 ; /* 0x0000000a0d047225 */
/* 0x000fc800078e0004 */
/*08c0*/ IMAD R13, R11.reuse, R10, RZ ; /* 0x0000000a0b0d7224 */
/* 0x040fe400078e02ff */
/*08d0*/ IMAD.HI.U32 R4, P0, R11, R9, R4 ; /* 0x000000090b047227 */
/* 0x000fc80007800004 */
/*08e0*/ IMAD.HI.U32 R11, R11, R10, RZ ; /* 0x0000000a0b0b7227 */
/* 0x000fe200078e00ff */
/*08f0*/ IADD3 R13, P1, R13, R4, RZ ; /* 0x000000040d0d7210 */
/* 0x000fc60007f3e0ff */
/*0900*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e060b */
/*0910*/ IMAD.WIDE.U32 R4, R13, R8, RZ ; /* 0x000000080d047225 */
/* 0x000fc800078e00ff */
/*0920*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*0930*/ IADD3 R9, P1, -R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x000fe20007f3e1ff */
/*0940*/ IMAD R5, R13, R7, R5 ; /* 0x000000070d057224 */
/* 0x000fc600078e0205 */
/*0950*/ ISETP.GE.U32.AND P0, PT, R9, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x080fe20003f06070 */
/*0960*/ IMAD R5, R11, R8, R5 ; /* 0x000000080b057224 */
/* 0x000fca00078e0205 */
/*0970*/ IADD3.X R16, ~R5, R10, RZ, P1, !PT ; /* 0x0000000a05107210 */
/* 0x000fe40000ffe5ff */
/*0980*/ IADD3 R4, P1, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe40007f3e0ff */
/*0990*/ IADD3 R5, P2, -R8, R9, RZ ; /* 0x0000000908057210 */
/* 0x000fe40007f5e1ff */
/*09a0*/ ISETP.GE.U32.AND.EX P0, PT, R16, R7, PT, P0 ; /* 0x000000071000720c */
/* 0x000fe20003f06100 */
/*09b0*/ IMAD.X R12, RZ, RZ, R11, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe200008e060b */
/*09c0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25070 */
/*09d0*/ IMAD.X R14, R16, 0x1, ~R7, P2 ; /* 0x00000001100e7824 */
/* 0x000fe200010e0e07 */
/*09e0*/ SEL R13, R4, R13, P0 ; /* 0x0000000d040d7207 */
/* 0x000fc40000000000 */
/*09f0*/ SEL R5, R5, R9, P0 ; /* 0x0000000905057207 */
/* 0x000fe40000000000 */
/*0a00*/ SEL R12, R12, R11, P0 ; /* 0x0000000b0c0c7207 */
/* 0x000fe40000000000 */
/*0a10*/ IADD3 R4, P2, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe40007f5e0ff */
/*0a20*/ SEL R14, R14, R16, P0 ; /* 0x000000100e0e7207 */
/* 0x000fe40000000000 */
/*0a30*/ ISETP.GE.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fe20003f06070 */
/*0a40*/ IMAD.X R5, RZ, RZ, R12, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e060c */
/*0a50*/ ISETP.NE.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fc40003f25310 */
/*0a60*/ ISETP.GE.U32.AND.EX P0, PT, R14, R7, PT, P0 ; /* 0x000000070e00720c */
/* 0x000fe20003f06100 */
/*0a70*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc600078e00ff */
/*0a80*/ SEL R4, R4, R13, P0 ; /* 0x0000000d04047207 */
/* 0x000fe40000000000 */
/*0a90*/ SEL R5, R5, R12, P0 ; /* 0x0000000c05057207 */
/* 0x000fe40000000000 */
/*0aa0*/ SEL R4, R4, 0xffffffff, P1 ; /* 0xffffffff04047807 */
/* 0x000fe40000800000 */
/*0ab0*/ SEL R5, R5, 0xffffffff, P1 ; /* 0xffffffff05057807 */
/* 0x000fe20000800000 */
/*0ac0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff53006007950 */
/* 0x000fec0003c3ffff */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sumGradPfS_S_S_S_i
.globl _Z7sumGradPfS_S_S_S_i
.p2align 8
.type _Z7sumGradPfS_S_S_S_i,@function
_Z7sumGradPfS_S_S_S_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_ashr_i32 s3, s2, 31
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_mul_i32 s4, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, 0
v_mov_b32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v2, s3, v[0:1]
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
s_and_saveexec_b32 s5, vcc_lo
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v0, s4
s_sub_u32 s6, 0, s4
s_subb_u32 s7, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, 0, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x2f800000, v0
v_trunc_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v1, 0xcf800000, v0
v_cvt_u32_f32_e32 v1, v1
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s6, v1
v_mul_hi_u32 v6, s6, v0
v_mul_lo_u32 v7, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v6, v5
v_mul_lo_u32 v6, s6, v0
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v0, v6
v_mul_lo_u32 v8, v0, v5
v_mul_hi_u32 v9, v0, v5
v_mul_hi_u32 v10, v1, v6
v_mul_lo_u32 v6, v1, v6
v_mul_hi_u32 v11, v1, v5
v_mul_lo_u32 v5, v1, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, s6, v0
v_mul_lo_u32 v7, s7, v0
v_mul_lo_u32 v6, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v6
v_mul_lo_u32 v6, s6, v0
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v0, v6
v_mul_lo_u32 v8, v0, v5
v_mul_hi_u32 v9, v0, v5
v_mul_hi_u32 v10, v1, v6
v_mul_lo_u32 v6, v1, v6
v_mul_hi_u32 v11, v1, v5
v_mul_lo_u32 v5, v1, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v9, vcc_lo, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, v3, v7
v_mad_u64_u32 v[5:6], null, v4, v7, 0
v_mad_u64_u32 v[0:1], null, v3, v9, 0
v_mad_u64_u32 v[7:8], null, v4, v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v0, vcc_lo, v1, v6, vcc_lo
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s4, v7, 0
v_mad_u64_u32 v[5:6], null, s4, v8, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v3, v0
v_sub_co_ci_u32_e32 v1, vcc_lo, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v3, vcc_lo, v0, s4
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_add_co_u32 v5, vcc_lo, v7, 2
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v3, -1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v7, 1
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v0, -1, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e32 v1, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e32 v0, v7, v1, vcc_lo
.LBB0_2:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s6, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s6, v0
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s4
v_sub_nc_u32_e32 v1, v3, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_mad_u64_u32 v[3:4], null, s2, v2, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v4
v_mad_u64_u32 v[4:5], null, s3, v2, v[1:2]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v4
v_cmp_ne_u64_e32 vcc_lo, 0, v[1:2]
v_mov_b32_e32 v1, v4
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v2, s4
s_sub_u32 s2, 0, s4
s_subb_u32 s5, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, 0, 0x4f800000, v2
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x5f7ffffc, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x2f800000, v2
v_trunc_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v2, v4, 0xcf800000, v2
v_cvt_u32_f32_e32 v4, v4
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s2, v4
v_mul_hi_u32 v6, s2, v2
v_mul_lo_u32 v7, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v6, v5
v_mul_lo_u32 v6, s2, v2
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v2, v6
v_mul_lo_u32 v8, v2, v5
v_mul_hi_u32 v9, v2, v5
v_mul_hi_u32 v10, v4, v6
v_mul_lo_u32 v6, v4, v6
v_mul_hi_u32 v11, v4, v5
v_mul_lo_u32 v5, v4, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, s2, v2
v_mul_lo_u32 v7, s5, v2
v_mul_lo_u32 v6, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v5, v6
v_mul_lo_u32 v6, s2, v2
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v7, v2, v6
v_mul_lo_u32 v8, v2, v5
v_mul_hi_u32 v9, v2, v5
v_mul_hi_u32 v10, v4, v6
v_mul_lo_u32 v6, v4, v6
v_mul_hi_u32 v11, v4, v5
v_mul_lo_u32 v5, v4, v5
v_add_co_u32 v7, vcc_lo, v7, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v6, vcc_lo, v8, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v5
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v11, v3, v2
v_mad_u64_u32 v[6:7], null, v1, v2, 0
v_mad_u64_u32 v[4:5], null, v3, v10, 0
v_mad_u64_u32 v[8:9], null, v1, v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v11, v4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v7, vcc_lo
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v2, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s4, v7, 0
v_mov_b32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s4, v8, v[2:3]
v_sub_co_u32 v2, vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
v_sub_co_u32 v3, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cmp_eq_u32_e64 s2, 0, v1
v_cndmask_b32_e64 v3, 0, -1, vcc_lo
v_add_co_u32 v5, vcc_lo, v7, 2
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v8, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, -1, v2, s2
v_cndmask_b32_e32 v3, -1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v7, 1
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v8, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v2, v9, v6 :: v_dual_cndmask_b32 v3, v4, v5
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_dual_cndmask_b32 v6, v8, v2 :: v_dual_cndmask_b32 v5, v7, v3
.LBB0_6:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s3, 0, s4
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s4
v_sub_nc_u32_e32 v2, v3, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v5, v1, v3, vcc_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 v[5:6], v[0:1]
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x20
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_10:
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v11, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v3, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v4, v[9:10], off
v_add_co_u32 v7, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v3, vcc_lo
global_load_b32 v9, v[11:12], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(2)
v_add_f32_e32 v4, v1, v4
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v9
v_cmp_le_u64_e64 s0, v[5:6], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v7
s_or_b32 s1, s0, s1
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sumGradPfS_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sumGradPfS_S_S_S_i, .Lfunc_end0-_Z7sumGradPfS_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sumGradPfS_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sumGradPfS_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019df76_00000000-6_sumGrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i
.type _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i, @function
_Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7sumGradPfS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i, .-_Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i
.globl _Z7sumGradPfS_S_S_S_i
.type _Z7sumGradPfS_S_S_S_i, @function
_Z7sumGradPfS_S_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7sumGradPfS_S_S_S_iPfS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sumGradPfS_S_S_S_i, .-_Z7sumGradPfS_S_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sumGradPfS_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sumGradPfS_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumGrad.hip"
.globl _Z22__device_stub__sumGradPfS_S_S_S_i # -- Begin function _Z22__device_stub__sumGradPfS_S_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__sumGradPfS_S_S_S_i,@function
_Z22__device_stub__sumGradPfS_S_S_S_i: # @_Z22__device_stub__sumGradPfS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7sumGradPfS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__sumGradPfS_S_S_S_i, .Lfunc_end0-_Z22__device_stub__sumGradPfS_S_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sumGradPfS_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sumGradPfS_S_S_S_i,@object # @_Z7sumGradPfS_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z7sumGradPfS_S_S_S_i
.p2align 3, 0x0
_Z7sumGradPfS_S_S_S_i:
.quad _Z22__device_stub__sumGradPfS_S_S_S_i
.size _Z7sumGradPfS_S_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sumGradPfS_S_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sumGradPfS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sumGradPfS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
#include <pthread.h>
#include <cuda.h>
#define NUM_THREADs 5
#define BLOCK_SIZE 16
#define PI 3.141592654
#define MEGEXTRA 1000000
typedef struct Matrix
{
int width;
int height;
double* elements;
} Matrix;
__global__ void find1elt(double *m, double *rs, int n)
{
int rownum = blockIdx.x; // this thread will handle row # rownum
double sum = 0;
for (int k = 0; k < n; k++)
sum += m[rownum*n+k];
rs[rownum] = sum;
}
__global__ void Vector_Sub( double *dev_a , double *dev_b , double *dev_c,int n)
{
//Get the id of thread within a block
// unsigned short tid = threadIdx.x ;
int tid=blockIdx.x * blockDim.x + threadIdx.x;
if ( tid < n ) // check the boundry condition for the threads{
{
dev_c [tid] = (dev_a[tid]*1.0) - (dev_b[tid]*0.5) ;
// printf("%f %f\n",dev_a[tid],dev_b[tid]);
}
}
extern "C" void get_host(Matrix A, Matrix D,double* Host_c , int n, int m,int dev_no){
int nDevices;
cudaGetDeviceCount(&nDevices);
if(nDevices!=6){
printf("shit\n");
nDevices = 6;
}
dev_no = ((dev_no)%(nDevices));
dev_no = nDevices - dev_no -1 ;
cudaSetDevice(dev_no);
double *dm, // device matrix
*hrs, // host rowsums
*drs; // device rowsums
//int n;
double msize = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// allocate space for device matrix
cudaMalloc((void **)&dm,msize);
// copy host matrix to device matrix
cudaMemcpy(dm,D.elements,msize,cudaMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize = n * sizeof(double);
hrs = (double *) malloc(rssize);
cudaMalloc((void **)&drs,rssize);
// set up parameters for threads structure
dim3 dimGrid(n,1); // n blocks
dim3 dimBlock(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid,dimBlock>>>(dm,drs,m);
// wait for kernel to finish
cudaThreadSynchronize();
// copy row vector from device to host
cudaMemcpy(hrs,drs,rssize,cudaMemcpyDeviceToHost);
// check results
/*
printf("Sum(A*Q.xA),2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs[i]);*/
// clean up
double *dm1, // device matrix
*hrs1, // host rowsums
*drs1; // device rowsums
//int n;
double msize1 = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// t = 0,i,j;
// allocate space for device matrix
cudaMalloc((void **)&dm1,msize1);
// copy host matrix to device matrix
cudaMemcpy(dm1,A.elements,msize1,cudaMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize1 = n * sizeof(double);
hrs1 = (double *) malloc(rssize1);
cudaMalloc((void **)&drs1,rssize1);
// set up parameters for threads structure
dim3 dimGrid1(n,1); // n blocks
dim3 dimBlock1(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid1,dimBlock1>>>(dm1,drs1,m);
// wait for kernel to finish
cudaThreadSynchronize();
// copy row vector from device to host
cudaMemcpy(hrs1,drs1,rssize1,cudaMemcpyDeviceToHost);
// check results
/* printf("Sum(A,2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs1[i]);*/
//Device array
double* dev_c1 ;
//Allocate the memory on the GPU
cudaMalloc((void **)&dev_c1 , n*sizeof(double) ) ;
dim3 dimGrid2(n,1); // n blocks
dim3 dimBlock2(1,1,1); // 1 thread per block
//Make a call to GPU kernel
//Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (dev_a1 , dev_b1 , dev_c1,n ) ;
Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (drs1 , drs , dev_c1,n ) ;
//Copy back to Host array from Device array
cudaMemcpy(Host_c , dev_c1 , n*sizeof(double) , cudaMemcpyDeviceToHost);
//Display the result
//printf("The F:=\n");
/* for ( int i = 0; i<n; i++ )
printf ("%f\n", Host_c[i] ) ; */
//Free the Device array memory
cudaFree (dev_c1) ;
cudaFree(dm);
free(hrs);
cudaFree(drs);
cudaFree(dm1);
free(hrs1);
cudaFree(drs1);
return;
} | code for sm_80
Function : _Z10Vector_SubPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DFMA R6, R4, -0.5, R2 ; /* 0xbfe000000406782b */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8find1eltPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fc6000001ff00 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x790 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0080*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0090*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd800078e00ff */
/*00c0*/ @!P0 BRA 0x690 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R26, -R2, c[0x0][0x170], RZ ; /* 0x00005c00021a7a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00f0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0100*/ IMAD R4, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a24 */
/* 0x001fe200078e02ff */
/*0110*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f04270 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fd400078e0205 */
/*0140*/ @!P0 BRA 0x590 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0x3f0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000f68000c1e1b00 */
/*01d0*/ LDG.E.64 R20, [R4.64+0x20] ; /* 0x0000200404147981 */
/* 0x000f68000c1e1b00 */
/*01e0*/ LDG.E.64 R24, [R4.64+0x28] ; /* 0x0000280404187981 */
/* 0x001f68000c1e1b00 */
/*01f0*/ LDG.E.64 R22, [R4.64+0x30] ; /* 0x0000300404167981 */
/* 0x000f68000c1e1b00 */
/*0200*/ LDG.E.64 R6, [R4.64+0x38] ; /* 0x0000380404067981 */
/* 0x000f68000c1e1b00 */
/*0210*/ LDG.E.64 R8, [R4.64+0x40] ; /* 0x0000400404087981 */
/* 0x000f62000c1e1b00 */
/*0220*/ DADD R12, R12, R10 ; /* 0x000000000c0c7229 */
/* 0x0060c6000000000a */
/*0230*/ LDG.E.64 R10, [R4.64+0x48] ; /* 0x00004804040a7981 */
/* 0x0010a6000c1e1b00 */
/*0240*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008308000000000e */
/*0250*/ LDG.E.64 R12, [R4.64+0x50] ; /* 0x00005004040c7981 */
/* 0x0020e4000c1e1b00 */
/*0260*/ DADD R16, R14, R16 ; /* 0x000000000e107229 */
/* 0x0103480000000010 */
/*0270*/ LDG.E.64 R14, [R4.64+0x58] ; /* 0x00005804040e7981 */
/* 0x002124000c1e1b00 */
/*0280*/ DADD R18, R16, R18 ; /* 0x0000000010127229 */
/* 0x0203480000000012 */
/*0290*/ LDG.E.64 R16, [R4.64+0x60] ; /* 0x0000600404107981 */
/* 0x002124000c1e1b00 */
/*02a0*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x0203480000000014 */
/*02b0*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680404127981 */
/* 0x002124000c1e1b00 */
/*02c0*/ DADD R24, R20, R24 ; /* 0x0000000014187229 */
/* 0x0203480000000018 */
/*02d0*/ LDG.E.64 R20, [R4.64+0x70] ; /* 0x0000700404147981 */
/* 0x002124000c1e1b00 */
/*02e0*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x0203480000000016 */
/*02f0*/ LDG.E.64 R24, [R4.64+0x78] ; /* 0x0000780404187981 */
/* 0x002122000c1e1b00 */
/*0300*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x020e620000000006 */
/*0320*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fc60003f24270 */
/*0340*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x002ea20000000008 */
/*0350*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fca0007f5e0ff */
/*0360*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0370*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x004ecc000000000a */
/*0380*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x008f0c000000000c */
/*0390*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x010e0c000000000e */
/*03a0*/ DADD R6, R6, R16 ; /* 0x0000000006067229 */
/* 0x001e0c0000000010 */
/*03b0*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x001e0c0000000012 */
/*03c0*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x001e0c0000000014 */
/*03d0*/ DADD R10, R6, R24 ; /* 0x00000000060a7229 */
/* 0x0010620000000018 */
/*03e0*/ @P1 BRA 0x190 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*03f0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*0400*/ @!P1 BRA 0x570 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E.64 R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1b00 */
/*0420*/ LDG.E.64 R20, [R4.64+0x8] ; /* 0x0000080404147981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000f28000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R4.64+0x18] ; /* 0x0000180404107981 */
/* 0x000f68000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000f68000c1e1b00 */
/*0460*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x000f68000c1e1b00 */
/*0470*/ LDG.E.64 R8, [R4.64+0x30] ; /* 0x0000300404087981 */
/* 0x000f68000c1e1b00 */
/*0480*/ LDG.E.64 R6, [R4.64+0x38] ; /* 0x0000380404067981 */
/* 0x001f62000c1e1b00 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04a0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DADD R22, R10, R22 ; /* 0x000000000a167229 */
/* 0x006ecc0000000016 */
/*04d0*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x008f0c0000000014 */
/*04e0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x010f4c0000000012 */
/*04f0*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x020e0c0000000010 */
/*0500*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x001e0c000000000e */
/*0510*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x001e0c000000000c */
/*0520*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0010640000000008 */
/*0530*/ IADD3 R12, P1, R4, 0x40, RZ ; /* 0x00000040040c7810 */
/* 0x001fc80007f3e0ff */
/*0540*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x0020620000000006 */
/*0550*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0560*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0570*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x003fda0000705670 */
/*0580*/ @!P0 BRA 0x690 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*05a0*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ee8000c1e1b00 */
/*05b0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000f28000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000162000c1e1b00 */
/*05d0*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0600*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x004ecc000000000a */
/*0610*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x0083240000000008 */
/*0620*/ IADD3 R8, P1, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x002fc80007f3e0ff */
/*0630*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x010f62000000000c */
/*0640*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0605 */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*0660*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0670*/ DADD R10, R6, R14 ; /* 0x00000000060a7229 */
/* 0x020064000000000e */
/*0680*/ @P0 BRA 0x590 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*0690*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*06a0*/ @!P0 BRA 0x790 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD R4, R0, c[0x0][0x170], R3 ; /* 0x00005c0000047a24 */
/* 0x001fc800078e0203 */
/*06d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*06e0*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0005 */
/*0700*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0710*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0006 */
/*0720*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0730*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R3, P1, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007f3e0ff */
/*0750*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*0760*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0770*/ DADD R10, R4, R10 ; /* 0x00000000040a7229 */
/* 0x006052000000000a */
/*0780*/ @P0 BRA 0x700 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*07a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0203 */
/*07b0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe2000c101b04 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
#include <pthread.h>
#include <cuda.h>
#define NUM_THREADs 5
#define BLOCK_SIZE 16
#define PI 3.141592654
#define MEGEXTRA 1000000
typedef struct Matrix
{
int width;
int height;
double* elements;
} Matrix;
__global__ void find1elt(double *m, double *rs, int n)
{
int rownum = blockIdx.x; // this thread will handle row # rownum
double sum = 0;
for (int k = 0; k < n; k++)
sum += m[rownum*n+k];
rs[rownum] = sum;
}
__global__ void Vector_Sub( double *dev_a , double *dev_b , double *dev_c,int n)
{
//Get the id of thread within a block
// unsigned short tid = threadIdx.x ;
int tid=blockIdx.x * blockDim.x + threadIdx.x;
if ( tid < n ) // check the boundry condition for the threads{
{
dev_c [tid] = (dev_a[tid]*1.0) - (dev_b[tid]*0.5) ;
// printf("%f %f\n",dev_a[tid],dev_b[tid]);
}
}
extern "C" void get_host(Matrix A, Matrix D,double* Host_c , int n, int m,int dev_no){
int nDevices;
cudaGetDeviceCount(&nDevices);
if(nDevices!=6){
printf("shit\n");
nDevices = 6;
}
dev_no = ((dev_no)%(nDevices));
dev_no = nDevices - dev_no -1 ;
cudaSetDevice(dev_no);
double *dm, // device matrix
*hrs, // host rowsums
*drs; // device rowsums
//int n;
double msize = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// allocate space for device matrix
cudaMalloc((void **)&dm,msize);
// copy host matrix to device matrix
cudaMemcpy(dm,D.elements,msize,cudaMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize = n * sizeof(double);
hrs = (double *) malloc(rssize);
cudaMalloc((void **)&drs,rssize);
// set up parameters for threads structure
dim3 dimGrid(n,1); // n blocks
dim3 dimBlock(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid,dimBlock>>>(dm,drs,m);
// wait for kernel to finish
cudaThreadSynchronize();
// copy row vector from device to host
cudaMemcpy(hrs,drs,rssize,cudaMemcpyDeviceToHost);
// check results
/*
printf("Sum(A*Q.xA),2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs[i]);*/
// clean up
double *dm1, // device matrix
*hrs1, // host rowsums
*drs1; // device rowsums
//int n;
double msize1 = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// t = 0,i,j;
// allocate space for device matrix
cudaMalloc((void **)&dm1,msize1);
// copy host matrix to device matrix
cudaMemcpy(dm1,A.elements,msize1,cudaMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize1 = n * sizeof(double);
hrs1 = (double *) malloc(rssize1);
cudaMalloc((void **)&drs1,rssize1);
// set up parameters for threads structure
dim3 dimGrid1(n,1); // n blocks
dim3 dimBlock1(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid1,dimBlock1>>>(dm1,drs1,m);
// wait for kernel to finish
cudaThreadSynchronize();
// copy row vector from device to host
cudaMemcpy(hrs1,drs1,rssize1,cudaMemcpyDeviceToHost);
// check results
/* printf("Sum(A,2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs1[i]);*/
//Device array
double* dev_c1 ;
//Allocate the memory on the GPU
cudaMalloc((void **)&dev_c1 , n*sizeof(double) ) ;
dim3 dimGrid2(n,1); // n blocks
dim3 dimBlock2(1,1,1); // 1 thread per block
//Make a call to GPU kernel
//Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (dev_a1 , dev_b1 , dev_c1,n ) ;
Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (drs1 , drs , dev_c1,n ) ;
//Copy back to Host array from Device array
cudaMemcpy(Host_c , dev_c1 , n*sizeof(double) , cudaMemcpyDeviceToHost);
//Display the result
//printf("The F:=\n");
/* for ( int i = 0; i<n; i++ )
printf ("%f\n", Host_c[i] ) ; */
//Free the Device array memory
cudaFree (dev_c1) ;
cudaFree(dm);
free(hrs);
cudaFree(drs);
cudaFree(dm1);
free(hrs1);
cudaFree(drs1);
return;
} | .file "tmpxft_000f9b3d_00000000-6_host_c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8find1eltPdS_iPdS_i
.type _Z30__device_stub__Z8find1eltPdS_iPdS_i, @function
_Z30__device_stub__Z8find1eltPdS_iPdS_i:
.LFB2105:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8find1eltPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z30__device_stub__Z8find1eltPdS_iPdS_i, .-_Z30__device_stub__Z8find1eltPdS_iPdS_i
.globl _Z8find1eltPdS_i
.type _Z8find1eltPdS_i, @function
_Z8find1eltPdS_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8find1eltPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z8find1eltPdS_i, .-_Z8find1eltPdS_i
.globl _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
.type _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i, @function
_Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10Vector_SubPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i, .-_Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
.globl _Z10Vector_SubPdS_S_i
.type _Z10Vector_SubPdS_S_i, @function
_Z10Vector_SubPdS_S_i:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _Z10Vector_SubPdS_S_i, .-_Z10Vector_SubPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "shit\n"
.text
.globl get_host
.type get_host, @function
get_host:
.LFB2080:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %r15
movq %rcx, %rbp
movq %r8, 8(%rsp)
movl %r9d, %ebx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $6, 20(%rsp)
jne .L34
.L20:
movl 20(%rsp), %edi
movl 216(%rsp), %eax
cltd
idivl %edi
subl %edx, %edi
subl $1, %edi
call cudaSetDevice@PLT
movl %ebx, %eax
imull 208(%rsp), %eax
cltq
salq $3, %rax
js .L21
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L22:
comisd .LC1(%rip), %xmm0
jnb .L23
cvttsd2siq %xmm0, %r13
.L24:
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq %ebx, %r12
salq $3, %r12
js .L25
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
.L26:
comisd .LC1(%rip), %xmm0
jnb .L27
cvttsd2siq %xmm0, %rbp
.L28:
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %ebx, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $6, 20(%rsp)
jmp .L20
.L21:
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L22
.L23:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %r13
btcq $63, %r13
jmp .L24
.L25:
movq %r12, %rax
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L26
.L27:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %rbp
btcq $63, %rbp
jmp .L28
.L35:
movl 208(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8find1eltPdS_iPdS_i
jmp .L29
.L36:
movl 208(%rsp), %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z8find1eltPdS_iPdS_i
jmp .L30
.L37:
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2080:
.size get_host, .-get_host
.section .rodata.str1.1
.LC2:
.string "_Z10Vector_SubPdS_S_i"
.LC3:
.string "_Z8find1eltPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10Vector_SubPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8find1eltPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
#include <pthread.h>
#include <cuda.h>
#define NUM_THREADs 5
#define BLOCK_SIZE 16
#define PI 3.141592654
#define MEGEXTRA 1000000
typedef struct Matrix
{
int width;
int height;
double* elements;
} Matrix;
__global__ void find1elt(double *m, double *rs, int n)
{
int rownum = blockIdx.x; // this thread will handle row # rownum
double sum = 0;
for (int k = 0; k < n; k++)
sum += m[rownum*n+k];
rs[rownum] = sum;
}
__global__ void Vector_Sub( double *dev_a , double *dev_b , double *dev_c,int n)
{
//Get the id of thread within a block
// unsigned short tid = threadIdx.x ;
int tid=blockIdx.x * blockDim.x + threadIdx.x;
if ( tid < n ) // check the boundry condition for the threads{
{
dev_c [tid] = (dev_a[tid]*1.0) - (dev_b[tid]*0.5) ;
// printf("%f %f\n",dev_a[tid],dev_b[tid]);
}
}
extern "C" void get_host(Matrix A, Matrix D,double* Host_c , int n, int m,int dev_no){
int nDevices;
cudaGetDeviceCount(&nDevices);
if(nDevices!=6){
printf("shit\n");
nDevices = 6;
}
dev_no = ((dev_no)%(nDevices));
dev_no = nDevices - dev_no -1 ;
cudaSetDevice(dev_no);
double *dm, // device matrix
*hrs, // host rowsums
*drs; // device rowsums
//int n;
double msize = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// allocate space for device matrix
cudaMalloc((void **)&dm,msize);
// copy host matrix to device matrix
cudaMemcpy(dm,D.elements,msize,cudaMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize = n * sizeof(double);
hrs = (double *) malloc(rssize);
cudaMalloc((void **)&drs,rssize);
// set up parameters for threads structure
dim3 dimGrid(n,1); // n blocks
dim3 dimBlock(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid,dimBlock>>>(dm,drs,m);
// wait for kernel to finish
cudaThreadSynchronize();
// copy row vector from device to host
cudaMemcpy(hrs,drs,rssize,cudaMemcpyDeviceToHost);
// check results
/*
printf("Sum(A*Q.xA),2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs[i]);*/
// clean up
double *dm1, // device matrix
*hrs1, // host rowsums
*drs1; // device rowsums
//int n;
double msize1 = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// t = 0,i,j;
// allocate space for device matrix
cudaMalloc((void **)&dm1,msize1);
// copy host matrix to device matrix
cudaMemcpy(dm1,A.elements,msize1,cudaMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize1 = n * sizeof(double);
hrs1 = (double *) malloc(rssize1);
cudaMalloc((void **)&drs1,rssize1);
// set up parameters for threads structure
dim3 dimGrid1(n,1); // n blocks
dim3 dimBlock1(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid1,dimBlock1>>>(dm1,drs1,m);
// wait for kernel to finish
cudaThreadSynchronize();
// copy row vector from device to host
cudaMemcpy(hrs1,drs1,rssize1,cudaMemcpyDeviceToHost);
// check results
/* printf("Sum(A,2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs1[i]);*/
//Device array
double* dev_c1 ;
//Allocate the memory on the GPU
cudaMalloc((void **)&dev_c1 , n*sizeof(double) ) ;
dim3 dimGrid2(n,1); // n blocks
dim3 dimBlock2(1,1,1); // 1 thread per block
//Make a call to GPU kernel
//Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (dev_a1 , dev_b1 , dev_c1,n ) ;
Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (drs1 , drs , dev_c1,n ) ;
//Copy back to Host array from Device array
cudaMemcpy(Host_c , dev_c1 , n*sizeof(double) , cudaMemcpyDeviceToHost);
//Display the result
//printf("The F:=\n");
/* for ( int i = 0; i<n; i++ )
printf ("%f\n", Host_c[i] ) ; */
//Free the Device array memory
cudaFree (dev_c1) ;
cudaFree(dm);
free(hrs);
cudaFree(drs);
cudaFree(dm1);
free(hrs1);
cudaFree(drs1);
return;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
#include <pthread.h>
#include <hip/hip_runtime.h>
#define NUM_THREADs 5
#define BLOCK_SIZE 16
#define PI 3.141592654
#define MEGEXTRA 1000000
typedef struct Matrix
{
int width;
int height;
double* elements;
} Matrix;
__global__ void find1elt(double *m, double *rs, int n)
{
int rownum = blockIdx.x; // this thread will handle row # rownum
double sum = 0;
for (int k = 0; k < n; k++)
sum += m[rownum*n+k];
rs[rownum] = sum;
}
__global__ void Vector_Sub( double *dev_a , double *dev_b , double *dev_c,int n)
{
//Get the id of thread within a block
// unsigned short tid = threadIdx.x ;
int tid=blockIdx.x * blockDim.x + threadIdx.x;
if ( tid < n ) // check the boundry condition for the threads{
{
dev_c [tid] = (dev_a[tid]*1.0) - (dev_b[tid]*0.5) ;
// printf("%f %f\n",dev_a[tid],dev_b[tid]);
}
}
extern "C" void get_host(Matrix A, Matrix D,double* Host_c , int n, int m,int dev_no){
int nDevices;
hipGetDeviceCount(&nDevices);
if(nDevices!=6){
printf("shit\n");
nDevices = 6;
}
dev_no = ((dev_no)%(nDevices));
dev_no = nDevices - dev_no -1 ;
hipSetDevice(dev_no);
double *dm, // device matrix
*hrs, // host rowsums
*drs; // device rowsums
//int n;
double msize = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// allocate space for device matrix
hipMalloc((void **)&dm,msize);
// copy host matrix to device matrix
hipMemcpy(dm,D.elements,msize,hipMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize = n * sizeof(double);
hrs = (double *) malloc(rssize);
hipMalloc((void **)&drs,rssize);
// set up parameters for threads structure
dim3 dimGrid(n,1); // n blocks
dim3 dimBlock(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid,dimBlock>>>(dm,drs,m);
// wait for kernel to finish
hipDeviceSynchronize();
// copy row vector from device to host
hipMemcpy(hrs,drs,rssize,hipMemcpyDeviceToHost);
// check results
/*
printf("Sum(A*Q.xA),2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs[i]);*/
// clean up
double *dm1, // device matrix
*hrs1, // host rowsums
*drs1; // device rowsums
//int n;
double msize1 = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// t = 0,i,j;
// allocate space for device matrix
hipMalloc((void **)&dm1,msize1);
// copy host matrix to device matrix
hipMemcpy(dm1,A.elements,msize1,hipMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize1 = n * sizeof(double);
hrs1 = (double *) malloc(rssize1);
hipMalloc((void **)&drs1,rssize1);
// set up parameters for threads structure
dim3 dimGrid1(n,1); // n blocks
dim3 dimBlock1(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid1,dimBlock1>>>(dm1,drs1,m);
// wait for kernel to finish
hipDeviceSynchronize();
// copy row vector from device to host
hipMemcpy(hrs1,drs1,rssize1,hipMemcpyDeviceToHost);
// check results
/* printf("Sum(A,2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs1[i]);*/
//Device array
double* dev_c1 ;
//Allocate the memory on the GPU
hipMalloc((void **)&dev_c1 , n*sizeof(double) ) ;
dim3 dimGrid2(n,1); // n blocks
dim3 dimBlock2(1,1,1); // 1 thread per block
//Make a call to GPU kernel
//Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (dev_a1 , dev_b1 , dev_c1,n ) ;
Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (drs1 , drs , dev_c1,n ) ;
//Copy back to Host array from Device array
hipMemcpy(Host_c , dev_c1 , n*sizeof(double) , hipMemcpyDeviceToHost);
//Display the result
//printf("The F:=\n");
/* for ( int i = 0; i<n; i++ )
printf ("%f\n", Host_c[i] ) ; */
//Free the Device array memory
hipFree (dev_c1) ;
hipFree(dm);
free(hrs);
hipFree(drs);
hipFree(dm1);
free(hrs1);
hipFree(drs1);
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
#include <pthread.h>
#include <hip/hip_runtime.h>
#define NUM_THREADs 5
#define BLOCK_SIZE 16
#define PI 3.141592654
#define MEGEXTRA 1000000
typedef struct Matrix
{
int width;
int height;
double* elements;
} Matrix;
__global__ void find1elt(double *m, double *rs, int n)
{
int rownum = blockIdx.x; // this thread will handle row # rownum
double sum = 0;
for (int k = 0; k < n; k++)
sum += m[rownum*n+k];
rs[rownum] = sum;
}
__global__ void Vector_Sub( double *dev_a , double *dev_b , double *dev_c,int n)
{
//Get the id of thread within a block
// unsigned short tid = threadIdx.x ;
int tid=blockIdx.x * blockDim.x + threadIdx.x;
if ( tid < n ) // check the boundry condition for the threads{
{
dev_c [tid] = (dev_a[tid]*1.0) - (dev_b[tid]*0.5) ;
// printf("%f %f\n",dev_a[tid],dev_b[tid]);
}
}
extern "C" void get_host(Matrix A, Matrix D,double* Host_c , int n, int m,int dev_no){
int nDevices;
hipGetDeviceCount(&nDevices);
if(nDevices!=6){
printf("shit\n");
nDevices = 6;
}
dev_no = ((dev_no)%(nDevices));
dev_no = nDevices - dev_no -1 ;
hipSetDevice(dev_no);
double *dm, // device matrix
*hrs, // host rowsums
*drs; // device rowsums
//int n;
double msize = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// allocate space for device matrix
hipMalloc((void **)&dm,msize);
// copy host matrix to device matrix
hipMemcpy(dm,D.elements,msize,hipMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize = n * sizeof(double);
hrs = (double *) malloc(rssize);
hipMalloc((void **)&drs,rssize);
// set up parameters for threads structure
dim3 dimGrid(n,1); // n blocks
dim3 dimBlock(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid,dimBlock>>>(dm,drs,m);
// wait for kernel to finish
hipDeviceSynchronize();
// copy row vector from device to host
hipMemcpy(hrs,drs,rssize,hipMemcpyDeviceToHost);
// check results
/*
printf("Sum(A*Q.xA),2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs[i]);*/
// clean up
double *dm1, // device matrix
*hrs1, // host rowsums
*drs1; // device rowsums
//int n;
double msize1 = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// t = 0,i,j;
// allocate space for device matrix
hipMalloc((void **)&dm1,msize1);
// copy host matrix to device matrix
hipMemcpy(dm1,A.elements,msize1,hipMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize1 = n * sizeof(double);
hrs1 = (double *) malloc(rssize1);
hipMalloc((void **)&drs1,rssize1);
// set up parameters for threads structure
dim3 dimGrid1(n,1); // n blocks
dim3 dimBlock1(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid1,dimBlock1>>>(dm1,drs1,m);
// wait for kernel to finish
hipDeviceSynchronize();
// copy row vector from device to host
hipMemcpy(hrs1,drs1,rssize1,hipMemcpyDeviceToHost);
// check results
/* printf("Sum(A,2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs1[i]);*/
//Device array
double* dev_c1 ;
//Allocate the memory on the GPU
hipMalloc((void **)&dev_c1 , n*sizeof(double) ) ;
dim3 dimGrid2(n,1); // n blocks
dim3 dimBlock2(1,1,1); // 1 thread per block
//Make a call to GPU kernel
//Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (dev_a1 , dev_b1 , dev_c1,n ) ;
Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (drs1 , drs , dev_c1,n ) ;
//Copy back to Host array from Device array
hipMemcpy(Host_c , dev_c1 , n*sizeof(double) , hipMemcpyDeviceToHost);
//Display the result
//printf("The F:=\n");
/* for ( int i = 0; i<n; i++ )
printf ("%f\n", Host_c[i] ) ; */
//Free the Device array memory
hipFree (dev_c1) ;
hipFree(dm);
free(hrs);
hipFree(drs);
hipFree(dm1);
free(hrs1);
hipFree(drs1);
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8find1eltPdS_i
.globl _Z8find1eltPdS_i
.p2align 8
.type _Z8find1eltPdS_i,@function
_Z8find1eltPdS_i:
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_mul_i32 s6, s2, s3
v_mov_b32_e32 v0, 0
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[6:7], s[6:7], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
.LBB0_2:
s_load_b64 s[6:7], s[4:5], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], s[6:7]
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8find1eltPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8find1eltPdS_i, .Lfunc_end0-_Z8find1eltPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10Vector_SubPdS_S_i
.globl _Z10Vector_SubPdS_S_i
.p2align 8
.type _Z10Vector_SubPdS_S_i,@function
_Z10Vector_SubPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], -0.5, v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10Vector_SubPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10Vector_SubPdS_S_i, .Lfunc_end1-_Z10Vector_SubPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8find1eltPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z8find1eltPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10Vector_SubPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10Vector_SubPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <stdbool.h>
#include <unistd.h>
#include <pthread.h>
#include <hip/hip_runtime.h>
#define NUM_THREADs 5
#define BLOCK_SIZE 16
#define PI 3.141592654
#define MEGEXTRA 1000000
typedef struct Matrix
{
int width;
int height;
double* elements;
} Matrix;
__global__ void find1elt(double *m, double *rs, int n)
{
int rownum = blockIdx.x; // this thread will handle row # rownum
double sum = 0;
for (int k = 0; k < n; k++)
sum += m[rownum*n+k];
rs[rownum] = sum;
}
__global__ void Vector_Sub( double *dev_a , double *dev_b , double *dev_c,int n)
{
//Get the id of thread within a block
// unsigned short tid = threadIdx.x ;
int tid=blockIdx.x * blockDim.x + threadIdx.x;
if ( tid < n ) // check the boundry condition for the threads{
{
dev_c [tid] = (dev_a[tid]*1.0) - (dev_b[tid]*0.5) ;
// printf("%f %f\n",dev_a[tid],dev_b[tid]);
}
}
extern "C" void get_host(Matrix A, Matrix D,double* Host_c , int n, int m,int dev_no){
int nDevices;
hipGetDeviceCount(&nDevices);
if(nDevices!=6){
printf("shit\n");
nDevices = 6;
}
dev_no = ((dev_no)%(nDevices));
dev_no = nDevices - dev_no -1 ;
hipSetDevice(dev_no);
double *dm, // device matrix
*hrs, // host rowsums
*drs; // device rowsums
//int n;
double msize = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// allocate space for device matrix
hipMalloc((void **)&dm,msize);
// copy host matrix to device matrix
hipMemcpy(dm,D.elements,msize,hipMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize = n * sizeof(double);
hrs = (double *) malloc(rssize);
hipMalloc((void **)&drs,rssize);
// set up parameters for threads structure
dim3 dimGrid(n,1); // n blocks
dim3 dimBlock(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid,dimBlock>>>(dm,drs,m);
// wait for kernel to finish
hipDeviceSynchronize();
// copy row vector from device to host
hipMemcpy(hrs,drs,rssize,hipMemcpyDeviceToHost);
// check results
/*
printf("Sum(A*Q.xA),2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs[i]);*/
// clean up
double *dm1, // device matrix
*hrs1, // host rowsums
*drs1; // device rowsums
//int n;
double msize1 = n * m * sizeof(double); // size of matrix in bytes
// allocate space for host matrix
// as a test, fill matrix with consecutive integers
// t = 0,i,j;
// allocate space for device matrix
hipMalloc((void **)&dm1,msize1);
// copy host matrix to device matrix
hipMemcpy(dm1,A.elements,msize1,hipMemcpyHostToDevice);
// allocate host, device rowsum arrays
double rssize1 = n * sizeof(double);
hrs1 = (double *) malloc(rssize1);
hipMalloc((void **)&drs1,rssize1);
// set up parameters for threads structure
dim3 dimGrid1(n,1); // n blocks
dim3 dimBlock1(1,1,1); // 1 thread per block
// invoke the kernel
find1elt<<<dimGrid1,dimBlock1>>>(dm1,drs1,m);
// wait for kernel to finish
hipDeviceSynchronize();
// copy row vector from device to host
hipMemcpy(hrs1,drs1,rssize1,hipMemcpyDeviceToHost);
// check results
/* printf("Sum(A,2)=\n");
if (n < 100) for(int i=0; i<n; i++) printf("%f\n",hrs1[i]);*/
//Device array
double* dev_c1 ;
//Allocate the memory on the GPU
hipMalloc((void **)&dev_c1 , n*sizeof(double) ) ;
dim3 dimGrid2(n,1); // n blocks
dim3 dimBlock2(1,1,1); // 1 thread per block
//Make a call to GPU kernel
//Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (dev_a1 , dev_b1 , dev_c1,n ) ;
Vector_Sub<<< dimGrid2 ,dimBlock2 >>> (drs1 , drs , dev_c1,n ) ;
//Copy back to Host array from Device array
hipMemcpy(Host_c , dev_c1 , n*sizeof(double) , hipMemcpyDeviceToHost);
//Display the result
//printf("The F:=\n");
/* for ( int i = 0; i<n; i++ )
printf ("%f\n", Host_c[i] ) ; */
//Free the Device array memory
hipFree (dev_c1) ;
hipFree(dm);
free(hrs);
hipFree(drs);
hipFree(dm1);
free(hrs1);
hipFree(drs1);
return;
} | .text
.file "host_c.hip"
.globl _Z23__device_stub__find1eltPdS_i # -- Begin function _Z23__device_stub__find1eltPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__find1eltPdS_i,@function
_Z23__device_stub__find1eltPdS_i: # @_Z23__device_stub__find1eltPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8find1eltPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__find1eltPdS_i, .Lfunc_end0-_Z23__device_stub__find1eltPdS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Vector_SubPdS_S_i # -- Begin function _Z25__device_stub__Vector_SubPdS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__Vector_SubPdS_S_i,@function
_Z25__device_stub__Vector_SubPdS_S_i: # @_Z25__device_stub__Vector_SubPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10Vector_SubPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__Vector_SubPdS_S_i, .Lfunc_end1-_Z25__device_stub__Vector_SubPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function get_host
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl get_host
.p2align 4, 0x90
.type get_host,@function
get_host: # @get_host
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r15d
movq %r8, 176(%rsp) # 8-byte Spill
movq %rcx, %rbx
movq %rsi, 168(%rsp) # 8-byte Spill
movl 248(%rsp), %r14d
movl 240(%rsp), %r12d
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $6, 4(%rsp)
je .LBB2_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
movl $6, 4(%rsp)
.LBB2_2:
movabsq $4294967297, %rbp # imm = 0x100000001
movl 4(%rsp), %edi
movl %r14d, %eax
cltd
idivl %edi
notl %edx
addl %edx, %edi
callq hipSetDevice
movl %r12d, %eax
imull %r15d, %eax
cltq
shlq $3, %rax
movq %rax, %xmm0
punpckldq .LCPI2_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI2_2(%rip), %xmm1
cvttsd2si %xmm1, %r13
andq %rcx, %r13
orq %rax, %r13
leaq 112(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 112(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, 120(%rsp) # 4-byte Spill
movslq %r15d, %r15
leaq (,%r15,8), %r14
movq %r14, %xmm0
punpckldq .LCPI2_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI2_2(%rip), %xmm1
cvttsd2si %xmm1, %rbx
andq %rcx, %rbx
orq %rax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r12
leaq 88(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r15d, %eax
leaq (%rax,%rbp), %r15
decq %r15
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 112(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl 240(%rsp), %eax
movl %eax, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8find1eltPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 88(%rsp), %rsi
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 104(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
movq 168(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq malloc
movq %rax, %r13
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 104(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl 240(%rsp), %eax
movl %eax, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8find1eltPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq 80(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 80(%rsp), %rax
movq 88(%rsp), %rcx
movq 96(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl 120(%rsp), %eax # 4-byte Reload
movl %eax, 124(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10Vector_SubPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 96(%rsp), %rsi
movq 176(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq 88(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq 80(%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size get_host, .Lfunc_end2-get_host
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8find1eltPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Vector_SubPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8find1eltPdS_i,@object # @_Z8find1eltPdS_i
.section .rodata,"a",@progbits
.globl _Z8find1eltPdS_i
.p2align 3, 0x0
_Z8find1eltPdS_i:
.quad _Z23__device_stub__find1eltPdS_i
.size _Z8find1eltPdS_i, 8
.type _Z10Vector_SubPdS_S_i,@object # @_Z10Vector_SubPdS_S_i
.globl _Z10Vector_SubPdS_S_i
.p2align 3, 0x0
_Z10Vector_SubPdS_S_i:
.quad _Z25__device_stub__Vector_SubPdS_S_i
.size _Z10Vector_SubPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8find1eltPdS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10Vector_SubPdS_S_i"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "shit"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__find1eltPdS_i
.addrsig_sym _Z25__device_stub__Vector_SubPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8find1eltPdS_i
.addrsig_sym _Z10Vector_SubPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10Vector_SubPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DFMA R6, R4, -0.5, R2 ; /* 0xbfe000000406782b */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8find1eltPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fc6000001ff00 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x790 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0080*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0090*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd800078e00ff */
/*00c0*/ @!P0 BRA 0x690 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R26, -R2, c[0x0][0x170], RZ ; /* 0x00005c00021a7a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00f0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0100*/ IMAD R4, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a24 */
/* 0x001fe200078e02ff */
/*0110*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f04270 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fd400078e0205 */
/*0140*/ @!P0 BRA 0x590 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0x3f0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000f68000c1e1b00 */
/*01d0*/ LDG.E.64 R20, [R4.64+0x20] ; /* 0x0000200404147981 */
/* 0x000f68000c1e1b00 */
/*01e0*/ LDG.E.64 R24, [R4.64+0x28] ; /* 0x0000280404187981 */
/* 0x001f68000c1e1b00 */
/*01f0*/ LDG.E.64 R22, [R4.64+0x30] ; /* 0x0000300404167981 */
/* 0x000f68000c1e1b00 */
/*0200*/ LDG.E.64 R6, [R4.64+0x38] ; /* 0x0000380404067981 */
/* 0x000f68000c1e1b00 */
/*0210*/ LDG.E.64 R8, [R4.64+0x40] ; /* 0x0000400404087981 */
/* 0x000f62000c1e1b00 */
/*0220*/ DADD R12, R12, R10 ; /* 0x000000000c0c7229 */
/* 0x0060c6000000000a */
/*0230*/ LDG.E.64 R10, [R4.64+0x48] ; /* 0x00004804040a7981 */
/* 0x0010a6000c1e1b00 */
/*0240*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008308000000000e */
/*0250*/ LDG.E.64 R12, [R4.64+0x50] ; /* 0x00005004040c7981 */
/* 0x0020e4000c1e1b00 */
/*0260*/ DADD R16, R14, R16 ; /* 0x000000000e107229 */
/* 0x0103480000000010 */
/*0270*/ LDG.E.64 R14, [R4.64+0x58] ; /* 0x00005804040e7981 */
/* 0x002124000c1e1b00 */
/*0280*/ DADD R18, R16, R18 ; /* 0x0000000010127229 */
/* 0x0203480000000012 */
/*0290*/ LDG.E.64 R16, [R4.64+0x60] ; /* 0x0000600404107981 */
/* 0x002124000c1e1b00 */
/*02a0*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x0203480000000014 */
/*02b0*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680404127981 */
/* 0x002124000c1e1b00 */
/*02c0*/ DADD R24, R20, R24 ; /* 0x0000000014187229 */
/* 0x0203480000000018 */
/*02d0*/ LDG.E.64 R20, [R4.64+0x70] ; /* 0x0000700404147981 */
/* 0x002124000c1e1b00 */
/*02e0*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x0203480000000016 */
/*02f0*/ LDG.E.64 R24, [R4.64+0x78] ; /* 0x0000780404187981 */
/* 0x002122000c1e1b00 */
/*0300*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x020e620000000006 */
/*0320*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0330*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fc60003f24270 */
/*0340*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x002ea20000000008 */
/*0350*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fca0007f5e0ff */
/*0360*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0370*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x004ecc000000000a */
/*0380*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x008f0c000000000c */
/*0390*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x010e0c000000000e */
/*03a0*/ DADD R6, R6, R16 ; /* 0x0000000006067229 */
/* 0x001e0c0000000010 */
/*03b0*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x001e0c0000000012 */
/*03c0*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x001e0c0000000014 */
/*03d0*/ DADD R10, R6, R24 ; /* 0x00000000060a7229 */
/* 0x0010620000000018 */
/*03e0*/ @P1 BRA 0x190 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*03f0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*0400*/ @!P1 BRA 0x570 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E.64 R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1b00 */
/*0420*/ LDG.E.64 R20, [R4.64+0x8] ; /* 0x0000080404147981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000f28000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R4.64+0x18] ; /* 0x0000180404107981 */
/* 0x000f68000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000f68000c1e1b00 */
/*0460*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x000f68000c1e1b00 */
/*0470*/ LDG.E.64 R8, [R4.64+0x30] ; /* 0x0000300404087981 */
/* 0x000f68000c1e1b00 */
/*0480*/ LDG.E.64 R6, [R4.64+0x38] ; /* 0x0000380404067981 */
/* 0x001f62000c1e1b00 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04a0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DADD R22, R10, R22 ; /* 0x000000000a167229 */
/* 0x006ecc0000000016 */
/*04d0*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x008f0c0000000014 */
/*04e0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x010f4c0000000012 */
/*04f0*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x020e0c0000000010 */
/*0500*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x001e0c000000000e */
/*0510*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x001e0c000000000c */
/*0520*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0010640000000008 */
/*0530*/ IADD3 R12, P1, R4, 0x40, RZ ; /* 0x00000040040c7810 */
/* 0x001fc80007f3e0ff */
/*0540*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x0020620000000006 */
/*0550*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0560*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0570*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x003fda0000705670 */
/*0580*/ @!P0 BRA 0x690 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*05a0*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ee8000c1e1b00 */
/*05b0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x000f28000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000162000c1e1b00 */
/*05d0*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0600*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x004ecc000000000a */
/*0610*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x0083240000000008 */
/*0620*/ IADD3 R8, P1, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x002fc80007f3e0ff */
/*0630*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x010f62000000000c */
/*0640*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0605 */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*0660*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0670*/ DADD R10, R6, R14 ; /* 0x00000000060a7229 */
/* 0x020064000000000e */
/*0680*/ @P0 BRA 0x590 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*0690*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*06a0*/ @!P0 BRA 0x790 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD R4, R0, c[0x0][0x170], R3 ; /* 0x00005c0000047a24 */
/* 0x001fc800078e0203 */
/*06d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*06e0*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0005 */
/*0700*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0710*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0006 */
/*0720*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0730*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R3, P1, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007f3e0ff */
/*0750*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*0760*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0770*/ DADD R10, R4, R10 ; /* 0x00000000040a7229 */
/* 0x006052000000000a */
/*0780*/ @P0 BRA 0x700 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*07a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0203 */
/*07b0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe2000c101b04 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8find1eltPdS_i
.globl _Z8find1eltPdS_i
.p2align 8
.type _Z8find1eltPdS_i,@function
_Z8find1eltPdS_i:
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_mul_i32 s6, s2, s3
v_mov_b32_e32 v0, 0
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[6:7], s[6:7], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
.LBB0_2:
s_load_b64 s[6:7], s[4:5], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], s[6:7]
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8find1eltPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8find1eltPdS_i, .Lfunc_end0-_Z8find1eltPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10Vector_SubPdS_S_i
.globl _Z10Vector_SubPdS_S_i
.p2align 8
.type _Z10Vector_SubPdS_S_i,@function
_Z10Vector_SubPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], -0.5, v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10Vector_SubPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10Vector_SubPdS_S_i, .Lfunc_end1-_Z10Vector_SubPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8find1eltPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z8find1eltPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10Vector_SubPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10Vector_SubPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f9b3d_00000000-6_host_c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8find1eltPdS_iPdS_i
.type _Z30__device_stub__Z8find1eltPdS_iPdS_i, @function
_Z30__device_stub__Z8find1eltPdS_iPdS_i:
.LFB2105:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8find1eltPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z30__device_stub__Z8find1eltPdS_iPdS_i, .-_Z30__device_stub__Z8find1eltPdS_iPdS_i
.globl _Z8find1eltPdS_i
.type _Z8find1eltPdS_i, @function
_Z8find1eltPdS_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8find1eltPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z8find1eltPdS_i, .-_Z8find1eltPdS_i
.globl _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
.type _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i, @function
_Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10Vector_SubPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i, .-_Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
.globl _Z10Vector_SubPdS_S_i
.type _Z10Vector_SubPdS_S_i, @function
_Z10Vector_SubPdS_S_i:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _Z10Vector_SubPdS_S_i, .-_Z10Vector_SubPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "shit\n"
.text
.globl get_host
.type get_host, @function
get_host:
.LFB2080:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %r15
movq %rcx, %rbp
movq %r8, 8(%rsp)
movl %r9d, %ebx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $6, 20(%rsp)
jne .L34
.L20:
movl 20(%rsp), %edi
movl 216(%rsp), %eax
cltd
idivl %edi
subl %edx, %edi
subl $1, %edi
call cudaSetDevice@PLT
movl %ebx, %eax
imull 208(%rsp), %eax
cltq
salq $3, %rax
js .L21
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L22:
comisd .LC1(%rip), %xmm0
jnb .L23
cvttsd2siq %xmm0, %r13
.L24:
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq %ebx, %r12
salq $3, %r12
js .L25
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
.L26:
comisd .LC1(%rip), %xmm0
jnb .L27
cvttsd2siq %xmm0, %rbp
.L28:
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %ebx, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $6, 20(%rsp)
jmp .L20
.L21:
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L22
.L23:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %r13
btcq $63, %r13
jmp .L24
.L25:
movq %r12, %rax
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L26
.L27:
subsd .LC1(%rip), %xmm0
cvttsd2siq %xmm0, %rbp
btcq $63, %rbp
jmp .L28
.L35:
movl 208(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8find1eltPdS_iPdS_i
jmp .L29
.L36:
movl 208(%rsp), %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z8find1eltPdS_iPdS_i
jmp .L30
.L37:
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z35__device_stub__Z10Vector_SubPdS_S_iPdS_S_i
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2080:
.size get_host, .-get_host
.section .rodata.str1.1
.LC2:
.string "_Z10Vector_SubPdS_S_i"
.LC3:
.string "_Z8find1eltPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10Vector_SubPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8find1eltPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "host_c.hip"
.globl _Z23__device_stub__find1eltPdS_i # -- Begin function _Z23__device_stub__find1eltPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__find1eltPdS_i,@function
_Z23__device_stub__find1eltPdS_i: # @_Z23__device_stub__find1eltPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8find1eltPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__find1eltPdS_i, .Lfunc_end0-_Z23__device_stub__find1eltPdS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Vector_SubPdS_S_i # -- Begin function _Z25__device_stub__Vector_SubPdS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__Vector_SubPdS_S_i,@function
_Z25__device_stub__Vector_SubPdS_S_i: # @_Z25__device_stub__Vector_SubPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10Vector_SubPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__Vector_SubPdS_S_i, .Lfunc_end1-_Z25__device_stub__Vector_SubPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function get_host
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl get_host
.p2align 4, 0x90
.type get_host,@function
get_host: # @get_host
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r15d
movq %r8, 176(%rsp) # 8-byte Spill
movq %rcx, %rbx
movq %rsi, 168(%rsp) # 8-byte Spill
movl 248(%rsp), %r14d
movl 240(%rsp), %r12d
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $6, 4(%rsp)
je .LBB2_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
movl $6, 4(%rsp)
.LBB2_2:
movabsq $4294967297, %rbp # imm = 0x100000001
movl 4(%rsp), %edi
movl %r14d, %eax
cltd
idivl %edi
notl %edx
addl %edx, %edi
callq hipSetDevice
movl %r12d, %eax
imull %r15d, %eax
cltq
shlq $3, %rax
movq %rax, %xmm0
punpckldq .LCPI2_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI2_2(%rip), %xmm1
cvttsd2si %xmm1, %r13
andq %rcx, %r13
orq %rax, %r13
leaq 112(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 112(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, 120(%rsp) # 4-byte Spill
movslq %r15d, %r15
leaq (,%r15,8), %r14
movq %r14, %xmm0
punpckldq .LCPI2_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI2_2(%rip), %xmm1
cvttsd2si %xmm1, %rbx
andq %rcx, %rbx
orq %rax, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r12
leaq 88(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r15d, %eax
leaq (%rax,%rbp), %r15
decq %r15
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 112(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl 240(%rsp), %eax
movl %eax, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8find1eltPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 88(%rsp), %rsi
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 104(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
movq 168(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq malloc
movq %rax, %r13
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 104(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl 240(%rsp), %eax
movl %eax, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8find1eltPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq 80(%rsp), %rsi
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 80(%rsp), %rax
movq 88(%rsp), %rcx
movq 96(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl 120(%rsp), %eax # 4-byte Reload
movl %eax, 124(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10Vector_SubPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 96(%rsp), %rsi
movq 176(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq 88(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq 80(%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size get_host, .Lfunc_end2-get_host
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8find1eltPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Vector_SubPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8find1eltPdS_i,@object # @_Z8find1eltPdS_i
.section .rodata,"a",@progbits
.globl _Z8find1eltPdS_i
.p2align 3, 0x0
_Z8find1eltPdS_i:
.quad _Z23__device_stub__find1eltPdS_i
.size _Z8find1eltPdS_i, 8
.type _Z10Vector_SubPdS_S_i,@object # @_Z10Vector_SubPdS_S_i
.globl _Z10Vector_SubPdS_S_i
.p2align 3, 0x0
_Z10Vector_SubPdS_S_i:
.quad _Z25__device_stub__Vector_SubPdS_S_i
.size _Z10Vector_SubPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8find1eltPdS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10Vector_SubPdS_S_i"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "shit"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__find1eltPdS_i
.addrsig_sym _Z25__device_stub__Vector_SubPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8find1eltPdS_i
.addrsig_sym _Z10Vector_SubPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void NmDistanceGradKernel(int b,int n,const float * xyz1,int m,const float * xyz2,const float * grad_dist1,const int * idx1,float * grad_xyz1,float * grad_xyz2){
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int j=threadIdx.x+blockIdx.y*blockDim.x;j<n;j+=blockDim.x*gridDim.y){
float x1=xyz1[(i*n+j)*3+0];
float y1=xyz1[(i*n+j)*3+1];
float z1=xyz1[(i*n+j)*3+2];
int j2=idx1[i*n+j];
float x2=xyz2[(i*m+j2)*3+0];
float y2=xyz2[(i*m+j2)*3+1];
float z2=xyz2[(i*m+j2)*3+2];
float g=grad_dist1[i*n+j]*2;
atomicAdd(&(grad_xyz1[(i*n+j)*3+0]),g*(x1-x2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+1]),g*(y1-y2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+2]),g*(z1-z2));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+0]),-(g*(x1-x2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+1]),-(g*(y1-y2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+2]),-(g*(z1-z2)));
}
}
} | code for sm_80
Function : _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0070*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x164], PT ; /* 0x0000590004007a0c */
/* 0x000fe20003f06270 */
/*0090*/ BSSY B0, 0x350 ; /* 0x000002b000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x340 ; /* 0x0000029000000947 */
/* 0x001fea0003800000 */
/*00b0*/ MOV R5, R4 ; /* 0x0000000400057202 */
/* 0x000fc80000000f00 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x001fe200000001ff */
/*00d0*/ IMAD R13, R0, c[0x0][0x164], R5 ; /* 0x00005900000d7a24 */
/* 0x000fd200078e0205 */
/*00e0*/ IMAD.WIDE R8, R13, R6, c[0x0][0x188] ; /* 0x000062000d087625 */
/* 0x000fcc00078e0206 */
/*00f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x0000a2000c1e1900 */
/*0100*/ LEA R7, R13.reuse, R13, 0x1 ; /* 0x0000000d0d077211 */
/* 0x040fe200078e08ff */
/*0110*/ IMAD.WIDE R12, R13, R6, c[0x0][0x180] ; /* 0x000060000d0c7625 */
/* 0x000fc800078e0206 */
/*0120*/ IMAD.WIDE R10, R7, R6, c[0x0][0x168] ; /* 0x00005a00070a7625 */
/* 0x000fe400078e0206 */
/*0130*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R14, [R10.64+0x4] ; /* 0x000004040a0e7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R8, [R10.64+0x8] ; /* 0x000008040a087981 */
/* 0x001ee2000c1e1900 */
/*0170*/ IMAD R2, R0, c[0x0][0x170], R9 ; /* 0x00005c0000027a24 */
/* 0x004fca00078e0209 */
/*0180*/ LEA R15, R2, R2, 0x1 ; /* 0x00000002020f7211 */
/* 0x000fca00078e08ff */
/*0190*/ IMAD.WIDE R2, R15, R6, c[0x0][0x178] ; /* 0x00005e000f027625 */
/* 0x000fca00078e0206 */
/*01a0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000128000c1e1900 */
/*01b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000168000c1e1900 */
/*01c0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x0000a4000c1e1900 */
/*01d0*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x001fca0000000f00 */
/*01e0*/ IMAD R5, R2, c[0x0][0x10], R5 ; /* 0x0000040002057a24 */
/* 0x000fca00078e0205 */
/*01f0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06270 */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ FADD R19, -R16, R19 ; /* 0x0000001310137221 */
/* 0x010fe40000000100 */
/*0220*/ FADD R16, R12, R12 ; /* 0x0000000c0c107221 */
/* 0x008fe40000000000 */
/*0230*/ FADD R21, R14, -R9 ; /* 0x800000090e157221 */
/* 0x020fe40000000000 */
/*0240*/ FMUL R19, R16, R19 ; /* 0x0000001310137220 */
/* 0x000fe40000400000 */
/*0250*/ FADD R17, R8, -R17 ; /* 0x8000001108117221 */
/* 0x004fc40000000000 */
/*0260*/ IMAD.WIDE R8, R7, R6, c[0x0][0x190] ; /* 0x0000640007087625 */
/* 0x000fc800078e0206 */
/*0270*/ FMUL R21, R16.reuse, R21 ; /* 0x0000001510157220 */
/* 0x040fe20000400000 */
/*0280*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64], R19 ; /* 0x000000130800798e */
/* 0x0001e2000c10e784 */
/*0290*/ FMUL R17, R16, R17 ; /* 0x0000001110117220 */
/* 0x000fe40000400000 */
/*02a0*/ IMAD.WIDE R6, R15, R6, c[0x0][0x198] ; /* 0x000066000f067625 */
/* 0x000fe200078e0206 */
/*02b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64+0x4], R21 ; /* 0x000004150800798e */
/* 0x0001e6000c10e784 */
/*02c0*/ FADD R3, -R19, -RZ ; /* 0x800000ff13037221 */
/* 0x000fe20000000100 */
/*02d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64+0x8], R17 ; /* 0x000008110800798e */
/* 0x0001e2000c10e784 */
/*02e0*/ FADD R11, -R21, -RZ ; /* 0x800000ff150b7221 */
/* 0x000fc40000000100 */
/*02f0*/ FADD R13, -R17, -RZ ; /* 0x800000ff110d7221 */
/* 0x000fe20000000100 */
/*0300*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R3 ; /* 0x000000030600798e */
/* 0x0001e8000c10e784 */
/*0310*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64+0x4], R11 ; /* 0x0000040b0600798e */
/* 0x0001e8000c10e784 */
/*0320*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64+0x8], R13 ; /* 0x0000080d0600798e */
/* 0x0001e2000c10e784 */
/*0330*/ @!P0 BRA 0xc0 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0370*/ @!P0 BRA 0x80 ; /* 0xfffffd0000008947 */
/* 0x000fea000383ffff */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void NmDistanceGradKernel(int b,int n,const float * xyz1,int m,const float * xyz2,const float * grad_dist1,const int * idx1,float * grad_xyz1,float * grad_xyz2){
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int j=threadIdx.x+blockIdx.y*blockDim.x;j<n;j+=blockDim.x*gridDim.y){
float x1=xyz1[(i*n+j)*3+0];
float y1=xyz1[(i*n+j)*3+1];
float z1=xyz1[(i*n+j)*3+2];
int j2=idx1[i*n+j];
float x2=xyz2[(i*m+j2)*3+0];
float y2=xyz2[(i*m+j2)*3+1];
float z2=xyz2[(i*m+j2)*3+2];
float g=grad_dist1[i*n+j]*2;
atomicAdd(&(grad_xyz1[(i*n+j)*3+0]),g*(x1-x2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+1]),g*(y1-y2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+2]),g*(z1-z2));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+0]),-(g*(x1-x2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+1]),-(g*(y1-y2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+2]),-(g*(z1-z2)));
}
}
} | .file "tmpxft_0001ae32_00000000-6_NmDistanceGradKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_
.type _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_, @function
_Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movl %ecx, 44(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_, .-_Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_
.globl _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.type _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, @function
_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, .-_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void NmDistanceGradKernel(int b,int n,const float * xyz1,int m,const float * xyz2,const float * grad_dist1,const int * idx1,float * grad_xyz1,float * grad_xyz2){
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int j=threadIdx.x+blockIdx.y*blockDim.x;j<n;j+=blockDim.x*gridDim.y){
float x1=xyz1[(i*n+j)*3+0];
float y1=xyz1[(i*n+j)*3+1];
float z1=xyz1[(i*n+j)*3+2];
int j2=idx1[i*n+j];
float x2=xyz2[(i*m+j2)*3+0];
float y2=xyz2[(i*m+j2)*3+1];
float z2=xyz2[(i*m+j2)*3+2];
float g=grad_dist1[i*n+j]*2;
atomicAdd(&(grad_xyz1[(i*n+j)*3+0]),g*(x1-x2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+1]),g*(y1-y2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+2]),g*(z1-z2));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+0]),-(g*(x1-x2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+1]),-(g*(y1-y2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+2]),-(g*(z1-z2)));
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NmDistanceGradKernel(int b,int n,const float * xyz1,int m,const float * xyz2,const float * grad_dist1,const int * idx1,float * grad_xyz1,float * grad_xyz2){
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int j=threadIdx.x+blockIdx.y*blockDim.x;j<n;j+=blockDim.x*gridDim.y){
float x1=xyz1[(i*n+j)*3+0];
float y1=xyz1[(i*n+j)*3+1];
float z1=xyz1[(i*n+j)*3+2];
int j2=idx1[i*n+j];
float x2=xyz2[(i*m+j2)*3+0];
float y2=xyz2[(i*m+j2)*3+1];
float z2=xyz2[(i*m+j2)*3+2];
float g=grad_dist1[i*n+j]*2;
atomicAdd(&(grad_xyz1[(i*n+j)*3+0]),g*(x1-x2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+1]),g*(y1-y2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+2]),g*(z1-z2));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+0]),-(g*(x1-x2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+1]),-(g*(y1-y2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+2]),-(g*(z1-z2)));
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NmDistanceGradKernel(int b,int n,const float * xyz1,int m,const float * xyz2,const float * grad_dist1,const int * idx1,float * grad_xyz1,float * grad_xyz2){
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int j=threadIdx.x+blockIdx.y*blockDim.x;j<n;j+=blockDim.x*gridDim.y){
float x1=xyz1[(i*n+j)*3+0];
float y1=xyz1[(i*n+j)*3+1];
float z1=xyz1[(i*n+j)*3+2];
int j2=idx1[i*n+j];
float x2=xyz2[(i*m+j2)*3+0];
float y2=xyz2[(i*m+j2)*3+1];
float z2=xyz2[(i*m+j2)*3+2];
float g=grad_dist1[i*n+j]*2;
atomicAdd(&(grad_xyz1[(i*n+j)*3+0]),g*(x1-x2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+1]),g*(y1-y2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+2]),g*(z1-z2));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+0]),-(g*(x1-x2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+1]),-(g*(y1-y2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+2]),-(g*(z1-z2)));
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.globl _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.p2align 8
.type _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_,@function
_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_:
s_load_b32 s18, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s18
s_cbranch_scc1 .LBB0_18
s_clause 0x6
s_load_b32 s22, s[0:1], 0x4c
s_load_b32 s19, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b32 s20, s[0:1], 0x40
s_load_b64 s[12:13], s[0:1], 0x8
s_load_b32 s21, s[0:1], 0x10
s_load_b256 s[4:11], s[0:1], 0x18
s_add_u32 s16, s0, 64
s_addc_u32 s17, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s22, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s19, v1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
s_add_i32 s14, s20, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s14, s18
s_cbranch_scc1 .LBB0_18
.LBB0_3:
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s24, s[16:17], 0x4
v_mov_b32_e32 v0, v1
s_mul_i32 s22, s14, s19
s_mul_i32 s23, s14, s21
s_mov_b32 s25, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s24, s24, s1
.LBB0_5:
v_add_nc_u32_e32 v2, s22, v0
s_mov_b32 s26, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s8, v3
v_add_co_ci_u32_e64 v6, s0, s9, v4, s0
global_load_b32 v9, v[5:6], off
v_lshl_add_u32 v5, v2, 1, v2
v_add_co_u32 v2, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s7, v4, s0
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v7, 1, v5
v_add_nc_u32_e32 v12, 2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[14:15], 2, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[10:11], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s12, v14
v_add_co_ci_u32_e64 v7, s0, s13, v15, s0
global_load_b32 v25, v[2:3], off
global_load_b32 v26, v[6:7], off
v_add_co_u32 v16, s0, s12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v17, s0, s13, v11, s0
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v5, s23, v9
v_lshlrev_b64 v[8:9], 2, v[12:13]
v_lshl_add_u32 v4, v5, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v12, 1, v4
v_add_nc_u32_e32 v2, 2, v4
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[12:13]
v_add_co_u32 v12, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s5, v7, s0
v_add_co_u32 v18, s0, s12, v8
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_ci_u32_e64 v19, s0, s13, v9, s0
v_add_co_u32 v21, s0, s4, v4
global_load_b32 v27, v[12:13], off
v_add_co_ci_u32_e64 v22, s0, s5, v5, s0
v_add_co_u32 v23, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v24, s0, s5, v3, s0
v_add_co_u32 v12, s0, s10, v14
v_add_co_ci_u32_e64 v13, s0, s11, v15, s0
s_clause 0x1
global_load_b32 v20, v[16:17], off
global_load_b32 v17, v[18:19], off
s_clause 0x1
global_load_b32 v21, v[21:22], off
global_load_b32 v18, v[23:24], off
global_load_b32 v15, v[12:13], off
s_waitcnt vmcnt(5)
v_dual_add_f32 v19, v25, v25 :: v_dual_sub_f32 v14, v26, v27
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v16, v14, v19
.LBB0_6:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v14, v15, v16
global_atomic_cmpswap_b32 v14, v[12:13], v[14:15], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v14, v15
v_mov_b32_e32 v15, v14
s_or_b32 s26, s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v10, s0, s10, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s11, v11, s0
v_sub_f32_e32 v12, v20, v21
s_mov_b32 s26, 0
global_load_b32 v13, v[10:11], off
v_mul_f32_e32 v14, v12, v19
.LBB0_8:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v13, v14
global_atomic_cmpswap_b32 v12, v[10:11], v[12:13], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v12, v13
v_mov_b32_e32 v13, v12
s_or_b32 s26, s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v8, s0, s10, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s11, v9, s0
v_sub_f32_e32 v10, v17, v18
s_mov_b32 s26, 0
global_load_b32 v11, v[8:9], off
v_mul_f32_e32 v12, v10, v19
.LBB0_10:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, v11, v12
global_atomic_cmpswap_b32 v10, v[8:9], v[10:11], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v10, v11
v_mov_b32_e32 v11, v10
s_or_b32 s26, s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_10
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v6, s0, s2, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
s_mov_b32 s26, 0
global_load_b32 v9, v[6:7], off
.LBB0_12:
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v9, v16
global_atomic_cmpswap_b32 v8, v[6:7], v[8:9], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v8, v9
v_mov_b32_e32 v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s26, s0, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v4, s0, s2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_mov_b32 s26, 0
global_load_b32 v7, v[4:5], off
.LBB0_14:
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v7, v14
global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v6, v7
v_mov_b32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s26, s0, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_14
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_mov_b32 s26, 0
global_load_b32 v5, v[2:3], off
.LBB0_16:
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v5, v12
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v4, v5
v_mov_b32_e32 v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s26, s0, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_16
s_or_b32 exec_lo, exec_lo, s26
v_add_nc_u32_e32 v0, s24, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s19, v0
s_or_b32 s25, s0, s25
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_18:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, .Lfunc_end0-_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NmDistanceGradKernel(int b,int n,const float * xyz1,int m,const float * xyz2,const float * grad_dist1,const int * idx1,float * grad_xyz1,float * grad_xyz2){
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int j=threadIdx.x+blockIdx.y*blockDim.x;j<n;j+=blockDim.x*gridDim.y){
float x1=xyz1[(i*n+j)*3+0];
float y1=xyz1[(i*n+j)*3+1];
float z1=xyz1[(i*n+j)*3+2];
int j2=idx1[i*n+j];
float x2=xyz2[(i*m+j2)*3+0];
float y2=xyz2[(i*m+j2)*3+1];
float z2=xyz2[(i*m+j2)*3+2];
float g=grad_dist1[i*n+j]*2;
atomicAdd(&(grad_xyz1[(i*n+j)*3+0]),g*(x1-x2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+1]),g*(y1-y2));
atomicAdd(&(grad_xyz1[(i*n+j)*3+2]),g*(z1-z2));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+0]),-(g*(x1-x2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+1]),-(g*(y1-y2)));
atomicAdd(&(grad_xyz2[(i*m+j2)*3+2]),-(g*(z1-z2)));
}
}
} | .text
.file "NmDistanceGradKernel.hip"
.globl _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_ # -- Begin function _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.p2align 4, 0x90
.type _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_,@function
_Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_: # @_Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, .Lfunc_end0-_Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_,@object # @_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.section .rodata,"a",@progbits
.globl _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.p2align 3, 0x0
_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_:
.quad _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.size _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0070*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x164], PT ; /* 0x0000590004007a0c */
/* 0x000fe20003f06270 */
/*0090*/ BSSY B0, 0x350 ; /* 0x000002b000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x340 ; /* 0x0000029000000947 */
/* 0x001fea0003800000 */
/*00b0*/ MOV R5, R4 ; /* 0x0000000400057202 */
/* 0x000fc80000000f00 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x001fe200000001ff */
/*00d0*/ IMAD R13, R0, c[0x0][0x164], R5 ; /* 0x00005900000d7a24 */
/* 0x000fd200078e0205 */
/*00e0*/ IMAD.WIDE R8, R13, R6, c[0x0][0x188] ; /* 0x000062000d087625 */
/* 0x000fcc00078e0206 */
/*00f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x0000a2000c1e1900 */
/*0100*/ LEA R7, R13.reuse, R13, 0x1 ; /* 0x0000000d0d077211 */
/* 0x040fe200078e08ff */
/*0110*/ IMAD.WIDE R12, R13, R6, c[0x0][0x180] ; /* 0x000060000d0c7625 */
/* 0x000fc800078e0206 */
/*0120*/ IMAD.WIDE R10, R7, R6, c[0x0][0x168] ; /* 0x00005a00070a7625 */
/* 0x000fe400078e0206 */
/*0130*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R14, [R10.64+0x4] ; /* 0x000004040a0e7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R8, [R10.64+0x8] ; /* 0x000008040a087981 */
/* 0x001ee2000c1e1900 */
/*0170*/ IMAD R2, R0, c[0x0][0x170], R9 ; /* 0x00005c0000027a24 */
/* 0x004fca00078e0209 */
/*0180*/ LEA R15, R2, R2, 0x1 ; /* 0x00000002020f7211 */
/* 0x000fca00078e08ff */
/*0190*/ IMAD.WIDE R2, R15, R6, c[0x0][0x178] ; /* 0x00005e000f027625 */
/* 0x000fca00078e0206 */
/*01a0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000128000c1e1900 */
/*01b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000168000c1e1900 */
/*01c0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x0000a4000c1e1900 */
/*01d0*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x001fca0000000f00 */
/*01e0*/ IMAD R5, R2, c[0x0][0x10], R5 ; /* 0x0000040002057a24 */
/* 0x000fca00078e0205 */
/*01f0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06270 */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ FADD R19, -R16, R19 ; /* 0x0000001310137221 */
/* 0x010fe40000000100 */
/*0220*/ FADD R16, R12, R12 ; /* 0x0000000c0c107221 */
/* 0x008fe40000000000 */
/*0230*/ FADD R21, R14, -R9 ; /* 0x800000090e157221 */
/* 0x020fe40000000000 */
/*0240*/ FMUL R19, R16, R19 ; /* 0x0000001310137220 */
/* 0x000fe40000400000 */
/*0250*/ FADD R17, R8, -R17 ; /* 0x8000001108117221 */
/* 0x004fc40000000000 */
/*0260*/ IMAD.WIDE R8, R7, R6, c[0x0][0x190] ; /* 0x0000640007087625 */
/* 0x000fc800078e0206 */
/*0270*/ FMUL R21, R16.reuse, R21 ; /* 0x0000001510157220 */
/* 0x040fe20000400000 */
/*0280*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64], R19 ; /* 0x000000130800798e */
/* 0x0001e2000c10e784 */
/*0290*/ FMUL R17, R16, R17 ; /* 0x0000001110117220 */
/* 0x000fe40000400000 */
/*02a0*/ IMAD.WIDE R6, R15, R6, c[0x0][0x198] ; /* 0x000066000f067625 */
/* 0x000fe200078e0206 */
/*02b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64+0x4], R21 ; /* 0x000004150800798e */
/* 0x0001e6000c10e784 */
/*02c0*/ FADD R3, -R19, -RZ ; /* 0x800000ff13037221 */
/* 0x000fe20000000100 */
/*02d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64+0x8], R17 ; /* 0x000008110800798e */
/* 0x0001e2000c10e784 */
/*02e0*/ FADD R11, -R21, -RZ ; /* 0x800000ff150b7221 */
/* 0x000fc40000000100 */
/*02f0*/ FADD R13, -R17, -RZ ; /* 0x800000ff110d7221 */
/* 0x000fe20000000100 */
/*0300*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R3 ; /* 0x000000030600798e */
/* 0x0001e8000c10e784 */
/*0310*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64+0x4], R11 ; /* 0x0000040b0600798e */
/* 0x0001e8000c10e784 */
/*0320*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64+0x8], R13 ; /* 0x0000080d0600798e */
/* 0x0001e2000c10e784 */
/*0330*/ @!P0 BRA 0xc0 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0370*/ @!P0 BRA 0x80 ; /* 0xfffffd0000008947 */
/* 0x000fea000383ffff */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.globl _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.p2align 8
.type _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_,@function
_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_:
s_load_b32 s18, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s18
s_cbranch_scc1 .LBB0_18
s_clause 0x6
s_load_b32 s22, s[0:1], 0x4c
s_load_b32 s19, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b32 s20, s[0:1], 0x40
s_load_b64 s[12:13], s[0:1], 0x8
s_load_b32 s21, s[0:1], 0x10
s_load_b256 s[4:11], s[0:1], 0x18
s_add_u32 s16, s0, 64
s_addc_u32 s17, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s22, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s19, v1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
s_add_i32 s14, s20, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s14, s18
s_cbranch_scc1 .LBB0_18
.LBB0_3:
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s24, s[16:17], 0x4
v_mov_b32_e32 v0, v1
s_mul_i32 s22, s14, s19
s_mul_i32 s23, s14, s21
s_mov_b32 s25, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s24, s24, s1
.LBB0_5:
v_add_nc_u32_e32 v2, s22, v0
s_mov_b32 s26, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s8, v3
v_add_co_ci_u32_e64 v6, s0, s9, v4, s0
global_load_b32 v9, v[5:6], off
v_lshl_add_u32 v5, v2, 1, v2
v_add_co_u32 v2, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s7, v4, s0
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v7, 1, v5
v_add_nc_u32_e32 v12, 2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[14:15], 2, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[10:11], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s12, v14
v_add_co_ci_u32_e64 v7, s0, s13, v15, s0
global_load_b32 v25, v[2:3], off
global_load_b32 v26, v[6:7], off
v_add_co_u32 v16, s0, s12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v17, s0, s13, v11, s0
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v5, s23, v9
v_lshlrev_b64 v[8:9], 2, v[12:13]
v_lshl_add_u32 v4, v5, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v12, 1, v4
v_add_nc_u32_e32 v2, 2, v4
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[12:13]
v_add_co_u32 v12, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s5, v7, s0
v_add_co_u32 v18, s0, s12, v8
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_ci_u32_e64 v19, s0, s13, v9, s0
v_add_co_u32 v21, s0, s4, v4
global_load_b32 v27, v[12:13], off
v_add_co_ci_u32_e64 v22, s0, s5, v5, s0
v_add_co_u32 v23, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v24, s0, s5, v3, s0
v_add_co_u32 v12, s0, s10, v14
v_add_co_ci_u32_e64 v13, s0, s11, v15, s0
s_clause 0x1
global_load_b32 v20, v[16:17], off
global_load_b32 v17, v[18:19], off
s_clause 0x1
global_load_b32 v21, v[21:22], off
global_load_b32 v18, v[23:24], off
global_load_b32 v15, v[12:13], off
s_waitcnt vmcnt(5)
v_dual_add_f32 v19, v25, v25 :: v_dual_sub_f32 v14, v26, v27
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v16, v14, v19
.LBB0_6:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v14, v15, v16
global_atomic_cmpswap_b32 v14, v[12:13], v[14:15], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v14, v15
v_mov_b32_e32 v15, v14
s_or_b32 s26, s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v10, s0, s10, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s11, v11, s0
v_sub_f32_e32 v12, v20, v21
s_mov_b32 s26, 0
global_load_b32 v13, v[10:11], off
v_mul_f32_e32 v14, v12, v19
.LBB0_8:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v13, v14
global_atomic_cmpswap_b32 v12, v[10:11], v[12:13], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v12, v13
v_mov_b32_e32 v13, v12
s_or_b32 s26, s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v8, s0, s10, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s11, v9, s0
v_sub_f32_e32 v10, v17, v18
s_mov_b32 s26, 0
global_load_b32 v11, v[8:9], off
v_mul_f32_e32 v12, v10, v19
.LBB0_10:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, v11, v12
global_atomic_cmpswap_b32 v10, v[8:9], v[10:11], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v10, v11
v_mov_b32_e32 v11, v10
s_or_b32 s26, s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_10
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v6, s0, s2, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
s_mov_b32 s26, 0
global_load_b32 v9, v[6:7], off
.LBB0_12:
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v9, v16
global_atomic_cmpswap_b32 v8, v[6:7], v[8:9], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v8, v9
v_mov_b32_e32 v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s26, s0, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v4, s0, s2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_mov_b32 s26, 0
global_load_b32 v7, v[4:5], off
.LBB0_14:
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v7, v14
global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v6, v7
v_mov_b32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s26, s0, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_14
s_or_b32 exec_lo, exec_lo, s26
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_mov_b32 s26, 0
global_load_b32 v5, v[2:3], off
.LBB0_16:
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v5, v12
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v4, v5
v_mov_b32_e32 v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s26, s0, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execnz .LBB0_16
s_or_b32 exec_lo, exec_lo, s26
v_add_nc_u32_e32 v0, s24, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s19, v0
s_or_b32 s25, s0, s25
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_18:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, .Lfunc_end0-_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001ae32_00000000-6_NmDistanceGradKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_
.type _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_, @function
_Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movl %ecx, 44(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_, .-_Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_
.globl _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.type _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, @function
_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_iiPKfiS0_S0_PKiPfS3_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, .-_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NmDistanceGradKernel.hip"
.globl _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_ # -- Begin function _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.p2align 4, 0x90
.type _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_,@function
_Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_: # @_Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, .Lfunc_end0-_Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_,@object # @_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.section .rodata,"a",@progbits
.globl _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.p2align 3, 0x0
_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_:
.quad _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.size _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20NmDistanceGradKerneliiPKfiS0_S0_PKiPfS3_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kExtractPatches3(float* images, float* patches, float* width_offset, float* height_offset, float* flip, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
int dest_col = blockIdx.x * blockDim.x + threadIdx.x;
int dest_row = blockIdx.y * blockDim.y + threadIdx.y;
if (dest_col < patch_width && dest_row < patch_height) {
for (unsigned int b = blockIdx.z; b < num_colors * num_images; b += gridDim.z) {
int color = b % num_colors;
int image_id = b / num_colors;
int source_row = int(height_offset[image_id]) + dest_row;
int source_col = int(width_offset[image_id]) + dest_col;
source_col = (flip[image_id] > 0.5) ? (img_width - source_col - 1) : source_col;
unsigned long source_index = source_col + img_width * (source_row + img_height * (color + num_colors * image_id));
unsigned long dest_index = dest_col + patch_width * (dest_row + patch_height * (color + num_colors * image_id));
__syncthreads();
patches[dest_index] = images[source_index];
}
}
} | code for sm_80
Function : _Z16kExtractPatches3PfS_S_S_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x198], PT ; /* 0x0000660000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x194], P0 ; /* 0x0000650002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ S2UR UR4, SR_CTAID.Z ; /* 0x00000000000479c3 */
/* 0x000e220000002700 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff037624 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fca00078e02ff */
/*00d0*/ ISETP.LE.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x001fda000bf03070 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ I2F.U32.RP R8, c[0x0][0x19c] ; /* 0x0000670000087b06 */
/* 0x000e220000209000 */
/*0100*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x19c], PT ; /* 0x00006700ff007a0c */
/* 0x000fe20003f05070 */
/*0110*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0170*/ IADD3 R5, RZ, -R7, RZ ; /* 0x80000007ff057210 */
/* 0x002fca0007ffe0ff */
/*0180*/ IMAD R5, R5, c[0x0][0x19c], RZ ; /* 0x0000670005057a24 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fe200078e0006 */
/*01a0*/ LOP3.LUT R5, RZ, c[0x0][0x19c], RZ, 0x33, !PT ; /* 0x00006700ff057a12 */
/* 0x000fca00078e33ff */
/*01b0*/ IMAD.HI.U32 R8, R7, R4, RZ ; /* 0x0000000407087227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x001fc800078e0a08 */
/*01d0*/ IMAD R6, R9, c[0x0][0x19c], R4 ; /* 0x0000670009067a24 */
/* 0x000fca00078e0204 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x19c], PT ; /* 0x0000670006007a0c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R6, R6, -c[0x0][0x19c], RZ ; /* 0x8000670006061a10 */
/* 0x000fe40007ffe0ff */
/*0200*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x19c], PT ; /* 0x0000670006007a0c */
/* 0x000fe40003f46070 */
/*0220*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fd60000000f00 */
/*0230*/ @P2 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108082810 */
/* 0x000fc80007ffe0ff */
/*0240*/ SEL R15, R5, R8, !P0 ; /* 0x00000008050f7207 */
/* 0x000fca0004000000 */
/*0250*/ IMAD.WIDE R10, R15, R6, c[0x0][0x170] ; /* 0x00005c000f0a7625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R8, R15.reuse, R6.reuse, c[0x0][0x178] ; /* 0x00005e000f087625 */
/* 0x0c0fe400078e0206 */
/*0270*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE R12, R15, R6, c[0x0][0x180] ; /* 0x000060000f0c7625 */
/* 0x000fe400078e0206 */
/*0290*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.MOV R21, RZ, RZ, -R15 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0a0f */
/*02c0*/ IMAD R14, R21, c[0x0][0x19c], R4 ; /* 0x00006700150e7a24 */
/* 0x000fc800078e0204 */
/*02d0*/ IMAD R14, R15, c[0x0][0x19c], R14 ; /* 0x000067000f0e7a24 */
/* 0x000fe200078e020e */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ F2I.TRUNC.NTZ R19, R10 ; /* 0x0000000a00137305 */
/* 0x004e30000020f100 */
/*0300*/ F2I.TRUNC.NTZ R17, R8 ; /* 0x0000000800117305 */
/* 0x008e62000020f100 */
/*0310*/ FSETP.GT.AND P1, PT, R12, 0.5, PT ; /* 0x3f0000000c00780b */
/* 0x010fc40003f24000 */
/*0320*/ IADD3 R19, R2, R19, RZ ; /* 0x0000001302137210 */
/* 0x001fc80007ffe0ff */
/*0330*/ LOP3.LUT R11, RZ, R19, RZ, 0x33, !PT ; /* 0x00000013ff0b7212 */
/* 0x000fe400078e33ff */
/*0340*/ IADD3 R17, R0, R17, RZ ; /* 0x0000001100117210 */
/* 0x002fca0007ffe0ff */
/*0350*/ @P1 IADD3 R19, R11, c[0x0][0x18c], RZ ; /* 0x000063000b131a10 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD R12, R14, c[0x0][0x190], R17 ; /* 0x000064000e0c7a24 */
/* 0x000fc800078e0211 */
/*0370*/ IMAD R9, R12, c[0x0][0x18c], R19 ; /* 0x000063000c097a24 */
/* 0x000fc800078e0213 */
/*0380*/ IMAD.WIDE R8, R9, R6, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fcc00078e0206 */
/*0390*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IADD3 R4, R4, c[0x0][0x14], RZ ; /* 0x0000050004047a10 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD R11, R14, c[0x0][0x198], R0 ; /* 0x000066000e0b7a24 */
/* 0x000fc600078e0200 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fe20003f26070 */
/*03d0*/ IMAD R11, R11, c[0x0][0x194], R2 ; /* 0x000065000b0b7a24 */
/* 0x000fc800078e0202 */
/*03e0*/ IMAD.WIDE R10, R11, R6, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fca00078e0206 */
/*03f0*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0041e6000c101904 */
/*0400*/ @!P1 BRA 0x1b0 ; /* 0xfffffda000009947 */
/* 0x000fea000383ffff */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kExtractPatches3(float* images, float* patches, float* width_offset, float* height_offset, float* flip, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
int dest_col = blockIdx.x * blockDim.x + threadIdx.x;
int dest_row = blockIdx.y * blockDim.y + threadIdx.y;
if (dest_col < patch_width && dest_row < patch_height) {
for (unsigned int b = blockIdx.z; b < num_colors * num_images; b += gridDim.z) {
int color = b % num_colors;
int image_id = b / num_colors;
int source_row = int(height_offset[image_id]) + dest_row;
int source_col = int(width_offset[image_id]) + dest_col;
source_col = (flip[image_id] > 0.5) ? (img_width - source_col - 1) : source_col;
unsigned long source_index = source_col + img_width * (source_row + img_height * (color + num_colors * image_id));
unsigned long dest_index = dest_col + patch_width * (dest_row + patch_height * (color + num_colors * image_id));
__syncthreads();
patches[dest_index] = images[source_index];
}
}
} | .file "tmpxft_0007012a_00000000-6_kExtractPatches3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.type _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kExtractPatches3PfS_S_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.globl _Z16kExtractPatches3PfS_S_S_S_iiiiii
.type _Z16kExtractPatches3PfS_S_S_S_iiiiii, @function
_Z16kExtractPatches3PfS_S_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16kExtractPatches3PfS_S_S_S_iiiiii, .-_Z16kExtractPatches3PfS_S_S_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16kExtractPatches3PfS_S_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kExtractPatches3PfS_S_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kExtractPatches3(float* images, float* patches, float* width_offset, float* height_offset, float* flip, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
int dest_col = blockIdx.x * blockDim.x + threadIdx.x;
int dest_row = blockIdx.y * blockDim.y + threadIdx.y;
if (dest_col < patch_width && dest_row < patch_height) {
for (unsigned int b = blockIdx.z; b < num_colors * num_images; b += gridDim.z) {
int color = b % num_colors;
int image_id = b / num_colors;
int source_row = int(height_offset[image_id]) + dest_row;
int source_col = int(width_offset[image_id]) + dest_col;
source_col = (flip[image_id] > 0.5) ? (img_width - source_col - 1) : source_col;
unsigned long source_index = source_col + img_width * (source_row + img_height * (color + num_colors * image_id));
unsigned long dest_index = dest_col + patch_width * (dest_row + patch_height * (color + num_colors * image_id));
__syncthreads();
patches[dest_index] = images[source_index];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches3(float* images, float* patches, float* width_offset, float* height_offset, float* flip, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
int dest_col = blockIdx.x * blockDim.x + threadIdx.x;
int dest_row = blockIdx.y * blockDim.y + threadIdx.y;
if (dest_col < patch_width && dest_row < patch_height) {
for (unsigned int b = blockIdx.z; b < num_colors * num_images; b += gridDim.z) {
int color = b % num_colors;
int image_id = b / num_colors;
int source_row = int(height_offset[image_id]) + dest_row;
int source_col = int(width_offset[image_id]) + dest_col;
source_col = (flip[image_id] > 0.5) ? (img_width - source_col - 1) : source_col;
unsigned long source_index = source_col + img_width * (source_row + img_height * (color + num_colors * image_id));
unsigned long dest_index = dest_col + patch_width * (dest_row + patch_height * (color + num_colors * image_id));
__syncthreads();
patches[dest_index] = images[source_index];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches3(float* images, float* patches, float* width_offset, float* height_offset, float* flip, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
int dest_col = blockIdx.x * blockDim.x + threadIdx.x;
int dest_row = blockIdx.y * blockDim.y + threadIdx.y;
if (dest_col < patch_width && dest_row < patch_height) {
for (unsigned int b = blockIdx.z; b < num_colors * num_images; b += gridDim.z) {
int color = b % num_colors;
int image_id = b / num_colors;
int source_row = int(height_offset[image_id]) + dest_row;
int source_col = int(width_offset[image_id]) + dest_col;
source_col = (flip[image_id] > 0.5) ? (img_width - source_col - 1) : source_col;
unsigned long source_index = source_col + img_width * (source_row + img_height * (color + num_colors * image_id));
unsigned long dest_index = dest_col + patch_width * (dest_row + patch_height * (color + num_colors * image_id));
__syncthreads();
patches[dest_index] = images[source_index];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kExtractPatches3PfS_S_S_S_iiiiii
.globl _Z16kExtractPatches3PfS_S_S_S_iiiiii
.p2align 8
.type _Z16kExtractPatches3PfS_S_S_S_iiiiii,@function
_Z16kExtractPatches3PfS_S_S_S_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b64 s[16:17], s[0:1], 0x34
s_add_u32 s4, s0, 64
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s19, s13, s3
s_mul_i32 s18, s14, s2
v_add_nc_u32_e32 v2, s19, v1
v_add_nc_u32_e32 v0, s18, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s16, v2
v_cmp_gt_i32_e64 s2, s17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s12, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s15, s13
s_cbranch_scc1 .LBB0_4
s_load_b32 s14, s[4:5], 0x8
s_load_b64 s[8:9], s[0:1], 0x2c
v_cvt_f32_u32_e32 v0, s12
s_mul_i32 s2, s15, s17
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v3, s18, s2, v4
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b256 s[0:7], s[0:1], 0x0
v_rcp_iflag_f32_e32 v0, v0
v_mul_lo_u32 v3, s16, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v0
v_add3_u32 v0, v1, v3, s19
s_waitcnt lgkmcnt(0)
s_mul_i32 s17, s14, s17
s_mul_i32 s19, s15, s9
v_cvt_u32_f32_e32 v3, v5
v_add3_u32 v4, s18, s19, v4
v_mov_b32_e32 v5, 0
s_mul_i32 s16, s17, s16
s_mul_i32 s9, s14, s9
s_sub_i32 s17, 0, s12
.LBB0_3:
v_readfirstlane_b32 s18, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s19, s17, s18
s_mul_hi_u32 s19, s18, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s18, s18, s19
s_mul_hi_u32 s18, s15, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_not_b32 s20, s18
s_mul_i32 s19, s17, s18
s_mul_i32 s20, s12, s20
s_add_i32 s19, s15, s19
s_add_i32 s21, s18, 1
s_add_i32 s20, s15, s20
s_cmp_ge_u32 s19, s12
s_cselect_b32 s18, s21, s18
s_cselect_b32 s19, s20, s19
s_add_i32 s20, s18, 1
s_cmp_ge_u32 s19, s12
s_cselect_b32 s18, s20, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s6, s18
s_addc_u32 s21, s7, s19
s_add_u32 s22, s4, s18
s_addc_u32 s23, s5, s19
s_clause 0x1
global_load_b32 v1, v5, s[20:21]
global_load_b32 v6, v5, s[22:23]
s_add_u32 s18, s10, s18
s_addc_u32 s19, s11, s19
s_add_i32 s15, s15, s14
global_load_b32 v7, v5, s[18:19]
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cmp_lt_u32 s15, s13
v_cvt_i32_f32_e32 v1, v1
v_cvt_i32_f32_e32 v6, v6
v_cmp_lt_f32_e32 vcc_lo, 0.5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v2, v6
v_add_nc_u32_e32 v9, v4, v1
v_add_nc_u32_e32 v4, s9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v8, v6, -1, s8
v_cndmask_b32_e32 v1, v6, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v9, s8, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s16, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kExtractPatches3PfS_S_S_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kExtractPatches3PfS_S_S_S_iiiiii, .Lfunc_end0-_Z16kExtractPatches3PfS_S_S_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kExtractPatches3PfS_S_S_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z16kExtractPatches3PfS_S_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches3(float* images, float* patches, float* width_offset, float* height_offset, float* flip, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
int dest_col = blockIdx.x * blockDim.x + threadIdx.x;
int dest_row = blockIdx.y * blockDim.y + threadIdx.y;
if (dest_col < patch_width && dest_row < patch_height) {
for (unsigned int b = blockIdx.z; b < num_colors * num_images; b += gridDim.z) {
int color = b % num_colors;
int image_id = b / num_colors;
int source_row = int(height_offset[image_id]) + dest_row;
int source_col = int(width_offset[image_id]) + dest_col;
source_col = (flip[image_id] > 0.5) ? (img_width - source_col - 1) : source_col;
unsigned long source_index = source_col + img_width * (source_row + img_height * (color + num_colors * image_id));
unsigned long dest_index = dest_col + patch_width * (dest_row + patch_height * (color + num_colors * image_id));
__syncthreads();
patches[dest_index] = images[source_index];
}
}
} | .text
.file "kExtractPatches3.hip"
.globl _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii # -- Begin function _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.p2align 4, 0x90
.type _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii,@function
_Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii: # @_Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16kExtractPatches3PfS_S_S_S_iiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii, .Lfunc_end0-_Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kExtractPatches3PfS_S_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kExtractPatches3PfS_S_S_S_iiiiii,@object # @_Z16kExtractPatches3PfS_S_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z16kExtractPatches3PfS_S_S_S_iiiiii
.p2align 3, 0x0
_Z16kExtractPatches3PfS_S_S_S_iiiiii:
.quad _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.size _Z16kExtractPatches3PfS_S_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16kExtractPatches3PfS_S_S_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kExtractPatches3PfS_S_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16kExtractPatches3PfS_S_S_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x198], PT ; /* 0x0000660000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x194], P0 ; /* 0x0000650002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ S2UR UR4, SR_CTAID.Z ; /* 0x00000000000479c3 */
/* 0x000e220000002700 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff037624 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fca00078e02ff */
/*00d0*/ ISETP.LE.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x001fda000bf03070 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ I2F.U32.RP R8, c[0x0][0x19c] ; /* 0x0000670000087b06 */
/* 0x000e220000209000 */
/*0100*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x19c], PT ; /* 0x00006700ff007a0c */
/* 0x000fe20003f05070 */
/*0110*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0170*/ IADD3 R5, RZ, -R7, RZ ; /* 0x80000007ff057210 */
/* 0x002fca0007ffe0ff */
/*0180*/ IMAD R5, R5, c[0x0][0x19c], RZ ; /* 0x0000670005057a24 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fe200078e0006 */
/*01a0*/ LOP3.LUT R5, RZ, c[0x0][0x19c], RZ, 0x33, !PT ; /* 0x00006700ff057a12 */
/* 0x000fca00078e33ff */
/*01b0*/ IMAD.HI.U32 R8, R7, R4, RZ ; /* 0x0000000407087227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x001fc800078e0a08 */
/*01d0*/ IMAD R6, R9, c[0x0][0x19c], R4 ; /* 0x0000670009067a24 */
/* 0x000fca00078e0204 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x19c], PT ; /* 0x0000670006007a0c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R6, R6, -c[0x0][0x19c], RZ ; /* 0x8000670006061a10 */
/* 0x000fe40007ffe0ff */
/*0200*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x19c], PT ; /* 0x0000670006007a0c */
/* 0x000fe40003f46070 */
/*0220*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fd60000000f00 */
/*0230*/ @P2 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108082810 */
/* 0x000fc80007ffe0ff */
/*0240*/ SEL R15, R5, R8, !P0 ; /* 0x00000008050f7207 */
/* 0x000fca0004000000 */
/*0250*/ IMAD.WIDE R10, R15, R6, c[0x0][0x170] ; /* 0x00005c000f0a7625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R8, R15.reuse, R6.reuse, c[0x0][0x178] ; /* 0x00005e000f087625 */
/* 0x0c0fe400078e0206 */
/*0270*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE R12, R15, R6, c[0x0][0x180] ; /* 0x000060000f0c7625 */
/* 0x000fe400078e0206 */
/*0290*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.MOV R21, RZ, RZ, -R15 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0a0f */
/*02c0*/ IMAD R14, R21, c[0x0][0x19c], R4 ; /* 0x00006700150e7a24 */
/* 0x000fc800078e0204 */
/*02d0*/ IMAD R14, R15, c[0x0][0x19c], R14 ; /* 0x000067000f0e7a24 */
/* 0x000fe200078e020e */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ F2I.TRUNC.NTZ R19, R10 ; /* 0x0000000a00137305 */
/* 0x004e30000020f100 */
/*0300*/ F2I.TRUNC.NTZ R17, R8 ; /* 0x0000000800117305 */
/* 0x008e62000020f100 */
/*0310*/ FSETP.GT.AND P1, PT, R12, 0.5, PT ; /* 0x3f0000000c00780b */
/* 0x010fc40003f24000 */
/*0320*/ IADD3 R19, R2, R19, RZ ; /* 0x0000001302137210 */
/* 0x001fc80007ffe0ff */
/*0330*/ LOP3.LUT R11, RZ, R19, RZ, 0x33, !PT ; /* 0x00000013ff0b7212 */
/* 0x000fe400078e33ff */
/*0340*/ IADD3 R17, R0, R17, RZ ; /* 0x0000001100117210 */
/* 0x002fca0007ffe0ff */
/*0350*/ @P1 IADD3 R19, R11, c[0x0][0x18c], RZ ; /* 0x000063000b131a10 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD R12, R14, c[0x0][0x190], R17 ; /* 0x000064000e0c7a24 */
/* 0x000fc800078e0211 */
/*0370*/ IMAD R9, R12, c[0x0][0x18c], R19 ; /* 0x000063000c097a24 */
/* 0x000fc800078e0213 */
/*0380*/ IMAD.WIDE R8, R9, R6, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fcc00078e0206 */
/*0390*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IADD3 R4, R4, c[0x0][0x14], RZ ; /* 0x0000050004047a10 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD R11, R14, c[0x0][0x198], R0 ; /* 0x000066000e0b7a24 */
/* 0x000fc600078e0200 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fe20003f26070 */
/*03d0*/ IMAD R11, R11, c[0x0][0x194], R2 ; /* 0x000065000b0b7a24 */
/* 0x000fc800078e0202 */
/*03e0*/ IMAD.WIDE R10, R11, R6, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fca00078e0206 */
/*03f0*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0041e6000c101904 */
/*0400*/ @!P1 BRA 0x1b0 ; /* 0xfffffda000009947 */
/* 0x000fea000383ffff */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kExtractPatches3PfS_S_S_S_iiiiii
.globl _Z16kExtractPatches3PfS_S_S_S_iiiiii
.p2align 8
.type _Z16kExtractPatches3PfS_S_S_S_iiiiii,@function
_Z16kExtractPatches3PfS_S_S_S_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b64 s[16:17], s[0:1], 0x34
s_add_u32 s4, s0, 64
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s19, s13, s3
s_mul_i32 s18, s14, s2
v_add_nc_u32_e32 v2, s19, v1
v_add_nc_u32_e32 v0, s18, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s16, v2
v_cmp_gt_i32_e64 s2, s17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s12, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s15, s13
s_cbranch_scc1 .LBB0_4
s_load_b32 s14, s[4:5], 0x8
s_load_b64 s[8:9], s[0:1], 0x2c
v_cvt_f32_u32_e32 v0, s12
s_mul_i32 s2, s15, s17
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v3, s18, s2, v4
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b256 s[0:7], s[0:1], 0x0
v_rcp_iflag_f32_e32 v0, v0
v_mul_lo_u32 v3, s16, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v0
v_add3_u32 v0, v1, v3, s19
s_waitcnt lgkmcnt(0)
s_mul_i32 s17, s14, s17
s_mul_i32 s19, s15, s9
v_cvt_u32_f32_e32 v3, v5
v_add3_u32 v4, s18, s19, v4
v_mov_b32_e32 v5, 0
s_mul_i32 s16, s17, s16
s_mul_i32 s9, s14, s9
s_sub_i32 s17, 0, s12
.LBB0_3:
v_readfirstlane_b32 s18, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s19, s17, s18
s_mul_hi_u32 s19, s18, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s18, s18, s19
s_mul_hi_u32 s18, s15, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_not_b32 s20, s18
s_mul_i32 s19, s17, s18
s_mul_i32 s20, s12, s20
s_add_i32 s19, s15, s19
s_add_i32 s21, s18, 1
s_add_i32 s20, s15, s20
s_cmp_ge_u32 s19, s12
s_cselect_b32 s18, s21, s18
s_cselect_b32 s19, s20, s19
s_add_i32 s20, s18, 1
s_cmp_ge_u32 s19, s12
s_cselect_b32 s18, s20, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s6, s18
s_addc_u32 s21, s7, s19
s_add_u32 s22, s4, s18
s_addc_u32 s23, s5, s19
s_clause 0x1
global_load_b32 v1, v5, s[20:21]
global_load_b32 v6, v5, s[22:23]
s_add_u32 s18, s10, s18
s_addc_u32 s19, s11, s19
s_add_i32 s15, s15, s14
global_load_b32 v7, v5, s[18:19]
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cmp_lt_u32 s15, s13
v_cvt_i32_f32_e32 v1, v1
v_cvt_i32_f32_e32 v6, v6
v_cmp_lt_f32_e32 vcc_lo, 0.5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v2, v6
v_add_nc_u32_e32 v9, v4, v1
v_add_nc_u32_e32 v4, s9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v8, v6, -1, s8
v_cndmask_b32_e32 v1, v6, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v9, s8, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s16, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kExtractPatches3PfS_S_S_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kExtractPatches3PfS_S_S_S_iiiiii, .Lfunc_end0-_Z16kExtractPatches3PfS_S_S_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kExtractPatches3PfS_S_S_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z16kExtractPatches3PfS_S_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007012a_00000000-6_kExtractPatches3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.type _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kExtractPatches3PfS_S_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.globl _Z16kExtractPatches3PfS_S_S_S_iiiiii
.type _Z16kExtractPatches3PfS_S_S_S_iiiiii, @function
_Z16kExtractPatches3PfS_S_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z16kExtractPatches3PfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16kExtractPatches3PfS_S_S_S_iiiiii, .-_Z16kExtractPatches3PfS_S_S_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16kExtractPatches3PfS_S_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kExtractPatches3PfS_S_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kExtractPatches3.hip"
.globl _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii # -- Begin function _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.p2align 4, 0x90
.type _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii,@function
_Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii: # @_Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16kExtractPatches3PfS_S_S_S_iiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii, .Lfunc_end0-_Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kExtractPatches3PfS_S_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kExtractPatches3PfS_S_S_S_iiiiii,@object # @_Z16kExtractPatches3PfS_S_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z16kExtractPatches3PfS_S_S_S_iiiiii
.p2align 3, 0x0
_Z16kExtractPatches3PfS_S_S_S_iiiiii:
.quad _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.size _Z16kExtractPatches3PfS_S_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16kExtractPatches3PfS_S_S_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kExtractPatches3PfS_S_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kExtractPatches3PfS_S_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda_runtime.h>
#include<stdio.h>
int main()
{
int num = 0;
int maxdev = 0;
cudaGetDeviceCount(&num);
if (num > 1)
{
int maxp = 0;
for (int i = 0; i < num; i++)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
if (maxp < props.multiProcessorCount)
{
maxp = props.multiProcessorCount;
maxdev = i;
}
}
cudaSetDevice(maxdev);
}
printf("dev idx: %d\n", maxdev);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda_runtime.h>
#include<stdio.h>
int main()
{
int num = 0;
int maxdev = 0;
cudaGetDeviceCount(&num);
if (num > 1)
{
int maxp = 0;
for (int i = 0; i < num; i++)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
if (maxp < props.multiProcessorCount)
{
maxp = props.multiProcessorCount;
maxdev = i;
}
}
cudaSetDevice(maxdev);
}
printf("dev idx: %d\n", maxdev);
} | .file "tmpxft_000fb95d_00000000-6_gpu_select.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "dev idx: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl $0, %r12d
cmpl $1, 12(%rsp)
jle .L4
movl $0, %ebx
movl $0, %ebp
leaq 16(%rsp), %r13
jmp .L6
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L12
.L6:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 404(%rsp), %eax
cmpl %ebp, %eax
jle .L5
movl %eax, %ebp
movl %ebx, %r12d
jmp .L5
.L12:
movl %r12d, %edi
call cudaSetDevice@PLT
.L4:
movl %r12d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L13
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda_runtime.h>
#include<stdio.h>
int main()
{
int num = 0;
int maxdev = 0;
cudaGetDeviceCount(&num);
if (num > 1)
{
int maxp = 0;
for (int i = 0; i < num; i++)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
if (maxp < props.multiProcessorCount)
{
maxp = props.multiProcessorCount;
maxdev = i;
}
}
cudaSetDevice(maxdev);
}
printf("dev idx: %d\n", maxdev);
} | #include<hip/hip_runtime.h>
#include<stdio.h>
int main()
{
int num = 0;
int maxdev = 0;
hipGetDeviceCount(&num);
if (num > 1)
{
int maxp = 0;
for (int i = 0; i < num; i++)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
if (maxp < props.multiProcessorCount)
{
maxp = props.multiProcessorCount;
maxdev = i;
}
}
hipSetDevice(maxdev);
}
printf("dev idx: %d\n", maxdev);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
int main()
{
int num = 0;
int maxdev = 0;
hipGetDeviceCount(&num);
if (num > 1)
{
int maxp = 0;
for (int i = 0; i < num; i++)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
if (maxp < props.multiProcessorCount)
{
maxp = props.multiProcessorCount;
maxdev = i;
}
}
hipSetDevice(maxdev);
}
printf("dev idx: %d\n", maxdev);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
int main()
{
int num = 0;
int maxdev = 0;
hipGetDeviceCount(&num);
if (num > 1)
{
int maxp = 0;
for (int i = 0; i < num; i++)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
if (maxp < props.multiProcessorCount)
{
maxp = props.multiProcessorCount;
maxdev = i;
}
}
hipSetDevice(maxdev);
}
printf("dev idx: %d\n", maxdev);
} | .text
.file "gpu_select.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
xorl %ebx, %ebx
cmpl $2, 4(%rsp)
jl .LBB0_4
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_2
# %bb.5: # %.lr.ph
xorl %ebp, %ebp
leaq 8(%rsp), %r14
xorl %r15d, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 396(%rsp), %eax
cmpl %eax, %r15d
cmovll %ebp, %ebx
cmovlel %eax, %r15d
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_6
jmp .LBB0_3
.LBB0_2:
xorl %ebx, %ebx
.LBB0_3: # %._crit_edge
movl %ebx, %edi
callq hipSetDevice
.LBB0_4:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "dev idx: %d\n"
.size .L.str, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fb95d_00000000-6_gpu_select.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "dev idx: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl $0, %r12d
cmpl $1, 12(%rsp)
jle .L4
movl $0, %ebx
movl $0, %ebp
leaq 16(%rsp), %r13
jmp .L6
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L12
.L6:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 404(%rsp), %eax
cmpl %ebp, %eax
jle .L5
movl %eax, %ebp
movl %ebx, %r12d
jmp .L5
.L12:
movl %r12d, %edi
call cudaSetDevice@PLT
.L4:
movl %r12d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L13
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_select.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
xorl %ebx, %ebx
cmpl $2, 4(%rsp)
jl .LBB0_4
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_2
# %bb.5: # %.lr.ph
xorl %ebp, %ebp
leaq 8(%rsp), %r14
xorl %r15d, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 396(%rsp), %eax
cmpl %eax, %r15d
cmovll %ebp, %ebx
cmovlel %eax, %r15d
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_6
jmp .LBB0_3
.LBB0_2:
xorl %ebx, %ebx
.LBB0_3: # %._crit_edge
movl %ebx, %edi
callq hipSetDevice
.LBB0_4:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "dev idx: %d\n"
.size .L.str, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "gpuMemoryLimitTester.cuh"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
std::fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void populateArrayWithRandomNumbers(int *array, int size)
{
for (int i = 0; i < size; i++)
{
array[i] = rand();
}
};
void checkGpuMemoryLimit()
{
int memoryAmount =30000;
//int memoryIncrement=1000;
int* host_array;
int* device_array;
host_array = (int *)malloc(3000 * sizeof(int));
populateArrayWithRandomNumbers(host_array, 3000);
for (int i = 0; i < 300000; i++)
{
std::cout << "Attempting to allocate gpu memory size of: " << memoryAmount << std::endl;
gpuErrchk(cudaMalloc((void**)&device_array, memoryAmount*sizeof(int)));
//host_array = (int *)malloc(3000*sizeof(int));
//populateArrayWithRandomNumbers(host_array, 3000);
cudaDeviceSynchronize();
gpuErrchk(cudaMemcpy(device_array, host_array, 3000 * sizeof(int), cudaMemcpyHostToDevice));
cudaDeviceSynchronize();
gpuErrchk(cudaFree(device_array));
std::cout << "Succesfully copied data to a: " << memoryAmount << " gpu array" << std::endl << std::endl;
memoryAmount = memoryAmount * 2;//+ memoryIncrement;
}
}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "gpuMemoryLimitTester.cuh"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
std::fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void populateArrayWithRandomNumbers(int *array, int size)
{
for (int i = 0; i < size; i++)
{
array[i] = rand();
}
};
void checkGpuMemoryLimit()
{
int memoryAmount =30000;
//int memoryIncrement=1000;
int* host_array;
int* device_array;
host_array = (int *)malloc(3000 * sizeof(int));
populateArrayWithRandomNumbers(host_array, 3000);
for (int i = 0; i < 300000; i++)
{
std::cout << "Attempting to allocate gpu memory size of: " << memoryAmount << std::endl;
gpuErrchk(cudaMalloc((void**)&device_array, memoryAmount*sizeof(int)));
//host_array = (int *)malloc(3000*sizeof(int));
//populateArrayWithRandomNumbers(host_array, 3000);
cudaDeviceSynchronize();
gpuErrchk(cudaMemcpy(device_array, host_array, 3000 * sizeof(int), cudaMemcpyHostToDevice));
cudaDeviceSynchronize();
gpuErrchk(cudaFree(device_array));
std::cout << "Succesfully copied data to a: " << memoryAmount << " gpu array" << std::endl << std::endl;
memoryAmount = memoryAmount * 2;//+ memoryIncrement;
}
}; | .file "tmpxft_00058774_00000000-6_gpuMemoryLimitTester.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30populateArrayWithRandomNumbersPii
.type _Z30populateArrayWithRandomNumbersPii, @function
_Z30populateArrayWithRandomNumbersPii:
.LFB4033:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE4033:
.size _Z30populateArrayWithRandomNumbersPii, .-_Z30populateArrayWithRandomNumbersPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Attempting to allocate gpu memory size of: "
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/JoshuaSelvan/pdbProcessingResources/master/CPUandGpuRangeSearch/gpuMemoryLimitTester.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Succesfully copied data to a: "
.section .rodata.str1.1
.LC4:
.string " gpu array"
.text
.globl _Z19checkGpuMemoryLimitv
.type _Z19checkGpuMemoryLimitv, @function
_Z19checkGpuMemoryLimitv:
.LFB4034:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $12000, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $3000, %esi
movq %rax, %rdi
call _Z30populateArrayWithRandomNumbersPii
movl $300000, 12(%rsp)
movl $30000, %r12d
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %r13
leaq 16(%rsp), %r15
.L27:
movl $43, %edx
movq %r14, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L31
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movslq %r12d, %rsi
salq $2, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
call cudaDeviceSynchronize@PLT
movl $1, %ecx
movl $12000, %edx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
movl $30, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $10, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L35
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L36
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %esi
.L26:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl %r12d, %r12d
subl $1, 12(%rsp)
jne .L27
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L38
call _ZSt16__throw_bad_castv@PLT
.L38:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $39, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $43, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $47, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L35:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L39
call _ZSt16__throw_bad_castv@PLT
.L39:
call __stack_chk_fail@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L36:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L40
call _ZSt16__throw_bad_castv@PLT
.L40:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z19checkGpuMemoryLimitv, .-_Z19checkGpuMemoryLimitv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "gpuMemoryLimitTester.cuh"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
std::fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void populateArrayWithRandomNumbers(int *array, int size)
{
for (int i = 0; i < size; i++)
{
array[i] = rand();
}
};
void checkGpuMemoryLimit()
{
int memoryAmount =30000;
//int memoryIncrement=1000;
int* host_array;
int* device_array;
host_array = (int *)malloc(3000 * sizeof(int));
populateArrayWithRandomNumbers(host_array, 3000);
for (int i = 0; i < 300000; i++)
{
std::cout << "Attempting to allocate gpu memory size of: " << memoryAmount << std::endl;
gpuErrchk(cudaMalloc((void**)&device_array, memoryAmount*sizeof(int)));
//host_array = (int *)malloc(3000*sizeof(int));
//populateArrayWithRandomNumbers(host_array, 3000);
cudaDeviceSynchronize();
gpuErrchk(cudaMemcpy(device_array, host_array, 3000 * sizeof(int), cudaMemcpyHostToDevice));
cudaDeviceSynchronize();
gpuErrchk(cudaFree(device_array));
std::cout << "Succesfully copied data to a: " << memoryAmount << " gpu array" << std::endl << std::endl;
memoryAmount = memoryAmount * 2;//+ memoryIncrement;
}
}; | #ifndef GPUMEMORYTESTER
#define GPUMEMORYTESTER
#include "hip/hip_runtime.h"
#include <string>
#include <vector>
#include <iostream>
#include <cstdio>
void checkGpuMemoryLimit();
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef GPUMEMORYTESTER
#define GPUMEMORYTESTER
#include "hip/hip_runtime.h"
#include <string>
#include <vector>
#include <iostream>
#include <cstdio>
void checkGpuMemoryLimit();
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef GPUMEMORYTESTER
#define GPUMEMORYTESTER
#include "hip/hip_runtime.h"
#include <string>
#include <vector>
#include <iostream>
#include <cstdio>
void checkGpuMemoryLimit();
#endif | .text
.file "gpuMemoryLimitTester.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058774_00000000-6_gpuMemoryLimitTester.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30populateArrayWithRandomNumbersPii
.type _Z30populateArrayWithRandomNumbersPii, @function
_Z30populateArrayWithRandomNumbersPii:
.LFB4033:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE4033:
.size _Z30populateArrayWithRandomNumbersPii, .-_Z30populateArrayWithRandomNumbersPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Attempting to allocate gpu memory size of: "
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/JoshuaSelvan/pdbProcessingResources/master/CPUandGpuRangeSearch/gpuMemoryLimitTester.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Succesfully copied data to a: "
.section .rodata.str1.1
.LC4:
.string " gpu array"
.text
.globl _Z19checkGpuMemoryLimitv
.type _Z19checkGpuMemoryLimitv, @function
_Z19checkGpuMemoryLimitv:
.LFB4034:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $12000, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $3000, %esi
movq %rax, %rdi
call _Z30populateArrayWithRandomNumbersPii
movl $300000, 12(%rsp)
movl $30000, %r12d
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %r13
leaq 16(%rsp), %r15
.L27:
movl $43, %edx
movq %r14, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L31
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movslq %r12d, %rsi
salq $2, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
call cudaDeviceSynchronize@PLT
movl $1, %ecx
movl $12000, %edx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
movl $30, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $10, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L35
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L36
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %esi
.L26:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl %r12d, %r12d
subl $1, 12(%rsp)
jne .L27
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L38
call _ZSt16__throw_bad_castv@PLT
.L38:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $39, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $43, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $47, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L35:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L39
call _ZSt16__throw_bad_castv@PLT
.L39:
call __stack_chk_fail@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L36:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L40
call _ZSt16__throw_bad_castv@PLT
.L40:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z19checkGpuMemoryLimitv, .-_Z19checkGpuMemoryLimitv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpuMemoryLimitTester.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include <cuda.h>
#define RANDOM(x) (rand() % x)
#define MAX 100000
#define BLOCKSIZE 16
__global__ void multiply(const int *a, const int *b, int *c, int n) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int k;
int sum = 0;
if (row < n && col < n) {
for (k = 0; k < n; k++) {
sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = sum;
}
}
int main(int argc, char **argv) {
int n = 512;
int i, j, k;
timeval start, finish;
if (argc == 2) {
n = atoi(argv[1]);
}
int *host_a = (int *)malloc(sizeof(int) * n * n);
int *host_b = (int *)malloc(sizeof(int) * n * n);
int *host_c = (int *)malloc(sizeof(int) * n * n);
int *host_c2 = (int *)malloc(sizeof(int) * n * n);
srand(time(NULL));
for (i = 0; i < n * n; i++) {
host_a[i] = RANDOM(MAX);
host_b[i] = RANDOM(MAX);
}
cudaError_t error = cudaSuccess;
int *device_a, *device_b, *device_c;
error = cudaMalloc((void **)&device_a, sizeof(int) * n * n);
error = cudaMalloc((void **)&device_b, sizeof(int) * n * n);
error = cudaMalloc((void **)&device_c, sizeof(int) * n * n);
if (error != cudaSuccess) {
printf("Fail to cudaMalloc on GPU");
return 1;
}
//GPU parallel start
gettimeofday(&start, 0);
cudaMemcpy(device_a, host_a, sizeof(int) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, sizeof(int) * n * n, cudaMemcpyHostToDevice);
double num = ceil(pow((double)n,2) / pow((double)BLOCKSIZE, 2));
int gridsize = (int)ceil(sqrt(num));
dim3 dimBlock(BLOCKSIZE, BLOCKSIZE, 1);
dim3 dimGrid(gridsize, gridsize, 1);
multiply<<<dimGrid, dimBlock>>>(device_a, device_b, device_c, n);
cudaThreadSynchronize();
cudaMemcpy(host_c, device_c, sizeof(int) * n * n, cudaMemcpyDeviceToHost);
gettimeofday(&finish, 0);
double t1 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t1 / 1000);
//GPU parallel finish
//CPU serial start
gettimeofday(&start, 0);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
host_c2[i * n + j] = 0;
for (k = 0; k < n; k++) {
host_c2[i * n + j] += host_a[i * n + k] * host_b[k * n + j];
}
}
}
gettimeofday(&finish, 0);
double t2 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t2 / 1000);
//CPU serial start
printf("加速比：%lf\n", t2 / t1);
//check
int errorNum = 0;
for (int i = 0; i < n * n; i++) {
if (host_c[i] != host_c2[i]) {
errorNum ++;
printf("Error occurs at index: %d: c = %d, c2 = %d\n", i, host_c[i], host_c2[i]);
}
}
if (errorNum == 0) {
printf("Successfully run on GPU and CPU!\n");
} else {
printf("%d error(s) occurs!\n", errorNum);
}
free(host_a);
free(host_b);
free(host_c);
free(host_c2);
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | code for sm_80
Function : _Z8multiplyPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include <cuda.h>
#define RANDOM(x) (rand() % x)
#define MAX 100000
#define BLOCKSIZE 16
__global__ void multiply(const int *a, const int *b, int *c, int n) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int k;
int sum = 0;
if (row < n && col < n) {
for (k = 0; k < n; k++) {
sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = sum;
}
}
int main(int argc, char **argv) {
int n = 512;
int i, j, k;
timeval start, finish;
if (argc == 2) {
n = atoi(argv[1]);
}
int *host_a = (int *)malloc(sizeof(int) * n * n);
int *host_b = (int *)malloc(sizeof(int) * n * n);
int *host_c = (int *)malloc(sizeof(int) * n * n);
int *host_c2 = (int *)malloc(sizeof(int) * n * n);
srand(time(NULL));
for (i = 0; i < n * n; i++) {
host_a[i] = RANDOM(MAX);
host_b[i] = RANDOM(MAX);
}
cudaError_t error = cudaSuccess;
int *device_a, *device_b, *device_c;
error = cudaMalloc((void **)&device_a, sizeof(int) * n * n);
error = cudaMalloc((void **)&device_b, sizeof(int) * n * n);
error = cudaMalloc((void **)&device_c, sizeof(int) * n * n);
if (error != cudaSuccess) {
printf("Fail to cudaMalloc on GPU");
return 1;
}
//GPU parallel start
gettimeofday(&start, 0);
cudaMemcpy(device_a, host_a, sizeof(int) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, sizeof(int) * n * n, cudaMemcpyHostToDevice);
double num = ceil(pow((double)n,2) / pow((double)BLOCKSIZE, 2));
int gridsize = (int)ceil(sqrt(num));
dim3 dimBlock(BLOCKSIZE, BLOCKSIZE, 1);
dim3 dimGrid(gridsize, gridsize, 1);
multiply<<<dimGrid, dimBlock>>>(device_a, device_b, device_c, n);
cudaThreadSynchronize();
cudaMemcpy(host_c, device_c, sizeof(int) * n * n, cudaMemcpyDeviceToHost);
gettimeofday(&finish, 0);
double t1 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t1 / 1000);
//GPU parallel finish
//CPU serial start
gettimeofday(&start, 0);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
host_c2[i * n + j] = 0;
for (k = 0; k < n; k++) {
host_c2[i * n + j] += host_a[i * n + k] * host_b[k * n + j];
}
}
}
gettimeofday(&finish, 0);
double t2 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t2 / 1000);
//CPU serial start
printf("加速比：%lf\n", t2 / t1);
//check
int errorNum = 0;
for (int i = 0; i < n * n; i++) {
if (host_c[i] != host_c2[i]) {
errorNum ++;
printf("Error occurs at index: %d: c = %d, c2 = %d\n", i, host_c[i], host_c2[i]);
}
}
if (errorNum == 0) {
printf("Successfully run on GPU and CPU!\n");
} else {
printf("%d error(s) occurs!\n", errorNum);
}
free(host_a);
free(host_b);
free(host_c);
free(host_c2);
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | .file "tmpxft_00056c07_00000000-6_Matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
.type _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii, @function
_Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii, .-_Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
.globl _Z8multiplyPKiS0_Pii
.type _Z8multiplyPKiS0_Pii, @function
_Z8multiplyPKiS0_Pii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8multiplyPKiS0_Pii, .-_Z8multiplyPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Fail to cudaMalloc on GPU"
.LC3:
.string "%lf ms\n"
.LC4:
.string "\345\212\240\351\200\237\346\257\224\357\274\232%lf\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Error occurs at index: %d: c = %d, c2 = %d\n"
.align 8
.LC6:
.string "Successfully run on GPU and CPU!\n"
.section .rodata.str1.1
.LC7:
.string "%d error(s) occurs!\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L36
movl $1048576, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $1048576, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $1048576, %edi
call malloc@PLT
movq %rax, %r15
movl $1048576, %edi
call malloc@PLT
movq %rax, 32(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $262144, 28(%rsp)
movl $512, %ebp
movq $1048576, (%rsp)
movl $512, %ebx
.L29:
movq 16(%rsp), %rdx
movq %rdx, %r12
movq 8(%rsp), %r13
movslq 28(%rsp), %rax
leaq (%rdx,%rax,4), %r14
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $351843721, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100000, %edx, %edx
subl %edx, %eax
movl %eax, (%r12)
call rand@PLT
movslq %eax, %rdx
imulq $351843721, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13)
addq $4, %r12
addq $4, %r13
cmpq %r14, %r12
jne .L14
.L13:
leaq 48(%rsp), %rdi
movq (%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq (%rsp), %r14
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
call ceil@PLT
call sqrt@PLT
call ceil@PLT
movl $16, 72(%rsp)
movl $16, 76(%rsp)
movl $1, 80(%rsp)
cvttsd2sil %xmm0, %eax
movl %eax, 84(%rsp)
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movl $1, %ecx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L17:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq (%rsp), %rdx
movq 64(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd %xmm1, 40(%rsp)
divsd .LC2(%rip), %xmm1
movapd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebp, %ebp
jle .L18
salq $2, %rbx
movq 16(%rsp), %rax
movq %rax, %r12
leaq (%rbx,%rax), %rdi
movq 32(%rsp), %rax
movl $0, %ecx
movl $0, %r13d
movq %r15, %rdx
jmp .L19
.L36:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebp
movslq %eax, %rbx
movq %rbx, %r15
imulq %rbx, %r15
leaq 0(,%r15,4), %r14
movq %r14, (%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
movq %r14, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %r12d, %eax
imull %r12d, %eax
movl %eax, 28(%rsp)
testl %eax, %eax
jle .L13
jmp .L29
.L37:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L38:
movl %ebp, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
jmp .L17
.L31:
movl %ecx, %r14d
.L21:
movq %r10, %r15
movq %r11, %r8
movq %r12, %rcx
movl $0, %r9d
.L20:
movl (%rcx), %esi
imull (%r8), %esi
addl %esi, %r9d
addq $4, %rcx
addq %rbx, %r8
cmpq %rdi, %rcx
jne .L20
movl %r9d, (%r15)
leal 1(%r14), %ecx
addq $4, %r10
addq $4, %r11
cmpl %ebp, %ecx
jne .L31
movl (%rsp), %ecx
leal 1(%rcx), %r8d
addq %rbx, %r12
addq %rbx, %rdi
addq %rbx, %rax
cmpl %r14d, %ecx
je .L22
movl %r8d, %ecx
.L19:
movq 8(%rsp), %r11
movq %rax, %r10
movl %r13d, %r14d
movl %ecx, (%rsp)
jmp .L21
.L18:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
movapd %xmm2, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
divsd 40(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 28(%rsp)
jg .L28
.L23:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L27:
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
addq $1, %rbx
cmpq %rbx, %rbp
je .L40
.L25:
movl (%r15,%rbx,4), %ecx
movl (%r14,%rbx,4), %r8d
cmpl %r8d, %ecx
je .L24
addl $1, %r13d
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L40:
testl %r13d, %r13d
je .L23
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L22:
movq %rdx, %r15
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movq %xmm4, %rbx
movapd %xmm4, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
divsd 40(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L28:
movslq 28(%rsp), %rbp
movl $0, %ebx
movl $0, %r13d
leaq .LC5(%rip), %r12
movq 32(%rsp), %r14
jmp .L25
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8multiplyPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1064304640
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include <cuda.h>
#define RANDOM(x) (rand() % x)
#define MAX 100000
#define BLOCKSIZE 16
__global__ void multiply(const int *a, const int *b, int *c, int n) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int k;
int sum = 0;
if (row < n && col < n) {
for (k = 0; k < n; k++) {
sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = sum;
}
}
int main(int argc, char **argv) {
int n = 512;
int i, j, k;
timeval start, finish;
if (argc == 2) {
n = atoi(argv[1]);
}
int *host_a = (int *)malloc(sizeof(int) * n * n);
int *host_b = (int *)malloc(sizeof(int) * n * n);
int *host_c = (int *)malloc(sizeof(int) * n * n);
int *host_c2 = (int *)malloc(sizeof(int) * n * n);
srand(time(NULL));
for (i = 0; i < n * n; i++) {
host_a[i] = RANDOM(MAX);
host_b[i] = RANDOM(MAX);
}
cudaError_t error = cudaSuccess;
int *device_a, *device_b, *device_c;
error = cudaMalloc((void **)&device_a, sizeof(int) * n * n);
error = cudaMalloc((void **)&device_b, sizeof(int) * n * n);
error = cudaMalloc((void **)&device_c, sizeof(int) * n * n);
if (error != cudaSuccess) {
printf("Fail to cudaMalloc on GPU");
return 1;
}
//GPU parallel start
gettimeofday(&start, 0);
cudaMemcpy(device_a, host_a, sizeof(int) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, sizeof(int) * n * n, cudaMemcpyHostToDevice);
double num = ceil(pow((double)n,2) / pow((double)BLOCKSIZE, 2));
int gridsize = (int)ceil(sqrt(num));
dim3 dimBlock(BLOCKSIZE, BLOCKSIZE, 1);
dim3 dimGrid(gridsize, gridsize, 1);
multiply<<<dimGrid, dimBlock>>>(device_a, device_b, device_c, n);
cudaThreadSynchronize();
cudaMemcpy(host_c, device_c, sizeof(int) * n * n, cudaMemcpyDeviceToHost);
gettimeofday(&finish, 0);
double t1 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t1 / 1000);
//GPU parallel finish
//CPU serial start
gettimeofday(&start, 0);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
host_c2[i * n + j] = 0;
for (k = 0; k < n; k++) {
host_c2[i * n + j] += host_a[i * n + k] * host_b[k * n + j];
}
}
}
gettimeofday(&finish, 0);
double t2 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t2 / 1000);
//CPU serial start
printf("加速比：%lf\n", t2 / t1);
//check
int errorNum = 0;
for (int i = 0; i < n * n; i++) {
if (host_c[i] != host_c2[i]) {
errorNum ++;
printf("Error occurs at index: %d: c = %d, c2 = %d\n", i, host_c[i], host_c2[i]);
}
}
if (errorNum == 0) {
printf("Successfully run on GPU and CPU!\n");
} else {
printf("%d error(s) occurs!\n", errorNum);
}
free(host_a);
free(host_b);
free(host_c);
free(host_c2);
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#define RANDOM(x) (rand() % x)
#define MAX 100000
#define BLOCKSIZE 16
__global__ void multiply(const int *a, const int *b, int *c, int n) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int k;
int sum = 0;
if (row < n && col < n) {
for (k = 0; k < n; k++) {
sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = sum;
}
}
int main(int argc, char **argv) {
int n = 512;
int i, j, k;
timeval start, finish;
if (argc == 2) {
n = atoi(argv[1]);
}
int *host_a = (int *)malloc(sizeof(int) * n * n);
int *host_b = (int *)malloc(sizeof(int) * n * n);
int *host_c = (int *)malloc(sizeof(int) * n * n);
int *host_c2 = (int *)malloc(sizeof(int) * n * n);
srand(time(NULL));
for (i = 0; i < n * n; i++) {
host_a[i] = RANDOM(MAX);
host_b[i] = RANDOM(MAX);
}
hipError_t error = hipSuccess;
int *device_a, *device_b, *device_c;
error = hipMalloc((void **)&device_a, sizeof(int) * n * n);
error = hipMalloc((void **)&device_b, sizeof(int) * n * n);
error = hipMalloc((void **)&device_c, sizeof(int) * n * n);
if (error != hipSuccess) {
printf("Fail to hipMalloc on GPU");
return 1;
}
//GPU parallel start
gettimeofday(&start, 0);
hipMemcpy(device_a, host_a, sizeof(int) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, sizeof(int) * n * n, hipMemcpyHostToDevice);
double num = ceil(pow((double)n,2) / pow((double)BLOCKSIZE, 2));
int gridsize = (int)ceil(sqrt(num));
dim3 dimBlock(BLOCKSIZE, BLOCKSIZE, 1);
dim3 dimGrid(gridsize, gridsize, 1);
multiply<<<dimGrid, dimBlock>>>(device_a, device_b, device_c, n);
hipDeviceSynchronize();
hipMemcpy(host_c, device_c, sizeof(int) * n * n, hipMemcpyDeviceToHost);
gettimeofday(&finish, 0);
double t1 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t1 / 1000);
//GPU parallel finish
//CPU serial start
gettimeofday(&start, 0);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
host_c2[i * n + j] = 0;
for (k = 0; k < n; k++) {
host_c2[i * n + j] += host_a[i * n + k] * host_b[k * n + j];
}
}
}
gettimeofday(&finish, 0);
double t2 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t2 / 1000);
//CPU serial start
printf("加速比：%lf\n", t2 / t1);
//check
int errorNum = 0;
for (int i = 0; i < n * n; i++) {
if (host_c[i] != host_c2[i]) {
errorNum ++;
printf("Error occurs at index: %d: c = %d, c2 = %d\n", i, host_c[i], host_c2[i]);
}
}
if (errorNum == 0) {
printf("Successfully run on GPU and CPU!\n");
} else {
printf("%d error(s) occurs!\n", errorNum);
}
free(host_a);
free(host_b);
free(host_c);
free(host_c2);
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#define RANDOM(x) (rand() % x)
#define MAX 100000
#define BLOCKSIZE 16
__global__ void multiply(const int *a, const int *b, int *c, int n) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int k;
int sum = 0;
if (row < n && col < n) {
for (k = 0; k < n; k++) {
sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = sum;
}
}
int main(int argc, char **argv) {
int n = 512;
int i, j, k;
timeval start, finish;
if (argc == 2) {
n = atoi(argv[1]);
}
int *host_a = (int *)malloc(sizeof(int) * n * n);
int *host_b = (int *)malloc(sizeof(int) * n * n);
int *host_c = (int *)malloc(sizeof(int) * n * n);
int *host_c2 = (int *)malloc(sizeof(int) * n * n);
srand(time(NULL));
for (i = 0; i < n * n; i++) {
host_a[i] = RANDOM(MAX);
host_b[i] = RANDOM(MAX);
}
hipError_t error = hipSuccess;
int *device_a, *device_b, *device_c;
error = hipMalloc((void **)&device_a, sizeof(int) * n * n);
error = hipMalloc((void **)&device_b, sizeof(int) * n * n);
error = hipMalloc((void **)&device_c, sizeof(int) * n * n);
if (error != hipSuccess) {
printf("Fail to hipMalloc on GPU");
return 1;
}
//GPU parallel start
gettimeofday(&start, 0);
hipMemcpy(device_a, host_a, sizeof(int) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, sizeof(int) * n * n, hipMemcpyHostToDevice);
double num = ceil(pow((double)n,2) / pow((double)BLOCKSIZE, 2));
int gridsize = (int)ceil(sqrt(num));
dim3 dimBlock(BLOCKSIZE, BLOCKSIZE, 1);
dim3 dimGrid(gridsize, gridsize, 1);
multiply<<<dimGrid, dimBlock>>>(device_a, device_b, device_c, n);
hipDeviceSynchronize();
hipMemcpy(host_c, device_c, sizeof(int) * n * n, hipMemcpyDeviceToHost);
gettimeofday(&finish, 0);
double t1 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t1 / 1000);
//GPU parallel finish
//CPU serial start
gettimeofday(&start, 0);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
host_c2[i * n + j] = 0;
for (k = 0; k < n; k++) {
host_c2[i * n + j] += host_a[i * n + k] * host_b[k * n + j];
}
}
}
gettimeofday(&finish, 0);
double t2 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t2 / 1000);
//CPU serial start
printf("加速比：%lf\n", t2 / t1);
//check
int errorNum = 0;
for (int i = 0; i < n * n; i++) {
if (host_c[i] != host_c2[i]) {
errorNum ++;
printf("Error occurs at index: %d: c = %d, c2 = %d\n", i, host_c[i], host_c2[i]);
}
}
if (errorNum == 0) {
printf("Successfully run on GPU and CPU!\n");
} else {
printf("%d error(s) occurs!\n", errorNum);
}
free(host_a);
free(host_b);
free(host_c);
free(host_c2);
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPKiS0_Pii
.globl _Z8multiplyPKiS0_Pii
.p2align 8
.type _Z8multiplyPKiS0_Pii,@function
_Z8multiplyPKiS0_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPKiS0_Pii, .Lfunc_end0-_Z8multiplyPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#define RANDOM(x) (rand() % x)
#define MAX 100000
#define BLOCKSIZE 16
__global__ void multiply(const int *a, const int *b, int *c, int n) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int k;
int sum = 0;
if (row < n && col < n) {
for (k = 0; k < n; k++) {
sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = sum;
}
}
int main(int argc, char **argv) {
int n = 512;
int i, j, k;
timeval start, finish;
if (argc == 2) {
n = atoi(argv[1]);
}
int *host_a = (int *)malloc(sizeof(int) * n * n);
int *host_b = (int *)malloc(sizeof(int) * n * n);
int *host_c = (int *)malloc(sizeof(int) * n * n);
int *host_c2 = (int *)malloc(sizeof(int) * n * n);
srand(time(NULL));
for (i = 0; i < n * n; i++) {
host_a[i] = RANDOM(MAX);
host_b[i] = RANDOM(MAX);
}
hipError_t error = hipSuccess;
int *device_a, *device_b, *device_c;
error = hipMalloc((void **)&device_a, sizeof(int) * n * n);
error = hipMalloc((void **)&device_b, sizeof(int) * n * n);
error = hipMalloc((void **)&device_c, sizeof(int) * n * n);
if (error != hipSuccess) {
printf("Fail to hipMalloc on GPU");
return 1;
}
//GPU parallel start
gettimeofday(&start, 0);
hipMemcpy(device_a, host_a, sizeof(int) * n * n, hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, sizeof(int) * n * n, hipMemcpyHostToDevice);
double num = ceil(pow((double)n,2) / pow((double)BLOCKSIZE, 2));
int gridsize = (int)ceil(sqrt(num));
dim3 dimBlock(BLOCKSIZE, BLOCKSIZE, 1);
dim3 dimGrid(gridsize, gridsize, 1);
multiply<<<dimGrid, dimBlock>>>(device_a, device_b, device_c, n);
hipDeviceSynchronize();
hipMemcpy(host_c, device_c, sizeof(int) * n * n, hipMemcpyDeviceToHost);
gettimeofday(&finish, 0);
double t1 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t1 / 1000);
//GPU parallel finish
//CPU serial start
gettimeofday(&start, 0);
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++) {
host_c2[i * n + j] = 0;
for (k = 0; k < n; k++) {
host_c2[i * n + j] += host_a[i * n + k] * host_b[k * n + j];
}
}
}
gettimeofday(&finish, 0);
double t2 = 1000000 * (finish.tv_sec - start.tv_sec) + finish.tv_usec - start.tv_usec;
printf("%lf ms\n", t2 / 1000);
//CPU serial start
printf("加速比：%lf\n", t2 / t1);
//check
int errorNum = 0;
for (int i = 0; i < n * n; i++) {
if (host_c[i] != host_c2[i]) {
errorNum ++;
printf("Error occurs at index: %d: c = %d, c2 = %d\n", i, host_c[i], host_c2[i]);
}
}
if (errorNum == 0) {
printf("Successfully run on GPU and CPU!\n");
} else {
printf("%d error(s) occurs!\n", errorNum);
}
free(host_a);
free(host_b);
free(host_c);
free(host_c2);
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} | .text
.file "Matrix.hip"
.globl _Z23__device_stub__multiplyPKiS0_Pii # -- Begin function _Z23__device_stub__multiplyPKiS0_Pii
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPKiS0_Pii,@function
_Z23__device_stub__multiplyPKiS0_Pii: # @_Z23__device_stub__multiplyPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPKiS0_Pii, .Lfunc_end0-_Z23__device_stub__multiplyPKiS0_Pii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %eax # imm = 0x200
cmpl $2, %edi
jne .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB1_2:
movq %rax, 8(%rsp) # 8-byte Spill
movslq %eax, %r15
movq %r15, %rbp
imulq %r15, %rbp
shlq $2, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %rbp, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r15d, %eax
imull %eax, %eax
movq %rax, 56(%rsp) # 8-byte Spill
testl %r15d, %r15d
je .LBB1_5
# %bb.3: # %.lr.ph.preheader
movq 56(%rsp), %r15 # 8-byte Reload
cmpl $1, %r15d
# kill: def $r15d killed $r15d killed $r15 def $r15
adcl $0, %r15d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_7
# %bb.6:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %eax
jmp .LBB1_28
.LBB1_7:
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %r15 # 8-byte Reload
cvtsi2sd %r15d, %xmm0
mulsd %xmm0, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_9
# %bb.8:
sqrtsd %xmm0, %xmm0
jmp .LBB1_10
.LBB1_9: # %call.sqrt
callq sqrt
.LBB1_10: # %.split
callq ceil@PLT
cvttsd2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %r15d, 52(%rsp)
leaq 192(%rsp), %rax
movq %rax, 80(%rsp)
leaq 184(%rsp), %rax
movq %rax, 88(%rsp)
leaq 176(%rsp), %rax
movq %rax, 96(%rsp)
leaq 52(%rsp), %rax
movq %rax, 104(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiS0_Pii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %r12, 120(%rsp) # 8-byte Spill
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 88(%rsp), %rax
subq 72(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r15d, %r15d
jle .LBB1_19
# %bb.13: # %.preheader.lr.ph
movl %r15d, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
# Child Loop BB1_16 Depth 3
movl %edx, %edi
leaq (%rbx,%rdi,4), %rdi
movq %rsi, %r8
imulq %rax, %r8
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r8
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_15: # %.lr.ph112
# Parent Loop BB1_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_16 Depth 3
movl $0, (%r8,%r10,4)
xorl %r11d, %r11d
movq %r9, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_14 Depth=1
# Parent Loop BB1_15 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15), %r12d
imull (%rdi,%r11,4), %r12d
addl %r12d, %r13d
incq %r11
addq %rcx, %r15
cmpq %r11, %rax
jne .LBB1_16
# %bb.17: # %._crit_edge113
# in Loop: Header=BB1_15 Depth=2
movl %r13d, (%r8,%r10,4)
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB1_15
# %bb.18: # %._crit_edge117
# in Loop: Header=BB1_14 Depth=1
incq %rsi
movq 8(%rsp), %r15 # 8-byte Reload
addl %r15d, %edx
cmpq %rax, %rsi
jne .LBB1_14
.LBB1_19: # %._crit_edge119
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 88(%rsp), %rax
subq 72(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 112(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.2, %edi
movb $1, %al
callq printf
testl %r15d, %r15d
movq 120(%rsp), %r15 # 8-byte Reload
movq 56(%rsp), %r12 # 8-byte Reload
je .LBB1_24
# %bb.20: # %.lr.ph123.preheader
cmpl $1, %r12d
adcl $0, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_23: # in Loop: Header=BB1_21 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB1_24
.LBB1_21: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %edx
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax,%r13,4), %ecx
cmpl %ecx, %edx
je .LBB1_23
# %bb.22: # in Loop: Header=BB1_21 Depth=1
incl %ebp
movl $.L.str.3, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_23
.LBB1_24: # %._crit_edge124
testl %ebp, %ebp
je .LBB1_25
# %bb.26:
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_27
.LBB1_25:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_27:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB1_28:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPKiS0_Pii,@object # @_Z8multiplyPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z8multiplyPKiS0_Pii
.p2align 3, 0x0
_Z8multiplyPKiS0_Pii:
.quad _Z23__device_stub__multiplyPKiS0_Pii
.size _Z8multiplyPKiS0_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fail to hipMalloc on GPU"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf ms\n"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\345\212\240\351\200\237\346\257\224\357\274\232%lf\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error occurs at index: %d: c = %d, c2 = %d\n"
.size .L.str.3, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d error(s) occurs!\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPKiS0_Pii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Successfully run on GPU and CPU!"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPKiS0_Pii
.globl _Z8multiplyPKiS0_Pii
.p2align 8
.type _Z8multiplyPKiS0_Pii,@function
_Z8multiplyPKiS0_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPKiS0_Pii, .Lfunc_end0-_Z8multiplyPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056c07_00000000-6_Matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
.type _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii, @function
_Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii, .-_Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
.globl _Z8multiplyPKiS0_Pii
.type _Z8multiplyPKiS0_Pii, @function
_Z8multiplyPKiS0_Pii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8multiplyPKiS0_Pii, .-_Z8multiplyPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Fail to cudaMalloc on GPU"
.LC3:
.string "%lf ms\n"
.LC4:
.string "\345\212\240\351\200\237\346\257\224\357\274\232%lf\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Error occurs at index: %d: c = %d, c2 = %d\n"
.align 8
.LC6:
.string "Successfully run on GPU and CPU!\n"
.section .rodata.str1.1
.LC7:
.string "%d error(s) occurs!\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L36
movl $1048576, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $1048576, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $1048576, %edi
call malloc@PLT
movq %rax, %r15
movl $1048576, %edi
call malloc@PLT
movq %rax, 32(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $262144, 28(%rsp)
movl $512, %ebp
movq $1048576, (%rsp)
movl $512, %ebx
.L29:
movq 16(%rsp), %rdx
movq %rdx, %r12
movq 8(%rsp), %r13
movslq 28(%rsp), %rax
leaq (%rdx,%rax,4), %r14
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $351843721, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100000, %edx, %edx
subl %edx, %eax
movl %eax, (%r12)
call rand@PLT
movslq %eax, %rdx
imulq $351843721, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13)
addq $4, %r12
addq $4, %r13
cmpq %r14, %r12
jne .L14
.L13:
leaq 48(%rsp), %rdi
movq (%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq (%rsp), %r14
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
call ceil@PLT
call sqrt@PLT
call ceil@PLT
movl $16, 72(%rsp)
movl $16, 76(%rsp)
movl $1, 80(%rsp)
cvttsd2sil %xmm0, %eax
movl %eax, 84(%rsp)
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movl $1, %ecx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L17:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq (%rsp), %rdx
movq 64(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd %xmm1, 40(%rsp)
divsd .LC2(%rip), %xmm1
movapd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebp, %ebp
jle .L18
salq $2, %rbx
movq 16(%rsp), %rax
movq %rax, %r12
leaq (%rbx,%rax), %rdi
movq 32(%rsp), %rax
movl $0, %ecx
movl $0, %r13d
movq %r15, %rdx
jmp .L19
.L36:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebp
movslq %eax, %rbx
movq %rbx, %r15
imulq %rbx, %r15
leaq 0(,%r15,4), %r14
movq %r14, (%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
movq %r14, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %r12d, %eax
imull %r12d, %eax
movl %eax, 28(%rsp)
testl %eax, %eax
jle .L13
jmp .L29
.L37:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L38:
movl %ebp, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z8multiplyPKiS0_PiiPKiS0_Pii
jmp .L17
.L31:
movl %ecx, %r14d
.L21:
movq %r10, %r15
movq %r11, %r8
movq %r12, %rcx
movl $0, %r9d
.L20:
movl (%rcx), %esi
imull (%r8), %esi
addl %esi, %r9d
addq $4, %rcx
addq %rbx, %r8
cmpq %rdi, %rcx
jne .L20
movl %r9d, (%r15)
leal 1(%r14), %ecx
addq $4, %r10
addq $4, %r11
cmpl %ebp, %ecx
jne .L31
movl (%rsp), %ecx
leal 1(%rcx), %r8d
addq %rbx, %r12
addq %rbx, %rdi
addq %rbx, %rax
cmpl %r14d, %ecx
je .L22
movl %r8d, %ecx
.L19:
movq 8(%rsp), %r11
movq %rax, %r10
movl %r13d, %r14d
movl %ecx, (%rsp)
jmp .L21
.L18:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movq %xmm2, %rbx
movapd %xmm2, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
divsd 40(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 28(%rsp)
jg .L28
.L23:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L27:
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
addq $1, %rbx
cmpq %rbx, %rbp
je .L40
.L25:
movl (%r15,%rbx,4), %ecx
movl (%r14,%rbx,4), %r8d
cmpl %r8d, %ecx
je .L24
addl $1, %r13d
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L40:
testl %r13d, %r13d
je .L23
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L22:
movq %rdx, %r15
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movq %xmm4, %rbx
movapd %xmm4, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
divsd 40(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L28:
movslq 28(%rsp), %rbp
movl $0, %ebx
movl $0, %r13d
leaq .LC5(%rip), %r12
movq 32(%rsp), %r14
jmp .L25
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8multiplyPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1064304640
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix.hip"
.globl _Z23__device_stub__multiplyPKiS0_Pii # -- Begin function _Z23__device_stub__multiplyPKiS0_Pii
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPKiS0_Pii,@function
_Z23__device_stub__multiplyPKiS0_Pii: # @_Z23__device_stub__multiplyPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPKiS0_Pii, .Lfunc_end0-_Z23__device_stub__multiplyPKiS0_Pii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %eax # imm = 0x200
cmpl $2, %edi
jne .LBB1_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB1_2:
movq %rax, 8(%rsp) # 8-byte Spill
movslq %eax, %r15
movq %r15, %rbp
imulq %r15, %rbp
shlq $2, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %rbp, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl %r15d, %eax
imull %eax, %eax
movq %rax, 56(%rsp) # 8-byte Spill
testl %r15d, %r15d
je .LBB1_5
# %bb.3: # %.lr.ph.preheader
movq 56(%rsp), %r15 # 8-byte Reload
cmpl $1, %r15d
# kill: def $r15d killed $r15d killed $r15 def $r15
adcl $0, %r15d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_7
# %bb.6:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %eax
jmp .LBB1_28
.LBB1_7:
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %r15 # 8-byte Reload
cvtsi2sd %r15d, %xmm0
mulsd %xmm0, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_9
# %bb.8:
sqrtsd %xmm0, %xmm0
jmp .LBB1_10
.LBB1_9: # %call.sqrt
callq sqrt
.LBB1_10: # %.split
callq ceil@PLT
cvttsd2si %xmm0, %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %r15d, 52(%rsp)
leaq 192(%rsp), %rax
movq %rax, 80(%rsp)
leaq 184(%rsp), %rax
movq %rax, 88(%rsp)
leaq 176(%rsp), %rax
movq %rax, 96(%rsp)
leaq 52(%rsp), %rax
movq %rax, 104(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiS0_Pii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %r12, 120(%rsp) # 8-byte Spill
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 88(%rsp), %rax
subq 72(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 112(%rsp) # 8-byte Spill
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r15d, %r15d
jle .LBB1_19
# %bb.13: # %.preheader.lr.ph
movl %r15d, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
# Child Loop BB1_16 Depth 3
movl %edx, %edi
leaq (%rbx,%rdi,4), %rdi
movq %rsi, %r8
imulq %rax, %r8
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r8
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_15: # %.lr.ph112
# Parent Loop BB1_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_16 Depth 3
movl $0, (%r8,%r10,4)
xorl %r11d, %r11d
movq %r9, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_14 Depth=1
# Parent Loop BB1_15 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r15), %r12d
imull (%rdi,%r11,4), %r12d
addl %r12d, %r13d
incq %r11
addq %rcx, %r15
cmpq %r11, %rax
jne .LBB1_16
# %bb.17: # %._crit_edge113
# in Loop: Header=BB1_15 Depth=2
movl %r13d, (%r8,%r10,4)
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB1_15
# %bb.18: # %._crit_edge117
# in Loop: Header=BB1_14 Depth=1
incq %rsi
movq 8(%rsp), %r15 # 8-byte Reload
addl %r15d, %edx
cmpq %rax, %rsi
jne .LBB1_14
.LBB1_19: # %._crit_edge119
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 88(%rsp), %rax
subq 72(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 112(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.2, %edi
movb $1, %al
callq printf
testl %r15d, %r15d
movq 120(%rsp), %r15 # 8-byte Reload
movq 56(%rsp), %r12 # 8-byte Reload
je .LBB1_24
# %bb.20: # %.lr.ph123.preheader
cmpl $1, %r12d
adcl $0, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_23: # in Loop: Header=BB1_21 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB1_24
.LBB1_21: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %edx
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax,%r13,4), %ecx
cmpl %ecx, %edx
je .LBB1_23
# %bb.22: # in Loop: Header=BB1_21 Depth=1
incl %ebp
movl $.L.str.3, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_23
.LBB1_24: # %._crit_edge124
testl %ebp, %ebp
je .LBB1_25
# %bb.26:
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_27
.LBB1_25:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_27:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB1_28:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPKiS0_Pii,@object # @_Z8multiplyPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z8multiplyPKiS0_Pii
.p2align 3, 0x0
_Z8multiplyPKiS0_Pii:
.quad _Z23__device_stub__multiplyPKiS0_Pii
.size _Z8multiplyPKiS0_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fail to hipMalloc on GPU"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf ms\n"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\345\212\240\351\200\237\346\257\224\357\274\232%lf\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error occurs at index: %d: c = %d, c2 = %d\n"
.size .L.str.3, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d error(s) occurs!\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPKiS0_Pii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Successfully run on GPU and CPU!"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void dkernel(unsigned *vector, unsigned vectorsize) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if (id % 2) vector[id] = id;
else vector[id] = vectorsize * vectorsize;
}
#define BLOCKSIZE 10
#define N BLOCKSIZE
int main(int nn, char *str[]) {
unsigned *vector, *hvector;
cudaMalloc(&vector, N * sizeof(unsigned));
hvector = (unsigned *)malloc(N * sizeof(unsigned));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
dkernel<<<nblocks, BLOCKSIZE>>>(vector, N);
cudaMemcpy(hvector, vector, N * sizeof(unsigned), cudaMemcpyDeviceToHost);
for (unsigned ii = 0; ii < N; ++ii) {
printf("%4d ", hvector[ii]);
}
printf("\n");
return 0;
} | code for sm_80
Function : _Z7dkernelPjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*0070*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fc800078ec0ff */
/*0080*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f05070 */
/*0090*/ IMAD.WIDE.U32 R2, R0.reuse, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe400078e0003 */
/*00a0*/ SEL R5, R0, UR4, !P0 ; /* 0x0000000400057c07 */
/* 0x000fe2000c000000 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void dkernel(unsigned *vector, unsigned vectorsize) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if (id % 2) vector[id] = id;
else vector[id] = vectorsize * vectorsize;
}
#define BLOCKSIZE 10
#define N BLOCKSIZE
int main(int nn, char *str[]) {
unsigned *vector, *hvector;
cudaMalloc(&vector, N * sizeof(unsigned));
hvector = (unsigned *)malloc(N * sizeof(unsigned));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
dkernel<<<nblocks, BLOCKSIZE>>>(vector, N);
cudaMemcpy(hvector, vector, N * sizeof(unsigned), cudaMemcpyDeviceToHost);
for (unsigned ii = 0; ii < N; ++ii) {
printf("%4d ", hvector[ii]);
}
printf("\n");
return 0;
} | .file "tmpxft_000ddcfe_00000000-6_divergence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7dkernelPjjPjj
.type _Z27__device_stub__Z7dkernelPjjPjj, @function
_Z27__device_stub__Z7dkernelPjjPjj:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7dkernelPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7dkernelPjjPjj, .-_Z27__device_stub__Z7dkernelPjjPjj
.globl _Z7dkernelPjj
.type _Z7dkernelPjj, @function
_Z7dkernelPjj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7dkernelPjjPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelPjj, .-_Z7dkernelPjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $40, %rbp
leaq .LC0(%rip), %r12
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7dkernelPjjPjj
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7dkernelPjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelPjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
__global__ void dkernel(unsigned *vector, unsigned vectorsize) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if (id % 2) vector[id] = id;
else vector[id] = vectorsize * vectorsize;
}
#define BLOCKSIZE 10
#define N BLOCKSIZE
int main(int nn, char *str[]) {
unsigned *vector, *hvector;
cudaMalloc(&vector, N * sizeof(unsigned));
hvector = (unsigned *)malloc(N * sizeof(unsigned));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
dkernel<<<nblocks, BLOCKSIZE>>>(vector, N);
cudaMemcpy(hvector, vector, N * sizeof(unsigned), cudaMemcpyDeviceToHost);
for (unsigned ii = 0; ii < N; ++ii) {
printf("%4d ", hvector[ii]);
}
printf("\n");
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void dkernel(unsigned *vector, unsigned vectorsize) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if (id % 2) vector[id] = id;
else vector[id] = vectorsize * vectorsize;
}
#define BLOCKSIZE 10
#define N BLOCKSIZE
int main(int nn, char *str[]) {
unsigned *vector, *hvector;
hipMalloc(&vector, N * sizeof(unsigned));
hvector = (unsigned *)malloc(N * sizeof(unsigned));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
dkernel<<<nblocks, BLOCKSIZE>>>(vector, N);
hipMemcpy(hvector, vector, N * sizeof(unsigned), hipMemcpyDeviceToHost);
for (unsigned ii = 0; ii < N; ++ii) {
printf("%4d ", hvector[ii]);
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void dkernel(unsigned *vector, unsigned vectorsize) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if (id % 2) vector[id] = id;
else vector[id] = vectorsize * vectorsize;
}
#define BLOCKSIZE 10
#define N BLOCKSIZE
int main(int nn, char *str[]) {
unsigned *vector, *hvector;
hipMalloc(&vector, N * sizeof(unsigned));
hvector = (unsigned *)malloc(N * sizeof(unsigned));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
dkernel<<<nblocks, BLOCKSIZE>>>(vector, N);
hipMemcpy(hvector, vector, N * sizeof(unsigned), hipMemcpyDeviceToHost);
for (unsigned ii = 0; ii < N; ++ii) {
printf("%4d ", hvector[ii]);
}
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7dkernelPjj
.globl _Z7dkernelPjj
.p2align 8
.type _Z7dkernelPjj,@function
_Z7dkernelPjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s3, s3
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 1, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v4, v1, s3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dkernelPjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7dkernelPjj, .Lfunc_end0-_Z7dkernelPjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dkernelPjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7dkernelPjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void dkernel(unsigned *vector, unsigned vectorsize) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if (id % 2) vector[id] = id;
else vector[id] = vectorsize * vectorsize;
}
#define BLOCKSIZE 10
#define N BLOCKSIZE
int main(int nn, char *str[]) {
unsigned *vector, *hvector;
hipMalloc(&vector, N * sizeof(unsigned));
hvector = (unsigned *)malloc(N * sizeof(unsigned));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
dkernel<<<nblocks, BLOCKSIZE>>>(vector, N);
hipMemcpy(hvector, vector, N * sizeof(unsigned), hipMemcpyDeviceToHost);
for (unsigned ii = 0; ii < N; ++ii) {
printf("%4d ", hvector[ii]);
}
printf("\n");
return 0;
} | .text
.file "divergence.hip"
.globl _Z22__device_stub__dkernelPjj # -- Begin function _Z22__device_stub__dkernelPjj
.p2align 4, 0x90
.type _Z22__device_stub__dkernelPjj,@function
_Z22__device_stub__dkernelPjj: # @_Z22__device_stub__dkernelPjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7dkernelPjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelPjj, .Lfunc_end0-_Z22__device_stub__dkernelPjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7dkernelPjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelPjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelPjj,@object # @_Z7dkernelPjj
.section .rodata,"a",@progbits
.globl _Z7dkernelPjj
.p2align 3, 0x0
_Z7dkernelPjj:
.quad _Z22__device_stub__dkernelPjj
.size _Z7dkernelPjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7dkernelPjj"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelPjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelPjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7dkernelPjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*0070*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fc800078ec0ff */
/*0080*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f05070 */
/*0090*/ IMAD.WIDE.U32 R2, R0.reuse, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe400078e0003 */
/*00a0*/ SEL R5, R0, UR4, !P0 ; /* 0x0000000400057c07 */
/* 0x000fe2000c000000 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7dkernelPjj
.globl _Z7dkernelPjj
.p2align 8
.type _Z7dkernelPjj,@function
_Z7dkernelPjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s3, s3
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 1, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v4, v1, s3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dkernelPjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7dkernelPjj, .Lfunc_end0-_Z7dkernelPjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dkernelPjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7dkernelPjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ddcfe_00000000-6_divergence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7dkernelPjjPjj
.type _Z27__device_stub__Z7dkernelPjjPjj, @function
_Z27__device_stub__Z7dkernelPjjPjj:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7dkernelPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7dkernelPjjPjj, .-_Z27__device_stub__Z7dkernelPjjPjj
.globl _Z7dkernelPjj
.type _Z7dkernelPjj, @function
_Z7dkernelPjj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7dkernelPjjPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelPjj, .-_Z7dkernelPjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $40, %rbp
leaq .LC0(%rip), %r12
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7dkernelPjjPjj
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7dkernelPjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelPjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "divergence.hip"
.globl _Z22__device_stub__dkernelPjj # -- Begin function _Z22__device_stub__dkernelPjj
.p2align 4, 0x90
.type _Z22__device_stub__dkernelPjj,@function
_Z22__device_stub__dkernelPjj: # @_Z22__device_stub__dkernelPjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7dkernelPjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelPjj, .Lfunc_end0-_Z22__device_stub__dkernelPjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7dkernelPjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelPjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelPjj,@object # @_Z7dkernelPjj
.section .rodata,"a",@progbits
.globl _Z7dkernelPjj
.p2align 3, 0x0
_Z7dkernelPjj:
.quad _Z22__device_stub__dkernelPjj
.size _Z7dkernelPjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7dkernelPjj"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelPjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelPjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
using namespace std;
struct particle {
float position[3];
float velocity[3];
};
struct seed {
int x;
int y;
int z;
};
__host__ __device__ float gen_random(int seed, int particle_id, int iteration,int num_particles)
{
float rand_num = (seed * particle_id + iteration) % num_particles;
return rand_num;
}
__global__ void timestep(struct particle* particles, seed seed, int iteration, int num_particles) {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_particles) {
// Velocity update:
particles[i].velocity[0] = gen_random(seed.x, i, iteration, num_particles);
particles[i].velocity[1] = gen_random(seed.y, i, iteration, num_particles);
particles[i].velocity[2] = gen_random(seed.z, i, iteration, num_particles);
// Position update:
particles[i].position[0] = particles[i].position[0] + particles[i].velocity[0];
particles[i].position[1] = particles[i].position[1] + particles[i].velocity[1];
particles[i].position[2] = particles[i].position[2] + particles[i].velocity[2];
}
}
int main(int argc, char *argv[])
{
int i = 0, j = 0, num_particles = 10000, num_iterations = 100, tpb = 256, num_blocks = 0;
struct timeval t0, t1;
seed seed = {5,6,7};
for(i = 1; i < argc; ++i) {
if (strcmp(argv[i], "-num_particles") == 0)
{
num_particles = atoi(argv[++i]);
}
else if (strcmp(argv[i], "-tpb") == 0)
{
tpb = atoi(argv[++i]);
}
else if (strcmp(argv[i], "--num_iterations") == 0)
{
num_iterations = atoi(argv[++i]);
}
}
num_blocks = (num_particles/tpb + 1);
struct particle *particlesCPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *particlesGPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *resultGPUSimulation = (struct particle*)malloc(num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the CPU...");
gettimeofday(&t0, 0);
for(i = 0; i < num_iterations; i++)
{
for(j = 0; j < num_particles; j++)
{
// Velocity update:
particlesCPU[j].velocity[0] = gen_random(seed.x, j, i, num_particles);
particlesCPU[j].velocity[1] = gen_random(seed.y, j, i, num_particles);
particlesCPU[j].velocity[2] = gen_random(seed.z, j, i, num_particles);
// Position update:
particlesCPU[j].position[0] = particlesCPU[j].position[0] + particlesCPU[j].velocity[0];
particlesCPU[j].position[1] = particlesCPU[j].position[1] + particlesCPU[j].velocity[1];
particlesCPU[j].position[2] = particlesCPU[j].position[2] + particlesCPU[j].velocity[2];
}
}
gettimeofday(&t1, 0);
long elapsed_cpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds", num_particles, num_iterations, elapsed_cpu);
cudaMalloc(&particlesGPU, num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the GPU...");
gettimeofday(&t0, 0);
for (int i = 0; i < num_iterations; i++) {
timestep<<<num_blocks, tpb>>>(particlesGPU, seed, i, num_particles);
cudaDeviceSynchronize();
}
cudaMemcpy(resultGPUSimulation, particlesGPU, num_particles * sizeof(struct particle), cudaMemcpyDeviceToHost);
gettimeofday(&t1, 0);
long elapsed_gpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds", num_particles, num_iterations, tpb, num_blocks, elapsed_gpu);
// comparing the results of the two versions
printf("\n\nComparing the output for each implementation...");
int flag_comparison = 0;
for (i = 0; i < num_particles; i++)
{
if( (abs(particlesCPU[i].velocity[0] - resultGPUSimulation[i].velocity[0]) > 1) || (abs(particlesCPU[i].velocity[1] - resultGPUSimulation[i].velocity[1]) > 1) || (abs(particlesCPU[i].velocity[2] - resultGPUSimulation[i].velocity[2]) > 1) || (abs(particlesCPU[i].position[0] - resultGPUSimulation[i].position[0]) > 1)|| (abs(particlesCPU[i].position[1] - resultGPUSimulation[i].position[1]) > 1) || (abs(particlesCPU[i].position[2] - resultGPUSimulation[i].position[2]) > 1) )
{
flag_comparison = 1;
break;
}
}
if(flag_comparison == 0)
{
printf("Correct!");
}
else
{
printf("Incorrect!");
}
// clean up
free(particlesCPU);
cudaFree(particlesGPU);
return 0;
} | code for sm_80
Function : _Z8timestepP8particle4seedii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, 0x18 ; /* 0x00000018ff027424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fca00078e0202 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64+0x8] ; /* 0x0000080402007981 */
/* 0x000f22000c1e1900 */
/*00c0*/ IABS R6, c[0x0][0x178] ; /* 0x00005e0000067a13 */
/* 0x000fe40000000000 */
/*00d0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fc40000000f00 */
/*00e0*/ I2F.RP R10, R6 ; /* 0x00000006000a7306 */
/* 0x000e220000209400 */
/*00f0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x000fe40000000f00 */
/*0100*/ IMAD R7, R11, R12, c[0x0][0x174] ; /* 0x00005d000b077624 */
/* 0x000fe400078e020c */
/*0110*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0c7624 */
/* 0x000fc600078e00ff */
/*0120*/ IABS R15, R7 ; /* 0x00000007000f7213 */
/* 0x000fe20000000000 */
/*0130*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fe20007ffe0ff */
/*0150*/ IMAD R10, R11.reuse, R12, c[0x0][0x174] ; /* 0x00005d000b0a7624 */
/* 0x040fe400078e020c */
/*0160*/ IMAD R12, R11, R14, c[0x0][0x174] ; /* 0x00005d000b0c7624 */
/* 0x000fc600078e020e */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*0180*/ ISETP.GE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f86270 */
/*0190*/ IABS R17, R12 ; /* 0x0000000c00117213 */
/* 0x000fe40000000000 */
/*01a0*/ ISETP.GE.AND P5, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003fa6270 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*01c0*/ IMAD.MOV R13, RZ, RZ, -R9 ; /* 0x000000ffff0d7224 */
/* 0x002fc800078e0a09 */
/*01d0*/ IMAD R13, R13, R6, RZ ; /* 0x000000060d0d7224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R8, R9, R13, R8 ; /* 0x0000000d09087227 */
/* 0x000fe200078e0008 */
/*01f0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe40000000f00 */
/*0200*/ IABS R15, R10 ; /* 0x0000000a000f7213 */
/* 0x000fc60000000000 */
/*0210*/ IMAD.HI.U32 R9, R8, R13, RZ ; /* 0x0000000d08097227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.HI.U32 R11, R8, R15, RZ ; /* 0x0000000f080b7227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.HI.U32 R8, R8, R17, RZ ; /* 0x0000001108087227 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fc60007ffe1ff */
/*0250*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a09 */
/*0260*/ IMAD R11, R6.reuse, R11, R15 ; /* 0x0000000b060b7224 */
/* 0x040fe400078e020f */
/*0270*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0a08 */
/*0280*/ IMAD R9, R6.reuse, R9, R13 ; /* 0x0000000906097224 */
/* 0x040fe200078e020d */
/*0290*/ ISETP.GT.U32.AND P1, PT, R6.reuse, R11, PT ; /* 0x0000000b0600720c */
/* 0x040fe20003f24070 */
/*02a0*/ IMAD R13, R6.reuse, R8, R17 ; /* 0x00000008060d7224 */
/* 0x040fe200078e0211 */
/*02b0*/ LOP3.LUT R8, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff087a12 */
/* 0x000fe400078e33ff */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc40003f04070 */
/*02d0*/ ISETP.GT.U32.AND P2, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fce0003f44070 */
/*02e0*/ @!P1 IMAD.IADD R11, R11, 0x1, -R6 ; /* 0x000000010b0b9824 */
/* 0x000fc800078e0a06 */
/*02f0*/ @!P0 IADD3 R9, R9, -R6.reuse, RZ ; /* 0x8000000609098210 */
/* 0x080fe40007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P1, PT, R6.reuse, R11, PT ; /* 0x0000000b0600720c */
/* 0x040fe40003f24070 */
/*0310*/ @!P2 IADD3 R13, R13, -R6, RZ ; /* 0x800000060d0da210 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.GT.U32.AND P3, PT, R6.reuse, R9, PT ; /* 0x000000090600720c */
/* 0x040fe40003f64070 */
/*0330*/ ISETP.GT.U32.AND P2, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe40003f44070 */
/*0340*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f06270 */
/*0350*/ @!P1 IADD3 R11, R11, -R6, RZ ; /* 0x800000060b0b9210 */
/* 0x000fc80007ffe0ff */
/*0360*/ @!P3 IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x000000010909b824 */
/* 0x000fe200078e0a06 */
/*0370*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f65270 */
/*0380*/ @!P4 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0bc224 */
/* 0x000fe200078e0a0b */
/*0390*/ @!P2 IADD3 R13, R13, -R6, RZ ; /* 0x800000060d0da210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @!P0 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff098224 */
/* 0x000fc600078e0a09 */
/*03b0*/ @!P5 IADD3 R13, -R13, RZ, RZ ; /* 0x000000ff0d0dd210 */
/* 0x000fe40007ffe1ff */
/*03c0*/ SEL R9, R8.reuse, R9, !P3 ; /* 0x0000000908097207 */
/* 0x040fe40005800000 */
/*03d0*/ SEL R11, R8.reuse, R11, !P3 ; /* 0x0000000b080b7207 */
/* 0x040fe40005800000 */
/*03e0*/ SEL R8, R8, R13, !P3 ; /* 0x0000000d08087207 */
/* 0x000fe40005800000 */
/*03f0*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e300000201400 */
/*0400*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000e700000201400 */
/*0410*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x000f620000201400 */
/*0420*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x001fe8000c101904 */
/*0430*/ STG.E [R2.64+0x10], R11 ; /* 0x0000100b02007986 */
/* 0x002fe8000c101904 */
/*0440*/ STG.E [R2.64+0x14], R7 ; /* 0x0000140702007986 */
/* 0x020fe2000c101904 */
/*0450*/ FADD R5, R9, R5 ; /* 0x0000000509057221 */
/* 0x004fc40000000000 */
/*0460*/ FADD R13, R11, R4 ; /* 0x000000040b0d7221 */
/* 0x008fc60000000000 */
/*0470*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0480*/ FADD R15, R7, R0 ; /* 0x00000000070f7221 */
/* 0x010fc60000000000 */
/*0490*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
using namespace std;
struct particle {
float position[3];
float velocity[3];
};
struct seed {
int x;
int y;
int z;
};
__host__ __device__ float gen_random(int seed, int particle_id, int iteration,int num_particles)
{
float rand_num = (seed * particle_id + iteration) % num_particles;
return rand_num;
}
__global__ void timestep(struct particle* particles, seed seed, int iteration, int num_particles) {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_particles) {
// Velocity update:
particles[i].velocity[0] = gen_random(seed.x, i, iteration, num_particles);
particles[i].velocity[1] = gen_random(seed.y, i, iteration, num_particles);
particles[i].velocity[2] = gen_random(seed.z, i, iteration, num_particles);
// Position update:
particles[i].position[0] = particles[i].position[0] + particles[i].velocity[0];
particles[i].position[1] = particles[i].position[1] + particles[i].velocity[1];
particles[i].position[2] = particles[i].position[2] + particles[i].velocity[2];
}
}
int main(int argc, char *argv[])
{
int i = 0, j = 0, num_particles = 10000, num_iterations = 100, tpb = 256, num_blocks = 0;
struct timeval t0, t1;
seed seed = {5,6,7};
for(i = 1; i < argc; ++i) {
if (strcmp(argv[i], "-num_particles") == 0)
{
num_particles = atoi(argv[++i]);
}
else if (strcmp(argv[i], "-tpb") == 0)
{
tpb = atoi(argv[++i]);
}
else if (strcmp(argv[i], "--num_iterations") == 0)
{
num_iterations = atoi(argv[++i]);
}
}
num_blocks = (num_particles/tpb + 1);
struct particle *particlesCPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *particlesGPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *resultGPUSimulation = (struct particle*)malloc(num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the CPU...");
gettimeofday(&t0, 0);
for(i = 0; i < num_iterations; i++)
{
for(j = 0; j < num_particles; j++)
{
// Velocity update:
particlesCPU[j].velocity[0] = gen_random(seed.x, j, i, num_particles);
particlesCPU[j].velocity[1] = gen_random(seed.y, j, i, num_particles);
particlesCPU[j].velocity[2] = gen_random(seed.z, j, i, num_particles);
// Position update:
particlesCPU[j].position[0] = particlesCPU[j].position[0] + particlesCPU[j].velocity[0];
particlesCPU[j].position[1] = particlesCPU[j].position[1] + particlesCPU[j].velocity[1];
particlesCPU[j].position[2] = particlesCPU[j].position[2] + particlesCPU[j].velocity[2];
}
}
gettimeofday(&t1, 0);
long elapsed_cpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds", num_particles, num_iterations, elapsed_cpu);
cudaMalloc(&particlesGPU, num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the GPU...");
gettimeofday(&t0, 0);
for (int i = 0; i < num_iterations; i++) {
timestep<<<num_blocks, tpb>>>(particlesGPU, seed, i, num_particles);
cudaDeviceSynchronize();
}
cudaMemcpy(resultGPUSimulation, particlesGPU, num_particles * sizeof(struct particle), cudaMemcpyDeviceToHost);
gettimeofday(&t1, 0);
long elapsed_gpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds", num_particles, num_iterations, tpb, num_blocks, elapsed_gpu);
// comparing the results of the two versions
printf("\n\nComparing the output for each implementation...");
int flag_comparison = 0;
for (i = 0; i < num_particles; i++)
{
if( (abs(particlesCPU[i].velocity[0] - resultGPUSimulation[i].velocity[0]) > 1) || (abs(particlesCPU[i].velocity[1] - resultGPUSimulation[i].velocity[1]) > 1) || (abs(particlesCPU[i].velocity[2] - resultGPUSimulation[i].velocity[2]) > 1) || (abs(particlesCPU[i].position[0] - resultGPUSimulation[i].position[0]) > 1)|| (abs(particlesCPU[i].position[1] - resultGPUSimulation[i].position[1]) > 1) || (abs(particlesCPU[i].position[2] - resultGPUSimulation[i].position[2]) > 1) )
{
flag_comparison = 1;
break;
}
}
if(flag_comparison == 0)
{
printf("Correct!");
}
else
{
printf("Incorrect!");
}
// clean up
free(particlesCPU);
cudaFree(particlesGPU);
return 0;
} | .file "tmpxft_000e35e6_00000000-6_exercise_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10gen_randomiiii
.type _Z10gen_randomiiii, @function
_Z10gen_randomiiii:
.LFB2057:
.cfi_startproc
endbr64
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z10gen_randomiiii, .-_Z10gen_randomiiii
.globl _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
.type _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii, @function
_Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8timestepP8particle4seedii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii, .-_Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
.globl _Z8timestepP8particle4seedii
.type _Z8timestepP8particle4seedii, @function
_Z8timestepP8particle4seedii:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %edx, %eax
movl %ecx, %edx
movl %r8d, %ecx
movq %rsi, (%rsp)
movl %eax, 8(%rsp)
movq %rsp, %rsi
call _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8timestepP8particle4seedii, .-_Z8timestepP8particle4seedii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-num_particles"
.LC1:
.string "-tpb"
.LC2:
.string "--num_iterations"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\n\nComputing simulation on the CPU..."
.section .rodata.str1.1
.LC4:
.string "Done!"
.section .rodata.str1.8
.align 8
.LC5:
.string "\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds"
.align 8
.LC6:
.string "\n\nComputing simulation on the GPU..."
.align 8
.LC7:
.string "\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds"
.align 8
.LC8:
.string "\n\nComparing the output for each implementation..."
.section .rodata.str1.1
.LC11:
.string "Correct!"
.LC12:
.string "Incorrect!"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L13
movq %rsi, %r13
movl $256, 4(%rsp)
movl $100, %r15d
movl $10000, %ebx
movl $1, %ebp
movl %r15d, 8(%rsp)
movl %edi, %r15d
jmp .L17
.L40:
addl $1, %ebp
movq 8(%r13,%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
.L15:
addl $1, %ebp
cmpl %ebp, %r15d
jle .L39
.L17:
movslq %ebp, %rax
leaq 0(,%rax,8), %r14
movq 0(%r13,%rax,8), %r12
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L40
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L41
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L15
addl $1, %ebp
movq 8(%r13,%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
jmp .L15
.L41:
addl $1, %ebp
movq 8(%r13,%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L15
.L39:
movl 8(%rsp), %r15d
movl %ebx, %eax
cltd
idivl 4(%rsp)
leal 1(%rax), %r12d
movslq %ebx, %rax
leaq (%rax,%rax,2), %rbp
salq $3, %rbp
movq %rbp, 16(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %r15d, %r15d
jle .L18
.L31:
leal (%rbx,%rbx,4), %r9d
movl $0, %r10d
jmp .L19
.L22:
movl %r10d, %esi
movq %r14, %rcx
movl %r10d, %r8d
movl %r10d, %edi
.L20:
movl %esi, %eax
cltd
idivl %ebx
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movss %xmm2, 12(%rcx)
movl %edi, %eax
cltd
idivl %ebx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
movss %xmm1, 16(%rcx)
movl %r8d, %eax
cltd
idivl %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 20(%rcx)
addss (%rcx), %xmm2
movss %xmm2, (%rcx)
addss 4(%rcx), %xmm1
movss %xmm1, 4(%rcx)
addss 8(%rcx), %xmm0
movss %xmm0, 8(%rcx)
addl $5, %esi
addq $24, %rcx
addl $6, %edi
addl $7, %r8d
cmpl %r9d, %esi
jne .L20
.L23:
addl $1, %r10d
addl $1, %r9d
cmpl %r15d, %r10d
je .L21
.L19:
testl %ebx, %ebx
jg .L22
jmp .L23
.L21:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rbp
subq 80(%rsp), %rbp
imulq $1000000, %rbp, %rbp
addq 104(%rsp), %rbp
subq 88(%rsp), %rbp
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %r8
movl %r15d, %ecx
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %ebp
leaq 68(%rsp), %r13
movq %r14, 24(%rsp)
movl 4(%rsp), %r14d
jmp .L25
.L24:
call cudaDeviceSynchronize@PLT
addl $1, %ebp
cmpl %r15d, %ebp
je .L42
.L25:
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
movl $5, 68(%rsp)
movl $6, 72(%rsp)
movl $7, 76(%rsp)
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
jmp .L24
.L42:
movq 24(%rsp), %r14
.L29:
movl $2, %ecx
movq 16(%rsp), %r13
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rbp
subq 80(%rsp), %rbp
imulq $1000000, %rbp, %rbp
addq 104(%rsp), %rbp
subq 88(%rsp), %rbp
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbp
.cfi_def_cfa_offset 208
movl %r12d, %r9d
movl 20(%rsp), %r8d
movl %r15d, %ecx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L26
movq %r14, %rax
movq 8(%rsp), %rdx
movq %r13, %rdi
addq %r14, %rdi
movss .LC9(%rip), %xmm2
movss .LC10(%rip), %xmm1
movaps %xmm2, %xmm4
movaps %xmm1, %xmm3
movaps %xmm2, %xmm6
movaps %xmm1, %xmm5
movaps %xmm2, %xmm8
movaps %xmm1, %xmm7
movaps %xmm2, %xmm9
movaps %xmm2, %xmm10
.L28:
movss 12(%rax), %xmm0
subss 12(%rdx), %xmm0
andps %xmm2, %xmm0
comiss %xmm1, %xmm0
ja .L27
movss 16(%rax), %xmm0
subss 16(%rdx), %xmm0
andps %xmm4, %xmm0
comiss %xmm3, %xmm0
ja .L27
movss 20(%rax), %xmm0
subss 20(%rdx), %xmm0
andps %xmm6, %xmm0
comiss %xmm5, %xmm0
ja .L27
movss (%rax), %xmm0
subss (%rdx), %xmm0
andps %xmm8, %xmm0
comiss %xmm7, %xmm0
ja .L27
movss 4(%rax), %xmm0
subss 4(%rdx), %xmm0
andps %xmm9, %xmm0
comiss .LC10(%rip), %xmm0
ja .L27
movss 8(%rax), %xmm0
subss 8(%rdx), %xmm0
andps %xmm10, %xmm0
comiss .LC10(%rip), %xmm0
ja .L27
addq $24, %rax
addq $24, %rdx
cmpq %rdi, %rax
jne .L28
.L26:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L30:
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
imulq $1000000, %rax, %rax
addq 104(%rsp), %rax
subq 88(%rsp), %rax
movq %rax, %r13
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %r8
movl %r15d, %ecx
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L29
.L27:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L13:
movl $240000, %edi
call malloc@PLT
movq %rax, %r14
movl $240000, %edi
call malloc@PLT
movq %rax, 32(%rsp)
movl $240000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $256, 4(%rsp)
movl $100, %r15d
movl $10000, %ebx
movl $40, %r12d
movq $240000, 16(%rsp)
jmp .L31
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8timestepP8particle4seedii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8timestepP8particle4seedii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
using namespace std;
struct particle {
float position[3];
float velocity[3];
};
struct seed {
int x;
int y;
int z;
};
__host__ __device__ float gen_random(int seed, int particle_id, int iteration,int num_particles)
{
float rand_num = (seed * particle_id + iteration) % num_particles;
return rand_num;
}
__global__ void timestep(struct particle* particles, seed seed, int iteration, int num_particles) {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_particles) {
// Velocity update:
particles[i].velocity[0] = gen_random(seed.x, i, iteration, num_particles);
particles[i].velocity[1] = gen_random(seed.y, i, iteration, num_particles);
particles[i].velocity[2] = gen_random(seed.z, i, iteration, num_particles);
// Position update:
particles[i].position[0] = particles[i].position[0] + particles[i].velocity[0];
particles[i].position[1] = particles[i].position[1] + particles[i].velocity[1];
particles[i].position[2] = particles[i].position[2] + particles[i].velocity[2];
}
}
int main(int argc, char *argv[])
{
int i = 0, j = 0, num_particles = 10000, num_iterations = 100, tpb = 256, num_blocks = 0;
struct timeval t0, t1;
seed seed = {5,6,7};
for(i = 1; i < argc; ++i) {
if (strcmp(argv[i], "-num_particles") == 0)
{
num_particles = atoi(argv[++i]);
}
else if (strcmp(argv[i], "-tpb") == 0)
{
tpb = atoi(argv[++i]);
}
else if (strcmp(argv[i], "--num_iterations") == 0)
{
num_iterations = atoi(argv[++i]);
}
}
num_blocks = (num_particles/tpb + 1);
struct particle *particlesCPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *particlesGPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *resultGPUSimulation = (struct particle*)malloc(num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the CPU...");
gettimeofday(&t0, 0);
for(i = 0; i < num_iterations; i++)
{
for(j = 0; j < num_particles; j++)
{
// Velocity update:
particlesCPU[j].velocity[0] = gen_random(seed.x, j, i, num_particles);
particlesCPU[j].velocity[1] = gen_random(seed.y, j, i, num_particles);
particlesCPU[j].velocity[2] = gen_random(seed.z, j, i, num_particles);
// Position update:
particlesCPU[j].position[0] = particlesCPU[j].position[0] + particlesCPU[j].velocity[0];
particlesCPU[j].position[1] = particlesCPU[j].position[1] + particlesCPU[j].velocity[1];
particlesCPU[j].position[2] = particlesCPU[j].position[2] + particlesCPU[j].velocity[2];
}
}
gettimeofday(&t1, 0);
long elapsed_cpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds", num_particles, num_iterations, elapsed_cpu);
cudaMalloc(&particlesGPU, num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the GPU...");
gettimeofday(&t0, 0);
for (int i = 0; i < num_iterations; i++) {
timestep<<<num_blocks, tpb>>>(particlesGPU, seed, i, num_particles);
cudaDeviceSynchronize();
}
cudaMemcpy(resultGPUSimulation, particlesGPU, num_particles * sizeof(struct particle), cudaMemcpyDeviceToHost);
gettimeofday(&t1, 0);
long elapsed_gpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds", num_particles, num_iterations, tpb, num_blocks, elapsed_gpu);
// comparing the results of the two versions
printf("\n\nComparing the output for each implementation...");
int flag_comparison = 0;
for (i = 0; i < num_particles; i++)
{
if( (abs(particlesCPU[i].velocity[0] - resultGPUSimulation[i].velocity[0]) > 1) || (abs(particlesCPU[i].velocity[1] - resultGPUSimulation[i].velocity[1]) > 1) || (abs(particlesCPU[i].velocity[2] - resultGPUSimulation[i].velocity[2]) > 1) || (abs(particlesCPU[i].position[0] - resultGPUSimulation[i].position[0]) > 1)|| (abs(particlesCPU[i].position[1] - resultGPUSimulation[i].position[1]) > 1) || (abs(particlesCPU[i].position[2] - resultGPUSimulation[i].position[2]) > 1) )
{
flag_comparison = 1;
break;
}
}
if(flag_comparison == 0)
{
printf("Correct!");
}
else
{
printf("Incorrect!");
}
// clean up
free(particlesCPU);
cudaFree(particlesGPU);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
using namespace std;
struct particle {
float position[3];
float velocity[3];
};
struct seed {
int x;
int y;
int z;
};
__host__ __device__ float gen_random(int seed, int particle_id, int iteration,int num_particles)
{
float rand_num = (seed * particle_id + iteration) % num_particles;
return rand_num;
}
__global__ void timestep(struct particle* particles, seed seed, int iteration, int num_particles) {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_particles) {
// Velocity update:
particles[i].velocity[0] = gen_random(seed.x, i, iteration, num_particles);
particles[i].velocity[1] = gen_random(seed.y, i, iteration, num_particles);
particles[i].velocity[2] = gen_random(seed.z, i, iteration, num_particles);
// Position update:
particles[i].position[0] = particles[i].position[0] + particles[i].velocity[0];
particles[i].position[1] = particles[i].position[1] + particles[i].velocity[1];
particles[i].position[2] = particles[i].position[2] + particles[i].velocity[2];
}
}
int main(int argc, char *argv[])
{
int i = 0, j = 0, num_particles = 10000, num_iterations = 100, tpb = 256, num_blocks = 0;
struct timeval t0, t1;
seed seed = {5,6,7};
for(i = 1; i < argc; ++i) {
if (strcmp(argv[i], "-num_particles") == 0)
{
num_particles = atoi(argv[++i]);
}
else if (strcmp(argv[i], "-tpb") == 0)
{
tpb = atoi(argv[++i]);
}
else if (strcmp(argv[i], "--num_iterations") == 0)
{
num_iterations = atoi(argv[++i]);
}
}
num_blocks = (num_particles/tpb + 1);
struct particle *particlesCPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *particlesGPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *resultGPUSimulation = (struct particle*)malloc(num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the CPU...");
gettimeofday(&t0, 0);
for(i = 0; i < num_iterations; i++)
{
for(j = 0; j < num_particles; j++)
{
// Velocity update:
particlesCPU[j].velocity[0] = gen_random(seed.x, j, i, num_particles);
particlesCPU[j].velocity[1] = gen_random(seed.y, j, i, num_particles);
particlesCPU[j].velocity[2] = gen_random(seed.z, j, i, num_particles);
// Position update:
particlesCPU[j].position[0] = particlesCPU[j].position[0] + particlesCPU[j].velocity[0];
particlesCPU[j].position[1] = particlesCPU[j].position[1] + particlesCPU[j].velocity[1];
particlesCPU[j].position[2] = particlesCPU[j].position[2] + particlesCPU[j].velocity[2];
}
}
gettimeofday(&t1, 0);
long elapsed_cpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds", num_particles, num_iterations, elapsed_cpu);
hipMalloc(&particlesGPU, num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the GPU...");
gettimeofday(&t0, 0);
for (int i = 0; i < num_iterations; i++) {
timestep<<<num_blocks, tpb>>>(particlesGPU, seed, i, num_particles);
hipDeviceSynchronize();
}
hipMemcpy(resultGPUSimulation, particlesGPU, num_particles * sizeof(struct particle), hipMemcpyDeviceToHost);
gettimeofday(&t1, 0);
long elapsed_gpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds", num_particles, num_iterations, tpb, num_blocks, elapsed_gpu);
// comparing the results of the two versions
printf("\n\nComparing the output for each implementation...");
int flag_comparison = 0;
for (i = 0; i < num_particles; i++)
{
if( (abs(particlesCPU[i].velocity[0] - resultGPUSimulation[i].velocity[0]) > 1) || (abs(particlesCPU[i].velocity[1] - resultGPUSimulation[i].velocity[1]) > 1) || (abs(particlesCPU[i].velocity[2] - resultGPUSimulation[i].velocity[2]) > 1) || (abs(particlesCPU[i].position[0] - resultGPUSimulation[i].position[0]) > 1)|| (abs(particlesCPU[i].position[1] - resultGPUSimulation[i].position[1]) > 1) || (abs(particlesCPU[i].position[2] - resultGPUSimulation[i].position[2]) > 1) )
{
flag_comparison = 1;
break;
}
}
if(flag_comparison == 0)
{
printf("Correct!");
}
else
{
printf("Incorrect!");
}
// clean up
free(particlesCPU);
hipFree(particlesGPU);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
using namespace std;
struct particle {
float position[3];
float velocity[3];
};
struct seed {
int x;
int y;
int z;
};
__host__ __device__ float gen_random(int seed, int particle_id, int iteration,int num_particles)
{
float rand_num = (seed * particle_id + iteration) % num_particles;
return rand_num;
}
__global__ void timestep(struct particle* particles, seed seed, int iteration, int num_particles) {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_particles) {
// Velocity update:
particles[i].velocity[0] = gen_random(seed.x, i, iteration, num_particles);
particles[i].velocity[1] = gen_random(seed.y, i, iteration, num_particles);
particles[i].velocity[2] = gen_random(seed.z, i, iteration, num_particles);
// Position update:
particles[i].position[0] = particles[i].position[0] + particles[i].velocity[0];
particles[i].position[1] = particles[i].position[1] + particles[i].velocity[1];
particles[i].position[2] = particles[i].position[2] + particles[i].velocity[2];
}
}
int main(int argc, char *argv[])
{
int i = 0, j = 0, num_particles = 10000, num_iterations = 100, tpb = 256, num_blocks = 0;
struct timeval t0, t1;
seed seed = {5,6,7};
for(i = 1; i < argc; ++i) {
if (strcmp(argv[i], "-num_particles") == 0)
{
num_particles = atoi(argv[++i]);
}
else if (strcmp(argv[i], "-tpb") == 0)
{
tpb = atoi(argv[++i]);
}
else if (strcmp(argv[i], "--num_iterations") == 0)
{
num_iterations = atoi(argv[++i]);
}
}
num_blocks = (num_particles/tpb + 1);
struct particle *particlesCPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *particlesGPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *resultGPUSimulation = (struct particle*)malloc(num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the CPU...");
gettimeofday(&t0, 0);
for(i = 0; i < num_iterations; i++)
{
for(j = 0; j < num_particles; j++)
{
// Velocity update:
particlesCPU[j].velocity[0] = gen_random(seed.x, j, i, num_particles);
particlesCPU[j].velocity[1] = gen_random(seed.y, j, i, num_particles);
particlesCPU[j].velocity[2] = gen_random(seed.z, j, i, num_particles);
// Position update:
particlesCPU[j].position[0] = particlesCPU[j].position[0] + particlesCPU[j].velocity[0];
particlesCPU[j].position[1] = particlesCPU[j].position[1] + particlesCPU[j].velocity[1];
particlesCPU[j].position[2] = particlesCPU[j].position[2] + particlesCPU[j].velocity[2];
}
}
gettimeofday(&t1, 0);
long elapsed_cpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds", num_particles, num_iterations, elapsed_cpu);
hipMalloc(&particlesGPU, num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the GPU...");
gettimeofday(&t0, 0);
for (int i = 0; i < num_iterations; i++) {
timestep<<<num_blocks, tpb>>>(particlesGPU, seed, i, num_particles);
hipDeviceSynchronize();
}
hipMemcpy(resultGPUSimulation, particlesGPU, num_particles * sizeof(struct particle), hipMemcpyDeviceToHost);
gettimeofday(&t1, 0);
long elapsed_gpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds", num_particles, num_iterations, tpb, num_blocks, elapsed_gpu);
// comparing the results of the two versions
printf("\n\nComparing the output for each implementation...");
int flag_comparison = 0;
for (i = 0; i < num_particles; i++)
{
if( (abs(particlesCPU[i].velocity[0] - resultGPUSimulation[i].velocity[0]) > 1) || (abs(particlesCPU[i].velocity[1] - resultGPUSimulation[i].velocity[1]) > 1) || (abs(particlesCPU[i].velocity[2] - resultGPUSimulation[i].velocity[2]) > 1) || (abs(particlesCPU[i].position[0] - resultGPUSimulation[i].position[0]) > 1)|| (abs(particlesCPU[i].position[1] - resultGPUSimulation[i].position[1]) > 1) || (abs(particlesCPU[i].position[2] - resultGPUSimulation[i].position[2]) > 1) )
{
flag_comparison = 1;
break;
}
}
if(flag_comparison == 0)
{
printf("Correct!");
}
else
{
printf("Incorrect!");
}
// clean up
free(particlesCPU);
hipFree(particlesGPU);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8timestepP8particle4seedii
.globl _Z8timestepP8particle4seedii
.p2align 8
.type _Z8timestepP8particle4seedii,@function
_Z8timestepP8particle4seedii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_xor_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s3
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[7:8], null, v1, 24, s[4:5]
s_mov_b32 s2, s1
s_sub_i32 s4, 0, s3
v_mad_u64_u32 v[9:10], null, s7, v1, s[2:3]
v_mad_u64_u32 v[10:11], null, s0, v1, s[2:3]
global_load_b96 v[4:6], v[7:8], off
v_mad_u64_u32 v[2:3], null, s6, v1, s[2:3]
v_ashrrev_i32_e32 v11, 31, v9
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_ashrrev_i32_e32 v12, 31, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, v9, v11
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, v10, v12
v_mul_lo_u32 v3, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
v_xor_b32_e32 v3, v9, v11
v_xor_b32_e32 v9, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v13, v3, v0
v_mul_lo_u32 v13, v13, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v13
v_add_nc_u32_e32 v2, v2, v1
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v2, v0
v_mul_hi_u32 v0, v9, v0
v_mul_lo_u32 v10, v10, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v0, s3
v_sub_nc_u32_e32 v2, v2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v9, v0
v_subrev_nc_u32_e32 v10, s3, v3
v_subrev_nc_u32_e32 v9, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v13, s3, v0
v_cndmask_b32_e32 v2, v2, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s3, v2
v_cndmask_b32_e32 v3, v3, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_subrev_nc_u32_e32 v10, s3, v3
v_cndmask_b32_e32 v0, v0, v13, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s3, v0
v_cndmask_b32_e32 v2, v2, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_xor_b32_e32 v2, v2, v1
v_cndmask_b32_e32 v3, v3, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v2, v1
v_xor_b32_e32 v3, v3, v11
v_cndmask_b32_e32 v0, v0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v11
v_xor_b32_e32 v0, v0, v12
v_cvt_f32_i32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v9, v2
v_sub_nc_u32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v10, v0
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v4, v3 :: v_dual_add_f32 v1, v5, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v2, v6, v10
s_clause 0x1
global_store_b64 v[7:8], v[9:10], off offset:16
global_store_b128 v[7:8], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8timestepP8particle4seedii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8timestepP8particle4seedii, .Lfunc_end0-_Z8timestepP8particle4seedii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 12
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8timestepP8particle4seedii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8timestepP8particle4seedii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
using namespace std;
struct particle {
float position[3];
float velocity[3];
};
struct seed {
int x;
int y;
int z;
};
__host__ __device__ float gen_random(int seed, int particle_id, int iteration,int num_particles)
{
float rand_num = (seed * particle_id + iteration) % num_particles;
return rand_num;
}
__global__ void timestep(struct particle* particles, seed seed, int iteration, int num_particles) {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < num_particles) {
// Velocity update:
particles[i].velocity[0] = gen_random(seed.x, i, iteration, num_particles);
particles[i].velocity[1] = gen_random(seed.y, i, iteration, num_particles);
particles[i].velocity[2] = gen_random(seed.z, i, iteration, num_particles);
// Position update:
particles[i].position[0] = particles[i].position[0] + particles[i].velocity[0];
particles[i].position[1] = particles[i].position[1] + particles[i].velocity[1];
particles[i].position[2] = particles[i].position[2] + particles[i].velocity[2];
}
}
int main(int argc, char *argv[])
{
int i = 0, j = 0, num_particles = 10000, num_iterations = 100, tpb = 256, num_blocks = 0;
struct timeval t0, t1;
seed seed = {5,6,7};
for(i = 1; i < argc; ++i) {
if (strcmp(argv[i], "-num_particles") == 0)
{
num_particles = atoi(argv[++i]);
}
else if (strcmp(argv[i], "-tpb") == 0)
{
tpb = atoi(argv[++i]);
}
else if (strcmp(argv[i], "--num_iterations") == 0)
{
num_iterations = atoi(argv[++i]);
}
}
num_blocks = (num_particles/tpb + 1);
struct particle *particlesCPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *particlesGPU = (struct particle*)malloc(num_particles * sizeof(struct particle));
struct particle *resultGPUSimulation = (struct particle*)malloc(num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the CPU...");
gettimeofday(&t0, 0);
for(i = 0; i < num_iterations; i++)
{
for(j = 0; j < num_particles; j++)
{
// Velocity update:
particlesCPU[j].velocity[0] = gen_random(seed.x, j, i, num_particles);
particlesCPU[j].velocity[1] = gen_random(seed.y, j, i, num_particles);
particlesCPU[j].velocity[2] = gen_random(seed.z, j, i, num_particles);
// Position update:
particlesCPU[j].position[0] = particlesCPU[j].position[0] + particlesCPU[j].velocity[0];
particlesCPU[j].position[1] = particlesCPU[j].position[1] + particlesCPU[j].velocity[1];
particlesCPU[j].position[2] = particlesCPU[j].position[2] + particlesCPU[j].velocity[2];
}
}
gettimeofday(&t1, 0);
long elapsed_cpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds", num_particles, num_iterations, elapsed_cpu);
hipMalloc(&particlesGPU, num_particles * sizeof(struct particle));
printf("\n\nComputing simulation on the GPU...");
gettimeofday(&t0, 0);
for (int i = 0; i < num_iterations; i++) {
timestep<<<num_blocks, tpb>>>(particlesGPU, seed, i, num_particles);
hipDeviceSynchronize();
}
hipMemcpy(resultGPUSimulation, particlesGPU, num_particles * sizeof(struct particle), hipMemcpyDeviceToHost);
gettimeofday(&t1, 0);
long elapsed_gpu = (t1.tv_sec-t0.tv_sec)*1000000 + t1.tv_usec-t0.tv_usec;
printf("Done!");
printf("\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds", num_particles, num_iterations, tpb, num_blocks, elapsed_gpu);
// comparing the results of the two versions
printf("\n\nComparing the output for each implementation...");
int flag_comparison = 0;
for (i = 0; i < num_particles; i++)
{
if( (abs(particlesCPU[i].velocity[0] - resultGPUSimulation[i].velocity[0]) > 1) || (abs(particlesCPU[i].velocity[1] - resultGPUSimulation[i].velocity[1]) > 1) || (abs(particlesCPU[i].velocity[2] - resultGPUSimulation[i].velocity[2]) > 1) || (abs(particlesCPU[i].position[0] - resultGPUSimulation[i].position[0]) > 1)|| (abs(particlesCPU[i].position[1] - resultGPUSimulation[i].position[1]) > 1) || (abs(particlesCPU[i].position[2] - resultGPUSimulation[i].position[2]) > 1) )
{
flag_comparison = 1;
break;
}
}
if(flag_comparison == 0)
{
printf("Correct!");
}
else
{
printf("Incorrect!");
}
// clean up
free(particlesCPU);
hipFree(particlesGPU);
return 0;
} | .text
.file "exercise_3.hip"
.globl _Z10gen_randomiiii # -- Begin function _Z10gen_randomiiii
.p2align 4, 0x90
.type _Z10gen_randomiiii,@function
_Z10gen_randomiiii: # @_Z10gen_randomiiii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $edi killed $edi def $rdi
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
cvtsi2ss %edx, %xmm0
retq
.Lfunc_end0:
.size _Z10gen_randomiiii, .Lfunc_end0-_Z10gen_randomiiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__timestepP8particle4seedii # -- Begin function _Z23__device_stub__timestepP8particle4seedii
.p2align 4, 0x90
.type _Z23__device_stub__timestepP8particle4seedii,@function
_Z23__device_stub__timestepP8particle4seedii: # @_Z23__device_stub__timestepP8particle4seedii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 64(%rsp)
movl %edx, 72(%rsp)
movq %rdi, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8timestepP8particle4seedii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__timestepP8particle4seedii, .Lfunc_end1-_Z23__device_stub__timestepP8particle4seedii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jl .LBB2_9
# %bb.1: # %.lr.ph.preheader
movq %rsi, %r12
movl %edi, %ebp
movl $256, %eax # imm = 0x100
movq %rax, 8(%rsp) # 8-byte Spill
movl $100, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $10000, %ebx # imm = 0x2710
movl $1, %r13d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_2: # in Loop: Header=BB2_4 Depth=1
leal 1(%r15), %r13d
movq 8(%r12,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB2_3: # in Loop: Header=BB2_4 Depth=1
incl %r13d
cmpl %ebp, %r13d
jge .LBB2_10
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r13d, %r15
movq (%r12,%r15,8), %r14
movl $.L.str, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB2_2
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB2_8
# %bb.6: # in Loop: Header=BB2_4 Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB2_3
# %bb.7: # in Loop: Header=BB2_4 Depth=1
leal 1(%r15), %r13d
movq 8(%r12,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_4 Depth=1
leal 1(%r15), %r13d
movq 8(%r12,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB2_3
.LBB2_9:
movl $10000, %ebx # imm = 0x2710
movl $100, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $256, %eax # imm = 0x100
movq %rax, 8(%rsp) # 8-byte Spill
.LBB2_10: # %._crit_edge
movl %ebx, %eax
cltd
idivl 8(%rsp) # 4-byte Folded Reload
movl %eax, %ebp
movslq %ebx, %rax
shlq $3, %rax
leaq (%rax,%rax,2), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, 24(%rsp)
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r15
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebx, %r14d
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB2_16
# %bb.11: # %.preheader.lr.ph
movl (%rsp), %r8d # 4-byte Reload
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r9
xorl %r10d, %r10d
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_12: # %._crit_edge136
# in Loop: Header=BB2_13 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB2_16
.LBB2_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_15 Depth 2
testl %ebx, %ebx
jle .LBB2_12
# %bb.14: # %.lr.ph135.preheader
# in Loop: Header=BB2_13 Depth=1
movl %r10d, %ecx
movl %r10d, %esi
movl %r10d, %edi
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_15: # %.lr.ph135
# Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, %eax
xorl %edx, %edx
divl %ebx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 12(%r12,%r11)
movl %esi, %eax
xorl %edx, %edx
divl %ebx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm1, 16(%r12,%r11)
movl %ecx, %eax
xorl %edx, %edx
divl %ebx
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
movss %xmm2, 20(%r12,%r11)
addss (%r12,%r11), %xmm0
movss %xmm0, (%r12,%r11)
addss 4(%r12,%r11), %xmm1
movss %xmm1, 4(%r12,%r11)
addss 8(%r12,%r11), %xmm2
movss %xmm2, 8(%r12,%r11)
addq $24, %r11
addl $5, %edi
addl $6, %esi
addl $7, %ecx
cmpq %r11, %r9
jne .LBB2_15
jmp .LBB2_12
.LBB2_16: # %._crit_edge138
movq %r14, 80(%rsp) # 8-byte Spill
incl %ebp
movl %ebp, 20(%rsp) # 4-byte Spill
xorl %r13d, %r13d
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %r14 # imm = 0xF4240
addq 56(%rsp), %r14
subq 72(%rsp), %r14
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %ebx, %esi
movq %r15, %rbp
movq (%rsp), %r15 # 8-byte Reload
movl %r15d, %edx
movq %r14, %rcx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r15d, %r15d
movq %rbp, %r15
jle .LBB2_21
# %bb.17: # %.lr.ph141
movl 20(%rsp), %r14d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl 8(%rsp), %ebp # 4-byte Reload
orq %rax, %rbp
jmp .LBB2_19
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_19 Depth=1
callq hipDeviceSynchronize
incl %r13d
cmpl %r13d, (%rsp) # 4-byte Folded Reload
je .LBB2_21
.LBB2_19: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.20: # in Loop: Header=BB2_19 Depth=1
movq 24(%rsp), %rax
movabsq $25769803781, %rcx # imm = 0x600000005
movq %rcx, 144(%rsp)
movl $7, 152(%rsp)
movq %rax, 136(%rsp)
movl %r13d, 36(%rsp)
movl %ebx, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z8timestepP8particle4seedii, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_18
.LBB2_21: # %._crit_edge142
movq 24(%rsp), %rsi
movq %r15, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %r14 # imm = 0xF4240
addq 56(%rsp), %r14
subq 72(%rsp), %r14
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movl %ebx, %esi
movq (%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movq 8(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movl 20(%rsp), %r8d # 4-byte Reload
movq %r14, %r9
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB2_31
# %bb.22: # %.lr.ph146.preheader
movq 80(%rsp), %rax # 8-byte Reload
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl $.L.str.10, %edi
.p2align 4, 0x90
.LBB2_23: # %.lr.ph146
# =>This Inner Loop Header: Depth=1
movss 12(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 12(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.24: # in Loop: Header=BB2_23 Depth=1
movss 16(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 16(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.25: # in Loop: Header=BB2_23 Depth=1
movss 20(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 20(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.26: # in Loop: Header=BB2_23 Depth=1
movss (%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.27: # in Loop: Header=BB2_23 Depth=1
movss 4(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 4(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.28: # in Loop: Header=BB2_23 Depth=1
movss 8(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 8(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.29: # in Loop: Header=BB2_23 Depth=1
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB2_23
.LBB2_31:
movl $.L.str.9, %edi
.LBB2_32: # %.critedge
xorl %eax, %eax
callq printf
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8timestepP8particle4seedii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8timestepP8particle4seedii,@object # @_Z8timestepP8particle4seedii
.section .rodata,"a",@progbits
.globl _Z8timestepP8particle4seedii
.p2align 3, 0x0
_Z8timestepP8particle4seedii:
.quad _Z23__device_stub__timestepP8particle4seedii
.size _Z8timestepP8particle4seedii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-num_particles"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "-tpb"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "--num_iterations"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nComputing simulation on the CPU..."
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Done!"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds"
.size .L.str.5, 90
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n\nComputing simulation on the GPU..."
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds"
.size .L.str.7, 106
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n\nComparing the output for each implementation..."
.size .L.str.8, 50
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Correct!"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Incorrect!"
.size .L.str.10, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8timestepP8particle4seedii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__timestepP8particle4seedii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8timestepP8particle4seedii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8timestepP8particle4seedii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, 0x18 ; /* 0x00000018ff027424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fca00078e0202 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64+0x8] ; /* 0x0000080402007981 */
/* 0x000f22000c1e1900 */
/*00c0*/ IABS R6, c[0x0][0x178] ; /* 0x00005e0000067a13 */
/* 0x000fe40000000000 */
/*00d0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fc40000000f00 */
/*00e0*/ I2F.RP R10, R6 ; /* 0x00000006000a7306 */
/* 0x000e220000209400 */
/*00f0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x000fe40000000f00 */
/*0100*/ IMAD R7, R11, R12, c[0x0][0x174] ; /* 0x00005d000b077624 */
/* 0x000fe400078e020c */
/*0110*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0c7624 */
/* 0x000fc600078e00ff */
/*0120*/ IABS R15, R7 ; /* 0x00000007000f7213 */
/* 0x000fe20000000000 */
/*0130*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fe20007ffe0ff */
/*0150*/ IMAD R10, R11.reuse, R12, c[0x0][0x174] ; /* 0x00005d000b0a7624 */
/* 0x040fe400078e020c */
/*0160*/ IMAD R12, R11, R14, c[0x0][0x174] ; /* 0x00005d000b0c7624 */
/* 0x000fc600078e020e */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*0180*/ ISETP.GE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f86270 */
/*0190*/ IABS R17, R12 ; /* 0x0000000c00117213 */
/* 0x000fe40000000000 */
/*01a0*/ ISETP.GE.AND P5, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003fa6270 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*01c0*/ IMAD.MOV R13, RZ, RZ, -R9 ; /* 0x000000ffff0d7224 */
/* 0x002fc800078e0a09 */
/*01d0*/ IMAD R13, R13, R6, RZ ; /* 0x000000060d0d7224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R8, R9, R13, R8 ; /* 0x0000000d09087227 */
/* 0x000fe200078e0008 */
/*01f0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe40000000f00 */
/*0200*/ IABS R15, R10 ; /* 0x0000000a000f7213 */
/* 0x000fc60000000000 */
/*0210*/ IMAD.HI.U32 R9, R8, R13, RZ ; /* 0x0000000d08097227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.HI.U32 R11, R8, R15, RZ ; /* 0x0000000f080b7227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.HI.U32 R8, R8, R17, RZ ; /* 0x0000001108087227 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fc60007ffe1ff */
/*0250*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a09 */
/*0260*/ IMAD R11, R6.reuse, R11, R15 ; /* 0x0000000b060b7224 */
/* 0x040fe400078e020f */
/*0270*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0a08 */
/*0280*/ IMAD R9, R6.reuse, R9, R13 ; /* 0x0000000906097224 */
/* 0x040fe200078e020d */
/*0290*/ ISETP.GT.U32.AND P1, PT, R6.reuse, R11, PT ; /* 0x0000000b0600720c */
/* 0x040fe20003f24070 */
/*02a0*/ IMAD R13, R6.reuse, R8, R17 ; /* 0x00000008060d7224 */
/* 0x040fe200078e0211 */
/*02b0*/ LOP3.LUT R8, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff087a12 */
/* 0x000fe400078e33ff */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc40003f04070 */
/*02d0*/ ISETP.GT.U32.AND P2, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fce0003f44070 */
/*02e0*/ @!P1 IMAD.IADD R11, R11, 0x1, -R6 ; /* 0x000000010b0b9824 */
/* 0x000fc800078e0a06 */
/*02f0*/ @!P0 IADD3 R9, R9, -R6.reuse, RZ ; /* 0x8000000609098210 */
/* 0x080fe40007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P1, PT, R6.reuse, R11, PT ; /* 0x0000000b0600720c */
/* 0x040fe40003f24070 */
/*0310*/ @!P2 IADD3 R13, R13, -R6, RZ ; /* 0x800000060d0da210 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.GT.U32.AND P3, PT, R6.reuse, R9, PT ; /* 0x000000090600720c */
/* 0x040fe40003f64070 */
/*0330*/ ISETP.GT.U32.AND P2, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe40003f44070 */
/*0340*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f06270 */
/*0350*/ @!P1 IADD3 R11, R11, -R6, RZ ; /* 0x800000060b0b9210 */
/* 0x000fc80007ffe0ff */
/*0360*/ @!P3 IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x000000010909b824 */
/* 0x000fe200078e0a06 */
/*0370*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f65270 */
/*0380*/ @!P4 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0bc224 */
/* 0x000fe200078e0a0b */
/*0390*/ @!P2 IADD3 R13, R13, -R6, RZ ; /* 0x800000060d0da210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @!P0 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff098224 */
/* 0x000fc600078e0a09 */
/*03b0*/ @!P5 IADD3 R13, -R13, RZ, RZ ; /* 0x000000ff0d0dd210 */
/* 0x000fe40007ffe1ff */
/*03c0*/ SEL R9, R8.reuse, R9, !P3 ; /* 0x0000000908097207 */
/* 0x040fe40005800000 */
/*03d0*/ SEL R11, R8.reuse, R11, !P3 ; /* 0x0000000b080b7207 */
/* 0x040fe40005800000 */
/*03e0*/ SEL R8, R8, R13, !P3 ; /* 0x0000000d08087207 */
/* 0x000fe40005800000 */
/*03f0*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e300000201400 */
/*0400*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000e700000201400 */
/*0410*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x000f620000201400 */
/*0420*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x001fe8000c101904 */
/*0430*/ STG.E [R2.64+0x10], R11 ; /* 0x0000100b02007986 */
/* 0x002fe8000c101904 */
/*0440*/ STG.E [R2.64+0x14], R7 ; /* 0x0000140702007986 */
/* 0x020fe2000c101904 */
/*0450*/ FADD R5, R9, R5 ; /* 0x0000000509057221 */
/* 0x004fc40000000000 */
/*0460*/ FADD R13, R11, R4 ; /* 0x000000040b0d7221 */
/* 0x008fc60000000000 */
/*0470*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0480*/ FADD R15, R7, R0 ; /* 0x00000000070f7221 */
/* 0x010fc60000000000 */
/*0490*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8timestepP8particle4seedii
.globl _Z8timestepP8particle4seedii
.p2align 8
.type _Z8timestepP8particle4seedii,@function
_Z8timestepP8particle4seedii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_xor_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s3
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[7:8], null, v1, 24, s[4:5]
s_mov_b32 s2, s1
s_sub_i32 s4, 0, s3
v_mad_u64_u32 v[9:10], null, s7, v1, s[2:3]
v_mad_u64_u32 v[10:11], null, s0, v1, s[2:3]
global_load_b96 v[4:6], v[7:8], off
v_mad_u64_u32 v[2:3], null, s6, v1, s[2:3]
v_ashrrev_i32_e32 v11, 31, v9
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_ashrrev_i32_e32 v12, 31, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, v9, v11
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, v10, v12
v_mul_lo_u32 v3, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
v_xor_b32_e32 v3, v9, v11
v_xor_b32_e32 v9, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v13, v3, v0
v_mul_lo_u32 v13, v13, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v13
v_add_nc_u32_e32 v2, v2, v1
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v2, v0
v_mul_hi_u32 v0, v9, v0
v_mul_lo_u32 v10, v10, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v0, s3
v_sub_nc_u32_e32 v2, v2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v9, v0
v_subrev_nc_u32_e32 v10, s3, v3
v_subrev_nc_u32_e32 v9, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v13, s3, v0
v_cndmask_b32_e32 v2, v2, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s3, v2
v_cndmask_b32_e32 v3, v3, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_subrev_nc_u32_e32 v10, s3, v3
v_cndmask_b32_e32 v0, v0, v13, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s3, v0
v_cndmask_b32_e32 v2, v2, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_xor_b32_e32 v2, v2, v1
v_cndmask_b32_e32 v3, v3, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v2, v1
v_xor_b32_e32 v3, v3, v11
v_cndmask_b32_e32 v0, v0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v3, v11
v_xor_b32_e32 v0, v0, v12
v_cvt_f32_i32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v9, v2
v_sub_nc_u32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v10, v0
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v4, v3 :: v_dual_add_f32 v1, v5, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v2, v6, v10
s_clause 0x1
global_store_b64 v[7:8], v[9:10], off offset:16
global_store_b128 v[7:8], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8timestepP8particle4seedii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8timestepP8particle4seedii, .Lfunc_end0-_Z8timestepP8particle4seedii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 12
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8timestepP8particle4seedii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8timestepP8particle4seedii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e35e6_00000000-6_exercise_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10gen_randomiiii
.type _Z10gen_randomiiii, @function
_Z10gen_randomiiii:
.LFB2057:
.cfi_startproc
endbr64
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z10gen_randomiiii, .-_Z10gen_randomiiii
.globl _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
.type _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii, @function
_Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8timestepP8particle4seedii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii, .-_Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
.globl _Z8timestepP8particle4seedii
.type _Z8timestepP8particle4seedii, @function
_Z8timestepP8particle4seedii:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %edx, %eax
movl %ecx, %edx
movl %r8d, %ecx
movq %rsi, (%rsp)
movl %eax, 8(%rsp)
movq %rsp, %rsi
call _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8timestepP8particle4seedii, .-_Z8timestepP8particle4seedii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-num_particles"
.LC1:
.string "-tpb"
.LC2:
.string "--num_iterations"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\n\nComputing simulation on the CPU..."
.section .rodata.str1.1
.LC4:
.string "Done!"
.section .rodata.str1.8
.align 8
.LC5:
.string "\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds"
.align 8
.LC6:
.string "\n\nComputing simulation on the GPU..."
.align 8
.LC7:
.string "\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds"
.align 8
.LC8:
.string "\n\nComparing the output for each implementation..."
.section .rodata.str1.1
.LC11:
.string "Correct!"
.LC12:
.string "Incorrect!"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L13
movq %rsi, %r13
movl $256, 4(%rsp)
movl $100, %r15d
movl $10000, %ebx
movl $1, %ebp
movl %r15d, 8(%rsp)
movl %edi, %r15d
jmp .L17
.L40:
addl $1, %ebp
movq 8(%r13,%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
.L15:
addl $1, %ebp
cmpl %ebp, %r15d
jle .L39
.L17:
movslq %ebp, %rax
leaq 0(,%rax,8), %r14
movq 0(%r13,%rax,8), %r12
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L40
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L41
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L15
addl $1, %ebp
movq 8(%r13,%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
jmp .L15
.L41:
addl $1, %ebp
movq 8(%r13,%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L15
.L39:
movl 8(%rsp), %r15d
movl %ebx, %eax
cltd
idivl 4(%rsp)
leal 1(%rax), %r12d
movslq %ebx, %rax
leaq (%rax,%rax,2), %rbp
salq $3, %rbp
movq %rbp, 16(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %r15d, %r15d
jle .L18
.L31:
leal (%rbx,%rbx,4), %r9d
movl $0, %r10d
jmp .L19
.L22:
movl %r10d, %esi
movq %r14, %rcx
movl %r10d, %r8d
movl %r10d, %edi
.L20:
movl %esi, %eax
cltd
idivl %ebx
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movss %xmm2, 12(%rcx)
movl %edi, %eax
cltd
idivl %ebx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
movss %xmm1, 16(%rcx)
movl %r8d, %eax
cltd
idivl %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 20(%rcx)
addss (%rcx), %xmm2
movss %xmm2, (%rcx)
addss 4(%rcx), %xmm1
movss %xmm1, 4(%rcx)
addss 8(%rcx), %xmm0
movss %xmm0, 8(%rcx)
addl $5, %esi
addq $24, %rcx
addl $6, %edi
addl $7, %r8d
cmpl %r9d, %esi
jne .L20
.L23:
addl $1, %r10d
addl $1, %r9d
cmpl %r15d, %r10d
je .L21
.L19:
testl %ebx, %ebx
jg .L22
jmp .L23
.L21:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rbp
subq 80(%rsp), %rbp
imulq $1000000, %rbp, %rbp
addq 104(%rsp), %rbp
subq 88(%rsp), %rbp
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %r8
movl %r15d, %ecx
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %ebp
leaq 68(%rsp), %r13
movq %r14, 24(%rsp)
movl 4(%rsp), %r14d
jmp .L25
.L24:
call cudaDeviceSynchronize@PLT
addl $1, %ebp
cmpl %r15d, %ebp
je .L42
.L25:
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
movl $5, 68(%rsp)
movl $6, 72(%rsp)
movl $7, 76(%rsp)
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z8timestepP8particle4seediiP8particleR4seedii
jmp .L24
.L42:
movq 24(%rsp), %r14
.L29:
movl $2, %ecx
movq 16(%rsp), %r13
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rbp
subq 80(%rsp), %rbp
imulq $1000000, %rbp, %rbp
addq 104(%rsp), %rbp
subq 88(%rsp), %rbp
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbp
.cfi_def_cfa_offset 208
movl %r12d, %r9d
movl 20(%rsp), %r8d
movl %r15d, %ecx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L26
movq %r14, %rax
movq 8(%rsp), %rdx
movq %r13, %rdi
addq %r14, %rdi
movss .LC9(%rip), %xmm2
movss .LC10(%rip), %xmm1
movaps %xmm2, %xmm4
movaps %xmm1, %xmm3
movaps %xmm2, %xmm6
movaps %xmm1, %xmm5
movaps %xmm2, %xmm8
movaps %xmm1, %xmm7
movaps %xmm2, %xmm9
movaps %xmm2, %xmm10
.L28:
movss 12(%rax), %xmm0
subss 12(%rdx), %xmm0
andps %xmm2, %xmm0
comiss %xmm1, %xmm0
ja .L27
movss 16(%rax), %xmm0
subss 16(%rdx), %xmm0
andps %xmm4, %xmm0
comiss %xmm3, %xmm0
ja .L27
movss 20(%rax), %xmm0
subss 20(%rdx), %xmm0
andps %xmm6, %xmm0
comiss %xmm5, %xmm0
ja .L27
movss (%rax), %xmm0
subss (%rdx), %xmm0
andps %xmm8, %xmm0
comiss %xmm7, %xmm0
ja .L27
movss 4(%rax), %xmm0
subss 4(%rdx), %xmm0
andps %xmm9, %xmm0
comiss .LC10(%rip), %xmm0
ja .L27
movss 8(%rax), %xmm0
subss 8(%rdx), %xmm0
andps %xmm10, %xmm0
comiss .LC10(%rip), %xmm0
ja .L27
addq $24, %rax
addq $24, %rdx
cmpq %rdi, %rax
jne .L28
.L26:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L30:
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
imulq $1000000, %rax, %rax
addq 104(%rsp), %rax
subq 88(%rsp), %rax
movq %rax, %r13
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %r8
movl %r15d, %ecx
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L29
.L27:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L13:
movl $240000, %edi
call malloc@PLT
movq %rax, %r14
movl $240000, %edi
call malloc@PLT
movq %rax, 32(%rsp)
movl $240000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $256, 4(%rsp)
movl $100, %r15d
movl $10000, %ebx
movl $40, %r12d
movq $240000, 16(%rsp)
jmp .L31
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8timestepP8particle4seedii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8timestepP8particle4seedii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_3.hip"
.globl _Z10gen_randomiiii # -- Begin function _Z10gen_randomiiii
.p2align 4, 0x90
.type _Z10gen_randomiiii,@function
_Z10gen_randomiiii: # @_Z10gen_randomiiii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $edi killed $edi def $rdi
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
cvtsi2ss %edx, %xmm0
retq
.Lfunc_end0:
.size _Z10gen_randomiiii, .Lfunc_end0-_Z10gen_randomiiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__timestepP8particle4seedii # -- Begin function _Z23__device_stub__timestepP8particle4seedii
.p2align 4, 0x90
.type _Z23__device_stub__timestepP8particle4seedii,@function
_Z23__device_stub__timestepP8particle4seedii: # @_Z23__device_stub__timestepP8particle4seedii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 64(%rsp)
movl %edx, 72(%rsp)
movq %rdi, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8timestepP8particle4seedii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__timestepP8particle4seedii, .Lfunc_end1-_Z23__device_stub__timestepP8particle4seedii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jl .LBB2_9
# %bb.1: # %.lr.ph.preheader
movq %rsi, %r12
movl %edi, %ebp
movl $256, %eax # imm = 0x100
movq %rax, 8(%rsp) # 8-byte Spill
movl $100, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $10000, %ebx # imm = 0x2710
movl $1, %r13d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_2: # in Loop: Header=BB2_4 Depth=1
leal 1(%r15), %r13d
movq 8(%r12,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB2_3: # in Loop: Header=BB2_4 Depth=1
incl %r13d
cmpl %ebp, %r13d
jge .LBB2_10
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r13d, %r15
movq (%r12,%r15,8), %r14
movl $.L.str, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB2_2
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB2_8
# %bb.6: # in Loop: Header=BB2_4 Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB2_3
# %bb.7: # in Loop: Header=BB2_4 Depth=1
leal 1(%r15), %r13d
movq 8(%r12,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_4 Depth=1
leal 1(%r15), %r13d
movq 8(%r12,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB2_3
.LBB2_9:
movl $10000, %ebx # imm = 0x2710
movl $100, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $256, %eax # imm = 0x100
movq %rax, 8(%rsp) # 8-byte Spill
.LBB2_10: # %._crit_edge
movl %ebx, %eax
cltd
idivl 8(%rsp) # 4-byte Folded Reload
movl %eax, %ebp
movslq %ebx, %rax
shlq $3, %rax
leaq (%rax,%rax,2), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, 24(%rsp)
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r15
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebx, %r14d
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB2_16
# %bb.11: # %.preheader.lr.ph
movl (%rsp), %r8d # 4-byte Reload
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %r9
xorl %r10d, %r10d
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_12: # %._crit_edge136
# in Loop: Header=BB2_13 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB2_16
.LBB2_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_15 Depth 2
testl %ebx, %ebx
jle .LBB2_12
# %bb.14: # %.lr.ph135.preheader
# in Loop: Header=BB2_13 Depth=1
movl %r10d, %ecx
movl %r10d, %esi
movl %r10d, %edi
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_15: # %.lr.ph135
# Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, %eax
xorl %edx, %edx
divl %ebx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 12(%r12,%r11)
movl %esi, %eax
xorl %edx, %edx
divl %ebx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm1, 16(%r12,%r11)
movl %ecx, %eax
xorl %edx, %edx
divl %ebx
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
movss %xmm2, 20(%r12,%r11)
addss (%r12,%r11), %xmm0
movss %xmm0, (%r12,%r11)
addss 4(%r12,%r11), %xmm1
movss %xmm1, 4(%r12,%r11)
addss 8(%r12,%r11), %xmm2
movss %xmm2, 8(%r12,%r11)
addq $24, %r11
addl $5, %edi
addl $6, %esi
addl $7, %ecx
cmpq %r11, %r9
jne .LBB2_15
jmp .LBB2_12
.LBB2_16: # %._crit_edge138
movq %r14, 80(%rsp) # 8-byte Spill
incl %ebp
movl %ebp, 20(%rsp) # 4-byte Spill
xorl %r13d, %r13d
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %r14 # imm = 0xF4240
addq 56(%rsp), %r14
subq 72(%rsp), %r14
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %ebx, %esi
movq %r15, %rbp
movq (%rsp), %r15 # 8-byte Reload
movl %r15d, %edx
movq %r14, %rcx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r15d, %r15d
movq %rbp, %r15
jle .LBB2_21
# %bb.17: # %.lr.ph141
movl 20(%rsp), %r14d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl 8(%rsp), %ebp # 4-byte Reload
orq %rax, %rbp
jmp .LBB2_19
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_19 Depth=1
callq hipDeviceSynchronize
incl %r13d
cmpl %r13d, (%rsp) # 4-byte Folded Reload
je .LBB2_21
.LBB2_19: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.20: # in Loop: Header=BB2_19 Depth=1
movq 24(%rsp), %rax
movabsq $25769803781, %rcx # imm = 0x600000005
movq %rcx, 144(%rsp)
movl $7, 152(%rsp)
movq %rax, 136(%rsp)
movl %r13d, 36(%rsp)
movl %ebx, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z8timestepP8particle4seedii, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_18
.LBB2_21: # %._crit_edge142
movq 24(%rsp), %rsi
movq %r15, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000000, %rax, %r14 # imm = 0xF4240
addq 56(%rsp), %r14
subq 72(%rsp), %r14
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movl %ebx, %esi
movq (%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movq 8(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movl 20(%rsp), %r8d # 4-byte Reload
movq %r14, %r9
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB2_31
# %bb.22: # %.lr.ph146.preheader
movq 80(%rsp), %rax # 8-byte Reload
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl $.L.str.10, %edi
.p2align 4, 0x90
.LBB2_23: # %.lr.ph146
# =>This Inner Loop Header: Depth=1
movss 12(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 12(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.24: # in Loop: Header=BB2_23 Depth=1
movss 16(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 16(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.25: # in Loop: Header=BB2_23 Depth=1
movss 20(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 20(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.26: # in Loop: Header=BB2_23 Depth=1
movss (%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.27: # in Loop: Header=BB2_23 Depth=1
movss 4(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 4(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.28: # in Loop: Header=BB2_23 Depth=1
movss 8(%r12,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 8(%r15,%rcx), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
ja .LBB2_32
# %bb.29: # in Loop: Header=BB2_23 Depth=1
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB2_23
.LBB2_31:
movl $.L.str.9, %edi
.LBB2_32: # %.critedge
xorl %eax, %eax
callq printf
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8timestepP8particle4seedii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8timestepP8particle4seedii,@object # @_Z8timestepP8particle4seedii
.section .rodata,"a",@progbits
.globl _Z8timestepP8particle4seedii
.p2align 3, 0x0
_Z8timestepP8particle4seedii:
.quad _Z23__device_stub__timestepP8particle4seedii
.size _Z8timestepP8particle4seedii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-num_particles"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "-tpb"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "--num_iterations"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nComputing simulation on the CPU..."
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Done!"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n\nTotal time taken for %d particles and %d iterations on the CPU alone = %ld microseconds"
.size .L.str.5, 90
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n\nComputing simulation on the GPU..."
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n\nTotal time taken for %d particles, %d iterations, %d tpb and %d blocks using the GPU = %ld microseconds"
.size .L.str.7, 106
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n\nComparing the output for each implementation..."
.size .L.str.8, 50
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Correct!"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Incorrect!"
.size .L.str.10, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8timestepP8particle4seedii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__timestepP8particle4seedii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8timestepP8particle4seedii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "graph.hh"
#include "node.hh"
#include <algorithm>
#include <cassert>
#include <map>
#include <set>
#include <string>
#include <iostream>
namespace rt
{
Graph::~Graph()
{
for (auto n : nodes_)
delete n;
}
void Graph::add(Node* node)
{
assert(node);
nodes_.push_back(node);
}
void Graph::remove(Node* node)
{
assert(node);
auto it = std::find(nodes_.begin(), nodes_.end(), node);
assert(it != nodes_.end());
nodes_.erase(it);
for (auto x : node->preds)
{
auto pred_it = std::find(x->succs.begin(), x->succs.end(), node);
assert(pred_it != x->succs.end());
x->succs.erase(pred_it);
}
for (auto x : node->succs)
remove(x);
delete node;
}
const std::vector<Node*> Graph::nodes() const
{
return nodes_;
}
namespace
{
void add_preds(Node* node, std::set<Node*>& set)
{
if (!set.insert(node).second)
return;
for (auto x : node->preds)
add_preds(x, set);
}
std::vector<Node*> get_preds(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->preds)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
std::vector<Node*> get_succs(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->succs)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
}
/**
* L ← Empty list that will contain the sorted elements
* S ← Set of all nodes with no incoming edge
* while S is non-empty do
* remove a node n from S
* add n to tail of L
* for each node m with an edge e from n to m do
* remove edge e from the graph
* if m has no other incoming edges then
* insert m into S
* if graph has edges then
* return error (graph has at least one cycle)
* else
* return L (a topologically sorted order)
*/
std::vector<Node*> Graph::topological_sort(const std::vector<Node*>& vals)
{
std::vector<Node*> res;
std::set<Node*> graph;
for (auto n : vals)
add_preds(n, graph);
std::vector<Node*> s;
for (auto x : graph)
if (get_preds(x, graph).empty())
s.push_back(x);
while (!s.empty())
{
Node* next = s.back();
s.pop_back();
res.push_back(next);
for (auto succ : get_succs(next, graph))
{
if (get_preds(succ, graph).size() == 1)
s.push_back(succ);
}
graph.erase(next);
}
if (!graph.empty())
throw std::runtime_error {"Topological sort failed"};
return res;
}
namespace
{
std::string op_name(const Node* node,
std::map<const Node*, std::string>& names)
{
auto it = names.find(node);
if (it != names.end())
return it->second;
std::string res = node->type == Node::OP_NOP ? "nop"
: Node::OP_NAMES[node->type];
res += ":" + std::to_string(names.size());
names[node] = res;
return res;
}
}
utils::DotGraph Graph::to_dot_graph() const
{
std::map<const Node*, std::string> names;
utils::DotGraph g;
for (auto n : nodes_)
for (auto succ : n->succs)
g.add_edge(op_name(n, names), op_name(succ, names));
return g;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "graph.hh"
#include "node.hh"
#include <algorithm>
#include <cassert>
#include <map>
#include <set>
#include <string>
#include <iostream>
namespace rt
{
Graph::~Graph()
{
for (auto n : nodes_)
delete n;
}
void Graph::add(Node* node)
{
assert(node);
nodes_.push_back(node);
}
void Graph::remove(Node* node)
{
assert(node);
auto it = std::find(nodes_.begin(), nodes_.end(), node);
assert(it != nodes_.end());
nodes_.erase(it);
for (auto x : node->preds)
{
auto pred_it = std::find(x->succs.begin(), x->succs.end(), node);
assert(pred_it != x->succs.end());
x->succs.erase(pred_it);
}
for (auto x : node->succs)
remove(x);
delete node;
}
const std::vector<Node*> Graph::nodes() const
{
return nodes_;
}
namespace
{
void add_preds(Node* node, std::set<Node*>& set)
{
if (!set.insert(node).second)
return;
for (auto x : node->preds)
add_preds(x, set);
}
std::vector<Node*> get_preds(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->preds)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
std::vector<Node*> get_succs(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->succs)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
}
/**
* L ← Empty list that will contain the sorted elements
* S ← Set of all nodes with no incoming edge
* while S is non-empty do
* remove a node n from S
* add n to tail of L
* for each node m with an edge e from n to m do
* remove edge e from the graph
* if m has no other incoming edges then
* insert m into S
* if graph has edges then
* return error (graph has at least one cycle)
* else
* return L (a topologically sorted order)
*/
std::vector<Node*> Graph::topological_sort(const std::vector<Node*>& vals)
{
std::vector<Node*> res;
std::set<Node*> graph;
for (auto n : vals)
add_preds(n, graph);
std::vector<Node*> s;
for (auto x : graph)
if (get_preds(x, graph).empty())
s.push_back(x);
while (!s.empty())
{
Node* next = s.back();
s.pop_back();
res.push_back(next);
for (auto succ : get_succs(next, graph))
{
if (get_preds(succ, graph).size() == 1)
s.push_back(succ);
}
graph.erase(next);
}
if (!graph.empty())
throw std::runtime_error {"Topological sort failed"};
return res;
}
namespace
{
std::string op_name(const Node* node,
std::map<const Node*, std::string>& names)
{
auto it = names.find(node);
if (it != names.end())
return it->second;
std::string res = node->type == Node::OP_NOP ? "nop"
: Node::OP_NAMES[node->type];
res += ":" + std::to_string(names.size());
names[node] = res;
return res;
}
}
utils::DotGraph Graph::to_dot_graph() const
{
std::map<const Node*, std::string> names;
utils::DotGraph g;
for (auto n : nodes_)
for (auto succ : n->succs)
g.add_edge(op_name(n, names), op_name(succ, names));
return g;
}
} | #include <hip/hip_runtime.h>
#include "graph.hh"
#include "node.hh"
#include <algorithm>
#include <cassert>
#include <map>
#include <set>
#include <string>
#include <iostream>
namespace rt
{
Graph::~Graph()
{
for (auto n : nodes_)
delete n;
}
void Graph::add(Node* node)
{
assert(node);
nodes_.push_back(node);
}
void Graph::remove(Node* node)
{
assert(node);
auto it = std::find(nodes_.begin(), nodes_.end(), node);
assert(it != nodes_.end());
nodes_.erase(it);
for (auto x : node->preds)
{
auto pred_it = std::find(x->succs.begin(), x->succs.end(), node);
assert(pred_it != x->succs.end());
x->succs.erase(pred_it);
}
for (auto x : node->succs)
remove(x);
delete node;
}
const std::vector<Node*> Graph::nodes() const
{
return nodes_;
}
namespace
{
void add_preds(Node* node, std::set<Node*>& set)
{
if (!set.insert(node).second)
return;
for (auto x : node->preds)
add_preds(x, set);
}
std::vector<Node*> get_preds(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->preds)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
std::vector<Node*> get_succs(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->succs)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
}
/**
* L ← Empty list that will contain the sorted elements
* S ← Set of all nodes with no incoming edge
* while S is non-empty do
* remove a node n from S
* add n to tail of L
* for each node m with an edge e from n to m do
* remove edge e from the graph
* if m has no other incoming edges then
* insert m into S
* if graph has edges then
* return error (graph has at least one cycle)
* else
* return L (a topologically sorted order)
*/
std::vector<Node*> Graph::topological_sort(const std::vector<Node*>& vals)
{
std::vector<Node*> res;
std::set<Node*> graph;
for (auto n : vals)
add_preds(n, graph);
std::vector<Node*> s;
for (auto x : graph)
if (get_preds(x, graph).empty())
s.push_back(x);
while (!s.empty())
{
Node* next = s.back();
s.pop_back();
res.push_back(next);
for (auto succ : get_succs(next, graph))
{
if (get_preds(succ, graph).size() == 1)
s.push_back(succ);
}
graph.erase(next);
}
if (!graph.empty())
throw std::runtime_error {"Topological sort failed"};
return res;
}
namespace
{
std::string op_name(const Node* node,
std::map<const Node*, std::string>& names)
{
auto it = names.find(node);
if (it != names.end())
return it->second;
std::string res = node->type == Node::OP_NOP ? "nop"
: Node::OP_NAMES[node->type];
res += ":" + std::to_string(names.size());
names[node] = res;
return res;
}
}
utils::DotGraph Graph::to_dot_graph() const
{
std::map<const Node*, std::string> names;
utils::DotGraph g;
for (auto n : nodes_)
for (auto succ : n->succs)
g.add_edge(op_name(n, names), op_name(succ, names));
return g;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "graph.hh"
#include "node.hh"
#include <algorithm>
#include <cassert>
#include <map>
#include <set>
#include <string>
#include <iostream>
namespace rt
{
Graph::~Graph()
{
for (auto n : nodes_)
delete n;
}
void Graph::add(Node* node)
{
assert(node);
nodes_.push_back(node);
}
void Graph::remove(Node* node)
{
assert(node);
auto it = std::find(nodes_.begin(), nodes_.end(), node);
assert(it != nodes_.end());
nodes_.erase(it);
for (auto x : node->preds)
{
auto pred_it = std::find(x->succs.begin(), x->succs.end(), node);
assert(pred_it != x->succs.end());
x->succs.erase(pred_it);
}
for (auto x : node->succs)
remove(x);
delete node;
}
const std::vector<Node*> Graph::nodes() const
{
return nodes_;
}
namespace
{
void add_preds(Node* node, std::set<Node*>& set)
{
if (!set.insert(node).second)
return;
for (auto x : node->preds)
add_preds(x, set);
}
std::vector<Node*> get_preds(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->preds)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
std::vector<Node*> get_succs(Node* node, std::set<Node*>& graph)
{
std::vector<Node*> res;
for (auto x : node->succs)
if (graph.find(x) != graph.end())
res.push_back(x);
return res;
}
}
/**
* L ← Empty list that will contain the sorted elements
* S ← Set of all nodes with no incoming edge
* while S is non-empty do
* remove a node n from S
* add n to tail of L
* for each node m with an edge e from n to m do
* remove edge e from the graph
* if m has no other incoming edges then
* insert m into S
* if graph has edges then
* return error (graph has at least one cycle)
* else
* return L (a topologically sorted order)
*/
std::vector<Node*> Graph::topological_sort(const std::vector<Node*>& vals)
{
std::vector<Node*> res;
std::set<Node*> graph;
for (auto n : vals)
add_preds(n, graph);
std::vector<Node*> s;
for (auto x : graph)
if (get_preds(x, graph).empty())
s.push_back(x);
while (!s.empty())
{
Node* next = s.back();
s.pop_back();
res.push_back(next);
for (auto succ : get_succs(next, graph))
{
if (get_preds(succ, graph).size() == 1)
s.push_back(succ);
}
graph.erase(next);
}
if (!graph.empty())
throw std::runtime_error {"Topological sort failed"};
return res;
}
namespace
{
std::string op_name(const Node* node,
std::map<const Node*, std::string>& names)
{
auto it = names.find(node);
if (it != names.end())
return it->second;
std::string res = node->type == Node::OP_NOP ? "nop"
: Node::OP_NAMES[node->type];
res += ":" + std::to_string(names.size());
names[node] = res;
return res;
}
}
utils::DotGraph Graph::to_dot_graph() const
{
std::map<const Node*, std::string> names;
utils::DotGraph g;
for (auto n : nodes_)
for (auto succ : n->succs)
g.add_edge(op_name(n, names), op_name(succ, names));
return g;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
extern "C" int use_cuda(void)
{
int nDevices = 0;
cudaError_t err = cudaGetDeviceCount(&nDevices);
if (err != cudaSuccess) {
std::cerr << "Failed to retrieve the number of CUDA enabled devices"
<< std::endl;
return 1;
}
std::cout << "Found " << nDevices << " CUDA enabled devices" << std::endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
extern "C" int use_cuda(void)
{
int nDevices = 0;
cudaError_t err = cudaGetDeviceCount(&nDevices);
if (err != cudaSuccess) {
std::cerr << "Failed to retrieve the number of CUDA enabled devices"
<< std::endl;
return 1;
}
std::cout << "Found " << nDevices << " CUDA enabled devices" << std::endl;
return 0;
} | .file "tmpxft_0016dbfb_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to retrieve the number of CUDA enabled devices"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Found "
.LC2:
.string " CUDA enabled devices"
.text
.globl use_cuda
.type use_cuda, @function
use_cuda:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L16
movl $6, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $21, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L17
cmpb $0, 56(%rbp)
je .L12
movzbl 67(%rbp), %esi
.L13:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $53, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L19
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %eax
jmp .L3
.L19:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L20
call _ZSt16__throw_bad_castv@PLT
.L20:
call __stack_chk_fail@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L17:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L21
call _ZSt16__throw_bad_castv@PLT
.L21:
call __stack_chk_fail@PLT
.L12:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size use_cuda, .-use_cuda
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
extern "C" int use_cuda(void)
{
int nDevices = 0;
cudaError_t err = cudaGetDeviceCount(&nDevices);
if (err != cudaSuccess) {
std::cerr << "Failed to retrieve the number of CUDA enabled devices"
<< std::endl;
return 1;
}
std::cout << "Found " << nDevices << " CUDA enabled devices" << std::endl;
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
extern "C" int use_cuda(void)
{
int nDevices = 0;
hipError_t err = hipGetDeviceCount(&nDevices);
if (err != hipSuccess) {
std::cerr << "Failed to retrieve the number of CUDA enabled devices"
<< std::endl;
return 1;
}
std::cout << "Found " << nDevices << " CUDA enabled devices" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
extern "C" int use_cuda(void)
{
int nDevices = 0;
hipError_t err = hipGetDeviceCount(&nDevices);
if (err != hipSuccess) {
std::cerr << "Failed to retrieve the number of CUDA enabled devices"
<< std::endl;
return 1;
}
std::cout << "Found " << nDevices << " CUDA enabled devices" << std::endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
extern "C" int use_cuda(void)
{
int nDevices = 0;
hipError_t err = hipGetDeviceCount(&nDevices);
if (err != hipSuccess) {
std::cerr << "Failed to retrieve the number of CUDA enabled devices"
<< std::endl;
return 1;
}
std::cout << "Found " << nDevices << " CUDA enabled devices" << std::endl;
return 0;
} | .text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl use_cuda # -- Begin function use_cuda
.p2align 4, 0x90
.type use_cuda,@function
use_cuda: # @use_cuda
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB0_6
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $53, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_12
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB0_5
.LBB0_6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $21, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i3
cmpb $0, 56(%r14)
je .LBB0_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB0_10
.LBB0_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movl $1, %ebx
jmp .LBB0_11
.LBB0_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit6
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
xorl %ebx, %ebx
.LBB0_11:
movq %rax, %rdi
callq _ZNSo5flushEv
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size use_cuda, .Lfunc_end0-use_cuda
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to retrieve the number of CUDA enabled devices"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Found "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " CUDA enabled devices"
.size .L.str.2, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016dbfb_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to retrieve the number of CUDA enabled devices"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Found "
.LC2:
.string " CUDA enabled devices"
.text
.globl use_cuda
.type use_cuda, @function
use_cuda:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L16
movl $6, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $21, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L17
cmpb $0, 56(%rbp)
je .L12
movzbl 67(%rbp), %esi
.L13:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $53, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L19
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %eax
jmp .L3
.L19:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L20
call _ZSt16__throw_bad_castv@PLT
.L20:
call __stack_chk_fail@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L17:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L21
call _ZSt16__throw_bad_castv@PLT
.L21:
call __stack_chk_fail@PLT
.L12:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size use_cuda, .-use_cuda
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl use_cuda # -- Begin function use_cuda
.p2align 4, 0x90
.type use_cuda,@function
use_cuda: # @use_cuda
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB0_6
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $53, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_12
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB0_5
.LBB0_6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $21, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i3
cmpb $0, 56(%r14)
je .LBB0_9
# %bb.8:
movzbl 67(%r14), %eax
jmp .LBB0_10
.LBB0_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movl $1, %ebx
jmp .LBB0_11
.LBB0_9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit6
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
xorl %ebx, %ebx
.LBB0_11:
movq %rax, %rdi
callq _ZNSo5flushEv
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size use_cuda, .Lfunc_end0-use_cuda
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to retrieve the number of CUDA enabled devices"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Found "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " CUDA enabled devices"
.size .L.str.2, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <memory>
#include "cuda_runtime.h"
__global__ void add_two_vectors(int* v1, int* v2, int* result){
int idx = threadIdx.x;
result[idx] = v1[idx] + v2[idx];
//printf("%i, ",result[idx]);
}
int main(int argc, char **argv) {
int* v1_host = (int*)malloc(64*sizeof(int));
int* v2_host = (int*)malloc(64*sizeof(int));
int* result_host = (int*)malloc(64*sizeof(int));
//memset(v1_host,64,1);
//memset(v2_host,64,2);
for(int i=0;i<64;i++){
v1_host[i] = 1;
v2_host[i] = 2;
}
int* v1_dev;
int* v2_dev;
int* result_dev;
cudaMalloc(&v1_dev, 64*sizeof(int));
cudaMalloc(&v2_dev, 64*sizeof(int));
cudaMalloc(&result_dev, 64*sizeof(int));
//copy memory
cudaMemcpy(v1_dev,v1_host,64*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(v2_dev,v2_host,64*sizeof(int),cudaMemcpyHostToDevice);
//launch kernel
dim3 grid(1,1,1);
dim3 block(64,1,1);
add_two_vectors<<<grid, block>>>(v1_dev, v2_dev, result_dev);
//sync
cudaDeviceSynchronize();
//copy memory from device to host
cudaMemcpy(result_host, result_dev, 64*sizeof(int),cudaMemcpyDeviceToHost);
for(int i=0;i<64;i++){
printf("%i, ",result_host[i]);
}
free(v1_host);
free(v2_host);
free(result_host);
cudaFree(v1_dev);
cudaFree(v2_dev);
cudaFree(result_dev);
std::shared_ptr<int> iptr = std::make_shared<int>(4);
printf("%i",*iptr);
} | code for sm_80
Function : _Z15add_two_vectorsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <memory>
#include "cuda_runtime.h"
__global__ void add_two_vectors(int* v1, int* v2, int* result){
int idx = threadIdx.x;
result[idx] = v1[idx] + v2[idx];
//printf("%i, ",result[idx]);
}
int main(int argc, char **argv) {
int* v1_host = (int*)malloc(64*sizeof(int));
int* v2_host = (int*)malloc(64*sizeof(int));
int* result_host = (int*)malloc(64*sizeof(int));
//memset(v1_host,64,1);
//memset(v2_host,64,2);
for(int i=0;i<64;i++){
v1_host[i] = 1;
v2_host[i] = 2;
}
int* v1_dev;
int* v2_dev;
int* result_dev;
cudaMalloc(&v1_dev, 64*sizeof(int));
cudaMalloc(&v2_dev, 64*sizeof(int));
cudaMalloc(&result_dev, 64*sizeof(int));
//copy memory
cudaMemcpy(v1_dev,v1_host,64*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(v2_dev,v2_host,64*sizeof(int),cudaMemcpyHostToDevice);
//launch kernel
dim3 grid(1,1,1);
dim3 block(64,1,1);
add_two_vectors<<<grid, block>>>(v1_dev, v2_dev, result_dev);
//sync
cudaDeviceSynchronize();
//copy memory from device to host
cudaMemcpy(result_host, result_dev, 64*sizeof(int),cudaMemcpyDeviceToHost);
for(int i=0;i<64;i++){
printf("%i, ",result_host[i]);
}
free(v1_host);
free(v2_host);
free(result_host);
cudaFree(v1_dev);
cudaFree(v2_dev);
cudaFree(result_dev);
std::shared_ptr<int> iptr = std::make_shared<int>(4);
printf("%i",*iptr);
} | .file "tmpxft_001bc66b_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED5Ev,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev:
.LFB5051:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE5051:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev
.set _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv:
.LFB5054:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE5054:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info:
.LFB5056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq 16(%rdi), %rbx
leaq _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag(%rip), %rax
cmpq %rax, %rsi
je .L3
movq 8(%rsi), %rdi
leaq _ZTSSt19_Sp_make_shared_tag(%rip), %rax
cmpq %rax, %rdi
je .L3
cmpb $42, (%rdi)
je .L5
movq %rax, %rsi
call strcmp@PLT
testl %eax, %eax
movl $0, %eax
cmovne %rax, %rbx
.L3:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
movl $0, %ebx
jmp .L3
.cfi_endproc
.LFE5056:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED5Ev,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev:
.LFB5053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $24, %esi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5053:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv:
.LFB5055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $24, %esi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5055:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4322:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4322:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
.type _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_, @function
_Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_:
.LFB4344:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15add_two_vectorsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4344:
.size _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_, .-_Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
.globl _Z15add_two_vectorsPiS_S_
.type _Z15add_two_vectorsPiS_S_, @function
_Z15add_two_vectorsPiS_S_:
.LFB4345:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4345:
.size _Z15add_two_vectorsPiS_S_, .-_Z15add_two_vectorsPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15add_two_vectorsPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4347:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15add_two_vectorsPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4347:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,comdat
.align 2
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, @function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv:
.LFB4651:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rax
call *16(%rax)
cmpb $0, __libc_single_threaded(%rip)
je .L24
movl 12(%rbx), %eax
leal -1(%rax), %edx
movl %edx, 12(%rbx)
.L25:
cmpl $1, %eax
je .L28
.L23:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $-1, %eax
lock xaddl %eax, 12(%rbx)
jmp .L25
.L28:
movq (%rbx), %rax
movq %rbx, %rdi
call *24(%rax)
jmp .L23
.cfi_endproc
.LFE4651:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, .-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv,comdat
.align 2
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv, @function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv:
.LFB3916:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdx
movabsq $4294967297, %rax
cmpq %rax, %rdx
je .L35
leaq 8(%rdi), %rcx
cmpb $0, __libc_single_threaded(%rip)
je .L32
movl 8(%rdi), %eax
leal -1(%rax), %edx
movl %edx, 8(%rdi)
.L33:
cmpl $1, %eax
je .L36
.L29:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $0, 8(%rdi)
movl $0, 12(%rdi)
movq (%rdi), %rax
call *16(%rax)
movq (%rbx), %rax
movq %rbx, %rdi
call *24(%rax)
jmp .L29
.L32:
movl $-1, %eax
lock xaddl %eax, (%rcx)
jmp .L33
.L36:
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
jmp .L29
.cfi_endproc
.LFE3916:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv, .-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
.section .rodata.str1.1
.LC1:
.string "%i, "
.LC2:
.string "%i"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4313
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
.L38:
movl $1, (%r12,%rax)
movl $2, 0(%rbp,%rax)
addq $4, %rax
cmpq $256, %rax
jne .L38
leaq 8(%rsp), %rdi
movl $256, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $256, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L39:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbx
leaq 256(%r14), %r15
leaq .LC1(%rip), %r13
.L40:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L40
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $24, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movl $1, 8(%rax)
movl $1, 12(%rax)
leaq 16+_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE(%rip), %rax
movq %rax, (%rbx)
movl $4, 16(%rbx)
movl $4, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
jmp .L50
.L49:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
.LEHB2:
call _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
jmp .L39
.L50:
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
endbr64
movq %rax, %rbp
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbp, %rdi
call _Unwind_Resume@PLT
.LEHE2:
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4313:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4313-.LLSDACSB4313
.LLSDACSB4313:
.uleb128 .LEHB0-.LFB4313
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4313
.uleb128 .LEHE1-.LEHB1
.uleb128 .L44-.LFB4313
.uleb128 0
.uleb128 .LEHB2-.LFB4313
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4313:
.text
.size main, .-main
.weak _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 47
_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.string "St11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 16
_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.weak _ZTSSt19_Sp_make_shared_tag
.section .rodata._ZTSSt19_Sp_make_shared_tag,"aG",@progbits,_ZTSSt19_Sp_make_shared_tag,comdat
.align 16
.type _ZTSSt19_Sp_make_shared_tag, @object
.size _ZTSSt19_Sp_make_shared_tag, 24
_ZTSSt19_Sp_make_shared_tag:
.string "St19_Sp_make_shared_tag"
.weak _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 52
_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.string "St16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 24
_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.weak _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 65
_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.string "St23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 24
_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.weak _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro.local._ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 56
_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.section .rodata._ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,"aG",@progbits,_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,comdat
.align 8
.type _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, @gnu_unique_object
.size _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, 16
_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag:
.zero 16
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <memory>
#include "cuda_runtime.h"
__global__ void add_two_vectors(int* v1, int* v2, int* result){
int idx = threadIdx.x;
result[idx] = v1[idx] + v2[idx];
//printf("%i, ",result[idx]);
}
int main(int argc, char **argv) {
int* v1_host = (int*)malloc(64*sizeof(int));
int* v2_host = (int*)malloc(64*sizeof(int));
int* result_host = (int*)malloc(64*sizeof(int));
//memset(v1_host,64,1);
//memset(v2_host,64,2);
for(int i=0;i<64;i++){
v1_host[i] = 1;
v2_host[i] = 2;
}
int* v1_dev;
int* v2_dev;
int* result_dev;
cudaMalloc(&v1_dev, 64*sizeof(int));
cudaMalloc(&v2_dev, 64*sizeof(int));
cudaMalloc(&result_dev, 64*sizeof(int));
//copy memory
cudaMemcpy(v1_dev,v1_host,64*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(v2_dev,v2_host,64*sizeof(int),cudaMemcpyHostToDevice);
//launch kernel
dim3 grid(1,1,1);
dim3 block(64,1,1);
add_two_vectors<<<grid, block>>>(v1_dev, v2_dev, result_dev);
//sync
cudaDeviceSynchronize();
//copy memory from device to host
cudaMemcpy(result_host, result_dev, 64*sizeof(int),cudaMemcpyDeviceToHost);
for(int i=0;i<64;i++){
printf("%i, ",result_host[i]);
}
free(v1_host);
free(v2_host);
free(result_host);
cudaFree(v1_dev);
cudaFree(v2_dev);
cudaFree(result_dev);
std::shared_ptr<int> iptr = std::make_shared<int>(4);
printf("%i",*iptr);
} | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <memory>
#include "hip/hip_runtime.h"
__global__ void add_two_vectors(int* v1, int* v2, int* result){
int idx = threadIdx.x;
result[idx] = v1[idx] + v2[idx];
//printf("%i, ",result[idx]);
}
int main(int argc, char **argv) {
int* v1_host = (int*)malloc(64*sizeof(int));
int* v2_host = (int*)malloc(64*sizeof(int));
int* result_host = (int*)malloc(64*sizeof(int));
//memset(v1_host,64,1);
//memset(v2_host,64,2);
for(int i=0;i<64;i++){
v1_host[i] = 1;
v2_host[i] = 2;
}
int* v1_dev;
int* v2_dev;
int* result_dev;
hipMalloc(&v1_dev, 64*sizeof(int));
hipMalloc(&v2_dev, 64*sizeof(int));
hipMalloc(&result_dev, 64*sizeof(int));
//copy memory
hipMemcpy(v1_dev,v1_host,64*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(v2_dev,v2_host,64*sizeof(int),hipMemcpyHostToDevice);
//launch kernel
dim3 grid(1,1,1);
dim3 block(64,1,1);
add_two_vectors<<<grid, block>>>(v1_dev, v2_dev, result_dev);
//sync
hipDeviceSynchronize();
//copy memory from device to host
hipMemcpy(result_host, result_dev, 64*sizeof(int),hipMemcpyDeviceToHost);
for(int i=0;i<64;i++){
printf("%i, ",result_host[i]);
}
free(v1_host);
free(v2_host);
free(result_host);
hipFree(v1_dev);
hipFree(v2_dev);
hipFree(result_dev);
std::shared_ptr<int> iptr = std::make_shared<int>(4);
printf("%i",*iptr);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <memory>
#include "hip/hip_runtime.h"
__global__ void add_two_vectors(int* v1, int* v2, int* result){
int idx = threadIdx.x;
result[idx] = v1[idx] + v2[idx];
//printf("%i, ",result[idx]);
}
int main(int argc, char **argv) {
int* v1_host = (int*)malloc(64*sizeof(int));
int* v2_host = (int*)malloc(64*sizeof(int));
int* result_host = (int*)malloc(64*sizeof(int));
//memset(v1_host,64,1);
//memset(v2_host,64,2);
for(int i=0;i<64;i++){
v1_host[i] = 1;
v2_host[i] = 2;
}
int* v1_dev;
int* v2_dev;
int* result_dev;
hipMalloc(&v1_dev, 64*sizeof(int));
hipMalloc(&v2_dev, 64*sizeof(int));
hipMalloc(&result_dev, 64*sizeof(int));
//copy memory
hipMemcpy(v1_dev,v1_host,64*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(v2_dev,v2_host,64*sizeof(int),hipMemcpyHostToDevice);
//launch kernel
dim3 grid(1,1,1);
dim3 block(64,1,1);
add_two_vectors<<<grid, block>>>(v1_dev, v2_dev, result_dev);
//sync
hipDeviceSynchronize();
//copy memory from device to host
hipMemcpy(result_host, result_dev, 64*sizeof(int),hipMemcpyDeviceToHost);
for(int i=0;i<64;i++){
printf("%i, ",result_host[i]);
}
free(v1_host);
free(v2_host);
free(result_host);
hipFree(v1_dev);
hipFree(v2_dev);
hipFree(result_dev);
std::shared_ptr<int> iptr = std::make_shared<int>(4);
printf("%i",*iptr);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15add_two_vectorsPiS_S_
.globl _Z15add_two_vectorsPiS_S_
.p2align 8
.type _Z15add_two_vectorsPiS_S_,@function
_Z15add_two_vectorsPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15add_two_vectorsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15add_two_vectorsPiS_S_, .Lfunc_end0-_Z15add_two_vectorsPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15add_two_vectorsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z15add_two_vectorsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <memory>
#include "hip/hip_runtime.h"
__global__ void add_two_vectors(int* v1, int* v2, int* result){
int idx = threadIdx.x;
result[idx] = v1[idx] + v2[idx];
//printf("%i, ",result[idx]);
}
int main(int argc, char **argv) {
int* v1_host = (int*)malloc(64*sizeof(int));
int* v2_host = (int*)malloc(64*sizeof(int));
int* result_host = (int*)malloc(64*sizeof(int));
//memset(v1_host,64,1);
//memset(v2_host,64,2);
for(int i=0;i<64;i++){
v1_host[i] = 1;
v2_host[i] = 2;
}
int* v1_dev;
int* v2_dev;
int* result_dev;
hipMalloc(&v1_dev, 64*sizeof(int));
hipMalloc(&v2_dev, 64*sizeof(int));
hipMalloc(&result_dev, 64*sizeof(int));
//copy memory
hipMemcpy(v1_dev,v1_host,64*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(v2_dev,v2_host,64*sizeof(int),hipMemcpyHostToDevice);
//launch kernel
dim3 grid(1,1,1);
dim3 block(64,1,1);
add_two_vectors<<<grid, block>>>(v1_dev, v2_dev, result_dev);
//sync
hipDeviceSynchronize();
//copy memory from device to host
hipMemcpy(result_host, result_dev, 64*sizeof(int),hipMemcpyDeviceToHost);
for(int i=0;i<64;i++){
printf("%i, ",result_host[i]);
}
free(v1_host);
free(v2_host);
free(result_host);
hipFree(v1_dev);
hipFree(v2_dev);
hipFree(result_dev);
std::shared_ptr<int> iptr = std::make_shared<int>(4);
printf("%i",*iptr);
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__add_two_vectorsPiS_S_ # -- Begin function _Z30__device_stub__add_two_vectorsPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__add_two_vectorsPiS_S_,@function
_Z30__device_stub__add_two_vectorsPiS_S_: # @_Z30__device_stub__add_two_vectorsPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15add_two_vectorsPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__add_two_vectorsPiS_S_, .Lfunc_end0-_Z30__device_stub__add_two_vectorsPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r15
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
movl $2, (%r15,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 16(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 63(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15add_two_vectorsPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $64, %r13
jne .LBB1_5
# %bb.6:
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $24, %edi
callq _Znwm
movq %rax, %r14
movq %rbx, 8(%rax)
movq $_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE+16, (%rax)
movl $4, 16(%rax)
movl $.L.str.1, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
movq 8(%r14), %rax
cmpq %rbx, %rax
jne .LBB1_8
# %bb.7:
movq $0, 8(%r14)
movq (%r14), %rax
movq %r14, %rdi
callq *16(%rax)
movq (%r14), %rax
movq %r14, %rdi
callq *24(%rax)
jmp .LBB1_13
.LBB1_8:
cmpb $0, __libc_single_threaded(%rip)
je .LBB1_10
# %bb.9:
movl 8(%r14), %eax
leal -1(%rax), %ecx
movl %ecx, 8(%r14)
cmpl $1, %eax
je .LBB1_12
.LBB1_13: # %_ZNSt12__shared_ptrIiLN9__gnu_cxx12_Lock_policyE2EED2Ev.exit
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 176
movl $-1, %eax
lock xaddl %eax, 8(%r14)
cmpl $1, %eax
jne .LBB1_13
.LBB1_12:
movq %r14, %rdi
callq _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
jmp .LBB1_13
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rax
callq *16(%rax)
cmpb $0, __libc_single_threaded(%rip)
je .LBB2_2
# %bb.1:
movl 12(%rbx), %eax
leal -1(%rax), %ecx
movl %ecx, 12(%rbx)
cmpl $1, %eax
jne .LBB2_4
.LBB2_5:
movq (%rbx), %rax
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmpq *24(%rax) # TAILCALL
.LBB2_2:
.cfi_def_cfa_offset 16
movl $-1, %eax
lock xaddl %eax, 12(%rbx)
cmpl $1, %eax
je .LBB2_5
.LBB2_4: # %_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE19_M_release_last_useEv.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, .Lfunc_end2-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_startproc
# %bb.0:
retq
.Lfunc_end3:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev, .Lfunc_end3-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_startproc
# %bb.0:
jmp _ZdlPv # TAILCALL
.Lfunc_end4:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, .Lfunc_end4-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end5:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, .Lfunc_end5-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_startproc
# %bb.0: # %_ZNSt15__allocated_ptrISaISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EEEED2Ev.exit
jmp _ZdlPv # TAILCALL
.Lfunc_end6:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .Lfunc_end6-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.cfi_startproc
# %bb.0:
movq %rdi, %rax
addq $16, %rax
cmpq $_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, %rsi
je .LBB7_5
# %bb.1:
movq 8(%rsi), %rdi
cmpq $_ZTSSt19_Sp_make_shared_tag, %rdi
je .LBB7_5
# %bb.2:
cmpb $42, (%rdi)
jne .LBB7_4
# %bb.3:
xorl %eax, %eax
retq
.LBB7_4:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZTSSt19_Sp_make_shared_tag, %esi
movq %rax, %rbx
callq strcmp
movl %eax, %ecx
movq %rbx, %rax
xorl %edx, %edx
testl %ecx, %ecx
cmovneq %rdx, %rax
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB7_5: # %_ZNKSt9type_infoeqERKS_.exit
retq
.Lfunc_end7:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, .Lfunc_end7-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_startproc
# %bb.0:
ud2
.Lfunc_end8:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev, .Lfunc_end8-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
jmpq *8(%rax) # TAILCALL
.Lfunc_end9:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .Lfunc_end9-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15add_two_vectorsPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15add_two_vectorsPiS_S_,@object # @_Z15add_two_vectorsPiS_S_
.section .rodata,"a",@progbits
.globl _Z15add_two_vectorsPiS_S_
.p2align 3, 0x0
_Z15add_two_vectorsPiS_S_:
.quad _Z30__device_stub__add_two_vectorsPiS_S_
.size _Z15add_two_vectorsPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i, "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%i"
.size .L.str.1, 3
.type _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.size _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 56
.type _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 65
.type _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 52
.type _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 47
.type _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 16
.type _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 24
.type _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 24
.type _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad __cxa_pure_virtual
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad __cxa_pure_virtual
.size _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 56
.type _ZTSSt19_Sp_make_shared_tag,@object # @_ZTSSt19_Sp_make_shared_tag
.section .rodata._ZTSSt19_Sp_make_shared_tag,"aG",@progbits,_ZTSSt19_Sp_make_shared_tag,comdat
.weak _ZTSSt19_Sp_make_shared_tag
_ZTSSt19_Sp_make_shared_tag:
.asciz "St19_Sp_make_shared_tag"
.size _ZTSSt19_Sp_make_shared_tag, 24
.type _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,@object # @_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.section .rodata._ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,"aG",@progbits,_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,comdat
.weak _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.p2align 3, 0x0
_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag:
.zero 16
.size _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, 16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15add_two_vectorsPiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__add_two_vectorsPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15add_two_vectorsPiS_S_
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTSSt19_Sp_make_shared_tag
.addrsig_sym _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15add_two_vectorsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15add_two_vectorsPiS_S_
.globl _Z15add_two_vectorsPiS_S_
.p2align 8
.type _Z15add_two_vectorsPiS_S_,@function
_Z15add_two_vectorsPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15add_two_vectorsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15add_two_vectorsPiS_S_, .Lfunc_end0-_Z15add_two_vectorsPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15add_two_vectorsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z15add_two_vectorsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bc66b_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED5Ev,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev:
.LFB5051:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE5051:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev
.set _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv:
.LFB5054:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE5054:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info:
.LFB5056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq 16(%rdi), %rbx
leaq _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag(%rip), %rax
cmpq %rax, %rsi
je .L3
movq 8(%rsi), %rdi
leaq _ZTSSt19_Sp_make_shared_tag(%rip), %rax
cmpq %rax, %rdi
je .L3
cmpb $42, (%rdi)
je .L5
movq %rax, %rsi
call strcmp@PLT
testl %eax, %eax
movl $0, %eax
cmovne %rax, %rbx
.L3:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
movl $0, %ebx
jmp .L3
.cfi_endproc
.LFE5056:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED5Ev,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev:
.LFB5053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $24, %esi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5053:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.align 2
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, @function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv:
.LFB5055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $24, %esi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5055:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4322:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4322:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
.type _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_, @function
_Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_:
.LFB4344:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15add_two_vectorsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4344:
.size _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_, .-_Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
.globl _Z15add_two_vectorsPiS_S_
.type _Z15add_two_vectorsPiS_S_, @function
_Z15add_two_vectorsPiS_S_:
.LFB4345:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4345:
.size _Z15add_two_vectorsPiS_S_, .-_Z15add_two_vectorsPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15add_two_vectorsPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4347:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15add_two_vectorsPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4347:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,comdat
.align 2
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, @function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv:
.LFB4651:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rax
call *16(%rax)
cmpb $0, __libc_single_threaded(%rip)
je .L24
movl 12(%rbx), %eax
leal -1(%rax), %edx
movl %edx, 12(%rbx)
.L25:
cmpl $1, %eax
je .L28
.L23:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $-1, %eax
lock xaddl %eax, 12(%rbx)
jmp .L25
.L28:
movq (%rbx), %rax
movq %rbx, %rdi
call *24(%rax)
jmp .L23
.cfi_endproc
.LFE4651:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, .-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv,comdat
.align 2
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv, @function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv:
.LFB3916:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdx
movabsq $4294967297, %rax
cmpq %rax, %rdx
je .L35
leaq 8(%rdi), %rcx
cmpb $0, __libc_single_threaded(%rip)
je .L32
movl 8(%rdi), %eax
leal -1(%rax), %edx
movl %edx, 8(%rdi)
.L33:
cmpl $1, %eax
je .L36
.L29:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $0, 8(%rdi)
movl $0, 12(%rdi)
movq (%rdi), %rax
call *16(%rax)
movq (%rbx), %rax
movq %rbx, %rdi
call *24(%rax)
jmp .L29
.L32:
movl $-1, %eax
lock xaddl %eax, (%rcx)
jmp .L33
.L36:
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
jmp .L29
.cfi_endproc
.LFE3916:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv, .-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
.section .rodata.str1.1
.LC1:
.string "%i, "
.LC2:
.string "%i"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4313
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
.L38:
movl $1, (%r12,%rax)
movl $2, 0(%rbp,%rax)
addq $4, %rax
cmpq $256, %rax
jne .L38
leaq 8(%rsp), %rdi
movl $256, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $256, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L39:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbx
leaq 256(%r14), %r15
leaq .LC1(%rip), %r13
.L40:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L40
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $24, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movl $1, 8(%rax)
movl $1, 12(%rax)
leaq 16+_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE(%rip), %rax
movq %rax, (%rbx)
movl $4, 16(%rbx)
movl $4, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
jmp .L50
.L49:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
.LEHB2:
call _Z39__device_stub__Z15add_two_vectorsPiS_S_PiS_S_
jmp .L39
.L50:
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
endbr64
movq %rax, %rbp
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbp, %rdi
call _Unwind_Resume@PLT
.LEHE2:
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4313:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4313-.LLSDACSB4313
.LLSDACSB4313:
.uleb128 .LEHB0-.LFB4313
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4313
.uleb128 .LEHE1-.LEHB1
.uleb128 .L44-.LFB4313
.uleb128 0
.uleb128 .LEHB2-.LFB4313
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4313:
.text
.size main, .-main
.weak _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 47
_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.string "St11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 16
_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.weak _ZTSSt19_Sp_make_shared_tag
.section .rodata._ZTSSt19_Sp_make_shared_tag,"aG",@progbits,_ZTSSt19_Sp_make_shared_tag,comdat
.align 16
.type _ZTSSt19_Sp_make_shared_tag, @object
.size _ZTSSt19_Sp_make_shared_tag, 24
_ZTSSt19_Sp_make_shared_tag:
.string "St19_Sp_make_shared_tag"
.weak _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 52
_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.string "St16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 24
_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.weak _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 65
_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.string "St23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 24
_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.weak _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro.local._ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 56
_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.section .rodata._ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,"aG",@progbits,_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,comdat
.align 8
.type _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, @gnu_unique_object
.size _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, 16
_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag:
.zero 16
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__add_two_vectorsPiS_S_ # -- Begin function _Z30__device_stub__add_two_vectorsPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__add_two_vectorsPiS_S_,@function
_Z30__device_stub__add_two_vectorsPiS_S_: # @_Z30__device_stub__add_two_vectorsPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15add_two_vectorsPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__add_two_vectorsPiS_S_, .Lfunc_end0-_Z30__device_stub__add_two_vectorsPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r15
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
movl $2, (%r15,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 16(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 63(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15add_two_vectorsPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $64, %r13
jne .LBB1_5
# %bb.6:
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $24, %edi
callq _Znwm
movq %rax, %r14
movq %rbx, 8(%rax)
movq $_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE+16, (%rax)
movl $4, 16(%rax)
movl $.L.str.1, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
movq 8(%r14), %rax
cmpq %rbx, %rax
jne .LBB1_8
# %bb.7:
movq $0, 8(%r14)
movq (%r14), %rax
movq %r14, %rdi
callq *16(%rax)
movq (%r14), %rax
movq %r14, %rdi
callq *24(%rax)
jmp .LBB1_13
.LBB1_8:
cmpb $0, __libc_single_threaded(%rip)
je .LBB1_10
# %bb.9:
movl 8(%r14), %eax
leal -1(%rax), %ecx
movl %ecx, 8(%r14)
cmpl $1, %eax
je .LBB1_12
.LBB1_13: # %_ZNSt12__shared_ptrIiLN9__gnu_cxx12_Lock_policyE2EED2Ev.exit
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 176
movl $-1, %eax
lock xaddl %eax, 8(%r14)
cmpl $1, %eax
jne .LBB1_13
.LBB1_12:
movq %r14, %rdi
callq _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
jmp .LBB1_13
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rax
callq *16(%rax)
cmpb $0, __libc_single_threaded(%rip)
je .LBB2_2
# %bb.1:
movl 12(%rbx), %eax
leal -1(%rax), %ecx
movl %ecx, 12(%rbx)
cmpl $1, %eax
jne .LBB2_4
.LBB2_5:
movq (%rbx), %rax
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmpq *24(%rax) # TAILCALL
.LBB2_2:
.cfi_def_cfa_offset 16
movl $-1, %eax
lock xaddl %eax, 12(%rbx)
cmpl $1, %eax
je .LBB2_5
.LBB2_4: # %_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE19_M_release_last_useEv.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, .Lfunc_end2-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_startproc
# %bb.0:
retq
.Lfunc_end3:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev, .Lfunc_end3-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_startproc
# %bb.0:
jmp _ZdlPv # TAILCALL
.Lfunc_end4:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, .Lfunc_end4-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end5:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, .Lfunc_end5-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_startproc
# %bb.0: # %_ZNSt15__allocated_ptrISaISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EEEED2Ev.exit
jmp _ZdlPv # TAILCALL
.Lfunc_end6:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .Lfunc_end6-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_endproc
# -- End function
.section .text._ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,"axG",@progbits,_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,comdat
.weak _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info # -- Begin function _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.p2align 4, 0x90
.type _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,@function
_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info: # @_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.cfi_startproc
# %bb.0:
movq %rdi, %rax
addq $16, %rax
cmpq $_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, %rsi
je .LBB7_5
# %bb.1:
movq 8(%rsi), %rdi
cmpq $_ZTSSt19_Sp_make_shared_tag, %rdi
je .LBB7_5
# %bb.2:
cmpb $42, (%rdi)
jne .LBB7_4
# %bb.3:
xorl %eax, %eax
retq
.LBB7_4:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZTSSt19_Sp_make_shared_tag, %esi
movq %rax, %rbx
callq strcmp
movl %eax, %ecx
movq %rbx, %rax
xorl %edx, %edx
testl %ecx, %ecx
cmovneq %rdx, %rax
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB7_5: # %_ZNKSt9type_infoeqERKS_.exit
retq
.Lfunc_end7:
.size _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, .Lfunc_end7-_ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_startproc
# %bb.0:
ud2
.Lfunc_end8:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev, .Lfunc_end8-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
jmpq *8(%rax) # TAILCALL
.Lfunc_end9:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .Lfunc_end9-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15add_two_vectorsPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15add_two_vectorsPiS_S_,@object # @_Z15add_two_vectorsPiS_S_
.section .rodata,"a",@progbits
.globl _Z15add_two_vectorsPiS_S_
.p2align 3, 0x0
_Z15add_two_vectorsPiS_S_:
.quad _Z30__device_stub__add_two_vectorsPiS_S_
.size _Z15add_two_vectorsPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i, "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%i"
.size .L.str.1, 3
.type _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad _ZNSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.size _ZTVSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 56
.type _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 65
.type _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 52
.type _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 47
.type _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 16
.type _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 24
.type _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE, 24
.type _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad __cxa_pure_virtual
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad __cxa_pure_virtual
.size _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 56
.type _ZTSSt19_Sp_make_shared_tag,@object # @_ZTSSt19_Sp_make_shared_tag
.section .rodata._ZTSSt19_Sp_make_shared_tag,"aG",@progbits,_ZTSSt19_Sp_make_shared_tag,comdat
.weak _ZTSSt19_Sp_make_shared_tag
_ZTSSt19_Sp_make_shared_tag:
.asciz "St19_Sp_make_shared_tag"
.size _ZTSSt19_Sp_make_shared_tag, 24
.type _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,@object # @_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.section .rodata._ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,"aG",@progbits,_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag,comdat
.weak _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.p2align 3, 0x0
_ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag:
.zero 16
.size _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag, 16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15add_two_vectorsPiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__add_two_vectorsPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15add_two_vectorsPiS_S_
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSSt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt23_Sp_counted_ptr_inplaceIiSaIvELN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTSSt19_Sp_make_shared_tag
.addrsig_sym _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void glcm_calculation_45(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=1;i<nx;i++){
if(blockIdx.x==i && idx <((i+1)*nx)-1){
k=max*A[idx]+A[idx-(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | code for sm_80
Function : _Z19glcm_calculation_45PiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e240000002200 */
/*0040*/ ISETP.GE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe40003f06270 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe400078e0202 */
/*0080*/ IMAD R6, R0, c[0x0][0x0], R5 ; /* 0x0000000000067a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R6, R3, c[0x0][0x170], R6 ; /* 0x00005c0003067a24 */
/* 0x000fe200078e0206 */
/*00a0*/ @!P0 BRA 0x720 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R10.reuse, -0x2, RZ ; /* 0xfffffffe0a027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R4, R6, -c[0x0][0x170], R3 ; /* 0x80005c0006047a10 */
/* 0x000fe40007ffe003 */
/*0130*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fc400078ec0ff */
/*0140*/ IMAD.WIDE.U32 R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0005 */
/*0150*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0005 */
/*0160*/ @!P0 BRA 0x5c0 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x000fe200078e00ff */
/*0180*/ LEA R11, R10.reuse, 0xffffffff, 0x2 ; /* 0xffffffff0a0b7811 */
/* 0x040fe200078e10ff */
/*0190*/ IMAD.MOV R12, RZ, RZ, -R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a00 */
/*01a0*/ LEA R17, R10.reuse, 0xffffffff, 0x1 ; /* 0xffffffff0a117811 */
/* 0x040fe200078e08ff */
/*01b0*/ IMAD R13, R10.reuse, 0x3, -R15.reuse ; /* 0x000000030a0d7824 */
/* 0x140fe200078e0a0f */
/*01c0*/ IADD3 R8, R7, -c[0x0][0x170], RZ ; /* 0x80005c0007087a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD R15, R10, 0x5, -R15 ; /* 0x000000050a0f7824 */
/* 0x000fe200078e0a0f */
/*01e0*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fe40000000f00 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R6.reuse, R17, PT ; /* 0x000000110600720c */
/* 0x040fe20003f26070 */
/*0200*/ BSSY B0, 0x340 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe40003f06070 */
/*0220*/ ISETP.NE.OR P1, PT, R12, -0x1, P1 ; /* 0xffffffff0c00780c */
/* 0x000fc40000f25670 */
/*0230*/ ISETP.GE.U32.AND P3, PT, R6.reuse, R11, PT ; /* 0x0000000b0600720c */
/* 0x040fe40003f66070 */
/*0240*/ IADD3 R19, R9.reuse, 0x1, RZ ; /* 0x0000000109137810 */
/* 0x041fe40007ffe0ff */
/*0250*/ IADD3 R21, R9.reuse, 0x2, RZ ; /* 0x0000000209157810 */
/* 0x040fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P2, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x000fe40003f46070 */
/*0270*/ IADD3 R23, R9, 0x3, RZ ; /* 0x0000000309177810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.OR P0, PT, R0, R19, P0 ; /* 0x000000130000720c */
/* 0x000fc40000705670 */
/*0290*/ ISETP.NE.OR P3, PT, R0.reuse, R21, P3 ; /* 0x000000150000720c */
/* 0x040fe40001f65670 */
/*02a0*/ ISETP.NE.OR P2, PT, R0, R23, P2 ; /* 0x000000170000720c */
/* 0x000fe20001745670 */
/*02b0*/ @P1 BRA 0x330 ; /* 0x0000007000001947 */
/* 0x000fee0003800000 */
/*02c0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*0310*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*0320*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ BSSY B0, 0x3e0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0350*/ @P0 BRA 0x3d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x001ea2000c1e1900 */
/*0380*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe200078e00ff */
/*0390*/ HFMA2.MMA R21, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff157435 */
/* 0x000fe200000001ff */
/*03a0*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*03b0*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*03c0*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ BSSY B0, 0x480 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*03f0*/ @P3 BRA 0x470 ; /* 0x0000007000003947 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x001ea2000c1e1900 */
/*0420*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*0450*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*0460*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ BSSY B0, 0x530 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0490*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @P2 BRA 0x520 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*04b0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*04c0*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x001ea2000c1e1900 */
/*04d0*/ MOV R18, 0x4 ; /* 0x0000000400127802 */
/* 0x000fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD R19, R10, c[0x0][0x178], R19 ; /* 0x00005e000a137a24 */
/* 0x004fc800078e0213 */
/*0500*/ IMAD.WIDE R18, R19, R18, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0212 */
/*0510*/ RED.E.ADD.STRONG.GPU [R18.64], R21 ; /* 0x000000151200798e */
/* 0x0001e4000c10e184 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ IMAD.IADD R14, R9, 0x1, R8 ; /* 0x00000001090e7824 */
/* 0x000fe200078e0208 */
/*0540*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe40000000f00 */
/*0550*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0560*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f05270 */
/*0570*/ IMAD R13, R10.reuse, 0x4, R13 ; /* 0x000000040a0d7824 */
/* 0x040fe200078e020d */
/*0580*/ LEA R15, R10.reuse, R15, 0x2 ; /* 0x0000000f0a0f7211 */
/* 0x040fe200078e10ff */
/*0590*/ IMAD R11, R10.reuse, 0x4, R11 ; /* 0x000000040a0b7824 */
/* 0x040fe400078e020b */
/*05a0*/ IMAD R17, R10, 0x4, R17 ; /* 0x000000040a117824 */
/* 0x000fd000078e0211 */
/*05b0*/ @P0 BRA 0x1f0 ; /* 0xfffffc3000000947 */
/* 0x000fea000383ffff */
/*05c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*05d0*/ @!P0 BRA 0x720 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R8, R9.reuse, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x040fe20007ffe0ff */
/*05f0*/ IMAD.IADD R0, R9, 0x1, -R0 ; /* 0x0000000109007824 */
/* 0x000fc800078e0a00 */
/*0600*/ IMAD R11, R8, R10, -0x1 ; /* 0xffffffff080b7424 */
/* 0x000fca00078e020a */
/*0610*/ ISETP.GE.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fe20003f06070 */
/*0620*/ BSSY B0, 0x6f0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0630*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0640*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fe40000705670 */
/*0650*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f25270 */
/*0660*/ @P0 BRA 0x6e0 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0670*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*0680*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0690*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*06a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD R8, R8, c[0x0][0x178], R9 ; /* 0x00005e0008087a24 */
/* 0x004fce00078e0209 */
/*06c0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*06d0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0003e4000c10e184 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ IADD3 R11, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0710*/ @P1 BRA 0x610 ; /* 0xfffffef000001947 */
/* 0x000fea000383ffff */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void glcm_calculation_45(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=1;i<nx;i++){
if(blockIdx.x==i && idx <((i+1)*nx)-1){
k=max*A[idx]+A[idx-(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | .file "tmpxft_000c3ad2_00000000-6_glcm_calculation_45.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii
.type _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii, @function
_Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19glcm_calculation_45PiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii, .-_Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii
.globl _Z19glcm_calculation_45PiS_iii
.type _Z19glcm_calculation_45PiS_iii, @function
_Z19glcm_calculation_45PiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19glcm_calculation_45PiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19glcm_calculation_45PiS_iii, .-_Z19glcm_calculation_45PiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19glcm_calculation_45PiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19glcm_calculation_45PiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void glcm_calculation_45(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=1;i<nx;i++){
if(blockIdx.x==i && idx <((i+1)*nx)-1){
k=max*A[idx]+A[idx-(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void glcm_calculation_45(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=1;i<nx;i++){
if(blockIdx.x==i && idx <((i+1)*nx)-1){
k=max*A[idx]+A[idx-(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void glcm_calculation_45(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=1;i<nx;i++){
if(blockIdx.x==i && idx <((i+1)*nx)-1){
k=max*A[idx]+A[idx-(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19glcm_calculation_45PiS_iii
.globl _Z19glcm_calculation_45PiS_iii
.p2align 8
.type _Z19glcm_calculation_45PiS_iii,@function
_Z19glcm_calculation_45PiS_iii:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b32 s3, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s3, s14, s3
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
v_add3_u32 v0, s3, v0, v1
v_mov_b32_e32 v1, 0
s_lshl_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s3, s3, -1
v_subrev_nc_u32_e32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v4
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v5, 1
v_add_co_u32 v3, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s1, s1, 1
s_add_i32 s3, s3, s2
s_cmp_lg_u32 s2, s1
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_cmp_eq_u32 s14, s1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, s4, vcc_lo
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v9, v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, s0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[6:7], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_atomic_add_u32 v[6:7], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19glcm_calculation_45PiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19glcm_calculation_45PiS_iii, .Lfunc_end0-_Z19glcm_calculation_45PiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19glcm_calculation_45PiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19glcm_calculation_45PiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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