system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// CUDA includes
#include <cuda.h>
#include <cuda_runtime.h>
//Input size
#define SIZE 16384
//2d index to 1d index
#define idx(x,y,z) x*y + z
//TOTAL size of a matrix
size_t TOTAL_SIZE = SIZE * SIZE;
//Device allocated matrices
double *d_mat, *d_matT, *d_matSym;
//Host allocated matrix
double *h_mat;
void printMatrix(double *d_mat, int num) {
if (SIZE > 16) {
printf("Too big of an input to be printed!\n");
return;
}
cudaMemcpy(h_mat, d_mat, sizeof(double) * TOTAL_SIZE, cudaMemcpyDeviceToHost);
int i, j;
printf("MAT:\n");
for (i=0; i<SIZE; ++i) {
for (j=0; j<SIZE; ++j) {
printf("%f ", h_mat[i * SIZE + j]);
}
}
}
void allocate() {
cudaMalloc((void **)&d_mat, sizeof(double) * TOTAL_SIZE);
cudaMalloc((void **)&d_matT, sizeof(double) * TOTAL_SIZE);
cudaMalloc((void **)&d_matSym, sizeof(double) * TOTAL_SIZE);
h_mat = (double *) malloc(sizeof(double) * TOTAL_SIZE);
}
__global__ void initialize(double *d_mat) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//loading the index itself
d_mat[idx(tx,SIZE,ty)] = idx(tx,SIZE,ty);
}
}
__global__ void transpose(double *d_mat, double *d_matT) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//Transposing the matrix
d_matT[idx(ty,SIZE,tx)] = d_mat[idx(tx,SIZE,ty)];
}
}
__global__ void matrixMultiply(double *d_mat, double *d_matT, double *d_matSym) {
//Global inidices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
int k;
if (tx < SIZE && ty < SIZE) {
double accum = 0.0;
//Accumulation for (tx,ty) position
for (k=0; k<SIZE; ++k) {
accum += d_mat[idx(tx,SIZE,k)] * d_matT[idx(k,SIZE,ty)];
}
d_matSym[idx(tx,SIZE,ty)] = accum;
}
}
void calculateSymmetricMatrix(int TILE_DIM) {
//Configuring the dimensions for thread launch
dim3 grid_dim(SIZE/TILE_DIM, SIZE/TILE_DIM, 1);
dim3 blk_dim(TILE_DIM, TILE_DIM, 1);
//This will generate a symmetric matrix where mat(i,j) = mat(j,i)
initialize<<<grid_dim, blk_dim>>>(d_mat);
cudaDeviceSynchronize();
transpose<<<grid_dim, blk_dim>>>(d_mat, d_matT);
cudaDeviceSynchronize();
matrixMultiply<<<grid_dim, blk_dim>>>(d_mat, d_matT, d_matSym);
cudaDeviceSynchronize();
}
void deallocate() {
cudaFree(d_mat);
cudaFree(d_matT);
cudaFree(d_matSym);
free(h_mat);
}
int main (int argc, char **argv) {
int i, N = 1, TILE_DIM = 32;
struct timeval start, stop;
double execTime = 0.0;
if (argc > 1) { // Number of iterations
N = atoi(argv[1]);
}
printf("\n%d x %d Matrix\n\n", SIZE, SIZE);
allocate();
printf("\nExecution times(sec)\n");
for (i=0; i<N; ++i) {
gettimeofday(&start, NULL);
calculateSymmetricMatrix(TILE_DIM);
gettimeofday(&stop, NULL);
execTime += (double)(stop.tv_usec - start.tv_usec) / 1000000 + (double)(stop.tv_sec - start.tv_sec);
printf("At %d\t%.8f s\n", i, execTime);
}
deallocate();
return 0;
} | code for sm_80
Function : _Z14matrixMultiplyPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3fff, PT ; /* 0x00003fff0000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R17, 0x3fff, P0 ; /* 0x00003fff1100780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.SHL.U32 R17, R17, 0x4000, RZ ; /* 0x0000400011117824 */
/* 0x000fe200078e00ff */
/*00b0*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ CS2R R26, SRZ ; /* 0x00000000001a7805 */
/* 0x000fe2000001ff00 */
/*00f0*/ IADD3 R19, R17, 0x1, RZ ; /* 0x0000000111137810 */
/* 0x000fe20007ffe0ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0120*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0130*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe4000f8e00ff */
/*0140*/ IMAD.WIDE R24, R17, 0x8, R4 ; /* 0x0000000811187825 */
/* 0x000fc800078e0204 */
/*0150*/ IMAD.WIDE R2, R0, 0x8, R2 ; /* 0x0000000800027825 */
/* 0x000fe400078e0202 */
/*0160*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea4000c1e1b00 */
/*0170*/ IMAD.WIDE R6, R19, 0x8, R4 ; /* 0x0000000813067825 */
/* 0x000fe400078e0204 */
/*0180*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ea8000c1e1b00 */
/*0190*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ee8000c1e1b00 */
/*01a0*/ LDG.E.64 R22, [R2.64+0x20000] ; /* 0x0200000402167981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R14, [R2.64+0x40000] ; /* 0x04000004020e7981 */
/* 0x000f28000c1e1b00 */
/*01d0*/ LDG.E.64 R10, [R2.64+0x60000] ; /* 0x06000004020a7981 */
/* 0x000f68000c1e1b00 */
/*01e0*/ LDG.E.64 R28, [R2.64+0x1e0000] ; /* 0x1e000004021c7981 */
/* 0x000f62000c1e1b00 */
/*01f0*/ DFMA R26, R8, R24, R26 ; /* 0x00000018081a722b */
/* 0x0060c6000000001a */
/*0200*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x001f68000c1e1b00 */
/*0210*/ LDG.E.64 R24, [R6.64+0x68] ; /* 0x0000680406187981 */
/* 0x000ea2000c1e1b00 */
/*0220*/ DFMA R26, R22, R20, R26 ; /* 0x00000014161a722b */
/* 0x008106000000001a */
/*0230*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x001ee8000c1e1b00 */
/*0240*/ LDG.E.64 R22, [R2.64+0x80000] ; /* 0x0800000402167981 */
/* 0x000ee2000c1e1b00 */
/*0250*/ DFMA R26, R14, R12, R26 ; /* 0x0000000c0e1a722b */
/* 0x010146000000001a */
/*0260*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001f28000c1e1b00 */
/*0270*/ LDG.E.64 R14, [R2.64+0xa0000] ; /* 0x0a000004020e7981 */
/* 0x000f22000c1e1b00 */
/*0280*/ DFMA R26, R10, R8, R26 ; /* 0x000000080a1a722b */
/* 0x0200c6000000001a */
/*0290*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x001f68000c1e1b00 */
/*02a0*/ LDG.E.64 R10, [R2.64+0xc0000] ; /* 0x0c000004020a7981 */
/* 0x000f62000c1e1b00 */
/*02b0*/ DFMA R26, R22, R20, R26 ; /* 0x00000014161a722b */
/* 0x008106000000001a */
/*02c0*/ LDG.E.64 R20, [R6.64+0x30] ; /* 0x0000300406147981 */
/* 0x001ee8000c1e1b00 */
/*02d0*/ LDG.E.64 R22, [R2.64+0xe0000] ; /* 0x0e00000402167981 */
/* 0x000ee2000c1e1b00 */
/*02e0*/ DFMA R26, R14, R12, R26 ; /* 0x0000000c0e1a722b */
/* 0x010146000000001a */
/*02f0*/ LDG.E.64 R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x001f28000c1e1b00 */
/*0300*/ LDG.E.64 R12, [R2.64+0x100000] ; /* 0x10000004020c7981 */
/* 0x000f22000c1e1b00 */
/*0310*/ DFMA R26, R10, R8, R26 ; /* 0x000000080a1a722b */
/* 0x0200c6000000001a */
/*0320*/ LDG.E.64 R10, [R6.64+0x40] ; /* 0x00004004060a7981 */
/* 0x001f68000c1e1b00 */
/*0330*/ LDG.E.64 R8, [R2.64+0x120000] ; /* 0x1200000402087981 */
/* 0x000f62000c1e1b00 */
/*0340*/ DFMA R26, R22, R20, R26 ; /* 0x00000014161a722b */
/* 0x008106000000001a */
/*0350*/ LDG.E.64 R22, [R6.64+0x48] ; /* 0x0000480406167981 */
/* 0x001ee8000c1e1b00 */
/*0360*/ LDG.E.64 R20, [R2.64+0x140000] ; /* 0x1400000402147981 */
/* 0x000ee2000c1e1b00 */
/*0370*/ DFMA R26, R12, R14, R26 ; /* 0x0000000e0c1a722b */
/* 0x010146000000001a */
/*0380*/ LDG.E.64 R14, [R6.64+0x50] ; /* 0x00005004060e7981 */
/* 0x001f28000c1e1b00 */
/*0390*/ LDG.E.64 R12, [R2.64+0x160000] ; /* 0x16000004020c7981 */
/* 0x000f22000c1e1b00 */
/*03a0*/ DFMA R26, R8, R10, R26 ; /* 0x0000000a081a722b */
/* 0x0200c6000000001a */
/*03b0*/ LDG.E.64 R10, [R6.64+0x58] ; /* 0x00005804060a7981 */
/* 0x001f68000c1e1b00 */
/*03c0*/ LDG.E.64 R8, [R2.64+0x180000] ; /* 0x1800000402087981 */
/* 0x000f62000c1e1b00 */
/*03d0*/ DFMA R26, R20, R22, R26 ; /* 0x00000016141a722b */
/* 0x008106000000001a */
/*03e0*/ LDG.E.64 R22, [R6.64+0x60] ; /* 0x0000600406167981 */
/* 0x001ee8000c1e1b00 */
/*03f0*/ LDG.E.64 R20, [R2.64+0x1a0000] ; /* 0x1a00000402147981 */
/* 0x000ee2000c1e1b00 */
/*0400*/ DFMA R12, R12, R14, R26 ; /* 0x0000000e0c0c722b */
/* 0x010146000000001a */
/*0410*/ LDG.E.64 R14, [R2.64+0x1c0000] ; /* 0x1c000004020e7981 */
/* 0x001ea8000c1e1b00 */
/*0420*/ LDG.E.64 R26, [R6.64+0x70] ; /* 0x00007004061a7981 */
/* 0x000f22000c1e1b00 */
/*0430*/ IADD3 R16, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R16, 0x4000, PT ; /* 0x000040001000780c */
/* 0x000fe20003f05270 */
/*0450*/ UIADD3 UR6, UP0, UR6, 0x200000, URZ ; /* 0x0020000006067890 */
/* 0x000fe2000ff1e03f */
/*0460*/ IADD3 R4, P1, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x000fc60007f3e0ff */
/*0470*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0480*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0490*/ DFMA R8, R8, R10, R12 ; /* 0x0000000a0808722b */
/* 0x020ecc000000000c */
/*04a0*/ DFMA R8, R20, R22, R8 ; /* 0x000000161408722b */
/* 0x008e8c0000000008 */
/*04b0*/ DFMA R8, R14, R24, R8 ; /* 0x000000180e08722b */
/* 0x004f0c0000000008 */
/*04c0*/ DFMA R26, R28, R26, R8 ; /* 0x0000001a1c1a722b */
/* 0x0100620000000008 */
/*04d0*/ @P0 BRA 0x120 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04e0*/ IADD3 R2, R0, R17, RZ ; /* 0x0000001100027210 */
/* 0x000fe40007ffe0ff */
/*04f0*/ MOV R3, 0x8 ; /* 0x0000000800037802 */
/* 0x000fca0000000f00 */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E.64 [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x002fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R5, 0x3fff, PT ; /* 0x00003fff0500780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3fff, P0 ; /* 0x00003fff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R2, R0, R5, 0xe ; /* 0x0000000500027211 */
/* 0x000fe200078e70ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ LEA R5, R5, R0, 0xe ; /* 0x0000000005057211 */
/* 0x000fca00078e70ff */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializePd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x3fff, PT ; /* 0x00003fff0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3fff, P0 ; /* 0x00003fff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ LEA R0, R0, R3, 0xe ; /* 0x0000000300007211 */
/* 0x000fe200078e70ff */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e2e0000201c00 */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// CUDA includes
#include <cuda.h>
#include <cuda_runtime.h>
//Input size
#define SIZE 16384
//2d index to 1d index
#define idx(x,y,z) x*y + z
//TOTAL size of a matrix
size_t TOTAL_SIZE = SIZE * SIZE;
//Device allocated matrices
double *d_mat, *d_matT, *d_matSym;
//Host allocated matrix
double *h_mat;
void printMatrix(double *d_mat, int num) {
if (SIZE > 16) {
printf("Too big of an input to be printed!\n");
return;
}
cudaMemcpy(h_mat, d_mat, sizeof(double) * TOTAL_SIZE, cudaMemcpyDeviceToHost);
int i, j;
printf("MAT:\n");
for (i=0; i<SIZE; ++i) {
for (j=0; j<SIZE; ++j) {
printf("%f ", h_mat[i * SIZE + j]);
}
}
}
void allocate() {
cudaMalloc((void **)&d_mat, sizeof(double) * TOTAL_SIZE);
cudaMalloc((void **)&d_matT, sizeof(double) * TOTAL_SIZE);
cudaMalloc((void **)&d_matSym, sizeof(double) * TOTAL_SIZE);
h_mat = (double *) malloc(sizeof(double) * TOTAL_SIZE);
}
__global__ void initialize(double *d_mat) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//loading the index itself
d_mat[idx(tx,SIZE,ty)] = idx(tx,SIZE,ty);
}
}
__global__ void transpose(double *d_mat, double *d_matT) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//Transposing the matrix
d_matT[idx(ty,SIZE,tx)] = d_mat[idx(tx,SIZE,ty)];
}
}
__global__ void matrixMultiply(double *d_mat, double *d_matT, double *d_matSym) {
//Global inidices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
int k;
if (tx < SIZE && ty < SIZE) {
double accum = 0.0;
//Accumulation for (tx,ty) position
for (k=0; k<SIZE; ++k) {
accum += d_mat[idx(tx,SIZE,k)] * d_matT[idx(k,SIZE,ty)];
}
d_matSym[idx(tx,SIZE,ty)] = accum;
}
}
void calculateSymmetricMatrix(int TILE_DIM) {
//Configuring the dimensions for thread launch
dim3 grid_dim(SIZE/TILE_DIM, SIZE/TILE_DIM, 1);
dim3 blk_dim(TILE_DIM, TILE_DIM, 1);
//This will generate a symmetric matrix where mat(i,j) = mat(j,i)
initialize<<<grid_dim, blk_dim>>>(d_mat);
cudaDeviceSynchronize();
transpose<<<grid_dim, blk_dim>>>(d_mat, d_matT);
cudaDeviceSynchronize();
matrixMultiply<<<grid_dim, blk_dim>>>(d_mat, d_matT, d_matSym);
cudaDeviceSynchronize();
}
void deallocate() {
cudaFree(d_mat);
cudaFree(d_matT);
cudaFree(d_matSym);
free(h_mat);
}
int main (int argc, char **argv) {
int i, N = 1, TILE_DIM = 32;
struct timeval start, stop;
double execTime = 0.0;
if (argc > 1) { // Number of iterations
N = atoi(argv[1]);
}
printf("\n%d x %d Matrix\n\n", SIZE, SIZE);
allocate();
printf("\nExecution times(sec)\n");
for (i=0; i<N; ++i) {
gettimeofday(&start, NULL);
calculateSymmetricMatrix(TILE_DIM);
gettimeofday(&stop, NULL);
execTime += (double)(stop.tv_usec - start.tv_usec) / 1000000 + (double)(stop.tv_sec - start.tv_sec);
printf("At %d\t%.8f s\n", i, execTime);
}
deallocate();
return 0;
} | .file "tmpxft_000c5745_00000000-6_matCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Too big of an input to be printed!\n"
.text
.globl _Z11printMatrixPdi
.type _Z11printMatrixPdi, @function
_Z11printMatrixPdi:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPdi, .-_Z11printMatrixPdi
.globl _Z8allocatev
.type _Z8allocatev, @function
_Z8allocatev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq d_mat(%rip), %rdi
call cudaMalloc@PLT
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq d_matT(%rip), %rdi
call cudaMalloc@PLT
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq d_matSym(%rip), %rdi
call cudaMalloc@PLT
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rdi
call malloc@PLT
movq %rax, h_mat(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8allocatev, .-_Z8allocatev
.globl _Z10deallocatev
.type _Z10deallocatev, @function
_Z10deallocatev:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_mat(%rip), %rdi
call cudaFree@PLT
movq d_matT(%rip), %rdi
call cudaFree@PLT
movq d_matSym(%rip), %rdi
call cudaFree@PLT
movq h_mat(%rip), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10deallocatev, .-_Z10deallocatev
.globl _Z30__device_stub__Z10initializePdPd
.type _Z30__device_stub__Z10initializePdPd, @function
_Z30__device_stub__Z10initializePdPd:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initializePd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z10initializePdPd, .-_Z30__device_stub__Z10initializePdPd
.globl _Z10initializePd
.type _Z10initializePd, @function
_Z10initializePd:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10initializePdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10initializePd, .-_Z10initializePd
.globl _Z30__device_stub__Z9transposePdS_PdS_
.type _Z30__device_stub__Z9transposePdS_PdS_, @function
_Z30__device_stub__Z9transposePdS_PdS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z30__device_stub__Z9transposePdS_PdS_, .-_Z30__device_stub__Z9transposePdS_PdS_
.globl _Z9transposePdS_
.type _Z9transposePdS_, @function
_Z9transposePdS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z9transposePdS_, .-_Z9transposePdS_
.globl _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
.type _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_, @function
_Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixMultiplyPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_, .-_Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
.globl _Z14matrixMultiplyPdS_S_
.type _Z14matrixMultiplyPdS_S_, @function
_Z14matrixMultiplyPdS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z14matrixMultiplyPdS_S_, .-_Z14matrixMultiplyPdS_S_
.globl _Z24calculateSymmetricMatrixi
.type _Z24calculateSymmetricMatrixi, @function
_Z24calculateSymmetricMatrixi:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16384, %eax
movl $0, %edx
idivl %edi
movl %eax, 8(%rsp)
movl %eax, 12(%rsp)
movl $1, 16(%rsp)
movl %edi, 20(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
call cudaDeviceSynchronize@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
call cudaDeviceSynchronize@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq d_mat(%rip), %rdi
call _Z30__device_stub__Z10initializePdPd
jmp .L34
.L39:
movq d_matT(%rip), %rsi
movq d_mat(%rip), %rdi
call _Z30__device_stub__Z9transposePdS_PdS_
jmp .L35
.L40:
movq d_matSym(%rip), %rdx
movq d_matT(%rip), %rsi
movq d_mat(%rip), %rdi
call _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
jmp .L36
.cfi_endproc
.LFE2059:
.size _Z24calculateSymmetricMatrixi, .-_Z24calculateSymmetricMatrixi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n%d x %d Matrix\n\n"
.LC3:
.string "\nExecution times(sec)\n"
.LC5:
.string "At %d\t%.8f s\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L50
movl $16384, %ecx
movl $16384, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z8allocatev
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebp
.L45:
movq $0x000000000, 8(%rsp)
movl $0, %ebx
leaq 16(%rsp), %r14
leaq 32(%rsp), %r13
leaq .LC5(%rip), %r12
.L44:
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
movl $32, %edi
call _Z24calculateSymmetricMatrixi
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
movq 40(%rsp), %rax
subq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq 32(%rsp), %rax
subq 16(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L44
.L43:
call _Z10deallocatev
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movl $16384, %ecx
movl $16384, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z8allocatev
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jg .L45
jmp .L43
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z14matrixMultiplyPdS_S_"
.LC7:
.string "_Z9transposePdS_"
.LC8:
.string "_Z10initializePd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_mat
.bss
.align 8
.type h_mat, @object
.size h_mat, 8
h_mat:
.zero 8
.globl d_matSym
.align 8
.type d_matSym, @object
.size d_matSym, 8
d_matSym:
.zero 8
.globl d_matT
.align 8
.type d_matT, @object
.size d_matT, 8
d_matT:
.zero 8
.globl d_mat
.align 8
.type d_mat, @object
.size d_mat, 8
d_mat:
.zero 8
.globl TOTAL_SIZE
.data
.align 8
.type TOTAL_SIZE, @object
.size TOTAL_SIZE, 8
TOTAL_SIZE:
.quad 268435456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// CUDA includes
#include <cuda.h>
#include <cuda_runtime.h>
//Input size
#define SIZE 16384
//2d index to 1d index
#define idx(x,y,z) x*y + z
//TOTAL size of a matrix
size_t TOTAL_SIZE = SIZE * SIZE;
//Device allocated matrices
double *d_mat, *d_matT, *d_matSym;
//Host allocated matrix
double *h_mat;
void printMatrix(double *d_mat, int num) {
if (SIZE > 16) {
printf("Too big of an input to be printed!\n");
return;
}
cudaMemcpy(h_mat, d_mat, sizeof(double) * TOTAL_SIZE, cudaMemcpyDeviceToHost);
int i, j;
printf("MAT:\n");
for (i=0; i<SIZE; ++i) {
for (j=0; j<SIZE; ++j) {
printf("%f ", h_mat[i * SIZE + j]);
}
}
}
void allocate() {
cudaMalloc((void **)&d_mat, sizeof(double) * TOTAL_SIZE);
cudaMalloc((void **)&d_matT, sizeof(double) * TOTAL_SIZE);
cudaMalloc((void **)&d_matSym, sizeof(double) * TOTAL_SIZE);
h_mat = (double *) malloc(sizeof(double) * TOTAL_SIZE);
}
__global__ void initialize(double *d_mat) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//loading the index itself
d_mat[idx(tx,SIZE,ty)] = idx(tx,SIZE,ty);
}
}
__global__ void transpose(double *d_mat, double *d_matT) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//Transposing the matrix
d_matT[idx(ty,SIZE,tx)] = d_mat[idx(tx,SIZE,ty)];
}
}
__global__ void matrixMultiply(double *d_mat, double *d_matT, double *d_matSym) {
//Global inidices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
int k;
if (tx < SIZE && ty < SIZE) {
double accum = 0.0;
//Accumulation for (tx,ty) position
for (k=0; k<SIZE; ++k) {
accum += d_mat[idx(tx,SIZE,k)] * d_matT[idx(k,SIZE,ty)];
}
d_matSym[idx(tx,SIZE,ty)] = accum;
}
}
void calculateSymmetricMatrix(int TILE_DIM) {
//Configuring the dimensions for thread launch
dim3 grid_dim(SIZE/TILE_DIM, SIZE/TILE_DIM, 1);
dim3 blk_dim(TILE_DIM, TILE_DIM, 1);
//This will generate a symmetric matrix where mat(i,j) = mat(j,i)
initialize<<<grid_dim, blk_dim>>>(d_mat);
cudaDeviceSynchronize();
transpose<<<grid_dim, blk_dim>>>(d_mat, d_matT);
cudaDeviceSynchronize();
matrixMultiply<<<grid_dim, blk_dim>>>(d_mat, d_matT, d_matSym);
cudaDeviceSynchronize();
}
void deallocate() {
cudaFree(d_mat);
cudaFree(d_matT);
cudaFree(d_matSym);
free(h_mat);
}
int main (int argc, char **argv) {
int i, N = 1, TILE_DIM = 32;
struct timeval start, stop;
double execTime = 0.0;
if (argc > 1) { // Number of iterations
N = atoi(argv[1]);
}
printf("\n%d x %d Matrix\n\n", SIZE, SIZE);
allocate();
printf("\nExecution times(sec)\n");
for (i=0; i<N; ++i) {
gettimeofday(&start, NULL);
calculateSymmetricMatrix(TILE_DIM);
gettimeofday(&stop, NULL);
execTime += (double)(stop.tv_usec - start.tv_usec) / 1000000 + (double)(stop.tv_sec - start.tv_sec);
printf("At %d\t%.8f s\n", i, execTime);
}
deallocate();
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// CUDA includes
#include <hip/hip_runtime.h>
//Input size
#define SIZE 16384
//2d index to 1d index
#define idx(x,y,z) x*y + z
//TOTAL size of a matrix
size_t TOTAL_SIZE = SIZE * SIZE;
//Device allocated matrices
double *d_mat, *d_matT, *d_matSym;
//Host allocated matrix
double *h_mat;
void printMatrix(double *d_mat, int num) {
if (SIZE > 16) {
printf("Too big of an input to be printed!\n");
return;
}
hipMemcpy(h_mat, d_mat, sizeof(double) * TOTAL_SIZE, hipMemcpyDeviceToHost);
int i, j;
printf("MAT:\n");
for (i=0; i<SIZE; ++i) {
for (j=0; j<SIZE; ++j) {
printf("%f ", h_mat[i * SIZE + j]);
}
}
}
void allocate() {
hipMalloc((void **)&d_mat, sizeof(double) * TOTAL_SIZE);
hipMalloc((void **)&d_matT, sizeof(double) * TOTAL_SIZE);
hipMalloc((void **)&d_matSym, sizeof(double) * TOTAL_SIZE);
h_mat = (double *) malloc(sizeof(double) * TOTAL_SIZE);
}
__global__ void initialize(double *d_mat) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//loading the index itself
d_mat[idx(tx,SIZE,ty)] = idx(tx,SIZE,ty);
}
}
__global__ void transpose(double *d_mat, double *d_matT) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//Transposing the matrix
d_matT[idx(ty,SIZE,tx)] = d_mat[idx(tx,SIZE,ty)];
}
}
__global__ void matrixMultiply(double *d_mat, double *d_matT, double *d_matSym) {
//Global inidices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
int k;
if (tx < SIZE && ty < SIZE) {
double accum = 0.0;
//Accumulation for (tx,ty) position
for (k=0; k<SIZE; ++k) {
accum += d_mat[idx(tx,SIZE,k)] * d_matT[idx(k,SIZE,ty)];
}
d_matSym[idx(tx,SIZE,ty)] = accum;
}
}
void calculateSymmetricMatrix(int TILE_DIM) {
//Configuring the dimensions for thread launch
dim3 grid_dim(SIZE/TILE_DIM, SIZE/TILE_DIM, 1);
dim3 blk_dim(TILE_DIM, TILE_DIM, 1);
//This will generate a symmetric matrix where mat(i,j) = mat(j,i)
initialize<<<grid_dim, blk_dim>>>(d_mat);
hipDeviceSynchronize();
transpose<<<grid_dim, blk_dim>>>(d_mat, d_matT);
hipDeviceSynchronize();
matrixMultiply<<<grid_dim, blk_dim>>>(d_mat, d_matT, d_matSym);
hipDeviceSynchronize();
}
void deallocate() {
hipFree(d_mat);
hipFree(d_matT);
hipFree(d_matSym);
free(h_mat);
}
int main (int argc, char **argv) {
int i, N = 1, TILE_DIM = 32;
struct timeval start, stop;
double execTime = 0.0;
if (argc > 1) { // Number of iterations
N = atoi(argv[1]);
}
printf("\n%d x %d Matrix\n\n", SIZE, SIZE);
allocate();
printf("\nExecution times(sec)\n");
for (i=0; i<N; ++i) {
gettimeofday(&start, NULL);
calculateSymmetricMatrix(TILE_DIM);
gettimeofday(&stop, NULL);
execTime += (double)(stop.tv_usec - start.tv_usec) / 1000000 + (double)(stop.tv_sec - start.tv_sec);
printf("At %d\t%.8f s\n", i, execTime);
}
deallocate();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// CUDA includes
#include <hip/hip_runtime.h>
//Input size
#define SIZE 16384
//2d index to 1d index
#define idx(x,y,z) x*y + z
//TOTAL size of a matrix
size_t TOTAL_SIZE = SIZE * SIZE;
//Device allocated matrices
double *d_mat, *d_matT, *d_matSym;
//Host allocated matrix
double *h_mat;
void printMatrix(double *d_mat, int num) {
if (SIZE > 16) {
printf("Too big of an input to be printed!\n");
return;
}
hipMemcpy(h_mat, d_mat, sizeof(double) * TOTAL_SIZE, hipMemcpyDeviceToHost);
int i, j;
printf("MAT:\n");
for (i=0; i<SIZE; ++i) {
for (j=0; j<SIZE; ++j) {
printf("%f ", h_mat[i * SIZE + j]);
}
}
}
void allocate() {
hipMalloc((void **)&d_mat, sizeof(double) * TOTAL_SIZE);
hipMalloc((void **)&d_matT, sizeof(double) * TOTAL_SIZE);
hipMalloc((void **)&d_matSym, sizeof(double) * TOTAL_SIZE);
h_mat = (double *) malloc(sizeof(double) * TOTAL_SIZE);
}
__global__ void initialize(double *d_mat) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//loading the index itself
d_mat[idx(tx,SIZE,ty)] = idx(tx,SIZE,ty);
}
}
__global__ void transpose(double *d_mat, double *d_matT) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//Transposing the matrix
d_matT[idx(ty,SIZE,tx)] = d_mat[idx(tx,SIZE,ty)];
}
}
__global__ void matrixMultiply(double *d_mat, double *d_matT, double *d_matSym) {
//Global inidices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
int k;
if (tx < SIZE && ty < SIZE) {
double accum = 0.0;
//Accumulation for (tx,ty) position
for (k=0; k<SIZE; ++k) {
accum += d_mat[idx(tx,SIZE,k)] * d_matT[idx(k,SIZE,ty)];
}
d_matSym[idx(tx,SIZE,ty)] = accum;
}
}
void calculateSymmetricMatrix(int TILE_DIM) {
//Configuring the dimensions for thread launch
dim3 grid_dim(SIZE/TILE_DIM, SIZE/TILE_DIM, 1);
dim3 blk_dim(TILE_DIM, TILE_DIM, 1);
//This will generate a symmetric matrix where mat(i,j) = mat(j,i)
initialize<<<grid_dim, blk_dim>>>(d_mat);
hipDeviceSynchronize();
transpose<<<grid_dim, blk_dim>>>(d_mat, d_matT);
hipDeviceSynchronize();
matrixMultiply<<<grid_dim, blk_dim>>>(d_mat, d_matT, d_matSym);
hipDeviceSynchronize();
}
void deallocate() {
hipFree(d_mat);
hipFree(d_matT);
hipFree(d_matSym);
free(h_mat);
}
int main (int argc, char **argv) {
int i, N = 1, TILE_DIM = 32;
struct timeval start, stop;
double execTime = 0.0;
if (argc > 1) { // Number of iterations
N = atoi(argv[1]);
}
printf("\n%d x %d Matrix\n\n", SIZE, SIZE);
allocate();
printf("\nExecution times(sec)\n");
for (i=0; i<N; ++i) {
gettimeofday(&start, NULL);
calculateSymmetricMatrix(TILE_DIM);
gettimeofday(&stop, NULL);
execTime += (double)(stop.tv_usec - start.tv_usec) / 1000000 + (double)(stop.tv_sec - start.tv_sec);
printf("At %d\t%.8f s\n", i, execTime);
}
deallocate();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePd
.globl _Z10initializePd
.p2align 8
.type _Z10initializePd,@function
_Z10initializePd:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB0_2
v_lshl_add_u32 v0, v0, 14, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[2:3], v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePd, .Lfunc_end0-_Z10initializePd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9transposePdS_
.globl _Z9transposePdS_
.p2align 8
.type _Z9transposePdS_,@function
_Z9transposePdS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v2, v0, 14, v1
v_lshl_add_u32 v0, v1, 14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9transposePdS_, .Lfunc_end1-_Z9transposePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14matrixMultiplyPdS_S_
.globl _Z14matrixMultiplyPdS_S_
.p2align 8
.type _Z14matrixMultiplyPdS_S_,@function
_Z14matrixMultiplyPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 14, v0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v4
v_mov_b32_e32 v4, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[10:11], 3, v[4:5]
v_add_nc_u32_e32 v4, 0x4000, v4
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 0x20000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[10:11], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[10:11], v[2:3]
s_cbranch_scc1 .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 14, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14matrixMultiplyPdS_S_, .Lfunc_end2-_Z14matrixMultiplyPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// CUDA includes
#include <hip/hip_runtime.h>
//Input size
#define SIZE 16384
//2d index to 1d index
#define idx(x,y,z) x*y + z
//TOTAL size of a matrix
size_t TOTAL_SIZE = SIZE * SIZE;
//Device allocated matrices
double *d_mat, *d_matT, *d_matSym;
//Host allocated matrix
double *h_mat;
void printMatrix(double *d_mat, int num) {
if (SIZE > 16) {
printf("Too big of an input to be printed!\n");
return;
}
hipMemcpy(h_mat, d_mat, sizeof(double) * TOTAL_SIZE, hipMemcpyDeviceToHost);
int i, j;
printf("MAT:\n");
for (i=0; i<SIZE; ++i) {
for (j=0; j<SIZE; ++j) {
printf("%f ", h_mat[i * SIZE + j]);
}
}
}
void allocate() {
hipMalloc((void **)&d_mat, sizeof(double) * TOTAL_SIZE);
hipMalloc((void **)&d_matT, sizeof(double) * TOTAL_SIZE);
hipMalloc((void **)&d_matSym, sizeof(double) * TOTAL_SIZE);
h_mat = (double *) malloc(sizeof(double) * TOTAL_SIZE);
}
__global__ void initialize(double *d_mat) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//loading the index itself
d_mat[idx(tx,SIZE,ty)] = idx(tx,SIZE,ty);
}
}
__global__ void transpose(double *d_mat, double *d_matT) {
//Global indices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
if (tx < SIZE && ty < SIZE) {
//Transposing the matrix
d_matT[idx(ty,SIZE,tx)] = d_mat[idx(tx,SIZE,ty)];
}
}
__global__ void matrixMultiply(double *d_mat, double *d_matT, double *d_matSym) {
//Global inidices
int tx = blockIdx.y * blockDim.y + threadIdx.y;
int ty = blockIdx.x * blockDim.x + threadIdx.x;
int k;
if (tx < SIZE && ty < SIZE) {
double accum = 0.0;
//Accumulation for (tx,ty) position
for (k=0; k<SIZE; ++k) {
accum += d_mat[idx(tx,SIZE,k)] * d_matT[idx(k,SIZE,ty)];
}
d_matSym[idx(tx,SIZE,ty)] = accum;
}
}
void calculateSymmetricMatrix(int TILE_DIM) {
//Configuring the dimensions for thread launch
dim3 grid_dim(SIZE/TILE_DIM, SIZE/TILE_DIM, 1);
dim3 blk_dim(TILE_DIM, TILE_DIM, 1);
//This will generate a symmetric matrix where mat(i,j) = mat(j,i)
initialize<<<grid_dim, blk_dim>>>(d_mat);
hipDeviceSynchronize();
transpose<<<grid_dim, blk_dim>>>(d_mat, d_matT);
hipDeviceSynchronize();
matrixMultiply<<<grid_dim, blk_dim>>>(d_mat, d_matT, d_matSym);
hipDeviceSynchronize();
}
void deallocate() {
hipFree(d_mat);
hipFree(d_matT);
hipFree(d_matSym);
free(h_mat);
}
int main (int argc, char **argv) {
int i, N = 1, TILE_DIM = 32;
struct timeval start, stop;
double execTime = 0.0;
if (argc > 1) { // Number of iterations
N = atoi(argv[1]);
}
printf("\n%d x %d Matrix\n\n", SIZE, SIZE);
allocate();
printf("\nExecution times(sec)\n");
for (i=0; i<N; ++i) {
gettimeofday(&start, NULL);
calculateSymmetricMatrix(TILE_DIM);
gettimeofday(&stop, NULL);
execTime += (double)(stop.tv_usec - start.tv_usec) / 1000000 + (double)(stop.tv_sec - start.tv_sec);
printf("At %d\t%.8f s\n", i, execTime);
}
deallocate();
return 0;
} | .text
.file "matCUDA.hip"
.globl _Z11printMatrixPdi # -- Begin function _Z11printMatrixPdi
.p2align 4, 0x90
.type _Z11printMatrixPdi,@function
_Z11printMatrixPdi: # @_Z11printMatrixPdi
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPdi, .Lfunc_end0-_Z11printMatrixPdi
.cfi_endproc
# -- End function
.globl _Z8allocatev # -- Begin function _Z8allocatev
.p2align 4, 0x90
.type _Z8allocatev,@function
_Z8allocatev: # @_Z8allocatev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_mat, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matT, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matSym, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rdi
shlq $3, %rdi
callq malloc
movq %rax, h_mat(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8allocatev, .Lfunc_end1-_Z8allocatev
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePd # -- Begin function _Z25__device_stub__initializePd
.p2align 4, 0x90
.type _Z25__device_stub__initializePd,@function
_Z25__device_stub__initializePd: # @_Z25__device_stub__initializePd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initializePd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z25__device_stub__initializePd, .Lfunc_end2-_Z25__device_stub__initializePd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePdS_ # -- Begin function _Z24__device_stub__transposePdS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePdS_,@function
_Z24__device_stub__transposePdS_: # @_Z24__device_stub__transposePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z24__device_stub__transposePdS_, .Lfunc_end3-_Z24__device_stub__transposePdS_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__matrixMultiplyPdS_S_ # -- Begin function _Z29__device_stub__matrixMultiplyPdS_S_
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPdS_S_,@function
_Z29__device_stub__matrixMultiplyPdS_S_: # @_Z29__device_stub__matrixMultiplyPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrixMultiplyPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z29__device_stub__matrixMultiplyPdS_S_, .Lfunc_end4-_Z29__device_stub__matrixMultiplyPdS_S_
.cfi_endproc
# -- End function
.globl _Z24calculateSymmetricMatrixi # -- Begin function _Z24calculateSymmetricMatrixi
.p2align 4, 0x90
.type _Z24calculateSymmetricMatrixi,@function
_Z24calculateSymmetricMatrixi: # @_Z24calculateSymmetricMatrixi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $16384, %eax # imm = 0x4000
xorl %edx, %edx
idivl %edi
# kill: def $eax killed $eax def $rax
movq %rax, %rbx
shlq $32, %rbx
orq %rax, %rbx
movl %edi, %eax
movq %rax, %r14
shlq $32, %r14
orq %rax, %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq d_mat(%rip), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initializePd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq d_mat(%rip), %rax
movq d_matT(%rip), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePdS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
callq hipDeviceSynchronize
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq d_mat(%rip), %rax
movq d_matT(%rip), %rcx
movq d_matSym(%rip), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14matrixMultiplyPdS_S_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
callq hipDeviceSynchronize
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z24calculateSymmetricMatrixi, .Lfunc_end5-_Z24calculateSymmetricMatrixi
.cfi_endproc
# -- End function
.globl _Z10deallocatev # -- Begin function _Z10deallocatev
.p2align 4, 0x90
.type _Z10deallocatev,@function
_Z10deallocatev: # @_Z10deallocatev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_mat(%rip), %rdi
callq hipFree
movq d_matT(%rip), %rdi
callq hipFree
movq d_matSym(%rip), %rdi
callq hipFree
movq h_mat(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end6:
.size _Z10deallocatev, .Lfunc_end6-_Z10deallocatev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %ebx
cmpl $2, %edi
jl .LBB7_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB7_2:
xorl %r14d, %r14d
movl $.L.str.1, %edi
movl $16384, %esi # imm = 0x4000
movl $16384, %edx # imm = 0x4000
xorl %eax, %eax
callq printf
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_mat, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matT, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matSym, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rdi
shlq $3, %rdi
callq malloc
movq %rax, h_mat(%rip)
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB7_5
# %bb.3: # %.lr.ph
xorpd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
leaq 24(%rsp), %r15
leaq 8(%rsp), %r12
.p2align 4, 0x90
.LBB7_4: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movl $32, %edi
callq _Z24calculateSymmetricMatrixi
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq 32(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq 8(%rsp), %rax
divsd .LCPI7_0(%rip), %xmm0
subq 24(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
addsd %xmm0, %xmm1
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movl $.L.str.3, %edi
movl %r14d, %esi
movsd %xmm0, (%rsp) # 8-byte Spill
movb $1, %al
callq printf
incl %r14d
cmpl %r14d, %ebx
jne .LBB7_4
.LBB7_5: # %._crit_edge
movq d_mat(%rip), %rdi
callq hipFree
movq d_matT(%rip), %rdi
callq hipFree
movq d_matSym(%rip), %rdi
callq hipFree
movq h_mat(%rip), %rdi
callq free
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type TOTAL_SIZE,@object # @TOTAL_SIZE
.data
.globl TOTAL_SIZE
.p2align 3, 0x0
TOTAL_SIZE:
.quad 268435456 # 0x10000000
.size TOTAL_SIZE, 8
.type d_mat,@object # @d_mat
.bss
.globl d_mat
.p2align 3, 0x0
d_mat:
.quad 0
.size d_mat, 8
.type d_matT,@object # @d_matT
.globl d_matT
.p2align 3, 0x0
d_matT:
.quad 0
.size d_matT, 8
.type d_matSym,@object # @d_matSym
.globl d_matSym
.p2align 3, 0x0
d_matSym:
.quad 0
.size d_matSym, 8
.type h_mat,@object # @h_mat
.globl h_mat
.p2align 3, 0x0
h_mat:
.quad 0
.size h_mat, 8
.type _Z10initializePd,@object # @_Z10initializePd
.section .rodata,"a",@progbits
.globl _Z10initializePd
.p2align 3, 0x0
_Z10initializePd:
.quad _Z25__device_stub__initializePd
.size _Z10initializePd, 8
.type _Z9transposePdS_,@object # @_Z9transposePdS_
.globl _Z9transposePdS_
.p2align 3, 0x0
_Z9transposePdS_:
.quad _Z24__device_stub__transposePdS_
.size _Z9transposePdS_, 8
.type _Z14matrixMultiplyPdS_S_,@object # @_Z14matrixMultiplyPdS_S_
.globl _Z14matrixMultiplyPdS_S_
.p2align 3, 0x0
_Z14matrixMultiplyPdS_S_:
.quad _Z29__device_stub__matrixMultiplyPdS_S_
.size _Z14matrixMultiplyPdS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\n%d x %d Matrix\n\n"
.size .L.str.1, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "At %d\t%.8f s\n"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePd"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9transposePdS_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14matrixMultiplyPdS_S_"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too big of an input to be printed!"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nExecution times(sec)"
.size .Lstr.1, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePd
.addrsig_sym _Z24__device_stub__transposePdS_
.addrsig_sym _Z29__device_stub__matrixMultiplyPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_mat
.addrsig_sym d_matT
.addrsig_sym d_matSym
.addrsig_sym _Z10initializePd
.addrsig_sym _Z9transposePdS_
.addrsig_sym _Z14matrixMultiplyPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14matrixMultiplyPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3fff, PT ; /* 0x00003fff0000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R17, 0x3fff, P0 ; /* 0x00003fff1100780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.SHL.U32 R17, R17, 0x4000, RZ ; /* 0x0000400011117824 */
/* 0x000fe200078e00ff */
/*00b0*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ CS2R R26, SRZ ; /* 0x00000000001a7805 */
/* 0x000fe2000001ff00 */
/*00f0*/ IADD3 R19, R17, 0x1, RZ ; /* 0x0000000111137810 */
/* 0x000fe20007ffe0ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0120*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0130*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe4000f8e00ff */
/*0140*/ IMAD.WIDE R24, R17, 0x8, R4 ; /* 0x0000000811187825 */
/* 0x000fc800078e0204 */
/*0150*/ IMAD.WIDE R2, R0, 0x8, R2 ; /* 0x0000000800027825 */
/* 0x000fe400078e0202 */
/*0160*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea4000c1e1b00 */
/*0170*/ IMAD.WIDE R6, R19, 0x8, R4 ; /* 0x0000000813067825 */
/* 0x000fe400078e0204 */
/*0180*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ea8000c1e1b00 */
/*0190*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ee8000c1e1b00 */
/*01a0*/ LDG.E.64 R22, [R2.64+0x20000] ; /* 0x0200000402167981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R14, [R2.64+0x40000] ; /* 0x04000004020e7981 */
/* 0x000f28000c1e1b00 */
/*01d0*/ LDG.E.64 R10, [R2.64+0x60000] ; /* 0x06000004020a7981 */
/* 0x000f68000c1e1b00 */
/*01e0*/ LDG.E.64 R28, [R2.64+0x1e0000] ; /* 0x1e000004021c7981 */
/* 0x000f62000c1e1b00 */
/*01f0*/ DFMA R26, R8, R24, R26 ; /* 0x00000018081a722b */
/* 0x0060c6000000001a */
/*0200*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x001f68000c1e1b00 */
/*0210*/ LDG.E.64 R24, [R6.64+0x68] ; /* 0x0000680406187981 */
/* 0x000ea2000c1e1b00 */
/*0220*/ DFMA R26, R22, R20, R26 ; /* 0x00000014161a722b */
/* 0x008106000000001a */
/*0230*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x001ee8000c1e1b00 */
/*0240*/ LDG.E.64 R22, [R2.64+0x80000] ; /* 0x0800000402167981 */
/* 0x000ee2000c1e1b00 */
/*0250*/ DFMA R26, R14, R12, R26 ; /* 0x0000000c0e1a722b */
/* 0x010146000000001a */
/*0260*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001f28000c1e1b00 */
/*0270*/ LDG.E.64 R14, [R2.64+0xa0000] ; /* 0x0a000004020e7981 */
/* 0x000f22000c1e1b00 */
/*0280*/ DFMA R26, R10, R8, R26 ; /* 0x000000080a1a722b */
/* 0x0200c6000000001a */
/*0290*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x001f68000c1e1b00 */
/*02a0*/ LDG.E.64 R10, [R2.64+0xc0000] ; /* 0x0c000004020a7981 */
/* 0x000f62000c1e1b00 */
/*02b0*/ DFMA R26, R22, R20, R26 ; /* 0x00000014161a722b */
/* 0x008106000000001a */
/*02c0*/ LDG.E.64 R20, [R6.64+0x30] ; /* 0x0000300406147981 */
/* 0x001ee8000c1e1b00 */
/*02d0*/ LDG.E.64 R22, [R2.64+0xe0000] ; /* 0x0e00000402167981 */
/* 0x000ee2000c1e1b00 */
/*02e0*/ DFMA R26, R14, R12, R26 ; /* 0x0000000c0e1a722b */
/* 0x010146000000001a */
/*02f0*/ LDG.E.64 R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x001f28000c1e1b00 */
/*0300*/ LDG.E.64 R12, [R2.64+0x100000] ; /* 0x10000004020c7981 */
/* 0x000f22000c1e1b00 */
/*0310*/ DFMA R26, R10, R8, R26 ; /* 0x000000080a1a722b */
/* 0x0200c6000000001a */
/*0320*/ LDG.E.64 R10, [R6.64+0x40] ; /* 0x00004004060a7981 */
/* 0x001f68000c1e1b00 */
/*0330*/ LDG.E.64 R8, [R2.64+0x120000] ; /* 0x1200000402087981 */
/* 0x000f62000c1e1b00 */
/*0340*/ DFMA R26, R22, R20, R26 ; /* 0x00000014161a722b */
/* 0x008106000000001a */
/*0350*/ LDG.E.64 R22, [R6.64+0x48] ; /* 0x0000480406167981 */
/* 0x001ee8000c1e1b00 */
/*0360*/ LDG.E.64 R20, [R2.64+0x140000] ; /* 0x1400000402147981 */
/* 0x000ee2000c1e1b00 */
/*0370*/ DFMA R26, R12, R14, R26 ; /* 0x0000000e0c1a722b */
/* 0x010146000000001a */
/*0380*/ LDG.E.64 R14, [R6.64+0x50] ; /* 0x00005004060e7981 */
/* 0x001f28000c1e1b00 */
/*0390*/ LDG.E.64 R12, [R2.64+0x160000] ; /* 0x16000004020c7981 */
/* 0x000f22000c1e1b00 */
/*03a0*/ DFMA R26, R8, R10, R26 ; /* 0x0000000a081a722b */
/* 0x0200c6000000001a */
/*03b0*/ LDG.E.64 R10, [R6.64+0x58] ; /* 0x00005804060a7981 */
/* 0x001f68000c1e1b00 */
/*03c0*/ LDG.E.64 R8, [R2.64+0x180000] ; /* 0x1800000402087981 */
/* 0x000f62000c1e1b00 */
/*03d0*/ DFMA R26, R20, R22, R26 ; /* 0x00000016141a722b */
/* 0x008106000000001a */
/*03e0*/ LDG.E.64 R22, [R6.64+0x60] ; /* 0x0000600406167981 */
/* 0x001ee8000c1e1b00 */
/*03f0*/ LDG.E.64 R20, [R2.64+0x1a0000] ; /* 0x1a00000402147981 */
/* 0x000ee2000c1e1b00 */
/*0400*/ DFMA R12, R12, R14, R26 ; /* 0x0000000e0c0c722b */
/* 0x010146000000001a */
/*0410*/ LDG.E.64 R14, [R2.64+0x1c0000] ; /* 0x1c000004020e7981 */
/* 0x001ea8000c1e1b00 */
/*0420*/ LDG.E.64 R26, [R6.64+0x70] ; /* 0x00007004061a7981 */
/* 0x000f22000c1e1b00 */
/*0430*/ IADD3 R16, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R16, 0x4000, PT ; /* 0x000040001000780c */
/* 0x000fe20003f05270 */
/*0450*/ UIADD3 UR6, UP0, UR6, 0x200000, URZ ; /* 0x0020000006067890 */
/* 0x000fe2000ff1e03f */
/*0460*/ IADD3 R4, P1, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x000fc60007f3e0ff */
/*0470*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0480*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0490*/ DFMA R8, R8, R10, R12 ; /* 0x0000000a0808722b */
/* 0x020ecc000000000c */
/*04a0*/ DFMA R8, R20, R22, R8 ; /* 0x000000161408722b */
/* 0x008e8c0000000008 */
/*04b0*/ DFMA R8, R14, R24, R8 ; /* 0x000000180e08722b */
/* 0x004f0c0000000008 */
/*04c0*/ DFMA R26, R28, R26, R8 ; /* 0x0000001a1c1a722b */
/* 0x0100620000000008 */
/*04d0*/ @P0 BRA 0x120 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04e0*/ IADD3 R2, R0, R17, RZ ; /* 0x0000001100027210 */
/* 0x000fe40007ffe0ff */
/*04f0*/ MOV R3, 0x8 ; /* 0x0000000800037802 */
/* 0x000fca0000000f00 */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E.64 [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x002fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R5, 0x3fff, PT ; /* 0x00003fff0500780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3fff, P0 ; /* 0x00003fff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R2, R0, R5, 0xe ; /* 0x0000000500027211 */
/* 0x000fe200078e70ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00e0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ LEA R5, R5, R0, 0xe ; /* 0x0000000005057211 */
/* 0x000fca00078e70ff */
/*0100*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializePd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x3fff, PT ; /* 0x00003fff0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3fff, P0 ; /* 0x00003fff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ LEA R0, R0, R3, 0xe ; /* 0x0000000300007211 */
/* 0x000fe200078e70ff */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e2e0000201c00 */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePd
.globl _Z10initializePd
.p2align 8
.type _Z10initializePd,@function
_Z10initializePd:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB0_2
v_lshl_add_u32 v0, v0, 14, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[2:3], v0
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePd, .Lfunc_end0-_Z10initializePd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9transposePdS_
.globl _Z9transposePdS_
.p2align 8
.type _Z9transposePdS_,@function
_Z9transposePdS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v2, v0, 14, v1
v_lshl_add_u32 v0, v1, 14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9transposePdS_, .Lfunc_end1-_Z9transposePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14matrixMultiplyPdS_S_
.globl _Z14matrixMultiplyPdS_S_
.p2align 8
.type _Z14matrixMultiplyPdS_S_,@function
_Z14matrixMultiplyPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 14, v0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v4
v_mov_b32_e32 v4, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[10:11], 3, v[4:5]
v_add_nc_u32_e32 v4, 0x4000, v4
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 0x20000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[10:11], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[10:11], v[2:3]
s_cbranch_scc1 .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 14, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14matrixMultiplyPdS_S_, .Lfunc_end2-_Z14matrixMultiplyPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c5745_00000000-6_matCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Too big of an input to be printed!\n"
.text
.globl _Z11printMatrixPdi
.type _Z11printMatrixPdi, @function
_Z11printMatrixPdi:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPdi, .-_Z11printMatrixPdi
.globl _Z8allocatev
.type _Z8allocatev, @function
_Z8allocatev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq d_mat(%rip), %rdi
call cudaMalloc@PLT
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq d_matT(%rip), %rdi
call cudaMalloc@PLT
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq d_matSym(%rip), %rdi
call cudaMalloc@PLT
movq TOTAL_SIZE(%rip), %rax
leaq 0(,%rax,8), %rdi
call malloc@PLT
movq %rax, h_mat(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8allocatev, .-_Z8allocatev
.globl _Z10deallocatev
.type _Z10deallocatev, @function
_Z10deallocatev:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_mat(%rip), %rdi
call cudaFree@PLT
movq d_matT(%rip), %rdi
call cudaFree@PLT
movq d_matSym(%rip), %rdi
call cudaFree@PLT
movq h_mat(%rip), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10deallocatev, .-_Z10deallocatev
.globl _Z30__device_stub__Z10initializePdPd
.type _Z30__device_stub__Z10initializePdPd, @function
_Z30__device_stub__Z10initializePdPd:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initializePd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z10initializePdPd, .-_Z30__device_stub__Z10initializePdPd
.globl _Z10initializePd
.type _Z10initializePd, @function
_Z10initializePd:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10initializePdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10initializePd, .-_Z10initializePd
.globl _Z30__device_stub__Z9transposePdS_PdS_
.type _Z30__device_stub__Z9transposePdS_PdS_, @function
_Z30__device_stub__Z9transposePdS_PdS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z30__device_stub__Z9transposePdS_PdS_, .-_Z30__device_stub__Z9transposePdS_PdS_
.globl _Z9transposePdS_
.type _Z9transposePdS_, @function
_Z9transposePdS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z9transposePdS_, .-_Z9transposePdS_
.globl _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
.type _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_, @function
_Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixMultiplyPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_, .-_Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
.globl _Z14matrixMultiplyPdS_S_
.type _Z14matrixMultiplyPdS_S_, @function
_Z14matrixMultiplyPdS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z14matrixMultiplyPdS_S_, .-_Z14matrixMultiplyPdS_S_
.globl _Z24calculateSymmetricMatrixi
.type _Z24calculateSymmetricMatrixi, @function
_Z24calculateSymmetricMatrixi:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16384, %eax
movl $0, %edx
idivl %edi
movl %eax, 8(%rsp)
movl %eax, 12(%rsp)
movl $1, 16(%rsp)
movl %edi, 20(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
call cudaDeviceSynchronize@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
call cudaDeviceSynchronize@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq d_mat(%rip), %rdi
call _Z30__device_stub__Z10initializePdPd
jmp .L34
.L39:
movq d_matT(%rip), %rsi
movq d_mat(%rip), %rdi
call _Z30__device_stub__Z9transposePdS_PdS_
jmp .L35
.L40:
movq d_matSym(%rip), %rdx
movq d_matT(%rip), %rsi
movq d_mat(%rip), %rdi
call _Z38__device_stub__Z14matrixMultiplyPdS_S_PdS_S_
jmp .L36
.cfi_endproc
.LFE2059:
.size _Z24calculateSymmetricMatrixi, .-_Z24calculateSymmetricMatrixi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n%d x %d Matrix\n\n"
.LC3:
.string "\nExecution times(sec)\n"
.LC5:
.string "At %d\t%.8f s\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L50
movl $16384, %ecx
movl $16384, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z8allocatev
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebp
.L45:
movq $0x000000000, 8(%rsp)
movl $0, %ebx
leaq 16(%rsp), %r14
leaq 32(%rsp), %r13
leaq .LC5(%rip), %r12
.L44:
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
movl $32, %edi
call _Z24calculateSymmetricMatrixi
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
movq 40(%rsp), %rax
subq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq 32(%rsp), %rax
subq 16(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L44
.L43:
call _Z10deallocatev
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movl $16384, %ecx
movl $16384, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z8allocatev
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jg .L45
jmp .L43
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z14matrixMultiplyPdS_S_"
.LC7:
.string "_Z9transposePdS_"
.LC8:
.string "_Z10initializePd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_mat
.bss
.align 8
.type h_mat, @object
.size h_mat, 8
h_mat:
.zero 8
.globl d_matSym
.align 8
.type d_matSym, @object
.size d_matSym, 8
d_matSym:
.zero 8
.globl d_matT
.align 8
.type d_matT, @object
.size d_matT, 8
d_matT:
.zero 8
.globl d_mat
.align 8
.type d_mat, @object
.size d_mat, 8
d_mat:
.zero 8
.globl TOTAL_SIZE
.data
.align 8
.type TOTAL_SIZE, @object
.size TOTAL_SIZE, 8
TOTAL_SIZE:
.quad 268435456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matCUDA.hip"
.globl _Z11printMatrixPdi # -- Begin function _Z11printMatrixPdi
.p2align 4, 0x90
.type _Z11printMatrixPdi,@function
_Z11printMatrixPdi: # @_Z11printMatrixPdi
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPdi, .Lfunc_end0-_Z11printMatrixPdi
.cfi_endproc
# -- End function
.globl _Z8allocatev # -- Begin function _Z8allocatev
.p2align 4, 0x90
.type _Z8allocatev,@function
_Z8allocatev: # @_Z8allocatev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_mat, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matT, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matSym, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rdi
shlq $3, %rdi
callq malloc
movq %rax, h_mat(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8allocatev, .Lfunc_end1-_Z8allocatev
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePd # -- Begin function _Z25__device_stub__initializePd
.p2align 4, 0x90
.type _Z25__device_stub__initializePd,@function
_Z25__device_stub__initializePd: # @_Z25__device_stub__initializePd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initializePd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z25__device_stub__initializePd, .Lfunc_end2-_Z25__device_stub__initializePd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePdS_ # -- Begin function _Z24__device_stub__transposePdS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePdS_,@function
_Z24__device_stub__transposePdS_: # @_Z24__device_stub__transposePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z24__device_stub__transposePdS_, .Lfunc_end3-_Z24__device_stub__transposePdS_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__matrixMultiplyPdS_S_ # -- Begin function _Z29__device_stub__matrixMultiplyPdS_S_
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPdS_S_,@function
_Z29__device_stub__matrixMultiplyPdS_S_: # @_Z29__device_stub__matrixMultiplyPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrixMultiplyPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z29__device_stub__matrixMultiplyPdS_S_, .Lfunc_end4-_Z29__device_stub__matrixMultiplyPdS_S_
.cfi_endproc
# -- End function
.globl _Z24calculateSymmetricMatrixi # -- Begin function _Z24calculateSymmetricMatrixi
.p2align 4, 0x90
.type _Z24calculateSymmetricMatrixi,@function
_Z24calculateSymmetricMatrixi: # @_Z24calculateSymmetricMatrixi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $16384, %eax # imm = 0x4000
xorl %edx, %edx
idivl %edi
# kill: def $eax killed $eax def $rax
movq %rax, %rbx
shlq $32, %rbx
orq %rax, %rbx
movl %edi, %eax
movq %rax, %r14
shlq $32, %r14
orq %rax, %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq d_mat(%rip), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initializePd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq d_mat(%rip), %rax
movq d_matT(%rip), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePdS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
callq hipDeviceSynchronize
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq d_mat(%rip), %rax
movq d_matT(%rip), %rcx
movq d_matSym(%rip), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14matrixMultiplyPdS_S_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
callq hipDeviceSynchronize
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z24calculateSymmetricMatrixi, .Lfunc_end5-_Z24calculateSymmetricMatrixi
.cfi_endproc
# -- End function
.globl _Z10deallocatev # -- Begin function _Z10deallocatev
.p2align 4, 0x90
.type _Z10deallocatev,@function
_Z10deallocatev: # @_Z10deallocatev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_mat(%rip), %rdi
callq hipFree
movq d_matT(%rip), %rdi
callq hipFree
movq d_matSym(%rip), %rdi
callq hipFree
movq h_mat(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end6:
.size _Z10deallocatev, .Lfunc_end6-_Z10deallocatev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %ebx
cmpl $2, %edi
jl .LBB7_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB7_2:
xorl %r14d, %r14d
movl $.L.str.1, %edi
movl $16384, %esi # imm = 0x4000
movl $16384, %edx # imm = 0x4000
xorl %eax, %eax
callq printf
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_mat, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matT, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rsi
shlq $3, %rsi
movl $d_matSym, %edi
callq hipMalloc
movq TOTAL_SIZE(%rip), %rdi
shlq $3, %rdi
callq malloc
movq %rax, h_mat(%rip)
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB7_5
# %bb.3: # %.lr.ph
xorpd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
leaq 24(%rsp), %r15
leaq 8(%rsp), %r12
.p2align 4, 0x90
.LBB7_4: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movl $32, %edi
callq _Z24calculateSymmetricMatrixi
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
subq 32(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq 8(%rsp), %rax
divsd .LCPI7_0(%rip), %xmm0
subq 24(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
addsd %xmm0, %xmm1
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movl $.L.str.3, %edi
movl %r14d, %esi
movsd %xmm0, (%rsp) # 8-byte Spill
movb $1, %al
callq printf
incl %r14d
cmpl %r14d, %ebx
jne .LBB7_4
.LBB7_5: # %._crit_edge
movq d_mat(%rip), %rdi
callq hipFree
movq d_matT(%rip), %rdi
callq hipFree
movq d_matSym(%rip), %rdi
callq hipFree
movq h_mat(%rip), %rdi
callq free
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type TOTAL_SIZE,@object # @TOTAL_SIZE
.data
.globl TOTAL_SIZE
.p2align 3, 0x0
TOTAL_SIZE:
.quad 268435456 # 0x10000000
.size TOTAL_SIZE, 8
.type d_mat,@object # @d_mat
.bss
.globl d_mat
.p2align 3, 0x0
d_mat:
.quad 0
.size d_mat, 8
.type d_matT,@object # @d_matT
.globl d_matT
.p2align 3, 0x0
d_matT:
.quad 0
.size d_matT, 8
.type d_matSym,@object # @d_matSym
.globl d_matSym
.p2align 3, 0x0
d_matSym:
.quad 0
.size d_matSym, 8
.type h_mat,@object # @h_mat
.globl h_mat
.p2align 3, 0x0
h_mat:
.quad 0
.size h_mat, 8
.type _Z10initializePd,@object # @_Z10initializePd
.section .rodata,"a",@progbits
.globl _Z10initializePd
.p2align 3, 0x0
_Z10initializePd:
.quad _Z25__device_stub__initializePd
.size _Z10initializePd, 8
.type _Z9transposePdS_,@object # @_Z9transposePdS_
.globl _Z9transposePdS_
.p2align 3, 0x0
_Z9transposePdS_:
.quad _Z24__device_stub__transposePdS_
.size _Z9transposePdS_, 8
.type _Z14matrixMultiplyPdS_S_,@object # @_Z14matrixMultiplyPdS_S_
.globl _Z14matrixMultiplyPdS_S_
.p2align 3, 0x0
_Z14matrixMultiplyPdS_S_:
.quad _Z29__device_stub__matrixMultiplyPdS_S_
.size _Z14matrixMultiplyPdS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\n%d x %d Matrix\n\n"
.size .L.str.1, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "At %d\t%.8f s\n"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePd"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9transposePdS_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14matrixMultiplyPdS_S_"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too big of an input to be printed!"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nExecution times(sec)"
.size .Lstr.1, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePd
.addrsig_sym _Z24__device_stub__transposePdS_
.addrsig_sym _Z29__device_stub__matrixMultiplyPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_mat
.addrsig_sym d_matT
.addrsig_sym d_matSym
.addrsig_sym _Z10initializePd
.addrsig_sym _Z9transposePdS_
.addrsig_sym _Z14matrixMultiplyPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define THREADS 64
__global__ void vecSum(int *a, int *b, int size){
__shared__ int c[THREADS];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int stid = threadIdx.x;
if(tid < size){
c[stid] = a[tid];
c[stid] += b[tid];
}
__syncthreads();
if(tid < size){
a[tid] = c[stid];
}
}
int main(int argc, char* argv[]){
//initialization code
int size,threads,blocks;
float total_time;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
size = 2048*2048;
blocks = size/THREADS;
threads = THREADS;
while(blocks*threads < size)
blocks++;
int totalSize = size * sizeof(int);
int *a,*b,*dev_a,*dev_b;
cudaMalloc((void**)&dev_a,totalSize);
cudaMalloc((void**)&dev_b,totalSize);
a = (int*) malloc(totalSize);
b = (int*) malloc(totalSize);
//end mallocs
int idx;
for(idx=0;idx<size;idx++){
a[idx] = idx;
b[idx] = idx*2;
}
//copy to dev
cudaMemcpy(dev_a,a,totalSize,cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,totalSize,cudaMemcpyHostToDevice);
int iteration = 0;
float avg_time = 0.0;
for(iteration=0;iteration<10;iteration++){
//call kernel and measure times
cudaEventRecord(start,0);
vecSum<<<blocks,threads>>>(dev_a,dev_b,size);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&total_time,start,stop);
printf("\n time for %i blocks of %i threads : %f \n",blocks,threads,total_time);
avg_time+=total_time;
}
avg_time/=10.0;
printf("average time for %i size vector mult is %f ",size,avg_time);
//copy back and prints
cudaMemcpy(a,dev_a,totalSize,cudaMemcpyDeviceToHost);
for(idx=0;idx<size;idx+=size/5)
printf("\n a[%i]=%i\n",idx,a[idx]);
//free
free(a);
free(b);
cudaFree(dev_a);
cudaFree(dev_b);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z6vecSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x100 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R0 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R4.reuse, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xf0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000eaa000c1e1900 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e40000004800 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e680000004800 */
/*0130*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define THREADS 64
__global__ void vecSum(int *a, int *b, int size){
__shared__ int c[THREADS];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int stid = threadIdx.x;
if(tid < size){
c[stid] = a[tid];
c[stid] += b[tid];
}
__syncthreads();
if(tid < size){
a[tid] = c[stid];
}
}
int main(int argc, char* argv[]){
//initialization code
int size,threads,blocks;
float total_time;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
size = 2048*2048;
blocks = size/THREADS;
threads = THREADS;
while(blocks*threads < size)
blocks++;
int totalSize = size * sizeof(int);
int *a,*b,*dev_a,*dev_b;
cudaMalloc((void**)&dev_a,totalSize);
cudaMalloc((void**)&dev_b,totalSize);
a = (int*) malloc(totalSize);
b = (int*) malloc(totalSize);
//end mallocs
int idx;
for(idx=0;idx<size;idx++){
a[idx] = idx;
b[idx] = idx*2;
}
//copy to dev
cudaMemcpy(dev_a,a,totalSize,cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,totalSize,cudaMemcpyHostToDevice);
int iteration = 0;
float avg_time = 0.0;
for(iteration=0;iteration<10;iteration++){
//call kernel and measure times
cudaEventRecord(start,0);
vecSum<<<blocks,threads>>>(dev_a,dev_b,size);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&total_time,start,stop);
printf("\n time for %i blocks of %i threads : %f \n",blocks,threads,total_time);
avg_time+=total_time;
}
avg_time/=10.0;
printf("average time for %i size vector mult is %f ",size,avg_time);
//copy back and prints
cudaMemcpy(a,dev_a,totalSize,cudaMemcpyDeviceToHost);
for(idx=0;idx<size;idx+=size/5)
printf("\n a[%i]=%i\n",idx,a[idx]);
//free
free(a);
free(b);
cudaFree(dev_a);
cudaFree(dev_b);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_00194fed_00000000-6_CUDA_P9_SumaVectoresCompartida.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6vecSumPiS_iPiS_i
.type _Z28__device_stub__Z6vecSumPiS_iPiS_i, @function
_Z28__device_stub__Z6vecSumPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecSumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6vecSumPiS_iPiS_i, .-_Z28__device_stub__Z6vecSumPiS_iPiS_i
.globl _Z6vecSumPiS_i
.type _Z6vecSumPiS_i, @function
_Z6vecSumPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6vecSumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecSumPiS_i, .-_Z6vecSumPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\n time for %i blocks of %i threads : %f \n"
.align 8
.LC3:
.string "average time for %i size vector mult is %f "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n a[%i]=%i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl %eax, (%rbx,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, %r12d
movl $0x00000000, %r14d
leaq .LC1(%rip), %r13
jmp .L14
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl $64, %ecx
movl $65536, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movd %r14d, %xmm1
addss 12(%rsp), %xmm1
movd %xmm1, %r14d
subl $1, %r12d
je .L21
.L14:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $65536, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6vecSumPiS_iPiS_i
jmp .L13
.L21:
movaps %xmm1, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $4194304, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $16777216, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq .LC4(%rip), %r13
.L15:
movl (%rbx,%r12,4), %ecx
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $838860, %r12
cmpq $5033160, %r12
jne .L15
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6vecSumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecSumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define THREADS 64
__global__ void vecSum(int *a, int *b, int size){
__shared__ int c[THREADS];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int stid = threadIdx.x;
if(tid < size){
c[stid] = a[tid];
c[stid] += b[tid];
}
__syncthreads();
if(tid < size){
a[tid] = c[stid];
}
}
int main(int argc, char* argv[]){
//initialization code
int size,threads,blocks;
float total_time;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
size = 2048*2048;
blocks = size/THREADS;
threads = THREADS;
while(blocks*threads < size)
blocks++;
int totalSize = size * sizeof(int);
int *a,*b,*dev_a,*dev_b;
cudaMalloc((void**)&dev_a,totalSize);
cudaMalloc((void**)&dev_b,totalSize);
a = (int*) malloc(totalSize);
b = (int*) malloc(totalSize);
//end mallocs
int idx;
for(idx=0;idx<size;idx++){
a[idx] = idx;
b[idx] = idx*2;
}
//copy to dev
cudaMemcpy(dev_a,a,totalSize,cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,totalSize,cudaMemcpyHostToDevice);
int iteration = 0;
float avg_time = 0.0;
for(iteration=0;iteration<10;iteration++){
//call kernel and measure times
cudaEventRecord(start,0);
vecSum<<<blocks,threads>>>(dev_a,dev_b,size);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&total_time,start,stop);
printf("\n time for %i blocks of %i threads : %f \n",blocks,threads,total_time);
avg_time+=total_time;
}
avg_time/=10.0;
printf("average time for %i size vector mult is %f ",size,avg_time);
//copy back and prints
cudaMemcpy(a,dev_a,totalSize,cudaMemcpyDeviceToHost);
for(idx=0;idx<size;idx+=size/5)
printf("\n a[%i]=%i\n",idx,a[idx]);
//free
free(a);
free(b);
cudaFree(dev_a);
cudaFree(dev_b);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define THREADS 64
__global__ void vecSum(int *a, int *b, int size){
__shared__ int c[THREADS];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int stid = threadIdx.x;
if(tid < size){
c[stid] = a[tid];
c[stid] += b[tid];
}
__syncthreads();
if(tid < size){
a[tid] = c[stid];
}
}
int main(int argc, char* argv[]){
//initialization code
int size,threads,blocks;
float total_time;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
size = 2048*2048;
blocks = size/THREADS;
threads = THREADS;
while(blocks*threads < size)
blocks++;
int totalSize = size * sizeof(int);
int *a,*b,*dev_a,*dev_b;
hipMalloc((void**)&dev_a,totalSize);
hipMalloc((void**)&dev_b,totalSize);
a = (int*) malloc(totalSize);
b = (int*) malloc(totalSize);
//end mallocs
int idx;
for(idx=0;idx<size;idx++){
a[idx] = idx;
b[idx] = idx*2;
}
//copy to dev
hipMemcpy(dev_a,a,totalSize,hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,totalSize,hipMemcpyHostToDevice);
int iteration = 0;
float avg_time = 0.0;
for(iteration=0;iteration<10;iteration++){
//call kernel and measure times
hipEventRecord(start,0);
vecSum<<<blocks,threads>>>(dev_a,dev_b,size);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&total_time,start,stop);
printf("\n time for %i blocks of %i threads : %f \n",blocks,threads,total_time);
avg_time+=total_time;
}
avg_time/=10.0;
printf("average time for %i size vector mult is %f ",size,avg_time);
//copy back and prints
hipMemcpy(a,dev_a,totalSize,hipMemcpyDeviceToHost);
for(idx=0;idx<size;idx+=size/5)
printf("\n a[%i]=%i\n",idx,a[idx]);
//free
free(a);
free(b);
hipFree(dev_a);
hipFree(dev_b);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define THREADS 64
__global__ void vecSum(int *a, int *b, int size){
__shared__ int c[THREADS];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int stid = threadIdx.x;
if(tid < size){
c[stid] = a[tid];
c[stid] += b[tid];
}
__syncthreads();
if(tid < size){
a[tid] = c[stid];
}
}
int main(int argc, char* argv[]){
//initialization code
int size,threads,blocks;
float total_time;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
size = 2048*2048;
blocks = size/THREADS;
threads = THREADS;
while(blocks*threads < size)
blocks++;
int totalSize = size * sizeof(int);
int *a,*b,*dev_a,*dev_b;
hipMalloc((void**)&dev_a,totalSize);
hipMalloc((void**)&dev_b,totalSize);
a = (int*) malloc(totalSize);
b = (int*) malloc(totalSize);
//end mallocs
int idx;
for(idx=0;idx<size;idx++){
a[idx] = idx;
b[idx] = idx*2;
}
//copy to dev
hipMemcpy(dev_a,a,totalSize,hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,totalSize,hipMemcpyHostToDevice);
int iteration = 0;
float avg_time = 0.0;
for(iteration=0;iteration<10;iteration++){
//call kernel and measure times
hipEventRecord(start,0);
vecSum<<<blocks,threads>>>(dev_a,dev_b,size);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&total_time,start,stop);
printf("\n time for %i blocks of %i threads : %f \n",blocks,threads,total_time);
avg_time+=total_time;
}
avg_time/=10.0;
printf("average time for %i size vector mult is %f ",size,avg_time);
//copy back and prints
hipMemcpy(a,dev_a,totalSize,hipMemcpyDeviceToHost);
for(idx=0;idx<size;idx+=size/5)
printf("\n a[%i]=%i\n",idx,a[idx]);
//free
free(a);
free(b);
hipFree(dev_a);
hipFree(dev_b);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecSumPiS_i
.globl _Z6vecSumPiS_i
.p2align 8
.type _Z6vecSumPiS_i,@function
_Z6vecSumPiS_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v4, s0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s0, s6, v3
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecSumPiS_i
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecSumPiS_i, .Lfunc_end0-_Z6vecSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define THREADS 64
__global__ void vecSum(int *a, int *b, int size){
__shared__ int c[THREADS];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int stid = threadIdx.x;
if(tid < size){
c[stid] = a[tid];
c[stid] += b[tid];
}
__syncthreads();
if(tid < size){
a[tid] = c[stid];
}
}
int main(int argc, char* argv[]){
//initialization code
int size,threads,blocks;
float total_time;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
size = 2048*2048;
blocks = size/THREADS;
threads = THREADS;
while(blocks*threads < size)
blocks++;
int totalSize = size * sizeof(int);
int *a,*b,*dev_a,*dev_b;
hipMalloc((void**)&dev_a,totalSize);
hipMalloc((void**)&dev_b,totalSize);
a = (int*) malloc(totalSize);
b = (int*) malloc(totalSize);
//end mallocs
int idx;
for(idx=0;idx<size;idx++){
a[idx] = idx;
b[idx] = idx*2;
}
//copy to dev
hipMemcpy(dev_a,a,totalSize,hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,totalSize,hipMemcpyHostToDevice);
int iteration = 0;
float avg_time = 0.0;
for(iteration=0;iteration<10;iteration++){
//call kernel and measure times
hipEventRecord(start,0);
vecSum<<<blocks,threads>>>(dev_a,dev_b,size);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&total_time,start,stop);
printf("\n time for %i blocks of %i threads : %f \n",blocks,threads,total_time);
avg_time+=total_time;
}
avg_time/=10.0;
printf("average time for %i size vector mult is %f ",size,avg_time);
//copy back and prints
hipMemcpy(a,dev_a,totalSize,hipMemcpyDeviceToHost);
for(idx=0;idx<size;idx+=size/5)
printf("\n a[%i]=%i\n",idx,a[idx]);
//free
free(a);
free(b);
hipFree(dev_a);
hipFree(dev_b);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "CUDA_P9_SumaVectoresCompartida.hip"
.globl _Z21__device_stub__vecSumPiS_i # -- Begin function _Z21__device_stub__vecSumPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__vecSumPiS_i,@function
_Z21__device_stub__vecSumPiS_i: # @_Z21__device_stub__vecSumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecSumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecSumPiS_i, .Lfunc_end0-_Z21__device_stub__vecSumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
movl %eax, (%r14,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $4194304, %rcx # imm = 0x400000
jne .LBB1_1
# %bb.2:
movabsq $4294967360, %r15 # imm = 0x100000040
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movl $10, %r13d
leaq 65472(%r15), %r12
leaq 4(%rsp), %rbp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
movq %rbp, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl $65536, %esi # imm = 0x10000
movl $64, %edx
movb $1, %al
callq printf
movss 40(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 4(%rsp), %xmm0
decl %r13d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, 40(%rsp) # 4-byte Spill
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $4194304, 44(%rsp) # imm = 0x400000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z6vecSumPiS_i, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl $4194304, %esi # imm = 0x400000
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq 838860(%r15), %rax
cmpq $3355444, %r15 # imm = 0x333334
movq %rax, %r15
jb .LBB1_7
# %bb.8:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecSumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecSumPiS_i,@object # @_Z6vecSumPiS_i
.section .rodata,"a",@progbits
.globl _Z6vecSumPiS_i
.p2align 3, 0x0
_Z6vecSumPiS_i:
.quad _Z21__device_stub__vecSumPiS_i
.size _Z6vecSumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n time for %i blocks of %i threads : %f \n"
.size .L.str, 42
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "average time for %i size vector mult is %f "
.size .L.str.1, 44
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n a[%i]=%i\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecSumPiS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecSumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecSumPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x100 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R0 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R4.reuse, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xf0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000eaa000c1e1900 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e40000004800 */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e680000004800 */
/*0130*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecSumPiS_i
.globl _Z6vecSumPiS_i
.p2align 8
.type _Z6vecSumPiS_i,@function
_Z6vecSumPiS_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v4, s0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s0, s6, v3
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecSumPiS_i
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecSumPiS_i, .Lfunc_end0-_Z6vecSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00194fed_00000000-6_CUDA_P9_SumaVectoresCompartida.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6vecSumPiS_iPiS_i
.type _Z28__device_stub__Z6vecSumPiS_iPiS_i, @function
_Z28__device_stub__Z6vecSumPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecSumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6vecSumPiS_iPiS_i, .-_Z28__device_stub__Z6vecSumPiS_iPiS_i
.globl _Z6vecSumPiS_i
.type _Z6vecSumPiS_i, @function
_Z6vecSumPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6vecSumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecSumPiS_i, .-_Z6vecSumPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\n time for %i blocks of %i threads : %f \n"
.align 8
.LC3:
.string "average time for %i size vector mult is %f "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\n a[%i]=%i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl %eax, (%rbx,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, %r12d
movl $0x00000000, %r14d
leaq .LC1(%rip), %r13
jmp .L14
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl $64, %ecx
movl $65536, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movd %r14d, %xmm1
addss 12(%rsp), %xmm1
movd %xmm1, %r14d
subl $1, %r12d
je .L21
.L14:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $65536, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6vecSumPiS_iPiS_i
jmp .L13
.L21:
movaps %xmm1, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $4194304, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $16777216, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq .LC4(%rip), %r13
.L15:
movl (%rbx,%r12,4), %ecx
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $838860, %r12
cmpq $5033160, %r12
jne .L15
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6vecSumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecSumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_P9_SumaVectoresCompartida.hip"
.globl _Z21__device_stub__vecSumPiS_i # -- Begin function _Z21__device_stub__vecSumPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__vecSumPiS_i,@function
_Z21__device_stub__vecSumPiS_i: # @_Z21__device_stub__vecSumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecSumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecSumPiS_i, .Lfunc_end0-_Z21__device_stub__vecSumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
movl %eax, (%r14,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $4194304, %rcx # imm = 0x400000
jne .LBB1_1
# %bb.2:
movabsq $4294967360, %r15 # imm = 0x100000040
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movl $10, %r13d
leaq 65472(%r15), %r12
leaq 4(%rsp), %rbp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
movq %rbp, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl $65536, %esi # imm = 0x10000
movl $64, %edx
movb $1, %al
callq printf
movss 40(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 4(%rsp), %xmm0
decl %r13d
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, 40(%rsp) # 4-byte Spill
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $4194304, 44(%rsp) # imm = 0x400000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z6vecSumPiS_i, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl $4194304, %esi # imm = 0x400000
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq 838860(%r15), %rax
cmpq $3355444, %r15 # imm = 0x333334
movq %rax, %r15
jb .LBB1_7
# %bb.8:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecSumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecSumPiS_i,@object # @_Z6vecSumPiS_i
.section .rodata,"a",@progbits
.globl _Z6vecSumPiS_i
.p2align 3, 0x0
_Z6vecSumPiS_i:
.quad _Z21__device_stub__vecSumPiS_i
.size _Z6vecSumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n time for %i blocks of %i threads : %f \n"
.size .L.str, 42
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "average time for %i size vector mult is %f "
.size .L.str.1, 44
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n a[%i]=%i\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecSumPiS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecSumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecSumPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<assert.h>
#include<cuda.h>
#define N 1000000
#define HANDLE_ERROR( err )(handleCudaError( err, __FILE__, __LINE__ ) )
int handleCudaError(cudaError_t cut,const char* file, int line)
{
if(cut != cudaSuccess)
{
printf("%s : File: %s Line: %d \n",cudaGetErrorString(cut),file,line);
return -1 ;
}
return 0;
}
int main(int argc, char* argv[])
{
// ============= INIT =====================
int *a_host= NULL;
int *b_host=NULL;
int *a_device_ptr = NULL ;
int *b_device_ptr = NULL ;
a_host=(int*)malloc(sizeof(int)*N);
b_host=(int*)malloc(sizeof(int)*N);
assert(a_host);
for(unsigned int i = 0; i < N; ++i)
{
a_host[i] = i ;
b_host[i] = 0;
}
HANDLE_ERROR(cudaMalloc(&a_device_ptr, sizeof(int)*N)); // malloc of a_device
HANDLE_ERROR(cudaMalloc(&b_device_ptr, sizeof(int)*N)); // malloc of b_device
//Transfer a_host to a_device
HANDLE_ERROR(cudaMemcpy(a_device_ptr, a_host, sizeof(int)*N, cudaMemcpyHostToDevice));
//Transfer a_device to b_device
HANDLE_ERROR(cudaMemcpy(b_device_ptr, a_device_ptr, sizeof(int)*N, cudaMemcpyDeviceToDevice));
//Transfer b_device to b_host
HANDLE_ERROR(cudaMemcpy(b_host, b_device_ptr, sizeof(int)*N, cudaMemcpyDeviceToHost));
//transfercheck
for(unsigned int i = 0; i < N; ++i)
{
//correct_transfer = correct_transfer & (a_host[i] == b_host[i]);
if(a_host[i] != b_host[i]) {
printf("Incorrect result at %d with %d and %d\n", i, a_host[i], b_host[i]);
return -1 ;
}
}
printf("Correct transfer \n");
HANDLE_ERROR(cudaFree(a_device_ptr));
HANDLE_ERROR(cudaFree(b_device_ptr));
free(a_host);
free(b_host);
a_host= NULL;
b_host= NULL;
return 0 ;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<assert.h>
#include<cuda.h>
#define N 1000000
#define HANDLE_ERROR( err )(handleCudaError( err, __FILE__, __LINE__ ) )
int handleCudaError(cudaError_t cut,const char* file, int line)
{
if(cut != cudaSuccess)
{
printf("%s : File: %s Line: %d \n",cudaGetErrorString(cut),file,line);
return -1 ;
}
return 0;
}
int main(int argc, char* argv[])
{
// ============= INIT =====================
int *a_host= NULL;
int *b_host=NULL;
int *a_device_ptr = NULL ;
int *b_device_ptr = NULL ;
a_host=(int*)malloc(sizeof(int)*N);
b_host=(int*)malloc(sizeof(int)*N);
assert(a_host);
for(unsigned int i = 0; i < N; ++i)
{
a_host[i] = i ;
b_host[i] = 0;
}
HANDLE_ERROR(cudaMalloc(&a_device_ptr, sizeof(int)*N)); // malloc of a_device
HANDLE_ERROR(cudaMalloc(&b_device_ptr, sizeof(int)*N)); // malloc of b_device
//Transfer a_host to a_device
HANDLE_ERROR(cudaMemcpy(a_device_ptr, a_host, sizeof(int)*N, cudaMemcpyHostToDevice));
//Transfer a_device to b_device
HANDLE_ERROR(cudaMemcpy(b_device_ptr, a_device_ptr, sizeof(int)*N, cudaMemcpyDeviceToDevice));
//Transfer b_device to b_host
HANDLE_ERROR(cudaMemcpy(b_host, b_device_ptr, sizeof(int)*N, cudaMemcpyDeviceToHost));
//transfercheck
for(unsigned int i = 0; i < N; ++i)
{
//correct_transfer = correct_transfer & (a_host[i] == b_host[i]);
if(a_host[i] != b_host[i]) {
printf("Incorrect result at %d with %d and %d\n", i, a_host[i], b_host[i]);
return -1 ;
}
}
printf("Correct transfer \n");
HANDLE_ERROR(cudaFree(a_device_ptr));
HANDLE_ERROR(cudaFree(b_device_ptr));
free(a_host);
free(b_host);
a_host= NULL;
b_host= NULL;
return 0 ;
} | .file "tmpxft_0003e688_00000000-6_exercise1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s : File: %s Line: %d \n"
.text
.globl _Z15handleCudaError9cudaErrorPKci
.type _Z15handleCudaError9cudaErrorPKci, @function
_Z15handleCudaError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L10
movl $0, %eax
ret
.L10:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15handleCudaError9cudaErrorPKci, .-_Z15handleCudaError9cudaErrorPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/StillerPatrick/parallel-programming-tutorial/master/exercise1/exercise1.cu"
.align 8
.LC2:
.string "Incorrect result at %d with %d and %d\n"
.section .rodata.str1.1
.LC3:
.string "Correct transfer \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $41, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $42, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $45, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $3, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $49, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $2, %ecx
movl $4000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $53, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $0, %edx
.L15:
movl 0(%rbp,%rdx,4), %ecx
movl (%rbx,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L20
addq $1, %rdx
cmpq $1000000, %rdx
jne .L15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $68, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $69, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
jmp .L11
.L20:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
.L11:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<assert.h>
#include<cuda.h>
#define N 1000000
#define HANDLE_ERROR( err )(handleCudaError( err, __FILE__, __LINE__ ) )
int handleCudaError(cudaError_t cut,const char* file, int line)
{
if(cut != cudaSuccess)
{
printf("%s : File: %s Line: %d \n",cudaGetErrorString(cut),file,line);
return -1 ;
}
return 0;
}
int main(int argc, char* argv[])
{
// ============= INIT =====================
int *a_host= NULL;
int *b_host=NULL;
int *a_device_ptr = NULL ;
int *b_device_ptr = NULL ;
a_host=(int*)malloc(sizeof(int)*N);
b_host=(int*)malloc(sizeof(int)*N);
assert(a_host);
for(unsigned int i = 0; i < N; ++i)
{
a_host[i] = i ;
b_host[i] = 0;
}
HANDLE_ERROR(cudaMalloc(&a_device_ptr, sizeof(int)*N)); // malloc of a_device
HANDLE_ERROR(cudaMalloc(&b_device_ptr, sizeof(int)*N)); // malloc of b_device
//Transfer a_host to a_device
HANDLE_ERROR(cudaMemcpy(a_device_ptr, a_host, sizeof(int)*N, cudaMemcpyHostToDevice));
//Transfer a_device to b_device
HANDLE_ERROR(cudaMemcpy(b_device_ptr, a_device_ptr, sizeof(int)*N, cudaMemcpyDeviceToDevice));
//Transfer b_device to b_host
HANDLE_ERROR(cudaMemcpy(b_host, b_device_ptr, sizeof(int)*N, cudaMemcpyDeviceToHost));
//transfercheck
for(unsigned int i = 0; i < N; ++i)
{
//correct_transfer = correct_transfer & (a_host[i] == b_host[i]);
if(a_host[i] != b_host[i]) {
printf("Incorrect result at %d with %d and %d\n", i, a_host[i], b_host[i]);
return -1 ;
}
}
printf("Correct transfer \n");
HANDLE_ERROR(cudaFree(a_device_ptr));
HANDLE_ERROR(cudaFree(b_device_ptr));
free(a_host);
free(b_host);
a_host= NULL;
b_host= NULL;
return 0 ;
} | #include<stdio.h>
#include<assert.h>
#include<hip/hip_runtime.h>
#define N 1000000
#define HANDLE_ERROR( err )(handleCudaError( err, __FILE__, __LINE__ ) )
int handleCudaError(hipError_t cut,const char* file, int line)
{
if(cut != hipSuccess)
{
printf("%s : File: %s Line: %d \n",hipGetErrorString(cut),file,line);
return -1 ;
}
return 0;
}
int main(int argc, char* argv[])
{
// ============= INIT =====================
int *a_host= NULL;
int *b_host=NULL;
int *a_device_ptr = NULL ;
int *b_device_ptr = NULL ;
a_host=(int*)malloc(sizeof(int)*N);
b_host=(int*)malloc(sizeof(int)*N);
assert(a_host);
for(unsigned int i = 0; i < N; ++i)
{
a_host[i] = i ;
b_host[i] = 0;
}
HANDLE_ERROR(hipMalloc(&a_device_ptr, sizeof(int)*N)); // malloc of a_device
HANDLE_ERROR(hipMalloc(&b_device_ptr, sizeof(int)*N)); // malloc of b_device
//Transfer a_host to a_device
HANDLE_ERROR(hipMemcpy(a_device_ptr, a_host, sizeof(int)*N, hipMemcpyHostToDevice));
//Transfer a_device to b_device
HANDLE_ERROR(hipMemcpy(b_device_ptr, a_device_ptr, sizeof(int)*N, hipMemcpyDeviceToDevice));
//Transfer b_device to b_host
HANDLE_ERROR(hipMemcpy(b_host, b_device_ptr, sizeof(int)*N, hipMemcpyDeviceToHost));
//transfercheck
for(unsigned int i = 0; i < N; ++i)
{
//correct_transfer = correct_transfer & (a_host[i] == b_host[i]);
if(a_host[i] != b_host[i]) {
printf("Incorrect result at %d with %d and %d\n", i, a_host[i], b_host[i]);
return -1 ;
}
}
printf("Correct transfer \n");
HANDLE_ERROR(hipFree(a_device_ptr));
HANDLE_ERROR(hipFree(b_device_ptr));
free(a_host);
free(b_host);
a_host= NULL;
b_host= NULL;
return 0 ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<assert.h>
#include<hip/hip_runtime.h>
#define N 1000000
#define HANDLE_ERROR( err )(handleCudaError( err, __FILE__, __LINE__ ) )
int handleCudaError(hipError_t cut,const char* file, int line)
{
if(cut != hipSuccess)
{
printf("%s : File: %s Line: %d \n",hipGetErrorString(cut),file,line);
return -1 ;
}
return 0;
}
int main(int argc, char* argv[])
{
// ============= INIT =====================
int *a_host= NULL;
int *b_host=NULL;
int *a_device_ptr = NULL ;
int *b_device_ptr = NULL ;
a_host=(int*)malloc(sizeof(int)*N);
b_host=(int*)malloc(sizeof(int)*N);
assert(a_host);
for(unsigned int i = 0; i < N; ++i)
{
a_host[i] = i ;
b_host[i] = 0;
}
HANDLE_ERROR(hipMalloc(&a_device_ptr, sizeof(int)*N)); // malloc of a_device
HANDLE_ERROR(hipMalloc(&b_device_ptr, sizeof(int)*N)); // malloc of b_device
//Transfer a_host to a_device
HANDLE_ERROR(hipMemcpy(a_device_ptr, a_host, sizeof(int)*N, hipMemcpyHostToDevice));
//Transfer a_device to b_device
HANDLE_ERROR(hipMemcpy(b_device_ptr, a_device_ptr, sizeof(int)*N, hipMemcpyDeviceToDevice));
//Transfer b_device to b_host
HANDLE_ERROR(hipMemcpy(b_host, b_device_ptr, sizeof(int)*N, hipMemcpyDeviceToHost));
//transfercheck
for(unsigned int i = 0; i < N; ++i)
{
//correct_transfer = correct_transfer & (a_host[i] == b_host[i]);
if(a_host[i] != b_host[i]) {
printf("Incorrect result at %d with %d and %d\n", i, a_host[i], b_host[i]);
return -1 ;
}
}
printf("Correct transfer \n");
HANDLE_ERROR(hipFree(a_device_ptr));
HANDLE_ERROR(hipFree(b_device_ptr));
free(a_host);
free(b_host);
a_host= NULL;
b_host= NULL;
return 0 ;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<assert.h>
#include<hip/hip_runtime.h>
#define N 1000000
#define HANDLE_ERROR( err )(handleCudaError( err, __FILE__, __LINE__ ) )
int handleCudaError(hipError_t cut,const char* file, int line)
{
if(cut != hipSuccess)
{
printf("%s : File: %s Line: %d \n",hipGetErrorString(cut),file,line);
return -1 ;
}
return 0;
}
int main(int argc, char* argv[])
{
// ============= INIT =====================
int *a_host= NULL;
int *b_host=NULL;
int *a_device_ptr = NULL ;
int *b_device_ptr = NULL ;
a_host=(int*)malloc(sizeof(int)*N);
b_host=(int*)malloc(sizeof(int)*N);
assert(a_host);
for(unsigned int i = 0; i < N; ++i)
{
a_host[i] = i ;
b_host[i] = 0;
}
HANDLE_ERROR(hipMalloc(&a_device_ptr, sizeof(int)*N)); // malloc of a_device
HANDLE_ERROR(hipMalloc(&b_device_ptr, sizeof(int)*N)); // malloc of b_device
//Transfer a_host to a_device
HANDLE_ERROR(hipMemcpy(a_device_ptr, a_host, sizeof(int)*N, hipMemcpyHostToDevice));
//Transfer a_device to b_device
HANDLE_ERROR(hipMemcpy(b_device_ptr, a_device_ptr, sizeof(int)*N, hipMemcpyDeviceToDevice));
//Transfer b_device to b_host
HANDLE_ERROR(hipMemcpy(b_host, b_device_ptr, sizeof(int)*N, hipMemcpyDeviceToHost));
//transfercheck
for(unsigned int i = 0; i < N; ++i)
{
//correct_transfer = correct_transfer & (a_host[i] == b_host[i]);
if(a_host[i] != b_host[i]) {
printf("Incorrect result at %d with %d and %d\n", i, a_host[i], b_host[i]);
return -1 ;
}
}
printf("Correct transfer \n");
HANDLE_ERROR(hipFree(a_device_ptr));
HANDLE_ERROR(hipFree(b_device_ptr));
free(a_host);
free(b_host);
a_host= NULL;
b_host= NULL;
return 0 ;
} | .text
.file "exercise1.hip"
.globl _Z15handleCudaError10hipError_tPKci # -- Begin function _Z15handleCudaError10hipError_tPKci
.p2align 4, 0x90
.type _Z15handleCudaError10hipError_tPKci,@function
_Z15handleCudaError10hipError_tPKci: # @_Z15handleCudaError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB0_1
# %bb.2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ebx
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movq %r14, %rdx
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $-1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z15handleCudaError10hipError_tPKci, .Lfunc_end0-_Z15handleCudaError10hipError_tPKci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r15d, (%rbx,%r15,4)
incq %r15
cmpq $1000000, %r15 # imm = 0xF4240
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $41, %ecx
xorl %eax, %eax
callq printf
.LBB1_4: # %_Z15handleCudaError10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $42, %ecx
xorl %eax, %eax
callq printf
.LBB1_6: # %_Z15handleCudaError10hipError_tPKci.exit30
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $45, %ecx
xorl %eax, %eax
callq printf
.LBB1_8: # %_Z15handleCudaError10hipError_tPKci.exit33
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $3, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
xorl %eax, %eax
callq printf
.LBB1_10: # %_Z15handleCudaError10hipError_tPKci.exit36
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $53, %ecx
xorl %eax, %eax
callq printf
.LBB1_12: # %_Z15handleCudaError10hipError_tPKci.exit39
movl (%rbx), %edx
movl (%r14), %ecx
xorl %esi, %esi
movl $0, %ebp
cmpl %ecx, %edx
jne .LBB1_17
# %bb.13: # %.lr.ph.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $999999, %rsi # imm = 0xF423F
je .LBB1_18
# %bb.15: # in Loop: Header=BB1_14 Depth=1
movl 4(%rbx,%rsi,4), %edx
movl 4(%r14,%rsi,4), %ecx
incq %rsi
cmpl %ecx, %edx
je .LBB1_14
# %bb.16: # %._crit_edge
leaq -1(%rsi), %rax
cmpq $999999, %rax # imm = 0xF423F
setae %bpl
.LBB1_17:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $-1, %eax
testb %bpl, %bpl
jne .LBB1_20
jmp .LBB1_25
.LBB1_18: # %.loopexit.loopexit
setae %bpl
xorl %eax, %eax
testb %bpl, %bpl
je .LBB1_25
.LBB1_20:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $68, %ecx
xorl %eax, %eax
callq printf
.LBB1_22: # %_Z15handleCudaError10hipError_tPKci.exit42
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_24
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $69, %ecx
xorl %eax, %eax
callq printf
.LBB1_24: # %_Z15handleCudaError10hipError_tPKci.exit45
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
.LBB1_25:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s : File: %s Line: %d \n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/StillerPatrick/parallel-programming-tutorial/master/exercise1/exercise1.hip"
.size .L.str.1, 133
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Incorrect result at %d with %d and %d\n"
.size .L.str.2, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct transfer "
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003e688_00000000-6_exercise1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s : File: %s Line: %d \n"
.text
.globl _Z15handleCudaError9cudaErrorPKci
.type _Z15handleCudaError9cudaErrorPKci, @function
_Z15handleCudaError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L10
movl $0, %eax
ret
.L10:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15handleCudaError9cudaErrorPKci, .-_Z15handleCudaError9cudaErrorPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/StillerPatrick/parallel-programming-tutorial/master/exercise1/exercise1.cu"
.align 8
.LC2:
.string "Incorrect result at %d with %d and %d\n"
.section .rodata.str1.1
.LC3:
.string "Correct transfer \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $41, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $42, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $45, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $3, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $49, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $2, %ecx
movl $4000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $53, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movl $0, %edx
.L15:
movl 0(%rbp,%rdx,4), %ecx
movl (%rbx,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L20
addq $1, %rdx
cmpq $1000000, %rdx
jne .L15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $68, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $69, %edx
movq %r12, %rsi
call _Z15handleCudaError9cudaErrorPKci
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
jmp .L11
.L20:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
.L11:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise1.hip"
.globl _Z15handleCudaError10hipError_tPKci # -- Begin function _Z15handleCudaError10hipError_tPKci
.p2align 4, 0x90
.type _Z15handleCudaError10hipError_tPKci,@function
_Z15handleCudaError10hipError_tPKci: # @_Z15handleCudaError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB0_1
# %bb.2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ebx
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movq %r14, %rdx
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $-1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z15handleCudaError10hipError_tPKci, .Lfunc_end0-_Z15handleCudaError10hipError_tPKci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r15d, (%rbx,%r15,4)
incq %r15
cmpq $1000000, %r15 # imm = 0xF4240
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $41, %ecx
xorl %eax, %eax
callq printf
.LBB1_4: # %_Z15handleCudaError10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $42, %ecx
xorl %eax, %eax
callq printf
.LBB1_6: # %_Z15handleCudaError10hipError_tPKci.exit30
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $45, %ecx
xorl %eax, %eax
callq printf
.LBB1_8: # %_Z15handleCudaError10hipError_tPKci.exit33
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $3, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
xorl %eax, %eax
callq printf
.LBB1_10: # %_Z15handleCudaError10hipError_tPKci.exit36
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $53, %ecx
xorl %eax, %eax
callq printf
.LBB1_12: # %_Z15handleCudaError10hipError_tPKci.exit39
movl (%rbx), %edx
movl (%r14), %ecx
xorl %esi, %esi
movl $0, %ebp
cmpl %ecx, %edx
jne .LBB1_17
# %bb.13: # %.lr.ph.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $999999, %rsi # imm = 0xF423F
je .LBB1_18
# %bb.15: # in Loop: Header=BB1_14 Depth=1
movl 4(%rbx,%rsi,4), %edx
movl 4(%r14,%rsi,4), %ecx
incq %rsi
cmpl %ecx, %edx
je .LBB1_14
# %bb.16: # %._crit_edge
leaq -1(%rsi), %rax
cmpq $999999, %rax # imm = 0xF423F
setae %bpl
.LBB1_17:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $-1, %eax
testb %bpl, %bpl
jne .LBB1_20
jmp .LBB1_25
.LBB1_18: # %.loopexit.loopexit
setae %bpl
xorl %eax, %eax
testb %bpl, %bpl
je .LBB1_25
.LBB1_20:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $68, %ecx
xorl %eax, %eax
callq printf
.LBB1_22: # %_Z15handleCudaError10hipError_tPKci.exit42
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_24
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $69, %ecx
xorl %eax, %eax
callq printf
.LBB1_24: # %_Z15handleCudaError10hipError_tPKci.exit45
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
.LBB1_25:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s : File: %s Line: %d \n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/StillerPatrick/parallel-programming-tutorial/master/exercise1/exercise1.hip"
.size .L.str.1, 133
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Incorrect result at %d with %d and %d\n"
.size .L.str.2, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct transfer "
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// TP: Lancer un kernel vide sur le GPU
//
#include <iostream>
__global__ void emptyKernel ();
int main(int argc, char** argv) {
cudaSetDevice(0);
emptyKernel<<<1,1>>>();
cudaDeviceSynchronize();
std::cout << "Hello, CUDA!" << std::endl;
return 0;
}
__global__ void emptyKernel(){
// Empty
} | code for sm_80
Function : _Z11emptyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// TP: Lancer un kernel vide sur le GPU
//
#include <iostream>
__global__ void emptyKernel ();
int main(int argc, char** argv) {
cudaSetDevice(0);
emptyKernel<<<1,1>>>();
cudaDeviceSynchronize();
std::cout << "Hello, CUDA!" << std::endl;
return 0;
}
__global__ void emptyKernel(){
// Empty
} | .file "tmpxft_000f3a79_00000000-6_empty-kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11emptyKernelvv
.type _Z30__device_stub__Z11emptyKernelvv, @function
_Z30__device_stub__Z11emptyKernelvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11emptyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z11emptyKernelvv, .-_Z30__device_stub__Z11emptyKernelvv
.globl _Z11emptyKernelv
.type _Z11emptyKernelv, @function
_Z11emptyKernelv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11emptyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11emptyKernelv, .-_Z11emptyKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, CUDA!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call cudaSetDevice@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11emptyKernelvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11emptyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11emptyKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// TP: Lancer un kernel vide sur le GPU
//
#include <iostream>
__global__ void emptyKernel ();
int main(int argc, char** argv) {
cudaSetDevice(0);
emptyKernel<<<1,1>>>();
cudaDeviceSynchronize();
std::cout << "Hello, CUDA!" << std::endl;
return 0;
}
__global__ void emptyKernel(){
// Empty
} | //
// TP: Lancer un kernel vide sur le GPU
//
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void emptyKernel ();
int main(int argc, char** argv) {
hipSetDevice(0);
emptyKernel<<<1,1>>>();
hipDeviceSynchronize();
std::cout << "Hello, CUDA!" << std::endl;
return 0;
}
__global__ void emptyKernel(){
// Empty
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// TP: Lancer un kernel vide sur le GPU
//
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void emptyKernel ();
int main(int argc, char** argv) {
hipSetDevice(0);
emptyKernel<<<1,1>>>();
hipDeviceSynchronize();
std::cout << "Hello, CUDA!" << std::endl;
return 0;
}
__global__ void emptyKernel(){
// Empty
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11emptyKernelv
.globl _Z11emptyKernelv
.p2align 8
.type _Z11emptyKernelv,@function
_Z11emptyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11emptyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11emptyKernelv, .Lfunc_end0-_Z11emptyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11emptyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11emptyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// TP: Lancer un kernel vide sur le GPU
//
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void emptyKernel ();
int main(int argc, char** argv) {
hipSetDevice(0);
emptyKernel<<<1,1>>>();
hipDeviceSynchronize();
std::cout << "Hello, CUDA!" << std::endl;
return 0;
}
__global__ void emptyKernel(){
// Empty
} | .text
.file "empty-kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z26__device_stub__emptyKernelv # -- Begin function _Z26__device_stub__emptyKernelv
.p2align 4, 0x90
.type _Z26__device_stub__emptyKernelv,@function
_Z26__device_stub__emptyKernelv: # @_Z26__device_stub__emptyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z26__device_stub__emptyKernelv, .Lfunc_end1-_Z26__device_stub__emptyKernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11emptyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11emptyKernelv,@object # @_Z11emptyKernelv
.section .rodata,"a",@progbits
.globl _Z11emptyKernelv
.p2align 3, 0x0
_Z11emptyKernelv:
.quad _Z26__device_stub__emptyKernelv
.size _Z11emptyKernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello, CUDA!"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11emptyKernelv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__emptyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11emptyKernelv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11emptyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11emptyKernelv
.globl _Z11emptyKernelv
.p2align 8
.type _Z11emptyKernelv,@function
_Z11emptyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11emptyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11emptyKernelv, .Lfunc_end0-_Z11emptyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11emptyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11emptyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f3a79_00000000-6_empty-kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11emptyKernelvv
.type _Z30__device_stub__Z11emptyKernelvv, @function
_Z30__device_stub__Z11emptyKernelvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11emptyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z11emptyKernelvv, .-_Z30__device_stub__Z11emptyKernelvv
.globl _Z11emptyKernelv
.type _Z11emptyKernelv, @function
_Z11emptyKernelv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11emptyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11emptyKernelv, .-_Z11emptyKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, CUDA!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call cudaSetDevice@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11emptyKernelvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11emptyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11emptyKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "empty-kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z26__device_stub__emptyKernelv # -- Begin function _Z26__device_stub__emptyKernelv
.p2align 4, 0x90
.type _Z26__device_stub__emptyKernelv,@function
_Z26__device_stub__emptyKernelv: # @_Z26__device_stub__emptyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z26__device_stub__emptyKernelv, .Lfunc_end1-_Z26__device_stub__emptyKernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11emptyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11emptyKernelv,@object # @_Z11emptyKernelv
.section .rodata,"a",@progbits
.globl _Z11emptyKernelv
.p2align 3, 0x0
_Z11emptyKernelv:
.quad _Z26__device_stub__emptyKernelv
.size _Z11emptyKernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello, CUDA!"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11emptyKernelv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__emptyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11emptyKernelv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***********************************************************************
! Version 1: 04/16 SCR *
! *
! CUDA/C optimization of: *
! *
! SNSWP3D - This routine calculates angular fluxes for a single *
! direction for an upstream corner-balance spatial *
! discretization in 3D. *
! *
! Input: *
! *
! Output: *
! *
! Questions: *
! 1. Should the hyperplane pass over zones or corners? *
! A: Corners *
! 2. *
! *
!**********************************************************************/
/*
TODO:
explicit setting of #hyperplanes
*/
#include<stdio.h>
//#include<omp.h>
//#include"nvToolsExt.h"
#define GROUPSET 16
#define NUMFACES 3
#define NUMSM 90
#define fouralpha 1.82
#define fouralpha4 5.82
//#include "snutil.cu"
//#include "snsweep.cu"
#define Connect(a,b,c) Connect[ a + 3 * ( b + mC * c ) ]
extern "C" {
void callCudaHostMalloc ();
// void CC_sweep(
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib );
/*
Simple C file to handle calling CUDA. Easily accessible from Fortran.
This removes any need to compile any other part of the program with nvcc.
Just this file needs nvcc. Everything else just uses regular intel compilers.
Simple.
*/
void callcudasub (
int *numzones,
int *numgroups,
int *ncornr,
int *numAngles,
int *AngleOrder,
int *maxcorners,
int *maxfaces,
int *octant, //=binRecv
int *NangBin,
int *nbelem,
double *omega,
int *nCorner,
int *nCFaces,
int *c0,
double *A_fp,
double *A_ez,
int *Connect,
double *STotal,
double *STime,
double *Volume,
double *psic,
double *psib,
int *next,
int *nextZ,
double *Sigt,
double *SigtInv
)
{
//dump data to check
static int dump_cnt=0;
int zone,ic;
static int* d_AngleOrder;
static double* d_omega;
static int* d_nextZ;
static int* d_next;
static int* d_nCorner;
static int* d_nCFaces;
static int* d_c0;
static double* d_STotal;
static double* d_STime;
static double* d_SigtInv;
static double* d_Volume;
static double* d_Sigt;
static double* d_A_fp;
static double* d_A_ez;
static int* d_Connect;
static double* d_psic;
static double* d_psib;
int nZ = *numzones;
int nA = *numAngles;
int mC = *maxcorners;
int mF = *maxfaces;
int nG = *numgroups;
int nC = *ncornr;
int nBe = *nbelem;
if ( dump_cnt < 5 )
{
// for(zone=0;zone<nZ;zone++)
// {
// for(ic=0;ic<nCorner[zone]; ic++)
// {
// printf(" zone,corner,connect3 = %d,%d,%d \n",zone,ic,Connect(2,ic,zone) );
// }
// }
printf("max faces=%d\n",mF);
if ( dump_cnt == 0 )
{
cudaMalloc(&d_AngleOrder,sizeof(int)*8*nA);
cudaMalloc(&d_omega,sizeof(double)*3*nA);
cudaMalloc(&d_nextZ,sizeof(int)*nZ*nA);
cudaMalloc(&d_next,sizeof(int)*(nC+1)*nA);
cudaMalloc(&d_nCorner,sizeof(int)*nZ);
cudaMalloc(&d_nCFaces,sizeof(int)*nZ);
cudaMalloc(&d_c0,sizeof(int)*nZ);
cudaMalloc(&d_STotal,sizeof(double)*nZ*nG*mC);
cudaMalloc(&d_STime,sizeof(double)*nZ*nA*nG*mC);
cudaMalloc(&d_SigtInv,sizeof(double)*nZ*nG);
cudaMalloc(&d_Volume,sizeof(double)*nZ*mC);
cudaMalloc(&d_Sigt,sizeof(double)*nZ*nG);
cudaMalloc(&d_A_fp,sizeof(double)*3*nZ*mC*mF);
cudaMalloc(&d_A_ez,sizeof(double)*3*nZ*mC*mF);
cudaMalloc(&d_Connect,sizeof(int)*3*nZ*mC*mF);
cudaMalloc(&d_psic,sizeof(double)*nG*nC*nA);
cudaMalloc(&d_psib,sizeof(double)*nG*nBe*nA);
}
cudaMemcpy(d_AngleOrder,AngleOrder,sizeof(int)*8*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_omega,omega,sizeof(double)*3*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_nextZ,nextZ,sizeof(int)*nZ*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_next,next,sizeof(int)*(nC+1)*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_nCorner,nCorner,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_nCFaces,nCFaces,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_c0,c0,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_STotal,STotal,sizeof(double)*nZ*nG*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_STime,STime,sizeof(double)*nZ*nA*nG*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_SigtInv,SigtInv,sizeof(double)*nZ*nG,cudaMemcpyHostToDevice);
cudaMemcpy(d_Volume,Volume,sizeof(double)*nZ*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_Sigt,Sigt,sizeof(double)*nZ*nG,cudaMemcpyHostToDevice);
cudaMemcpy(d_A_fp,A_fp,sizeof(double)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_A_ez,A_ez,sizeof(double)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_Connect,Connect,sizeof(int)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_psib,psib,sizeof(double)*nG*nBe*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_psic,psic,sizeof(double)*nG*nC*nA,cudaMemcpyHostToDevice);
//
//
GPU_sweep<<<nA,32>>>(
mC,
mF, //
nA,
nZ,
nC,
nG,
nBe,
d_AngleOrder,
d_omega,
d_nextZ,
d_next,
d_nCorner,
d_nCFaces,
d_c0,
d_STotal,
d_STime,
d_SigtInv,
d_Volume,
d_Sigt,
d_A_fp,
d_A_ez,
d_Connect,
d_psic,
d_psib
);
cudaMemcpy(psic,d_psic,sizeof(double)*nG*nC*nA,cudaMemcpyDeviceToHost);
// CC_sweep(
// *maxcorners,
// mF, //*maxfaces,
// *numAngles,
// *numzones,
// nC,
// *numgroups,
// nBe,
// AngleOrder,
// omega,
// nextZ,
// next,
// nCorner,
// nCFaces,
// c0,
// STotal,
// STime,
// SigtInv,
// Volume,
// Sigt,
// A_fp,
// A_ez,
// Connect,
// psic,
// psib
// );
dump_cnt++;
}
} //callcuasub
} // extern C | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***********************************************************************
! Version 1: 04/16 SCR *
! *
! CUDA/C optimization of: *
! *
! SNSWP3D - This routine calculates angular fluxes for a single *
! direction for an upstream corner-balance spatial *
! discretization in 3D. *
! *
! Input: *
! *
! Output: *
! *
! Questions: *
! 1. Should the hyperplane pass over zones or corners? *
! A: Corners *
! 2. *
! *
!**********************************************************************/
/*
TODO:
explicit setting of #hyperplanes
*/
#include<stdio.h>
//#include<omp.h>
//#include"nvToolsExt.h"
#define GROUPSET 16
#define NUMFACES 3
#define NUMSM 90
#define fouralpha 1.82
#define fouralpha4 5.82
//#include "snutil.cu"
//#include "snsweep.cu"
#define Connect(a,b,c) Connect[ a + 3 * ( b + mC * c ) ]
extern "C" {
void callCudaHostMalloc ();
// void CC_sweep(
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib );
/*
Simple C file to handle calling CUDA. Easily accessible from Fortran.
This removes any need to compile any other part of the program with nvcc.
Just this file needs nvcc. Everything else just uses regular intel compilers.
Simple.
*/
void callcudasub (
int *numzones,
int *numgroups,
int *ncornr,
int *numAngles,
int *AngleOrder,
int *maxcorners,
int *maxfaces,
int *octant, //=binRecv
int *NangBin,
int *nbelem,
double *omega,
int *nCorner,
int *nCFaces,
int *c0,
double *A_fp,
double *A_ez,
int *Connect,
double *STotal,
double *STime,
double *Volume,
double *psic,
double *psib,
int *next,
int *nextZ,
double *Sigt,
double *SigtInv
)
{
//dump data to check
static int dump_cnt=0;
int zone,ic;
static int* d_AngleOrder;
static double* d_omega;
static int* d_nextZ;
static int* d_next;
static int* d_nCorner;
static int* d_nCFaces;
static int* d_c0;
static double* d_STotal;
static double* d_STime;
static double* d_SigtInv;
static double* d_Volume;
static double* d_Sigt;
static double* d_A_fp;
static double* d_A_ez;
static int* d_Connect;
static double* d_psic;
static double* d_psib;
int nZ = *numzones;
int nA = *numAngles;
int mC = *maxcorners;
int mF = *maxfaces;
int nG = *numgroups;
int nC = *ncornr;
int nBe = *nbelem;
if ( dump_cnt < 5 )
{
// for(zone=0;zone<nZ;zone++)
// {
// for(ic=0;ic<nCorner[zone]; ic++)
// {
// printf(" zone,corner,connect3 = %d,%d,%d \n",zone,ic,Connect(2,ic,zone) );
// }
// }
printf("max faces=%d\n",mF);
if ( dump_cnt == 0 )
{
cudaMalloc(&d_AngleOrder,sizeof(int)*8*nA);
cudaMalloc(&d_omega,sizeof(double)*3*nA);
cudaMalloc(&d_nextZ,sizeof(int)*nZ*nA);
cudaMalloc(&d_next,sizeof(int)*(nC+1)*nA);
cudaMalloc(&d_nCorner,sizeof(int)*nZ);
cudaMalloc(&d_nCFaces,sizeof(int)*nZ);
cudaMalloc(&d_c0,sizeof(int)*nZ);
cudaMalloc(&d_STotal,sizeof(double)*nZ*nG*mC);
cudaMalloc(&d_STime,sizeof(double)*nZ*nA*nG*mC);
cudaMalloc(&d_SigtInv,sizeof(double)*nZ*nG);
cudaMalloc(&d_Volume,sizeof(double)*nZ*mC);
cudaMalloc(&d_Sigt,sizeof(double)*nZ*nG);
cudaMalloc(&d_A_fp,sizeof(double)*3*nZ*mC*mF);
cudaMalloc(&d_A_ez,sizeof(double)*3*nZ*mC*mF);
cudaMalloc(&d_Connect,sizeof(int)*3*nZ*mC*mF);
cudaMalloc(&d_psic,sizeof(double)*nG*nC*nA);
cudaMalloc(&d_psib,sizeof(double)*nG*nBe*nA);
}
cudaMemcpy(d_AngleOrder,AngleOrder,sizeof(int)*8*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_omega,omega,sizeof(double)*3*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_nextZ,nextZ,sizeof(int)*nZ*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_next,next,sizeof(int)*(nC+1)*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_nCorner,nCorner,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_nCFaces,nCFaces,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_c0,c0,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_STotal,STotal,sizeof(double)*nZ*nG*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_STime,STime,sizeof(double)*nZ*nA*nG*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_SigtInv,SigtInv,sizeof(double)*nZ*nG,cudaMemcpyHostToDevice);
cudaMemcpy(d_Volume,Volume,sizeof(double)*nZ*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_Sigt,Sigt,sizeof(double)*nZ*nG,cudaMemcpyHostToDevice);
cudaMemcpy(d_A_fp,A_fp,sizeof(double)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_A_ez,A_ez,sizeof(double)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_Connect,Connect,sizeof(int)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_psib,psib,sizeof(double)*nG*nBe*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_psic,psic,sizeof(double)*nG*nC*nA,cudaMemcpyHostToDevice);
//
//
GPU_sweep<<<nA,32>>>(
mC,
mF, //
nA,
nZ,
nC,
nG,
nBe,
d_AngleOrder,
d_omega,
d_nextZ,
d_next,
d_nCorner,
d_nCFaces,
d_c0,
d_STotal,
d_STime,
d_SigtInv,
d_Volume,
d_Sigt,
d_A_fp,
d_A_ez,
d_Connect,
d_psic,
d_psib
);
cudaMemcpy(psic,d_psic,sizeof(double)*nG*nC*nA,cudaMemcpyDeviceToHost);
// CC_sweep(
// *maxcorners,
// mF, //*maxfaces,
// *numAngles,
// *numzones,
// nC,
// *numgroups,
// nBe,
// AngleOrder,
// omega,
// nextZ,
// next,
// nCorner,
// nCFaces,
// c0,
// STotal,
// STime,
// SigtInv,
// Volume,
// Sigt,
// A_fp,
// A_ez,
// Connect,
// psic,
// psib
// );
dump_cnt++;
}
} //callcuasub
} // extern C | .file "tmpxft_0000c164_00000000-6_callcudasub.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "max faces=%d\n"
.text
.globl callcudasub
.type callcudasub, @function
callcudasub:
.LFB2057:
.cfi_startproc
endbr64
cmpl $4, _ZZ11callcudasubE8dump_cnt(%rip)
jle .L11
ret
.L11:
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, %rax
movq %r8, %r15
movl (%rdi), %ebx
movl %ebx, 20(%rsp)
movl (%rcx), %ebx
movl %ebx, 16(%rsp)
movl (%r9), %ebx
movl %ebx, 24(%rsp)
movq 144(%rsp), %rdx
movl (%rdx), %edx
movl %edx, 28(%rsp)
movl (%rsi), %ebx
movl %ebx, 32(%rsp)
movl (%rax), %eax
movl %eax, 12(%rsp)
movq 168(%rsp), %rax
movl (%rax), %eax
movl %eax, 36(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, _ZZ11callcudasubE8dump_cnt(%rip)
je .L12
.L5:
movslq 16(%rsp), %rbx
movq %rbx, %rdx
salq $5, %rdx
movl $1, %ecx
movq %r15, %rsi
movq _ZZ11callcudasubE12d_AngleOrder(%rip), %rdi
call cudaMemcpy@PLT
leaq (%rbx,%rbx,2), %rdx
salq $3, %rdx
movl $1, %ecx
movq 176(%rsp), %rsi
movq _ZZ11callcudasubE7d_omega(%rip), %rdi
call cudaMemcpy@PLT
movslq 20(%rsp), %rbp
movq %rbx, %r15
imulq %rbp, %r15
leaq 0(,%r15,4), %rdx
movl $1, %ecx
movq 280(%rsp), %rsi
movq _ZZ11callcudasubE7d_nextZ(%rip), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %ecx
leal 1(%rcx), %edx
movslq %edx, %rdx
imulq %rbx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 272(%rsp), %rsi
movq _ZZ11callcudasubE6d_next(%rip), %rdi
call cudaMemcpy@PLT
leaq 0(,%rbp,4), %r12
movl $1, %ecx
movq %r12, %rdx
movq 184(%rsp), %rsi
movq _ZZ11callcudasubE9d_nCorner(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 192(%rsp), %rsi
movq _ZZ11callcudasubE9d_nCFaces(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 200(%rsp), %rsi
movq _ZZ11callcudasubE4d_c0(%rip), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %r13
movq %rbp, %r12
imulq %r13, %r12
movslq 24(%rsp), %r14
movq %r12, %rdx
imulq %r14, %rdx
salq $3, %rdx
movl $1, %ecx
movq 232(%rsp), %rsi
movq _ZZ11callcudasubE8d_STotal(%rip), %rdi
call cudaMemcpy@PLT
movq %r13, %rdx
imulq %r14, %rdx
imulq %r15, %rdx
salq $3, %rdx
movl $1, %ecx
movq 240(%rsp), %rsi
movq _ZZ11callcudasubE7d_STime(%rip), %rdi
call cudaMemcpy@PLT
salq $3, %r12
movl $1, %ecx
movq %r12, %rdx
movq 296(%rsp), %rsi
movq _ZZ11callcudasubE9d_SigtInv(%rip), %rdi
call cudaMemcpy@PLT
imulq %r14, %rbp
leaq 0(,%rbp,8), %rdx
movl $1, %ecx
movq 248(%rsp), %rsi
movq _ZZ11callcudasubE8d_Volume(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 288(%rsp), %rsi
movq _ZZ11callcudasubE6d_Sigt(%rip), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rax
imulq %rax, %rbp
leaq (%rbp,%rbp), %r12
leaq (%r12,%rbp), %r14
salq $3, %r14
movl $1, %ecx
movq %r14, %rdx
movq 208(%rsp), %rsi
movq _ZZ11callcudasubE6d_A_fp(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 216(%rsp), %rsi
movq _ZZ11callcudasubE6d_A_ez(%rip), %rdi
call cudaMemcpy@PLT
leaq (%r12,%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 224(%rsp), %rsi
movq _ZZ11callcudasubE9d_Connect(%rip), %rdi
call cudaMemcpy@PLT
movslq 36(%rsp), %rdx
imulq %r13, %rdx
imulq %rbx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 264(%rsp), %rsi
movq _ZZ11callcudasubE6d_psib(%rip), %rdi
call cudaMemcpy@PLT
movslq 12(%rsp), %rax
imulq %r13, %rax
imulq %rax, %rbx
salq $3, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq 256(%rsp), %rsi
movq _ZZ11callcudasubE6d_psic(%rip), %rdi
call cudaMemcpy@PLT
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl 16(%rsp), %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L13
.L6:
movl $2, %ecx
movq %rbx, %rdx
movq _ZZ11callcudasubE6d_psic(%rip), %rsi
movq 256(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, _ZZ11callcudasubE8dump_cnt(%rip)
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movslq 16(%rsp), %rbx
movq %rbx, %rsi
salq $5, %rsi
leaq _ZZ11callcudasubE12d_AngleOrder(%rip), %rdi
call cudaMalloc@PLT
leaq (%rbx,%rbx,2), %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE7d_omega(%rip), %rdi
call cudaMalloc@PLT
movslq 20(%rsp), %rbp
movq %rbx, %rax
imulq %rbp, %rax
movq %rax, 40(%rsp)
leaq 0(,%rax,4), %rsi
leaq _ZZ11callcudasubE7d_nextZ(%rip), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %ecx
leal 1(%rcx), %esi
movslq %esi, %rsi
imulq %rbx, %rsi
salq $2, %rsi
leaq _ZZ11callcudasubE6d_next(%rip), %rdi
call cudaMalloc@PLT
leaq 0(,%rbp,4), %r12
movq %r12, %rsi
leaq _ZZ11callcudasubE9d_nCorner(%rip), %rdi
call cudaMalloc@PLT
movq %r12, %rsi
leaq _ZZ11callcudasubE9d_nCFaces(%rip), %rdi
call cudaMalloc@PLT
movq %r12, %rsi
leaq _ZZ11callcudasubE4d_c0(%rip), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %r13
movq %rbp, %r12
imulq %r13, %r12
movslq 24(%rsp), %r14
movq %r12, %rsi
imulq %r14, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE8d_STotal(%rip), %rdi
call cudaMalloc@PLT
movq %r13, %rsi
imulq %r14, %rsi
movq 40(%rsp), %rax
imulq %rax, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE7d_STime(%rip), %rdi
call cudaMalloc@PLT
salq $3, %r12
movq %r12, %rsi
leaq _ZZ11callcudasubE9d_SigtInv(%rip), %rdi
call cudaMalloc@PLT
imulq %r14, %rbp
leaq 0(,%rbp,8), %rsi
leaq _ZZ11callcudasubE8d_Volume(%rip), %rdi
call cudaMalloc@PLT
movq %r12, %rsi
leaq _ZZ11callcudasubE6d_Sigt(%rip), %rdi
call cudaMalloc@PLT
movslq 28(%rsp), %rax
imulq %rax, %rbp
leaq (%rbp,%rbp), %r12
leaq (%r12,%rbp), %r14
salq $3, %r14
movq %r14, %rsi
leaq _ZZ11callcudasubE6d_A_fp(%rip), %rdi
call cudaMalloc@PLT
movq %r14, %rsi
leaq _ZZ11callcudasubE6d_A_ez(%rip), %rdi
call cudaMalloc@PLT
leaq (%r12,%rbp), %rsi
salq $2, %rsi
leaq _ZZ11callcudasubE9d_Connect(%rip), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
imulq %r13, %rsi
imulq %rbx, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE6d_psic(%rip), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
imulq %r13, %rsi
imulq %rbx, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE6d_psib(%rip), %rdi
call cudaMalloc@PLT
jmp .L5
.L13:
pushq _ZZ11callcudasubE6d_psib(%rip)
.cfi_def_cfa_offset 152
pushq _ZZ11callcudasubE6d_psic(%rip)
.cfi_def_cfa_offset 160
pushq _ZZ11callcudasubE9d_Connect(%rip)
.cfi_def_cfa_offset 168
pushq _ZZ11callcudasubE6d_A_ez(%rip)
.cfi_def_cfa_offset 176
pushq _ZZ11callcudasubE6d_A_fp(%rip)
.cfi_def_cfa_offset 184
pushq _ZZ11callcudasubE6d_Sigt(%rip)
.cfi_def_cfa_offset 192
pushq _ZZ11callcudasubE8d_Volume(%rip)
.cfi_def_cfa_offset 200
pushq _ZZ11callcudasubE9d_SigtInv(%rip)
.cfi_def_cfa_offset 208
pushq _ZZ11callcudasubE7d_STime(%rip)
.cfi_def_cfa_offset 216
pushq _ZZ11callcudasubE8d_STotal(%rip)
.cfi_def_cfa_offset 224
pushq _ZZ11callcudasubE4d_c0(%rip)
.cfi_def_cfa_offset 232
pushq _ZZ11callcudasubE9d_nCFaces(%rip)
.cfi_def_cfa_offset 240
pushq _ZZ11callcudasubE9d_nCorner(%rip)
.cfi_def_cfa_offset 248
pushq _ZZ11callcudasubE6d_next(%rip)
.cfi_def_cfa_offset 256
pushq _ZZ11callcudasubE7d_nextZ(%rip)
.cfi_def_cfa_offset 264
pushq _ZZ11callcudasubE7d_omega(%rip)
.cfi_def_cfa_offset 272
pushq _ZZ11callcudasubE12d_AngleOrder(%rip)
.cfi_def_cfa_offset 280
movl 172(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 288
movl 176(%rsp), %r9d
movl 156(%rsp), %r8d
movl 164(%rsp), %ecx
movl 160(%rsp), %edx
movl 172(%rsp), %esi
movl 168(%rsp), %edi
call GPU_sweep@PLT
addq $144, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.cfi_endproc
.LFE2057:
.size callcudasub, .-callcudasub
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ11callcudasubE6d_psib
.comm _ZZ11callcudasubE6d_psib,8,8
.local _ZZ11callcudasubE6d_psic
.comm _ZZ11callcudasubE6d_psic,8,8
.local _ZZ11callcudasubE9d_Connect
.comm _ZZ11callcudasubE9d_Connect,8,8
.local _ZZ11callcudasubE6d_A_ez
.comm _ZZ11callcudasubE6d_A_ez,8,8
.local _ZZ11callcudasubE6d_A_fp
.comm _ZZ11callcudasubE6d_A_fp,8,8
.local _ZZ11callcudasubE6d_Sigt
.comm _ZZ11callcudasubE6d_Sigt,8,8
.local _ZZ11callcudasubE8d_Volume
.comm _ZZ11callcudasubE8d_Volume,8,8
.local _ZZ11callcudasubE9d_SigtInv
.comm _ZZ11callcudasubE9d_SigtInv,8,8
.local _ZZ11callcudasubE7d_STime
.comm _ZZ11callcudasubE7d_STime,8,8
.local _ZZ11callcudasubE8d_STotal
.comm _ZZ11callcudasubE8d_STotal,8,8
.local _ZZ11callcudasubE4d_c0
.comm _ZZ11callcudasubE4d_c0,8,8
.local _ZZ11callcudasubE9d_nCFaces
.comm _ZZ11callcudasubE9d_nCFaces,8,8
.local _ZZ11callcudasubE9d_nCorner
.comm _ZZ11callcudasubE9d_nCorner,8,8
.local _ZZ11callcudasubE6d_next
.comm _ZZ11callcudasubE6d_next,8,8
.local _ZZ11callcudasubE7d_nextZ
.comm _ZZ11callcudasubE7d_nextZ,8,8
.local _ZZ11callcudasubE7d_omega
.comm _ZZ11callcudasubE7d_omega,8,8
.local _ZZ11callcudasubE12d_AngleOrder
.comm _ZZ11callcudasubE12d_AngleOrder,8,8
.local _ZZ11callcudasubE8dump_cnt
.comm _ZZ11callcudasubE8dump_cnt,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***********************************************************************
! Version 1: 04/16 SCR *
! *
! CUDA/C optimization of: *
! *
! SNSWP3D - This routine calculates angular fluxes for a single *
! direction for an upstream corner-balance spatial *
! discretization in 3D. *
! *
! Input: *
! *
! Output: *
! *
! Questions: *
! 1. Should the hyperplane pass over zones or corners? *
! A: Corners *
! 2. *
! *
!**********************************************************************/
/*
TODO:
explicit setting of #hyperplanes
*/
#include<stdio.h>
//#include<omp.h>
//#include"nvToolsExt.h"
#define GROUPSET 16
#define NUMFACES 3
#define NUMSM 90
#define fouralpha 1.82
#define fouralpha4 5.82
//#include "snutil.cu"
//#include "snsweep.cu"
#define Connect(a,b,c) Connect[ a + 3 * ( b + mC * c ) ]
extern "C" {
void callCudaHostMalloc ();
// void CC_sweep(
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib );
/*
Simple C file to handle calling CUDA. Easily accessible from Fortran.
This removes any need to compile any other part of the program with nvcc.
Just this file needs nvcc. Everything else just uses regular intel compilers.
Simple.
*/
void callcudasub (
int *numzones,
int *numgroups,
int *ncornr,
int *numAngles,
int *AngleOrder,
int *maxcorners,
int *maxfaces,
int *octant, //=binRecv
int *NangBin,
int *nbelem,
double *omega,
int *nCorner,
int *nCFaces,
int *c0,
double *A_fp,
double *A_ez,
int *Connect,
double *STotal,
double *STime,
double *Volume,
double *psic,
double *psib,
int *next,
int *nextZ,
double *Sigt,
double *SigtInv
)
{
//dump data to check
static int dump_cnt=0;
int zone,ic;
static int* d_AngleOrder;
static double* d_omega;
static int* d_nextZ;
static int* d_next;
static int* d_nCorner;
static int* d_nCFaces;
static int* d_c0;
static double* d_STotal;
static double* d_STime;
static double* d_SigtInv;
static double* d_Volume;
static double* d_Sigt;
static double* d_A_fp;
static double* d_A_ez;
static int* d_Connect;
static double* d_psic;
static double* d_psib;
int nZ = *numzones;
int nA = *numAngles;
int mC = *maxcorners;
int mF = *maxfaces;
int nG = *numgroups;
int nC = *ncornr;
int nBe = *nbelem;
if ( dump_cnt < 5 )
{
// for(zone=0;zone<nZ;zone++)
// {
// for(ic=0;ic<nCorner[zone]; ic++)
// {
// printf(" zone,corner,connect3 = %d,%d,%d \n",zone,ic,Connect(2,ic,zone) );
// }
// }
printf("max faces=%d\n",mF);
if ( dump_cnt == 0 )
{
cudaMalloc(&d_AngleOrder,sizeof(int)*8*nA);
cudaMalloc(&d_omega,sizeof(double)*3*nA);
cudaMalloc(&d_nextZ,sizeof(int)*nZ*nA);
cudaMalloc(&d_next,sizeof(int)*(nC+1)*nA);
cudaMalloc(&d_nCorner,sizeof(int)*nZ);
cudaMalloc(&d_nCFaces,sizeof(int)*nZ);
cudaMalloc(&d_c0,sizeof(int)*nZ);
cudaMalloc(&d_STotal,sizeof(double)*nZ*nG*mC);
cudaMalloc(&d_STime,sizeof(double)*nZ*nA*nG*mC);
cudaMalloc(&d_SigtInv,sizeof(double)*nZ*nG);
cudaMalloc(&d_Volume,sizeof(double)*nZ*mC);
cudaMalloc(&d_Sigt,sizeof(double)*nZ*nG);
cudaMalloc(&d_A_fp,sizeof(double)*3*nZ*mC*mF);
cudaMalloc(&d_A_ez,sizeof(double)*3*nZ*mC*mF);
cudaMalloc(&d_Connect,sizeof(int)*3*nZ*mC*mF);
cudaMalloc(&d_psic,sizeof(double)*nG*nC*nA);
cudaMalloc(&d_psib,sizeof(double)*nG*nBe*nA);
}
cudaMemcpy(d_AngleOrder,AngleOrder,sizeof(int)*8*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_omega,omega,sizeof(double)*3*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_nextZ,nextZ,sizeof(int)*nZ*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_next,next,sizeof(int)*(nC+1)*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_nCorner,nCorner,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_nCFaces,nCFaces,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_c0,c0,sizeof(int)*nZ,cudaMemcpyHostToDevice);
cudaMemcpy(d_STotal,STotal,sizeof(double)*nZ*nG*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_STime,STime,sizeof(double)*nZ*nA*nG*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_SigtInv,SigtInv,sizeof(double)*nZ*nG,cudaMemcpyHostToDevice);
cudaMemcpy(d_Volume,Volume,sizeof(double)*nZ*mC,cudaMemcpyHostToDevice);
cudaMemcpy(d_Sigt,Sigt,sizeof(double)*nZ*nG,cudaMemcpyHostToDevice);
cudaMemcpy(d_A_fp,A_fp,sizeof(double)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_A_ez,A_ez,sizeof(double)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_Connect,Connect,sizeof(int)*3*nZ*mC*mF,cudaMemcpyHostToDevice);
cudaMemcpy(d_psib,psib,sizeof(double)*nG*nBe*nA,cudaMemcpyHostToDevice);
cudaMemcpy(d_psic,psic,sizeof(double)*nG*nC*nA,cudaMemcpyHostToDevice);
//
//
GPU_sweep<<<nA,32>>>(
mC,
mF, //
nA,
nZ,
nC,
nG,
nBe,
d_AngleOrder,
d_omega,
d_nextZ,
d_next,
d_nCorner,
d_nCFaces,
d_c0,
d_STotal,
d_STime,
d_SigtInv,
d_Volume,
d_Sigt,
d_A_fp,
d_A_ez,
d_Connect,
d_psic,
d_psib
);
cudaMemcpy(psic,d_psic,sizeof(double)*nG*nC*nA,cudaMemcpyDeviceToHost);
// CC_sweep(
// *maxcorners,
// mF, //*maxfaces,
// *numAngles,
// *numzones,
// nC,
// *numgroups,
// nBe,
// AngleOrder,
// omega,
// nextZ,
// next,
// nCorner,
// nCFaces,
// c0,
// STotal,
// STime,
// SigtInv,
// Volume,
// Sigt,
// A_fp,
// A_ez,
// Connect,
// psic,
// psib
// );
dump_cnt++;
}
} //callcuasub
} // extern C | /***********************************************************************
! Version 1: 04/16 SCR *
! *
! CUDA/C optimization of: *
! *
! SNSWP3D - This routine calculates angular fluxes for a single *
! direction for an upstream corner-balance spatial *
! discretization in 3D. *
! *
! Input: *
! *
! Output: *
! *
! Questions: *
! 1. Should the hyperplane pass over zones or corners? *
! A: Corners *
! 2. *
! *
!**********************************************************************/
/*
TODO:
explicit setting of #hyperplanes
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
//#include<omp.h>
//#include"nvToolsExt.h"
#define GROUPSET 16
#define NUMFACES 3
#define NUMSM 90
#define fouralpha 1.82
#define fouralpha4 5.82
//#include "snutil.cu"
//#include "snsweep.cu"
#define Connect(a,b,c) Connect[ a + 3 * ( b + mC * c ) ]
extern "C" {
void callCudaHostMalloc ();
// void CC_sweep(
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib );
/*
Simple C file to handle calling CUDA. Easily accessible from Fortran.
This removes any need to compile any other part of the program with nvcc.
Just this file needs nvcc. Everything else just uses regular intel compilers.
Simple.
*/
void callcudasub (
int *numzones,
int *numgroups,
int *ncornr,
int *numAngles,
int *AngleOrder,
int *maxcorners,
int *maxfaces,
int *octant, //=binRecv
int *NangBin,
int *nbelem,
double *omega,
int *nCorner,
int *nCFaces,
int *c0,
double *A_fp,
double *A_ez,
int *Connect,
double *STotal,
double *STime,
double *Volume,
double *psic,
double *psib,
int *next,
int *nextZ,
double *Sigt,
double *SigtInv
)
{
//dump data to check
static int dump_cnt=0;
int zone,ic;
static int* d_AngleOrder;
static double* d_omega;
static int* d_nextZ;
static int* d_next;
static int* d_nCorner;
static int* d_nCFaces;
static int* d_c0;
static double* d_STotal;
static double* d_STime;
static double* d_SigtInv;
static double* d_Volume;
static double* d_Sigt;
static double* d_A_fp;
static double* d_A_ez;
static int* d_Connect;
static double* d_psic;
static double* d_psib;
int nZ = *numzones;
int nA = *numAngles;
int mC = *maxcorners;
int mF = *maxfaces;
int nG = *numgroups;
int nC = *ncornr;
int nBe = *nbelem;
if ( dump_cnt < 5 )
{
// for(zone=0;zone<nZ;zone++)
// {
// for(ic=0;ic<nCorner[zone]; ic++)
// {
// printf(" zone,corner,connect3 = %d,%d,%d \n",zone,ic,Connect(2,ic,zone) );
// }
// }
printf("max faces=%d\n",mF);
if ( dump_cnt == 0 )
{
hipMalloc(&d_AngleOrder,sizeof(int)*8*nA);
hipMalloc(&d_omega,sizeof(double)*3*nA);
hipMalloc(&d_nextZ,sizeof(int)*nZ*nA);
hipMalloc(&d_next,sizeof(int)*(nC+1)*nA);
hipMalloc(&d_nCorner,sizeof(int)*nZ);
hipMalloc(&d_nCFaces,sizeof(int)*nZ);
hipMalloc(&d_c0,sizeof(int)*nZ);
hipMalloc(&d_STotal,sizeof(double)*nZ*nG*mC);
hipMalloc(&d_STime,sizeof(double)*nZ*nA*nG*mC);
hipMalloc(&d_SigtInv,sizeof(double)*nZ*nG);
hipMalloc(&d_Volume,sizeof(double)*nZ*mC);
hipMalloc(&d_Sigt,sizeof(double)*nZ*nG);
hipMalloc(&d_A_fp,sizeof(double)*3*nZ*mC*mF);
hipMalloc(&d_A_ez,sizeof(double)*3*nZ*mC*mF);
hipMalloc(&d_Connect,sizeof(int)*3*nZ*mC*mF);
hipMalloc(&d_psic,sizeof(double)*nG*nC*nA);
hipMalloc(&d_psib,sizeof(double)*nG*nBe*nA);
}
hipMemcpy(d_AngleOrder,AngleOrder,sizeof(int)*8*nA,hipMemcpyHostToDevice);
hipMemcpy(d_omega,omega,sizeof(double)*3*nA,hipMemcpyHostToDevice);
hipMemcpy(d_nextZ,nextZ,sizeof(int)*nZ*nA,hipMemcpyHostToDevice);
hipMemcpy(d_next,next,sizeof(int)*(nC+1)*nA,hipMemcpyHostToDevice);
hipMemcpy(d_nCorner,nCorner,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_nCFaces,nCFaces,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_c0,c0,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_STotal,STotal,sizeof(double)*nZ*nG*mC,hipMemcpyHostToDevice);
hipMemcpy(d_STime,STime,sizeof(double)*nZ*nA*nG*mC,hipMemcpyHostToDevice);
hipMemcpy(d_SigtInv,SigtInv,sizeof(double)*nZ*nG,hipMemcpyHostToDevice);
hipMemcpy(d_Volume,Volume,sizeof(double)*nZ*mC,hipMemcpyHostToDevice);
hipMemcpy(d_Sigt,Sigt,sizeof(double)*nZ*nG,hipMemcpyHostToDevice);
hipMemcpy(d_A_fp,A_fp,sizeof(double)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_A_ez,A_ez,sizeof(double)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_Connect,Connect,sizeof(int)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_psib,psib,sizeof(double)*nG*nBe*nA,hipMemcpyHostToDevice);
hipMemcpy(d_psic,psic,sizeof(double)*nG*nC*nA,hipMemcpyHostToDevice);
//
//
GPU_sweep<<<nA,32>>>(
mC,
mF, //
nA,
nZ,
nC,
nG,
nBe,
d_AngleOrder,
d_omega,
d_nextZ,
d_next,
d_nCorner,
d_nCFaces,
d_c0,
d_STotal,
d_STime,
d_SigtInv,
d_Volume,
d_Sigt,
d_A_fp,
d_A_ez,
d_Connect,
d_psic,
d_psib
);
hipMemcpy(psic,d_psic,sizeof(double)*nG*nC*nA,hipMemcpyDeviceToHost);
// CC_sweep(
// *maxcorners,
// mF, //*maxfaces,
// *numAngles,
// *numzones,
// nC,
// *numgroups,
// nBe,
// AngleOrder,
// omega,
// nextZ,
// next,
// nCorner,
// nCFaces,
// c0,
// STotal,
// STime,
// SigtInv,
// Volume,
// Sigt,
// A_fp,
// A_ez,
// Connect,
// psic,
// psib
// );
dump_cnt++;
}
} //callcuasub
} // extern C |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***********************************************************************
! Version 1: 04/16 SCR *
! *
! CUDA/C optimization of: *
! *
! SNSWP3D - This routine calculates angular fluxes for a single *
! direction for an upstream corner-balance spatial *
! discretization in 3D. *
! *
! Input: *
! *
! Output: *
! *
! Questions: *
! 1. Should the hyperplane pass over zones or corners? *
! A: Corners *
! 2. *
! *
!**********************************************************************/
/*
TODO:
explicit setting of #hyperplanes
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
//#include<omp.h>
//#include"nvToolsExt.h"
#define GROUPSET 16
#define NUMFACES 3
#define NUMSM 90
#define fouralpha 1.82
#define fouralpha4 5.82
//#include "snutil.cu"
//#include "snsweep.cu"
#define Connect(a,b,c) Connect[ a + 3 * ( b + mC * c ) ]
extern "C" {
void callCudaHostMalloc ();
// void CC_sweep(
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib );
/*
Simple C file to handle calling CUDA. Easily accessible from Fortran.
This removes any need to compile any other part of the program with nvcc.
Just this file needs nvcc. Everything else just uses regular intel compilers.
Simple.
*/
void callcudasub (
int *numzones,
int *numgroups,
int *ncornr,
int *numAngles,
int *AngleOrder,
int *maxcorners,
int *maxfaces,
int *octant, //=binRecv
int *NangBin,
int *nbelem,
double *omega,
int *nCorner,
int *nCFaces,
int *c0,
double *A_fp,
double *A_ez,
int *Connect,
double *STotal,
double *STime,
double *Volume,
double *psic,
double *psib,
int *next,
int *nextZ,
double *Sigt,
double *SigtInv
)
{
//dump data to check
static int dump_cnt=0;
int zone,ic;
static int* d_AngleOrder;
static double* d_omega;
static int* d_nextZ;
static int* d_next;
static int* d_nCorner;
static int* d_nCFaces;
static int* d_c0;
static double* d_STotal;
static double* d_STime;
static double* d_SigtInv;
static double* d_Volume;
static double* d_Sigt;
static double* d_A_fp;
static double* d_A_ez;
static int* d_Connect;
static double* d_psic;
static double* d_psib;
int nZ = *numzones;
int nA = *numAngles;
int mC = *maxcorners;
int mF = *maxfaces;
int nG = *numgroups;
int nC = *ncornr;
int nBe = *nbelem;
if ( dump_cnt < 5 )
{
// for(zone=0;zone<nZ;zone++)
// {
// for(ic=0;ic<nCorner[zone]; ic++)
// {
// printf(" zone,corner,connect3 = %d,%d,%d \n",zone,ic,Connect(2,ic,zone) );
// }
// }
printf("max faces=%d\n",mF);
if ( dump_cnt == 0 )
{
hipMalloc(&d_AngleOrder,sizeof(int)*8*nA);
hipMalloc(&d_omega,sizeof(double)*3*nA);
hipMalloc(&d_nextZ,sizeof(int)*nZ*nA);
hipMalloc(&d_next,sizeof(int)*(nC+1)*nA);
hipMalloc(&d_nCorner,sizeof(int)*nZ);
hipMalloc(&d_nCFaces,sizeof(int)*nZ);
hipMalloc(&d_c0,sizeof(int)*nZ);
hipMalloc(&d_STotal,sizeof(double)*nZ*nG*mC);
hipMalloc(&d_STime,sizeof(double)*nZ*nA*nG*mC);
hipMalloc(&d_SigtInv,sizeof(double)*nZ*nG);
hipMalloc(&d_Volume,sizeof(double)*nZ*mC);
hipMalloc(&d_Sigt,sizeof(double)*nZ*nG);
hipMalloc(&d_A_fp,sizeof(double)*3*nZ*mC*mF);
hipMalloc(&d_A_ez,sizeof(double)*3*nZ*mC*mF);
hipMalloc(&d_Connect,sizeof(int)*3*nZ*mC*mF);
hipMalloc(&d_psic,sizeof(double)*nG*nC*nA);
hipMalloc(&d_psib,sizeof(double)*nG*nBe*nA);
}
hipMemcpy(d_AngleOrder,AngleOrder,sizeof(int)*8*nA,hipMemcpyHostToDevice);
hipMemcpy(d_omega,omega,sizeof(double)*3*nA,hipMemcpyHostToDevice);
hipMemcpy(d_nextZ,nextZ,sizeof(int)*nZ*nA,hipMemcpyHostToDevice);
hipMemcpy(d_next,next,sizeof(int)*(nC+1)*nA,hipMemcpyHostToDevice);
hipMemcpy(d_nCorner,nCorner,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_nCFaces,nCFaces,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_c0,c0,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_STotal,STotal,sizeof(double)*nZ*nG*mC,hipMemcpyHostToDevice);
hipMemcpy(d_STime,STime,sizeof(double)*nZ*nA*nG*mC,hipMemcpyHostToDevice);
hipMemcpy(d_SigtInv,SigtInv,sizeof(double)*nZ*nG,hipMemcpyHostToDevice);
hipMemcpy(d_Volume,Volume,sizeof(double)*nZ*mC,hipMemcpyHostToDevice);
hipMemcpy(d_Sigt,Sigt,sizeof(double)*nZ*nG,hipMemcpyHostToDevice);
hipMemcpy(d_A_fp,A_fp,sizeof(double)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_A_ez,A_ez,sizeof(double)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_Connect,Connect,sizeof(int)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_psib,psib,sizeof(double)*nG*nBe*nA,hipMemcpyHostToDevice);
hipMemcpy(d_psic,psic,sizeof(double)*nG*nC*nA,hipMemcpyHostToDevice);
//
//
GPU_sweep<<<nA,32>>>(
mC,
mF, //
nA,
nZ,
nC,
nG,
nBe,
d_AngleOrder,
d_omega,
d_nextZ,
d_next,
d_nCorner,
d_nCFaces,
d_c0,
d_STotal,
d_STime,
d_SigtInv,
d_Volume,
d_Sigt,
d_A_fp,
d_A_ez,
d_Connect,
d_psic,
d_psib
);
hipMemcpy(psic,d_psic,sizeof(double)*nG*nC*nA,hipMemcpyDeviceToHost);
// CC_sweep(
// *maxcorners,
// mF, //*maxfaces,
// *numAngles,
// *numzones,
// nC,
// *numgroups,
// nBe,
// AngleOrder,
// omega,
// nextZ,
// next,
// nCorner,
// nCFaces,
// c0,
// STotal,
// STime,
// SigtInv,
// Volume,
// Sigt,
// A_fp,
// A_ez,
// Connect,
// psic,
// psib
// );
dump_cnt++;
}
} //callcuasub
} // extern C | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***********************************************************************
! Version 1: 04/16 SCR *
! *
! CUDA/C optimization of: *
! *
! SNSWP3D - This routine calculates angular fluxes for a single *
! direction for an upstream corner-balance spatial *
! discretization in 3D. *
! *
! Input: *
! *
! Output: *
! *
! Questions: *
! 1. Should the hyperplane pass over zones or corners? *
! A: Corners *
! 2. *
! *
!**********************************************************************/
/*
TODO:
explicit setting of #hyperplanes
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
//#include<omp.h>
//#include"nvToolsExt.h"
#define GROUPSET 16
#define NUMFACES 3
#define NUMSM 90
#define fouralpha 1.82
#define fouralpha4 5.82
//#include "snutil.cu"
//#include "snsweep.cu"
#define Connect(a,b,c) Connect[ a + 3 * ( b + mC * c ) ]
extern "C" {
void callCudaHostMalloc ();
// void CC_sweep(
__global__ void GPU_sweep(
int size_maxCorner,
int size_maxcf,
int nAngle,
int nzones,
int ncornr,
int Groups,
int nbelem,
int* Angle,
double* soa_omega,
int* nextZ,
int* next,
int* soa_nCorner,
int* soa_nCFaces,
int* soa_c0,
double* soa_STotal,
double* soa_STime,
double* soa_SigtInv,
double* soa_Volume,
double* soa_Sigt,
double* soa_A_fp,
double* soa_A_ez,
int* soa_Connect,
double* psic,
double* psib );
/*
Simple C file to handle calling CUDA. Easily accessible from Fortran.
This removes any need to compile any other part of the program with nvcc.
Just this file needs nvcc. Everything else just uses regular intel compilers.
Simple.
*/
void callcudasub (
int *numzones,
int *numgroups,
int *ncornr,
int *numAngles,
int *AngleOrder,
int *maxcorners,
int *maxfaces,
int *octant, //=binRecv
int *NangBin,
int *nbelem,
double *omega,
int *nCorner,
int *nCFaces,
int *c0,
double *A_fp,
double *A_ez,
int *Connect,
double *STotal,
double *STime,
double *Volume,
double *psic,
double *psib,
int *next,
int *nextZ,
double *Sigt,
double *SigtInv
)
{
//dump data to check
static int dump_cnt=0;
int zone,ic;
static int* d_AngleOrder;
static double* d_omega;
static int* d_nextZ;
static int* d_next;
static int* d_nCorner;
static int* d_nCFaces;
static int* d_c0;
static double* d_STotal;
static double* d_STime;
static double* d_SigtInv;
static double* d_Volume;
static double* d_Sigt;
static double* d_A_fp;
static double* d_A_ez;
static int* d_Connect;
static double* d_psic;
static double* d_psib;
int nZ = *numzones;
int nA = *numAngles;
int mC = *maxcorners;
int mF = *maxfaces;
int nG = *numgroups;
int nC = *ncornr;
int nBe = *nbelem;
if ( dump_cnt < 5 )
{
// for(zone=0;zone<nZ;zone++)
// {
// for(ic=0;ic<nCorner[zone]; ic++)
// {
// printf(" zone,corner,connect3 = %d,%d,%d \n",zone,ic,Connect(2,ic,zone) );
// }
// }
printf("max faces=%d\n",mF);
if ( dump_cnt == 0 )
{
hipMalloc(&d_AngleOrder,sizeof(int)*8*nA);
hipMalloc(&d_omega,sizeof(double)*3*nA);
hipMalloc(&d_nextZ,sizeof(int)*nZ*nA);
hipMalloc(&d_next,sizeof(int)*(nC+1)*nA);
hipMalloc(&d_nCorner,sizeof(int)*nZ);
hipMalloc(&d_nCFaces,sizeof(int)*nZ);
hipMalloc(&d_c0,sizeof(int)*nZ);
hipMalloc(&d_STotal,sizeof(double)*nZ*nG*mC);
hipMalloc(&d_STime,sizeof(double)*nZ*nA*nG*mC);
hipMalloc(&d_SigtInv,sizeof(double)*nZ*nG);
hipMalloc(&d_Volume,sizeof(double)*nZ*mC);
hipMalloc(&d_Sigt,sizeof(double)*nZ*nG);
hipMalloc(&d_A_fp,sizeof(double)*3*nZ*mC*mF);
hipMalloc(&d_A_ez,sizeof(double)*3*nZ*mC*mF);
hipMalloc(&d_Connect,sizeof(int)*3*nZ*mC*mF);
hipMalloc(&d_psic,sizeof(double)*nG*nC*nA);
hipMalloc(&d_psib,sizeof(double)*nG*nBe*nA);
}
hipMemcpy(d_AngleOrder,AngleOrder,sizeof(int)*8*nA,hipMemcpyHostToDevice);
hipMemcpy(d_omega,omega,sizeof(double)*3*nA,hipMemcpyHostToDevice);
hipMemcpy(d_nextZ,nextZ,sizeof(int)*nZ*nA,hipMemcpyHostToDevice);
hipMemcpy(d_next,next,sizeof(int)*(nC+1)*nA,hipMemcpyHostToDevice);
hipMemcpy(d_nCorner,nCorner,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_nCFaces,nCFaces,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_c0,c0,sizeof(int)*nZ,hipMemcpyHostToDevice);
hipMemcpy(d_STotal,STotal,sizeof(double)*nZ*nG*mC,hipMemcpyHostToDevice);
hipMemcpy(d_STime,STime,sizeof(double)*nZ*nA*nG*mC,hipMemcpyHostToDevice);
hipMemcpy(d_SigtInv,SigtInv,sizeof(double)*nZ*nG,hipMemcpyHostToDevice);
hipMemcpy(d_Volume,Volume,sizeof(double)*nZ*mC,hipMemcpyHostToDevice);
hipMemcpy(d_Sigt,Sigt,sizeof(double)*nZ*nG,hipMemcpyHostToDevice);
hipMemcpy(d_A_fp,A_fp,sizeof(double)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_A_ez,A_ez,sizeof(double)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_Connect,Connect,sizeof(int)*3*nZ*mC*mF,hipMemcpyHostToDevice);
hipMemcpy(d_psib,psib,sizeof(double)*nG*nBe*nA,hipMemcpyHostToDevice);
hipMemcpy(d_psic,psic,sizeof(double)*nG*nC*nA,hipMemcpyHostToDevice);
//
//
GPU_sweep<<<nA,32>>>(
mC,
mF, //
nA,
nZ,
nC,
nG,
nBe,
d_AngleOrder,
d_omega,
d_nextZ,
d_next,
d_nCorner,
d_nCFaces,
d_c0,
d_STotal,
d_STime,
d_SigtInv,
d_Volume,
d_Sigt,
d_A_fp,
d_A_ez,
d_Connect,
d_psic,
d_psib
);
hipMemcpy(psic,d_psic,sizeof(double)*nG*nC*nA,hipMemcpyDeviceToHost);
// CC_sweep(
// *maxcorners,
// mF, //*maxfaces,
// *numAngles,
// *numzones,
// nC,
// *numgroups,
// nBe,
// AngleOrder,
// omega,
// nextZ,
// next,
// nCorner,
// nCFaces,
// c0,
// STotal,
// STime,
// SigtInv,
// Volume,
// Sigt,
// A_fp,
// A_ez,
// Connect,
// psic,
// psib
// );
dump_cnt++;
}
} //callcuasub
} // extern C | .text
.file "callcudasub.hip"
.globl callcudasub # -- Begin function callcudasub
.p2align 4, 0x90
.type callcudasub,@function
callcudasub: # @callcudasub
.cfi_startproc
# %bb.0:
cmpl $4, _ZZ11callcudasubE8dump_cnt(%rip)
jg .LBB0_6
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movq 264(%rsp), %r12
movq 256(%rsp), %rbx
movq 152(%rsp), %rax
movq 128(%rsp), %r8
movslq (%rdi), %rdi
movq %rdi, 16(%rsp) # 8-byte Spill
movslq (%rcx), %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
movslq (%r9), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movslq (%r8), %r8
movslq (%rsi), %rcx
movq %rcx, 48(%rsp) # 8-byte Spill
movslq (%rdx), %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movslq (%rax), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq 216(%rsp), %rbp
movl $.L.str, %edi
movq %r8, 24(%rsp) # 8-byte Spill
movl %r8d, %esi
xorl %eax, %eax
callq printf
cmpl $0, _ZZ11callcudasubE8dump_cnt(%rip)
jne .LBB0_3
# %bb.2:
movq %r15, 64(%rsp) # 8-byte Spill
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
shlq $5, %rsi
movl $_ZZ11callcudasubE12d_AngleOrder, %edi
callq hipMalloc
leaq (,%r15,8), %rax
leaq (%rax,%rax,2), %rsi
movl $_ZZ11callcudasubE7d_omega, %edi
callq hipMalloc
movq 16(%rsp), %r13 # 8-byte Reload
leaq (,%r13,4), %rbx
movq %rbx, %rsi
imulq %r15, %rsi
movl $_ZZ11callcudasubE7d_nextZ, %edi
callq hipMalloc
movq 8(%rsp), %rax # 8-byte Reload
leaq 1(%rax), %rsi
imulq %r15, %rsi
shlq $2, %rsi
movl $_ZZ11callcudasubE6d_next, %edi
callq hipMalloc
movl $_ZZ11callcudasubE9d_nCorner, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE9d_nCFaces, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE4d_c0, %edi
movq %rbx, %rsi
callq hipMalloc
leaq (,%r13,8), %rbx
movq %rbx, %rbp
movq 48(%rsp), %r14 # 8-byte Reload
imulq %r14, %rbp
movq %rbp, %rsi
movq 40(%rsp), %r12 # 8-byte Reload
imulq %r12, %rsi
movl $_ZZ11callcudasubE8d_STotal, %edi
callq hipMalloc
imulq %r12, %rbx
imulq %r14, %r15
movq %rbx, %rsi
imulq %r15, %rsi
movl $_ZZ11callcudasubE7d_STime, %edi
callq hipMalloc
movl $_ZZ11callcudasubE9d_SigtInv, %edi
movq %rbp, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE8d_Volume, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE6d_Sigt, %edi
movq %rbp, %rsi
callq hipMalloc
movq %r12, %rbp
movq 264(%rsp), %r12
imulq %r13, %rbp
imulq 24(%rsp), %rbp # 8-byte Folded Reload
leaq (,%rbp,8), %rax
leaq (%rax,%rax,2), %rbx
movl $_ZZ11callcudasubE6d_A_fp, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE6d_A_ez, %edi
movq %rbx, %rsi
movq 256(%rsp), %rbx
callq hipMalloc
shlq $2, %rbp
leaq (,%rbp,2), %rsi
addq %rbp, %rsi
movq 216(%rsp), %rbp
movl $_ZZ11callcudasubE9d_Connect, %edi
callq hipMalloc
shlq $3, %r15
movq %r15, %rsi
imulq 8(%rsp), %rsi # 8-byte Folded Reload
movl $_ZZ11callcudasubE6d_psic, %edi
callq hipMalloc
imulq 56(%rsp), %r15 # 8-byte Folded Reload
movl $_ZZ11callcudasubE6d_psib, %edi
movq %r15, %rsi
movq 64(%rsp), %r15 # 8-byte Reload
callq hipMalloc
.LBB0_3:
movq _ZZ11callcudasubE12d_AngleOrder(%rip), %rdi
movq 32(%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
shlq $5, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE7d_omega(%rip), %rdi
leaq (,%r13,8), %rax
leaq (%rax,%rax,2), %rdx
movq 160(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE7d_nextZ(%rip), %rdi
movq 16(%rsp), %r14 # 8-byte Reload
leaq (,%r14,4), %r15
movq %r15, %rdx
imulq %r13, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_next(%rip), %rdi
movq 8(%rsp), %rax # 8-byte Reload
leaq 1(%rax), %rdx
imulq %r13, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_nCorner(%rip), %rdi
movq 168(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_nCFaces(%rip), %rdi
movq 176(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE4d_c0(%rip), %rdi
movq 184(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE8d_STotal(%rip), %rdi
leaq (,%r14,8), %r15
movq %r15, %rbx
movq 48(%rsp), %r14 # 8-byte Reload
imulq %r14, %rbx
movq %rbx, %rdx
movq 40(%rsp), %r12 # 8-byte Reload
imulq %r12, %rdx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE7d_STime(%rip), %rdi
imulq %r12, %r15
movq %r13, %rbp
imulq %r14, %rbp
movq %r15, %rdx
imulq %rbp, %rdx
movq 224(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_SigtInv(%rip), %rdi
movq 280(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE8d_Volume(%rip), %rdi
movq 232(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_Sigt(%rip), %rdi
movq 272(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_A_fp(%rip), %rdi
imulq 16(%rsp), %r12 # 8-byte Folded Reload
imulq 24(%rsp), %r12 # 8-byte Folded Reload
leaq (,%r12,8), %rax
leaq (%rax,%rax,2), %rbx
movq 192(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_A_ez(%rip), %rdi
movq 200(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_Connect(%rip), %rdi
shlq $2, %r12
leaq (%r12,%r12,2), %rdx
movq 208(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_psib(%rip), %rdi
shlq $3, %rbp
movq %rbp, %rdx
imulq 56(%rsp), %rdx # 8-byte Folded Reload
movq 248(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_psic(%rip), %rdi
imulq 8(%rsp), %rbp # 8-byte Folded Reload
movq 240(%rsp), %rbx
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4:
movq 40(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movq 24(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq 32(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movq 16(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq 8(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
movq 48(%rsp), %r9 # 8-byte Reload
# kill: def $r9d killed $r9d killed $r9
pushq _ZZ11callcudasubE6d_psib(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_psic(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_Connect(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_A_ez(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_A_fp(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_Sigt(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE8d_Volume(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_SigtInv(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE7d_STime(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE8d_STotal(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE4d_c0(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_nCFaces(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_nCorner(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_next(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE7d_nextZ(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE7d_omega(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE12d_AngleOrder(%rip)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
callq __device_stub__GPU_sweep
addq $144, %rsp
.cfi_adjust_cfa_offset -144
.LBB0_5:
movq _ZZ11callcudasubE6d_psic(%rip), %rsi
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
incl _ZZ11callcudasubE8dump_cnt(%rip)
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_6:
retq
.Lfunc_end0:
.size callcudasub, .Lfunc_end0-callcudasub
.cfi_endproc
# -- End function
.type _ZZ11callcudasubE8dump_cnt,@object # @_ZZ11callcudasubE8dump_cnt
.local _ZZ11callcudasubE8dump_cnt
.comm _ZZ11callcudasubE8dump_cnt,4,4
.type _ZZ11callcudasubE12d_AngleOrder,@object # @_ZZ11callcudasubE12d_AngleOrder
.local _ZZ11callcudasubE12d_AngleOrder
.comm _ZZ11callcudasubE12d_AngleOrder,8,8
.type _ZZ11callcudasubE7d_omega,@object # @_ZZ11callcudasubE7d_omega
.local _ZZ11callcudasubE7d_omega
.comm _ZZ11callcudasubE7d_omega,8,8
.type _ZZ11callcudasubE7d_nextZ,@object # @_ZZ11callcudasubE7d_nextZ
.local _ZZ11callcudasubE7d_nextZ
.comm _ZZ11callcudasubE7d_nextZ,8,8
.type _ZZ11callcudasubE6d_next,@object # @_ZZ11callcudasubE6d_next
.local _ZZ11callcudasubE6d_next
.comm _ZZ11callcudasubE6d_next,8,8
.type _ZZ11callcudasubE9d_nCorner,@object # @_ZZ11callcudasubE9d_nCorner
.local _ZZ11callcudasubE9d_nCorner
.comm _ZZ11callcudasubE9d_nCorner,8,8
.type _ZZ11callcudasubE9d_nCFaces,@object # @_ZZ11callcudasubE9d_nCFaces
.local _ZZ11callcudasubE9d_nCFaces
.comm _ZZ11callcudasubE9d_nCFaces,8,8
.type _ZZ11callcudasubE4d_c0,@object # @_ZZ11callcudasubE4d_c0
.local _ZZ11callcudasubE4d_c0
.comm _ZZ11callcudasubE4d_c0,8,8
.type _ZZ11callcudasubE8d_STotal,@object # @_ZZ11callcudasubE8d_STotal
.local _ZZ11callcudasubE8d_STotal
.comm _ZZ11callcudasubE8d_STotal,8,8
.type _ZZ11callcudasubE7d_STime,@object # @_ZZ11callcudasubE7d_STime
.local _ZZ11callcudasubE7d_STime
.comm _ZZ11callcudasubE7d_STime,8,8
.type _ZZ11callcudasubE9d_SigtInv,@object # @_ZZ11callcudasubE9d_SigtInv
.local _ZZ11callcudasubE9d_SigtInv
.comm _ZZ11callcudasubE9d_SigtInv,8,8
.type _ZZ11callcudasubE8d_Volume,@object # @_ZZ11callcudasubE8d_Volume
.local _ZZ11callcudasubE8d_Volume
.comm _ZZ11callcudasubE8d_Volume,8,8
.type _ZZ11callcudasubE6d_Sigt,@object # @_ZZ11callcudasubE6d_Sigt
.local _ZZ11callcudasubE6d_Sigt
.comm _ZZ11callcudasubE6d_Sigt,8,8
.type _ZZ11callcudasubE6d_A_fp,@object # @_ZZ11callcudasubE6d_A_fp
.local _ZZ11callcudasubE6d_A_fp
.comm _ZZ11callcudasubE6d_A_fp,8,8
.type _ZZ11callcudasubE6d_A_ez,@object # @_ZZ11callcudasubE6d_A_ez
.local _ZZ11callcudasubE6d_A_ez
.comm _ZZ11callcudasubE6d_A_ez,8,8
.type _ZZ11callcudasubE9d_Connect,@object # @_ZZ11callcudasubE9d_Connect
.local _ZZ11callcudasubE9d_Connect
.comm _ZZ11callcudasubE9d_Connect,8,8
.type _ZZ11callcudasubE6d_psic,@object # @_ZZ11callcudasubE6d_psic
.local _ZZ11callcudasubE6d_psic
.comm _ZZ11callcudasubE6d_psic,8,8
.type _ZZ11callcudasubE6d_psib,@object # @_ZZ11callcudasubE6d_psib
.local _ZZ11callcudasubE6d_psib
.comm _ZZ11callcudasubE6d_psib,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max faces=%d\n"
.size .L.str, 14
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZZ11callcudasubE12d_AngleOrder
.addrsig_sym _ZZ11callcudasubE7d_omega
.addrsig_sym _ZZ11callcudasubE7d_nextZ
.addrsig_sym _ZZ11callcudasubE6d_next
.addrsig_sym _ZZ11callcudasubE9d_nCorner
.addrsig_sym _ZZ11callcudasubE9d_nCFaces
.addrsig_sym _ZZ11callcudasubE4d_c0
.addrsig_sym _ZZ11callcudasubE8d_STotal
.addrsig_sym _ZZ11callcudasubE7d_STime
.addrsig_sym _ZZ11callcudasubE9d_SigtInv
.addrsig_sym _ZZ11callcudasubE8d_Volume
.addrsig_sym _ZZ11callcudasubE6d_Sigt
.addrsig_sym _ZZ11callcudasubE6d_A_fp
.addrsig_sym _ZZ11callcudasubE6d_A_ez
.addrsig_sym _ZZ11callcudasubE9d_Connect
.addrsig_sym _ZZ11callcudasubE6d_psic
.addrsig_sym _ZZ11callcudasubE6d_psib
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000c164_00000000-6_callcudasub.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "max faces=%d\n"
.text
.globl callcudasub
.type callcudasub, @function
callcudasub:
.LFB2057:
.cfi_startproc
endbr64
cmpl $4, _ZZ11callcudasubE8dump_cnt(%rip)
jle .L11
ret
.L11:
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, %rax
movq %r8, %r15
movl (%rdi), %ebx
movl %ebx, 20(%rsp)
movl (%rcx), %ebx
movl %ebx, 16(%rsp)
movl (%r9), %ebx
movl %ebx, 24(%rsp)
movq 144(%rsp), %rdx
movl (%rdx), %edx
movl %edx, 28(%rsp)
movl (%rsi), %ebx
movl %ebx, 32(%rsp)
movl (%rax), %eax
movl %eax, 12(%rsp)
movq 168(%rsp), %rax
movl (%rax), %eax
movl %eax, 36(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, _ZZ11callcudasubE8dump_cnt(%rip)
je .L12
.L5:
movslq 16(%rsp), %rbx
movq %rbx, %rdx
salq $5, %rdx
movl $1, %ecx
movq %r15, %rsi
movq _ZZ11callcudasubE12d_AngleOrder(%rip), %rdi
call cudaMemcpy@PLT
leaq (%rbx,%rbx,2), %rdx
salq $3, %rdx
movl $1, %ecx
movq 176(%rsp), %rsi
movq _ZZ11callcudasubE7d_omega(%rip), %rdi
call cudaMemcpy@PLT
movslq 20(%rsp), %rbp
movq %rbx, %r15
imulq %rbp, %r15
leaq 0(,%r15,4), %rdx
movl $1, %ecx
movq 280(%rsp), %rsi
movq _ZZ11callcudasubE7d_nextZ(%rip), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %ecx
leal 1(%rcx), %edx
movslq %edx, %rdx
imulq %rbx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 272(%rsp), %rsi
movq _ZZ11callcudasubE6d_next(%rip), %rdi
call cudaMemcpy@PLT
leaq 0(,%rbp,4), %r12
movl $1, %ecx
movq %r12, %rdx
movq 184(%rsp), %rsi
movq _ZZ11callcudasubE9d_nCorner(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 192(%rsp), %rsi
movq _ZZ11callcudasubE9d_nCFaces(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 200(%rsp), %rsi
movq _ZZ11callcudasubE4d_c0(%rip), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %r13
movq %rbp, %r12
imulq %r13, %r12
movslq 24(%rsp), %r14
movq %r12, %rdx
imulq %r14, %rdx
salq $3, %rdx
movl $1, %ecx
movq 232(%rsp), %rsi
movq _ZZ11callcudasubE8d_STotal(%rip), %rdi
call cudaMemcpy@PLT
movq %r13, %rdx
imulq %r14, %rdx
imulq %r15, %rdx
salq $3, %rdx
movl $1, %ecx
movq 240(%rsp), %rsi
movq _ZZ11callcudasubE7d_STime(%rip), %rdi
call cudaMemcpy@PLT
salq $3, %r12
movl $1, %ecx
movq %r12, %rdx
movq 296(%rsp), %rsi
movq _ZZ11callcudasubE9d_SigtInv(%rip), %rdi
call cudaMemcpy@PLT
imulq %r14, %rbp
leaq 0(,%rbp,8), %rdx
movl $1, %ecx
movq 248(%rsp), %rsi
movq _ZZ11callcudasubE8d_Volume(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 288(%rsp), %rsi
movq _ZZ11callcudasubE6d_Sigt(%rip), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rax
imulq %rax, %rbp
leaq (%rbp,%rbp), %r12
leaq (%r12,%rbp), %r14
salq $3, %r14
movl $1, %ecx
movq %r14, %rdx
movq 208(%rsp), %rsi
movq _ZZ11callcudasubE6d_A_fp(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 216(%rsp), %rsi
movq _ZZ11callcudasubE6d_A_ez(%rip), %rdi
call cudaMemcpy@PLT
leaq (%r12,%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 224(%rsp), %rsi
movq _ZZ11callcudasubE9d_Connect(%rip), %rdi
call cudaMemcpy@PLT
movslq 36(%rsp), %rdx
imulq %r13, %rdx
imulq %rbx, %rdx
salq $3, %rdx
movl $1, %ecx
movq 264(%rsp), %rsi
movq _ZZ11callcudasubE6d_psib(%rip), %rdi
call cudaMemcpy@PLT
movslq 12(%rsp), %rax
imulq %r13, %rax
imulq %rax, %rbx
salq $3, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq 256(%rsp), %rsi
movq _ZZ11callcudasubE6d_psic(%rip), %rdi
call cudaMemcpy@PLT
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl 16(%rsp), %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L13
.L6:
movl $2, %ecx
movq %rbx, %rdx
movq _ZZ11callcudasubE6d_psic(%rip), %rsi
movq 256(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, _ZZ11callcudasubE8dump_cnt(%rip)
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movslq 16(%rsp), %rbx
movq %rbx, %rsi
salq $5, %rsi
leaq _ZZ11callcudasubE12d_AngleOrder(%rip), %rdi
call cudaMalloc@PLT
leaq (%rbx,%rbx,2), %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE7d_omega(%rip), %rdi
call cudaMalloc@PLT
movslq 20(%rsp), %rbp
movq %rbx, %rax
imulq %rbp, %rax
movq %rax, 40(%rsp)
leaq 0(,%rax,4), %rsi
leaq _ZZ11callcudasubE7d_nextZ(%rip), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %ecx
leal 1(%rcx), %esi
movslq %esi, %rsi
imulq %rbx, %rsi
salq $2, %rsi
leaq _ZZ11callcudasubE6d_next(%rip), %rdi
call cudaMalloc@PLT
leaq 0(,%rbp,4), %r12
movq %r12, %rsi
leaq _ZZ11callcudasubE9d_nCorner(%rip), %rdi
call cudaMalloc@PLT
movq %r12, %rsi
leaq _ZZ11callcudasubE9d_nCFaces(%rip), %rdi
call cudaMalloc@PLT
movq %r12, %rsi
leaq _ZZ11callcudasubE4d_c0(%rip), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %r13
movq %rbp, %r12
imulq %r13, %r12
movslq 24(%rsp), %r14
movq %r12, %rsi
imulq %r14, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE8d_STotal(%rip), %rdi
call cudaMalloc@PLT
movq %r13, %rsi
imulq %r14, %rsi
movq 40(%rsp), %rax
imulq %rax, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE7d_STime(%rip), %rdi
call cudaMalloc@PLT
salq $3, %r12
movq %r12, %rsi
leaq _ZZ11callcudasubE9d_SigtInv(%rip), %rdi
call cudaMalloc@PLT
imulq %r14, %rbp
leaq 0(,%rbp,8), %rsi
leaq _ZZ11callcudasubE8d_Volume(%rip), %rdi
call cudaMalloc@PLT
movq %r12, %rsi
leaq _ZZ11callcudasubE6d_Sigt(%rip), %rdi
call cudaMalloc@PLT
movslq 28(%rsp), %rax
imulq %rax, %rbp
leaq (%rbp,%rbp), %r12
leaq (%r12,%rbp), %r14
salq $3, %r14
movq %r14, %rsi
leaq _ZZ11callcudasubE6d_A_fp(%rip), %rdi
call cudaMalloc@PLT
movq %r14, %rsi
leaq _ZZ11callcudasubE6d_A_ez(%rip), %rdi
call cudaMalloc@PLT
leaq (%r12,%rbp), %rsi
salq $2, %rsi
leaq _ZZ11callcudasubE9d_Connect(%rip), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
imulq %r13, %rsi
imulq %rbx, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE6d_psic(%rip), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
imulq %r13, %rsi
imulq %rbx, %rsi
salq $3, %rsi
leaq _ZZ11callcudasubE6d_psib(%rip), %rdi
call cudaMalloc@PLT
jmp .L5
.L13:
pushq _ZZ11callcudasubE6d_psib(%rip)
.cfi_def_cfa_offset 152
pushq _ZZ11callcudasubE6d_psic(%rip)
.cfi_def_cfa_offset 160
pushq _ZZ11callcudasubE9d_Connect(%rip)
.cfi_def_cfa_offset 168
pushq _ZZ11callcudasubE6d_A_ez(%rip)
.cfi_def_cfa_offset 176
pushq _ZZ11callcudasubE6d_A_fp(%rip)
.cfi_def_cfa_offset 184
pushq _ZZ11callcudasubE6d_Sigt(%rip)
.cfi_def_cfa_offset 192
pushq _ZZ11callcudasubE8d_Volume(%rip)
.cfi_def_cfa_offset 200
pushq _ZZ11callcudasubE9d_SigtInv(%rip)
.cfi_def_cfa_offset 208
pushq _ZZ11callcudasubE7d_STime(%rip)
.cfi_def_cfa_offset 216
pushq _ZZ11callcudasubE8d_STotal(%rip)
.cfi_def_cfa_offset 224
pushq _ZZ11callcudasubE4d_c0(%rip)
.cfi_def_cfa_offset 232
pushq _ZZ11callcudasubE9d_nCFaces(%rip)
.cfi_def_cfa_offset 240
pushq _ZZ11callcudasubE9d_nCorner(%rip)
.cfi_def_cfa_offset 248
pushq _ZZ11callcudasubE6d_next(%rip)
.cfi_def_cfa_offset 256
pushq _ZZ11callcudasubE7d_nextZ(%rip)
.cfi_def_cfa_offset 264
pushq _ZZ11callcudasubE7d_omega(%rip)
.cfi_def_cfa_offset 272
pushq _ZZ11callcudasubE12d_AngleOrder(%rip)
.cfi_def_cfa_offset 280
movl 172(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 288
movl 176(%rsp), %r9d
movl 156(%rsp), %r8d
movl 164(%rsp), %ecx
movl 160(%rsp), %edx
movl 172(%rsp), %esi
movl 168(%rsp), %edi
call GPU_sweep@PLT
addq $144, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.cfi_endproc
.LFE2057:
.size callcudasub, .-callcudasub
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ11callcudasubE6d_psib
.comm _ZZ11callcudasubE6d_psib,8,8
.local _ZZ11callcudasubE6d_psic
.comm _ZZ11callcudasubE6d_psic,8,8
.local _ZZ11callcudasubE9d_Connect
.comm _ZZ11callcudasubE9d_Connect,8,8
.local _ZZ11callcudasubE6d_A_ez
.comm _ZZ11callcudasubE6d_A_ez,8,8
.local _ZZ11callcudasubE6d_A_fp
.comm _ZZ11callcudasubE6d_A_fp,8,8
.local _ZZ11callcudasubE6d_Sigt
.comm _ZZ11callcudasubE6d_Sigt,8,8
.local _ZZ11callcudasubE8d_Volume
.comm _ZZ11callcudasubE8d_Volume,8,8
.local _ZZ11callcudasubE9d_SigtInv
.comm _ZZ11callcudasubE9d_SigtInv,8,8
.local _ZZ11callcudasubE7d_STime
.comm _ZZ11callcudasubE7d_STime,8,8
.local _ZZ11callcudasubE8d_STotal
.comm _ZZ11callcudasubE8d_STotal,8,8
.local _ZZ11callcudasubE4d_c0
.comm _ZZ11callcudasubE4d_c0,8,8
.local _ZZ11callcudasubE9d_nCFaces
.comm _ZZ11callcudasubE9d_nCFaces,8,8
.local _ZZ11callcudasubE9d_nCorner
.comm _ZZ11callcudasubE9d_nCorner,8,8
.local _ZZ11callcudasubE6d_next
.comm _ZZ11callcudasubE6d_next,8,8
.local _ZZ11callcudasubE7d_nextZ
.comm _ZZ11callcudasubE7d_nextZ,8,8
.local _ZZ11callcudasubE7d_omega
.comm _ZZ11callcudasubE7d_omega,8,8
.local _ZZ11callcudasubE12d_AngleOrder
.comm _ZZ11callcudasubE12d_AngleOrder,8,8
.local _ZZ11callcudasubE8dump_cnt
.comm _ZZ11callcudasubE8dump_cnt,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "callcudasub.hip"
.globl callcudasub # -- Begin function callcudasub
.p2align 4, 0x90
.type callcudasub,@function
callcudasub: # @callcudasub
.cfi_startproc
# %bb.0:
cmpl $4, _ZZ11callcudasubE8dump_cnt(%rip)
jg .LBB0_6
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movq 264(%rsp), %r12
movq 256(%rsp), %rbx
movq 152(%rsp), %rax
movq 128(%rsp), %r8
movslq (%rdi), %rdi
movq %rdi, 16(%rsp) # 8-byte Spill
movslq (%rcx), %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
movslq (%r9), %rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movslq (%r8), %r8
movslq (%rsi), %rcx
movq %rcx, 48(%rsp) # 8-byte Spill
movslq (%rdx), %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movslq (%rax), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq 216(%rsp), %rbp
movl $.L.str, %edi
movq %r8, 24(%rsp) # 8-byte Spill
movl %r8d, %esi
xorl %eax, %eax
callq printf
cmpl $0, _ZZ11callcudasubE8dump_cnt(%rip)
jne .LBB0_3
# %bb.2:
movq %r15, 64(%rsp) # 8-byte Spill
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
shlq $5, %rsi
movl $_ZZ11callcudasubE12d_AngleOrder, %edi
callq hipMalloc
leaq (,%r15,8), %rax
leaq (%rax,%rax,2), %rsi
movl $_ZZ11callcudasubE7d_omega, %edi
callq hipMalloc
movq 16(%rsp), %r13 # 8-byte Reload
leaq (,%r13,4), %rbx
movq %rbx, %rsi
imulq %r15, %rsi
movl $_ZZ11callcudasubE7d_nextZ, %edi
callq hipMalloc
movq 8(%rsp), %rax # 8-byte Reload
leaq 1(%rax), %rsi
imulq %r15, %rsi
shlq $2, %rsi
movl $_ZZ11callcudasubE6d_next, %edi
callq hipMalloc
movl $_ZZ11callcudasubE9d_nCorner, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE9d_nCFaces, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE4d_c0, %edi
movq %rbx, %rsi
callq hipMalloc
leaq (,%r13,8), %rbx
movq %rbx, %rbp
movq 48(%rsp), %r14 # 8-byte Reload
imulq %r14, %rbp
movq %rbp, %rsi
movq 40(%rsp), %r12 # 8-byte Reload
imulq %r12, %rsi
movl $_ZZ11callcudasubE8d_STotal, %edi
callq hipMalloc
imulq %r12, %rbx
imulq %r14, %r15
movq %rbx, %rsi
imulq %r15, %rsi
movl $_ZZ11callcudasubE7d_STime, %edi
callq hipMalloc
movl $_ZZ11callcudasubE9d_SigtInv, %edi
movq %rbp, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE8d_Volume, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE6d_Sigt, %edi
movq %rbp, %rsi
callq hipMalloc
movq %r12, %rbp
movq 264(%rsp), %r12
imulq %r13, %rbp
imulq 24(%rsp), %rbp # 8-byte Folded Reload
leaq (,%rbp,8), %rax
leaq (%rax,%rax,2), %rbx
movl $_ZZ11callcudasubE6d_A_fp, %edi
movq %rbx, %rsi
callq hipMalloc
movl $_ZZ11callcudasubE6d_A_ez, %edi
movq %rbx, %rsi
movq 256(%rsp), %rbx
callq hipMalloc
shlq $2, %rbp
leaq (,%rbp,2), %rsi
addq %rbp, %rsi
movq 216(%rsp), %rbp
movl $_ZZ11callcudasubE9d_Connect, %edi
callq hipMalloc
shlq $3, %r15
movq %r15, %rsi
imulq 8(%rsp), %rsi # 8-byte Folded Reload
movl $_ZZ11callcudasubE6d_psic, %edi
callq hipMalloc
imulq 56(%rsp), %r15 # 8-byte Folded Reload
movl $_ZZ11callcudasubE6d_psib, %edi
movq %r15, %rsi
movq 64(%rsp), %r15 # 8-byte Reload
callq hipMalloc
.LBB0_3:
movq _ZZ11callcudasubE12d_AngleOrder(%rip), %rdi
movq 32(%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
shlq $5, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE7d_omega(%rip), %rdi
leaq (,%r13,8), %rax
leaq (%rax,%rax,2), %rdx
movq 160(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE7d_nextZ(%rip), %rdi
movq 16(%rsp), %r14 # 8-byte Reload
leaq (,%r14,4), %r15
movq %r15, %rdx
imulq %r13, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_next(%rip), %rdi
movq 8(%rsp), %rax # 8-byte Reload
leaq 1(%rax), %rdx
imulq %r13, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_nCorner(%rip), %rdi
movq 168(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_nCFaces(%rip), %rdi
movq 176(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE4d_c0(%rip), %rdi
movq 184(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE8d_STotal(%rip), %rdi
leaq (,%r14,8), %r15
movq %r15, %rbx
movq 48(%rsp), %r14 # 8-byte Reload
imulq %r14, %rbx
movq %rbx, %rdx
movq 40(%rsp), %r12 # 8-byte Reload
imulq %r12, %rdx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE7d_STime(%rip), %rdi
imulq %r12, %r15
movq %r13, %rbp
imulq %r14, %rbp
movq %r15, %rdx
imulq %rbp, %rdx
movq 224(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_SigtInv(%rip), %rdi
movq 280(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE8d_Volume(%rip), %rdi
movq 232(%rsp), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_Sigt(%rip), %rdi
movq 272(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_A_fp(%rip), %rdi
imulq 16(%rsp), %r12 # 8-byte Folded Reload
imulq 24(%rsp), %r12 # 8-byte Folded Reload
leaq (,%r12,8), %rax
leaq (%rax,%rax,2), %rbx
movq 192(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_A_ez(%rip), %rdi
movq 200(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE9d_Connect(%rip), %rdi
shlq $2, %r12
leaq (%r12,%r12,2), %rdx
movq 208(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_psib(%rip), %rdi
shlq $3, %rbp
movq %rbp, %rdx
imulq 56(%rsp), %rdx # 8-byte Folded Reload
movq 248(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq _ZZ11callcudasubE6d_psic(%rip), %rdi
imulq 8(%rsp), %rbp # 8-byte Folded Reload
movq 240(%rsp), %rbx
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4:
movq 40(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movq 24(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq 32(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movq 16(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq 8(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
movq 48(%rsp), %r9 # 8-byte Reload
# kill: def $r9d killed $r9d killed $r9
pushq _ZZ11callcudasubE6d_psib(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_psic(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_Connect(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_A_ez(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_A_fp(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_Sigt(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE8d_Volume(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_SigtInv(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE7d_STime(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE8d_STotal(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE4d_c0(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_nCFaces(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE9d_nCorner(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE6d_next(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE7d_nextZ(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE7d_omega(%rip)
.cfi_adjust_cfa_offset 8
pushq _ZZ11callcudasubE12d_AngleOrder(%rip)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
callq __device_stub__GPU_sweep
addq $144, %rsp
.cfi_adjust_cfa_offset -144
.LBB0_5:
movq _ZZ11callcudasubE6d_psic(%rip), %rsi
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
incl _ZZ11callcudasubE8dump_cnt(%rip)
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_6:
retq
.Lfunc_end0:
.size callcudasub, .Lfunc_end0-callcudasub
.cfi_endproc
# -- End function
.type _ZZ11callcudasubE8dump_cnt,@object # @_ZZ11callcudasubE8dump_cnt
.local _ZZ11callcudasubE8dump_cnt
.comm _ZZ11callcudasubE8dump_cnt,4,4
.type _ZZ11callcudasubE12d_AngleOrder,@object # @_ZZ11callcudasubE12d_AngleOrder
.local _ZZ11callcudasubE12d_AngleOrder
.comm _ZZ11callcudasubE12d_AngleOrder,8,8
.type _ZZ11callcudasubE7d_omega,@object # @_ZZ11callcudasubE7d_omega
.local _ZZ11callcudasubE7d_omega
.comm _ZZ11callcudasubE7d_omega,8,8
.type _ZZ11callcudasubE7d_nextZ,@object # @_ZZ11callcudasubE7d_nextZ
.local _ZZ11callcudasubE7d_nextZ
.comm _ZZ11callcudasubE7d_nextZ,8,8
.type _ZZ11callcudasubE6d_next,@object # @_ZZ11callcudasubE6d_next
.local _ZZ11callcudasubE6d_next
.comm _ZZ11callcudasubE6d_next,8,8
.type _ZZ11callcudasubE9d_nCorner,@object # @_ZZ11callcudasubE9d_nCorner
.local _ZZ11callcudasubE9d_nCorner
.comm _ZZ11callcudasubE9d_nCorner,8,8
.type _ZZ11callcudasubE9d_nCFaces,@object # @_ZZ11callcudasubE9d_nCFaces
.local _ZZ11callcudasubE9d_nCFaces
.comm _ZZ11callcudasubE9d_nCFaces,8,8
.type _ZZ11callcudasubE4d_c0,@object # @_ZZ11callcudasubE4d_c0
.local _ZZ11callcudasubE4d_c0
.comm _ZZ11callcudasubE4d_c0,8,8
.type _ZZ11callcudasubE8d_STotal,@object # @_ZZ11callcudasubE8d_STotal
.local _ZZ11callcudasubE8d_STotal
.comm _ZZ11callcudasubE8d_STotal,8,8
.type _ZZ11callcudasubE7d_STime,@object # @_ZZ11callcudasubE7d_STime
.local _ZZ11callcudasubE7d_STime
.comm _ZZ11callcudasubE7d_STime,8,8
.type _ZZ11callcudasubE9d_SigtInv,@object # @_ZZ11callcudasubE9d_SigtInv
.local _ZZ11callcudasubE9d_SigtInv
.comm _ZZ11callcudasubE9d_SigtInv,8,8
.type _ZZ11callcudasubE8d_Volume,@object # @_ZZ11callcudasubE8d_Volume
.local _ZZ11callcudasubE8d_Volume
.comm _ZZ11callcudasubE8d_Volume,8,8
.type _ZZ11callcudasubE6d_Sigt,@object # @_ZZ11callcudasubE6d_Sigt
.local _ZZ11callcudasubE6d_Sigt
.comm _ZZ11callcudasubE6d_Sigt,8,8
.type _ZZ11callcudasubE6d_A_fp,@object # @_ZZ11callcudasubE6d_A_fp
.local _ZZ11callcudasubE6d_A_fp
.comm _ZZ11callcudasubE6d_A_fp,8,8
.type _ZZ11callcudasubE6d_A_ez,@object # @_ZZ11callcudasubE6d_A_ez
.local _ZZ11callcudasubE6d_A_ez
.comm _ZZ11callcudasubE6d_A_ez,8,8
.type _ZZ11callcudasubE9d_Connect,@object # @_ZZ11callcudasubE9d_Connect
.local _ZZ11callcudasubE9d_Connect
.comm _ZZ11callcudasubE9d_Connect,8,8
.type _ZZ11callcudasubE6d_psic,@object # @_ZZ11callcudasubE6d_psic
.local _ZZ11callcudasubE6d_psic
.comm _ZZ11callcudasubE6d_psic,8,8
.type _ZZ11callcudasubE6d_psib,@object # @_ZZ11callcudasubE6d_psib
.local _ZZ11callcudasubE6d_psib
.comm _ZZ11callcudasubE6d_psib,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max faces=%d\n"
.size .L.str, 14
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZZ11callcudasubE12d_AngleOrder
.addrsig_sym _ZZ11callcudasubE7d_omega
.addrsig_sym _ZZ11callcudasubE7d_nextZ
.addrsig_sym _ZZ11callcudasubE6d_next
.addrsig_sym _ZZ11callcudasubE9d_nCorner
.addrsig_sym _ZZ11callcudasubE9d_nCFaces
.addrsig_sym _ZZ11callcudasubE4d_c0
.addrsig_sym _ZZ11callcudasubE8d_STotal
.addrsig_sym _ZZ11callcudasubE7d_STime
.addrsig_sym _ZZ11callcudasubE9d_SigtInv
.addrsig_sym _ZZ11callcudasubE8d_Volume
.addrsig_sym _ZZ11callcudasubE6d_Sigt
.addrsig_sym _ZZ11callcudasubE6d_A_fp
.addrsig_sym _ZZ11callcudasubE6d_A_ez
.addrsig_sym _ZZ11callcudasubE9d_Connect
.addrsig_sym _ZZ11callcudasubE6d_psic
.addrsig_sym _ZZ11callcudasubE6d_psib
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void segCountSum(int *counter, int *segcounter, const int countlength)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < countlength){
for (int jj=0; jj<countlength; jj++){
counter[xIndex] = counter[xIndex] + segcounter[xIndex + jj*countlength];
}
}
} | code for sm_80
Function : _Z11segCountSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R19, SR_CTAID.X ; /* 0x0000000000137919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R5, R19, c[0x0][0x0], R10 ; /* 0x0000000013057a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.U32.OR P0, PT, R5, c[0x0][0x170], !P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0004706470 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ LOP3.LUT R0, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306007812 */
/* 0x000fe200078ec0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*00f0*/ IMAD.WIDE.U32 R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0004 */
/*0100*/ @!P1 BRA 0x310 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0120*/ IADD3 R8, R10, c[0x0][0x170], RZ ; /* 0x00005c000a087a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD R21, R6.reuse, 0x3, R5 ; /* 0x0000000306157824 */
/* 0x040fe200078e0205 */
/*0140*/ LEA R7, R6, R5.reuse, 0x1 ; /* 0x0000000506077211 */
/* 0x080fe400078e08ff */
/*0150*/ IADD3 R18, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000127a10 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD R19, R19, c[0x0][0x0], R8 ; /* 0x0000000013137a24 */
/* 0x000fe200078e0208 */
/*0170*/ MOV R23, R5 ; /* 0x0000000500177202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE.U32 R10, R23, R4, c[0x0][0x168] ; /* 0x00005a00170a7625 */
/* 0x000fcc00078e0004 */
/*01a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE.U32 R12, R19, R4, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fc800078e0004 */
/*01c0*/ IMAD.IADD R25, R10, 0x1, R9 ; /* 0x000000010a197824 */
/* 0x026fca00078e0209 */
/*01d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*01e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R14, R7, R4, c[0x0][0x168] ; /* 0x00005a00070e7625 */
/* 0x000fe200078e0004 */
/*0200*/ IADD3 R27, R25, R12, RZ ; /* 0x0000000c191b7210 */
/* 0x004fca0007ffe0ff */
/*0210*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE.U32 R16, R21, R4, c[0x0][0x168] ; /* 0x00005a0015107625 */
/* 0x000fe200078e0004 */
/*0240*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007ffe0ff */
/*0250*/ IMAD.IADD R29, R27, 0x1, R14 ; /* 0x000000011b1d7824 */
/* 0x004fca00078e020e */
/*0260*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*0270*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.IADD R10, R18, 0x1, R8 ; /* 0x00000001120a7824 */
/* 0x000fe200078e0208 */
/*0290*/ LEA R23, R6.reuse, R23, 0x2 ; /* 0x0000001706177211 */
/* 0x040fe200078e10ff */
/*02a0*/ IMAD R19, R6.reuse, 0x4, R19 ; /* 0x0000000406137824 */
/* 0x040fe200078e0213 */
/*02b0*/ LEA R7, R6.reuse, R7, 0x2 ; /* 0x0000000706077211 */
/* 0x040fe200078e10ff */
/*02c0*/ IMAD R21, R6, 0x4, R21 ; /* 0x0000000406157824 */
/* 0x000fe200078e0215 */
/*02d0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc40003f25270 */
/*02e0*/ IADD3 R9, R29, R16, RZ ; /* 0x000000101d097210 */
/* 0x004fca0007ffe0ff */
/*02f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ec000c101904 */
/*0300*/ @P1 BRA 0x190 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0310*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0320*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x002362000c1e1900 */
/*0330*/ IMAD R5, R8, c[0x0][0x170], R5 ; /* 0x00005c0008057a24 */
/* 0x000fc800078e0205 */
/*0340*/ IMAD.WIDE.U32 R6, R5, R4, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fcc00078e0004 */
/*0350*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x004ea2000c1e1900 */
/*0360*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a10 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0390*/ IADD3 R9, R6, R9, RZ ; /* 0x0000000906097210 */
/* 0x024fca0007ffe0ff */
/*03a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005ec000c101904 */
/*03b0*/ @P0 BRA 0x340 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void segCountSum(int *counter, int *segcounter, const int countlength)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < countlength){
for (int jj=0; jj<countlength; jj++){
counter[xIndex] = counter[xIndex] + segcounter[xIndex + jj*countlength];
}
}
} | .file "tmpxft_00098e4b_00000000-6_segCountSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11segCountSumPiS_iPiS_i
.type _Z34__device_stub__Z11segCountSumPiS_iPiS_i, @function
_Z34__device_stub__Z11segCountSumPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11segCountSumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11segCountSumPiS_iPiS_i, .-_Z34__device_stub__Z11segCountSumPiS_iPiS_i
.globl _Z11segCountSumPiS_i
.type _Z11segCountSumPiS_i, @function
_Z11segCountSumPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11segCountSumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11segCountSumPiS_i, .-_Z11segCountSumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11segCountSumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11segCountSumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void segCountSum(int *counter, int *segcounter, const int countlength)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < countlength){
for (int jj=0; jj<countlength; jj++){
counter[xIndex] = counter[xIndex] + segcounter[xIndex + jj*countlength];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void segCountSum(int *counter, int *segcounter, const int countlength)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < countlength){
for (int jj=0; jj<countlength; jj++){
counter[xIndex] = counter[xIndex] + segcounter[xIndex + jj*countlength];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void segCountSum(int *counter, int *segcounter, const int countlength)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < countlength){
for (int jj=0; jj<countlength; jj++){
counter[xIndex] = counter[xIndex] + segcounter[xIndex + jj*countlength];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11segCountSumPiS_i
.globl _Z11segCountSumPiS_i
.p2align 8
.type _Z11segCountSumPiS_i,@function
_Z11segCountSumPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s4, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s0, s4
global_load_b32 v0, v[3:4], off
.LBB0_2:
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s0, 0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11segCountSumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11segCountSumPiS_i, .Lfunc_end0-_Z11segCountSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11segCountSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11segCountSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void segCountSum(int *counter, int *segcounter, const int countlength)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if (xIndex < countlength){
for (int jj=0; jj<countlength; jj++){
counter[xIndex] = counter[xIndex] + segcounter[xIndex + jj*countlength];
}
}
} | .text
.file "segCountSum.hip"
.globl _Z26__device_stub__segCountSumPiS_i # -- Begin function _Z26__device_stub__segCountSumPiS_i
.p2align 4, 0x90
.type _Z26__device_stub__segCountSumPiS_i,@function
_Z26__device_stub__segCountSumPiS_i: # @_Z26__device_stub__segCountSumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11segCountSumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__segCountSumPiS_i, .Lfunc_end0-_Z26__device_stub__segCountSumPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11segCountSumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11segCountSumPiS_i,@object # @_Z11segCountSumPiS_i
.section .rodata,"a",@progbits
.globl _Z11segCountSumPiS_i
.p2align 3, 0x0
_Z11segCountSumPiS_i:
.quad _Z26__device_stub__segCountSumPiS_i
.size _Z11segCountSumPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11segCountSumPiS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__segCountSumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11segCountSumPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11segCountSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R19, SR_CTAID.X ; /* 0x0000000000137919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R5, R19, c[0x0][0x0], R10 ; /* 0x0000000013057a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.U32.OR P0, PT, R5, c[0x0][0x170], !P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0004706470 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ LOP3.LUT R0, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306007812 */
/* 0x000fe200078ec0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*00f0*/ IMAD.WIDE.U32 R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0004 */
/*0100*/ @!P1 BRA 0x310 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0120*/ IADD3 R8, R10, c[0x0][0x170], RZ ; /* 0x00005c000a087a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD R21, R6.reuse, 0x3, R5 ; /* 0x0000000306157824 */
/* 0x040fe200078e0205 */
/*0140*/ LEA R7, R6, R5.reuse, 0x1 ; /* 0x0000000506077211 */
/* 0x080fe400078e08ff */
/*0150*/ IADD3 R18, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000127a10 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD R19, R19, c[0x0][0x0], R8 ; /* 0x0000000013137a24 */
/* 0x000fe200078e0208 */
/*0170*/ MOV R23, R5 ; /* 0x0000000500177202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE.U32 R10, R23, R4, c[0x0][0x168] ; /* 0x00005a00170a7625 */
/* 0x000fcc00078e0004 */
/*01a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE.U32 R12, R19, R4, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fc800078e0004 */
/*01c0*/ IMAD.IADD R25, R10, 0x1, R9 ; /* 0x000000010a197824 */
/* 0x026fca00078e0209 */
/*01d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*01e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R14, R7, R4, c[0x0][0x168] ; /* 0x00005a00070e7625 */
/* 0x000fe200078e0004 */
/*0200*/ IADD3 R27, R25, R12, RZ ; /* 0x0000000c191b7210 */
/* 0x004fca0007ffe0ff */
/*0210*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE.U32 R16, R21, R4, c[0x0][0x168] ; /* 0x00005a0015107625 */
/* 0x000fe200078e0004 */
/*0240*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007ffe0ff */
/*0250*/ IMAD.IADD R29, R27, 0x1, R14 ; /* 0x000000011b1d7824 */
/* 0x004fca00078e020e */
/*0260*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*0270*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.IADD R10, R18, 0x1, R8 ; /* 0x00000001120a7824 */
/* 0x000fe200078e0208 */
/*0290*/ LEA R23, R6.reuse, R23, 0x2 ; /* 0x0000001706177211 */
/* 0x040fe200078e10ff */
/*02a0*/ IMAD R19, R6.reuse, 0x4, R19 ; /* 0x0000000406137824 */
/* 0x040fe200078e0213 */
/*02b0*/ LEA R7, R6.reuse, R7, 0x2 ; /* 0x0000000706077211 */
/* 0x040fe200078e10ff */
/*02c0*/ IMAD R21, R6, 0x4, R21 ; /* 0x0000000406157824 */
/* 0x000fe200078e0215 */
/*02d0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc40003f25270 */
/*02e0*/ IADD3 R9, R29, R16, RZ ; /* 0x000000101d097210 */
/* 0x004fca0007ffe0ff */
/*02f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ec000c101904 */
/*0300*/ @P1 BRA 0x190 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0310*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0320*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x002362000c1e1900 */
/*0330*/ IMAD R5, R8, c[0x0][0x170], R5 ; /* 0x00005c0008057a24 */
/* 0x000fc800078e0205 */
/*0340*/ IMAD.WIDE.U32 R6, R5, R4, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fcc00078e0004 */
/*0350*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x004ea2000c1e1900 */
/*0360*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a10 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0390*/ IADD3 R9, R6, R9, RZ ; /* 0x0000000906097210 */
/* 0x024fca0007ffe0ff */
/*03a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005ec000c101904 */
/*03b0*/ @P0 BRA 0x340 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11segCountSumPiS_i
.globl _Z11segCountSumPiS_i
.p2align 8
.type _Z11segCountSumPiS_i,@function
_Z11segCountSumPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s4, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s0, s4
global_load_b32 v0, v[3:4], off
.LBB0_2:
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s0, 0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11segCountSumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11segCountSumPiS_i, .Lfunc_end0-_Z11segCountSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11segCountSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11segCountSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098e4b_00000000-6_segCountSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11segCountSumPiS_iPiS_i
.type _Z34__device_stub__Z11segCountSumPiS_iPiS_i, @function
_Z34__device_stub__Z11segCountSumPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11segCountSumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11segCountSumPiS_iPiS_i, .-_Z34__device_stub__Z11segCountSumPiS_iPiS_i
.globl _Z11segCountSumPiS_i
.type _Z11segCountSumPiS_i, @function
_Z11segCountSumPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11segCountSumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11segCountSumPiS_i, .-_Z11segCountSumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11segCountSumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11segCountSumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "segCountSum.hip"
.globl _Z26__device_stub__segCountSumPiS_i # -- Begin function _Z26__device_stub__segCountSumPiS_i
.p2align 4, 0x90
.type _Z26__device_stub__segCountSumPiS_i,@function
_Z26__device_stub__segCountSumPiS_i: # @_Z26__device_stub__segCountSumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11segCountSumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__segCountSumPiS_i, .Lfunc_end0-_Z26__device_stub__segCountSumPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11segCountSumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11segCountSumPiS_i,@object # @_Z11segCountSumPiS_i
.section .rodata,"a",@progbits
.globl _Z11segCountSumPiS_i
.p2align 3, 0x0
_Z11segCountSumPiS_i:
.quad _Z26__device_stub__segCountSumPiS_i
.size _Z11segCountSumPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11segCountSumPiS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__segCountSumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11segCountSumPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void searchGPU(float *data, const float x, int *result)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (data[idx] == x)
{
result[0] = static_cast<int>(data[idx]);
result[1] = idx;
}
} | code for sm_80
Function : _Z9searchGPUPffPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FSETP.NEU.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0b */
/* 0x004fda0003f0d000 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ F2I.TRUNC.NTZ R7, R0 ; /* 0x0000000000077305 */
/* 0x000e22000020f100 */
/*00b0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*00d0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void searchGPU(float *data, const float x, int *result)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (data[idx] == x)
{
result[0] = static_cast<int>(data[idx]);
result[1] = idx;
}
} | .file "tmpxft_00100c55_00000000-6_searchGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1ff, .-_Z1ff
.globl _Z31__device_stub__Z9searchGPUPffPiPffPi
.type _Z31__device_stub__Z9searchGPUPffPiPffPi, @function
_Z31__device_stub__Z9searchGPUPffPiPffPi:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9searchGPUPffPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z31__device_stub__Z9searchGPUPffPiPffPi, .-_Z31__device_stub__Z9searchGPUPffPiPffPi
.globl _Z9searchGPUPffPi
.type _Z9searchGPUPffPi, @function
_Z9searchGPUPffPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9searchGPUPffPiPffPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9searchGPUPffPi, .-_Z9searchGPUPffPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9searchGPUPffPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9searchGPUPffPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void searchGPU(float *data, const float x, int *result)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (data[idx] == x)
{
result[0] = static_cast<int>(data[idx]);
result[1] = idx;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void searchGPU(float *data, const float x, int *result)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (data[idx] == x)
{
result[0] = static_cast<int>(data[idx]);
result[1] = idx;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void searchGPU(float *data, const float x, int *result)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (data[idx] == x)
{
result[0] = static_cast<int>(data[idx]);
result[1] = idx;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9searchGPUPffPi
.globl _Z9searchGPUPffPi
.p2align 8
.type _Z9searchGPUPffPi,@function
_Z9searchGPUPffPi:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 s4, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_cvt_i32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9searchGPUPffPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9searchGPUPffPi, .Lfunc_end0-_Z9searchGPUPffPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9searchGPUPffPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9searchGPUPffPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void searchGPU(float *data, const float x, int *result)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (data[idx] == x)
{
result[0] = static_cast<int>(data[idx]);
result[1] = idx;
}
} | .text
.file "searchGPU.hip"
.globl _Z24__device_stub__searchGPUPffPi # -- Begin function _Z24__device_stub__searchGPUPffPi
.p2align 4, 0x90
.type _Z24__device_stub__searchGPUPffPi,@function
_Z24__device_stub__searchGPUPffPi: # @_Z24__device_stub__searchGPUPffPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9searchGPUPffPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__searchGPUPffPi, .Lfunc_end0-_Z24__device_stub__searchGPUPffPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9searchGPUPffPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9searchGPUPffPi,@object # @_Z9searchGPUPffPi
.section .rodata,"a",@progbits
.globl _Z9searchGPUPffPi
.p2align 3, 0x0
_Z9searchGPUPffPi:
.quad _Z24__device_stub__searchGPUPffPi
.size _Z9searchGPUPffPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9searchGPUPffPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__searchGPUPffPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9searchGPUPffPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9searchGPUPffPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FSETP.NEU.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0b */
/* 0x004fda0003f0d000 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ F2I.TRUNC.NTZ R7, R0 ; /* 0x0000000000077305 */
/* 0x000e22000020f100 */
/*00b0*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*00d0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9searchGPUPffPi
.globl _Z9searchGPUPffPi
.p2align 8
.type _Z9searchGPUPffPi,@function
_Z9searchGPUPffPi:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 s4, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_cvt_i32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9searchGPUPffPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9searchGPUPffPi, .Lfunc_end0-_Z9searchGPUPffPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9searchGPUPffPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9searchGPUPffPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00100c55_00000000-6_searchGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1ff, .-_Z1ff
.globl _Z31__device_stub__Z9searchGPUPffPiPffPi
.type _Z31__device_stub__Z9searchGPUPffPiPffPi, @function
_Z31__device_stub__Z9searchGPUPffPiPffPi:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9searchGPUPffPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z31__device_stub__Z9searchGPUPffPiPffPi, .-_Z31__device_stub__Z9searchGPUPffPiPffPi
.globl _Z9searchGPUPffPi
.type _Z9searchGPUPffPi, @function
_Z9searchGPUPffPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9searchGPUPffPiPffPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9searchGPUPffPi, .-_Z9searchGPUPffPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9searchGPUPffPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9searchGPUPffPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "searchGPU.hip"
.globl _Z24__device_stub__searchGPUPffPi # -- Begin function _Z24__device_stub__searchGPUPffPi
.p2align 4, 0x90
.type _Z24__device_stub__searchGPUPffPi,@function
_Z24__device_stub__searchGPUPffPi: # @_Z24__device_stub__searchGPUPffPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9searchGPUPffPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__searchGPUPffPi, .Lfunc_end0-_Z24__device_stub__searchGPUPffPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9searchGPUPffPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9searchGPUPffPi,@object # @_Z9searchGPUPffPi
.section .rodata,"a",@progbits
.globl _Z9searchGPUPffPi
.p2align 3, 0x0
_Z9searchGPUPffPi:
.quad _Z24__device_stub__searchGPUPffPi
.size _Z9searchGPUPffPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9searchGPUPffPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__searchGPUPffPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9searchGPUPffPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
void polynomial_expansion (float* poly, int degree,
int n, float* array) {
}
int main (int argc, char* argv[]) {
//TODO: add usage
if (argc < 3) {
std::cerr<<"usage: "<<argv[0]<<" n degree"<<std::endl;
return -1;
}
int n = atoi(argv[1]); //TODO: atoi is an unsafe function
int degree = atoi(argv[2]);
int nbiter = 1;
float* array = new float[n];
float* poly = new float[degree+1];
for (int i=0; i<n; ++i)
array[i] = 1.;
for (int i=0; i<degree+1; ++i)
poly[i] = 1.;
std::chrono::time_point<std::chrono::system_clock> begin, end;
begin = std::chrono::system_clock::now();
for (int iter = 0; iter<nbiter; ++iter)
polynomial_expansion (poly, degree, n, array);
end = std::chrono::system_clock::now();
std::chrono::duration<double> totaltime = (end-begin)/nbiter;
std::cerr<<array[0]<<std::endl;
std::cout<<n<<" "<<degree<<" "<<totaltime.count()<<std::endl;
delete[] array;
delete[] poly;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
void polynomial_expansion (float* poly, int degree,
int n, float* array) {
}
int main (int argc, char* argv[]) {
//TODO: add usage
if (argc < 3) {
std::cerr<<"usage: "<<argv[0]<<" n degree"<<std::endl;
return -1;
}
int n = atoi(argv[1]); //TODO: atoi is an unsafe function
int degree = atoi(argv[2]);
int nbiter = 1;
float* array = new float[n];
float* poly = new float[degree+1];
for (int i=0; i<n; ++i)
array[i] = 1.;
for (int i=0; i<degree+1; ++i)
poly[i] = 1.;
std::chrono::time_point<std::chrono::system_clock> begin, end;
begin = std::chrono::system_clock::now();
for (int iter = 0; iter<nbiter; ++iter)
polynomial_expansion (poly, degree, n, array);
end = std::chrono::system_clock::now();
std::chrono::duration<double> totaltime = (end-begin)/nbiter;
std::cerr<<array[0]<<std::endl;
std::cout<<n<<" "<<degree<<" "<<totaltime.count()<<std::endl;
delete[] array;
delete[] poly;
return 0;
} | .file "tmpxft_0015c9ed_00000000-6_polynomial_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3780:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3780:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20polynomial_expansionPfiiS_
.type _Z20polynomial_expansionPfiiS_, @function
_Z20polynomial_expansionPfiiS_:
.LFB3768:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3768:
.size _Z20polynomial_expansionPfiiS_, .-_Z20polynomial_expansionPfiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: "
.LC1:
.string " n degree"
.LC4:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
cmpl $2, %edi
jle .L19
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movslq %ebp, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L7
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
leal 1(%rbx), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L20
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
testl %ebp, %ebp
jle .L11
movq %r12, %rax
leal -1(%rbp), %edx
leaq 4(%r12,%rdx,4), %rdx
movss .LC2(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
.L11:
testl %ebx, %ebx
js .L13
movq %r13, %rax
movl %ebx, %ebx
leaq 4(%r13,%rbx,4), %rdx
movss .LC2(%rip), %xmm0
.L14:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L14
.L13:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq %xmm0, %rbx
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movl $0, %eax
.L4:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %eax
jmp .L4
.L7:
call __cxa_throw_bad_array_new_length@PLT
.L20:
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
void polynomial_expansion (float* poly, int degree,
int n, float* array) {
}
int main (int argc, char* argv[]) {
//TODO: add usage
if (argc < 3) {
std::cerr<<"usage: "<<argv[0]<<" n degree"<<std::endl;
return -1;
}
int n = atoi(argv[1]); //TODO: atoi is an unsafe function
int degree = atoi(argv[2]);
int nbiter = 1;
float* array = new float[n];
float* poly = new float[degree+1];
for (int i=0; i<n; ++i)
array[i] = 1.;
for (int i=0; i<degree+1; ++i)
poly[i] = 1.;
std::chrono::time_point<std::chrono::system_clock> begin, end;
begin = std::chrono::system_clock::now();
for (int iter = 0; iter<nbiter; ++iter)
polynomial_expansion (poly, degree, n, array);
end = std::chrono::system_clock::now();
std::chrono::duration<double> totaltime = (end-begin)/nbiter;
std::cerr<<array[0]<<std::endl;
std::cout<<n<<" "<<degree<<" "<<totaltime.count()<<std::endl;
delete[] array;
delete[] poly;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
void polynomial_expansion (float* poly, int degree,
int n, float* array) {
}
int main (int argc, char* argv[]) {
//TODO: add usage
if (argc < 3) {
std::cerr<<"usage: "<<argv[0]<<" n degree"<<std::endl;
return -1;
}
int n = atoi(argv[1]); //TODO: atoi is an unsafe function
int degree = atoi(argv[2]);
int nbiter = 1;
float* array = new float[n];
float* poly = new float[degree+1];
for (int i=0; i<n; ++i)
array[i] = 1.;
for (int i=0; i<degree+1; ++i)
poly[i] = 1.;
std::chrono::time_point<std::chrono::system_clock> begin, end;
begin = std::chrono::system_clock::now();
for (int iter = 0; iter<nbiter; ++iter)
polynomial_expansion (poly, degree, n, array);
end = std::chrono::system_clock::now();
std::chrono::duration<double> totaltime = (end-begin)/nbiter;
std::cerr<<array[0]<<std::endl;
std::cout<<n<<" "<<degree<<" "<<totaltime.count()<<std::endl;
delete[] array;
delete[] poly;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
void polynomial_expansion (float* poly, int degree,
int n, float* array) {
}
int main (int argc, char* argv[]) {
//TODO: add usage
if (argc < 3) {
std::cerr<<"usage: "<<argv[0]<<" n degree"<<std::endl;
return -1;
}
int n = atoi(argv[1]); //TODO: atoi is an unsafe function
int degree = atoi(argv[2]);
int nbiter = 1;
float* array = new float[n];
float* poly = new float[degree+1];
for (int i=0; i<n; ++i)
array[i] = 1.;
for (int i=0; i<degree+1; ++i)
poly[i] = 1.;
std::chrono::time_point<std::chrono::system_clock> begin, end;
begin = std::chrono::system_clock::now();
for (int iter = 0; iter<nbiter; ++iter)
polynomial_expansion (poly, degree, n, array);
end = std::chrono::system_clock::now();
std::chrono::duration<double> totaltime = (end-begin)/nbiter;
std::cerr<<array[0]<<std::endl;
std::cout<<n<<" "<<degree<<" "<<totaltime.count()<<std::endl;
delete[] array;
delete[] poly;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
void polynomial_expansion (float* poly, int degree,
int n, float* array) {
}
int main (int argc, char* argv[]) {
//TODO: add usage
if (argc < 3) {
std::cerr<<"usage: "<<argv[0]<<" n degree"<<std::endl;
return -1;
}
int n = atoi(argv[1]); //TODO: atoi is an unsafe function
int degree = atoi(argv[2]);
int nbiter = 1;
float* array = new float[n];
float* poly = new float[degree+1];
for (int i=0; i<n; ++i)
array[i] = 1.;
for (int i=0; i<degree+1; ++i)
poly[i] = 1.;
std::chrono::time_point<std::chrono::system_clock> begin, end;
begin = std::chrono::system_clock::now();
for (int iter = 0; iter<nbiter; ++iter)
polynomial_expansion (poly, degree, n, array);
end = std::chrono::system_clock::now();
std::chrono::duration<double> totaltime = (end-begin)/nbiter;
std::cerr<<array[0]<<std::endl;
std::cout<<n<<" "<<degree<<" "<<totaltime.count()<<std::endl;
delete[] array;
delete[] poly;
return 0;
} | .text
.file "polynomial_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20polynomial_expansionPfiiS_ # -- Begin function _Z20polynomial_expansionPfiiS_
.p2align 4, 0x90
.type _Z20polynomial_expansionPfiiS_,@function
_Z20polynomial_expansionPfiiS_: # @_Z20polynomial_expansionPfiiS_
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z20polynomial_expansionPfiiS_, .Lfunc_end0-_Z20polynomial_expansionPfiiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $2, %edi
jg .LBB1_9
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.3:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_9:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r15d, %r12
leaq (,%r12,4), %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB1_12
# %bb.10: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB1_11
.LBB1_12: # %.critedge
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cerr, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_22
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33
subq %r13, %rbp
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
cmpb $0, 56(%r12)
je .LBB1_15
# %bb.14:
movzbl 67(%r12), %ecx
jmp .LBB1_16
.LBB1_2:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_22
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_15:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_22
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38
cmpb $0, 56(%r14)
je .LBB1_19
# %bb.18:
movzbl 67(%r14), %ecx
jmp .LBB1_20
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
jmp .LBB1_21
.LBB1_19:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB1_21:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " n degree"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015c9ed_00000000-6_polynomial_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3780:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3780:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20polynomial_expansionPfiiS_
.type _Z20polynomial_expansionPfiiS_, @function
_Z20polynomial_expansionPfiiS_:
.LFB3768:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3768:
.size _Z20polynomial_expansionPfiiS_, .-_Z20polynomial_expansionPfiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: "
.LC1:
.string " n degree"
.LC4:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
cmpl $2, %edi
jle .L19
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movslq %ebp, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L7
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
leal 1(%rbx), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L20
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
testl %ebp, %ebp
jle .L11
movq %r12, %rax
leal -1(%rbp), %edx
leaq 4(%r12,%rdx,4), %rdx
movss .LC2(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
.L11:
testl %ebx, %ebx
js .L13
movq %r13, %rax
movl %ebx, %ebx
leaq 4(%r13,%rbx,4), %rdx
movss .LC2(%rip), %xmm0
.L14:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L14
.L13:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq %xmm0, %rbx
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movl $0, %eax
.L4:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %eax
jmp .L4
.L7:
call __cxa_throw_bad_array_new_length@PLT
.L20:
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "polynomial_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20polynomial_expansionPfiiS_ # -- Begin function _Z20polynomial_expansionPfiiS_
.p2align 4, 0x90
.type _Z20polynomial_expansionPfiiS_,@function
_Z20polynomial_expansionPfiiS_: # @_Z20polynomial_expansionPfiiS_
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z20polynomial_expansionPfiiS_, .Lfunc_end0-_Z20polynomial_expansionPfiiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $2, %edi
jg .LBB1_9
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.3:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_9:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r15d, %r12
leaq (,%r12,4), %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB1_12
# %bb.10: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB1_11
.LBB1_12: # %.critedge
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cerr, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_22
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33
subq %r13, %rbp
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
cmpb $0, 56(%r12)
je .LBB1_15
# %bb.14:
movzbl 67(%r12), %ecx
jmp .LBB1_16
.LBB1_2:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_22
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_15:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_22
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38
cmpb $0, 56(%r14)
je .LBB1_19
# %bb.18:
movzbl 67(%r14), %ecx
jmp .LBB1_20
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
jmp .LBB1_21
.LBB1_19:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB1_21:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " n degree"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void pack_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// gather
d_output[address] = d_input[idx];
}
} | code for sm_80
Function : _Z11pack_kernelPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*00e0*/ SHF.L.U64.HI R3, R0, 0x2, R3 ; /* 0x0000000200037819 */
/* 0x000fe40000010203 */
/*00f0*/ IADD3 R4, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3.X R5, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003057a10 */
/* 0x000fca00007fe4ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R7, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x000fcc00007fe4ff */
/*0140*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FADD R0, R4, -1 ; /* 0xbf80000004007421 */
/* 0x004fcc0000000000 */
/*0160*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e24000020f100 */
/*0170*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0209 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x008fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void pack_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// gather
d_output[address] = d_input[idx];
}
} | .file "tmpxft_001ac94f_00000000-6_pack_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i
.type _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i, @function
_Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11pack_kernelPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i, .-_Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i
.globl _Z11pack_kernelPfS_S_S_i
.type _Z11pack_kernelPfS_S_S_i, @function
_Z11pack_kernelPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11pack_kernelPfS_S_S_i, .-_Z11pack_kernelPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11pack_kernelPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11pack_kernelPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void pack_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// gather
d_output[address] = d_input[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pack_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// gather
d_output[address] = d_input[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pack_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// gather
d_output[address] = d_input[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11pack_kernelPfS_S_S_i
.globl _Z11pack_kernelPfS_S_S_i
.p2align 8
.type _Z11pack_kernelPfS_S_S_i,@function
_Z11pack_kernelPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, -1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11pack_kernelPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11pack_kernelPfS_S_S_i, .Lfunc_end0-_Z11pack_kernelPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11pack_kernelPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11pack_kernelPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pack_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// gather
d_output[address] = d_input[idx];
}
} | .text
.file "pack_kernel.hip"
.globl _Z26__device_stub__pack_kernelPfS_S_S_i # -- Begin function _Z26__device_stub__pack_kernelPfS_S_S_i
.p2align 4, 0x90
.type _Z26__device_stub__pack_kernelPfS_S_S_i,@function
_Z26__device_stub__pack_kernelPfS_S_S_i: # @_Z26__device_stub__pack_kernelPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11pack_kernelPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__pack_kernelPfS_S_S_i, .Lfunc_end0-_Z26__device_stub__pack_kernelPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11pack_kernelPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11pack_kernelPfS_S_S_i,@object # @_Z11pack_kernelPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z11pack_kernelPfS_S_S_i
.p2align 3, 0x0
_Z11pack_kernelPfS_S_S_i:
.quad _Z26__device_stub__pack_kernelPfS_S_S_i
.size _Z11pack_kernelPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11pack_kernelPfS_S_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__pack_kernelPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11pack_kernelPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11pack_kernelPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*00e0*/ SHF.L.U64.HI R3, R0, 0x2, R3 ; /* 0x0000000200037819 */
/* 0x000fe40000010203 */
/*00f0*/ IADD3 R4, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3.X R5, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003057a10 */
/* 0x000fca00007fe4ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R7, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x000fcc00007fe4ff */
/*0140*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FADD R0, R4, -1 ; /* 0xbf80000004007421 */
/* 0x004fcc0000000000 */
/*0160*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e24000020f100 */
/*0170*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0209 */
/*0180*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x008fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11pack_kernelPfS_S_S_i
.globl _Z11pack_kernelPfS_S_S_i
.p2align 8
.type _Z11pack_kernelPfS_S_S_i,@function
_Z11pack_kernelPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, -1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11pack_kernelPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11pack_kernelPfS_S_S_i, .Lfunc_end0-_Z11pack_kernelPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11pack_kernelPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11pack_kernelPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ac94f_00000000-6_pack_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i
.type _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i, @function
_Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11pack_kernelPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i, .-_Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i
.globl _Z11pack_kernelPfS_S_S_i
.type _Z11pack_kernelPfS_S_S_i, @function
_Z11pack_kernelPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11pack_kernelPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11pack_kernelPfS_S_S_i, .-_Z11pack_kernelPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11pack_kernelPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11pack_kernelPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pack_kernel.hip"
.globl _Z26__device_stub__pack_kernelPfS_S_S_i # -- Begin function _Z26__device_stub__pack_kernelPfS_S_S_i
.p2align 4, 0x90
.type _Z26__device_stub__pack_kernelPfS_S_S_i,@function
_Z26__device_stub__pack_kernelPfS_S_S_i: # @_Z26__device_stub__pack_kernelPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11pack_kernelPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__pack_kernelPfS_S_S_i, .Lfunc_end0-_Z26__device_stub__pack_kernelPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11pack_kernelPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11pack_kernelPfS_S_S_i,@object # @_Z11pack_kernelPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z11pack_kernelPfS_S_S_i
.p2align 3, 0x0
_Z11pack_kernelPfS_S_S_i:
.quad _Z26__device_stub__pack_kernelPfS_S_S_i
.size _Z11pack_kernelPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11pack_kernelPfS_S_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__pack_kernelPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11pack_kernelPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
__global__ void staticReverse(int *d, int n)
{
__shared__ int staticMem[12288];
int idx = threadIdx.x;
if (n <= blockDim.x & idx < n) {
staticMem[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
staticMem[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = staticMem[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = staticMem[k + i];
++i;
}
}
}
}
__global__ void dynamicReverse(int *d, int n)
{
extern __shared__ int dynamicMem[];
int idx = threadIdx.x;
int *arr = dynamicMem;
if (n <= blockDim.x & idx < n) {
arr[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
arr[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = arr[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = arr[k + i];
++i;
}
}
}
}
int main(int argc, char **argv)
{
int n = atoi(argv[1]); // FIX ME TO max possible size
int r[n]; // FIX ME TO dynamic arrays if neccesary
size_t bytes = n * sizeof(int);
int *a = (int *) malloc(bytes);
int *d = (int *) malloc(bytes);
for (int i = 0; i < n; i++) {
a[i] = i;
r[i] = n-i-1;
d[i] = 0;
}
int *d_d;
cudaMalloc(&d_d, bytes);
int blockSize = 1024;
// run version with static shared memory
cudaMemcpy(d_d, a, bytes, cudaMemcpyHostToDevice);
staticReverse<<<1, blockSize>>>(d_d, n); // FIX kernel execution params
cudaMemcpy(d, d_d, bytes, cudaMemcpyDeviceToHost);
int flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("staticReverse OK\n");
}
for (int i = 0; i < n; ++i) {
d[i] = 0;
}
// run dynamic shared memory version
cudaMemcpy(d_d, a, n*sizeof(int), cudaMemcpyHostToDevice);
dynamicReverse<<<1, blockSize, n*sizeof(int)>>>(d_d, n); // FIX kernel executon params
cudaMemcpy(d, d_d, n * sizeof(int), cudaMemcpyDeviceToHost);
flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("dynamicReverse OK\n");
}
free(a);
free(d);
cudaFree(d_d);
return 0;
} | code for sm_80
Function : _Z14dynamicReversePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0050*/ BSSY B0, 0x270 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R8.reuse, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x041fe40003f06270 */
/*0070*/ IMAD.WIDE R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe400078e020b */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706070 */
/*0090*/ @P0 BRA 0x220 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R8, 0xc, RZ ; /* 0x0000000c08007824 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B1, 0x210 ; /* 0x0000015000017945 */
/* 0x000fe80003800000 */
/*00c0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f26270 */
/*00d0*/ @P1 BRA 0x200 ; /* 0x0000012000001947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e020b */
/*0100*/ IADD3 R6, -R0.reuse, c[0x0][0x168], -R7 ; /* 0x00005a0000067a10 */
/* 0x040fe20007ffe907 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0120*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0009 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*0170*/ ISETP.GE.AND P1, PT, R0.reuse, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x040fe40003f26270 */
/*0180*/ ISETP.LT.U32.AND P3, PT, R7.reuse, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x040fe40003f61070 */
/*0190*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fca0007f5e0ff */
/*01c0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*01d0*/ STS [R6], R5 ; /* 0x0000000506007388 */
/* 0x0041e40000000800 */
/*01e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x001fe20007ffe0ff */
/*01f0*/ @!P1 BRA P3, 0x150 ; /* 0xffffff5000009947 */
/* 0x000fea000183ffff */
/*0200*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x260 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0230*/ LOP3.LUT R4, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff047212 */
/* 0x000fc800078e33ff */
/*0240*/ IADD3 R5, R4, c[0x0][0x168], RZ ; /* 0x00005a0004057a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x0041e40000004800 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ @P0 BRA 0x3b0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD R4, R8, 0xc, RZ ; /* 0x0000000c08047824 */
/* 0x000fca00078e02ff */
/*02a0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*02b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.WIDE R2, R4.reuse, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e020b */
/*02d0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD R0, R8, 0x30, RZ ; /* 0x0000003008007824 */
/* 0x001fe400078e02ff */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0300*/ LDS R7, [R0] ; /* 0x0000000000077984 */
/* 0x0000620000000800 */
/*0310*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x040fe40003f06270 */
/*0320*/ ISETP.LT.U32.AND P2, PT, R5.reuse, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x040fe40003f41070 */
/*0330*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0021e4000c101904 */
/*0370*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0380*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0390*/ @!P0 BRA P2, 0x300 ; /* 0xffffff6000008947 */
/* 0x000fea000103ffff */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ LDS R5, [R8.X4] ; /* 0x0000000008057984 */
/* 0x001e280000004800 */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13staticReversePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0050*/ BSSY B0, 0x270 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R8.reuse, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x041fe40003f06270 */
/*0070*/ IMAD.WIDE R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe400078e020b */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706070 */
/*0090*/ @P0 BRA 0x220 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R8, 0xc, RZ ; /* 0x0000000c08007824 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B1, 0x210 ; /* 0x0000015000017945 */
/* 0x000fe80003800000 */
/*00c0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f26270 */
/*00d0*/ @P1 BRA 0x200 ; /* 0x0000012000001947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e020b */
/*0100*/ IADD3 R6, -R0.reuse, c[0x0][0x168], -R7 ; /* 0x00005a0000067a10 */
/* 0x040fe20007ffe907 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0120*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0009 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*0170*/ ISETP.GE.AND P1, PT, R0.reuse, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x040fe40003f26270 */
/*0180*/ ISETP.LT.U32.AND P3, PT, R7.reuse, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x040fe40003f61070 */
/*0190*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fca0007f5e0ff */
/*01c0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*01d0*/ STS [R6], R5 ; /* 0x0000000506007388 */
/* 0x0041e40000000800 */
/*01e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x001fe20007ffe0ff */
/*01f0*/ @!P1 BRA P3, 0x150 ; /* 0xffffff5000009947 */
/* 0x000fea000183ffff */
/*0200*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x260 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0230*/ LOP3.LUT R4, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff047212 */
/* 0x000fc800078e33ff */
/*0240*/ IADD3 R5, R4, c[0x0][0x168], RZ ; /* 0x00005a0004057a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x0041e40000004800 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ @P0 BRA 0x3b0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD R4, R8, 0xc, RZ ; /* 0x0000000c08047824 */
/* 0x000fca00078e02ff */
/*02a0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*02b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.WIDE R2, R4.reuse, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e020b */
/*02d0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD R0, R8, 0x30, RZ ; /* 0x0000003008007824 */
/* 0x001fe400078e02ff */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0300*/ LDS R7, [R0] ; /* 0x0000000000077984 */
/* 0x0000620000000800 */
/*0310*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x040fe40003f06270 */
/*0320*/ ISETP.LT.U32.AND P2, PT, R5.reuse, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x040fe40003f41070 */
/*0330*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0021e4000c101904 */
/*0370*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0380*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0390*/ @!P0 BRA P2, 0x300 ; /* 0xffffff6000008947 */
/* 0x000fea000103ffff */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ LDS R5, [R8.X4] ; /* 0x0000000008057984 */
/* 0x001e280000004800 */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
__global__ void staticReverse(int *d, int n)
{
__shared__ int staticMem[12288];
int idx = threadIdx.x;
if (n <= blockDim.x & idx < n) {
staticMem[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
staticMem[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = staticMem[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = staticMem[k + i];
++i;
}
}
}
}
__global__ void dynamicReverse(int *d, int n)
{
extern __shared__ int dynamicMem[];
int idx = threadIdx.x;
int *arr = dynamicMem;
if (n <= blockDim.x & idx < n) {
arr[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
arr[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = arr[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = arr[k + i];
++i;
}
}
}
}
int main(int argc, char **argv)
{
int n = atoi(argv[1]); // FIX ME TO max possible size
int r[n]; // FIX ME TO dynamic arrays if neccesary
size_t bytes = n * sizeof(int);
int *a = (int *) malloc(bytes);
int *d = (int *) malloc(bytes);
for (int i = 0; i < n; i++) {
a[i] = i;
r[i] = n-i-1;
d[i] = 0;
}
int *d_d;
cudaMalloc(&d_d, bytes);
int blockSize = 1024;
// run version with static shared memory
cudaMemcpy(d_d, a, bytes, cudaMemcpyHostToDevice);
staticReverse<<<1, blockSize>>>(d_d, n); // FIX kernel execution params
cudaMemcpy(d, d_d, bytes, cudaMemcpyDeviceToHost);
int flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("staticReverse OK\n");
}
for (int i = 0; i < n; ++i) {
d[i] = 0;
}
// run dynamic shared memory version
cudaMemcpy(d_d, a, n*sizeof(int), cudaMemcpyHostToDevice);
dynamicReverse<<<1, blockSize, n*sizeof(int)>>>(d_d, n); // FIX kernel executon params
cudaMemcpy(d, d_d, n * sizeof(int), cudaMemcpyDeviceToHost);
flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("dynamicReverse OK\n");
}
free(a);
free(d);
cudaFree(d_d);
return 0;
} | .file "tmpxft_0010639c_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13staticReversePiiPii
.type _Z34__device_stub__Z13staticReversePiiPii, @function
_Z34__device_stub__Z13staticReversePiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13staticReversePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z34__device_stub__Z13staticReversePiiPii, .-_Z34__device_stub__Z13staticReversePiiPii
.globl _Z13staticReversePii
.type _Z13staticReversePii, @function
_Z13staticReversePii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13staticReversePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13staticReversePii, .-_Z13staticReversePii
.globl _Z35__device_stub__Z14dynamicReversePiiPii
.type _Z35__device_stub__Z14dynamicReversePiiPii, @function
_Z35__device_stub__Z14dynamicReversePiiPii:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14dynamicReversePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z35__device_stub__Z14dynamicReversePiiPii, .-_Z35__device_stub__Z14dynamicReversePiiPii
.globl _Z14dynamicReversePii
.type _Z14dynamicReversePii, @function
_Z14dynamicReversePii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14dynamicReversePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z14dynamicReversePii, .-_Z14dynamicReversePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: d[%d]!=r[%d] (%d, %d)\n"
.LC1:
.string "staticReverse OK\n"
.LC2:
.string "dynamicReverse OK\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -112(%rbp)
movl %eax, -116(%rbp)
cltq
salq $2, %rax
movq %rax, -104(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L20:
cmpq %rdx, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L22
orq $0, -8(%rsp,%rax)
.L22:
movq %rsp, %r13
movq -104(%rbp), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq -112(%rbp), %rax
testl %eax, %eax
jle .L23
leal -1(%rax), %ecx
movl %ecx, %esi
movl $0, %eax
.L24:
movl %eax, (%r14,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, 0(%r13,%rax,4)
movl $0, (%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rsi, %rdx
jne .L24
.L23:
leaq -88(%rbp), %rdi
movq -104(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L25:
movl $2, %ecx
movq -104(%rbp), %rdx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -112(%rbp), %rax
testl %eax, %eax
jle .L26
leal -1(%rax), %r15d
movl $0, %ebx
movl $1, %edx
jmp .L28
.L43:
movl -116(%rbp), %esi
movq -88(%rbp), %rdi
call _Z34__device_stub__Z13staticReversePiiPii
jmp .L25
.L27:
leaq 1(%rbx), %rax
cmpq %r15, %rbx
je .L44
movq %rax, %rbx
.L28:
movl (%r12,%rbx,4), %r8d
movl 0(%r13,%rbx,4), %r9d
cmpl %r9d, %r8d
je .L27
movl %ebx, %edx
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L27
.L44:
testl %edx, %edx
jne .L26
.L29:
movq %r12, %rax
movq -112(%rbp), %rdi
leal -1(%rdi), %edx
leaq 4(%r12,%rdx,4), %rdx
.L31:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L31
.L30:
movl $1, %ecx
movq -104(%rbp), %rbx
movq %rbx, %rdx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movq %rbx, %r8
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L32:
movl $2, %ecx
movq -104(%rbp), %rdx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -112(%rbp), %rax
testl %eax, %eax
jle .L33
leal -1(%rax), %r15d
movl $0, %ebx
movl $1, %edx
jmp .L35
.L26:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, -112(%rbp)
jg .L29
jmp .L30
.L45:
movl -116(%rbp), %esi
movq -88(%rbp), %rdi
call _Z35__device_stub__Z14dynamicReversePiiPii
jmp .L32
.L34:
leaq 1(%rbx), %rax
cmpq %r15, %rbx
je .L46
movq %rax, %rbx
.L35:
movl (%r12,%rbx,4), %r8d
movl 0(%r13,%rbx,4), %r9d
cmpl %r9d, %r8d
je .L34
movl %ebx, %edx
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L34
.L46:
testl %edx, %edx
jne .L33
.L36:
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L33:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14dynamicReversePii"
.LC4:
.string "_Z13staticReversePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dynamicReversePii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13staticReversePii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
__global__ void staticReverse(int *d, int n)
{
__shared__ int staticMem[12288];
int idx = threadIdx.x;
if (n <= blockDim.x & idx < n) {
staticMem[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
staticMem[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = staticMem[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = staticMem[k + i];
++i;
}
}
}
}
__global__ void dynamicReverse(int *d, int n)
{
extern __shared__ int dynamicMem[];
int idx = threadIdx.x;
int *arr = dynamicMem;
if (n <= blockDim.x & idx < n) {
arr[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
arr[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = arr[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = arr[k + i];
++i;
}
}
}
}
int main(int argc, char **argv)
{
int n = atoi(argv[1]); // FIX ME TO max possible size
int r[n]; // FIX ME TO dynamic arrays if neccesary
size_t bytes = n * sizeof(int);
int *a = (int *) malloc(bytes);
int *d = (int *) malloc(bytes);
for (int i = 0; i < n; i++) {
a[i] = i;
r[i] = n-i-1;
d[i] = 0;
}
int *d_d;
cudaMalloc(&d_d, bytes);
int blockSize = 1024;
// run version with static shared memory
cudaMemcpy(d_d, a, bytes, cudaMemcpyHostToDevice);
staticReverse<<<1, blockSize>>>(d_d, n); // FIX kernel execution params
cudaMemcpy(d, d_d, bytes, cudaMemcpyDeviceToHost);
int flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("staticReverse OK\n");
}
for (int i = 0; i < n; ++i) {
d[i] = 0;
}
// run dynamic shared memory version
cudaMemcpy(d_d, a, n*sizeof(int), cudaMemcpyHostToDevice);
dynamicReverse<<<1, blockSize, n*sizeof(int)>>>(d_d, n); // FIX kernel executon params
cudaMemcpy(d, d_d, n * sizeof(int), cudaMemcpyDeviceToHost);
flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("dynamicReverse OK\n");
}
free(a);
free(d);
cudaFree(d_d);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void staticReverse(int *d, int n)
{
__shared__ int staticMem[12288];
int idx = threadIdx.x;
if (n <= blockDim.x & idx < n) {
staticMem[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
staticMem[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = staticMem[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = staticMem[k + i];
++i;
}
}
}
}
__global__ void dynamicReverse(int *d, int n)
{
extern __shared__ int dynamicMem[];
int idx = threadIdx.x;
int *arr = dynamicMem;
if (n <= blockDim.x & idx < n) {
arr[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
arr[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = arr[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = arr[k + i];
++i;
}
}
}
}
int main(int argc, char **argv)
{
int n = atoi(argv[1]); // FIX ME TO max possible size
int r[n]; // FIX ME TO dynamic arrays if neccesary
size_t bytes = n * sizeof(int);
int *a = (int *) malloc(bytes);
int *d = (int *) malloc(bytes);
for (int i = 0; i < n; i++) {
a[i] = i;
r[i] = n-i-1;
d[i] = 0;
}
int *d_d;
hipMalloc(&d_d, bytes);
int blockSize = 1024;
// run version with static shared memory
hipMemcpy(d_d, a, bytes, hipMemcpyHostToDevice);
staticReverse<<<1, blockSize>>>(d_d, n); // FIX kernel execution params
hipMemcpy(d, d_d, bytes, hipMemcpyDeviceToHost);
int flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("staticReverse OK\n");
}
for (int i = 0; i < n; ++i) {
d[i] = 0;
}
// run dynamic shared memory version
hipMemcpy(d_d, a, n*sizeof(int), hipMemcpyHostToDevice);
dynamicReverse<<<1, blockSize, n*sizeof(int)>>>(d_d, n); // FIX kernel executon params
hipMemcpy(d, d_d, n * sizeof(int), hipMemcpyDeviceToHost);
flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("dynamicReverse OK\n");
}
free(a);
free(d);
hipFree(d_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void staticReverse(int *d, int n)
{
__shared__ int staticMem[12288];
int idx = threadIdx.x;
if (n <= blockDim.x & idx < n) {
staticMem[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
staticMem[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = staticMem[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = staticMem[k + i];
++i;
}
}
}
}
__global__ void dynamicReverse(int *d, int n)
{
extern __shared__ int dynamicMem[];
int idx = threadIdx.x;
int *arr = dynamicMem;
if (n <= blockDim.x & idx < n) {
arr[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
arr[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = arr[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = arr[k + i];
++i;
}
}
}
}
int main(int argc, char **argv)
{
int n = atoi(argv[1]); // FIX ME TO max possible size
int r[n]; // FIX ME TO dynamic arrays if neccesary
size_t bytes = n * sizeof(int);
int *a = (int *) malloc(bytes);
int *d = (int *) malloc(bytes);
for (int i = 0; i < n; i++) {
a[i] = i;
r[i] = n-i-1;
d[i] = 0;
}
int *d_d;
hipMalloc(&d_d, bytes);
int blockSize = 1024;
// run version with static shared memory
hipMemcpy(d_d, a, bytes, hipMemcpyHostToDevice);
staticReverse<<<1, blockSize>>>(d_d, n); // FIX kernel execution params
hipMemcpy(d, d_d, bytes, hipMemcpyDeviceToHost);
int flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("staticReverse OK\n");
}
for (int i = 0; i < n; ++i) {
d[i] = 0;
}
// run dynamic shared memory version
hipMemcpy(d_d, a, n*sizeof(int), hipMemcpyHostToDevice);
dynamicReverse<<<1, blockSize, n*sizeof(int)>>>(d_d, n); // FIX kernel executon params
hipMemcpy(d, d_d, n * sizeof(int), hipMemcpyDeviceToHost);
flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("dynamicReverse OK\n");
}
free(a);
free(d);
hipFree(d_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13staticReversePii
.globl _Z13staticReversePii
.p2align 8
.type _Z13staticReversePii,@function
_Z13staticReversePii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_cmp_lt_u32 s3, s2
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_7
v_mul_u32_u24_e32 v3, 12, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s6, s2, 2
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, s6, v1
v_add_co_u32 v1, s6, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s6
s_mov_b32 s6, -4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_6
.LBB0_4:
s_or_b32 s8, s8, exec_lo
s_mov_b32 s9, exec_lo
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB0_3
global_load_b32 v5, v[1:2], off
v_add_nc_u32_e32 v6, s6, v4
s_add_i32 s6, s6, -4
v_add_co_u32 v1, vcc_lo, v1, 4
s_cmpk_eq_i32 s6, 0xffcc
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cselect_b32 s10, -1, 0
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v1, 2, v0
v_not_b32_e32 v2, v0
global_load_b32 v1, v1, s[0:1]
v_add_lshl_u32 v2, v2, s2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s4
s_cbranch_execnz .LBB0_12
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execnz .LBB0_18
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_12:
v_mul_u32_u24_e32 v2, 12, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_17
v_lshlrev_b32_e32 v3, 2, v2
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s5, s0, v3
v_add_co_ci_u32_e64 v1, null, s1, 0, s5
s_movk_i32 s5, 0xffd0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_17
.LBB0_15:
s_or_b32 s7, s7, exec_lo
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v4, s5, v3
s_add_i32 s5, s5, 4
v_add_nc_u32_e32 v2, 1, v2
s_cmp_eq_u32 s5, 0
s_cselect_b32 s9, -1, 0
ds_load_b32 v4, v4 offset:48
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_14
.LBB0_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_11
.LBB0_18:
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13staticReversePii
.amdhsa_group_segment_fixed_size 49152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13staticReversePii, .Lfunc_end0-_Z13staticReversePii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14dynamicReversePii
.globl _Z14dynamicReversePii
.p2align 8
.type _Z14dynamicReversePii,@function
_Z14dynamicReversePii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_cmp_lt_u32 s3, s2
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB1_7
v_mul_u32_u24_e32 v3, 12, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB1_6
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s6, s2, 2
s_mov_b32 s7, -4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, s6, v1
v_add_co_u32 v1, s6, s0, v1
v_add_nc_u32_e32 v4, 0, v2
v_add_co_ci_u32_e64 v2, null, s1, 0, s6
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_6
.LBB1_4:
s_or_b32 s8, s8, exec_lo
s_mov_b32 s9, exec_lo
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB1_3
global_load_b32 v5, v[1:2], off
v_add_nc_u32_e32 v6, s7, v4
s_add_i32 s7, s7, -4
v_add_co_u32 v1, vcc_lo, v1, 4
s_cmpk_eq_i32 s7, 0xffcc
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cselect_b32 s10, -1, 0
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_branch .LBB1_3
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB1_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB1_9
v_lshlrev_b32_e32 v1, 2, v0
v_not_b32_e32 v2, v0
s_lshl_b32 s5, s2, 2
global_load_b32 v1, v1, s[0:1]
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, s5, 0, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s4
s_cbranch_execnz .LBB1_12
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execnz .LBB1_18
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB1_12:
v_mul_u32_u24_e32 v2, 12, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB1_17
v_lshlrev_b32_e32 v0, 2, v2
s_movk_i32 s6, 0xffd0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0, v0
v_add_co_u32 v0, s5, s0, v0
v_add_co_ci_u32_e64 v1, null, s1, 0, s5
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_15
.p2align 6
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s5, s8, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_17
.LBB1_15:
s_or_b32 s7, s7, exec_lo
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB1_14
v_add_nc_u32_e32 v4, s6, v3
s_add_i32 s6, s6, 4
v_add_nc_u32_e32 v2, 1, v2
s_cmp_eq_u32 s6, 0
s_cselect_b32 s9, -1, 0
ds_load_b32 v4, v4 offset:48
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB1_14
.LBB1_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_11
.LBB1_18:
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0, v0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14dynamicReversePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14dynamicReversePii, .Lfunc_end1-_Z14dynamicReversePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 49152
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13staticReversePii
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z13staticReversePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14dynamicReversePii
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z14dynamicReversePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void staticReverse(int *d, int n)
{
__shared__ int staticMem[12288];
int idx = threadIdx.x;
if (n <= blockDim.x & idx < n) {
staticMem[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
staticMem[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = staticMem[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = staticMem[k + i];
++i;
}
}
}
}
__global__ void dynamicReverse(int *d, int n)
{
extern __shared__ int dynamicMem[];
int idx = threadIdx.x;
int *arr = dynamicMem;
if (n <= blockDim.x & idx < n) {
arr[n - 1 - idx] = d[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
arr[n - 1 - (k + i)] = d[k + i];
++i;
}
}
}
__syncthreads();
idx = threadIdx.x;
if (n <= blockDim.x && idx < n) {
d[idx] = arr[idx];
} else {
int k = idx * 12;
if (k < n) {
int i = 0;
while (i < 12 && (k + i) < n) {
d[k + i] = arr[k + i];
++i;
}
}
}
}
int main(int argc, char **argv)
{
int n = atoi(argv[1]); // FIX ME TO max possible size
int r[n]; // FIX ME TO dynamic arrays if neccesary
size_t bytes = n * sizeof(int);
int *a = (int *) malloc(bytes);
int *d = (int *) malloc(bytes);
for (int i = 0; i < n; i++) {
a[i] = i;
r[i] = n-i-1;
d[i] = 0;
}
int *d_d;
hipMalloc(&d_d, bytes);
int blockSize = 1024;
// run version with static shared memory
hipMemcpy(d_d, a, bytes, hipMemcpyHostToDevice);
staticReverse<<<1, blockSize>>>(d_d, n); // FIX kernel execution params
hipMemcpy(d, d_d, bytes, hipMemcpyDeviceToHost);
int flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("staticReverse OK\n");
}
for (int i = 0; i < n; ++i) {
d[i] = 0;
}
// run dynamic shared memory version
hipMemcpy(d_d, a, n*sizeof(int), hipMemcpyHostToDevice);
dynamicReverse<<<1, blockSize, n*sizeof(int)>>>(d_d, n); // FIX kernel executon params
hipMemcpy(d, d_d, n * sizeof(int), hipMemcpyDeviceToHost);
flag = 1;
for (int i = 0; i < n; i++) {
if (d[i] != r[i]) {
printf("Error: d[%d]!=r[%d] (%d, %d)\n", i, i, d[i], r[i]);
flag = 0;
}
}
if (flag) {
printf("dynamicReverse OK\n");
}
free(a);
free(d);
hipFree(d_d);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__staticReversePii # -- Begin function _Z28__device_stub__staticReversePii
.p2align 4, 0x90
.type _Z28__device_stub__staticReversePii,@function
_Z28__device_stub__staticReversePii: # @_Z28__device_stub__staticReversePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13staticReversePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__staticReversePii, .Lfunc_end0-_Z28__device_stub__staticReversePii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__dynamicReversePii # -- Begin function _Z29__device_stub__dynamicReversePii
.p2align 4, 0x90
.type _Z29__device_stub__dynamicReversePii,@function
_Z29__device_stub__dynamicReversePii: # @_Z29__device_stub__dynamicReversePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14dynamicReversePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z29__device_stub__dynamicReversePii, .Lfunc_end1-_Z29__device_stub__dynamicReversePii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl %r13d, %eax
leaq 15(,%rax,4), %rax
andq $-16, %rax
movq %rsp, %r12
subq %rax, %r12
movq %r12, %rsp
movslq %r13d, %rbx
leaq (,%rbx,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, -144(%rbp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r14
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
leaq (,%r13,4), %rdx
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdx
xorl %ebx, %ebx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl %r13d, %eax
leal -1(%r13), %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, (%r15,%rbx,4)
movl %ecx, (%r12,%rbx,4)
incq %rbx
decl %ecx
cmpq %rbx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r13, -152(%rbp) # 8-byte Spill
movabsq $4294967297, %r13 # imm = 0x100000001
leaq -48(%rbp), %rdi
movq -144(%rbp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
movq -48(%rbp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1023(%r13), %rdx
movq %r13, %rdi
movq -152(%rbp), %r13 # 8-byte Reload
movl $1, %esi
movq %rdx, -160(%rbp) # 8-byte Spill
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq -48(%rbp), %rax
movq %rax, -112(%rbp)
movl %r13d, -52(%rbp)
leaq -112(%rbp), %rax
movq %rax, -128(%rbp)
leaq -52(%rbp), %rax
movq %rax, -120(%rbp)
leaq -104(%rbp), %rdi
leaq -88(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -64(%rbp), %rcx
callq __hipPopCallConfiguration
movq -104(%rbp), %rsi
movl -96(%rbp), %edx
movq -88(%rbp), %rcx
movl -80(%rbp), %r8d
leaq -128(%rbp), %r9
movl $_Z13staticReversePii, %edi
pushq -64(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_5:
movq -48(%rbp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
movq %r15, -136(%rbp) # 8-byte Spill
jle .LBB2_11
# %bb.6: # %.lr.ph103.preheader
movl %r13d, %r15d
movl $1, %ebx
xorl %r13d, %r13d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r13
cmpq %r13, %r15
je .LBB2_10
.LBB2_7: # %.lr.ph103
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %ecx
movl (%r12,%r13,4), %r8d
cmpl %r8d, %ecx
je .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
movl %r13d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
jmp .LBB2_9
.LBB2_10: # %._crit_edge104.loopexit
testl %ebx, %ebx
movq -136(%rbp), %r15 # 8-byte Reload
movq -152(%rbp), %r13 # 8-byte Reload
movq -144(%rbp), %rbx # 8-byte Reload
je .LBB2_12
.LBB2_11: # %.critedge
movl $.Lstr, %edi
callq puts@PLT
.LBB2_12:
testl %r13d, %r13d
jle .LBB2_14
# %bb.13: # %.lr.ph107.preheader
movq %r13, %rdx
shlq $2, %rdx
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_14: # %._crit_edge108
movq -48(%rbp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq -160(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq -48(%rbp), %rax
movq %rax, -112(%rbp)
movl %r13d, -52(%rbp)
leaq -112(%rbp), %rax
movq %rax, -128(%rbp)
leaq -52(%rbp), %rax
movq %rax, -120(%rbp)
leaq -104(%rbp), %rdi
leaq -88(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -64(%rbp), %rcx
callq __hipPopCallConfiguration
movq -104(%rbp), %rsi
movl -96(%rbp), %edx
movq -88(%rbp), %rcx
movl -80(%rbp), %r8d
leaq -128(%rbp), %r9
movl $_Z14dynamicReversePii, %edi
pushq -64(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_16:
movq -48(%rbp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
jle .LBB2_22
# %bb.17: # %.lr.ph112.preheader
movl %r13d, %r13d
movl $1, %ebx
xorl %r15d, %r15d
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_20: # in Loop: Header=BB2_18 Depth=1
incq %r15
cmpq %r15, %r13
je .LBB2_21
.LBB2_18: # %.lr.ph112
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %ecx
movl (%r12,%r15,4), %r8d
cmpl %r8d, %ecx
je .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
movl %r15d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
jmp .LBB2_20
.LBB2_21: # %._crit_edge113.loopexit
testl %ebx, %ebx
movq -136(%rbp), %r15 # 8-byte Reload
je .LBB2_23
.LBB2_22: # %.critedge129
movl $.Lstr.1, %edi
callq puts@PLT
.LBB2_23:
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq -48(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13staticReversePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dynamicReversePii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13staticReversePii,@object # @_Z13staticReversePii
.section .rodata,"a",@progbits
.globl _Z13staticReversePii
.p2align 3, 0x0
_Z13staticReversePii:
.quad _Z28__device_stub__staticReversePii
.size _Z13staticReversePii, 8
.type _Z14dynamicReversePii,@object # @_Z14dynamicReversePii
.globl _Z14dynamicReversePii
.p2align 3, 0x0
_Z14dynamicReversePii:
.quad _Z29__device_stub__dynamicReversePii
.size _Z14dynamicReversePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: d[%d]!=r[%d] (%d, %d)\n"
.size .L.str, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13staticReversePii"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14dynamicReversePii"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "staticReverse OK"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "dynamicReverse OK"
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__staticReversePii
.addrsig_sym _Z29__device_stub__dynamicReversePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13staticReversePii
.addrsig_sym _Z14dynamicReversePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14dynamicReversePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0050*/ BSSY B0, 0x270 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R8.reuse, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x041fe40003f06270 */
/*0070*/ IMAD.WIDE R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe400078e020b */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706070 */
/*0090*/ @P0 BRA 0x220 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R8, 0xc, RZ ; /* 0x0000000c08007824 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B1, 0x210 ; /* 0x0000015000017945 */
/* 0x000fe80003800000 */
/*00c0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f26270 */
/*00d0*/ @P1 BRA 0x200 ; /* 0x0000012000001947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e020b */
/*0100*/ IADD3 R6, -R0.reuse, c[0x0][0x168], -R7 ; /* 0x00005a0000067a10 */
/* 0x040fe20007ffe907 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0120*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0009 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*0170*/ ISETP.GE.AND P1, PT, R0.reuse, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x040fe40003f26270 */
/*0180*/ ISETP.LT.U32.AND P3, PT, R7.reuse, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x040fe40003f61070 */
/*0190*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fca0007f5e0ff */
/*01c0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*01d0*/ STS [R6], R5 ; /* 0x0000000506007388 */
/* 0x0041e40000000800 */
/*01e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x001fe20007ffe0ff */
/*01f0*/ @!P1 BRA P3, 0x150 ; /* 0xffffff5000009947 */
/* 0x000fea000183ffff */
/*0200*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x260 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0230*/ LOP3.LUT R4, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff047212 */
/* 0x000fc800078e33ff */
/*0240*/ IADD3 R5, R4, c[0x0][0x168], RZ ; /* 0x00005a0004057a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x0041e40000004800 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ @P0 BRA 0x3b0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD R4, R8, 0xc, RZ ; /* 0x0000000c08047824 */
/* 0x000fca00078e02ff */
/*02a0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*02b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.WIDE R2, R4.reuse, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e020b */
/*02d0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD R0, R8, 0x30, RZ ; /* 0x0000003008007824 */
/* 0x001fe400078e02ff */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0300*/ LDS R7, [R0] ; /* 0x0000000000077984 */
/* 0x0000620000000800 */
/*0310*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x040fe40003f06270 */
/*0320*/ ISETP.LT.U32.AND P2, PT, R5.reuse, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x040fe40003f41070 */
/*0330*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0021e4000c101904 */
/*0370*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0380*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0390*/ @!P0 BRA P2, 0x300 ; /* 0xffffff6000008947 */
/* 0x000fea000103ffff */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ LDS R5, [R8.X4] ; /* 0x0000000008057984 */
/* 0x001e280000004800 */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13staticReversePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0050*/ BSSY B0, 0x270 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R8.reuse, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x041fe40003f06270 */
/*0070*/ IMAD.WIDE R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fe400078e020b */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706070 */
/*0090*/ @P0 BRA 0x220 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R8, 0xc, RZ ; /* 0x0000000c08007824 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B1, 0x210 ; /* 0x0000015000017945 */
/* 0x000fe80003800000 */
/*00c0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f26270 */
/*00d0*/ @P1 BRA 0x200 ; /* 0x0000012000001947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e020b */
/*0100*/ IADD3 R6, -R0.reuse, c[0x0][0x168], -R7 ; /* 0x00005a0000067a10 */
/* 0x040fe20007ffe907 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0120*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0009 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*0170*/ ISETP.GE.AND P1, PT, R0.reuse, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x040fe40003f26270 */
/*0180*/ ISETP.LT.U32.AND P3, PT, R7.reuse, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x040fe40003f61070 */
/*0190*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fca0007f5e0ff */
/*01c0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*01d0*/ STS [R6], R5 ; /* 0x0000000506007388 */
/* 0x0041e40000000800 */
/*01e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x001fe20007ffe0ff */
/*01f0*/ @!P1 BRA P3, 0x150 ; /* 0xffffff5000009947 */
/* 0x000fea000183ffff */
/*0200*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x260 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0230*/ LOP3.LUT R4, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff047212 */
/* 0x000fc800078e33ff */
/*0240*/ IADD3 R5, R4, c[0x0][0x168], RZ ; /* 0x00005a0004057a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x0041e40000004800 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ @P0 BRA 0x3b0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD R4, R8, 0xc, RZ ; /* 0x0000000c08047824 */
/* 0x000fca00078e02ff */
/*02a0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*02b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.WIDE R2, R4.reuse, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe200078e020b */
/*02d0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD R0, R8, 0x30, RZ ; /* 0x0000003008007824 */
/* 0x001fe400078e02ff */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0300*/ LDS R7, [R0] ; /* 0x0000000000077984 */
/* 0x0000620000000800 */
/*0310*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x040fe40003f06270 */
/*0320*/ ISETP.LT.U32.AND P2, PT, R5.reuse, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x040fe40003f41070 */
/*0330*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0021e4000c101904 */
/*0370*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0380*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0390*/ @!P0 BRA P2, 0x300 ; /* 0xffffff6000008947 */
/* 0x000fea000103ffff */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ LDS R5, [R8.X4] ; /* 0x0000000008057984 */
/* 0x001e280000004800 */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13staticReversePii
.globl _Z13staticReversePii
.p2align 8
.type _Z13staticReversePii,@function
_Z13staticReversePii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_cmp_lt_u32 s3, s2
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_7
v_mul_u32_u24_e32 v3, 12, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s6, s2, 2
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, s6, v1
v_add_co_u32 v1, s6, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s6
s_mov_b32 s6, -4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_6
.LBB0_4:
s_or_b32 s8, s8, exec_lo
s_mov_b32 s9, exec_lo
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB0_3
global_load_b32 v5, v[1:2], off
v_add_nc_u32_e32 v6, s6, v4
s_add_i32 s6, s6, -4
v_add_co_u32 v1, vcc_lo, v1, 4
s_cmpk_eq_i32 s6, 0xffcc
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cselect_b32 s10, -1, 0
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v1, 2, v0
v_not_b32_e32 v2, v0
global_load_b32 v1, v1, s[0:1]
v_add_lshl_u32 v2, v2, s2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s4
s_cbranch_execnz .LBB0_12
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execnz .LBB0_18
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_12:
v_mul_u32_u24_e32 v2, 12, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_17
v_lshlrev_b32_e32 v3, 2, v2
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s5, s0, v3
v_add_co_ci_u32_e64 v1, null, s1, 0, s5
s_movk_i32 s5, 0xffd0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_17
.LBB0_15:
s_or_b32 s7, s7, exec_lo
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v4, s5, v3
s_add_i32 s5, s5, 4
v_add_nc_u32_e32 v2, 1, v2
s_cmp_eq_u32 s5, 0
s_cselect_b32 s9, -1, 0
ds_load_b32 v4, v4 offset:48
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_14
.LBB0_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_11
.LBB0_18:
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13staticReversePii
.amdhsa_group_segment_fixed_size 49152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13staticReversePii, .Lfunc_end0-_Z13staticReversePii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14dynamicReversePii
.globl _Z14dynamicReversePii
.p2align 8
.type _Z14dynamicReversePii,@function
_Z14dynamicReversePii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_cmp_lt_u32 s3, s2
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB1_7
v_mul_u32_u24_e32 v3, 12, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB1_6
v_lshlrev_b32_e32 v1, 2, v3
s_lshl_b32 s6, s2, 2
s_mov_b32 s7, -4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, s6, v1
v_add_co_u32 v1, s6, s0, v1
v_add_nc_u32_e32 v4, 0, v2
v_add_co_ci_u32_e64 v2, null, s1, 0, s6
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_6
.LBB1_4:
s_or_b32 s8, s8, exec_lo
s_mov_b32 s9, exec_lo
v_cmpx_gt_i32_e64 s2, v3
s_cbranch_execz .LBB1_3
global_load_b32 v5, v[1:2], off
v_add_nc_u32_e32 v6, s7, v4
s_add_i32 s7, s7, -4
v_add_co_u32 v1, vcc_lo, v1, 4
s_cmpk_eq_i32 s7, 0xffcc
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cselect_b32 s10, -1, 0
v_add_nc_u32_e32 v3, 1, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_branch .LBB1_3
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB1_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB1_9
v_lshlrev_b32_e32 v1, 2, v0
v_not_b32_e32 v2, v0
s_lshl_b32 s5, s2, 2
global_load_b32 v1, v1, s[0:1]
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, s5, 0, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s4
s_cbranch_execnz .LBB1_12
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execnz .LBB1_18
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB1_12:
v_mul_u32_u24_e32 v2, 12, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB1_17
v_lshlrev_b32_e32 v0, 2, v2
s_movk_i32 s6, 0xffd0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0, v0
v_add_co_u32 v0, s5, s0, v0
v_add_co_ci_u32_e64 v1, null, s1, 0, s5
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_15
.p2align 6
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s5, s8, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_17
.LBB1_15:
s_or_b32 s7, s7, exec_lo
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB1_14
v_add_nc_u32_e32 v4, s6, v3
s_add_i32 s6, s6, 4
v_add_nc_u32_e32 v2, 1, v2
s_cmp_eq_u32 s6, 0
s_cselect_b32 s9, -1, 0
ds_load_b32 v4, v4 offset:48
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB1_14
.LBB1_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_11
.LBB1_18:
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0, v0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14dynamicReversePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14dynamicReversePii, .Lfunc_end1-_Z14dynamicReversePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 49152
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13staticReversePii
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z13staticReversePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14dynamicReversePii
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z14dynamicReversePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010639c_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13staticReversePiiPii
.type _Z34__device_stub__Z13staticReversePiiPii, @function
_Z34__device_stub__Z13staticReversePiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13staticReversePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z34__device_stub__Z13staticReversePiiPii, .-_Z34__device_stub__Z13staticReversePiiPii
.globl _Z13staticReversePii
.type _Z13staticReversePii, @function
_Z13staticReversePii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13staticReversePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13staticReversePii, .-_Z13staticReversePii
.globl _Z35__device_stub__Z14dynamicReversePiiPii
.type _Z35__device_stub__Z14dynamicReversePiiPii, @function
_Z35__device_stub__Z14dynamicReversePiiPii:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14dynamicReversePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z35__device_stub__Z14dynamicReversePiiPii, .-_Z35__device_stub__Z14dynamicReversePiiPii
.globl _Z14dynamicReversePii
.type _Z14dynamicReversePii, @function
_Z14dynamicReversePii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14dynamicReversePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z14dynamicReversePii, .-_Z14dynamicReversePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: d[%d]!=r[%d] (%d, %d)\n"
.LC1:
.string "staticReverse OK\n"
.LC2:
.string "dynamicReverse OK\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -112(%rbp)
movl %eax, -116(%rbp)
cltq
salq $2, %rax
movq %rax, -104(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L20:
cmpq %rdx, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L22
orq $0, -8(%rsp,%rax)
.L22:
movq %rsp, %r13
movq -104(%rbp), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq -112(%rbp), %rax
testl %eax, %eax
jle .L23
leal -1(%rax), %ecx
movl %ecx, %esi
movl $0, %eax
.L24:
movl %eax, (%r14,%rax,4)
movl %ecx, %edx
subl %eax, %edx
movl %edx, 0(%r13,%rax,4)
movl $0, (%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rsi, %rdx
jne .L24
.L23:
leaq -88(%rbp), %rdi
movq -104(%rbp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L25:
movl $2, %ecx
movq -104(%rbp), %rdx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -112(%rbp), %rax
testl %eax, %eax
jle .L26
leal -1(%rax), %r15d
movl $0, %ebx
movl $1, %edx
jmp .L28
.L43:
movl -116(%rbp), %esi
movq -88(%rbp), %rdi
call _Z34__device_stub__Z13staticReversePiiPii
jmp .L25
.L27:
leaq 1(%rbx), %rax
cmpq %r15, %rbx
je .L44
movq %rax, %rbx
.L28:
movl (%r12,%rbx,4), %r8d
movl 0(%r13,%rbx,4), %r9d
cmpl %r9d, %r8d
je .L27
movl %ebx, %edx
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L27
.L44:
testl %edx, %edx
jne .L26
.L29:
movq %r12, %rax
movq -112(%rbp), %rdi
leal -1(%rdi), %edx
leaq 4(%r12,%rdx,4), %rdx
.L31:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L31
.L30:
movl $1, %ecx
movq -104(%rbp), %rbx
movq %rbx, %rdx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movq %rbx, %r8
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L32:
movl $2, %ecx
movq -104(%rbp), %rdx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -112(%rbp), %rax
testl %eax, %eax
jle .L33
leal -1(%rax), %r15d
movl $0, %ebx
movl $1, %edx
jmp .L35
.L26:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, -112(%rbp)
jg .L29
jmp .L30
.L45:
movl -116(%rbp), %esi
movq -88(%rbp), %rdi
call _Z35__device_stub__Z14dynamicReversePiiPii
jmp .L32
.L34:
leaq 1(%rbx), %rax
cmpq %r15, %rbx
je .L46
movq %rax, %rbx
.L35:
movl (%r12,%rbx,4), %r8d
movl 0(%r13,%rbx,4), %r9d
cmpl %r9d, %r8d
je .L34
movl %ebx, %edx
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L34
.L46:
testl %edx, %edx
jne .L33
.L36:
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L33:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14dynamicReversePii"
.LC4:
.string "_Z13staticReversePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14dynamicReversePii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13staticReversePii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__staticReversePii # -- Begin function _Z28__device_stub__staticReversePii
.p2align 4, 0x90
.type _Z28__device_stub__staticReversePii,@function
_Z28__device_stub__staticReversePii: # @_Z28__device_stub__staticReversePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13staticReversePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__staticReversePii, .Lfunc_end0-_Z28__device_stub__staticReversePii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__dynamicReversePii # -- Begin function _Z29__device_stub__dynamicReversePii
.p2align 4, 0x90
.type _Z29__device_stub__dynamicReversePii,@function
_Z29__device_stub__dynamicReversePii: # @_Z29__device_stub__dynamicReversePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14dynamicReversePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z29__device_stub__dynamicReversePii, .Lfunc_end1-_Z29__device_stub__dynamicReversePii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl %r13d, %eax
leaq 15(,%rax,4), %rax
andq $-16, %rax
movq %rsp, %r12
subq %rax, %r12
movq %r12, %rsp
movslq %r13d, %rbx
leaq (,%rbx,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, -144(%rbp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r14
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
leaq (,%r13,4), %rdx
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdx
xorl %ebx, %ebx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl %r13d, %eax
leal -1(%r13), %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, (%r15,%rbx,4)
movl %ecx, (%r12,%rbx,4)
incq %rbx
decl %ecx
cmpq %rbx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r13, -152(%rbp) # 8-byte Spill
movabsq $4294967297, %r13 # imm = 0x100000001
leaq -48(%rbp), %rdi
movq -144(%rbp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
movq -48(%rbp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1023(%r13), %rdx
movq %r13, %rdi
movq -152(%rbp), %r13 # 8-byte Reload
movl $1, %esi
movq %rdx, -160(%rbp) # 8-byte Spill
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq -48(%rbp), %rax
movq %rax, -112(%rbp)
movl %r13d, -52(%rbp)
leaq -112(%rbp), %rax
movq %rax, -128(%rbp)
leaq -52(%rbp), %rax
movq %rax, -120(%rbp)
leaq -104(%rbp), %rdi
leaq -88(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -64(%rbp), %rcx
callq __hipPopCallConfiguration
movq -104(%rbp), %rsi
movl -96(%rbp), %edx
movq -88(%rbp), %rcx
movl -80(%rbp), %r8d
leaq -128(%rbp), %r9
movl $_Z13staticReversePii, %edi
pushq -64(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_5:
movq -48(%rbp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
movq %r15, -136(%rbp) # 8-byte Spill
jle .LBB2_11
# %bb.6: # %.lr.ph103.preheader
movl %r13d, %r15d
movl $1, %ebx
xorl %r13d, %r13d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r13
cmpq %r13, %r15
je .LBB2_10
.LBB2_7: # %.lr.ph103
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %ecx
movl (%r12,%r13,4), %r8d
cmpl %r8d, %ecx
je .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
movl %r13d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
jmp .LBB2_9
.LBB2_10: # %._crit_edge104.loopexit
testl %ebx, %ebx
movq -136(%rbp), %r15 # 8-byte Reload
movq -152(%rbp), %r13 # 8-byte Reload
movq -144(%rbp), %rbx # 8-byte Reload
je .LBB2_12
.LBB2_11: # %.critedge
movl $.Lstr, %edi
callq puts@PLT
.LBB2_12:
testl %r13d, %r13d
jle .LBB2_14
# %bb.13: # %.lr.ph107.preheader
movq %r13, %rdx
shlq $2, %rdx
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_14: # %._crit_edge108
movq -48(%rbp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq -160(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq -48(%rbp), %rax
movq %rax, -112(%rbp)
movl %r13d, -52(%rbp)
leaq -112(%rbp), %rax
movq %rax, -128(%rbp)
leaq -52(%rbp), %rax
movq %rax, -120(%rbp)
leaq -104(%rbp), %rdi
leaq -88(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -64(%rbp), %rcx
callq __hipPopCallConfiguration
movq -104(%rbp), %rsi
movl -96(%rbp), %edx
movq -88(%rbp), %rcx
movl -80(%rbp), %r8d
leaq -128(%rbp), %r9
movl $_Z14dynamicReversePii, %edi
pushq -64(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_16:
movq -48(%rbp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
jle .LBB2_22
# %bb.17: # %.lr.ph112.preheader
movl %r13d, %r13d
movl $1, %ebx
xorl %r15d, %r15d
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_20: # in Loop: Header=BB2_18 Depth=1
incq %r15
cmpq %r15, %r13
je .LBB2_21
.LBB2_18: # %.lr.ph112
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %ecx
movl (%r12,%r15,4), %r8d
cmpl %r8d, %ecx
je .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
movl %r15d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
jmp .LBB2_20
.LBB2_21: # %._crit_edge113.loopexit
testl %ebx, %ebx
movq -136(%rbp), %r15 # 8-byte Reload
je .LBB2_23
.LBB2_22: # %.critedge129
movl $.Lstr.1, %edi
callq puts@PLT
.LBB2_23:
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq -48(%rbp), %rdi
callq hipFree
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13staticReversePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14dynamicReversePii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13staticReversePii,@object # @_Z13staticReversePii
.section .rodata,"a",@progbits
.globl _Z13staticReversePii
.p2align 3, 0x0
_Z13staticReversePii:
.quad _Z28__device_stub__staticReversePii
.size _Z13staticReversePii, 8
.type _Z14dynamicReversePii,@object # @_Z14dynamicReversePii
.globl _Z14dynamicReversePii
.p2align 3, 0x0
_Z14dynamicReversePii:
.quad _Z29__device_stub__dynamicReversePii
.size _Z14dynamicReversePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: d[%d]!=r[%d] (%d, %d)\n"
.size .L.str, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13staticReversePii"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14dynamicReversePii"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "staticReverse OK"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "dynamicReverse OK"
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__staticReversePii
.addrsig_sym _Z29__device_stub__dynamicReversePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13staticReversePii
.addrsig_sym _Z14dynamicReversePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p4.cu -o assignment5-p4
#include <cmath>
#include <cuda.h>
#include <iostream>
const uint64_t N = (1 << 10);
using namespace std;
__global__ void kernel1(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__global__ void kernel2(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__host__ void cpumatMul(uint64_t* A, uint64_t* B, uint64_t* C) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
float sum = 0.0;
for (uint64_t k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = sum;
}
}
}
__host__ void check_result(uint64_t* w_ref, uint64_t* w_opt) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
if (w_ref[i * N + j] != w_opt[i * N + j]) {
cout << "Difference found\n";
exit(EXIT_FAILURE);
}
}
}
cout << "No differences found between base and test versions\n";
}
int main() {
int SIZE = N * N;
cudaError_t status;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
uint64_t *h_A, *h_B, *h_C1, *h_C2, *cpuResult;
h_A = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_B = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C1 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C2 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
cpuResult = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
h_A[i * N + j] = 1;
h_B[i * N + j] = 2;
h_C1[i * N + j] = 0;
h_C2[i * N + j] = 0;
cpuResult[i * N + j] = 0;
}
}
cpumatMul(h_A, h_B, cpuResult);
uint64_t *d_A, *d_B, *d_C1, *d_C2;
status = cudaMalloc((void**)&d_A, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_B, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_C1, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_C2, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMemcpy(d_A, h_A, SIZE * sizeof(uint64_t), cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMemcpy(d_B, h_B, SIZE * sizeof(uint64_t), cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
dim3 blocksPerGrid(1);
dim3 threadsPerBlock(1);
cudaEventRecord(start, 0);
kernel1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C1);
cudaEventRecord(end, 0);
float kernel_time;
cudaEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 1 time (ms): " << kernel_time << "\n";
cudaMemcpy(h_C1, d_C1, SIZE * sizeof(uint64_t), cudaMemcpyDeviceToHost);
cudaEventRecord(start, 0);
kernel2<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C2);
cudaEventRecord(end, 0);
cudaEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 2 time (ms): " << kernel_time << "\n";
cudaMemcpy(h_C2, d_C2, SIZE * sizeof(uint64_t), cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C1);
cudaFree(d_C2);
free(h_A);
free(h_B);
check_result(h_C1, cpuResult);
check_result(h_C2, cpuResult);
free(cpuResult);
free(h_C1);
free(h_C2);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z7kernel2PmS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1PmS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p4.cu -o assignment5-p4
#include <cmath>
#include <cuda.h>
#include <iostream>
const uint64_t N = (1 << 10);
using namespace std;
__global__ void kernel1(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__global__ void kernel2(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__host__ void cpumatMul(uint64_t* A, uint64_t* B, uint64_t* C) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
float sum = 0.0;
for (uint64_t k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = sum;
}
}
}
__host__ void check_result(uint64_t* w_ref, uint64_t* w_opt) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
if (w_ref[i * N + j] != w_opt[i * N + j]) {
cout << "Difference found\n";
exit(EXIT_FAILURE);
}
}
}
cout << "No differences found between base and test versions\n";
}
int main() {
int SIZE = N * N;
cudaError_t status;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
uint64_t *h_A, *h_B, *h_C1, *h_C2, *cpuResult;
h_A = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_B = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C1 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C2 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
cpuResult = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
h_A[i * N + j] = 1;
h_B[i * N + j] = 2;
h_C1[i * N + j] = 0;
h_C2[i * N + j] = 0;
cpuResult[i * N + j] = 0;
}
}
cpumatMul(h_A, h_B, cpuResult);
uint64_t *d_A, *d_B, *d_C1, *d_C2;
status = cudaMalloc((void**)&d_A, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_B, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_C1, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_C2, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMemcpy(d_A, h_A, SIZE * sizeof(uint64_t), cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMemcpy(d_B, h_B, SIZE * sizeof(uint64_t), cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
dim3 blocksPerGrid(1);
dim3 threadsPerBlock(1);
cudaEventRecord(start, 0);
kernel1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C1);
cudaEventRecord(end, 0);
float kernel_time;
cudaEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 1 time (ms): " << kernel_time << "\n";
cudaMemcpy(h_C1, d_C1, SIZE * sizeof(uint64_t), cudaMemcpyDeviceToHost);
cudaEventRecord(start, 0);
kernel2<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C2);
cudaEventRecord(end, 0);
cudaEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 2 time (ms): " << kernel_time << "\n";
cudaMemcpy(h_C2, d_C2, SIZE * sizeof(uint64_t), cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C1);
cudaFree(d_C2);
free(h_A);
free(h_B);
check_result(h_C1, cpuResult);
check_result(h_C2, cpuResult);
free(cpuResult);
free(h_C1);
free(h_C2);
return EXIT_SUCCESS;
} | .file "tmpxft_0004b677_00000000-6_template_p4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpumatMulPmS_S_
.type _Z9cpumatMulPmS_S_, @function
_Z9cpumatMulPmS_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movl $0, %ebx
movss .LC1(%rip), %xmm2
movabsq $-9223372036854775808, %r11
jmp .L4
.L5:
movq %rax, %rsi
shrq %rsi
andl $1, %eax
orq %rax, %rsi
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
addss %xmm0, %xmm0
.L6:
addss %xmm0, %xmm1
addq $8, %rcx
addq $8192, %rdx
cmpq %rdi, %rdx
je .L15
.L7:
movq (%rcx), %rax
imulq (%rdx), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L6
.L15:
comiss .LC1(%rip), %xmm1
jnb .L8
cvttss2siq %xmm1, %rax
movq %rax, (%r9,%r8,8)
.L9:
addq $1, %r8
addq $8, %rdi
cmpq $1024, %r8
je .L10
.L12:
leaq -8388608(%rdi), %rdx
movq %r10, %rcx
pxor %xmm1, %xmm1
jmp .L7
.L8:
subss %xmm2, %xmm1
cvttss2siq %xmm1, %rax
movq %rax, (%r9,%r8,8)
xorq %r11, (%r9,%r8,8)
jmp .L9
.L10:
addq $1024, %rbx
cmpq $1048576, %rbx
je .L3
.L4:
leaq 8388608(%r12), %rdi
leaq 0(,%rbx,8), %r9
leaq 0(%r13,%r9), %r10
addq %rbp, %r9
movl $0, %r8d
jmp .L12
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z9cpumatMulPmS_S_, .-_Z9cpumatMulPmS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Difference found\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "No differences found between base and test versions\n"
.text
.globl _Z12check_resultPmS_
.type _Z12check_resultPmS_, @function
_Z12check_resultPmS_:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rcx
movl $0, %esi
movl $8192, %edx
jmp .L17
.L23:
movl $17, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edi
call exit@PLT
.L24:
addq $8192, %rdx
addq $1024, %rsi
cmpq $1048576, %rsi
je .L20
.L17:
leaq 0(,%rsi,8), %rax
.L19:
movq (%rcx,%rax), %r8
cmpq %r8, (%rdi,%rax)
jne .L23
addq $8, %rax
cmpq %rdx, %rax
jne .L19
jmp .L24
.L20:
movl $52, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z12check_resultPmS_, .-_Z12check_resultPmS_
.globl _Z30__device_stub__Z7kernel1PmS_S_PmS_S_
.type _Z30__device_stub__Z7kernel1PmS_S_PmS_S_, @function
_Z30__device_stub__Z7kernel1PmS_S_PmS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel1PmS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z7kernel1PmS_S_PmS_S_, .-_Z30__device_stub__Z7kernel1PmS_S_PmS_S_
.globl _Z7kernel1PmS_S_
.type _Z7kernel1PmS_S_, @function
_Z7kernel1PmS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7kernel1PmS_S_PmS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z7kernel1PmS_S_, .-_Z7kernel1PmS_S_
.globl _Z30__device_stub__Z7kernel2PmS_S_PmS_S_
.type _Z30__device_stub__Z7kernel2PmS_S_PmS_S_, @function
_Z30__device_stub__Z7kernel2PmS_S_PmS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel2PmS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z30__device_stub__Z7kernel2PmS_S_PmS_S_, .-_Z30__device_stub__Z7kernel2PmS_S_PmS_S_
.globl _Z7kernel2PmS_S_
.type _Z7kernel2PmS_S_, @function
_Z7kernel2PmS_S_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7kernel2PmS_S_PmS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z7kernel2PmS_S_, .-_Z7kernel2PmS_S_
.section .rodata.str1.1
.LC4:
.string "Kernel 1 time (ms): "
.LC5:
.string "\n"
.LC6:
.string "Kernel 2 time (ms): "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $8388608, %edi
call malloc@PLT
movq %rax, %r14
movl $8388608, %edi
call malloc@PLT
movq %rax, %r13
movl $8388608, %edi
call malloc@PLT
movq %rax, %r12
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbp
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movl $8192, %edx
movl $0, %ecx
.L42:
leaq 0(,%rcx,8), %rax
.L43:
movq $1, (%r14,%rax)
movq $2, 0(%r13,%rax)
movq $0, (%r12,%rax)
movq $0, 0(%rbp,%rax)
movq $0, (%rbx,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L43
addq $1024, %rcx
addq $8192, %rdx
cmpq $1048576, %rcx
jne .L42
movq %rbx, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z9cpumatMulPmS_S_
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L56
.L45:
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L57
.L46:
leaq 48(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L58
.L47:
leaq 56(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L59
.L48:
movl $1, %ecx
movl $8388608, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L60
.L49:
movl $1, %ecx
movl $8388608, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L61
.L50:
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L51:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $8388608, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L52:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $8388608, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rsi
movq %r12, %rdi
call _Z12check_resultPmS_
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12check_resultPmS_
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L45
.L57:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L58:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L47
.L59:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L48
.L60:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L61:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L50
.L62:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z7kernel1PmS_S_PmS_S_
jmp .L51
.L63:
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z7kernel2PmS_S_PmS_S_
jmp .L52
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7kernel2PmS_S_"
.LC8:
.string "_Z7kernel1PmS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PmS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PmS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1593835520
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p4.cu -o assignment5-p4
#include <cmath>
#include <cuda.h>
#include <iostream>
const uint64_t N = (1 << 10);
using namespace std;
__global__ void kernel1(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__global__ void kernel2(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__host__ void cpumatMul(uint64_t* A, uint64_t* B, uint64_t* C) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
float sum = 0.0;
for (uint64_t k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = sum;
}
}
}
__host__ void check_result(uint64_t* w_ref, uint64_t* w_opt) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
if (w_ref[i * N + j] != w_opt[i * N + j]) {
cout << "Difference found\n";
exit(EXIT_FAILURE);
}
}
}
cout << "No differences found between base and test versions\n";
}
int main() {
int SIZE = N * N;
cudaError_t status;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
uint64_t *h_A, *h_B, *h_C1, *h_C2, *cpuResult;
h_A = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_B = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C1 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C2 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
cpuResult = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
h_A[i * N + j] = 1;
h_B[i * N + j] = 2;
h_C1[i * N + j] = 0;
h_C2[i * N + j] = 0;
cpuResult[i * N + j] = 0;
}
}
cpumatMul(h_A, h_B, cpuResult);
uint64_t *d_A, *d_B, *d_C1, *d_C2;
status = cudaMalloc((void**)&d_A, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_B, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_C1, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMalloc((void**)&d_C2, SIZE * sizeof(uint64_t));
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMemcpy(d_A, h_A, SIZE * sizeof(uint64_t), cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
status = cudaMemcpy(d_B, h_B, SIZE * sizeof(uint64_t), cudaMemcpyHostToDevice);
if (status != cudaSuccess) {
cerr << cudaGetErrorString(status) << endl;
}
dim3 blocksPerGrid(1);
dim3 threadsPerBlock(1);
cudaEventRecord(start, 0);
kernel1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C1);
cudaEventRecord(end, 0);
float kernel_time;
cudaEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 1 time (ms): " << kernel_time << "\n";
cudaMemcpy(h_C1, d_C1, SIZE * sizeof(uint64_t), cudaMemcpyDeviceToHost);
cudaEventRecord(start, 0);
kernel2<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C2);
cudaEventRecord(end, 0);
cudaEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 2 time (ms): " << kernel_time << "\n";
cudaMemcpy(h_C2, d_C2, SIZE * sizeof(uint64_t), cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C1);
cudaFree(d_C2);
free(h_A);
free(h_B);
check_result(h_C1, cpuResult);
check_result(h_C2, cpuResult);
free(cpuResult);
free(h_C1);
free(h_C2);
return EXIT_SUCCESS;
} | // Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p4.cu -o assignment5-p4
#include <cmath>
#include <hip/hip_runtime.h>
#include <iostream>
const uint64_t N = (1 << 10);
using namespace std;
__global__ void kernel1(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__global__ void kernel2(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__host__ void cpumatMul(uint64_t* A, uint64_t* B, uint64_t* C) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
float sum = 0.0;
for (uint64_t k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = sum;
}
}
}
__host__ void check_result(uint64_t* w_ref, uint64_t* w_opt) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
if (w_ref[i * N + j] != w_opt[i * N + j]) {
cout << "Difference found\n";
exit(EXIT_FAILURE);
}
}
}
cout << "No differences found between base and test versions\n";
}
int main() {
int SIZE = N * N;
hipError_t status;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
uint64_t *h_A, *h_B, *h_C1, *h_C2, *cpuResult;
h_A = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_B = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C1 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C2 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
cpuResult = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
h_A[i * N + j] = 1;
h_B[i * N + j] = 2;
h_C1[i * N + j] = 0;
h_C2[i * N + j] = 0;
cpuResult[i * N + j] = 0;
}
}
cpumatMul(h_A, h_B, cpuResult);
uint64_t *d_A, *d_B, *d_C1, *d_C2;
status = hipMalloc((void**)&d_A, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_B, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_C1, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_C2, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMemcpy(d_A, h_A, SIZE * sizeof(uint64_t), hipMemcpyHostToDevice);
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMemcpy(d_B, h_B, SIZE * sizeof(uint64_t), hipMemcpyHostToDevice);
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
dim3 blocksPerGrid(1);
dim3 threadsPerBlock(1);
hipEventRecord(start, 0);
kernel1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C1);
hipEventRecord(end, 0);
float kernel_time;
hipEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 1 time (ms): " << kernel_time << "\n";
hipMemcpy(h_C1, d_C1, SIZE * sizeof(uint64_t), hipMemcpyDeviceToHost);
hipEventRecord(start, 0);
kernel2<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C2);
hipEventRecord(end, 0);
hipEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 2 time (ms): " << kernel_time << "\n";
hipMemcpy(h_C2, d_C2, SIZE * sizeof(uint64_t), hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C1);
hipFree(d_C2);
free(h_A);
free(h_B);
check_result(h_C1, cpuResult);
check_result(h_C2, cpuResult);
free(cpuResult);
free(h_C1);
free(h_C2);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p4.cu -o assignment5-p4
#include <cmath>
#include <hip/hip_runtime.h>
#include <iostream>
const uint64_t N = (1 << 10);
using namespace std;
__global__ void kernel1(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__global__ void kernel2(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__host__ void cpumatMul(uint64_t* A, uint64_t* B, uint64_t* C) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
float sum = 0.0;
for (uint64_t k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = sum;
}
}
}
__host__ void check_result(uint64_t* w_ref, uint64_t* w_opt) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
if (w_ref[i * N + j] != w_opt[i * N + j]) {
cout << "Difference found\n";
exit(EXIT_FAILURE);
}
}
}
cout << "No differences found between base and test versions\n";
}
int main() {
int SIZE = N * N;
hipError_t status;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
uint64_t *h_A, *h_B, *h_C1, *h_C2, *cpuResult;
h_A = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_B = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C1 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C2 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
cpuResult = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
h_A[i * N + j] = 1;
h_B[i * N + j] = 2;
h_C1[i * N + j] = 0;
h_C2[i * N + j] = 0;
cpuResult[i * N + j] = 0;
}
}
cpumatMul(h_A, h_B, cpuResult);
uint64_t *d_A, *d_B, *d_C1, *d_C2;
status = hipMalloc((void**)&d_A, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_B, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_C1, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_C2, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMemcpy(d_A, h_A, SIZE * sizeof(uint64_t), hipMemcpyHostToDevice);
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMemcpy(d_B, h_B, SIZE * sizeof(uint64_t), hipMemcpyHostToDevice);
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
dim3 blocksPerGrid(1);
dim3 threadsPerBlock(1);
hipEventRecord(start, 0);
kernel1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C1);
hipEventRecord(end, 0);
float kernel_time;
hipEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 1 time (ms): " << kernel_time << "\n";
hipMemcpy(h_C1, d_C1, SIZE * sizeof(uint64_t), hipMemcpyDeviceToHost);
hipEventRecord(start, 0);
kernel2<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C2);
hipEventRecord(end, 0);
hipEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 2 time (ms): " << kernel_time << "\n";
hipMemcpy(h_C2, d_C2, SIZE * sizeof(uint64_t), hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C1);
hipFree(d_C2);
free(h_A);
free(h_B);
check_result(h_C1, cpuResult);
check_result(h_C2, cpuResult);
free(cpuResult);
free(h_C1);
free(h_C2);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PmS_S_
.globl _Z7kernel1PmS_S_
.p2align 8
.type _Z7kernel1PmS_S_,@function
_Z7kernel1PmS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PmS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PmS_S_, .Lfunc_end0-_Z7kernel1PmS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2PmS_S_
.globl _Z7kernel2PmS_S_
.p2align 8
.type _Z7kernel2PmS_S_,@function
_Z7kernel2PmS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PmS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2PmS_S_, .Lfunc_end1-_Z7kernel2PmS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PmS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7kernel1PmS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PmS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7kernel2PmS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p4.cu -o assignment5-p4
#include <cmath>
#include <hip/hip_runtime.h>
#include <iostream>
const uint64_t N = (1 << 10);
using namespace std;
__global__ void kernel1(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__global__ void kernel2(uint64_t* A, uint64_t* B, uint64_t* C) {
// SB: Write your code here
}
__host__ void cpumatMul(uint64_t* A, uint64_t* B, uint64_t* C) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
float sum = 0.0;
for (uint64_t k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = sum;
}
}
}
__host__ void check_result(uint64_t* w_ref, uint64_t* w_opt) {
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
if (w_ref[i * N + j] != w_opt[i * N + j]) {
cout << "Difference found\n";
exit(EXIT_FAILURE);
}
}
}
cout << "No differences found between base and test versions\n";
}
int main() {
int SIZE = N * N;
hipError_t status;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
uint64_t *h_A, *h_B, *h_C1, *h_C2, *cpuResult;
h_A = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_B = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C1 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
h_C2 = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
cpuResult = (uint64_t*)malloc(SIZE * sizeof(uint64_t));
for (uint64_t i = 0; i < N; i++) {
for (uint64_t j = 0; j < N; j++) {
h_A[i * N + j] = 1;
h_B[i * N + j] = 2;
h_C1[i * N + j] = 0;
h_C2[i * N + j] = 0;
cpuResult[i * N + j] = 0;
}
}
cpumatMul(h_A, h_B, cpuResult);
uint64_t *d_A, *d_B, *d_C1, *d_C2;
status = hipMalloc((void**)&d_A, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_B, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_C1, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMalloc((void**)&d_C2, SIZE * sizeof(uint64_t));
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMemcpy(d_A, h_A, SIZE * sizeof(uint64_t), hipMemcpyHostToDevice);
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
status = hipMemcpy(d_B, h_B, SIZE * sizeof(uint64_t), hipMemcpyHostToDevice);
if (status != hipSuccess) {
cerr << hipGetErrorString(status) << endl;
}
dim3 blocksPerGrid(1);
dim3 threadsPerBlock(1);
hipEventRecord(start, 0);
kernel1<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C1);
hipEventRecord(end, 0);
float kernel_time;
hipEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 1 time (ms): " << kernel_time << "\n";
hipMemcpy(h_C1, d_C1, SIZE * sizeof(uint64_t), hipMemcpyDeviceToHost);
hipEventRecord(start, 0);
kernel2<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C2);
hipEventRecord(end, 0);
hipEventElapsedTime(&kernel_time, start, end);
std::cout << "Kernel 2 time (ms): " << kernel_time << "\n";
hipMemcpy(h_C2, d_C2, SIZE * sizeof(uint64_t), hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C1);
hipFree(d_C2);
free(h_A);
free(h_B);
check_result(h_C1, cpuResult);
check_result(h_C2, cpuResult);
free(cpuResult);
free(h_C1);
free(h_C2);
return EXIT_SUCCESS;
} | .text
.file "template_p4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__kernel1PmS_S_ # -- Begin function _Z22__device_stub__kernel1PmS_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PmS_S_,@function
_Z22__device_stub__kernel1PmS_S_: # @_Z22__device_stub__kernel1PmS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel1PmS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PmS_S_, .Lfunc_end0-_Z22__device_stub__kernel1PmS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2PmS_S_ # -- Begin function _Z22__device_stub__kernel2PmS_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PmS_S_,@function
_Z22__device_stub__kernel2PmS_S_: # @_Z22__device_stub__kernel2PmS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel2PmS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2PmS_S_, .Lfunc_end1-_Z22__device_stub__kernel2PmS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9cpumatMulPmS_S_
.LCPI2_0:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl _Z9cpumatMulPmS_S_
.p2align 4, 0x90
.type _Z9cpumatMulPmS_S_,@function
_Z9cpumatMulPmS_S_: # @_Z9cpumatMulPmS_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $8192, %rdi # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
je .LBB2_6
.LBB2_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
movq %rax, %rcx
shlq $13, %rcx
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_2 Depth=2
cvttss2si %xmm1, %r10
movq %r10, %r11
sarq $63, %r11
subss %xmm0, %xmm1
cvttss2si %xmm1, %rbx
andq %r11, %rbx
orq %r10, %rbx
movq %rbx, (%rcx,%r9,8)
incq %r9
addq $8, %r8
cmpq $1024, %r9 # imm = 0x400
je .LBB2_5
.LBB2_2: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorps %xmm1, %xmm1
movq %r8, %r10
xorl %r11d, %r11d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=3
xorps %xmm2, %xmm2
cvtsi2ss %rbx, %xmm2
.LBB2_8: # in Loop: Header=BB2_3 Depth=3
addss %xmm2, %xmm1
incq %r11
addq $8192, %r10 # imm = 0x2000
cmpq $1024, %r11 # imm = 0x400
je .LBB2_9
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movq (%r10), %rbx
imulq (%rdi,%r11,8), %rbx
testq %rbx, %rbx
jns .LBB2_7
# %bb.4: # in Loop: Header=BB2_3 Depth=3
movq %rbx, %r14
shrq %r14
andl $1, %ebx
orq %r14, %rbx
xorps %xmm2, %xmm2
cvtsi2ss %rbx, %xmm2
addss %xmm2, %xmm2
jmp .LBB2_8
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9cpumatMulPmS_S_, .Lfunc_end2-_Z9cpumatMulPmS_S_
.cfi_endproc
# -- End function
.globl _Z12check_resultPmS_ # -- Begin function _Z12check_resultPmS_
.p2align 4, 0x90
.type _Z12check_resultPmS_,@function
_Z12check_resultPmS_: # @_Z12check_resultPmS_
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rdi,%rcx,8), %rdx
cmpq (%rsi,%rcx,8), %rdx
jne .LBB3_6
# %bb.3: # in Loop: Header=BB3_2 Depth=2
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB3_2
# %bb.4: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $8192, %rsi # imm = 0x2000
addq $8192, %rdi # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB3_1
# %bb.5:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $52, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.LBB3_6:
.cfi_def_cfa_offset 16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z12check_resultPmS_, .Lfunc_end3-_Z12check_resultPmS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r12
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r13
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
xorl %ebp, %ebp
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $8388608, %edx # imm = 0x800000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $8388608, %edx # imm = 0x800000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r12, %rax
movq %r13, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movq $1, (%rax,%rdx,8)
movq $2, (%rcx,%rdx,8)
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rbp
addq $8192, %rcx # imm = 0x2000
addq $8192, %rax # imm = 0x2000
cmpq $1024, %rbp # imm = 0x400
jne .LBB4_1
# %bb.4: # %.preheader19.i.preheader
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r12, %rcx
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_5 Depth=1
incq %rax
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
je .LBB4_11
.LBB4_5: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
# Child Loop BB4_7 Depth 3
movq %rax, %rdx
shlq $13, %rdx
addq %r15, %rdx
movq %r13, %rsi
xorl %edi, %edi
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_6 Depth=2
cvttss2si %xmm1, %r8
movq %r8, %r9
sarq $63, %r9
subss %xmm0, %xmm1
cvttss2si %xmm1, %r10
andq %r9, %r10
orq %r8, %r10
movq %r10, (%rdx,%rdi,8)
incq %rdi
addq $8, %rsi
cmpq $1024, %rdi # imm = 0x400
je .LBB4_10
.LBB4_6: # %.preheader.i
# Parent Loop BB4_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_7 Depth 3
xorps %xmm1, %xmm1
movq %rsi, %r8
xorl %r9d, %r9d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_14: # in Loop: Header=BB4_7 Depth=3
xorps %xmm2, %xmm2
cvtsi2ss %r10, %xmm2
.LBB4_15: # in Loop: Header=BB4_7 Depth=3
addss %xmm2, %xmm1
incq %r9
addq $8192, %r8 # imm = 0x2000
cmpq $1024, %r9 # imm = 0x400
je .LBB4_9
.LBB4_7: # Parent Loop BB4_5 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Inner Loop Header: Depth=3
movq (%r8), %r10
imulq (%rcx,%r9,8), %r10
testq %r10, %r10
jns .LBB4_14
# %bb.8: # in Loop: Header=BB4_7 Depth=3
movq %r10, %r11
shrq %r11
andl $1, %r10d
orq %r11, %r10
xorps %xmm2, %xmm2
cvtsi2ss %r10, %xmm2
addss %xmm2, %xmm2
jmp .LBB4_15
.LBB4_11: # %_Z9cpumatMulPmS_S_.exit
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_22
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_13
# %bb.16:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_17
.LBB4_13:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB4_20
# %bb.19:
movzbl 67(%rbp), %eax
jmp .LBB4_21
.LBB4_20:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_22:
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_31
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_24
# %bb.25:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_26
.LBB4_24:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_26: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit89
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i115
cmpb $0, 56(%rbp)
je .LBB4_29
# %bb.28:
movzbl 67(%rbp), %eax
jmp .LBB4_30
.LBB4_29:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit118
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_31:
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_40
# %bb.32:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_33
# %bb.34:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_35
.LBB4_33:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit91
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i120
cmpb $0, 56(%rbp)
je .LBB4_38
# %bb.37:
movzbl 67(%rbp), %eax
jmp .LBB4_39
.LBB4_38:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit123
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_40:
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_49
# %bb.41:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_42
# %bb.43:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_44
.LBB4_42:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit93
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i125
cmpb $0, 56(%rbp)
je .LBB4_47
# %bb.46:
movzbl 67(%rbp), %eax
jmp .LBB4_48
.LBB4_47:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit128
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_49:
movq 16(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_58
# %bb.50:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_51
# %bb.52:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_53
.LBB4_51:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit95
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i130
cmpb $0, 56(%rbp)
je .LBB4_56
# %bb.55:
movzbl 67(%rbp), %eax
jmp .LBB4_57
.LBB4_56:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit133
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_58:
movq 8(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_67
# %bb.59:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_60
# %bb.61:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_62
.LBB4_60:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_62: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit97
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
cmpb $0, 56(%rbp)
je .LBB4_65
# %bb.64:
movzbl 67(%rbp), %eax
jmp .LBB4_66
.LBB4_65:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_66: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit138
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_67:
movabsq $4294967297, %rbp # imm = 0x100000001
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_69
# %bb.68:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7kernel1PmS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_69:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 48(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_71
# %bb.70:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7kernel2PmS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_71:
movq 24(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 40(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbx, %rax
movq %r15, %rcx
.p2align 4, 0x90
.LBB4_72: # %.preheader.i104
# =>This Loop Header: Depth=1
# Child Loop BB4_73 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_73: # Parent Loop BB4_72 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rax,%rdx,8), %rsi
cmpq (%rcx,%rdx,8), %rsi
jne .LBB4_83
# %bb.74: # in Loop: Header=BB4_73 Depth=2
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB4_73
# %bb.75: # in Loop: Header=BB4_72 Depth=1
incq %rbp
addq $8192, %rcx # imm = 0x2000
addq $8192, %rax # imm = 0x2000
cmpq $1024, %rbp # imm = 0x400
jne .LBB4_72
# %bb.76: # %_Z12check_resultPmS_.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %r14, %rcx
movq %r15, %rdx
.p2align 4, 0x90
.LBB4_77: # %.preheader.i107
# =>This Loop Header: Depth=1
# Child Loop BB4_78 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_78: # Parent Loop BB4_77 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rcx,%rsi,8), %rdi
cmpq (%rdx,%rsi,8), %rdi
jne .LBB4_83
# %bb.79: # in Loop: Header=BB4_78 Depth=2
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_78
# %bb.80: # in Loop: Header=BB4_77 Depth=1
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB4_77
# %bb.81: # %_Z12check_resultPmS_.exit113
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_83:
.cfi_def_cfa_offset 208
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $1, %edi
callq exit
.LBB4_82:
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PmS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PmS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1PmS_S_,@object # @_Z7kernel1PmS_S_
.section .rodata,"a",@progbits
.globl _Z7kernel1PmS_S_
.p2align 3, 0x0
_Z7kernel1PmS_S_:
.quad _Z22__device_stub__kernel1PmS_S_
.size _Z7kernel1PmS_S_, 8
.type _Z7kernel2PmS_S_,@object # @_Z7kernel2PmS_S_
.globl _Z7kernel2PmS_S_
.p2align 3, 0x0
_Z7kernel2PmS_S_:
.quad _Z22__device_stub__kernel2PmS_S_
.size _Z7kernel2PmS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Difference found\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "No differences found between base and test versions\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel 1 time (ms): "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel 2 time (ms): "
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1PmS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2PmS_S_"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PmS_S_
.addrsig_sym _Z22__device_stub__kernel2PmS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1PmS_S_
.addrsig_sym _Z7kernel2PmS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel2PmS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1PmS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PmS_S_
.globl _Z7kernel1PmS_S_
.p2align 8
.type _Z7kernel1PmS_S_,@function
_Z7kernel1PmS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PmS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PmS_S_, .Lfunc_end0-_Z7kernel1PmS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2PmS_S_
.globl _Z7kernel2PmS_S_
.p2align 8
.type _Z7kernel2PmS_S_,@function
_Z7kernel2PmS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PmS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2PmS_S_, .Lfunc_end1-_Z7kernel2PmS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PmS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7kernel1PmS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PmS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7kernel2PmS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b677_00000000-6_template_p4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpumatMulPmS_S_
.type _Z9cpumatMulPmS_S_, @function
_Z9cpumatMulPmS_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movl $0, %ebx
movss .LC1(%rip), %xmm2
movabsq $-9223372036854775808, %r11
jmp .L4
.L5:
movq %rax, %rsi
shrq %rsi
andl $1, %eax
orq %rax, %rsi
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
addss %xmm0, %xmm0
.L6:
addss %xmm0, %xmm1
addq $8, %rcx
addq $8192, %rdx
cmpq %rdi, %rdx
je .L15
.L7:
movq (%rcx), %rax
imulq (%rdx), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L6
.L15:
comiss .LC1(%rip), %xmm1
jnb .L8
cvttss2siq %xmm1, %rax
movq %rax, (%r9,%r8,8)
.L9:
addq $1, %r8
addq $8, %rdi
cmpq $1024, %r8
je .L10
.L12:
leaq -8388608(%rdi), %rdx
movq %r10, %rcx
pxor %xmm1, %xmm1
jmp .L7
.L8:
subss %xmm2, %xmm1
cvttss2siq %xmm1, %rax
movq %rax, (%r9,%r8,8)
xorq %r11, (%r9,%r8,8)
jmp .L9
.L10:
addq $1024, %rbx
cmpq $1048576, %rbx
je .L3
.L4:
leaq 8388608(%r12), %rdi
leaq 0(,%rbx,8), %r9
leaq 0(%r13,%r9), %r10
addq %rbp, %r9
movl $0, %r8d
jmp .L12
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z9cpumatMulPmS_S_, .-_Z9cpumatMulPmS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Difference found\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "No differences found between base and test versions\n"
.text
.globl _Z12check_resultPmS_
.type _Z12check_resultPmS_, @function
_Z12check_resultPmS_:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rcx
movl $0, %esi
movl $8192, %edx
jmp .L17
.L23:
movl $17, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edi
call exit@PLT
.L24:
addq $8192, %rdx
addq $1024, %rsi
cmpq $1048576, %rsi
je .L20
.L17:
leaq 0(,%rsi,8), %rax
.L19:
movq (%rcx,%rax), %r8
cmpq %r8, (%rdi,%rax)
jne .L23
addq $8, %rax
cmpq %rdx, %rax
jne .L19
jmp .L24
.L20:
movl $52, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z12check_resultPmS_, .-_Z12check_resultPmS_
.globl _Z30__device_stub__Z7kernel1PmS_S_PmS_S_
.type _Z30__device_stub__Z7kernel1PmS_S_PmS_S_, @function
_Z30__device_stub__Z7kernel1PmS_S_PmS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel1PmS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z7kernel1PmS_S_PmS_S_, .-_Z30__device_stub__Z7kernel1PmS_S_PmS_S_
.globl _Z7kernel1PmS_S_
.type _Z7kernel1PmS_S_, @function
_Z7kernel1PmS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7kernel1PmS_S_PmS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z7kernel1PmS_S_, .-_Z7kernel1PmS_S_
.globl _Z30__device_stub__Z7kernel2PmS_S_PmS_S_
.type _Z30__device_stub__Z7kernel2PmS_S_PmS_S_, @function
_Z30__device_stub__Z7kernel2PmS_S_PmS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel2PmS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z30__device_stub__Z7kernel2PmS_S_PmS_S_, .-_Z30__device_stub__Z7kernel2PmS_S_PmS_S_
.globl _Z7kernel2PmS_S_
.type _Z7kernel2PmS_S_, @function
_Z7kernel2PmS_S_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7kernel2PmS_S_PmS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z7kernel2PmS_S_, .-_Z7kernel2PmS_S_
.section .rodata.str1.1
.LC4:
.string "Kernel 1 time (ms): "
.LC5:
.string "\n"
.LC6:
.string "Kernel 2 time (ms): "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $8388608, %edi
call malloc@PLT
movq %rax, %r14
movl $8388608, %edi
call malloc@PLT
movq %rax, %r13
movl $8388608, %edi
call malloc@PLT
movq %rax, %r12
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbp
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movl $8192, %edx
movl $0, %ecx
.L42:
leaq 0(,%rcx,8), %rax
.L43:
movq $1, (%r14,%rax)
movq $2, 0(%r13,%rax)
movq $0, (%r12,%rax)
movq $0, 0(%rbp,%rax)
movq $0, (%rbx,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L43
addq $1024, %rcx
addq $8192, %rdx
cmpq $1048576, %rcx
jne .L42
movq %rbx, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z9cpumatMulPmS_S_
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L56
.L45:
leaq 40(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L57
.L46:
leaq 48(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L58
.L47:
leaq 56(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L59
.L48:
movl $1, %ecx
movl $8388608, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L60
.L49:
movl $1, %ecx
movl $8388608, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L61
.L50:
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L51:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $8388608, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L52:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $8388608, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rsi
movq %r12, %rdi
call _Z12check_resultPmS_
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12check_resultPmS_
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L45
.L57:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L46
.L58:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L47
.L59:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L48
.L60:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L49
.L61:
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L50
.L62:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z7kernel1PmS_S_PmS_S_
jmp .L51
.L63:
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z7kernel2PmS_S_PmS_S_
jmp .L52
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7kernel2PmS_S_"
.LC8:
.string "_Z7kernel1PmS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PmS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PmS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1593835520
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "template_p4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__kernel1PmS_S_ # -- Begin function _Z22__device_stub__kernel1PmS_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PmS_S_,@function
_Z22__device_stub__kernel1PmS_S_: # @_Z22__device_stub__kernel1PmS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel1PmS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PmS_S_, .Lfunc_end0-_Z22__device_stub__kernel1PmS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2PmS_S_ # -- Begin function _Z22__device_stub__kernel2PmS_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PmS_S_,@function
_Z22__device_stub__kernel2PmS_S_: # @_Z22__device_stub__kernel2PmS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel2PmS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2PmS_S_, .Lfunc_end1-_Z22__device_stub__kernel2PmS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9cpumatMulPmS_S_
.LCPI2_0:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl _Z9cpumatMulPmS_S_
.p2align 4, 0x90
.type _Z9cpumatMulPmS_S_,@function
_Z9cpumatMulPmS_S_: # @_Z9cpumatMulPmS_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $8192, %rdi # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
je .LBB2_6
.LBB2_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
movq %rax, %rcx
shlq $13, %rcx
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_2 Depth=2
cvttss2si %xmm1, %r10
movq %r10, %r11
sarq $63, %r11
subss %xmm0, %xmm1
cvttss2si %xmm1, %rbx
andq %r11, %rbx
orq %r10, %rbx
movq %rbx, (%rcx,%r9,8)
incq %r9
addq $8, %r8
cmpq $1024, %r9 # imm = 0x400
je .LBB2_5
.LBB2_2: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorps %xmm1, %xmm1
movq %r8, %r10
xorl %r11d, %r11d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=3
xorps %xmm2, %xmm2
cvtsi2ss %rbx, %xmm2
.LBB2_8: # in Loop: Header=BB2_3 Depth=3
addss %xmm2, %xmm1
incq %r11
addq $8192, %r10 # imm = 0x2000
cmpq $1024, %r11 # imm = 0x400
je .LBB2_9
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movq (%r10), %rbx
imulq (%rdi,%r11,8), %rbx
testq %rbx, %rbx
jns .LBB2_7
# %bb.4: # in Loop: Header=BB2_3 Depth=3
movq %rbx, %r14
shrq %r14
andl $1, %ebx
orq %r14, %rbx
xorps %xmm2, %xmm2
cvtsi2ss %rbx, %xmm2
addss %xmm2, %xmm2
jmp .LBB2_8
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9cpumatMulPmS_S_, .Lfunc_end2-_Z9cpumatMulPmS_S_
.cfi_endproc
# -- End function
.globl _Z12check_resultPmS_ # -- Begin function _Z12check_resultPmS_
.p2align 4, 0x90
.type _Z12check_resultPmS_,@function
_Z12check_resultPmS_: # @_Z12check_resultPmS_
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rdi,%rcx,8), %rdx
cmpq (%rsi,%rcx,8), %rdx
jne .LBB3_6
# %bb.3: # in Loop: Header=BB3_2 Depth=2
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB3_2
# %bb.4: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $8192, %rsi # imm = 0x2000
addq $8192, %rdi # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB3_1
# %bb.5:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $52, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.LBB3_6:
.cfi_def_cfa_offset 16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z12check_resultPmS_, .Lfunc_end3-_Z12check_resultPmS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r12
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r13
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r14
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %r15
xorl %ebp, %ebp
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $8388608, %edx # imm = 0x800000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $8388608, %edx # imm = 0x800000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r12, %rax
movq %r13, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movq $1, (%rax,%rdx,8)
movq $2, (%rcx,%rdx,8)
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rbp
addq $8192, %rcx # imm = 0x2000
addq $8192, %rax # imm = 0x2000
cmpq $1024, %rbp # imm = 0x400
jne .LBB4_1
# %bb.4: # %.preheader19.i.preheader
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r12, %rcx
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_5 Depth=1
incq %rax
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
je .LBB4_11
.LBB4_5: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
# Child Loop BB4_7 Depth 3
movq %rax, %rdx
shlq $13, %rdx
addq %r15, %rdx
movq %r13, %rsi
xorl %edi, %edi
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_6 Depth=2
cvttss2si %xmm1, %r8
movq %r8, %r9
sarq $63, %r9
subss %xmm0, %xmm1
cvttss2si %xmm1, %r10
andq %r9, %r10
orq %r8, %r10
movq %r10, (%rdx,%rdi,8)
incq %rdi
addq $8, %rsi
cmpq $1024, %rdi # imm = 0x400
je .LBB4_10
.LBB4_6: # %.preheader.i
# Parent Loop BB4_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_7 Depth 3
xorps %xmm1, %xmm1
movq %rsi, %r8
xorl %r9d, %r9d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_14: # in Loop: Header=BB4_7 Depth=3
xorps %xmm2, %xmm2
cvtsi2ss %r10, %xmm2
.LBB4_15: # in Loop: Header=BB4_7 Depth=3
addss %xmm2, %xmm1
incq %r9
addq $8192, %r8 # imm = 0x2000
cmpq $1024, %r9 # imm = 0x400
je .LBB4_9
.LBB4_7: # Parent Loop BB4_5 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Inner Loop Header: Depth=3
movq (%r8), %r10
imulq (%rcx,%r9,8), %r10
testq %r10, %r10
jns .LBB4_14
# %bb.8: # in Loop: Header=BB4_7 Depth=3
movq %r10, %r11
shrq %r11
andl $1, %r10d
orq %r11, %r10
xorps %xmm2, %xmm2
cvtsi2ss %r10, %xmm2
addss %xmm2, %xmm2
jmp .LBB4_15
.LBB4_11: # %_Z9cpumatMulPmS_S_.exit
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_22
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_13
# %bb.16:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_17
.LBB4_13:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB4_20
# %bb.19:
movzbl 67(%rbp), %eax
jmp .LBB4_21
.LBB4_20:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_22:
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_31
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_24
# %bb.25:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_26
.LBB4_24:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_26: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit89
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i115
cmpb $0, 56(%rbp)
je .LBB4_29
# %bb.28:
movzbl 67(%rbp), %eax
jmp .LBB4_30
.LBB4_29:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit118
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_31:
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_40
# %bb.32:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_33
# %bb.34:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_35
.LBB4_33:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit91
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i120
cmpb $0, 56(%rbp)
je .LBB4_38
# %bb.37:
movzbl 67(%rbp), %eax
jmp .LBB4_39
.LBB4_38:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit123
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_40:
leaq 40(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
testl %eax, %eax
je .LBB4_49
# %bb.41:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_42
# %bb.43:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_44
.LBB4_42:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit93
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i125
cmpb $0, 56(%rbp)
je .LBB4_47
# %bb.46:
movzbl 67(%rbp), %eax
jmp .LBB4_48
.LBB4_47:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit128
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_49:
movq 16(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_58
# %bb.50:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_51
# %bb.52:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_53
.LBB4_51:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit95
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i130
cmpb $0, 56(%rbp)
je .LBB4_56
# %bb.55:
movzbl 67(%rbp), %eax
jmp .LBB4_57
.LBB4_56:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit133
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_58:
movq 8(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB4_67
# %bb.59:
movl %eax, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB4_60
# %bb.61:
movq %rax, %rdi
movq %rax, %rbp
callq strlen
movl $_ZSt4cerr, %edi
movq %rbp, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_62
.LBB4_60:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB4_62: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit97
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbp
testq %rbp, %rbp
je .LBB4_82
# %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
cmpb $0, 56(%rbp)
je .LBB4_65
# %bb.64:
movzbl 67(%rbp), %eax
jmp .LBB4_66
.LBB4_65:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_66: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit138
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB4_67:
movabsq $4294967297, %rbp # imm = 0x100000001
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_69
# %bb.68:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7kernel1PmS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_69:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 48(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_71
# %bb.70:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7kernel2PmS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_71:
movq 24(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 40(%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbx, %rax
movq %r15, %rcx
.p2align 4, 0x90
.LBB4_72: # %.preheader.i104
# =>This Loop Header: Depth=1
# Child Loop BB4_73 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_73: # Parent Loop BB4_72 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rax,%rdx,8), %rsi
cmpq (%rcx,%rdx,8), %rsi
jne .LBB4_83
# %bb.74: # in Loop: Header=BB4_73 Depth=2
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB4_73
# %bb.75: # in Loop: Header=BB4_72 Depth=1
incq %rbp
addq $8192, %rcx # imm = 0x2000
addq $8192, %rax # imm = 0x2000
cmpq $1024, %rbp # imm = 0x400
jne .LBB4_72
# %bb.76: # %_Z12check_resultPmS_.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %r14, %rcx
movq %r15, %rdx
.p2align 4, 0x90
.LBB4_77: # %.preheader.i107
# =>This Loop Header: Depth=1
# Child Loop BB4_78 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_78: # Parent Loop BB4_77 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rcx,%rsi,8), %rdi
cmpq (%rdx,%rsi,8), %rdi
jne .LBB4_83
# %bb.79: # in Loop: Header=BB4_78 Depth=2
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_78
# %bb.80: # in Loop: Header=BB4_77 Depth=1
incq %rax
addq $8192, %rdx # imm = 0x2000
addq $8192, %rcx # imm = 0x2000
cmpq $1024, %rax # imm = 0x400
jne .LBB4_77
# %bb.81: # %_Z12check_resultPmS_.exit113
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_83:
.cfi_def_cfa_offset 208
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $1, %edi
callq exit
.LBB4_82:
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PmS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PmS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1PmS_S_,@object # @_Z7kernel1PmS_S_
.section .rodata,"a",@progbits
.globl _Z7kernel1PmS_S_
.p2align 3, 0x0
_Z7kernel1PmS_S_:
.quad _Z22__device_stub__kernel1PmS_S_
.size _Z7kernel1PmS_S_, 8
.type _Z7kernel2PmS_S_,@object # @_Z7kernel2PmS_S_
.globl _Z7kernel2PmS_S_
.p2align 3, 0x0
_Z7kernel2PmS_S_:
.quad _Z22__device_stub__kernel2PmS_S_
.size _Z7kernel2PmS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Difference found\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "No differences found between base and test versions\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel 1 time (ms): "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel 2 time (ms): "
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1PmS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2PmS_S_"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PmS_S_
.addrsig_sym _Z22__device_stub__kernel2PmS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1PmS_S_
.addrsig_sym _Z7kernel2PmS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <stdio.h>
#include <thrust/copy.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
struct GpuTimer {
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer() {
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer() {
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start() {
cudaEventRecord(start, 0);
cudaEventSynchronize(start);
}
void Stop() { cudaEventRecord(stop, 0); }
float Elapsed() {
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void printArray(const uint32_t *a, int n) {
for (int i = 0; i < n; i++)
printf("%2i ", a[i]);
printf("\n");
}
void sortByThrust(const uint32_t *in, int n, uint32_t *out, int nBits) {
thrust::device_vector<uint32_t> dv_out(in, in + n);
thrust::sort(dv_out.begin(), dv_out.end());
thrust::copy(dv_out.begin(), dv_out.end(), out);
}
// Sequential radix sort (paper)
// scan in counting sort Assume: nBits (k in slides) in {1, 2, 4, 8, 16} Why
// "int * blockSizes"? Because we may want different block sizes for diffrent
// kernels:
// blockSizes[0] for the histogram kernel
// blockSizes[1] for the scan kernel
void sortByHost(const uint32_t *in, int n, uint32_t *out, int nBits,
int *blockSizes) {
// TODO
const int nBins = 1 << nBits;
const dim3 histBlockSize = dim3(blockSizes[0]);
const int histBlockCount = (n - 1) / histBlockSize.x + 1;
const dim3 histGridSize = dim3(histBlockCount);
// Not use
// const dim3 scanBlockSize = dim3(blockSizes[1]);
// const int scanBlockCount = (nBins * histBlockCount - 1) / scanBlockSize.x +
// 1; const dim3 scanGridSize = dim3(scanBlockCount);
uint32_t *hist =
(uint32_t *)malloc(nBins * histGridSize.x * sizeof(uint32_t));
uint32_t *histScan =
(uint32_t *)malloc(nBins * histGridSize.x * sizeof(uint32_t));
uint32_t *src = (uint32_t *)malloc(n * sizeof(uint32_t));
memcpy(src, in, n * sizeof(uint32_t));
uint32_t *originalSrc = src; // Use originalSrc to free memory later
uint32_t *dst = out;
/* GpuTimer timer; */
for (int bit = 0; bit < 8 * sizeof(uint32_t); bit += nBits) {
/* printf("#%d (iteration):\n", bit / nBits + 1); */
// Step 1: Calculate local histogram of each block
/* printf(" + Step 1. Local histogram. "); */
/* timer.Start(); */
memset(hist, 0, nBins * histGridSize.x * sizeof(uint32_t));
for (int blockIndex = 0; blockIndex < histGridSize.x; blockIndex++) {
for (int threadIndex = 0; threadIndex < histBlockSize.x; threadIndex++) {
int index_data = blockIndex * histBlockSize.x + threadIndex;
if (index_data < n) {
int bin = (src[index_data] >> bit) & (nBins - 1);
hist[blockIndex * nBins + bin]++;
}
}
}
/* timer.Stop(); */
/* printf("Time: %.3f ms\n", timer.Elapsed()); */
// Step 2: Scan (exclusive) "hist"
/* printf(" + Step 2. Exclusive scan. "); */
/* timer.Start(); */
int pre = 0;
for (int bin = 0; bin < nBins; bin++) {
for (int blockIndex = 0; blockIndex < histGridSize.x; blockIndex++) {
histScan[blockIndex * nBins + bin] = pre;
pre = pre + hist[blockIndex * nBins + bin];
}
}
/* timer.Stop(); */
/* printf("Time: %.3f ms\n", timer.Elapsed()); */
// Step 3: Scatter
/* printf(" + Step 3. Scatter. "); */
/* timer.Start(); */
for (int blockIndex = 0; blockIndex < histGridSize.x; blockIndex++) {
for (int threadIndex = 0; threadIndex < histBlockSize.x; threadIndex++) {
int index_data = blockIndex * histBlockSize.x + threadIndex;
if (index_data < n) {
int bin =
blockIndex * nBins + ((src[index_data] >> bit) & (nBins - 1));
dst[histScan[bin]] = src[index_data];
histScan[bin]++;
}
}
}
/* timer.Stop(); */
/* printf("Time: %.3f ms\n", timer.Elapsed()); */
// Swap "src" and "dst"
uint32_t *tmp = src;
src = dst;
dst = tmp;
}
// Copy result to "out"
memcpy(out, src, n * sizeof(uint32_t));
// Free memories
free(hist);
free(histScan);
free(originalSrc);
}
// Radix sort
void sort(const uint32_t *in, int n, uint32_t *out, int nBits,
bool useThrust = false, int *blockSizes = NULL) {
GpuTimer timer;
timer.Start();
if (useThrust == false) {
printf("\nRadix sort by thrust\n");
sortByThrust(in, n, out, nBits);
} else // use device
{
printf("\nRadix sort by host (#paper: sequential radix sort)\n");
sortByHost(in, n, out, nBits, blockSizes);
}
timer.Stop();
printf("Time: %.3f ms\n", timer.Elapsed());
}
void printDeviceInfo() {
cudaDeviceProp devProv;
CHECK(cudaGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name);
printf("Compute capability: %d.%d\n", devProv.major, devProv.minor);
printf("Num SMs: %d\n", devProv.multiProcessorCount);
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor);
printf("Max num warps per SM: %d\n",
devProv.maxThreadsPerMultiProcessor / devProv.warpSize);
printf("GMEM: %zu byte\n", devProv.totalGlobalMem);
printf("SMEM per SM: %zu byte\n", devProv.sharedMemPerMultiprocessor);
printf("SMEM per block: %zu byte\n", devProv.sharedMemPerBlock);
printf("****************************\n");
}
void checkCorrectness(uint32_t *out, uint32_t *correctOut, int n) {
for (int i = 0; i < n; i++) {
if (out[i] != correctOut[i]) {
printf("INCORRECT :(\n");
return;
}
}
printf("CORRECT :)\n");
}
int main(int argc, char **argv) {
// PRINT OUT DEVICE INFO
printDeviceInfo();
// SET UP INPUT SIZE
int n = (1 << 24) + 1;
// int n = 10;
/* n = 17; */
printf("\nInput size: %d\n", n);
// ALLOCATE MEMORIES
size_t bytes = n * sizeof(uint32_t);
uint32_t *in = (uint32_t *)malloc(bytes);
uint32_t *out = (uint32_t *)malloc(bytes); // Device result
uint32_t *correctOut = (uint32_t *)malloc(bytes); // Thrust result
// SET UP INPUT DATA
for (int i = 0; i < n; i++)
in[i] = rand();
/* in[i] = rand() % 16; */
// SET UP NBITS
int nBits = 4; // Default
if (argc > 1)
nBits = atoi(argv[1]);
printf("\nNum bits per digit: %d\n", nBits);
// DETERMINE BLOCK SIZES
int blockSizes[2] = {512, 512}; // One for histogram, one for scan
if (argc == 4) {
blockSizes[0] = atoi(argv[2]);
blockSizes[1] = atoi(argv[3]);
}
printf("\nHist block size: %d, scan block size: %d\n", blockSizes[0],
blockSizes[1]);
// SORT BY THRUST
sort(in, n, correctOut, nBits);
// SORT BY DEVICE
sort(in, n, out, nBits, true, blockSizes);
checkCorrectness(out, correctOut, n);
// FREE MEMORIES
free(in);
free(out);
free(correctOut);
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <thrust/copy.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
struct GpuTimer {
hipEvent_t start;
hipEvent_t stop;
GpuTimer() {
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer() {
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start() {
hipEventRecord(start, 0);
hipEventSynchronize(start);
}
void Stop() { hipEventRecord(stop, 0); }
float Elapsed() {
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
void printArray(const uint32_t *a, int n) {
for (int i = 0; i < n; i++)
printf("%2i ", a[i]);
printf("\n");
}
void sortByThrust(const uint32_t *in, int n, uint32_t *out, int nBits) {
thrust::device_vector<uint32_t> dv_out(in, in + n);
thrust::sort(dv_out.begin(), dv_out.end());
thrust::copy(dv_out.begin(), dv_out.end(), out);
}
// Sequential radix sort (paper)
// scan in counting sort Assume: nBits (k in slides) in {1, 2, 4, 8, 16} Why
// "int * blockSizes"? Because we may want different block sizes for diffrent
// kernels:
// blockSizes[0] for the histogram kernel
// blockSizes[1] for the scan kernel
void sortByHost(const uint32_t *in, int n, uint32_t *out, int nBits,
int *blockSizes) {
// TODO
const int nBins = 1 << nBits;
const dim3 histBlockSize = dim3(blockSizes[0]);
const int histBlockCount = (n - 1) / histBlockSize.x + 1;
const dim3 histGridSize = dim3(histBlockCount);
// Not use
// const dim3 scanBlockSize = dim3(blockSizes[1]);
// const int scanBlockCount = (nBins * histBlockCount - 1) / scanBlockSize.x +
// 1; const dim3 scanGridSize = dim3(scanBlockCount);
uint32_t *hist =
(uint32_t *)malloc(nBins * histGridSize.x * sizeof(uint32_t));
uint32_t *histScan =
(uint32_t *)malloc(nBins * histGridSize.x * sizeof(uint32_t));
uint32_t *src = (uint32_t *)malloc(n * sizeof(uint32_t));
memcpy(src, in, n * sizeof(uint32_t));
uint32_t *originalSrc = src; // Use originalSrc to free memory later
uint32_t *dst = out;
/* GpuTimer timer; */
for (int bit = 0; bit < 8 * sizeof(uint32_t); bit += nBits) {
/* printf("#%d (iteration):\n", bit / nBits + 1); */
// Step 1: Calculate local histogram of each block
/* printf(" + Step 1. Local histogram. "); */
/* timer.Start(); */
memset(hist, 0, nBins * histGridSize.x * sizeof(uint32_t));
for (int blockIndex = 0; blockIndex < histGridSize.x; blockIndex++) {
for (int threadIndex = 0; threadIndex < histBlockSize.x; threadIndex++) {
int index_data = blockIndex * histBlockSize.x + threadIndex;
if (index_data < n) {
int bin = (src[index_data] >> bit) & (nBins - 1);
hist[blockIndex * nBins + bin]++;
}
}
}
/* timer.Stop(); */
/* printf("Time: %.3f ms\n", timer.Elapsed()); */
// Step 2: Scan (exclusive) "hist"
/* printf(" + Step 2. Exclusive scan. "); */
/* timer.Start(); */
int pre = 0;
for (int bin = 0; bin < nBins; bin++) {
for (int blockIndex = 0; blockIndex < histGridSize.x; blockIndex++) {
histScan[blockIndex * nBins + bin] = pre;
pre = pre + hist[blockIndex * nBins + bin];
}
}
/* timer.Stop(); */
/* printf("Time: %.3f ms\n", timer.Elapsed()); */
// Step 3: Scatter
/* printf(" + Step 3. Scatter. "); */
/* timer.Start(); */
for (int blockIndex = 0; blockIndex < histGridSize.x; blockIndex++) {
for (int threadIndex = 0; threadIndex < histBlockSize.x; threadIndex++) {
int index_data = blockIndex * histBlockSize.x + threadIndex;
if (index_data < n) {
int bin =
blockIndex * nBins + ((src[index_data] >> bit) & (nBins - 1));
dst[histScan[bin]] = src[index_data];
histScan[bin]++;
}
}
}
/* timer.Stop(); */
/* printf("Time: %.3f ms\n", timer.Elapsed()); */
// Swap "src" and "dst"
uint32_t *tmp = src;
src = dst;
dst = tmp;
}
// Copy result to "out"
memcpy(out, src, n * sizeof(uint32_t));
// Free memories
free(hist);
free(histScan);
free(originalSrc);
}
// Radix sort
void sort(const uint32_t *in, int n, uint32_t *out, int nBits,
bool useThrust = false, int *blockSizes = NULL) {
GpuTimer timer;
timer.Start();
if (useThrust == false) {
printf("\nRadix sort by thrust\n");
sortByThrust(in, n, out, nBits);
} else // use device
{
printf("\nRadix sort by host (#paper: sequential radix sort)\n");
sortByHost(in, n, out, nBits, blockSizes);
}
timer.Stop();
printf("Time: %.3f ms\n", timer.Elapsed());
}
void printDeviceInfo() {
hipDeviceProp_t devProv;
CHECK(hipGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name);
printf("Compute capability: %d.%d\n", devProv.major, devProv.minor);
printf("Num SMs: %d\n", devProv.multiProcessorCount);
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor);
printf("Max num warps per SM: %d\n",
devProv.maxThreadsPerMultiProcessor / devProv.warpSize);
printf("GMEM: %zu byte\n", devProv.totalGlobalMem);
printf("SMEM per SM: %zu byte\n", devProv.sharedMemPerMultiprocessor);
printf("SMEM per block: %zu byte\n", devProv.sharedMemPerBlock);
printf("****************************\n");
}
void checkCorrectness(uint32_t *out, uint32_t *correctOut, int n) {
for (int i = 0; i < n; i++) {
if (out[i] != correctOut[i]) {
printf("INCORRECT :(\n");
return;
}
}
printf("CORRECT :)\n");
}
int main(int argc, char **argv) {
// PRINT OUT DEVICE INFO
printDeviceInfo();
// SET UP INPUT SIZE
int n = (1 << 24) + 1;
// int n = 10;
/* n = 17; */
printf("\nInput size: %d\n", n);
// ALLOCATE MEMORIES
size_t bytes = n * sizeof(uint32_t);
uint32_t *in = (uint32_t *)malloc(bytes);
uint32_t *out = (uint32_t *)malloc(bytes); // Device result
uint32_t *correctOut = (uint32_t *)malloc(bytes); // Thrust result
// SET UP INPUT DATA
for (int i = 0; i < n; i++)
in[i] = rand();
/* in[i] = rand() % 16; */
// SET UP NBITS
int nBits = 4; // Default
if (argc > 1)
nBits = atoi(argv[1]);
printf("\nNum bits per digit: %d\n", nBits);
// DETERMINE BLOCK SIZES
int blockSizes[2] = {512, 512}; // One for histogram, one for scan
if (argc == 4) {
blockSizes[0] = atoi(argv[2]);
blockSizes[1] = atoi(argv[3]);
}
printf("\nHist block size: %d, scan block size: %d\n", blockSizes[0],
blockSizes[1]);
// SORT BY THRUST
sort(in, n, correctOut, nBits);
// SORT BY DEVICE
sort(in, n, out, nBits, true, blockSizes);
checkCorrectness(out, correctOut, n);
// FREE MEMORIES
free(in);
free(out);
free(correctOut);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <ctime>
using namespace std;
#define TILE_WIDTH 16
void host_init(float *arr, int n, float init_val){
for (int i=0; i < n; i++)
arr[i] = init_val;
}
void host_matmul(float *h_a, float *h_b, float *h_c, int m, int n, int k){
// h_a (mxk); h_b (kxn); h_c (mxn)
for (int row = 0; row < m; row++){
for (int col = 0; col < n; col++){
float sum = 0;
for (int kk = 0; kk < k; kk++){
float a = h_a[row*k + kk];
float b = h_b[kk*n + col];
sum += a * b;
}
h_c[row*n + col] = sum;
}
}
}
__global__
void cuda_matmul(float *d_a, float *d_b, float *d_c, int m, int n, int k){
__shared__ float shmem_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float shmem_b[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x*blockDim.x + tx;
int row = blockIdx.y*blockDim.y + ty;
float c_val = 0.0;
for (int phase = 0; phase < (k-1)/TILE_WIDTH + 1; phase++){
if (row < m && (tx + phase*TILE_WIDTH) < k)
shmem_a[ty][tx] = d_a[row*k + (tx + phase*TILE_WIDTH)];
else
shmem_a[ty][tx] = 0.0;
if (col < n && ((ty + phase*TILE_WIDTH) < k))
shmem_b[ty][tx] = d_b[(ty + phase*TILE_WIDTH)*n + col];
else
shmem_b[ty][tx] = 0.0;
__syncthreads();
for (int kk = 0; kk < TILE_WIDTH; kk++){
c_val += shmem_a[ty][kk] * shmem_b[kk][tx];
}
__syncthreads();
}
if (col < n and row < m)
d_c[row*n + col] = c_val;
}
void cudaError_check(cudaError_t err, int line){
if (err != cudaSuccess){
printf("GPUassert: %s %s %d\n", cudaGetErrorString(err), __FILE__, line);
exit(EXIT_FAILURE);
}
}
int main(){
float *h_a, *h_b, *h_c, *h_c_cpy;
float *d_a, *d_b, *d_c;
// h_a dimensions = MxK
// h_b dimensions = KxN
// h_c dimensions = MxN
int m = 1024; //
int n = 1024; //
int k = 1024; //
size_t size_ha = k*m*sizeof(float);
size_t size_hb = k*n*sizeof(float);
size_t size_hc = m*n*sizeof(float);
clock_t start, stop;
//################## HOST Start ###################//
h_a = (float*) malloc (size_ha);
h_b = (float*) malloc (size_hb);
h_c = (float*) malloc (size_hc);
h_c_cpy = (float*) malloc (size_hc);
host_init(h_a, k*m, 1);
host_init(h_b, n*k, 2);
host_init(h_c, n*m, 0);
host_init(h_c_cpy, n*m, 0);
start = clock();
host_matmul(h_a, h_b, h_c, m, n, k);
stop = clock();
double cpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## HOST End ###################//
//################## CUDA Start ###################//
cudaError_t err ;
err = cudaMalloc((void **) &d_a, size_ha);
cudaError_check(err, __LINE__);
err = cudaMemcpy(d_a, h_a, size_ha, cudaMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = cudaMalloc((void **) &d_b, size_hb);
cudaError_check(err, __LINE__);
err = cudaMemcpy(d_b, h_b, size_hb, cudaMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = cudaMalloc((void **) &d_c, size_hc);
cudaError_check(err, __LINE__);
//Kernel invocation
int num_threads_per_block = TILE_WIDTH;
dim3 gridDim ((m-1)/num_threads_per_block + 1, (n-1)/num_threads_per_block + 1, 1);
dim3 blockDim (num_threads_per_block, num_threads_per_block, 1);
start = clock();
cuda_matmul<<<gridDim, blockDim>>>(d_a, d_b, d_c, m, n, k);
stop = clock();
err = cudaMemcpy(h_c_cpy, d_c, size_hc, cudaMemcpyDeviceToHost);
cudaError_check(err, __LINE__);
double gpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## CUDA End ###################//
int success = 1;
for (int i = 0; i < n*m; i++){
if (h_c[i] != h_c_cpy[i]){
success = 0;
printf("Failure at idx: %d\n", i);
break;
}
}
if (success == 1)
printf("Success\n");
printf("CPU Duration: %0.3f secs \n", cpu_duration);
printf("GPU Duration: %0.5f secs \n", gpu_duration);
return 1;
} | code for sm_80
Function : _Z11cuda_matmulPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xe, PT ; /* 0xfffffff20400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x180], R2 ; /* 0x00006000030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x17c], R0 ; /* 0x00005f000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000e */
/*0190*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fc400078e10ff */
/*01a0*/ LEA R19, R2, R17, 0x2 ; /* 0x0000001102137211 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x17c], P1 ; /* 0x00005f0000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff199424 */
/* 0x000fe400078e00ff */
/*0230*/ @!P2 MOV R4, R18 ; /* 0x000000120004a202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff05a224 */
/* 0x000fe400078e000f */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x168] ; /* 0x00005a000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x17c], R12 ; /* 0x00005f00050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <ctime>
using namespace std;
#define TILE_WIDTH 16
void host_init(float *arr, int n, float init_val){
for (int i=0; i < n; i++)
arr[i] = init_val;
}
void host_matmul(float *h_a, float *h_b, float *h_c, int m, int n, int k){
// h_a (mxk); h_b (kxn); h_c (mxn)
for (int row = 0; row < m; row++){
for (int col = 0; col < n; col++){
float sum = 0;
for (int kk = 0; kk < k; kk++){
float a = h_a[row*k + kk];
float b = h_b[kk*n + col];
sum += a * b;
}
h_c[row*n + col] = sum;
}
}
}
__global__
void cuda_matmul(float *d_a, float *d_b, float *d_c, int m, int n, int k){
__shared__ float shmem_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float shmem_b[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x*blockDim.x + tx;
int row = blockIdx.y*blockDim.y + ty;
float c_val = 0.0;
for (int phase = 0; phase < (k-1)/TILE_WIDTH + 1; phase++){
if (row < m && (tx + phase*TILE_WIDTH) < k)
shmem_a[ty][tx] = d_a[row*k + (tx + phase*TILE_WIDTH)];
else
shmem_a[ty][tx] = 0.0;
if (col < n && ((ty + phase*TILE_WIDTH) < k))
shmem_b[ty][tx] = d_b[(ty + phase*TILE_WIDTH)*n + col];
else
shmem_b[ty][tx] = 0.0;
__syncthreads();
for (int kk = 0; kk < TILE_WIDTH; kk++){
c_val += shmem_a[ty][kk] * shmem_b[kk][tx];
}
__syncthreads();
}
if (col < n and row < m)
d_c[row*n + col] = c_val;
}
void cudaError_check(cudaError_t err, int line){
if (err != cudaSuccess){
printf("GPUassert: %s %s %d\n", cudaGetErrorString(err), __FILE__, line);
exit(EXIT_FAILURE);
}
}
int main(){
float *h_a, *h_b, *h_c, *h_c_cpy;
float *d_a, *d_b, *d_c;
// h_a dimensions = MxK
// h_b dimensions = KxN
// h_c dimensions = MxN
int m = 1024; //
int n = 1024; //
int k = 1024; //
size_t size_ha = k*m*sizeof(float);
size_t size_hb = k*n*sizeof(float);
size_t size_hc = m*n*sizeof(float);
clock_t start, stop;
//################## HOST Start ###################//
h_a = (float*) malloc (size_ha);
h_b = (float*) malloc (size_hb);
h_c = (float*) malloc (size_hc);
h_c_cpy = (float*) malloc (size_hc);
host_init(h_a, k*m, 1);
host_init(h_b, n*k, 2);
host_init(h_c, n*m, 0);
host_init(h_c_cpy, n*m, 0);
start = clock();
host_matmul(h_a, h_b, h_c, m, n, k);
stop = clock();
double cpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## HOST End ###################//
//################## CUDA Start ###################//
cudaError_t err ;
err = cudaMalloc((void **) &d_a, size_ha);
cudaError_check(err, __LINE__);
err = cudaMemcpy(d_a, h_a, size_ha, cudaMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = cudaMalloc((void **) &d_b, size_hb);
cudaError_check(err, __LINE__);
err = cudaMemcpy(d_b, h_b, size_hb, cudaMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = cudaMalloc((void **) &d_c, size_hc);
cudaError_check(err, __LINE__);
//Kernel invocation
int num_threads_per_block = TILE_WIDTH;
dim3 gridDim ((m-1)/num_threads_per_block + 1, (n-1)/num_threads_per_block + 1, 1);
dim3 blockDim (num_threads_per_block, num_threads_per_block, 1);
start = clock();
cuda_matmul<<<gridDim, blockDim>>>(d_a, d_b, d_c, m, n, k);
stop = clock();
err = cudaMemcpy(h_c_cpy, d_c, size_hc, cudaMemcpyDeviceToHost);
cudaError_check(err, __LINE__);
double gpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## CUDA End ###################//
int success = 1;
for (int i = 0; i < n*m; i++){
if (h_c[i] != h_c_cpy[i]){
success = 0;
printf("Failure at idx: %d\n", i);
break;
}
}
if (success == 1)
printf("Success\n");
printf("CPU Duration: %0.3f secs \n", cpu_duration);
printf("GPU Duration: %0.5f secs \n", gpu_duration);
return 1;
} | .file "tmpxft_00187e72_00000000-6_cuda_tiled_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9host_initPfif
.type _Z9host_initPfif, @function
_Z9host_initPfif:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z9host_initPfif, .-_Z9host_initPfif
.globl _Z11host_matmulPfS_S_iii
.type _Z11host_matmulPfS_S_iii, @function
_Z11host_matmulPfS_S_iii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
testl %ecx, %ecx
jle .L7
movq %rdi, %rbx
movl %r8d, %r13d
movslq %r8d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r14d
movl $0, %r12d
movl $0, %edx
movslq %r9d, %r15
movq %r15, %rcx
jmp .L9
.L10:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L10
.L12:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r10
cmpq %r8, %rbp
je .L17
.L13:
movq %r10, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r9d, %r9d
jg .L10
jmp .L12
.L17:
movl -24(%rsp), %edx
.L11:
addl $1, %edx
addl %r13d, %r12d
addl %r9d, %r14d
cmpl %edx, -20(%rsp)
je .L7
.L9:
testl %r13d, %r13d
jle .L11
movq -16(%rsp), %r10
movslq %r14d, %rax
leaq (%rbx,%rax,4), %r15
addq %rcx, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -8(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L13
.L7:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11host_matmulPfS_S_iii, .-_Z11host_matmulPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sandeep-skb/cuda_programs/master/cuda_tiled_matmul.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z15cudaError_check9cudaErrori
.type _Z15cudaError_check9cudaErrori, @function
_Z15cudaError_check9cudaErrori:
.LFB3671:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L25
ret
.L25:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z15cudaError_check9cudaErrori, .-_Z15cudaError_check9cudaErrori
.globl _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
.type _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii, @function
_Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11cuda_matmulPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii, .-_Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
.globl _Z11cuda_matmulPfS_S_iii
.type _Z11cuda_matmulPfS_S_iii, @function
_Z11cuda_matmulPfS_S_iii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z11cuda_matmulPfS_S_iii, .-_Z11cuda_matmulPfS_S_iii
.section .rodata.str1.1
.LC6:
.string "Failure at idx: %d\n"
.LC7:
.string "Success\n"
.LC8:
.string "CPU Duration: %0.3f secs \n"
.LC9:
.string "GPU Duration: %0.5f secs \n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movss .LC3(%rip), %xmm0
movl $1048576, %esi
movq %r13, %rdi
call _Z9host_initPfif
movss .LC4(%rip), %xmm0
movl $1048576, %esi
movq %r12, %rdi
call _Z9host_initPfif
pxor %xmm0, %xmm0
movl $1048576, %esi
movq %rbp, %rdi
call _Z9host_initPfif
pxor %xmm0, %xmm0
movl $1048576, %esi
movq %rbx, %rdi
call _Z9host_initPfif
call clock@PLT
movq %rax, %r14
movl $1024, %r9d
movl $1024, %r8d
movl $1024, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z11host_matmulPfS_S_iii
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
movq %xmm0, %r14
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $101, %esi
call _Z15cudaError_check9cudaErrori
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $103, %esi
call _Z15cudaError_check9cudaErrori
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $105, %esi
call _Z15cudaError_check9cudaErrori
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $107, %esi
call _Z15cudaError_check9cudaErrori
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $109, %esi
call _Z15cudaError_check9cudaErrori
movl $64, 32(%rsp)
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
call clock@PLT
movq %rax, %r13
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L35:
call clock@PLT
movq %rax, %r12
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $119, %esi
call _Z15cudaError_check9cudaErrori
subq %r13, %r12
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
divsd .LC5(%rip), %xmm0
movq %xmm0, %r12
movl $0, %edx
.L39:
movss 0(%rbp,%rdx,4), %xmm0
ucomiss (%rbx,%rdx,4), %xmm0
jp .L41
jne .L41
addq $1, %rdx
cmpq $1048576, %rdx
jne .L39
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L38
.L44:
movl $1024, %r9d
movl $1024, %r8d
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
jmp .L35
.L41:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L38:
movq %r14, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $1, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z11cuda_matmulPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cuda_matmulPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <ctime>
using namespace std;
#define TILE_WIDTH 16
void host_init(float *arr, int n, float init_val){
for (int i=0; i < n; i++)
arr[i] = init_val;
}
void host_matmul(float *h_a, float *h_b, float *h_c, int m, int n, int k){
// h_a (mxk); h_b (kxn); h_c (mxn)
for (int row = 0; row < m; row++){
for (int col = 0; col < n; col++){
float sum = 0;
for (int kk = 0; kk < k; kk++){
float a = h_a[row*k + kk];
float b = h_b[kk*n + col];
sum += a * b;
}
h_c[row*n + col] = sum;
}
}
}
__global__
void cuda_matmul(float *d_a, float *d_b, float *d_c, int m, int n, int k){
__shared__ float shmem_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float shmem_b[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x*blockDim.x + tx;
int row = blockIdx.y*blockDim.y + ty;
float c_val = 0.0;
for (int phase = 0; phase < (k-1)/TILE_WIDTH + 1; phase++){
if (row < m && (tx + phase*TILE_WIDTH) < k)
shmem_a[ty][tx] = d_a[row*k + (tx + phase*TILE_WIDTH)];
else
shmem_a[ty][tx] = 0.0;
if (col < n && ((ty + phase*TILE_WIDTH) < k))
shmem_b[ty][tx] = d_b[(ty + phase*TILE_WIDTH)*n + col];
else
shmem_b[ty][tx] = 0.0;
__syncthreads();
for (int kk = 0; kk < TILE_WIDTH; kk++){
c_val += shmem_a[ty][kk] * shmem_b[kk][tx];
}
__syncthreads();
}
if (col < n and row < m)
d_c[row*n + col] = c_val;
}
void cudaError_check(cudaError_t err, int line){
if (err != cudaSuccess){
printf("GPUassert: %s %s %d\n", cudaGetErrorString(err), __FILE__, line);
exit(EXIT_FAILURE);
}
}
int main(){
float *h_a, *h_b, *h_c, *h_c_cpy;
float *d_a, *d_b, *d_c;
// h_a dimensions = MxK
// h_b dimensions = KxN
// h_c dimensions = MxN
int m = 1024; //
int n = 1024; //
int k = 1024; //
size_t size_ha = k*m*sizeof(float);
size_t size_hb = k*n*sizeof(float);
size_t size_hc = m*n*sizeof(float);
clock_t start, stop;
//################## HOST Start ###################//
h_a = (float*) malloc (size_ha);
h_b = (float*) malloc (size_hb);
h_c = (float*) malloc (size_hc);
h_c_cpy = (float*) malloc (size_hc);
host_init(h_a, k*m, 1);
host_init(h_b, n*k, 2);
host_init(h_c, n*m, 0);
host_init(h_c_cpy, n*m, 0);
start = clock();
host_matmul(h_a, h_b, h_c, m, n, k);
stop = clock();
double cpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## HOST End ###################//
//################## CUDA Start ###################//
cudaError_t err ;
err = cudaMalloc((void **) &d_a, size_ha);
cudaError_check(err, __LINE__);
err = cudaMemcpy(d_a, h_a, size_ha, cudaMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = cudaMalloc((void **) &d_b, size_hb);
cudaError_check(err, __LINE__);
err = cudaMemcpy(d_b, h_b, size_hb, cudaMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = cudaMalloc((void **) &d_c, size_hc);
cudaError_check(err, __LINE__);
//Kernel invocation
int num_threads_per_block = TILE_WIDTH;
dim3 gridDim ((m-1)/num_threads_per_block + 1, (n-1)/num_threads_per_block + 1, 1);
dim3 blockDim (num_threads_per_block, num_threads_per_block, 1);
start = clock();
cuda_matmul<<<gridDim, blockDim>>>(d_a, d_b, d_c, m, n, k);
stop = clock();
err = cudaMemcpy(h_c_cpy, d_c, size_hc, cudaMemcpyDeviceToHost);
cudaError_check(err, __LINE__);
double gpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## CUDA End ###################//
int success = 1;
for (int i = 0; i < n*m; i++){
if (h_c[i] != h_c_cpy[i]){
success = 0;
printf("Failure at idx: %d\n", i);
break;
}
}
if (success == 1)
printf("Success\n");
printf("CPU Duration: %0.3f secs \n", cpu_duration);
printf("GPU Duration: %0.5f secs \n", gpu_duration);
return 1;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <ctime>
using namespace std;
#define TILE_WIDTH 16
void host_init(float *arr, int n, float init_val){
for (int i=0; i < n; i++)
arr[i] = init_val;
}
void host_matmul(float *h_a, float *h_b, float *h_c, int m, int n, int k){
// h_a (mxk); h_b (kxn); h_c (mxn)
for (int row = 0; row < m; row++){
for (int col = 0; col < n; col++){
float sum = 0;
for (int kk = 0; kk < k; kk++){
float a = h_a[row*k + kk];
float b = h_b[kk*n + col];
sum += a * b;
}
h_c[row*n + col] = sum;
}
}
}
__global__
void cuda_matmul(float *d_a, float *d_b, float *d_c, int m, int n, int k){
__shared__ float shmem_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float shmem_b[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x*blockDim.x + tx;
int row = blockIdx.y*blockDim.y + ty;
float c_val = 0.0;
for (int phase = 0; phase < (k-1)/TILE_WIDTH + 1; phase++){
if (row < m && (tx + phase*TILE_WIDTH) < k)
shmem_a[ty][tx] = d_a[row*k + (tx + phase*TILE_WIDTH)];
else
shmem_a[ty][tx] = 0.0;
if (col < n && ((ty + phase*TILE_WIDTH) < k))
shmem_b[ty][tx] = d_b[(ty + phase*TILE_WIDTH)*n + col];
else
shmem_b[ty][tx] = 0.0;
__syncthreads();
for (int kk = 0; kk < TILE_WIDTH; kk++){
c_val += shmem_a[ty][kk] * shmem_b[kk][tx];
}
__syncthreads();
}
if (col < n and row < m)
d_c[row*n + col] = c_val;
}
void cudaError_check(hipError_t err, int line){
if (err != hipSuccess){
printf("GPUassert: %s %s %d\n", hipGetErrorString(err), __FILE__, line);
exit(EXIT_FAILURE);
}
}
int main(){
float *h_a, *h_b, *h_c, *h_c_cpy;
float *d_a, *d_b, *d_c;
// h_a dimensions = MxK
// h_b dimensions = KxN
// h_c dimensions = MxN
int m = 1024; //
int n = 1024; //
int k = 1024; //
size_t size_ha = k*m*sizeof(float);
size_t size_hb = k*n*sizeof(float);
size_t size_hc = m*n*sizeof(float);
clock_t start, stop;
//################## HOST Start ###################//
h_a = (float*) malloc (size_ha);
h_b = (float*) malloc (size_hb);
h_c = (float*) malloc (size_hc);
h_c_cpy = (float*) malloc (size_hc);
host_init(h_a, k*m, 1);
host_init(h_b, n*k, 2);
host_init(h_c, n*m, 0);
host_init(h_c_cpy, n*m, 0);
start = clock();
host_matmul(h_a, h_b, h_c, m, n, k);
stop = clock();
double cpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## HOST End ###################//
//################## CUDA Start ###################//
hipError_t err ;
err = hipMalloc((void **) &d_a, size_ha);
cudaError_check(err, __LINE__);
err = hipMemcpy(d_a, h_a, size_ha, hipMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = hipMalloc((void **) &d_b, size_hb);
cudaError_check(err, __LINE__);
err = hipMemcpy(d_b, h_b, size_hb, hipMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = hipMalloc((void **) &d_c, size_hc);
cudaError_check(err, __LINE__);
//Kernel invocation
int num_threads_per_block = TILE_WIDTH;
dim3 gridDim ((m-1)/num_threads_per_block + 1, (n-1)/num_threads_per_block + 1, 1);
dim3 blockDim (num_threads_per_block, num_threads_per_block, 1);
start = clock();
cuda_matmul<<<gridDim, blockDim>>>(d_a, d_b, d_c, m, n, k);
stop = clock();
err = hipMemcpy(h_c_cpy, d_c, size_hc, hipMemcpyDeviceToHost);
cudaError_check(err, __LINE__);
double gpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## CUDA End ###################//
int success = 1;
for (int i = 0; i < n*m; i++){
if (h_c[i] != h_c_cpy[i]){
success = 0;
printf("Failure at idx: %d\n", i);
break;
}
}
if (success == 1)
printf("Success\n");
printf("CPU Duration: %0.3f secs \n", cpu_duration);
printf("GPU Duration: %0.5f secs \n", gpu_duration);
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <ctime>
using namespace std;
#define TILE_WIDTH 16
void host_init(float *arr, int n, float init_val){
for (int i=0; i < n; i++)
arr[i] = init_val;
}
void host_matmul(float *h_a, float *h_b, float *h_c, int m, int n, int k){
// h_a (mxk); h_b (kxn); h_c (mxn)
for (int row = 0; row < m; row++){
for (int col = 0; col < n; col++){
float sum = 0;
for (int kk = 0; kk < k; kk++){
float a = h_a[row*k + kk];
float b = h_b[kk*n + col];
sum += a * b;
}
h_c[row*n + col] = sum;
}
}
}
__global__
void cuda_matmul(float *d_a, float *d_b, float *d_c, int m, int n, int k){
__shared__ float shmem_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float shmem_b[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x*blockDim.x + tx;
int row = blockIdx.y*blockDim.y + ty;
float c_val = 0.0;
for (int phase = 0; phase < (k-1)/TILE_WIDTH + 1; phase++){
if (row < m && (tx + phase*TILE_WIDTH) < k)
shmem_a[ty][tx] = d_a[row*k + (tx + phase*TILE_WIDTH)];
else
shmem_a[ty][tx] = 0.0;
if (col < n && ((ty + phase*TILE_WIDTH) < k))
shmem_b[ty][tx] = d_b[(ty + phase*TILE_WIDTH)*n + col];
else
shmem_b[ty][tx] = 0.0;
__syncthreads();
for (int kk = 0; kk < TILE_WIDTH; kk++){
c_val += shmem_a[ty][kk] * shmem_b[kk][tx];
}
__syncthreads();
}
if (col < n and row < m)
d_c[row*n + col] = c_val;
}
void cudaError_check(hipError_t err, int line){
if (err != hipSuccess){
printf("GPUassert: %s %s %d\n", hipGetErrorString(err), __FILE__, line);
exit(EXIT_FAILURE);
}
}
int main(){
float *h_a, *h_b, *h_c, *h_c_cpy;
float *d_a, *d_b, *d_c;
// h_a dimensions = MxK
// h_b dimensions = KxN
// h_c dimensions = MxN
int m = 1024; //
int n = 1024; //
int k = 1024; //
size_t size_ha = k*m*sizeof(float);
size_t size_hb = k*n*sizeof(float);
size_t size_hc = m*n*sizeof(float);
clock_t start, stop;
//################## HOST Start ###################//
h_a = (float*) malloc (size_ha);
h_b = (float*) malloc (size_hb);
h_c = (float*) malloc (size_hc);
h_c_cpy = (float*) malloc (size_hc);
host_init(h_a, k*m, 1);
host_init(h_b, n*k, 2);
host_init(h_c, n*m, 0);
host_init(h_c_cpy, n*m, 0);
start = clock();
host_matmul(h_a, h_b, h_c, m, n, k);
stop = clock();
double cpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## HOST End ###################//
//################## CUDA Start ###################//
hipError_t err ;
err = hipMalloc((void **) &d_a, size_ha);
cudaError_check(err, __LINE__);
err = hipMemcpy(d_a, h_a, size_ha, hipMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = hipMalloc((void **) &d_b, size_hb);
cudaError_check(err, __LINE__);
err = hipMemcpy(d_b, h_b, size_hb, hipMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = hipMalloc((void **) &d_c, size_hc);
cudaError_check(err, __LINE__);
//Kernel invocation
int num_threads_per_block = TILE_WIDTH;
dim3 gridDim ((m-1)/num_threads_per_block + 1, (n-1)/num_threads_per_block + 1, 1);
dim3 blockDim (num_threads_per_block, num_threads_per_block, 1);
start = clock();
cuda_matmul<<<gridDim, blockDim>>>(d_a, d_b, d_c, m, n, k);
stop = clock();
err = hipMemcpy(h_c_cpy, d_c, size_hc, hipMemcpyDeviceToHost);
cudaError_check(err, __LINE__);
double gpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## CUDA End ###################//
int success = 1;
for (int i = 0; i < n*m; i++){
if (h_c[i] != h_c_cpy[i]){
success = 0;
printf("Failure at idx: %d\n", i);
break;
}
}
if (success == 1)
printf("Success\n");
printf("CPU Duration: %0.3f secs \n", cpu_duration);
printf("GPU Duration: %0.5f secs \n", gpu_duration);
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cuda_matmulPfS_S_iii
.globl _Z11cuda_matmulPfS_S_iii
.p2align 8
.type _Z11cuda_matmulPfS_S_iii,@function
_Z11cuda_matmulPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_cmp_lt_i32 s10, -14
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s3, v[4:5]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s3, s10, -1
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v5, 6, v3
s_ashr_i32 s11, s3, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v6, 0x400, v2
s_lshr_b32 s11, s11, 28
v_mul_lo_u32 v8, v0, s10
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s8, v0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, v5, v2
v_cmp_le_i32_e64 s12, s9, v1
v_add_nc_u32_e32 v9, v6, v5
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
v_lshl_add_u32 v11, s14, 4, v4
s_and_not1_b32 s17, s11, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s10, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v7, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v12, s14, 4, v3
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s10, v12
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v12, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v6
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v5
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s9, v1
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cuda_matmulPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cuda_matmulPfS_S_iii, .Lfunc_end0-_Z11cuda_matmulPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cuda_matmulPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11cuda_matmulPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <ctime>
using namespace std;
#define TILE_WIDTH 16
void host_init(float *arr, int n, float init_val){
for (int i=0; i < n; i++)
arr[i] = init_val;
}
void host_matmul(float *h_a, float *h_b, float *h_c, int m, int n, int k){
// h_a (mxk); h_b (kxn); h_c (mxn)
for (int row = 0; row < m; row++){
for (int col = 0; col < n; col++){
float sum = 0;
for (int kk = 0; kk < k; kk++){
float a = h_a[row*k + kk];
float b = h_b[kk*n + col];
sum += a * b;
}
h_c[row*n + col] = sum;
}
}
}
__global__
void cuda_matmul(float *d_a, float *d_b, float *d_c, int m, int n, int k){
__shared__ float shmem_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float shmem_b[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x*blockDim.x + tx;
int row = blockIdx.y*blockDim.y + ty;
float c_val = 0.0;
for (int phase = 0; phase < (k-1)/TILE_WIDTH + 1; phase++){
if (row < m && (tx + phase*TILE_WIDTH) < k)
shmem_a[ty][tx] = d_a[row*k + (tx + phase*TILE_WIDTH)];
else
shmem_a[ty][tx] = 0.0;
if (col < n && ((ty + phase*TILE_WIDTH) < k))
shmem_b[ty][tx] = d_b[(ty + phase*TILE_WIDTH)*n + col];
else
shmem_b[ty][tx] = 0.0;
__syncthreads();
for (int kk = 0; kk < TILE_WIDTH; kk++){
c_val += shmem_a[ty][kk] * shmem_b[kk][tx];
}
__syncthreads();
}
if (col < n and row < m)
d_c[row*n + col] = c_val;
}
void cudaError_check(hipError_t err, int line){
if (err != hipSuccess){
printf("GPUassert: %s %s %d\n", hipGetErrorString(err), __FILE__, line);
exit(EXIT_FAILURE);
}
}
int main(){
float *h_a, *h_b, *h_c, *h_c_cpy;
float *d_a, *d_b, *d_c;
// h_a dimensions = MxK
// h_b dimensions = KxN
// h_c dimensions = MxN
int m = 1024; //
int n = 1024; //
int k = 1024; //
size_t size_ha = k*m*sizeof(float);
size_t size_hb = k*n*sizeof(float);
size_t size_hc = m*n*sizeof(float);
clock_t start, stop;
//################## HOST Start ###################//
h_a = (float*) malloc (size_ha);
h_b = (float*) malloc (size_hb);
h_c = (float*) malloc (size_hc);
h_c_cpy = (float*) malloc (size_hc);
host_init(h_a, k*m, 1);
host_init(h_b, n*k, 2);
host_init(h_c, n*m, 0);
host_init(h_c_cpy, n*m, 0);
start = clock();
host_matmul(h_a, h_b, h_c, m, n, k);
stop = clock();
double cpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## HOST End ###################//
//################## CUDA Start ###################//
hipError_t err ;
err = hipMalloc((void **) &d_a, size_ha);
cudaError_check(err, __LINE__);
err = hipMemcpy(d_a, h_a, size_ha, hipMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = hipMalloc((void **) &d_b, size_hb);
cudaError_check(err, __LINE__);
err = hipMemcpy(d_b, h_b, size_hb, hipMemcpyHostToDevice);
cudaError_check(err, __LINE__);
err = hipMalloc((void **) &d_c, size_hc);
cudaError_check(err, __LINE__);
//Kernel invocation
int num_threads_per_block = TILE_WIDTH;
dim3 gridDim ((m-1)/num_threads_per_block + 1, (n-1)/num_threads_per_block + 1, 1);
dim3 blockDim (num_threads_per_block, num_threads_per_block, 1);
start = clock();
cuda_matmul<<<gridDim, blockDim>>>(d_a, d_b, d_c, m, n, k);
stop = clock();
err = hipMemcpy(h_c_cpy, d_c, size_hc, hipMemcpyDeviceToHost);
cudaError_check(err, __LINE__);
double gpu_duration = (stop - start) / (double) CLOCKS_PER_SEC;
//################## CUDA End ###################//
int success = 1;
for (int i = 0; i < n*m; i++){
if (h_c[i] != h_c_cpy[i]){
success = 0;
printf("Failure at idx: %d\n", i);
break;
}
}
if (success == 1)
printf("Success\n");
printf("CPU Duration: %0.3f secs \n", cpu_duration);
printf("GPU Duration: %0.5f secs \n", gpu_duration);
return 1;
} | .text
.file "cuda_tiled_matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9host_initPfif # -- Begin function _Z9host_initPfif
.p2align 4, 0x90
.type _Z9host_initPfif,@function
_Z9host_initPfif: # @_Z9host_initPfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9host_initPfif, .Lfunc_end0-_Z9host_initPfif
.cfi_endproc
# -- End function
.globl _Z11host_matmulPfS_S_iii # -- Begin function _Z11host_matmulPfS_S_iii
.p2align 4, 0x90
.type _Z11host_matmulPfS_S_iii,@function
_Z11host_matmulPfS_S_iii: # @_Z11host_matmulPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB1_9
# %bb.1: # %.preheader29.lr.ph
movslq %r8d, %rdi
movl %ecx, %ecx
movl %edi, %r10d
movl %r9d, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge33
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %r9d, %r14d
cmpq %rcx, %r15
je .LBB1_9
.LBB1_2: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %r8d, %r8d
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB1_8
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
xorps %xmm0, %xmm0
testl %r9d, %r9d
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
movq %rsi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rdx
addq %rbx, %rbp
cmpq %rdx, %r11
jne .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge35
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11host_matmulPfS_S_iii, .Lfunc_end1-_Z11host_matmulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__cuda_matmulPfS_S_iii # -- Begin function _Z26__device_stub__cuda_matmulPfS_S_iii
.p2align 4, 0x90
.type _Z26__device_stub__cuda_matmulPfS_S_iii,@function
_Z26__device_stub__cuda_matmulPfS_S_iii: # @_Z26__device_stub__cuda_matmulPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11cuda_matmulPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z26__device_stub__cuda_matmulPfS_S_iii, .Lfunc_end2-_Z26__device_stub__cuda_matmulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z15cudaError_check10hipError_ti # -- Begin function _Z15cudaError_check10hipError_ti
.p2align 4, 0x90
.type _Z15cudaError_check10hipError_ti,@function
_Z15cudaError_check10hipError_ti: # @_Z15cudaError_check10hipError_ti
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB3_2
# %bb.1:
retq
.LBB3_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z15cudaError_check10hipError_ti, .Lfunc_end3-_Z15cudaError_check10hipError_ti
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r13
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_1
# %bb.2: # %.lr.ph.i75.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i75
# =>This Inner Loop Header: Depth=1
movl $1073741824, (%r13,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_3
# %bb.4: # %.lr.ph.i80.preheader
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
callq clock
movq %rax, %r15
movq %rbp, %rax
.p2align 4, 0x90
.LBB4_5: # %.preheader29.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
# Child Loop BB4_7 Depth 3
movq %r12, %rcx
shlq $12, %rcx
addq %rbx, %rcx
movq %r13, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_6: # %.preheader.i
# Parent Loop BB4_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_7 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i90
# Parent Loop BB4_5 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB4_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB4_6 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_6
# %bb.9: # %._crit_edge33.i
# in Loop: Header=BB4_5 Depth=1
incq %r12
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB4_5
# %bb.10: # %_Z11host_matmulPfS_S_iii.exit
callq clock
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_11
# %bb.13: # %_Z15cudaError_check10hipError_ti.exit
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z15cudaError_check10hipError_ti.exit95
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z15cudaError_check10hipError_ti.exit97
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z15cudaError_check10hipError_ti.exit99
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z15cudaError_check10hipError_ti.exit101
callq clock
movq %rax, %r13
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $1024, 20(%rsp) # imm = 0x400
movl $1024, 16(%rsp) # imm = 0x400
movl $1024, 12(%rsp) # imm = 0x400
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z11cuda_matmulPfS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
callq clock
movq %rax, %rbp
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_30
# %bb.24: # %_Z15cudaError_check10hipError_ti.exit103.preheader.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_25: # %_Z15cudaError_check10hipError_ti.exit103.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%rsi,4), %xmm0
jne .LBB4_26
jp .LBB4_26
# %bb.27: # %_Z15cudaError_check10hipError_ti.exit103
# in Loop: Header=BB4_25 Depth=1
incq %rsi
cmpq $1048576, %rsi # imm = 0x100000
jne .LBB4_25
# %bb.28: # %.critedge
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB4_29
.LBB4_26:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB4_29:
subq %r13, %rbp
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
subq %r15, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $1, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $103, %ecx
jmp .LBB4_12
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $105, %ecx
jmp .LBB4_12
.LBB4_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $107, %ecx
jmp .LBB4_12
.LBB4_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $109, %ecx
jmp .LBB4_12
.LBB4_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $111, %ecx
jmp .LBB4_12
.LBB4_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $121, %ecx
.LBB4_12:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11cuda_matmulPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11cuda_matmulPfS_S_iii,@object # @_Z11cuda_matmulPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z11cuda_matmulPfS_S_iii
.p2align 3, 0x0
_Z11cuda_matmulPfS_S_iii:
.quad _Z26__device_stub__cuda_matmulPfS_S_iii
.size _Z11cuda_matmulPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPUassert: %s %s %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sandeep-skb/cuda_programs/master/cuda_tiled_matmul.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failure at idx: %d\n"
.size .L.str.2, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU Duration: %0.3f secs \n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU Duration: %0.5f secs \n"
.size .L.str.5, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11cuda_matmulPfS_S_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__cuda_matmulPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11cuda_matmulPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11cuda_matmulPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xe, PT ; /* 0xfffffff20400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x180], R2 ; /* 0x00006000030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x17c], R0 ; /* 0x00005f000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000e */
/*0190*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fc400078e10ff */
/*01a0*/ LEA R19, R2, R17, 0x2 ; /* 0x0000001102137211 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x17c], P1 ; /* 0x00005f0000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R22, RZ ; /* 0x000000ff00167202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff199424 */
/* 0x000fe400078e00ff */
/*0230*/ @!P2 MOV R4, R18 ; /* 0x000000120004a202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P2 IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff05a224 */
/* 0x000fe400078e000f */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x168] ; /* 0x00005a000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x17c], R12 ; /* 0x00005f00050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cuda_matmulPfS_S_iii
.globl _Z11cuda_matmulPfS_S_iii
.p2align 8
.type _Z11cuda_matmulPfS_S_iii,@function
_Z11cuda_matmulPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_cmp_lt_i32 s10, -14
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s3, v[4:5]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s3, s10, -1
v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v5, 6, v3
s_ashr_i32 s11, s3, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v6, 0x400, v2
s_lshr_b32 s11, s11, 28
v_mul_lo_u32 v8, v0, s10
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s8, v0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, v5, v2
v_cmp_le_i32_e64 s12, s9, v1
v_add_nc_u32_e32 v9, v6, v5
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
v_lshl_add_u32 v11, s14, 4, v4
s_and_not1_b32 s17, s11, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s10, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v7, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v12, s14, 4, v3
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s10, v12
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v12, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v6
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v5
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s9, v1
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cuda_matmulPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cuda_matmulPfS_S_iii, .Lfunc_end0-_Z11cuda_matmulPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cuda_matmulPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11cuda_matmulPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187e72_00000000-6_cuda_tiled_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9host_initPfif
.type _Z9host_initPfif, @function
_Z9host_initPfif:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z9host_initPfif, .-_Z9host_initPfif
.globl _Z11host_matmulPfS_S_iii
.type _Z11host_matmulPfS_S_iii, @function
_Z11host_matmulPfS_S_iii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
testl %ecx, %ecx
jle .L7
movq %rdi, %rbx
movl %r8d, %r13d
movslq %r8d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r14d
movl $0, %r12d
movl $0, %edx
movslq %r9d, %r15
movq %r15, %rcx
jmp .L9
.L10:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L10
.L12:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r10
cmpq %r8, %rbp
je .L17
.L13:
movq %r10, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r9d, %r9d
jg .L10
jmp .L12
.L17:
movl -24(%rsp), %edx
.L11:
addl $1, %edx
addl %r13d, %r12d
addl %r9d, %r14d
cmpl %edx, -20(%rsp)
je .L7
.L9:
testl %r13d, %r13d
jle .L11
movq -16(%rsp), %r10
movslq %r14d, %rax
leaq (%rbx,%rax,4), %r15
addq %rcx, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -8(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L13
.L7:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11host_matmulPfS_S_iii, .-_Z11host_matmulPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sandeep-skb/cuda_programs/master/cuda_tiled_matmul.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z15cudaError_check9cudaErrori
.type _Z15cudaError_check9cudaErrori, @function
_Z15cudaError_check9cudaErrori:
.LFB3671:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L25
ret
.L25:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z15cudaError_check9cudaErrori, .-_Z15cudaError_check9cudaErrori
.globl _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
.type _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii, @function
_Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11cuda_matmulPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii, .-_Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
.globl _Z11cuda_matmulPfS_S_iii
.type _Z11cuda_matmulPfS_S_iii, @function
_Z11cuda_matmulPfS_S_iii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z11cuda_matmulPfS_S_iii, .-_Z11cuda_matmulPfS_S_iii
.section .rodata.str1.1
.LC6:
.string "Failure at idx: %d\n"
.LC7:
.string "Success\n"
.LC8:
.string "CPU Duration: %0.3f secs \n"
.LC9:
.string "GPU Duration: %0.5f secs \n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movss .LC3(%rip), %xmm0
movl $1048576, %esi
movq %r13, %rdi
call _Z9host_initPfif
movss .LC4(%rip), %xmm0
movl $1048576, %esi
movq %r12, %rdi
call _Z9host_initPfif
pxor %xmm0, %xmm0
movl $1048576, %esi
movq %rbp, %rdi
call _Z9host_initPfif
pxor %xmm0, %xmm0
movl $1048576, %esi
movq %rbx, %rdi
call _Z9host_initPfif
call clock@PLT
movq %rax, %r14
movl $1024, %r9d
movl $1024, %r8d
movl $1024, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z11host_matmulPfS_S_iii
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
movq %xmm0, %r14
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $101, %esi
call _Z15cudaError_check9cudaErrori
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $103, %esi
call _Z15cudaError_check9cudaErrori
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $105, %esi
call _Z15cudaError_check9cudaErrori
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $107, %esi
call _Z15cudaError_check9cudaErrori
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $109, %esi
call _Z15cudaError_check9cudaErrori
movl $64, 32(%rsp)
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
call clock@PLT
movq %rax, %r13
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L35:
call clock@PLT
movq %rax, %r12
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $119, %esi
call _Z15cudaError_check9cudaErrori
subq %r13, %r12
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
divsd .LC5(%rip), %xmm0
movq %xmm0, %r12
movl $0, %edx
.L39:
movss 0(%rbp,%rdx,4), %xmm0
ucomiss (%rbx,%rdx,4), %xmm0
jp .L41
jne .L41
addq $1, %rdx
cmpq $1048576, %rdx
jne .L39
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L38
.L44:
movl $1024, %r9d
movl $1024, %r8d
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z11cuda_matmulPfS_S_iiiPfS_S_iii
jmp .L35
.L41:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L38:
movq %r14, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $1, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z11cuda_matmulPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cuda_matmulPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_tiled_matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9host_initPfif # -- Begin function _Z9host_initPfif
.p2align 4, 0x90
.type _Z9host_initPfif,@function
_Z9host_initPfif: # @_Z9host_initPfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9host_initPfif, .Lfunc_end0-_Z9host_initPfif
.cfi_endproc
# -- End function
.globl _Z11host_matmulPfS_S_iii # -- Begin function _Z11host_matmulPfS_S_iii
.p2align 4, 0x90
.type _Z11host_matmulPfS_S_iii,@function
_Z11host_matmulPfS_S_iii: # @_Z11host_matmulPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB1_9
# %bb.1: # %.preheader29.lr.ph
movslq %r8d, %rdi
movl %ecx, %ecx
movl %edi, %r10d
movl %r9d, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge33
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %r9d, %r14d
cmpq %rcx, %r15
je .LBB1_9
.LBB1_2: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %r8d, %r8d
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB1_8
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
xorps %xmm0, %xmm0
testl %r9d, %r9d
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
movq %rsi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rdx
addq %rbx, %rbp
cmpq %rdx, %r11
jne .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge35
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11host_matmulPfS_S_iii, .Lfunc_end1-_Z11host_matmulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__cuda_matmulPfS_S_iii # -- Begin function _Z26__device_stub__cuda_matmulPfS_S_iii
.p2align 4, 0x90
.type _Z26__device_stub__cuda_matmulPfS_S_iii,@function
_Z26__device_stub__cuda_matmulPfS_S_iii: # @_Z26__device_stub__cuda_matmulPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11cuda_matmulPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z26__device_stub__cuda_matmulPfS_S_iii, .Lfunc_end2-_Z26__device_stub__cuda_matmulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z15cudaError_check10hipError_ti # -- Begin function _Z15cudaError_check10hipError_ti
.p2align 4, 0x90
.type _Z15cudaError_check10hipError_ti,@function
_Z15cudaError_check10hipError_ti: # @_Z15cudaError_check10hipError_ti
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB3_2
# %bb.1:
retq
.LBB3_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z15cudaError_check10hipError_ti, .Lfunc_end3-_Z15cudaError_check10hipError_ti
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r13
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_1
# %bb.2: # %.lr.ph.i75.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i75
# =>This Inner Loop Header: Depth=1
movl $1073741824, (%r13,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_3
# %bb.4: # %.lr.ph.i80.preheader
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
callq clock
movq %rax, %r15
movq %rbp, %rax
.p2align 4, 0x90
.LBB4_5: # %.preheader29.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
# Child Loop BB4_7 Depth 3
movq %r12, %rcx
shlq $12, %rcx
addq %rbx, %rcx
movq %r13, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_6: # %.preheader.i
# Parent Loop BB4_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_7 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i90
# Parent Loop BB4_5 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB4_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB4_6 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_6
# %bb.9: # %._crit_edge33.i
# in Loop: Header=BB4_5 Depth=1
incq %r12
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB4_5
# %bb.10: # %_Z11host_matmulPfS_S_iii.exit
callq clock
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_11
# %bb.13: # %_Z15cudaError_check10hipError_ti.exit
movq 40(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z15cudaError_check10hipError_ti.exit95
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z15cudaError_check10hipError_ti.exit97
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z15cudaError_check10hipError_ti.exit99
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z15cudaError_check10hipError_ti.exit101
callq clock
movq %rax, %r13
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $1024, 20(%rsp) # imm = 0x400
movl $1024, 16(%rsp) # imm = 0x400
movl $1024, 12(%rsp) # imm = 0x400
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z11cuda_matmulPfS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
callq clock
movq %rax, %rbp
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_30
# %bb.24: # %_Z15cudaError_check10hipError_ti.exit103.preheader.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_25: # %_Z15cudaError_check10hipError_ti.exit103.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r14,%rsi,4), %xmm0
jne .LBB4_26
jp .LBB4_26
# %bb.27: # %_Z15cudaError_check10hipError_ti.exit103
# in Loop: Header=BB4_25 Depth=1
incq %rsi
cmpq $1048576, %rsi # imm = 0x100000
jne .LBB4_25
# %bb.28: # %.critedge
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB4_29
.LBB4_26:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB4_29:
subq %r13, %rbp
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
subq %r15, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $1, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $103, %ecx
jmp .LBB4_12
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $105, %ecx
jmp .LBB4_12
.LBB4_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $107, %ecx
jmp .LBB4_12
.LBB4_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $109, %ecx
jmp .LBB4_12
.LBB4_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $111, %ecx
jmp .LBB4_12
.LBB4_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $121, %ecx
.LBB4_12:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11cuda_matmulPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11cuda_matmulPfS_S_iii,@object # @_Z11cuda_matmulPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z11cuda_matmulPfS_S_iii
.p2align 3, 0x0
_Z11cuda_matmulPfS_S_iii:
.quad _Z26__device_stub__cuda_matmulPfS_S_iii
.size _Z11cuda_matmulPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPUassert: %s %s %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sandeep-skb/cuda_programs/master/cuda_tiled_matmul.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failure at idx: %d\n"
.size .L.str.2, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU Duration: %0.3f secs \n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU Duration: %0.5f secs \n"
.size .L.str.5, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11cuda_matmulPfS_S_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__cuda_matmulPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11cuda_matmulPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/time.h>
#define N 1048576
#define TAMSIMPLESORT 1024
#define TPB 1024
#define DEBUG false
#define PRINTARRAY false
typedef float dato; //Tipo de dato a ordenar
__device__ void simple_sort(dato *data, int left, int right) {
for (int i = left; i <= right; ++i) {
dato min_val = data[i];
int min_idx = i;
// Find the smallest value in the range [left, right].
for (int j = i + 1; j <= right; ++j) {
unsigned val_j = data[j];
if (val_j < min_val) {
min_idx = j;
min_val = val_j;
}
}
// Swap the values.
if (i != min_idx) {
data[min_idx] = data[i];
data[i] = min_val;
}
}
}
__global__ void run_simple_sort(dato * clasificado, int * indices) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int min = thread * TAMSIMPLESORT * 2;
int max = (thread * TAMSIMPLESORT * 2) + indices[thread] - 1;
if (DEBUG) printf("RSS Hilo %d - min:%d - max:%d\n", thread, min, max);
simple_sort(clasificado, min, max);
}
__global__ void clasificar(dato * v, dato * fronteras, int * indices, int bloques, dato * clasificado) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int ind, i;
for (i = 0; i <= bloques; i++) {
if (v[thread] <= fronteras[i]) {
ind = atomicAdd(indices + i, 1);
break;
}
}
clasificado[2 * TAMSIMPLESORT*i + ind] = v[thread];
}
__global__ void rellenarIndFront(dato min, dato paso, int * indices, dato * fronteras) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
indices[thread] = 0;
fronteras[thread] = min + paso*(thread+1);
if (DEBUG) printf("RELLENAR hilo:%d frontera:%f min:%f paso:%f\n", thread, fronteras[thread], min, paso);
}
void runsort(dato * v_H, int l) {
dato * v_D;
cudaMalloc((void **)&v_D, sizeof(dato)*l);
cudaMemcpy(v_D, v_H, sizeof(dato)*l, cudaMemcpyHostToDevice);
dato min = v_H[0];
dato max = v_H[0];
for (int i = 0; i < l; i++) {
if (v_H[i] < min) {
min = v_H[i];
}
if (v_H[i] > max) {
max = v_H[i];
}
}
int bloques = l / TAMSIMPLESORT;
if (l % TAMSIMPLESORT != 0) bloques++;
dato * fronteras;
cudaMalloc((void**)&fronteras, bloques * sizeof(dato));
int * indices;
cudaMalloc((void**)&indices, bloques * sizeof(int));
int cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
int cudathreads = bloques / cudablocks;
if (DEBUG) printf("RUNSORT RELLENAR blocks:%d threads:%d min:%f, max:%f\n", cudablocks, cudathreads, min, max);
rellenarIndFront <<<cudablocks, cudathreads>>> (min, (max-min) / (dato)bloques, indices, fronteras);
cudablocks = l / TPB;
if (l % TPB != 0) cudablocks++;
cudathreads = l / cudablocks;
dato * destino;
cudaMalloc((void**)&destino, l * 2 * sizeof(dato));
clasificar <<<cudablocks, cudathreads >>> (v_D, fronteras, indices, bloques, destino);
cudaFree(v_D);
cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
cudathreads = bloques / cudablocks;
run_simple_sort <<<cudablocks, cudathreads >>> (destino, indices);
int * H_indices = (int *) malloc(sizeof(int)*bloques);
cudaMemcpy(H_indices, indices, sizeof(int)*bloques, cudaMemcpyDeviceToHost);
int offset = 0;
for (int i = 0; i < bloques; i++) {
if (DEBUG) printf("COPY Dest: %d Origen: %d Long: %d\n", offset, i*TAMSIMPLESORT * 2, H_indices[i]+1);
cudaMemcpy(v_H + offset, destino + i*TAMSIMPLESORT * 2, sizeof(dato)*(H_indices[i]+1), cudaMemcpyDeviceToHost);
offset += H_indices[i];
}
if (DEBUG) printf("NUM ELEMENTOS = %d\n", offset);
cudaFree(v_D);
cudaFree(destino);
cudaFree(fronteras);
cudaFree(indices);
}
int main()
{
dato *vector;
vector = (dato *)malloc(N * sizeof(dato));
srand(time(NULL));
for (int i = 0; i<N; i++)
vector[i] = rand();
bool correcto = true;
struct timeval t1, t2;
printf("Ordenando vector de %d elementos...\n", N);
gettimeofday(&t1, 0);
runsort(vector, N);
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Ordenado en %f ms \n", time);
dato aux = 0;
for (int i = 0; i<N; i++) {
if (aux > vector[i]) {
correcto = false;
}
aux = vector[i];
if (PRINTARRAY) printf("%d - %f\n", i, aux);
}
if (correcto) {
printf("El vector se ha ordenado correctamente.\n\n");
}
else {
printf("Ha fallado la ordenacion del vector.\n\n");
}
return 0;
} | .file "tmpxft_00011205_00000000-6_clasificador.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11simple_sortPfii
.type _Z11simple_sortPfii, @function
_Z11simple_sortPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11simple_sortPfii, .-_Z11simple_sortPfii
.globl _Z37__device_stub__Z15run_simple_sortPfPiPfPi
.type _Z37__device_stub__Z15run_simple_sortPfPiPfPi, @function
_Z37__device_stub__Z15run_simple_sortPfPiPfPi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15run_simple_sortPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z15run_simple_sortPfPiPfPi, .-_Z37__device_stub__Z15run_simple_sortPfPiPfPi
.globl _Z15run_simple_sortPfPi
.type _Z15run_simple_sortPfPi, @function
_Z15run_simple_sortPfPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15run_simple_sortPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15run_simple_sortPfPi, .-_Z15run_simple_sortPfPi
.globl _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
.type _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_, @function
_Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10clasificarPfS_PiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_, .-_Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
.globl _Z10clasificarPfS_PiiS_
.type _Z10clasificarPfS_PiiS_, @function
_Z10clasificarPfS_PiiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10clasificarPfS_PiiS_, .-_Z10clasificarPfS_PiiS_
.globl _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
.type _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf, @function
_Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16rellenarIndFrontffPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf, .-_Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
.globl _Z16rellenarIndFrontffPiPf
.type _Z16rellenarIndFrontffPiPf, @function
_Z16rellenarIndFrontffPiPf:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16rellenarIndFrontffPiPf, .-_Z16rellenarIndFrontffPiPf
.globl _Z7runsortPfi
.type _Z7runsortPfi, @function
_Z7runsortPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %esi, %rdx
leaq 0(,%rdx,4), %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movss (%r12), %xmm5
movss %xmm5, 8(%rsp)
testl %ebp, %ebp
jle .L42
movq %r12, %rax
leaq (%rbx,%r12), %rdx
movss %xmm5, 12(%rsp)
.L33:
movss (%rax), %xmm0
movaps %xmm0, %xmm2
minss 8(%rsp), %xmm2
movss %xmm2, 8(%rsp)
maxss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
.L30:
leal 1023(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $10, %ebx
movl %ebp, %eax
andl $1023, %eax
cmpl $1, %eax
sbbl $-1, %ebx
movslq %ebx, %r14
salq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leal 1023(%rbx), %r13d
testl %ebx, %ebx
cmovns %ebx, %r13d
sarl $10, %r13d
movl %ebx, %eax
andl $1023, %eax
cmpl $1, %eax
sbbl $-1, %r13d
movl %ebx, %eax
cltd
idivl %r13d
movl %eax, %r15d
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L36:
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, 8(%rsp)
leal (%rbp,%rbp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L37:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %r15d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r14, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L39
movq %rbp, %rbx
addq %rbp, %r14
movl $0, %r13d
movl $0, %ebp
.L40:
movl (%rbx), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movq %r13, %rsi
addq 40(%rsp), %rsi
movslq %ebp, %rax
leaq (%r12,%rax,4), %rdi
movl $2, %ecx
call cudaMemcpy@PLT
addl (%rbx), %ebp
addq $4, %rbx
addq $8192, %r13
cmpq %r14, %rbx
jne .L40
.L39:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movss 8(%rsp), %xmm7
movss %xmm7, 12(%rsp)
jmp .L30
.L48:
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm6
subss %xmm6, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
divss %xmm0, %xmm1
movaps %xmm6, %xmm0
call _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
jmp .L36
.L49:
movq 40(%rsp), %r8
movl %ebx, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
jmp .L37
.L50:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z37__device_stub__Z15run_simple_sortPfPiPfPi
jmp .L38
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z7runsortPfi, .-_Z7runsortPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Ordenando vector de %d elementos...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Ordenado en %f ms \n"
.section .rodata.str1.8
.align 8
.LC5:
.string "El vector se ha ordenado correctamente.\n\n"
.align 8
.LC6:
.string "Ha fallado la ordenacion del vector.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 4194304(%r13), %r12
movq %r13, %rbp
.L53:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L53
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1048576, %esi
movq %r13, %rdi
call _Z7runsortPfi
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rax
subq (%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
movl $1, %eax
movl $0, %edx
.L55:
movaps %xmm0, %xmm1
movss (%rbx), %xmm0
ucomiss %xmm0, %xmm1
cmova %edx, %eax
addq $4, %rbx
cmpq %r12, %rbx
jne .L55
testb %al, %al
je .L56
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L57:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L57
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z16rellenarIndFrontffPiPf"
.LC8:
.string "_Z10clasificarPfS_PiiS_"
.LC9:
.string "_Z15run_simple_sortPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rellenarIndFrontffPiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10clasificarPfS_PiiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15run_simple_sortPfPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/time.h>
#define N 1048576
#define TAMSIMPLESORT 1024
#define TPB 1024
#define DEBUG false
#define PRINTARRAY false
typedef float dato; //Tipo de dato a ordenar
__device__ void simple_sort(dato *data, int left, int right) {
for (int i = left; i <= right; ++i) {
dato min_val = data[i];
int min_idx = i;
// Find the smallest value in the range [left, right].
for (int j = i + 1; j <= right; ++j) {
unsigned val_j = data[j];
if (val_j < min_val) {
min_idx = j;
min_val = val_j;
}
}
// Swap the values.
if (i != min_idx) {
data[min_idx] = data[i];
data[i] = min_val;
}
}
}
__global__ void run_simple_sort(dato * clasificado, int * indices) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int min = thread * TAMSIMPLESORT * 2;
int max = (thread * TAMSIMPLESORT * 2) + indices[thread] - 1;
if (DEBUG) printf("RSS Hilo %d - min:%d - max:%d\n", thread, min, max);
simple_sort(clasificado, min, max);
}
__global__ void clasificar(dato * v, dato * fronteras, int * indices, int bloques, dato * clasificado) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int ind, i;
for (i = 0; i <= bloques; i++) {
if (v[thread] <= fronteras[i]) {
ind = atomicAdd(indices + i, 1);
break;
}
}
clasificado[2 * TAMSIMPLESORT*i + ind] = v[thread];
}
__global__ void rellenarIndFront(dato min, dato paso, int * indices, dato * fronteras) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
indices[thread] = 0;
fronteras[thread] = min + paso*(thread+1);
if (DEBUG) printf("RELLENAR hilo:%d frontera:%f min:%f paso:%f\n", thread, fronteras[thread], min, paso);
}
void runsort(dato * v_H, int l) {
dato * v_D;
cudaMalloc((void **)&v_D, sizeof(dato)*l);
cudaMemcpy(v_D, v_H, sizeof(dato)*l, cudaMemcpyHostToDevice);
dato min = v_H[0];
dato max = v_H[0];
for (int i = 0; i < l; i++) {
if (v_H[i] < min) {
min = v_H[i];
}
if (v_H[i] > max) {
max = v_H[i];
}
}
int bloques = l / TAMSIMPLESORT;
if (l % TAMSIMPLESORT != 0) bloques++;
dato * fronteras;
cudaMalloc((void**)&fronteras, bloques * sizeof(dato));
int * indices;
cudaMalloc((void**)&indices, bloques * sizeof(int));
int cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
int cudathreads = bloques / cudablocks;
if (DEBUG) printf("RUNSORT RELLENAR blocks:%d threads:%d min:%f, max:%f\n", cudablocks, cudathreads, min, max);
rellenarIndFront <<<cudablocks, cudathreads>>> (min, (max-min) / (dato)bloques, indices, fronteras);
cudablocks = l / TPB;
if (l % TPB != 0) cudablocks++;
cudathreads = l / cudablocks;
dato * destino;
cudaMalloc((void**)&destino, l * 2 * sizeof(dato));
clasificar <<<cudablocks, cudathreads >>> (v_D, fronteras, indices, bloques, destino);
cudaFree(v_D);
cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
cudathreads = bloques / cudablocks;
run_simple_sort <<<cudablocks, cudathreads >>> (destino, indices);
int * H_indices = (int *) malloc(sizeof(int)*bloques);
cudaMemcpy(H_indices, indices, sizeof(int)*bloques, cudaMemcpyDeviceToHost);
int offset = 0;
for (int i = 0; i < bloques; i++) {
if (DEBUG) printf("COPY Dest: %d Origen: %d Long: %d\n", offset, i*TAMSIMPLESORT * 2, H_indices[i]+1);
cudaMemcpy(v_H + offset, destino + i*TAMSIMPLESORT * 2, sizeof(dato)*(H_indices[i]+1), cudaMemcpyDeviceToHost);
offset += H_indices[i];
}
if (DEBUG) printf("NUM ELEMENTOS = %d\n", offset);
cudaFree(v_D);
cudaFree(destino);
cudaFree(fronteras);
cudaFree(indices);
}
int main()
{
dato *vector;
vector = (dato *)malloc(N * sizeof(dato));
srand(time(NULL));
for (int i = 0; i<N; i++)
vector[i] = rand();
bool correcto = true;
struct timeval t1, t2;
printf("Ordenando vector de %d elementos...\n", N);
gettimeofday(&t1, 0);
runsort(vector, N);
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Ordenado en %f ms \n", time);
dato aux = 0;
for (int i = 0; i<N; i++) {
if (aux > vector[i]) {
correcto = false;
}
aux = vector[i];
if (PRINTARRAY) printf("%d - %f\n", i, aux);
}
if (correcto) {
printf("El vector se ha ordenado correctamente.\n\n");
}
else {
printf("Ha fallado la ordenacion del vector.\n\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/time.h>
#define N 1048576
#define TAMSIMPLESORT 1024
#define TPB 1024
#define DEBUG false
#define PRINTARRAY false
typedef float dato; //Tipo de dato a ordenar
__device__ void simple_sort(dato *data, int left, int right) {
for (int i = left; i <= right; ++i) {
dato min_val = data[i];
int min_idx = i;
// Find the smallest value in the range [left, right].
for (int j = i + 1; j <= right; ++j) {
unsigned val_j = data[j];
if (val_j < min_val) {
min_idx = j;
min_val = val_j;
}
}
// Swap the values.
if (i != min_idx) {
data[min_idx] = data[i];
data[i] = min_val;
}
}
}
__global__ void run_simple_sort(dato * clasificado, int * indices) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int min = thread * TAMSIMPLESORT * 2;
int max = (thread * TAMSIMPLESORT * 2) + indices[thread] - 1;
if (DEBUG) printf("RSS Hilo %d - min:%d - max:%d\n", thread, min, max);
simple_sort(clasificado, min, max);
}
__global__ void clasificar(dato * v, dato * fronteras, int * indices, int bloques, dato * clasificado) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int ind, i;
for (i = 0; i <= bloques; i++) {
if (v[thread] <= fronteras[i]) {
ind = atomicAdd(indices + i, 1);
break;
}
}
clasificado[2 * TAMSIMPLESORT*i + ind] = v[thread];
}
__global__ void rellenarIndFront(dato min, dato paso, int * indices, dato * fronteras) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
indices[thread] = 0;
fronteras[thread] = min + paso*(thread+1);
if (DEBUG) printf("RELLENAR hilo:%d frontera:%f min:%f paso:%f\n", thread, fronteras[thread], min, paso);
}
void runsort(dato * v_H, int l) {
dato * v_D;
hipMalloc((void **)&v_D, sizeof(dato)*l);
hipMemcpy(v_D, v_H, sizeof(dato)*l, hipMemcpyHostToDevice);
dato min = v_H[0];
dato max = v_H[0];
for (int i = 0; i < l; i++) {
if (v_H[i] < min) {
min = v_H[i];
}
if (v_H[i] > max) {
max = v_H[i];
}
}
int bloques = l / TAMSIMPLESORT;
if (l % TAMSIMPLESORT != 0) bloques++;
dato * fronteras;
hipMalloc((void**)&fronteras, bloques * sizeof(dato));
int * indices;
hipMalloc((void**)&indices, bloques * sizeof(int));
int cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
int cudathreads = bloques / cudablocks;
if (DEBUG) printf("RUNSORT RELLENAR blocks:%d threads:%d min:%f, max:%f\n", cudablocks, cudathreads, min, max);
rellenarIndFront <<<cudablocks, cudathreads>>> (min, (max-min) / (dato)bloques, indices, fronteras);
cudablocks = l / TPB;
if (l % TPB != 0) cudablocks++;
cudathreads = l / cudablocks;
dato * destino;
hipMalloc((void**)&destino, l * 2 * sizeof(dato));
clasificar <<<cudablocks, cudathreads >>> (v_D, fronteras, indices, bloques, destino);
hipFree(v_D);
cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
cudathreads = bloques / cudablocks;
run_simple_sort <<<cudablocks, cudathreads >>> (destino, indices);
int * H_indices = (int *) malloc(sizeof(int)*bloques);
hipMemcpy(H_indices, indices, sizeof(int)*bloques, hipMemcpyDeviceToHost);
int offset = 0;
for (int i = 0; i < bloques; i++) {
if (DEBUG) printf("COPY Dest: %d Origen: %d Long: %d\n", offset, i*TAMSIMPLESORT * 2, H_indices[i]+1);
hipMemcpy(v_H + offset, destino + i*TAMSIMPLESORT * 2, sizeof(dato)*(H_indices[i]+1), hipMemcpyDeviceToHost);
offset += H_indices[i];
}
if (DEBUG) printf("NUM ELEMENTOS = %d\n", offset);
hipFree(v_D);
hipFree(destino);
hipFree(fronteras);
hipFree(indices);
}
int main()
{
dato *vector;
vector = (dato *)malloc(N * sizeof(dato));
srand(time(NULL));
for (int i = 0; i<N; i++)
vector[i] = rand();
bool correcto = true;
struct timeval t1, t2;
printf("Ordenando vector de %d elementos...\n", N);
gettimeofday(&t1, 0);
runsort(vector, N);
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Ordenado en %f ms \n", time);
dato aux = 0;
for (int i = 0; i<N; i++) {
if (aux > vector[i]) {
correcto = false;
}
aux = vector[i];
if (PRINTARRAY) printf("%d - %f\n", i, aux);
}
if (correcto) {
printf("El vector se ha ordenado correctamente.\n\n");
}
else {
printf("Ha fallado la ordenacion del vector.\n\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/time.h>
#define N 1048576
#define TAMSIMPLESORT 1024
#define TPB 1024
#define DEBUG false
#define PRINTARRAY false
typedef float dato; //Tipo de dato a ordenar
__device__ void simple_sort(dato *data, int left, int right) {
for (int i = left; i <= right; ++i) {
dato min_val = data[i];
int min_idx = i;
// Find the smallest value in the range [left, right].
for (int j = i + 1; j <= right; ++j) {
unsigned val_j = data[j];
if (val_j < min_val) {
min_idx = j;
min_val = val_j;
}
}
// Swap the values.
if (i != min_idx) {
data[min_idx] = data[i];
data[i] = min_val;
}
}
}
__global__ void run_simple_sort(dato * clasificado, int * indices) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int min = thread * TAMSIMPLESORT * 2;
int max = (thread * TAMSIMPLESORT * 2) + indices[thread] - 1;
if (DEBUG) printf("RSS Hilo %d - min:%d - max:%d\n", thread, min, max);
simple_sort(clasificado, min, max);
}
__global__ void clasificar(dato * v, dato * fronteras, int * indices, int bloques, dato * clasificado) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int ind, i;
for (i = 0; i <= bloques; i++) {
if (v[thread] <= fronteras[i]) {
ind = atomicAdd(indices + i, 1);
break;
}
}
clasificado[2 * TAMSIMPLESORT*i + ind] = v[thread];
}
__global__ void rellenarIndFront(dato min, dato paso, int * indices, dato * fronteras) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
indices[thread] = 0;
fronteras[thread] = min + paso*(thread+1);
if (DEBUG) printf("RELLENAR hilo:%d frontera:%f min:%f paso:%f\n", thread, fronteras[thread], min, paso);
}
void runsort(dato * v_H, int l) {
dato * v_D;
hipMalloc((void **)&v_D, sizeof(dato)*l);
hipMemcpy(v_D, v_H, sizeof(dato)*l, hipMemcpyHostToDevice);
dato min = v_H[0];
dato max = v_H[0];
for (int i = 0; i < l; i++) {
if (v_H[i] < min) {
min = v_H[i];
}
if (v_H[i] > max) {
max = v_H[i];
}
}
int bloques = l / TAMSIMPLESORT;
if (l % TAMSIMPLESORT != 0) bloques++;
dato * fronteras;
hipMalloc((void**)&fronteras, bloques * sizeof(dato));
int * indices;
hipMalloc((void**)&indices, bloques * sizeof(int));
int cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
int cudathreads = bloques / cudablocks;
if (DEBUG) printf("RUNSORT RELLENAR blocks:%d threads:%d min:%f, max:%f\n", cudablocks, cudathreads, min, max);
rellenarIndFront <<<cudablocks, cudathreads>>> (min, (max-min) / (dato)bloques, indices, fronteras);
cudablocks = l / TPB;
if (l % TPB != 0) cudablocks++;
cudathreads = l / cudablocks;
dato * destino;
hipMalloc((void**)&destino, l * 2 * sizeof(dato));
clasificar <<<cudablocks, cudathreads >>> (v_D, fronteras, indices, bloques, destino);
hipFree(v_D);
cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
cudathreads = bloques / cudablocks;
run_simple_sort <<<cudablocks, cudathreads >>> (destino, indices);
int * H_indices = (int *) malloc(sizeof(int)*bloques);
hipMemcpy(H_indices, indices, sizeof(int)*bloques, hipMemcpyDeviceToHost);
int offset = 0;
for (int i = 0; i < bloques; i++) {
if (DEBUG) printf("COPY Dest: %d Origen: %d Long: %d\n", offset, i*TAMSIMPLESORT * 2, H_indices[i]+1);
hipMemcpy(v_H + offset, destino + i*TAMSIMPLESORT * 2, sizeof(dato)*(H_indices[i]+1), hipMemcpyDeviceToHost);
offset += H_indices[i];
}
if (DEBUG) printf("NUM ELEMENTOS = %d\n", offset);
hipFree(v_D);
hipFree(destino);
hipFree(fronteras);
hipFree(indices);
}
int main()
{
dato *vector;
vector = (dato *)malloc(N * sizeof(dato));
srand(time(NULL));
for (int i = 0; i<N; i++)
vector[i] = rand();
bool correcto = true;
struct timeval t1, t2;
printf("Ordenando vector de %d elementos...\n", N);
gettimeofday(&t1, 0);
runsort(vector, N);
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Ordenado en %f ms \n", time);
dato aux = 0;
for (int i = 0; i<N; i++) {
if (aux > vector[i]) {
correcto = false;
}
aux = vector[i];
if (PRINTARRAY) printf("%d - %f\n", i, aux);
}
if (correcto) {
printf("El vector se ha ordenado correctamente.\n\n");
}
else {
printf("Ha fallado la ordenacion del vector.\n\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15run_simple_sortPfPi
.globl _Z15run_simple_sortPfPi
.p2align 8
.type _Z15run_simple_sortPfPi,@function
_Z15run_simple_sortPfPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 11, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v8, v0, v2, -1
v_or_b32_e32 v0, 1, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, 1, v2
v_cmp_ge_i32_e32 vcc_lo, v2, v8
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, v1
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, v2
s_mov_b32 s5, exec_lo
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v9, v[3:4], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v1, v9
v_cmpx_lt_i32_e64 v2, v8
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v10, v2
v_mov_b32_e32 v5, v2
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_mov_b32_e32 v1, v9
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
.p2align 6
.LBB0_5:
global_load_b32 v11, v[6:7], off
v_add_nc_u32_e32 v10, 1, v10
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s1, v10, v8
s_or_b32 s6, s1, s6
s_waitcnt vmcnt(0)
v_cvt_u32_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v11, v11
v_cmp_gt_f32_e64 s0, v1, v11
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v1, v1, v11, s0
v_cndmask_b32_e64 v5, v5, v10, s0
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e64 v2, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_store_b32 v[5:6], v9, off
global_store_b32 v[3:4], v1, off
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15run_simple_sortPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15run_simple_sortPfPi, .Lfunc_end0-_Z15run_simple_sortPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10clasificarPfS_PiiS_
.globl _Z10clasificarPfS_PiiS_
.p2align 8
.type _Z10clasificarPfS_PiiS_,@function
_Z10clasificarPfS_PiiS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v5, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lt_i32 s8, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB1_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x8
s_add_i32 s11, s8, 1
s_mov_b32 s15, 0
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s17, exec_lo, s14
v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v6, s15
v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v4, s7
s_or_b32 s10, s17, s10
s_and_not1_b32 s6, s12, exec_lo
s_and_b32 s7, s13, exec_lo
s_mov_b32 s15, s16
s_or_b32 s12, s6, s7
s_mov_b64 s[6:7], s[8:9]
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB1_6
.LBB1_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_or_b32 s13, s13, exec_lo
s_or_b32 s14, s14, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_nge_f32_e32 vcc_lo, s8, v0
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB1_2
s_add_i32 s16, s15, 1
s_add_u32 s8, s6, 4
s_addc_u32 s9, s7, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s11, s16
s_cselect_b32 s18, -1, 0
s_and_not1_b32 s14, s14, exec_lo
s_and_b32 s18, s18, exec_lo
s_and_not1_b32 s13, s13, exec_lo
s_or_b32 s14, s14, s18
s_branch .LBB1_2
.LBB1_5:
s_branch .LBB1_9
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_and_saveexec_b32 s4, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB1_8
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v5, v6
global_atomic_add_u32 v0, v[3:4], v0, off glc
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s4
.LBB1_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v5, 11, v0
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10clasificarPfS_PiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10clasificarPfS_PiiS_, .Lfunc_end1-_Z10clasificarPfS_PiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16rellenarIndFrontffPiPf
.globl _Z16rellenarIndFrontffPiPf
.p2align 8
.type _Z16rellenarIndFrontffPiPf,@function
_Z16rellenarIndFrontffPiPf:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v3, s5, s4
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16rellenarIndFrontffPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16rellenarIndFrontffPiPf, .Lfunc_end2-_Z16rellenarIndFrontffPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15run_simple_sortPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15run_simple_sortPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10clasificarPfS_PiiS_
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z10clasificarPfS_PiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16rellenarIndFrontffPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16rellenarIndFrontffPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/time.h>
#define N 1048576
#define TAMSIMPLESORT 1024
#define TPB 1024
#define DEBUG false
#define PRINTARRAY false
typedef float dato; //Tipo de dato a ordenar
__device__ void simple_sort(dato *data, int left, int right) {
for (int i = left; i <= right; ++i) {
dato min_val = data[i];
int min_idx = i;
// Find the smallest value in the range [left, right].
for (int j = i + 1; j <= right; ++j) {
unsigned val_j = data[j];
if (val_j < min_val) {
min_idx = j;
min_val = val_j;
}
}
// Swap the values.
if (i != min_idx) {
data[min_idx] = data[i];
data[i] = min_val;
}
}
}
__global__ void run_simple_sort(dato * clasificado, int * indices) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int min = thread * TAMSIMPLESORT * 2;
int max = (thread * TAMSIMPLESORT * 2) + indices[thread] - 1;
if (DEBUG) printf("RSS Hilo %d - min:%d - max:%d\n", thread, min, max);
simple_sort(clasificado, min, max);
}
__global__ void clasificar(dato * v, dato * fronteras, int * indices, int bloques, dato * clasificado) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
int ind, i;
for (i = 0; i <= bloques; i++) {
if (v[thread] <= fronteras[i]) {
ind = atomicAdd(indices + i, 1);
break;
}
}
clasificado[2 * TAMSIMPLESORT*i + ind] = v[thread];
}
__global__ void rellenarIndFront(dato min, dato paso, int * indices, dato * fronteras) {
int thread = blockIdx.x*blockDim.x + threadIdx.x;
indices[thread] = 0;
fronteras[thread] = min + paso*(thread+1);
if (DEBUG) printf("RELLENAR hilo:%d frontera:%f min:%f paso:%f\n", thread, fronteras[thread], min, paso);
}
void runsort(dato * v_H, int l) {
dato * v_D;
hipMalloc((void **)&v_D, sizeof(dato)*l);
hipMemcpy(v_D, v_H, sizeof(dato)*l, hipMemcpyHostToDevice);
dato min = v_H[0];
dato max = v_H[0];
for (int i = 0; i < l; i++) {
if (v_H[i] < min) {
min = v_H[i];
}
if (v_H[i] > max) {
max = v_H[i];
}
}
int bloques = l / TAMSIMPLESORT;
if (l % TAMSIMPLESORT != 0) bloques++;
dato * fronteras;
hipMalloc((void**)&fronteras, bloques * sizeof(dato));
int * indices;
hipMalloc((void**)&indices, bloques * sizeof(int));
int cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
int cudathreads = bloques / cudablocks;
if (DEBUG) printf("RUNSORT RELLENAR blocks:%d threads:%d min:%f, max:%f\n", cudablocks, cudathreads, min, max);
rellenarIndFront <<<cudablocks, cudathreads>>> (min, (max-min) / (dato)bloques, indices, fronteras);
cudablocks = l / TPB;
if (l % TPB != 0) cudablocks++;
cudathreads = l / cudablocks;
dato * destino;
hipMalloc((void**)&destino, l * 2 * sizeof(dato));
clasificar <<<cudablocks, cudathreads >>> (v_D, fronteras, indices, bloques, destino);
hipFree(v_D);
cudablocks = bloques / TPB;
if (bloques % TPB != 0) cudablocks++;
cudathreads = bloques / cudablocks;
run_simple_sort <<<cudablocks, cudathreads >>> (destino, indices);
int * H_indices = (int *) malloc(sizeof(int)*bloques);
hipMemcpy(H_indices, indices, sizeof(int)*bloques, hipMemcpyDeviceToHost);
int offset = 0;
for (int i = 0; i < bloques; i++) {
if (DEBUG) printf("COPY Dest: %d Origen: %d Long: %d\n", offset, i*TAMSIMPLESORT * 2, H_indices[i]+1);
hipMemcpy(v_H + offset, destino + i*TAMSIMPLESORT * 2, sizeof(dato)*(H_indices[i]+1), hipMemcpyDeviceToHost);
offset += H_indices[i];
}
if (DEBUG) printf("NUM ELEMENTOS = %d\n", offset);
hipFree(v_D);
hipFree(destino);
hipFree(fronteras);
hipFree(indices);
}
int main()
{
dato *vector;
vector = (dato *)malloc(N * sizeof(dato));
srand(time(NULL));
for (int i = 0; i<N; i++)
vector[i] = rand();
bool correcto = true;
struct timeval t1, t2;
printf("Ordenando vector de %d elementos...\n", N);
gettimeofday(&t1, 0);
runsort(vector, N);
gettimeofday(&t2, 0);
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Ordenado en %f ms \n", time);
dato aux = 0;
for (int i = 0; i<N; i++) {
if (aux > vector[i]) {
correcto = false;
}
aux = vector[i];
if (PRINTARRAY) printf("%d - %f\n", i, aux);
}
if (correcto) {
printf("El vector se ha ordenado correctamente.\n\n");
}
else {
printf("Ha fallado la ordenacion del vector.\n\n");
}
return 0;
} | .text
.file "clasificador.hip"
.globl _Z30__device_stub__run_simple_sortPfPi # -- Begin function _Z30__device_stub__run_simple_sortPfPi
.p2align 4, 0x90
.type _Z30__device_stub__run_simple_sortPfPi,@function
_Z30__device_stub__run_simple_sortPfPi: # @_Z30__device_stub__run_simple_sortPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15run_simple_sortPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__run_simple_sortPfPi, .Lfunc_end0-_Z30__device_stub__run_simple_sortPfPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__clasificarPfS_PiiS_ # -- Begin function _Z25__device_stub__clasificarPfS_PiiS_
.p2align 4, 0x90
.type _Z25__device_stub__clasificarPfS_PiiS_,@function
_Z25__device_stub__clasificarPfS_PiiS_: # @_Z25__device_stub__clasificarPfS_PiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10clasificarPfS_PiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z25__device_stub__clasificarPfS_PiiS_, .Lfunc_end1-_Z25__device_stub__clasificarPfS_PiiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__rellenarIndFrontffPiPf # -- Begin function _Z31__device_stub__rellenarIndFrontffPiPf
.p2align 4, 0x90
.type _Z31__device_stub__rellenarIndFrontffPiPf,@function
_Z31__device_stub__rellenarIndFrontffPiPf: # @_Z31__device_stub__rellenarIndFrontffPiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16rellenarIndFrontffPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z31__device_stub__rellenarIndFrontffPiPf, .Lfunc_end2-_Z31__device_stub__rellenarIndFrontffPiPf
.cfi_endproc
# -- End function
.globl _Z7runsortPfi # -- Begin function _Z7runsortPfi
.p2align 4, 0x90
.type _Z7runsortPfi,@function
_Z7runsortPfi: # @_Z7runsortPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r12d
movq %rdi, %rbx
movslq %esi, %r15
leaq (,%r15,4), %r14
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 80(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
testl %r15d, %r15d
jle .LBB3_1
# %bb.12: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
movaps %xmm0, %xmm1
.p2align 4, 0x90
.LBB3_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
minss %xmm0, %xmm3
maxss %xmm1, %xmm2
incq %rcx
movaps %xmm3, %xmm0
movaps %xmm2, %xmm1
cmpq %rcx, %rax
jne .LBB3_13
jmp .LBB3_2
.LBB3_1:
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
.LBB3_2: # %._crit_edge
movss %xmm3, 116(%rsp) # 4-byte Spill
movss %xmm2, 120(%rsp) # 4-byte Spill
movabsq $4294967296, %rbp # imm = 0x100000000
leal 1023(%r12), %r14d
testl %r12d, %r12d
cmovnsl %r12d, %r14d
sarl $10, %r14d
movl %r12d, %eax
andl $1023, %eax # imm = 0x3FF
cmpl $1, %eax
sbbl $-1, %r14d
movslq %r14d, %r13
leaq (,%r13,4), %r15
leaq 88(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, 176(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
leal 1023(%r13), %r15d
testl %r13d, %r13d
cmovnsl %r14d, %r15d
sarl $10, %r15d
movl %r13d, %eax
andl $1023, %eax # imm = 0x3FF
cmpl $1, %eax
sbbl $-1, %r15d
movl %r13d, %eax
cltd
idivl %r15d
movl %eax, %r13d
orq %rbp, %r15
orq %rbp, %r13
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movss 120(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 116(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm2, %xmm1
divss %xmm0, %xmm1
movq (%rsp), %rax
movq 88(%rsp), %rcx
movss %xmm2, 104(%rsp)
movss %xmm1, 96(%rsp)
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z16rellenarIndFrontffPiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movl %r12d, %eax
cltd
idivl %r14d
movl %eax, %ebp
addl %r12d, %r12d
movslq %r12d, %rsi
shlq $2, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movl %r14d, %r12d
movq %r12, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 80(%rsp), %rax
movq 88(%rsp), %rcx
movq (%rsp), %rdx
movq 72(%rsp), %rsi
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 16(%rsp)
movl %r14d, 124(%rsp)
movq %rsi, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10clasificarPfS_PiiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 80(%rsp), %rdi
callq hipFree
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 72(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15run_simple_sortPfPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
movq 176(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movq %rax, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB3_11
# %bb.9: # %.lr.ph124.preheader
xorl %r14d, %r14d
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_10: # %.lr.ph124
# =>This Inner Loop Header: Depth=1
movslq %ebp, %rbp
leaq (%rbx,%rbp,4), %rdi
movq 72(%rsp), %rsi
addq %r14, %rsi
movslq (%r15,%r13,4), %rax
leaq 4(,%rax,4), %rdx
movl $2, %ecx
callq hipMemcpy
addl (%r15,%r13,4), %ebp
incq %r13
addq $8192, %r14 # imm = 0x2000
cmpq %r13, %r12
jne .LBB3_10
.LBB3_11: # %._crit_edge125
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7runsortPfi, .Lfunc_end3-_Z7runsortPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB4_1
# %bb.2:
xorl %r14d, %r14d
movl $.L.str, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
movl $1048576, %esi # imm = 0x100000
callq _Z7runsortPfi
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
subq 16(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm2
addsd %xmm1, %xmm0
subsd %xmm2, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movb $1, %bpl
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movzbl %bpl, %ebp
cmoval %r14d, %ebp
incq %rax
movaps %xmm1, %xmm0
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_3
# %bb.4:
testb $1, %bpl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15run_simple_sortPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10clasificarPfS_PiiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rellenarIndFrontffPiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15run_simple_sortPfPi,@object # @_Z15run_simple_sortPfPi
.section .rodata,"a",@progbits
.globl _Z15run_simple_sortPfPi
.p2align 3, 0x0
_Z15run_simple_sortPfPi:
.quad _Z30__device_stub__run_simple_sortPfPi
.size _Z15run_simple_sortPfPi, 8
.type _Z10clasificarPfS_PiiS_,@object # @_Z10clasificarPfS_PiiS_
.globl _Z10clasificarPfS_PiiS_
.p2align 3, 0x0
_Z10clasificarPfS_PiiS_:
.quad _Z25__device_stub__clasificarPfS_PiiS_
.size _Z10clasificarPfS_PiiS_, 8
.type _Z16rellenarIndFrontffPiPf,@object # @_Z16rellenarIndFrontffPiPf
.globl _Z16rellenarIndFrontffPiPf
.p2align 3, 0x0
_Z16rellenarIndFrontffPiPf:
.quad _Z31__device_stub__rellenarIndFrontffPiPf
.size _Z16rellenarIndFrontffPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Ordenando vector de %d elementos...\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Ordenado en %f ms \n"
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15run_simple_sortPfPi"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10clasificarPfS_PiiS_"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16rellenarIndFrontffPiPf"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Ha fallado la ordenacion del vector.\n"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "El vector se ha ordenado correctamente.\n"
.size .Lstr.1, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__run_simple_sortPfPi
.addrsig_sym _Z25__device_stub__clasificarPfS_PiiS_
.addrsig_sym _Z31__device_stub__rellenarIndFrontffPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15run_simple_sortPfPi
.addrsig_sym _Z10clasificarPfS_PiiS_
.addrsig_sym _Z16rellenarIndFrontffPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00011205_00000000-6_clasificador.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11simple_sortPfii
.type _Z11simple_sortPfii, @function
_Z11simple_sortPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11simple_sortPfii, .-_Z11simple_sortPfii
.globl _Z37__device_stub__Z15run_simple_sortPfPiPfPi
.type _Z37__device_stub__Z15run_simple_sortPfPiPfPi, @function
_Z37__device_stub__Z15run_simple_sortPfPiPfPi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15run_simple_sortPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z15run_simple_sortPfPiPfPi, .-_Z37__device_stub__Z15run_simple_sortPfPiPfPi
.globl _Z15run_simple_sortPfPi
.type _Z15run_simple_sortPfPi, @function
_Z15run_simple_sortPfPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15run_simple_sortPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15run_simple_sortPfPi, .-_Z15run_simple_sortPfPi
.globl _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
.type _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_, @function
_Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10clasificarPfS_PiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_, .-_Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
.globl _Z10clasificarPfS_PiiS_
.type _Z10clasificarPfS_PiiS_, @function
_Z10clasificarPfS_PiiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10clasificarPfS_PiiS_, .-_Z10clasificarPfS_PiiS_
.globl _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
.type _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf, @function
_Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16rellenarIndFrontffPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf, .-_Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
.globl _Z16rellenarIndFrontffPiPf
.type _Z16rellenarIndFrontffPiPf, @function
_Z16rellenarIndFrontffPiPf:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16rellenarIndFrontffPiPf, .-_Z16rellenarIndFrontffPiPf
.globl _Z7runsortPfi
.type _Z7runsortPfi, @function
_Z7runsortPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %esi, %rdx
leaq 0(,%rdx,4), %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movss (%r12), %xmm5
movss %xmm5, 8(%rsp)
testl %ebp, %ebp
jle .L42
movq %r12, %rax
leaq (%rbx,%r12), %rdx
movss %xmm5, 12(%rsp)
.L33:
movss (%rax), %xmm0
movaps %xmm0, %xmm2
minss 8(%rsp), %xmm2
movss %xmm2, 8(%rsp)
maxss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
.L30:
leal 1023(%rbp), %ebx
testl %ebp, %ebp
cmovns %ebp, %ebx
sarl $10, %ebx
movl %ebp, %eax
andl $1023, %eax
cmpl $1, %eax
sbbl $-1, %ebx
movslq %ebx, %r14
salq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leal 1023(%rbx), %r13d
testl %ebx, %ebx
cmovns %ebx, %r13d
sarl $10, %r13d
movl %ebx, %eax
andl $1023, %eax
cmpl $1, %eax
sbbl $-1, %r13d
movl %ebx, %eax
cltd
idivl %r13d
movl %eax, %r15d
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L36:
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, 8(%rsp)
leal (%rbp,%rbp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L37:
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %r15d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r13d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r14, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L39
movq %rbp, %rbx
addq %rbp, %r14
movl $0, %r13d
movl $0, %ebp
.L40:
movl (%rbx), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movq %r13, %rsi
addq 40(%rsp), %rsi
movslq %ebp, %rax
leaq (%r12,%rax,4), %rdi
movl $2, %ecx
call cudaMemcpy@PLT
addl (%rbx), %ebp
addq $4, %rbx
addq $8192, %r13
cmpq %r14, %rbx
jne .L40
.L39:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movss 8(%rsp), %xmm7
movss %xmm7, 12(%rsp)
jmp .L30
.L48:
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm6
subss %xmm6, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
divss %xmm0, %xmm1
movaps %xmm6, %xmm0
call _Z40__device_stub__Z16rellenarIndFrontffPiPfffPiPf
jmp .L36
.L49:
movq 40(%rsp), %r8
movl %ebx, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z10clasificarPfS_PiiS_PfS_PiiS_
jmp .L37
.L50:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z37__device_stub__Z15run_simple_sortPfPiPfPi
jmp .L38
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z7runsortPfi, .-_Z7runsortPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Ordenando vector de %d elementos...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Ordenado en %f ms \n"
.section .rodata.str1.8
.align 8
.LC5:
.string "El vector se ha ordenado correctamente.\n\n"
.align 8
.LC6:
.string "Ha fallado la ordenacion del vector.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 4194304(%r13), %r12
movq %r13, %rbp
.L53:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L53
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1048576, %esi
movq %r13, %rdi
call _Z7runsortPfi
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rax
subq (%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
movl $1, %eax
movl $0, %edx
.L55:
movaps %xmm0, %xmm1
movss (%rbx), %xmm0
ucomiss %xmm0, %xmm1
cmova %edx, %eax
addq $4, %rbx
cmpq %r12, %rbx
jne .L55
testb %al, %al
je .L56
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L57:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L57
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z16rellenarIndFrontffPiPf"
.LC8:
.string "_Z10clasificarPfS_PiiS_"
.LC9:
.string "_Z15run_simple_sortPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rellenarIndFrontffPiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10clasificarPfS_PiiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15run_simple_sortPfPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "clasificador.hip"
.globl _Z30__device_stub__run_simple_sortPfPi # -- Begin function _Z30__device_stub__run_simple_sortPfPi
.p2align 4, 0x90
.type _Z30__device_stub__run_simple_sortPfPi,@function
_Z30__device_stub__run_simple_sortPfPi: # @_Z30__device_stub__run_simple_sortPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15run_simple_sortPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__run_simple_sortPfPi, .Lfunc_end0-_Z30__device_stub__run_simple_sortPfPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__clasificarPfS_PiiS_ # -- Begin function _Z25__device_stub__clasificarPfS_PiiS_
.p2align 4, 0x90
.type _Z25__device_stub__clasificarPfS_PiiS_,@function
_Z25__device_stub__clasificarPfS_PiiS_: # @_Z25__device_stub__clasificarPfS_PiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10clasificarPfS_PiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z25__device_stub__clasificarPfS_PiiS_, .Lfunc_end1-_Z25__device_stub__clasificarPfS_PiiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__rellenarIndFrontffPiPf # -- Begin function _Z31__device_stub__rellenarIndFrontffPiPf
.p2align 4, 0x90
.type _Z31__device_stub__rellenarIndFrontffPiPf,@function
_Z31__device_stub__rellenarIndFrontffPiPf: # @_Z31__device_stub__rellenarIndFrontffPiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16rellenarIndFrontffPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z31__device_stub__rellenarIndFrontffPiPf, .Lfunc_end2-_Z31__device_stub__rellenarIndFrontffPiPf
.cfi_endproc
# -- End function
.globl _Z7runsortPfi # -- Begin function _Z7runsortPfi
.p2align 4, 0x90
.type _Z7runsortPfi,@function
_Z7runsortPfi: # @_Z7runsortPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r12d
movq %rdi, %rbx
movslq %esi, %r15
leaq (,%r15,4), %r14
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 80(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
testl %r15d, %r15d
jle .LBB3_1
# %bb.12: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
movaps %xmm0, %xmm1
.p2align 4, 0x90
.LBB3_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
minss %xmm0, %xmm3
maxss %xmm1, %xmm2
incq %rcx
movaps %xmm3, %xmm0
movaps %xmm2, %xmm1
cmpq %rcx, %rax
jne .LBB3_13
jmp .LBB3_2
.LBB3_1:
movaps %xmm0, %xmm2
movaps %xmm0, %xmm3
.LBB3_2: # %._crit_edge
movss %xmm3, 116(%rsp) # 4-byte Spill
movss %xmm2, 120(%rsp) # 4-byte Spill
movabsq $4294967296, %rbp # imm = 0x100000000
leal 1023(%r12), %r14d
testl %r12d, %r12d
cmovnsl %r12d, %r14d
sarl $10, %r14d
movl %r12d, %eax
andl $1023, %eax # imm = 0x3FF
cmpl $1, %eax
sbbl $-1, %r14d
movslq %r14d, %r13
leaq (,%r13,4), %r15
leaq 88(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, 176(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
leal 1023(%r13), %r15d
testl %r13d, %r13d
cmovnsl %r14d, %r15d
sarl $10, %r15d
movl %r13d, %eax
andl $1023, %eax # imm = 0x3FF
cmpl $1, %eax
sbbl $-1, %r15d
movl %r13d, %eax
cltd
idivl %r15d
movl %eax, %r13d
orq %rbp, %r15
orq %rbp, %r13
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movss 120(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 116(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm2, %xmm1
divss %xmm0, %xmm1
movq (%rsp), %rax
movq 88(%rsp), %rcx
movss %xmm2, 104(%rsp)
movss %xmm1, 96(%rsp)
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z16rellenarIndFrontffPiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movl %r12d, %eax
cltd
idivl %r14d
movl %eax, %ebp
addl %r12d, %r12d
movslq %r12d, %rsi
shlq $2, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movl %r14d, %r12d
movq %r12, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 80(%rsp), %rax
movq 88(%rsp), %rcx
movq (%rsp), %rdx
movq 72(%rsp), %rsi
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 16(%rsp)
movl %r14d, 124(%rsp)
movq %rsi, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10clasificarPfS_PiiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 80(%rsp), %rdi
callq hipFree
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 72(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15run_simple_sortPfPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
movq 176(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movq %rax, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB3_11
# %bb.9: # %.lr.ph124.preheader
xorl %r14d, %r14d
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_10: # %.lr.ph124
# =>This Inner Loop Header: Depth=1
movslq %ebp, %rbp
leaq (%rbx,%rbp,4), %rdi
movq 72(%rsp), %rsi
addq %r14, %rsi
movslq (%r15,%r13,4), %rax
leaq 4(,%rax,4), %rdx
movl $2, %ecx
callq hipMemcpy
addl (%r15,%r13,4), %ebp
incq %r13
addq $8192, %r14 # imm = 0x2000
cmpq %r13, %r12
jne .LBB3_10
.LBB3_11: # %._crit_edge125
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7runsortPfi, .Lfunc_end3-_Z7runsortPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB4_1
# %bb.2:
xorl %r14d, %r14d
movl $.L.str, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
movl $1048576, %esi # imm = 0x100000
callq _Z7runsortPfi
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
subq 16(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI4_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm2
addsd %xmm1, %xmm0
subsd %xmm2, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movb $1, %bpl
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movzbl %bpl, %ebp
cmoval %r14d, %ebp
incq %rax
movaps %xmm1, %xmm0
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_3
# %bb.4:
testb $1, %bpl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15run_simple_sortPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10clasificarPfS_PiiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rellenarIndFrontffPiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15run_simple_sortPfPi,@object # @_Z15run_simple_sortPfPi
.section .rodata,"a",@progbits
.globl _Z15run_simple_sortPfPi
.p2align 3, 0x0
_Z15run_simple_sortPfPi:
.quad _Z30__device_stub__run_simple_sortPfPi
.size _Z15run_simple_sortPfPi, 8
.type _Z10clasificarPfS_PiiS_,@object # @_Z10clasificarPfS_PiiS_
.globl _Z10clasificarPfS_PiiS_
.p2align 3, 0x0
_Z10clasificarPfS_PiiS_:
.quad _Z25__device_stub__clasificarPfS_PiiS_
.size _Z10clasificarPfS_PiiS_, 8
.type _Z16rellenarIndFrontffPiPf,@object # @_Z16rellenarIndFrontffPiPf
.globl _Z16rellenarIndFrontffPiPf
.p2align 3, 0x0
_Z16rellenarIndFrontffPiPf:
.quad _Z31__device_stub__rellenarIndFrontffPiPf
.size _Z16rellenarIndFrontffPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Ordenando vector de %d elementos...\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Ordenado en %f ms \n"
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15run_simple_sortPfPi"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10clasificarPfS_PiiS_"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16rellenarIndFrontffPiPf"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Ha fallado la ordenacion del vector.\n"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "El vector se ha ordenado correctamente.\n"
.size .Lstr.1, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__run_simple_sortPfPi
.addrsig_sym _Z25__device_stub__clasificarPfS_PiiS_
.addrsig_sym _Z31__device_stub__rellenarIndFrontffPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15run_simple_sortPfPi
.addrsig_sym _Z10clasificarPfS_PiiS_
.addrsig_sym _Z16rellenarIndFrontffPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/device_vector.h>
#include <thrust/tabulate.h>
#include <iostream>
struct Fragment
{
int index[3];
Fragment() = default;
};
struct functor
{
__device__ __host__
Fragment operator() (const int &i) const {
Fragment f;
f.index[0] = i; f.index[1] = i+1; f.index[2] = i+2;
return f;
}
};
int main()
{
const int N = 10;
thrust::device_vector<Fragment> dvFragment(N);
thrust::tabulate(dvFragment.begin(), dvFragment.end(), functor());
for(auto p : dvFragment) {
Fragment f = p;
std::cout << f.index[0] << " " << f.index[1] << " " << f.index[2] << std::endl;
}
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub10__tabulate7functorINS7_6detail15normal_iteratorINS7_10device_ptrI8FragmentEEEE7functorlEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0xc ; /* 0x0000000cff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.WIDE.U32 R4, R4, 0x200, RZ ; /* 0x0000020004047825 */
/* 0x001fca00078e00ff */
/*0060*/ IADD3 R13, P0, R4.reuse, R11, RZ ; /* 0x0000000b040d7210 */
/* 0x042fe40007f1e0ff */
/*0070*/ IADD3 R6, P1, -R4, c[0x0][0x160], RZ ; /* 0x0000580004067a10 */
/* 0x000fc60007f3e1ff */
/*0080*/ IMAD.X R0, RZ, RZ, R5, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0605 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe20003f04070 */
/*00a0*/ IMAD.WIDE.U32 R2, R13, R2, c[0x0][0x168] ; /* 0x00005a000d027625 */
/* 0x000fe200078e0002 */
/*00b0*/ IADD3.X R8, ~R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005087a10 */
/* 0x000fc60000ffe5ff */
/*00c0*/ IMAD R7, R0, 0xc, RZ ; /* 0x0000000c00077824 */
/* 0x000fe200078e02ff */
/*00d0*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fc60003f04300 */
/*00e0*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fd400078e0207 */
/*00f0*/ @P0 BRA 0x230 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fe40003f04070 */
/*0110*/ SHF.R.S32.HI R0, RZ, 0x1f, R6 ; /* 0x0000001fff007819 */
/* 0x000fe40000011406 */
/*0120*/ IADD3 R11, R11, 0x100, RZ ; /* 0x000001000b0b7810 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.GT.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f04300 */
/*0140*/ @P0 IADD3 R7, R13.reuse, 0x1, RZ ; /* 0x000000010d070810 */
/* 0x040fe20007ffe0ff */
/*0150*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0001e2000c101904 */
/*0160*/ @P0 IADD3 R9, R13, 0x2, RZ ; /* 0x000000020d090810 */
/* 0x000fc60007ffe0ff */
/*0170*/ @P0 STG.E [R2.64+0x4], R7 ; /* 0x0000040702000986 */
/* 0x0001e8000c101904 */
/*0180*/ @P0 STG.E [R2.64+0x8], R9 ; /* 0x0000080902000986 */
/* 0x0001e2000c101904 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fc80003f04070 */
/*01a0*/ ISETP.GT.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f04300 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.IADD R11, R4, 0x1, R11 ; /* 0x00000001040b7824 */
/* 0x001fca00078e020b */
/*01d0*/ IADD3 R5, R11.reuse, 0x1, RZ ; /* 0x000000010b057810 */
/* 0x040fe20007ffe0ff */
/*01e0*/ STG.E [R2.64+0xc00], R11 ; /* 0x000c000b02007986 */
/* 0x000fe2000c101904 */
/*01f0*/ IADD3 R7, R11, 0x2, RZ ; /* 0x000000020b077810 */
/* 0x000fc60007ffe0ff */
/*0200*/ STG.E [R2.64+0xc04], R5 ; /* 0x000c040502007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64+0xc08], R7 ; /* 0x000c080702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R11, R4, 0x100, R11 ; /* 0x00000100040b7810 */
/* 0x000fe20007ffe00b */
/*0240*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0250*/ IADD3 R5, R13.reuse, 0x1, RZ ; /* 0x000000010d057810 */
/* 0x040fe40007ffe0ff */
/*0260*/ IADD3 R7, R13, 0x2, RZ ; /* 0x000000020d077810 */
/* 0x000fe20007ffe0ff */
/*0270*/ STG.E [R2.64+0xc00], R11 ; /* 0x000c000b02007986 */
/* 0x000fe2000c101904 */
/*0280*/ IADD3 R9, R11, 0x1, RZ ; /* 0x000000010b097810 */
/* 0x000fc40007ffe0ff */
/*0290*/ IADD3 R15, R11, 0x2, RZ ; /* 0x000000020b0f7810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*02b0*/ STG.E [R2.64+0x8], R7 ; /* 0x0000080702007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R2.64+0xc04], R9 ; /* 0x000c040902007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R2.64+0xc08], R15 ; /* 0x000c080f02007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrI8FragmentEESC_EEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0xc ; /* 0x0000000cff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0060*/ IADD3 R6, P0, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x040fe40007f1e1ff */
/*0070*/ IADD3 R0, P1, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f3e0ff */
/*0080*/ IADD3.X R7, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003077a10 */
/* 0x000fe400007fe5ff */
/*0090*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe20003f04070 */
/*00a0*/ IMAD.X R4, RZ, RZ, R3, P1 ; /* 0x000000ffff047224 */
/* 0x000fe400008e0603 */
/*00b0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0009 */
/*00c0*/ ISETP.GT.U32.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fc60003f04100 */
/*00d0*/ IMAD R9, R4, 0xc, RZ ; /* 0x0000000c04097824 */
/* 0x000fca00078e02ff */
/*00e0*/ IADD3 R3, R3, R9, RZ ; /* 0x0000000903037210 */
/* 0x000fca0007ffe0ff */
/*00f0*/ @P0 BRA 0x240 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fe40003f04070 */
/*0110*/ SHF.R.S32.HI R4, RZ, 0x1f, R6 ; /* 0x0000001fff047819 */
/* 0x000fe40000011406 */
/*0120*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f04100 */
/*0140*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fe200078e00ff */
/*0150*/ @P0 MOV R11, c[0x0][0x178] ; /* 0x00005e00000b0a02 */
/* 0x000fe20000000f00 */
/*0160*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff090624 */
/* 0x000fc600078e00ff */
/*0170*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e8000c101904 */
/*0180*/ @P0 STG.E [R2.64+0x4], R9 ; /* 0x0000040902000986 */
/* 0x0001e8000c101904 */
/*0190*/ @P0 STG.E [R2.64+0x8], R11 ; /* 0x0000080b02000986 */
/* 0x0001e2000c101904 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fc80003f04070 */
/*01b0*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f04100 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fe200078e00ff */
/*01e0*/ MOV R9, c[0x0][0x178] ; /* 0x00005e0000097a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0200*/ STG.E [R2.64+0xc00], R5 ; /* 0x000c000502007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64+0xc04], R7 ; /* 0x000c040702007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R2.64+0xc08], R9 ; /* 0x000c080902007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*0250*/ MOV R9, c[0x0][0x178] ; /* 0x00005e0000097a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R2.64+0xc00], R5 ; /* 0x000c000502007986 */
/* 0x000fe8000c101904 */
/*0290*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STG.E [R2.64+0xc04], R7 ; /* 0x000c040702007986 */
/* 0x000fe8000c101904 */
/*02b0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R2.64+0xc08], R9 ; /* 0x000c080902007986 */
/* 0x000fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/tabulate.h>
#include <iostream>
struct Fragment
{
int index[3];
Fragment() = default;
};
struct functor
{
__device__ __host__
Fragment operator() (const int &i) const {
Fragment f;
f.index[0] = i; f.index[1] = i+1; f.index[2] = i+2;
return f;
}
};
int main()
{
const int N = 10;
thrust::device_vector<Fragment> dvFragment(N);
thrust::tabulate(dvFragment.begin(), dvFragment.end(), functor());
for(auto p : dvFragment) {
Fragment f = p;
std::cout << f.index[0] << " " << f.index[1] << " " << f.index[2] << std::endl;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/tabulate.h>
#include <iostream>
struct Fragment
{
int index[3];
Fragment() = default;
};
struct functor
{
__device__ __host__
Fragment operator() (const int &i) const {
Fragment f;
f.index[0] = i; f.index[1] = i+1; f.index[2] = i+2;
return f;
}
};
int main()
{
const int N = 10;
thrust::device_vector<Fragment> dvFragment(N);
thrust::tabulate(dvFragment.begin(), dvFragment.end(), functor());
for(auto p : dvFragment) {
Fragment f = p;
std::cout << f.index[0] << " " << f.index[1] << " " << f.index[2] << std::endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/tabulate.h>
#include <iostream>
struct Fragment
{
int index[3];
Fragment() = default;
};
struct functor
{
__device__ __host__
Fragment operator() (const int &i) const {
Fragment f;
f.index[0] = i; f.index[1] = i+1; f.index[2] = i+2;
return f;
}
};
int main()
{
const int N = 10;
thrust::device_vector<Fragment> dvFragment(N);
thrust::tabulate(dvFragment.begin(), dvFragment.end(), functor());
for(auto p : dvFragment) {
Fragment f = p;
std::cout << f.index[0] << " " << f.index[1] << " " << f.index[2] << std::endl;
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x10
s_mul_i32 s3, s3, 12
s_mul_hi_u32 s0, s2, 12
s_mul_i32 s2, s2, 12
s_add_i32 s1, s0, s3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s1
v_mov_b32_e32 v2, s8
v_mad_u64_u32 v[3:4], null, v0, 12, s[0:1]
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
flat_store_b96 v[3:4], v[0:2]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_:
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s2, s10
s_addc_u32 s4, 0, s11
s_sub_u32 s6, s8, s3
s_subb_u32 s7, s9, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s2, 0x100, s[6:7]
s_and_b32 s2, s2, exec_lo
s_cselect_b32 s5, s6, 0x100
s_mov_b32 s2, 0
s_cmpk_lg_i32 s5, 0x100
s_cbranch_scc0 .LBB1_4
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_mov_b32 s5, 0
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB1_3
v_add_co_u32 v3, s7, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, null, s4, 0, s7
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, v3, 12, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, 12, v[2:3]
v_mov_b32_e32 v2, v4
flat_store_b32 v[1:2], v3
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB1_5
s_branch .LBB1_6
.LBB1_4:
s_cbranch_execz .LBB1_6
.LBB1_5:
v_add_co_u32 v3, s3, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, null, s4, 0, s3
s_or_b32 s2, s2, exec_lo
v_mad_u64_u32 v[1:2], null, v3, 12, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v2
v_mad_u64_u32 v[4:5], null, v6, 12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v4
flat_store_b32 v[1:2], v3
.LBB1_6:
s_and_saveexec_b32 s0, s2
s_cbranch_execnz .LBB1_8
s_endpgm
.LBB1_8:
v_add_nc_u32_e32 v4, 2, v3
v_add_nc_u32_e32 v3, 1, v3
flat_store_b64 v[1:2], v[3:4] offset:4
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub10__tabulate7functorINS7_6detail15normal_iteratorINS7_10device_ptrI8FragmentEEEE7functorlEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0xc ; /* 0x0000000cff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.WIDE.U32 R4, R4, 0x200, RZ ; /* 0x0000020004047825 */
/* 0x001fca00078e00ff */
/*0060*/ IADD3 R13, P0, R4.reuse, R11, RZ ; /* 0x0000000b040d7210 */
/* 0x042fe40007f1e0ff */
/*0070*/ IADD3 R6, P1, -R4, c[0x0][0x160], RZ ; /* 0x0000580004067a10 */
/* 0x000fc60007f3e1ff */
/*0080*/ IMAD.X R0, RZ, RZ, R5, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0605 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe20003f04070 */
/*00a0*/ IMAD.WIDE.U32 R2, R13, R2, c[0x0][0x168] ; /* 0x00005a000d027625 */
/* 0x000fe200078e0002 */
/*00b0*/ IADD3.X R8, ~R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005087a10 */
/* 0x000fc60000ffe5ff */
/*00c0*/ IMAD R7, R0, 0xc, RZ ; /* 0x0000000c00077824 */
/* 0x000fe200078e02ff */
/*00d0*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fc60003f04300 */
/*00e0*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fd400078e0207 */
/*00f0*/ @P0 BRA 0x230 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fe40003f04070 */
/*0110*/ SHF.R.S32.HI R0, RZ, 0x1f, R6 ; /* 0x0000001fff007819 */
/* 0x000fe40000011406 */
/*0120*/ IADD3 R11, R11, 0x100, RZ ; /* 0x000001000b0b7810 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.GT.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f04300 */
/*0140*/ @P0 IADD3 R7, R13.reuse, 0x1, RZ ; /* 0x000000010d070810 */
/* 0x040fe20007ffe0ff */
/*0150*/ @P0 STG.E [R2.64], R13 ; /* 0x0000000d02000986 */
/* 0x0001e2000c101904 */
/*0160*/ @P0 IADD3 R9, R13, 0x2, RZ ; /* 0x000000020d090810 */
/* 0x000fc60007ffe0ff */
/*0170*/ @P0 STG.E [R2.64+0x4], R7 ; /* 0x0000040702000986 */
/* 0x0001e8000c101904 */
/*0180*/ @P0 STG.E [R2.64+0x8], R9 ; /* 0x0000080902000986 */
/* 0x0001e2000c101904 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fc80003f04070 */
/*01a0*/ ISETP.GT.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f04300 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.IADD R11, R4, 0x1, R11 ; /* 0x00000001040b7824 */
/* 0x001fca00078e020b */
/*01d0*/ IADD3 R5, R11.reuse, 0x1, RZ ; /* 0x000000010b057810 */
/* 0x040fe20007ffe0ff */
/*01e0*/ STG.E [R2.64+0xc00], R11 ; /* 0x000c000b02007986 */
/* 0x000fe2000c101904 */
/*01f0*/ IADD3 R7, R11, 0x2, RZ ; /* 0x000000020b077810 */
/* 0x000fc60007ffe0ff */
/*0200*/ STG.E [R2.64+0xc04], R5 ; /* 0x000c040502007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64+0xc08], R7 ; /* 0x000c080702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R11, R4, 0x100, R11 ; /* 0x00000100040b7810 */
/* 0x000fe20007ffe00b */
/*0240*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0250*/ IADD3 R5, R13.reuse, 0x1, RZ ; /* 0x000000010d057810 */
/* 0x040fe40007ffe0ff */
/*0260*/ IADD3 R7, R13, 0x2, RZ ; /* 0x000000020d077810 */
/* 0x000fe20007ffe0ff */
/*0270*/ STG.E [R2.64+0xc00], R11 ; /* 0x000c000b02007986 */
/* 0x000fe2000c101904 */
/*0280*/ IADD3 R9, R11, 0x1, RZ ; /* 0x000000010b097810 */
/* 0x000fc40007ffe0ff */
/*0290*/ IADD3 R15, R11, 0x2, RZ ; /* 0x000000020b0f7810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*02b0*/ STG.E [R2.64+0x8], R7 ; /* 0x0000080702007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R2.64+0xc04], R9 ; /* 0x000c040902007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R2.64+0xc08], R15 ; /* 0x000c080f02007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrI8FragmentEESC_EEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0xc ; /* 0x0000000cff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0060*/ IADD3 R6, P0, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x040fe40007f1e1ff */
/*0070*/ IADD3 R0, P1, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f3e0ff */
/*0080*/ IADD3.X R7, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003077a10 */
/* 0x000fe400007fe5ff */
/*0090*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe20003f04070 */
/*00a0*/ IMAD.X R4, RZ, RZ, R3, P1 ; /* 0x000000ffff047224 */
/* 0x000fe400008e0603 */
/*00b0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0009 */
/*00c0*/ ISETP.GT.U32.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fc60003f04100 */
/*00d0*/ IMAD R9, R4, 0xc, RZ ; /* 0x0000000c04097824 */
/* 0x000fca00078e02ff */
/*00e0*/ IADD3 R3, R3, R9, RZ ; /* 0x0000000903037210 */
/* 0x000fca0007ffe0ff */
/*00f0*/ @P0 BRA 0x240 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fe40003f04070 */
/*0110*/ SHF.R.S32.HI R4, RZ, 0x1f, R6 ; /* 0x0000001fff047819 */
/* 0x000fe40000011406 */
/*0120*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f04100 */
/*0140*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fe200078e00ff */
/*0150*/ @P0 MOV R11, c[0x0][0x178] ; /* 0x00005e00000b0a02 */
/* 0x000fe20000000f00 */
/*0160*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff090624 */
/* 0x000fc600078e00ff */
/*0170*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e8000c101904 */
/*0180*/ @P0 STG.E [R2.64+0x4], R9 ; /* 0x0000040902000986 */
/* 0x0001e8000c101904 */
/*0190*/ @P0 STG.E [R2.64+0x8], R11 ; /* 0x0000080b02000986 */
/* 0x0001e2000c101904 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fc80003f04070 */
/*01b0*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f04100 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fe200078e00ff */
/*01e0*/ MOV R9, c[0x0][0x178] ; /* 0x00005e0000097a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0200*/ STG.E [R2.64+0xc00], R5 ; /* 0x000c000502007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64+0xc04], R7 ; /* 0x000c040702007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R2.64+0xc08], R9 ; /* 0x000c080902007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*0250*/ MOV R9, c[0x0][0x178] ; /* 0x00005e0000097a02 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R2.64+0xc00], R5 ; /* 0x000c000502007986 */
/* 0x000fe8000c101904 */
/*0290*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STG.E [R2.64+0xc04], R7 ; /* 0x000c040702007986 */
/* 0x000fe8000c101904 */
/*02b0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R2.64+0xc08], R9 ; /* 0x000c080902007986 */
/* 0x000fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x10
s_mul_i32 s3, s3, 12
s_mul_hi_u32 s0, s2, 12
s_mul_i32 s2, s2, 12
s_add_i32 s1, s0, s3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s1
v_mov_b32_e32 v2, s8
v_mad_u64_u32 v[3:4], null, v0, 12, s[0:1]
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
flat_store_b96 v[3:4], v[0:2]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_:
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s2, s10
s_addc_u32 s4, 0, s11
s_sub_u32 s6, s8, s3
s_subb_u32 s7, s9, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s2, 0x100, s[6:7]
s_and_b32 s2, s2, exec_lo
s_cselect_b32 s5, s6, 0x100
s_mov_b32 s2, 0
s_cmpk_lg_i32 s5, 0x100
s_cbranch_scc0 .LBB1_4
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_mov_b32 s5, 0
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB1_3
v_add_co_u32 v3, s7, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, null, s4, 0, s7
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, v3, 12, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, 12, v[2:3]
v_mov_b32_e32 v2, v4
flat_store_b32 v[1:2], v3
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB1_5
s_branch .LBB1_6
.LBB1_4:
s_cbranch_execz .LBB1_6
.LBB1_5:
v_add_co_u32 v3, s3, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, null, s4, 0, s3
s_or_b32 s2, s2, exec_lo
v_mad_u64_u32 v[1:2], null, v3, 12, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v2
v_mad_u64_u32 v[4:5], null, v6, 12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v4
flat_store_b32 v[1:2], v3
.LBB1_6:
s_and_saveexec_b32 s0, s2
s_cbranch_execnz .LBB1_8
s_endpgm
.LBB1_8:
v_add_nc_u32_e32 v4, 2, v3
v_add_nc_u32_e32 v3, 1, v3
flat_store_b64 v[1:2], v[3:4] offset:4
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrI8FragmentEES6_EEmLj1EEEvT0_T1_SA_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrI8FragmentEEEE7functorlEElLj1EEEvT0_T1_SE_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#pragma diag_suppress integer_sign_change
static unsigned short* d_in;
static unsigned char* d_out;
static unsigned int h_Width;
static unsigned int h_Height;
static unsigned int h_BlockWidth;
static unsigned int h_BlockHeight;
#define THREAD_TOTAL_X_LEN 12
#define THREAD_AUX_X_LEN 4
#define THREAD_WORKING_X_LEN (THREAD_TOTAL_X_LEN - THREAD_AUX_X_LEN)
#define THREAD_TOTAL_Y_LEN 12
#define THREAD_AUX_Y_LEN 4
#define THREAD_WORKING_Y_LEN (THREAD_TOTAL_Y_LEN - THREAD_AUX_Y_LEN)
#define OFFSET(x,y) sIdx + y * THREAD_TOTAL_X_LEN + x
__global__ void Sobel(const unsigned short* in,unsigned char* out, const unsigned int width, const unsigned int height)
{
extern __shared__ float s[];
const unsigned int xPos = (blockIdx.x * THREAD_WORKING_X_LEN + threadIdx.x) - (THREAD_AUX_X_LEN / 2);
const unsigned int yPos = (blockIdx.y * THREAD_WORKING_Y_LEN + threadIdx.y) - (THREAD_AUX_Y_LEN / 2);
const unsigned int inPos = (xPos + yPos * width);
const unsigned int sIdx = (threadIdx.x + threadIdx.y * THREAD_TOTAL_X_LEN);
unsigned int outIt = inPos * 4;
if (xPos < width && yPos < height)
s[sIdx] = in[inPos] / float(USHRT_MAX);
else
s[sIdx] = 0.0f;
__syncthreads();
if ((threadIdx.x - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_X_LEN && (threadIdx.y - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_Y_LEN)
{
const float sobelX = (
-1 * s[OFFSET(-2,-2)] -2 * s[OFFSET(-1,-2)] +0 * s[OFFSET(0,-2)] +2 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
-1 * s[OFFSET(-2,-1)] -2 * s[OFFSET(-1,-1)] +0 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +1 * s[OFFSET(2,-1)]
-2 * s[OFFSET(-2, 0)] -4 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +4 * s[OFFSET(1, 0)] +2 * s[OFFSET(2, 0)]
-1 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] +0 * s[OFFSET(0, 1)] +2 * s[OFFSET(1, 1)] +1 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -2 * s[OFFSET(-1, 2)] +0 * s[OFFSET(0, 2)] +2 * s[OFFSET(1, 2)] +1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float sobelY = (
+1 * s[OFFSET(-2,-2)] +1 * s[OFFSET(-1,-2)] +2 * s[OFFSET(0,-2)] +1 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
+2 * s[OFFSET(-2,-1)] +2 * s[OFFSET(-1,-1)] +4 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +2 * s[OFFSET(2,-1)]
+0 * s[OFFSET(-2, 0)] +0 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +0 * s[OFFSET(1, 0)] +0 * s[OFFSET(2, 0)]
-2 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] -4 * s[OFFSET(0, 1)] -2 * s[OFFSET(1, 1)] -2 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -1 * s[OFFSET(-1, 2)] -2 * s[OFFSET(0, 2)] -1 * s[OFFSET(1, 2)] -1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float gradientLen = sqrt(sobelX*sobelX + sobelY*sobelY + 1.0f);
const unsigned char xLen = -(sobelX * 128)/gradientLen + 128;
const unsigned char yLen = -(sobelY * 128)/gradientLen + 128;
const unsigned char zLen = (UCHAR_MAX)/gradientLen;
out[outIt++] = xLen;
out[outIt++] = yLen;
out[outIt++] = zLen;
out[outIt] = 255;
}
} | .file "tmpxft_0016b3ca_00000000-6_Sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj
.type _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj, @function
_Z29__device_stub__Z5SobelPKtPhjjPKtPhjj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5SobelPKtPhjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj, .-_Z29__device_stub__Z5SobelPKtPhjjPKtPhjj
.globl _Z5SobelPKtPhjj
.type _Z5SobelPKtPhjj, @function
_Z5SobelPKtPhjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5SobelPKtPhjj, .-_Z5SobelPKtPhjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5SobelPKtPhjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5SobelPKtPhjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#pragma diag_suppress integer_sign_change
static unsigned short* d_in;
static unsigned char* d_out;
static unsigned int h_Width;
static unsigned int h_Height;
static unsigned int h_BlockWidth;
static unsigned int h_BlockHeight;
#define THREAD_TOTAL_X_LEN 12
#define THREAD_AUX_X_LEN 4
#define THREAD_WORKING_X_LEN (THREAD_TOTAL_X_LEN - THREAD_AUX_X_LEN)
#define THREAD_TOTAL_Y_LEN 12
#define THREAD_AUX_Y_LEN 4
#define THREAD_WORKING_Y_LEN (THREAD_TOTAL_Y_LEN - THREAD_AUX_Y_LEN)
#define OFFSET(x,y) sIdx + y * THREAD_TOTAL_X_LEN + x
__global__ void Sobel(const unsigned short* in,unsigned char* out, const unsigned int width, const unsigned int height)
{
extern __shared__ float s[];
const unsigned int xPos = (blockIdx.x * THREAD_WORKING_X_LEN + threadIdx.x) - (THREAD_AUX_X_LEN / 2);
const unsigned int yPos = (blockIdx.y * THREAD_WORKING_Y_LEN + threadIdx.y) - (THREAD_AUX_Y_LEN / 2);
const unsigned int inPos = (xPos + yPos * width);
const unsigned int sIdx = (threadIdx.x + threadIdx.y * THREAD_TOTAL_X_LEN);
unsigned int outIt = inPos * 4;
if (xPos < width && yPos < height)
s[sIdx] = in[inPos] / float(USHRT_MAX);
else
s[sIdx] = 0.0f;
__syncthreads();
if ((threadIdx.x - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_X_LEN && (threadIdx.y - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_Y_LEN)
{
const float sobelX = (
-1 * s[OFFSET(-2,-2)] -2 * s[OFFSET(-1,-2)] +0 * s[OFFSET(0,-2)] +2 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
-1 * s[OFFSET(-2,-1)] -2 * s[OFFSET(-1,-1)] +0 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +1 * s[OFFSET(2,-1)]
-2 * s[OFFSET(-2, 0)] -4 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +4 * s[OFFSET(1, 0)] +2 * s[OFFSET(2, 0)]
-1 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] +0 * s[OFFSET(0, 1)] +2 * s[OFFSET(1, 1)] +1 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -2 * s[OFFSET(-1, 2)] +0 * s[OFFSET(0, 2)] +2 * s[OFFSET(1, 2)] +1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float sobelY = (
+1 * s[OFFSET(-2,-2)] +1 * s[OFFSET(-1,-2)] +2 * s[OFFSET(0,-2)] +1 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
+2 * s[OFFSET(-2,-1)] +2 * s[OFFSET(-1,-1)] +4 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +2 * s[OFFSET(2,-1)]
+0 * s[OFFSET(-2, 0)] +0 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +0 * s[OFFSET(1, 0)] +0 * s[OFFSET(2, 0)]
-2 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] -4 * s[OFFSET(0, 1)] -2 * s[OFFSET(1, 1)] -2 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -1 * s[OFFSET(-1, 2)] -2 * s[OFFSET(0, 2)] -1 * s[OFFSET(1, 2)] -1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float gradientLen = sqrt(sobelX*sobelX + sobelY*sobelY + 1.0f);
const unsigned char xLen = -(sobelX * 128)/gradientLen + 128;
const unsigned char yLen = -(sobelY * 128)/gradientLen + 128;
const unsigned char zLen = (UCHAR_MAX)/gradientLen;
out[outIt++] = xLen;
out[outIt++] = yLen;
out[outIt++] = zLen;
out[outIt] = 255;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#pragma diag_suppress integer_sign_change
static unsigned short* d_in;
static unsigned char* d_out;
static unsigned int h_Width;
static unsigned int h_Height;
static unsigned int h_BlockWidth;
static unsigned int h_BlockHeight;
#define THREAD_TOTAL_X_LEN 12
#define THREAD_AUX_X_LEN 4
#define THREAD_WORKING_X_LEN (THREAD_TOTAL_X_LEN - THREAD_AUX_X_LEN)
#define THREAD_TOTAL_Y_LEN 12
#define THREAD_AUX_Y_LEN 4
#define THREAD_WORKING_Y_LEN (THREAD_TOTAL_Y_LEN - THREAD_AUX_Y_LEN)
#define OFFSET(x,y) sIdx + y * THREAD_TOTAL_X_LEN + x
__global__ void Sobel(const unsigned short* in,unsigned char* out, const unsigned int width, const unsigned int height)
{
extern __shared__ float s[];
const unsigned int xPos = (blockIdx.x * THREAD_WORKING_X_LEN + threadIdx.x) - (THREAD_AUX_X_LEN / 2);
const unsigned int yPos = (blockIdx.y * THREAD_WORKING_Y_LEN + threadIdx.y) - (THREAD_AUX_Y_LEN / 2);
const unsigned int inPos = (xPos + yPos * width);
const unsigned int sIdx = (threadIdx.x + threadIdx.y * THREAD_TOTAL_X_LEN);
unsigned int outIt = inPos * 4;
if (xPos < width && yPos < height)
s[sIdx] = in[inPos] / float(USHRT_MAX);
else
s[sIdx] = 0.0f;
__syncthreads();
if ((threadIdx.x - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_X_LEN && (threadIdx.y - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_Y_LEN)
{
const float sobelX = (
-1 * s[OFFSET(-2,-2)] -2 * s[OFFSET(-1,-2)] +0 * s[OFFSET(0,-2)] +2 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
-1 * s[OFFSET(-2,-1)] -2 * s[OFFSET(-1,-1)] +0 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +1 * s[OFFSET(2,-1)]
-2 * s[OFFSET(-2, 0)] -4 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +4 * s[OFFSET(1, 0)] +2 * s[OFFSET(2, 0)]
-1 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] +0 * s[OFFSET(0, 1)] +2 * s[OFFSET(1, 1)] +1 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -2 * s[OFFSET(-1, 2)] +0 * s[OFFSET(0, 2)] +2 * s[OFFSET(1, 2)] +1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float sobelY = (
+1 * s[OFFSET(-2,-2)] +1 * s[OFFSET(-1,-2)] +2 * s[OFFSET(0,-2)] +1 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
+2 * s[OFFSET(-2,-1)] +2 * s[OFFSET(-1,-1)] +4 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +2 * s[OFFSET(2,-1)]
+0 * s[OFFSET(-2, 0)] +0 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +0 * s[OFFSET(1, 0)] +0 * s[OFFSET(2, 0)]
-2 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] -4 * s[OFFSET(0, 1)] -2 * s[OFFSET(1, 1)] -2 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -1 * s[OFFSET(-1, 2)] -2 * s[OFFSET(0, 2)] -1 * s[OFFSET(1, 2)] -1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float gradientLen = sqrt(sobelX*sobelX + sobelY*sobelY + 1.0f);
const unsigned char xLen = -(sobelX * 128)/gradientLen + 128;
const unsigned char yLen = -(sobelY * 128)/gradientLen + 128;
const unsigned char zLen = (UCHAR_MAX)/gradientLen;
out[outIt++] = xLen;
out[outIt++] = yLen;
out[outIt++] = zLen;
out[outIt] = 255;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#pragma diag_suppress integer_sign_change
static unsigned short* d_in;
static unsigned char* d_out;
static unsigned int h_Width;
static unsigned int h_Height;
static unsigned int h_BlockWidth;
static unsigned int h_BlockHeight;
#define THREAD_TOTAL_X_LEN 12
#define THREAD_AUX_X_LEN 4
#define THREAD_WORKING_X_LEN (THREAD_TOTAL_X_LEN - THREAD_AUX_X_LEN)
#define THREAD_TOTAL_Y_LEN 12
#define THREAD_AUX_Y_LEN 4
#define THREAD_WORKING_Y_LEN (THREAD_TOTAL_Y_LEN - THREAD_AUX_Y_LEN)
#define OFFSET(x,y) sIdx + y * THREAD_TOTAL_X_LEN + x
__global__ void Sobel(const unsigned short* in,unsigned char* out, const unsigned int width, const unsigned int height)
{
extern __shared__ float s[];
const unsigned int xPos = (blockIdx.x * THREAD_WORKING_X_LEN + threadIdx.x) - (THREAD_AUX_X_LEN / 2);
const unsigned int yPos = (blockIdx.y * THREAD_WORKING_Y_LEN + threadIdx.y) - (THREAD_AUX_Y_LEN / 2);
const unsigned int inPos = (xPos + yPos * width);
const unsigned int sIdx = (threadIdx.x + threadIdx.y * THREAD_TOTAL_X_LEN);
unsigned int outIt = inPos * 4;
if (xPos < width && yPos < height)
s[sIdx] = in[inPos] / float(USHRT_MAX);
else
s[sIdx] = 0.0f;
__syncthreads();
if ((threadIdx.x - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_X_LEN && (threadIdx.y - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_Y_LEN)
{
const float sobelX = (
-1 * s[OFFSET(-2,-2)] -2 * s[OFFSET(-1,-2)] +0 * s[OFFSET(0,-2)] +2 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
-1 * s[OFFSET(-2,-1)] -2 * s[OFFSET(-1,-1)] +0 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +1 * s[OFFSET(2,-1)]
-2 * s[OFFSET(-2, 0)] -4 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +4 * s[OFFSET(1, 0)] +2 * s[OFFSET(2, 0)]
-1 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] +0 * s[OFFSET(0, 1)] +2 * s[OFFSET(1, 1)] +1 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -2 * s[OFFSET(-1, 2)] +0 * s[OFFSET(0, 2)] +2 * s[OFFSET(1, 2)] +1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float sobelY = (
+1 * s[OFFSET(-2,-2)] +1 * s[OFFSET(-1,-2)] +2 * s[OFFSET(0,-2)] +1 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
+2 * s[OFFSET(-2,-1)] +2 * s[OFFSET(-1,-1)] +4 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +2 * s[OFFSET(2,-1)]
+0 * s[OFFSET(-2, 0)] +0 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +0 * s[OFFSET(1, 0)] +0 * s[OFFSET(2, 0)]
-2 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] -4 * s[OFFSET(0, 1)] -2 * s[OFFSET(1, 1)] -2 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -1 * s[OFFSET(-1, 2)] -2 * s[OFFSET(0, 2)] -1 * s[OFFSET(1, 2)] -1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float gradientLen = sqrt(sobelX*sobelX + sobelY*sobelY + 1.0f);
const unsigned char xLen = -(sobelX * 128)/gradientLen + 128;
const unsigned char yLen = -(sobelY * 128)/gradientLen + 128;
const unsigned char zLen = (UCHAR_MAX)/gradientLen;
out[outIt++] = xLen;
out[outIt++] = yLen;
out[outIt++] = zLen;
out[outIt] = 255;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5SobelPKtPhjj
.globl _Z5SobelPKtPhjj
.p2align 8
.type _Z5SobelPKtPhjj,@function
_Z5SobelPKtPhjj:
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_lshl_b32 s4, s14, 3
s_lshl_b32 s5, s15, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v4, v2, s4, -2
v_add3_u32 v5, v3, s5, -2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v5, s2, v[4:5]
v_cmp_gt_u32_e32 vcc_lo, s2, v4
v_cmp_gt_u32_e64 s2, s3, v5
v_mov_b32_e32 v4, 0
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_u16 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v1, v1
v_div_scale_f32 v4, null, 0x477fff00, 0x477fff00, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v1, 0x477fff00, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v4, v4, 0x477fff00, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, -2, v2
v_add_nc_u32_e32 v5, -2, v3
v_mad_u32_u24 v2, v3, 12, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_u32_e32 v3, v1, v5
v_lshl_add_u32 v1, v2, 2, 0
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v3
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v2, 0xffffff98, v1
v_add_nc_u32_e32 v3, 0xffffff9c, v1
v_add_nc_u32_e32 v4, 0xffffffa0, v1
v_add_nc_u32_e32 v6, 0xffffffa8, v1
v_subrev_nc_u32_e32 v7, 56, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v3
v_add_nc_u32_e32 v5, 0xffffffa4, v1
ds_load_b32 v4, v4
v_subrev_nc_u32_e32 v9, 52, v1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_fma_f32 v8, v3, -2.0, -v2
v_add_f32_e32 v2, v2, v3
ds_load_b32 v5, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v7
ds_load_b32 v12, v1 offset:104
v_subrev_nc_u32_e32 v3, 48, v1
v_fmac_f32_e32 v8, 0, v4
ds_load_b32 v9, v9
v_fmac_f32_e32 v2, 2.0, v4
v_subrev_nc_u32_e32 v4, 44, v1
ds_load_b32 v3, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v8, 2.0, v5
s_waitcnt lgkmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_add_f32 v2, v5, v2 :: v_dual_add_f32 v5, v6, v8
v_subrev_nc_u32_e32 v8, 40, v1
s_waitcnt lgkmcnt(4)
v_sub_f32_e32 v5, v5, v7
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(3)
v_fmac_f32_e32 v5, -2.0, v9
v_add_f32_e32 v13, v6, v2
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v5, 0, v3 :: v_dual_add_nc_u32 v6, -4, v1
v_fmac_f32_e32 v13, 2.0, v7
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 2.0, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v14, v8, v5
v_fmac_f32_e32 v13, 2.0, v9
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v13, 4.0, v3 :: v_dual_add_nc_u32 v2, -8, v1
ds_load_b32 v7, v2
ds_load_b32 v6, v6
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(2)
v_dual_fmac_f32 v14, -2.0, v7 :: v_dual_fmac_f32 v13, 2.0, v4
ds_load_2addr_b32 v[4:5], v1 offset0:2 offset1:10
s_waitcnt lgkmcnt(2)
v_dual_fmac_f32 v14, -4.0, v6 :: v_dual_fmac_f32 v13, 2.0, v8
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v14, 0, v2 :: v_dual_fmac_f32 v13, 0, v7
v_dual_fmac_f32 v14, 4.0, v3 :: v_dual_fmac_f32 v13, 0, v6
ds_load_2addr_b32 v[6:7], v1 offset0:11 offset1:12
ds_load_2addr_b32 v[8:9], v1 offset0:13 offset1:14
ds_load_2addr_b32 v[10:11], v1 offset0:22 offset1:23
s_waitcnt lgkmcnt(3)
v_dual_fmac_f32 v13, 0, v2 :: v_dual_fmac_f32 v14, 2.0, v4
ds_load_2addr_b32 v[1:2], v1 offset0:24 offset1:25
v_fmac_f32_e32 v13, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, 0, v4
v_fmac_f32_e32 v13, -2.0, v5
s_waitcnt lgkmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, -2.0, v6
v_fmac_f32_e32 v13, -4.0, v7
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, -2.0, v8
v_fmac_f32_e32 v13, -2.0, v9
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v14, v5 :: v_dual_sub_f32 v4, v13, v10
v_dual_fmac_f32 v3, -2.0, v6 :: v_dual_sub_f32 v4, v4, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v3, 0, v7 :: v_dual_fmac_f32 v4, -2.0, v1
v_fmac_f32_e32 v3, 2.0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v3
v_sub_f32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, -2.0, v11
v_fmac_f32_e32 v3, 0, v1
v_sub_f32_e32 v1, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, 2.0, v2
v_dual_sub_f32 v1, v1, v12 :: v_dual_add_f32 v2, v12, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v1, 0x42800000, v1 :: v_dual_mul_f32 v2, 0x42800000, v2
v_div_scale_f32 v4, null, 0x41900000, 0x41900000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, 0x41900000, 0x41900000, v2
v_rcp_f32_e32 v6, v4
v_div_scale_f32 v9, vcc_lo, v2, 0x41900000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v7, -v3, v5, 1.0
v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v5, v7, v5
v_div_scale_f32 v7, s2, v1, 0x41900000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v8, v9, v5
v_mul_f32_e32 v10, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v3, v8, v9
v_fma_f32 v12, -v4, v10, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v11, v5
v_fmac_f32_e32 v10, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, -v3, v8, v9
v_fma_f32 v4, -v4, v10, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v3, v3, v5, v8
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v4, v4, v6, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v3, 0x41900000, v2
v_div_fixup_f32 v1, v4, 0x41900000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, v1, v1
v_mul_f32_e32 v1, 0x43000000, v1
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v2, 0x43000000, v2 :: v_dual_add_f32 v3, 1.0, v3
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v4, v3
v_fma_f32 v8, -v6, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v4, v4, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v5, null, v3, v3, v1
v_div_scale_f32 v7, null, v3, v3, 0x437f0000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v8, v5
v_div_scale_f32 v11, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v9, v7
v_div_scale_f32 v13, s2, v1, v3, v1
v_fma_f32 v10, -v4, v6, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v5, v8, 1.0
v_fmac_f32_e32 v6, v10, v6
v_fma_f32 v10, -v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v8, v12, v8
v_div_scale_f32 v12, s3, 0x437f0000, v3, 0x437f0000
v_dual_mul_f32 v14, v11, v6 :: v_dual_fmac_f32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v13, v8
v_fma_f32 v15, -v4, v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v16, v12, v9
v_fma_f32 v17, -v5, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v14, v15, v6
v_fma_f32 v15, -v7, v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v10, v17, v8
v_fma_f32 v4, -v4, v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v16, v15, v9
v_fma_f32 v5, -v5, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v6, v14
s_mov_b32 vcc_lo, s2
v_fma_f32 v6, -v7, v16, v12
s_delay_alu instid0(VALU_DEP_3)
v_div_fmas_f32 v5, v5, v8, v10
s_mov_b32 vcc_lo, s3
v_div_fixup_f32 v2, v4, v3, v2
v_or_b32_e32 v7, 3, v0
v_div_fmas_f32 v4, v6, v9, v16
v_div_fixup_f32 v1, v5, v3, v1
v_or_b32_e32 v6, 2, v0
v_sub_f32_e32 v2, 0x43000000, v2
v_mov_b32_e32 v5, 0xff
v_div_fixup_f32 v3, v4, v3, 0x437f0000
v_sub_f32_e32 v1, 0x43000000, v1
v_or_b32_e32 v4, 1, v0
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v3, v3
v_cvt_i32_f32_e32 v1, v1
s_clause 0x3
global_store_b8 v0, v2, s[0:1]
global_store_b8 v4, v1, s[0:1]
global_store_b8 v6, v3, s[0:1]
global_store_b8 v7, v5, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5SobelPKtPhjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5SobelPKtPhjj, .Lfunc_end0-_Z5SobelPKtPhjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5SobelPKtPhjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5SobelPKtPhjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#pragma diag_suppress integer_sign_change
static unsigned short* d_in;
static unsigned char* d_out;
static unsigned int h_Width;
static unsigned int h_Height;
static unsigned int h_BlockWidth;
static unsigned int h_BlockHeight;
#define THREAD_TOTAL_X_LEN 12
#define THREAD_AUX_X_LEN 4
#define THREAD_WORKING_X_LEN (THREAD_TOTAL_X_LEN - THREAD_AUX_X_LEN)
#define THREAD_TOTAL_Y_LEN 12
#define THREAD_AUX_Y_LEN 4
#define THREAD_WORKING_Y_LEN (THREAD_TOTAL_Y_LEN - THREAD_AUX_Y_LEN)
#define OFFSET(x,y) sIdx + y * THREAD_TOTAL_X_LEN + x
__global__ void Sobel(const unsigned short* in,unsigned char* out, const unsigned int width, const unsigned int height)
{
extern __shared__ float s[];
const unsigned int xPos = (blockIdx.x * THREAD_WORKING_X_LEN + threadIdx.x) - (THREAD_AUX_X_LEN / 2);
const unsigned int yPos = (blockIdx.y * THREAD_WORKING_Y_LEN + threadIdx.y) - (THREAD_AUX_Y_LEN / 2);
const unsigned int inPos = (xPos + yPos * width);
const unsigned int sIdx = (threadIdx.x + threadIdx.y * THREAD_TOTAL_X_LEN);
unsigned int outIt = inPos * 4;
if (xPos < width && yPos < height)
s[sIdx] = in[inPos] / float(USHRT_MAX);
else
s[sIdx] = 0.0f;
__syncthreads();
if ((threadIdx.x - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_X_LEN && (threadIdx.y - (THREAD_AUX_X_LEN / 2)) < THREAD_WORKING_Y_LEN)
{
const float sobelX = (
-1 * s[OFFSET(-2,-2)] -2 * s[OFFSET(-1,-2)] +0 * s[OFFSET(0,-2)] +2 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
-1 * s[OFFSET(-2,-1)] -2 * s[OFFSET(-1,-1)] +0 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +1 * s[OFFSET(2,-1)]
-2 * s[OFFSET(-2, 0)] -4 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +4 * s[OFFSET(1, 0)] +2 * s[OFFSET(2, 0)]
-1 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] +0 * s[OFFSET(0, 1)] +2 * s[OFFSET(1, 1)] +1 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -2 * s[OFFSET(-1, 2)] +0 * s[OFFSET(0, 2)] +2 * s[OFFSET(1, 2)] +1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float sobelY = (
+1 * s[OFFSET(-2,-2)] +1 * s[OFFSET(-1,-2)] +2 * s[OFFSET(0,-2)] +1 * s[OFFSET(1,-2)] +1 * s[OFFSET(2,-2)]
+2 * s[OFFSET(-2,-1)] +2 * s[OFFSET(-1,-1)] +4 * s[OFFSET(0,-1)] +2 * s[OFFSET(1,-1)] +2 * s[OFFSET(2,-1)]
+0 * s[OFFSET(-2, 0)] +0 * s[OFFSET(-1, 0)] +0 * s[OFFSET(0, 0)] +0 * s[OFFSET(1, 0)] +0 * s[OFFSET(2, 0)]
-2 * s[OFFSET(-2, 1)] -2 * s[OFFSET(-1, 1)] -4 * s[OFFSET(0, 1)] -2 * s[OFFSET(1, 1)] -2 * s[OFFSET(2, 1)]
-1 * s[OFFSET(-2, 2)] -1 * s[OFFSET(-1, 2)] -2 * s[OFFSET(0, 2)] -1 * s[OFFSET(1, 2)] -1 * s[OFFSET(2, 2)]
)*(512/8)/18;
const float gradientLen = sqrt(sobelX*sobelX + sobelY*sobelY + 1.0f);
const unsigned char xLen = -(sobelX * 128)/gradientLen + 128;
const unsigned char yLen = -(sobelY * 128)/gradientLen + 128;
const unsigned char zLen = (UCHAR_MAX)/gradientLen;
out[outIt++] = xLen;
out[outIt++] = yLen;
out[outIt++] = zLen;
out[outIt] = 255;
}
} | .text
.file "Sobel.hip"
.globl _Z20__device_stub__SobelPKtPhjj # -- Begin function _Z20__device_stub__SobelPKtPhjj
.p2align 4, 0x90
.type _Z20__device_stub__SobelPKtPhjj,@function
_Z20__device_stub__SobelPKtPhjj: # @_Z20__device_stub__SobelPKtPhjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5SobelPKtPhjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__SobelPKtPhjj, .Lfunc_end0-_Z20__device_stub__SobelPKtPhjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5SobelPKtPhjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5SobelPKtPhjj,@object # @_Z5SobelPKtPhjj
.section .rodata,"a",@progbits
.globl _Z5SobelPKtPhjj
.p2align 3, 0x0
_Z5SobelPKtPhjj:
.quad _Z20__device_stub__SobelPKtPhjj
.size _Z5SobelPKtPhjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5SobelPKtPhjj"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__SobelPKtPhjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5SobelPKtPhjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016b3ca_00000000-6_Sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj
.type _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj, @function
_Z29__device_stub__Z5SobelPKtPhjjPKtPhjj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5SobelPKtPhjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj, .-_Z29__device_stub__Z5SobelPKtPhjjPKtPhjj
.globl _Z5SobelPKtPhjj
.type _Z5SobelPKtPhjj, @function
_Z5SobelPKtPhjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5SobelPKtPhjjPKtPhjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5SobelPKtPhjj, .-_Z5SobelPKtPhjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5SobelPKtPhjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5SobelPKtPhjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sobel.hip"
.globl _Z20__device_stub__SobelPKtPhjj # -- Begin function _Z20__device_stub__SobelPKtPhjj
.p2align 4, 0x90
.type _Z20__device_stub__SobelPKtPhjj,@function
_Z20__device_stub__SobelPKtPhjj: # @_Z20__device_stub__SobelPKtPhjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5SobelPKtPhjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__SobelPKtPhjj, .Lfunc_end0-_Z20__device_stub__SobelPKtPhjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5SobelPKtPhjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5SobelPKtPhjj,@object # @_Z5SobelPKtPhjj
.section .rodata,"a",@progbits
.globl _Z5SobelPKtPhjj
.p2align 3, 0x0
_Z5SobelPKtPhjj:
.quad _Z20__device_stub__SobelPKtPhjj
.size _Z5SobelPKtPhjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5SobelPKtPhjj"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__SobelPKtPhjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5SobelPKtPhjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void block_sum_kernel(int *arr, int size, int *block_sums) {
int num_threads = blockDim.x * gridDim.x;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Each thread finds local sum of its assigned area
int my_sum = 0;
__shared__ int smem[128];
while (tid < size) {
my_sum += arr[tid];
tid += num_threads;
}
smem[threadIdx.x] = my_sum;
// Barrier then use parallel reduction to get block sum
__syncthreads();
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
// Block sum added to global arr
if (threadIdx.x == 0) {
block_sums[blockIdx.x] = smem[0];
}
} | code for sm_80
Function : _Z16block_sum_kernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xa30 ; /* 0x000009f000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R6, R0, c[0x0][0x0], R3 ; /* 0x0000000000067a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xa20 ; /* 0x0000098000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R5, R2, c[0x0][0xc], RZ ; /* 0x0000030002057a24 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B1, 0x980 ; /* 0x000008c000017945 */
/* 0x000fe60003800000 */
/*00c0*/ I2F.U32.RP R7, R5 ; /* 0x0000000500077306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a05 */
/*00e0*/ ISETP.NE.U32.AND P2, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe20003f45070 */
/*00f0*/ IMAD.IADD R4, R5, 0x1, R6 ; /* 0x0000000105047824 */
/* 0x000fca00078e0206 */
/*0100*/ LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff047212 */
/* 0x000fc800078e33ff */
/*0110*/ IADD3 R4, R4, c[0x0][0x168], R5 ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe005 */
/*0120*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R8, R7, 0xffffffe, RZ ; /* 0x0ffffffe07087810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD R11, R11, R9, RZ ; /* 0x000000090b0b7224 */
/* 0x002fc800078e02ff */
/*0170*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fcc00078e0008 */
/*0180*/ IMAD.HI.U32 R9, R9, R4, RZ ; /* 0x0000000409097227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R7, RZ, RZ, -R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a09 */
/*01a0*/ IMAD R4, R5, R7, R4 ; /* 0x0000000705047224 */
/* 0x000fca00078e0204 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x0000000104040824 */
/* 0x000fe200078e0a05 */
/*01d0*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109091810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff09a212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*0220*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fce00078ec0ff */
/*0240*/ @!P0 BRA 0x970 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104047824 */
/* 0x000fe200078e0a07 */
/*0260*/ BSSY B0, 0x870 ; /* 0x0000060000007945 */
/* 0x000fe20003800000 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f04270 */
/*0290*/ @!P0 BRA 0x860 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*02b0*/ BSSY B3, 0x640 ; /* 0x0000038000037945 */
/* 0x000fe20003800000 */
/*02c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02d0*/ @!P1 BRA 0x630 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0300*/ IADD3 R10, R5, R6, R5 ; /* 0x00000006050a7210 */
/* 0x000fc60007ffe005 */
/*0310*/ IMAD.WIDE R28, R6, R9, c[0x0][0x160] ; /* 0x00005800061c7625 */
/* 0x000fe200078e0209 */
/*0320*/ IADD3 R10, R5, R10, R5 ; /* 0x0000000a050a7210 */
/* 0x000fc80007ffe005 */
/*0330*/ IADD3 R6, R5.reuse, R10, R5 ; /* 0x0000000a05067210 */
/* 0x040fe20007ffe005 */
/*0340*/ IMAD.WIDE R18, R5.reuse, 0x4, R28 ; /* 0x0000000405127825 */
/* 0x040fe400078e021c */
/*0350*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IADD3 R6, R5.reuse, R6, R5 ; /* 0x0000000605067210 */
/* 0x040fe20007ffe005 */
/*0370*/ IMAD.WIDE R24, R10, R9, c[0x0][0x160] ; /* 0x000058000a187625 */
/* 0x000fe400078e0209 */
/*0380*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0002a4000c1e1900 */
/*0390*/ IMAD.WIDE R12, R5, 0x4, R18 ; /* 0x00000004050c7825 */
/* 0x000fc800078e0212 */
/*03a0*/ IMAD.WIDE R14, R5.reuse, 0x4, R24 ; /* 0x00000004050e7825 */
/* 0x040fe200078e0218 */
/*03b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000726000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R6, R9, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fe200078e0209 */
/*03d0*/ IADD3 R6, R5.reuse, R6, R5 ; /* 0x0000000605067210 */
/* 0x040fe20007ffe005 */
/*03e0*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000b24000c1e1900 */
/*03f0*/ IMAD.WIDE R20, R5.reuse, 0x4, R14 ; /* 0x0000000405147825 */
/* 0x040fe200078e020e */
/*0400*/ IADD3 R6, R5.reuse, R6, R5 ; /* 0x0000000605067210 */
/* 0x040fe20007ffe005 */
/*0410*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000124000c1e1900 */
/*0420*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x008fc400078e020c */
/*0430*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000724000c1e1900 */
/*0440*/ IMAD.WIDE R16, R5.reuse, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x040fe400078e020a */
/*0450*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x020b24000c1e1900 */
/*0460*/ IMAD.WIDE R18, R5, 0x4, R20 ; /* 0x0000000405127825 */
/* 0x002fe400078e0214 */
/*0470*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000324000c1e1900 */
/*0480*/ IMAD.WIDE R12, R6, R9, c[0x0][0x160] ; /* 0x00005800060c7625 */
/* 0x020fc400078e0209 */
/*0490*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000b24000c1e1900 */
/*04a0*/ IMAD.WIDE R14, R5.reuse, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x041fe400078e0210 */
/*04b0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x002124000c1e1900 */
/*04c0*/ IMAD.WIDE R18, R5, 0x4, R12 ; /* 0x0000000405127825 */
/* 0x001fc800078e020c */
/*04d0*/ IMAD.WIDE R16, R5.reuse, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x060fe400078e020e */
/*04e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000164000c1e1900 */
/*04f0*/ IMAD.WIDE R20, R5.reuse, 0x4, R18 ; /* 0x0000000405147825 */
/* 0x048fe400078e0212 */
/*0500*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000f68000c1e1900 */
/*0510*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x0010e4000c1e1900 */
/*0530*/ IMAD.WIDE R12, R5, 0x4, R20 ; /* 0x00000004050c7825 */
/* 0x001fc400078e0214 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee8000c1e1900 */
/*0550*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0580*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fc80007ffe005 */
/*0590*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fe40007ffe005 */
/*05a0*/ IADD3 R27, R27, R28, R8 ; /* 0x0000001c1b1b7210 */
/* 0x004fc80007ffe008 */
/*05b0*/ IADD3 R25, R25, R26, R27 ; /* 0x0000001a19197210 */
/* 0x010fc80007ffe01b */
/*05c0*/ IADD3 R23, R23, R24, R25 ; /* 0x0000001817177210 */
/* 0x000fc80007ffe019 */
/*05d0*/ IADD3 R11, R11, R22, R23 ; /* 0x000000160b0b7210 */
/* 0x000fc80007ffe017 */
/*05e0*/ IADD3 R9, R9, R10, R11 ; /* 0x0000000a09097210 */
/* 0x000fc80007ffe00b */
/*05f0*/ IADD3 R9, R29, R14, R9 ; /* 0x0000000e1d097210 */
/* 0x020fc80007ffe009 */
/*0600*/ IADD3 R9, R18, R15, R9 ; /* 0x0000000f12097210 */
/* 0x008fc80007ffe009 */
/*0610*/ IADD3 R8, R13, R20, R9 ; /* 0x000000140d087210 */
/* 0x000fe20007ffe009 */
/*0620*/ @P1 BRA 0x2f0 ; /* 0xfffffcc000001947 */
/* 0x000fea000383ffff */
/*0630*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fe20003f24270 */
/*0650*/ BSSY B3, 0x830 ; /* 0x000001d000037945 */
/* 0x000fd80003800000 */
/*0660*/ @!P1 BRA 0x820 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0680*/ IADD3 R10, R5, R6, R5 ; /* 0x00000006050a7210 */
/* 0x000fc60007ffe005 */
/*0690*/ IMAD.WIDE R24, R6, R15, c[0x0][0x160] ; /* 0x0000580006187625 */
/* 0x000fe200078e020f */
/*06a0*/ IADD3 R6, R5, R10, R5 ; /* 0x0000000a05067210 */
/* 0x000fc80007ffe005 */
/*06b0*/ LDG.E R9, [R24.64] ; /* 0x0000000418097981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.WIDE R20, R5, 0x4, R24 ; /* 0x0000000405147825 */
/* 0x000fc800078e0218 */
/*06d0*/ IMAD.WIDE R14, R6, R15, c[0x0][0x160] ; /* 0x00005800060e7625 */
/* 0x000fc800078e020f */
/*06e0*/ IMAD.WIDE R10, R5.reuse, 0x4, R20 ; /* 0x00000004050a7825 */
/* 0x040fe400078e0214 */
/*06f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*0700*/ IMAD.WIDE R12, R5.reuse, 0x4, R14 ; /* 0x00000004050c7825 */
/* 0x040fe400078e020e */
/*0710*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1900 */
/*0720*/ IMAD.WIDE R16, R5.reuse, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x040fe400078e020a */
/*0730*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f24000c1e1900 */
/*0740*/ IMAD.WIDE R18, R5, 0x4, R12 ; /* 0x0000000405127825 */
/* 0x000fc400078e020c */
/*0750*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0760*/ IMAD.WIDE R22, R5.reuse, 0x4, R18 ; /* 0x0000000405167825 */
/* 0x040fe200078e0212 */
/*0770*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0780*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fc40007ffe005 */
/*07b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07c0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fe40007ffe005 */
/*07e0*/ IADD3 R9, R20, R9, R8 ; /* 0x0000000914097210 */
/* 0x004fc80007ffe008 */
/*07f0*/ IADD3 R9, R16, R10, R9 ; /* 0x0000000a10097210 */
/* 0x010fc80007ffe009 */
/*0800*/ IADD3 R9, R12, R14, R9 ; /* 0x0000000e0c097210 */
/* 0x008fc80007ffe009 */
/*0810*/ IADD3 R8, R22, R18, R9 ; /* 0x0000001216087210 */
/* 0x020fe40007ffe009 */
/*0820*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0840*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0850*/ @!P0 BRA 0x970 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0880*/ IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fcc00078e020b */
/*0890*/ IMAD.WIDE R12, R5.reuse, 0x4, R10 ; /* 0x00000004050c7825 */
/* 0x040fe400078e020a */
/*08a0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ IMAD.WIDE R14, R5.reuse, 0x4, R12 ; /* 0x00000004050e7825 */
/* 0x040fe400078e020c */
/*08c0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*08d0*/ IMAD.WIDE R16, R5, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x000fc400078e020e */
/*08e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*0900*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0920*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fc80007ffe005 */
/*0930*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fe40007ffe005 */
/*0940*/ IADD3 R8, R12, R11, R8 ; /* 0x0000000b0c087210 */
/* 0x004fc80007ffe008 */
/*0950*/ IADD3 R8, R16, R15, R8 ; /* 0x0000000f10087210 */
/* 0x008fe20007ffe008 */
/*0960*/ @P0 BRA 0x870 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0970*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0990*/ @!P0 BRA 0xa20 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*09b0*/ IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fca00078e020b */
/*09c0*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x0000a2000c1e1900 */
/*09d0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*09e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*09f0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x001fc800078e020a */
/*0a00*/ IMAD.IADD R8, R9, 0x1, R8 ; /* 0x0000000109087824 */
/* 0x004fd000078e0208 */
/*0a10*/ @P0 BRA 0x9c0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0a40*/ SHF.R.U32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011602 */
/*0a50*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x0001e80000004800 */
/*0a60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a70*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0a80*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fd60003f05270 */
/*0a90*/ @!P1 BRA 0xb60 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0002 */
/*0ab0*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x000fc600078e00ff */
/*0ac0*/ ISETP.GE.U32.AND P1, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f26070 */
/*0ad0*/ @!P1 IMAD R6, R4, 0x4, R2 ; /* 0x0000000404069824 */
/* 0x000fe200078e0202 */
/*0ae0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe20000004800 */
/*0af0*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*0b00*/ @!P1 LDS R6, [R6] ; /* 0x0000000006069984 */
/* 0x000e240000000800 */
/*0b10*/ @!P1 IMAD.IADD R8, R5, 0x1, R6 ; /* 0x0000000105089824 */
/* 0x001fca00078e0206 */
/*0b20*/ @!P1 STS [R3.X4], R8 ; /* 0x0000000803009388 */
/* 0x0001e80000004800 */
/*0b30*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b40*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*0b50*/ @P1 BRA 0xac0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0b60*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0b70*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0b80*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0b90*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*0ba0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.