system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void block_sum_kernel(int *arr, int size, int *block_sums) {
int num_threads = blockDim.x * gridDim.x;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Each thread finds local sum of its assigned area
int my_sum = 0;
__shared__ int smem[128];
while (tid < size) {
my_sum += arr[tid];
tid += num_threads;
}
smem[threadIdx.x] = my_sum;
// Barrier then use parallel reduction to get block sum
__syncthreads();
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
// Block sum added to global arr
if (threadIdx.x == 0) {
block_sums[blockIdx.x] = smem[0];
}
} | .file "tmpxft_0009a054_00000000-6_block_sum_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_
.type _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_, @function
_Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16block_sum_kernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_, .-_Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_
.globl _Z16block_sum_kernelPiiS_
.type _Z16block_sum_kernelPiiS_, @function
_Z16block_sum_kernelPiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16block_sum_kernelPiiS_, .-_Z16block_sum_kernelPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16block_sum_kernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16block_sum_kernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void block_sum_kernel(int *arr, int size, int *block_sums) {
int num_threads = blockDim.x * gridDim.x;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Each thread finds local sum of its assigned area
int my_sum = 0;
__shared__ int smem[128];
while (tid < size) {
my_sum += arr[tid];
tid += num_threads;
}
smem[threadIdx.x] = my_sum;
// Barrier then use parallel reduction to get block sum
__syncthreads();
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
// Block sum added to global arr
if (threadIdx.x == 0) {
block_sums[blockIdx.x] = smem[0];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void block_sum_kernel(int *arr, int size, int *block_sums) {
int num_threads = blockDim.x * gridDim.x;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Each thread finds local sum of its assigned area
int my_sum = 0;
__shared__ int smem[128];
while (tid < size) {
my_sum += arr[tid];
tid += num_threads;
}
smem[threadIdx.x] = my_sum;
// Barrier then use parallel reduction to get block sum
__syncthreads();
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
// Block sum added to global arr
if (threadIdx.x == 0) {
block_sums[blockIdx.x] = smem[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void block_sum_kernel(int *arr, int size, int *block_sums) {
int num_threads = blockDim.x * gridDim.x;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Each thread finds local sum of its assigned area
int my_sum = 0;
__shared__ int smem[128];
while (tid < size) {
my_sum += arr[tid];
tid += num_threads;
}
smem[threadIdx.x] = my_sum;
// Barrier then use parallel reduction to get block sum
__syncthreads();
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
// Block sum added to global arr
if (threadIdx.x == 0) {
block_sums[blockIdx.x] = smem[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16block_sum_kernelPiiS_
.globl _Z16block_sum_kernelPiiS_
.p2align 8
.type _Z16block_sum_kernelPiiS_,@function
_Z16block_sum_kernelPiiS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_mov_b32 s4, s15
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s5
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_mov_b32 s3, 0
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s10, v1
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s5, 2
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s2
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s2, s5, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s2, v0, 2
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16block_sum_kernelPiiS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16block_sum_kernelPiiS_, .Lfunc_end0-_Z16block_sum_kernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16block_sum_kernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16block_sum_kernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void block_sum_kernel(int *arr, int size, int *block_sums) {
int num_threads = blockDim.x * gridDim.x;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// Each thread finds local sum of its assigned area
int my_sum = 0;
__shared__ int smem[128];
while (tid < size) {
my_sum += arr[tid];
tid += num_threads;
}
smem[threadIdx.x] = my_sum;
// Barrier then use parallel reduction to get block sum
__syncthreads();
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
// Block sum added to global arr
if (threadIdx.x == 0) {
block_sums[blockIdx.x] = smem[0];
}
} | .text
.file "block_sum_kernel.hip"
.globl _Z31__device_stub__block_sum_kernelPiiS_ # -- Begin function _Z31__device_stub__block_sum_kernelPiiS_
.p2align 4, 0x90
.type _Z31__device_stub__block_sum_kernelPiiS_,@function
_Z31__device_stub__block_sum_kernelPiiS_: # @_Z31__device_stub__block_sum_kernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16block_sum_kernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__block_sum_kernelPiiS_, .Lfunc_end0-_Z31__device_stub__block_sum_kernelPiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16block_sum_kernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16block_sum_kernelPiiS_,@object # @_Z16block_sum_kernelPiiS_
.section .rodata,"a",@progbits
.globl _Z16block_sum_kernelPiiS_
.p2align 3, 0x0
_Z16block_sum_kernelPiiS_:
.quad _Z31__device_stub__block_sum_kernelPiiS_
.size _Z16block_sum_kernelPiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16block_sum_kernelPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__block_sum_kernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16block_sum_kernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16block_sum_kernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0xa30 ; /* 0x000009f000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD R6, R0, c[0x0][0x0], R3 ; /* 0x0000000000067a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xa20 ; /* 0x0000098000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R5, R2, c[0x0][0xc], RZ ; /* 0x0000030002057a24 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B1, 0x980 ; /* 0x000008c000017945 */
/* 0x000fe60003800000 */
/*00c0*/ I2F.U32.RP R7, R5 ; /* 0x0000000500077306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a05 */
/*00e0*/ ISETP.NE.U32.AND P2, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe20003f45070 */
/*00f0*/ IMAD.IADD R4, R5, 0x1, R6 ; /* 0x0000000105047824 */
/* 0x000fca00078e0206 */
/*0100*/ LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff047212 */
/* 0x000fc800078e33ff */
/*0110*/ IADD3 R4, R4, c[0x0][0x168], R5 ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe005 */
/*0120*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R8, R7, 0xffffffe, RZ ; /* 0x0ffffffe07087810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD R11, R11, R9, RZ ; /* 0x000000090b0b7224 */
/* 0x002fc800078e02ff */
/*0170*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fcc00078e0008 */
/*0180*/ IMAD.HI.U32 R9, R9, R4, RZ ; /* 0x0000000409097227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R7, RZ, RZ, -R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a09 */
/*01a0*/ IMAD R4, R5, R7, R4 ; /* 0x0000000705047224 */
/* 0x000fca00078e0204 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x0000000104040824 */
/* 0x000fe200078e0a05 */
/*01d0*/ @P0 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109090810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109091810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R9, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff09a212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*0220*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fce00078ec0ff */
/*0240*/ @!P0 BRA 0x970 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104047824 */
/* 0x000fe200078e0a07 */
/*0260*/ BSSY B0, 0x870 ; /* 0x0000060000007945 */
/* 0x000fe20003800000 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f04270 */
/*0290*/ @!P0 BRA 0x860 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*02b0*/ BSSY B3, 0x640 ; /* 0x0000038000037945 */
/* 0x000fe20003800000 */
/*02c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02d0*/ @!P1 BRA 0x630 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*02e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0300*/ IADD3 R10, R5, R6, R5 ; /* 0x00000006050a7210 */
/* 0x000fc60007ffe005 */
/*0310*/ IMAD.WIDE R28, R6, R9, c[0x0][0x160] ; /* 0x00005800061c7625 */
/* 0x000fe200078e0209 */
/*0320*/ IADD3 R10, R5, R10, R5 ; /* 0x0000000a050a7210 */
/* 0x000fc80007ffe005 */
/*0330*/ IADD3 R6, R5.reuse, R10, R5 ; /* 0x0000000a05067210 */
/* 0x040fe20007ffe005 */
/*0340*/ IMAD.WIDE R18, R5.reuse, 0x4, R28 ; /* 0x0000000405127825 */
/* 0x040fe400078e021c */
/*0350*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IADD3 R6, R5.reuse, R6, R5 ; /* 0x0000000605067210 */
/* 0x040fe20007ffe005 */
/*0370*/ IMAD.WIDE R24, R10, R9, c[0x0][0x160] ; /* 0x000058000a187625 */
/* 0x000fe400078e0209 */
/*0380*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0002a4000c1e1900 */
/*0390*/ IMAD.WIDE R12, R5, 0x4, R18 ; /* 0x00000004050c7825 */
/* 0x000fc800078e0212 */
/*03a0*/ IMAD.WIDE R14, R5.reuse, 0x4, R24 ; /* 0x00000004050e7825 */
/* 0x040fe200078e0218 */
/*03b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000726000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R6, R9, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fe200078e0209 */
/*03d0*/ IADD3 R6, R5.reuse, R6, R5 ; /* 0x0000000605067210 */
/* 0x040fe20007ffe005 */
/*03e0*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000b24000c1e1900 */
/*03f0*/ IMAD.WIDE R20, R5.reuse, 0x4, R14 ; /* 0x0000000405147825 */
/* 0x040fe200078e020e */
/*0400*/ IADD3 R6, R5.reuse, R6, R5 ; /* 0x0000000605067210 */
/* 0x040fe20007ffe005 */
/*0410*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000124000c1e1900 */
/*0420*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x008fc400078e020c */
/*0430*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000724000c1e1900 */
/*0440*/ IMAD.WIDE R16, R5.reuse, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x040fe400078e020a */
/*0450*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x020b24000c1e1900 */
/*0460*/ IMAD.WIDE R18, R5, 0x4, R20 ; /* 0x0000000405127825 */
/* 0x002fe400078e0214 */
/*0470*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000324000c1e1900 */
/*0480*/ IMAD.WIDE R12, R6, R9, c[0x0][0x160] ; /* 0x00005800060c7625 */
/* 0x020fc400078e0209 */
/*0490*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000b24000c1e1900 */
/*04a0*/ IMAD.WIDE R14, R5.reuse, 0x4, R16 ; /* 0x00000004050e7825 */
/* 0x041fe400078e0210 */
/*04b0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x002124000c1e1900 */
/*04c0*/ IMAD.WIDE R18, R5, 0x4, R12 ; /* 0x0000000405127825 */
/* 0x001fc800078e020c */
/*04d0*/ IMAD.WIDE R16, R5.reuse, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x060fe400078e020e */
/*04e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000164000c1e1900 */
/*04f0*/ IMAD.WIDE R20, R5.reuse, 0x4, R18 ; /* 0x0000000405147825 */
/* 0x048fe400078e0212 */
/*0500*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000f68000c1e1900 */
/*0510*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x0010e4000c1e1900 */
/*0530*/ IMAD.WIDE R12, R5, 0x4, R20 ; /* 0x00000004050c7825 */
/* 0x001fc400078e0214 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee8000c1e1900 */
/*0550*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee2000c1e1900 */
/*0560*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0580*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fc80007ffe005 */
/*0590*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fe40007ffe005 */
/*05a0*/ IADD3 R27, R27, R28, R8 ; /* 0x0000001c1b1b7210 */
/* 0x004fc80007ffe008 */
/*05b0*/ IADD3 R25, R25, R26, R27 ; /* 0x0000001a19197210 */
/* 0x010fc80007ffe01b */
/*05c0*/ IADD3 R23, R23, R24, R25 ; /* 0x0000001817177210 */
/* 0x000fc80007ffe019 */
/*05d0*/ IADD3 R11, R11, R22, R23 ; /* 0x000000160b0b7210 */
/* 0x000fc80007ffe017 */
/*05e0*/ IADD3 R9, R9, R10, R11 ; /* 0x0000000a09097210 */
/* 0x000fc80007ffe00b */
/*05f0*/ IADD3 R9, R29, R14, R9 ; /* 0x0000000e1d097210 */
/* 0x020fc80007ffe009 */
/*0600*/ IADD3 R9, R18, R15, R9 ; /* 0x0000000f12097210 */
/* 0x008fc80007ffe009 */
/*0610*/ IADD3 R8, R13, R20, R9 ; /* 0x000000140d087210 */
/* 0x000fe20007ffe009 */
/*0620*/ @P1 BRA 0x2f0 ; /* 0xfffffcc000001947 */
/* 0x000fea000383ffff */
/*0630*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fe20003f24270 */
/*0650*/ BSSY B3, 0x830 ; /* 0x000001d000037945 */
/* 0x000fd80003800000 */
/*0660*/ @!P1 BRA 0x820 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0680*/ IADD3 R10, R5, R6, R5 ; /* 0x00000006050a7210 */
/* 0x000fc60007ffe005 */
/*0690*/ IMAD.WIDE R24, R6, R15, c[0x0][0x160] ; /* 0x0000580006187625 */
/* 0x000fe200078e020f */
/*06a0*/ IADD3 R6, R5, R10, R5 ; /* 0x0000000a05067210 */
/* 0x000fc80007ffe005 */
/*06b0*/ LDG.E R9, [R24.64] ; /* 0x0000000418097981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.WIDE R20, R5, 0x4, R24 ; /* 0x0000000405147825 */
/* 0x000fc800078e0218 */
/*06d0*/ IMAD.WIDE R14, R6, R15, c[0x0][0x160] ; /* 0x00005800060e7625 */
/* 0x000fc800078e020f */
/*06e0*/ IMAD.WIDE R10, R5.reuse, 0x4, R20 ; /* 0x00000004050a7825 */
/* 0x040fe400078e0214 */
/*06f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*0700*/ IMAD.WIDE R12, R5.reuse, 0x4, R14 ; /* 0x00000004050c7825 */
/* 0x040fe400078e020e */
/*0710*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1900 */
/*0720*/ IMAD.WIDE R16, R5.reuse, 0x4, R10 ; /* 0x0000000405107825 */
/* 0x040fe400078e020a */
/*0730*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f24000c1e1900 */
/*0740*/ IMAD.WIDE R18, R5, 0x4, R12 ; /* 0x0000000405127825 */
/* 0x000fc400078e020c */
/*0750*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0760*/ IMAD.WIDE R22, R5.reuse, 0x4, R18 ; /* 0x0000000405167825 */
/* 0x040fe200078e0212 */
/*0770*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0780*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fc40007ffe005 */
/*07b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07c0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fe40007ffe005 */
/*07e0*/ IADD3 R9, R20, R9, R8 ; /* 0x0000000914097210 */
/* 0x004fc80007ffe008 */
/*07f0*/ IADD3 R9, R16, R10, R9 ; /* 0x0000000a10097210 */
/* 0x010fc80007ffe009 */
/*0800*/ IADD3 R9, R12, R14, R9 ; /* 0x0000000e0c097210 */
/* 0x008fc80007ffe009 */
/*0810*/ IADD3 R8, R22, R18, R9 ; /* 0x0000001216087210 */
/* 0x020fe40007ffe009 */
/*0820*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0840*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0850*/ @!P0 BRA 0x970 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0880*/ IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fcc00078e020b */
/*0890*/ IMAD.WIDE R12, R5.reuse, 0x4, R10 ; /* 0x00000004050c7825 */
/* 0x040fe400078e020a */
/*08a0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ IMAD.WIDE R14, R5.reuse, 0x4, R12 ; /* 0x00000004050e7825 */
/* 0x040fe400078e020c */
/*08c0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*08d0*/ IMAD.WIDE R16, R5, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x000fc400078e020e */
/*08e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*0900*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0920*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fc80007ffe005 */
/*0930*/ IADD3 R6, R5, R6, R5 ; /* 0x0000000605067210 */
/* 0x000fe40007ffe005 */
/*0940*/ IADD3 R8, R12, R11, R8 ; /* 0x0000000b0c087210 */
/* 0x004fc80007ffe008 */
/*0950*/ IADD3 R8, R16, R15, R8 ; /* 0x0000000f10087210 */
/* 0x008fe20007ffe008 */
/*0960*/ @P0 BRA 0x870 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0970*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0990*/ @!P0 BRA 0xa20 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*09b0*/ IMAD.WIDE R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fca00078e020b */
/*09c0*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x0000a2000c1e1900 */
/*09d0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*09e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*09f0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x001fc800078e020a */
/*0a00*/ IMAD.IADD R8, R9, 0x1, R8 ; /* 0x0000000109087824 */
/* 0x004fd000078e0208 */
/*0a10*/ @P0 BRA 0x9c0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0a40*/ SHF.R.U32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011602 */
/*0a50*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x0001e80000004800 */
/*0a60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a70*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0a80*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fd60003f05270 */
/*0a90*/ @!P1 BRA 0xb60 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0002 */
/*0ab0*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x000fc600078e00ff */
/*0ac0*/ ISETP.GE.U32.AND P1, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f26070 */
/*0ad0*/ @!P1 IMAD R6, R4, 0x4, R2 ; /* 0x0000000404069824 */
/* 0x000fe200078e0202 */
/*0ae0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe20000004800 */
/*0af0*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*0b00*/ @!P1 LDS R6, [R6] ; /* 0x0000000006069984 */
/* 0x000e240000000800 */
/*0b10*/ @!P1 IMAD.IADD R8, R5, 0x1, R6 ; /* 0x0000000105089824 */
/* 0x001fca00078e0206 */
/*0b20*/ @!P1 STS [R3.X4], R8 ; /* 0x0000000803009388 */
/* 0x0001e80000004800 */
/*0b30*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b40*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*0b50*/ @P1 BRA 0xac0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0b60*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0b70*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0b80*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0b90*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*0ba0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16block_sum_kernelPiiS_
.globl _Z16block_sum_kernelPiiS_
.p2align 8
.type _Z16block_sum_kernelPiiS_,@function
_Z16block_sum_kernelPiiS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_mov_b32 s4, s15
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s5
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_mov_b32 s3, 0
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_2:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s10, v1
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s5, 2
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s2
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s2, s5, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s2, v0, 2
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16block_sum_kernelPiiS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16block_sum_kernelPiiS_, .Lfunc_end0-_Z16block_sum_kernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16block_sum_kernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16block_sum_kernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009a054_00000000-6_block_sum_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_
.type _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_, @function
_Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16block_sum_kernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_, .-_Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_
.globl _Z16block_sum_kernelPiiS_
.type _Z16block_sum_kernelPiiS_, @function
_Z16block_sum_kernelPiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16block_sum_kernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16block_sum_kernelPiiS_, .-_Z16block_sum_kernelPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16block_sum_kernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16block_sum_kernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "block_sum_kernel.hip"
.globl _Z31__device_stub__block_sum_kernelPiiS_ # -- Begin function _Z31__device_stub__block_sum_kernelPiiS_
.p2align 4, 0x90
.type _Z31__device_stub__block_sum_kernelPiiS_,@function
_Z31__device_stub__block_sum_kernelPiiS_: # @_Z31__device_stub__block_sum_kernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16block_sum_kernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__block_sum_kernelPiiS_, .Lfunc_end0-_Z31__device_stub__block_sum_kernelPiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16block_sum_kernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16block_sum_kernelPiiS_,@object # @_Z16block_sum_kernelPiiS_
.section .rodata,"a",@progbits
.globl _Z16block_sum_kernelPiiS_
.p2align 3, 0x0
_Z16block_sum_kernelPiiS_:
.quad _Z31__device_stub__block_sum_kernelPiiS_
.size _Z16block_sum_kernelPiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16block_sum_kernelPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__block_sum_kernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16block_sum_kernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
// nvcc -arch=sm_70 -std=c++14 exemplo5.cu -o exemplo5 && ./exemplo5
struct raw_access {
thrust::minstd_rand rng;
thrust::uniform_real_distribution<double> dist;
raw_access (thrust::uniform_real_distribution<double> dist, thrust::minstd_rand rng) : dist(dist), rng(rng) {};
__device__ __host__
double operator()(const int &i) {
rng.discard(i);
return dist(rng);
}
};
// http://www.cplusplus.com/reference/random/linear_congruential_engine/discard/
int main(){
thrust::minstd_rand rng;
thrust::uniform_real_distribution<double> dist(25, 40);
thrust::device_vector<double> vetor(10, 0);
thrust::counting_iterator<int> iter(0);
raw_access ra(dist, rng);
thrust::transform(iter, iter+vetor.size(), vetor.begin(), ra);
thrust::host_vector<double> host(vetor);
for (auto i = host.begin(); i != host.end(); i++)
{
std::cout << *i << " "; // este acesso é rápido -- CPU
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
// nvcc -arch=sm_70 -std=c++14 exemplo5.cu -o exemplo5 && ./exemplo5
struct raw_access {
thrust::minstd_rand rng;
thrust::uniform_real_distribution<double> dist;
raw_access (thrust::uniform_real_distribution<double> dist, thrust::minstd_rand rng) : dist(dist), rng(rng) {};
__device__ __host__
double operator()(const int &i) {
rng.discard(i);
return dist(rng);
}
};
// http://www.cplusplus.com/reference/random/linear_congruential_engine/discard/
int main(){
thrust::minstd_rand rng;
thrust::uniform_real_distribution<double> dist(25, 40);
thrust::device_vector<double> vetor(10, 0);
thrust::counting_iterator<int> iter(0);
raw_access ra(dist, rng);
thrust::transform(iter, iter+vetor.size(), vetor.begin(), ra);
thrust::host_vector<double> host(vetor);
for (auto i = host.begin(); i != host.end(); i++)
{
std::cout << *i << " "; // este acesso é rápido -- CPU
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
// nvcc -arch=sm_70 -std=c++14 exemplo5.cu -o exemplo5 && ./exemplo5
struct raw_access {
thrust::minstd_rand rng;
thrust::uniform_real_distribution<double> dist;
raw_access (thrust::uniform_real_distribution<double> dist, thrust::minstd_rand rng) : dist(dist), rng(rng) {};
__device__ __host__
double operator()(const int &i) {
rng.discard(i);
return dist(rng);
}
};
// http://www.cplusplus.com/reference/random/linear_congruential_engine/discard/
int main(){
thrust::minstd_rand rng;
thrust::uniform_real_distribution<double> dist(25, 40);
thrust::device_vector<double> vetor(10, 0);
thrust::counting_iterator<int> iter(0);
raw_access ra(dist, rng);
thrust::transform(iter, iter+vetor.size(), vetor.begin(), ra);
thrust::host_vector<double> host(vetor);
for (auto i = host.begin(); i != host.end(); i++)
{
std::cout << *i << " "; // este acesso é rápido -- CPU
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_lshl_b64 s[0:1], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
flat_store_b64 v[0:1], v[2:3]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_:
s_clause 0x2
s_load_b128 s[16:19], s[0:1], 0x30
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s7, s2, s18
s_addc_u32 s8, 0, s19
s_sub_u32 s4, s16, s7
s_subb_u32 s5, s17, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s2, 0x100, s[4:5]
s_and_b32 s2, s2, exec_lo
s_cselect_b32 s4, s4, 0x100
s_mov_b32 s2, 0
s_cmpk_lg_i32 s4, 0x100
s_cbranch_scc0 .LBB1_7
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_mov_b32 s9, 0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB1_12
v_add_co_u32 v1, s2, s7, v0
v_mov_b32_e32 v5, 1
v_add_co_ci_u32_e64 v2, null, s8, 0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, s6, v1
s_mov_b32 s12, 0
s_mov_b32 s11, exec_lo
v_cmpx_ne_u32_e32 0, v3
s_cbranch_execz .LBB1_11
v_mov_b32_e32 v5, 1
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b64 s[4:5], 0xbc8f
s_branch .LBB1_5
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s13
s_mul_i32 s2, s4, s5
s_mul_hi_u32 s5, s4, s4
s_movk_i32 s13, 0x401
s_add_i32 s5, s5, s2
s_mul_i32 s4, s4, s4
s_add_i32 s2, s5, s2
s_add_u32 s5, 0x402, s13
s_addc_u32 s13, 0, 0
v_add_co_u32 v7, s5, s5, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s5, 0
v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
s_addc_u32 s13, s13, 1
v_readfirstlane_b32 s5, v7
s_mul_i32 s14, s13, 0x80000001
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s15, s5, 0x80000001
s_mul_i32 s16, s5, 0x80000001
s_sub_i32 s15, s15, s5
s_mul_hi_u32 s17, s5, s16
s_add_i32 s15, s15, s14
s_mul_hi_u32 s18, s13, s16
s_mul_i32 s14, s13, s16
s_mul_hi_u32 s16, s5, s15
s_mul_i32 s5, s5, s15
s_mul_hi_u32 s19, s13, s15
s_add_u32 s5, s17, s5
s_addc_u32 s16, 0, s16
s_add_u32 s5, s5, s14
s_mul_i32 s15, s13, s15
s_addc_u32 s5, s16, s18
s_addc_u32 s14, s19, 0
s_add_u32 s5, s5, s15
s_addc_u32 s14, 0, s14
v_add_co_u32 v7, s5, v7, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
s_addc_u32 s5, s13, s14
v_readfirstlane_b32 s13, v7
s_mul_i32 s15, s4, s5
s_mul_hi_u32 s14, s4, s5
s_mul_hi_u32 s16, s2, s5
s_mul_i32 s5, s2, s5
s_mul_hi_u32 s17, s4, s13
s_mul_hi_u32 s18, s2, s13
s_mul_i32 s13, s2, s13
s_add_u32 s15, s17, s15
s_addc_u32 s14, 0, s14
s_add_u32 s13, s15, s13
s_addc_u32 s13, s14, s18
s_addc_u32 s14, s16, 0
s_add_u32 s5, s13, s5
s_addc_u32 s13, 0, s14
s_mul_hi_u32 s14, s5, 0x7fffffff
s_mul_i32 s5, s5, 0x7fffffff
s_mul_i32 s13, s13, 0x7fffffff
v_sub_co_u32 v7, s4, s4, s5
s_add_i32 s14, s14, s13
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v8, s4, v7, 0x7fffffff
s_subb_u32 s2, s2, s14
s_cmp_lg_u32 s4, 0
v_readfirstlane_b32 s16, v7
v_sub_co_u32 v9, s4, v8, 0x7fffffff
v_readfirstlane_b32 s5, v8
s_subb_u32 s13, s2, 0
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_2)
v_readfirstlane_b32 s15, v9
s_subb_u32 s4, s13, 0
s_cmp_gt_u32 s5, 0x7ffffffe
v_lshrrev_b64 v[7:8], 1, v[3:4]
s_cselect_b32 s14, -1, 0
s_cmp_eq_u32 s13, 0
s_cselect_b32 s14, s14, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s14, 0
v_dual_mov_b32 v3, v7 :: v_dual_mov_b32 v4, v8
s_cselect_b32 s4, s4, s13
s_cselect_b32 s13, s15, s5
s_cmp_gt_u32 s16, 0x7ffffffe
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
s_cselect_b32 s5, s4, s2
s_cselect_b32 s4, s13, s16
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB1_10
.LBB1_5:
v_and_b32_e32 v7, 1, v3
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v7
s_cbranch_execz .LBB1_4
s_movk_i32 s2, 0x401
v_mul_lo_u32 v9, s5, v5
s_add_u32 s2, 0x402, s2
s_addc_u32 s14, 0, 0
v_add_co_u32 v8, s2, s2, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_mul_lo_u32 v10, s4, v6
s_addc_u32 s14, s14, 1
v_readfirstlane_b32 s2, v8
s_mul_i32 s15, s14, 0x80000001
v_mad_u64_u32 v[6:7], null, s4, v5, 0
s_delay_alu instid0(VALU_DEP_2)
s_mul_hi_u32 s16, s2, 0x80000001
s_mul_i32 s17, s2, 0x80000001
s_sub_i32 s16, s16, s2
s_mul_hi_u32 s18, s2, s17
s_add_i32 s16, s16, s15
s_mul_i32 s15, s14, s17
s_mul_hi_u32 s19, s2, s16
s_mul_i32 s2, s2, s16
s_mul_hi_u32 s17, s14, s17
s_add_u32 s2, s18, s2
s_addc_u32 s18, 0, s19
s_mul_hi_u32 s20, s14, s16
s_add_u32 s2, s2, s15
s_addc_u32 s2, s18, s17
s_mul_i32 s15, s14, s16
s_addc_u32 s16, s20, 0
s_add_u32 s2, s2, s15
s_addc_u32 s15, 0, s16
v_add_co_u32 v5, s2, v8, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_add3_u32 v13, v7, v10, v9
s_addc_u32 s2, s14, s15
v_mul_hi_u32 v14, v6, v5
v_mad_u64_u32 v[7:8], null, v6, s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[9:10], null, v13, v5, 0
v_mad_u64_u32 v[11:12], null, v13, s2, 0
v_add_co_u32 v5, vcc_lo, v14, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
v_mad_u64_u32 v[7:8], null, v5, 0x7fffffff, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v5, v8
v_mad_u64_u32 v[8:9], null, v10, 0x7fffffff, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v5, vcc_lo, v6, v7
v_sub_co_ci_u32_e32 v6, vcc_lo, v13, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v7, vcc_lo, v5, 0x7fffffff
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v7
v_cmp_eq_u32_e64 s2, 0, v6
v_cndmask_b32_e64 v9, 0, -1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v5
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, -1, v9, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, 0x7fffffff
v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v8, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
v_cndmask_b32_e64 v9, -1, v10, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v8, v8, v12 :: v_dual_cndmask_b32 v7, v7, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v5, v5, v7
s_branch .LBB1_4
.LBB1_7:
s_cbranch_execnz .LBB1_13
.LBB1_8:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_20
.LBB1_9:
v_xor_b32_e32 v0, 0x7fffffff, v4
v_sub_nc_u32_e32 v4, 0, v4
s_mov_b32 s3, 0x41dfffff
s_mov_b32 s2, 0xff800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v4, v0, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x8
v_add3_u32 v0, v3, v0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[3:4], v0
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_div_scale_f64 v[5:6], null, s[2:3], s[2:3], v[3:4]
v_div_scale_f64 v[11:12], vcc_lo, v[3:4], s[2:3], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f64 v[3:4], v[5:6], s[2:3], v[3:4]
v_add_f64 v[5:6], s[6:7], -s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[5:6], v[3:4], s[4:5]
flat_store_b64 v[0:1], v[3:4]
s_endpgm
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s12
.LBB1_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
s_movk_i32 s4, 0x401
v_mad_u64_u32 v[3:4], null, v5, s3, 0
s_add_u32 s4, 0x402, s4
s_addc_u32 s5, 0, 0
v_add_co_u32 v5, s4, s4, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_mov_b32 s2, exec_lo
s_addc_u32 s5, s5, 1
v_readfirstlane_b32 s4, v5
s_mul_i32 s11, s5, 0x80000001
v_mad_u64_u32 v[7:8], null, v6, s3, v[4:5]
s_delay_alu instid0(VALU_DEP_2)
s_mul_hi_u32 s12, s4, 0x80000001
s_mul_i32 s13, s4, 0x80000001
s_sub_i32 s12, s12, s4
s_mul_hi_u32 s14, s4, s13
s_add_i32 s12, s12, s11
s_mul_i32 s11, s5, s13
s_mul_hi_u32 s15, s4, s12
s_mul_i32 s4, s4, s12
s_mul_hi_u32 s13, s5, s13
s_add_u32 s4, s14, s4
s_addc_u32 s14, 0, s15
s_mul_hi_u32 s16, s5, s12
s_add_u32 s4, s4, s11
s_addc_u32 s4, s14, s13
s_mul_i32 s11, s5, s12
s_addc_u32 s12, s16, 0
s_add_u32 s4, s4, s11
s_addc_u32 s11, 0, s12
v_add_co_u32 v10, s4, v5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s5, s11
v_mul_hi_u32 v6, v3, v10
v_mad_u64_u32 v[4:5], null, v3, s4, 0
v_mad_u64_u32 v[8:9], null, v7, v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v5, vcc_lo
v_mad_u64_u32 v[4:5], null, v7, s4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v8
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v5, vcc_lo
v_mad_u64_u32 v[4:5], null, v6, 0x7fffffff, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v10, 0x7fffffff, v[5:6]
v_sub_co_u32 v3, vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v4, vcc_lo, v7, v8, vcc_lo
v_sub_co_u32 v5, vcc_lo, v3, 0x7fffffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v5
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v3
v_cndmask_b32_e64 v8, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v6, -1, v7 :: v_dual_add_nc_u32 v7, 0x80000001, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v4, -1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, 0xbc8f1391
v_lshrrev_b32_e32 v4, 15, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v5, 0xadc8, v4
v_mul_u32_u24_e32 v4, 0xd47, v4
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 0xbc8f
v_cmp_lt_u32_e32 vcc_lo, v3, v4
s_and_b32 s4, vcc_lo, exec_lo
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB1_8
.LBB1_13:
v_add_co_u32 v1, s2, s7, v0
v_mov_b32_e32 v5, 1
v_add_co_ci_u32_e64 v2, null, s8, 0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, s6, v1
s_mov_b32 s7, 0
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e32 0, v3
s_cbranch_execz .LBB1_19
v_mov_b32_e32 v5, 1
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b64 s[4:5], 0xbc8f
s_branch .LBB1_16
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s8
s_mul_i32 s2, s4, s5
s_mul_hi_u32 s5, s4, s4
s_movk_i32 s8, 0x401
s_add_i32 s5, s5, s2
s_mul_i32 s4, s4, s4
s_add_i32 s2, s5, s2
s_add_u32 s5, 0x402, s8
s_addc_u32 s8, 0, 0
v_add_co_u32 v0, s5, s5, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s5, 0
v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
s_addc_u32 s8, s8, 1
v_readfirstlane_b32 s5, v0
s_mul_i32 s9, s8, 0x80000001
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s10, s5, 0x80000001
s_mul_i32 s11, s5, 0x80000001
s_sub_i32 s10, s10, s5
s_mul_hi_u32 s12, s5, s11
s_add_i32 s10, s10, s9
s_mul_hi_u32 s13, s8, s11
s_mul_i32 s9, s8, s11
s_mul_hi_u32 s11, s5, s10
s_mul_i32 s5, s5, s10
s_mul_hi_u32 s14, s8, s10
s_add_u32 s5, s12, s5
s_addc_u32 s11, 0, s11
s_add_u32 s5, s5, s9
s_mul_i32 s10, s8, s10
s_addc_u32 s5, s11, s13
s_addc_u32 s9, s14, 0
s_add_u32 s5, s5, s10
s_addc_u32 s9, 0, s9
v_add_co_u32 v0, s5, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
s_addc_u32 s5, s8, s9
v_readfirstlane_b32 s8, v0
s_mul_i32 s10, s4, s5
s_mul_hi_u32 s9, s4, s5
s_mul_hi_u32 s11, s2, s5
s_mul_i32 s5, s2, s5
s_mul_hi_u32 s12, s4, s8
s_mul_hi_u32 s13, s2, s8
s_mul_i32 s8, s2, s8
s_add_u32 s10, s12, s10
s_addc_u32 s9, 0, s9
s_add_u32 s8, s10, s8
s_addc_u32 s8, s9, s13
s_addc_u32 s9, s11, 0
s_add_u32 s5, s8, s5
s_addc_u32 s8, 0, s9
s_mul_hi_u32 s9, s5, 0x7fffffff
s_mul_i32 s5, s5, 0x7fffffff
s_mul_i32 s8, s8, 0x7fffffff
v_sub_co_u32 v0, s4, s4, s5
s_add_i32 s9, s9, s8
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v7, s4, v0, 0x7fffffff
s_subb_u32 s2, s2, s9
s_cmp_lg_u32 s4, 0
v_readfirstlane_b32 s11, v0
v_sub_co_u32 v8, s4, v7, 0x7fffffff
v_readfirstlane_b32 s5, v7
s_subb_u32 s8, s2, 0
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_2)
v_readfirstlane_b32 s10, v8
s_subb_u32 s4, s8, 0
s_cmp_gt_u32 s5, 0x7ffffffe
v_lshrrev_b64 v[7:8], 1, v[3:4]
s_cselect_b32 s9, -1, 0
s_cmp_eq_u32 s8, 0
s_cselect_b32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
v_dual_mov_b32 v3, v7 :: v_dual_mov_b32 v4, v8
s_cselect_b32 s4, s4, s8
s_cselect_b32 s8, s10, s5
s_cmp_gt_u32 s11, 0x7ffffffe
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
s_cselect_b32 s5, s4, s2
s_cselect_b32 s4, s8, s11
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB1_18
.LBB1_16:
v_and_b32_e32 v0, 1, v3
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v0
s_cbranch_execz .LBB1_15
s_movk_i32 s2, 0x401
v_mul_lo_u32 v8, s5, v5
s_add_u32 s2, 0x402, s2
s_addc_u32 s9, 0, 0
v_add_co_u32 v0, s2, s2, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_mul_lo_u32 v9, s4, v6
s_addc_u32 s9, s9, 1
v_readfirstlane_b32 s2, v0
s_mul_i32 s10, s9, 0x80000001
v_mad_u64_u32 v[6:7], null, s4, v5, 0
s_delay_alu instid0(VALU_DEP_2)
s_mul_hi_u32 s11, s2, 0x80000001
s_mul_i32 s12, s2, 0x80000001
s_sub_i32 s11, s11, s2
s_mul_hi_u32 s13, s2, s12
s_add_i32 s11, s11, s10
s_mul_i32 s10, s9, s12
s_mul_hi_u32 s14, s2, s11
s_mul_i32 s2, s2, s11
s_mul_hi_u32 s12, s9, s12
s_add_u32 s2, s13, s2
s_addc_u32 s13, 0, s14
s_mul_hi_u32 s15, s9, s11
s_add_u32 s2, s2, s10
s_addc_u32 s2, s13, s12
s_mul_i32 s10, s9, s11
s_addc_u32 s11, s15, 0
s_add_u32 s2, s2, s10
s_addc_u32 s10, 0, s11
v_add_co_u32 v0, s2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_add3_u32 v5, v7, v9, v8
s_addc_u32 s2, s9, s10
v_mul_hi_u32 v13, v6, v0
v_mad_u64_u32 v[7:8], null, v6, s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[9:10], null, v5, v0, 0
v_mad_u64_u32 v[11:12], null, v5, s2, 0
v_add_co_u32 v0, vcc_lo, v13, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v0, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
v_mad_u64_u32 v[7:8], null, v0, 0x7fffffff, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v8
v_mad_u64_u32 v[8:9], null, v10, 0x7fffffff, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v6, v7
v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v6, vcc_lo, v0, 0x7fffffff
v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v6
v_cmp_eq_u32_e64 s2, 0, v5
v_cndmask_b32_e64 v8, 0, -1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v0
v_cndmask_b32_e64 v9, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, -1, v8, vcc_lo
v_sub_co_u32 v10, vcc_lo, v6, 0x7fffffff
v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v8
v_cndmask_b32_e64 v8, -1, v9, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v9, v6, v10, vcc_lo
v_cndmask_b32_e32 v7, v7, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
v_dual_cndmask_b32 v6, v5, v7 :: v_dual_cndmask_b32 v5, v0, v9
s_branch .LBB1_15
.LBB1_18:
s_or_b32 exec_lo, exec_lo, s7
.LBB1_19:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_movk_i32 s2, 0x401
v_mad_u64_u32 v[3:4], null, v5, s3, 0
s_add_u32 s2, 0x402, s2
s_addc_u32 s4, 0, 0
v_add_co_u32 v5, s2, s2, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
s_addc_u32 s4, s4, 1
v_readfirstlane_b32 s2, v5
s_mul_i32 s5, s4, 0x80000001
v_mov_b32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_2)
s_mul_hi_u32 s6, s2, 0x80000001
s_mul_i32 s7, s2, 0x80000001
s_sub_i32 s6, s6, s2
s_mul_hi_u32 s8, s2, s7
s_add_i32 s6, s6, s5
s_mul_hi_u32 s9, s4, s7
s_mul_i32 s5, s4, s7
s_mul_hi_u32 s7, s2, s6
s_mul_i32 s2, s2, s6
s_mul_hi_u32 s10, s4, s6
s_add_u32 s2, s8, s2
s_addc_u32 s7, 0, s7
s_add_u32 s2, s2, s5
s_addc_u32 s2, s7, s9
s_mul_i32 s5, s4, s6
s_addc_u32 s6, s10, 0
s_add_u32 s2, s2, s5
s_addc_u32 s5, 0, s6
v_add_co_u32 v9, s2, v5, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_mad_u64_u32 v[4:5], null, v6, s3, v[0:1]
s_addc_u32 s2, s4, s5
v_mul_hi_u32 v0, v3, v9
v_mad_u64_u32 v[5:6], null, v3, s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[7:8], null, v4, v9, 0
v_mad_u64_u32 v[9:10], null, v4, s2, 0
v_add_co_u32 v0, vcc_lo, v0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_mov_b32 s2, -1
v_add_co_u32 v0, vcc_lo, v0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v0, vcc_lo, v5, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo
v_mad_u64_u32 v[5:6], null, v0, 0x7fffffff, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v6
v_mad_u64_u32 v[6:7], null, v8, 0x7fffffff, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v3, v5
v_sub_co_ci_u32_e32 v3, vcc_lo, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v4, vcc_lo, v0, 0x7fffffff
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v4
v_cndmask_b32_e64 v6, 0, -1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v0
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_cndmask_b32_e32 v5, -1, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v3, -1, v7 :: v_dual_add_nc_u32 v6, 0x80000001, v4
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_hi_u32 v3, v0, 0xbc8f1391
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 15, v3
v_mul_u32_u24_e32 v3, 0xadc8, v4
v_mul_u32_u24_e32 v4, 0xd47, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v3, v0, 0xbc8f
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e64 s4, v3, v4
s_and_saveexec_b32 s3, s2
s_cbranch_execnz .LBB1_9
.LBB1_20:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 48
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE10raw_accessNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //****************************************************************************80
//
// file name:
//
// raise_to_power.cu
//
// licensing:
//
// this code is distributed under the mit license.
//
// author:
// bo pace
//
// reference:
// based on https://developer.nvidia.com/blog/even-easier-introduction-cuda/
// an article by mark harris of nvidia
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
//****************************************************************************80
//
// description:
//
// cuda kernal function. raises the elements of one array to the power of the
// elements of another array
//
// last modified:
//
// 17 april 2021
//
// input:
//
// int n - the length of the arrays
// float* arr1 - pointer to array of bases
// float* arr2 - pointer to array of exponents
//
__global__
void raise_to_power(int n, float* arr1, float* arr2)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
arr2[i] = pow(arr1[i], arr2[i]);
}
}
int main(void)
{
int arr_size = 1 << 20; // 1 million
// allocate unified memory -- accessible from cpu or gpu
float* arr1, * arr2;
cudaMallocManaged(&arr1, arr_size * sizeof(float));
cudaMallocManaged(&arr2, arr_size * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < arr_size; i++)
{
arr1[i] = 3.0f;
arr2[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (arr_size + blockSize - 1) / blockSize;
raise_to_power <<<numBlocks, blockSize>>> (arr_size, arr1, arr2);
// wait for gpu to finish before accessing on host
cudaDeviceSynchronize();
// check for errors (all values should be 9.0f)
float maxError = 0.0f;
for (int i = 0; i < arr_size; i++)
{
maxError = fmax(maxError, fabs(arr2[i] - 9.0f));
}
std::cout << "Max error: " << maxError << '\n';
// free memory
cudaFree(arr1);
cudaFree(arr2);
return 0;
} | code for sm_80
Function : _Z14raise_to_poweriPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ MOV R17, 0x3a2c32e4 ; /* 0x3a2c32e400117802 */
/* 0x000fe20000000f00 */
/*00f0*/ BSSY B0, 0x6e0 ; /* 0x000005e000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R0, R7, R0, RZ ; /* 0x0000000007007210 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f26270 */
/*0120*/ FMUL R8, |R9|.reuse, 16777216 ; /* 0x4b80000009087820 */
/* 0x044fe20000400200 */
/*0130*/ FSETP.GEU.AND P0, PT, |R9|, 1.175494350822287508e-38, PT ; /* 0x008000000900780b */
/* 0x000fc80003f0e200 */
/*0140*/ FSEL R8, R8, |R9|, !P0 ; /* 0x4000000908087208 */
/* 0x000fc80004000000 */
/*0150*/ IADD3 R10, R8, -0x3f3504f3, RZ ; /* 0xc0cafb0d080a7810 */
/* 0x000fc80007ffe0ff */
/*0160*/ LOP3.LUT R11, R10, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000a0b7812 */
/* 0x000fe400078ec0ff */
/*0170*/ FSEL R10, RZ, -24, P0 ; /* 0xc1c00000ff0a7808 */
/* 0x000fe40000000000 */
/*0180*/ IADD3 R8, R8, -R11, RZ ; /* 0x8000000b08087210 */
/* 0x000fe40007ffe0ff */
/*0190*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000fe60000201400 */
/*01a0*/ FADD R12, R8.reuse, 1 ; /* 0x3f800000080c7421 */
/* 0x040fe40000000000 */
/*01b0*/ FADD R15, R8, -1 ; /* 0xbf800000080f7421 */
/* 0x000fc80000000000 */
/*01c0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x000e220000001000 */
/*01d0*/ FADD R13, R15, R15 ; /* 0x0000000f0f0d7221 */
/* 0x000fc80000000000 */
/*01e0*/ FMUL R8, R12, R13 ; /* 0x0000000d0c087220 */
/* 0x001fe40000400000 */
/*01f0*/ FFMA R13, R11, 1.1920928955078125e-07, R10 ; /* 0x340000000b0d7823 */
/* 0x000fe4000000000a */
/*0200*/ FADD R10, R15, -R8 ; /* 0x800000080f0a7221 */
/* 0x000fe40000000000 */
/*0210*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x000fe40000400000 */
/*0220*/ FADD R16, R10, R10 ; /* 0x0000000a0a107221 */
/* 0x000fe40000000000 */
/*0230*/ FFMA R10, R8, 1.4426950216293334961, R13 ; /* 0x3fb8aa3b080a7823 */
/* 0x000fc4000000000d */
/*0240*/ FFMA R11, R14.reuse, R17, 0.0032181653659790754318 ; /* 0x3b52e7db0e0b7423 */
/* 0x040fe40000000011 */
/*0250*/ FFMA R15, R15, -R8, R16 ; /* 0x800000080f0f7223 */
/* 0x000fe40000000010 */
/*0260*/ FADD R13, R13, -R10 ; /* 0x8000000a0d0d7221 */
/* 0x000fe40000000000 */
/*0270*/ FFMA R11, R14, R11, 0.018033718690276145935 ; /* 0x3c93bb730e0b7423 */
/* 0x000fe4000000000b */
/*0280*/ FMUL R15, R12, R15 ; /* 0x0000000f0c0f7220 */
/* 0x000fe40000400000 */
/*0290*/ FFMA R12, R8, 1.4426950216293334961, R13 ; /* 0x3fb8aa3b080c7823 */
/* 0x000fc4000000000d */
/*02a0*/ FFMA R11, R14.reuse, R11, 0.12022458761930465698 ; /* 0x3df6384f0e0b7423 */
/* 0x040fe4000000000b */
/*02b0*/ FFMA R13, R15, 1.4426950216293334961, R12 ; /* 0x3fb8aa3b0f0d7823 */
/* 0x000fe4000000000c */
/*02c0*/ FMUL R11, R14, R11 ; /* 0x0000000b0e0b7220 */
/* 0x000fe40000400000 */
/*02d0*/ FFMA R12, R8, 1.9251366722983220825e-08, R13 ; /* 0x32a55e34080c7823 */
/* 0x000fe4000000000d */
/*02e0*/ FMUL R13, R11, 3 ; /* 0x404000000b0d7820 */
/* 0x000fc80000400000 */
/*02f0*/ FFMA R12, R15, R13, R12 ; /* 0x0000000d0f0c7223 */
/* 0x000fc8000000000c */
/*0300*/ FFMA R13, R8, R11, R12 ; /* 0x0000000b080d7223 */
/* 0x000fc8000000000c */
/*0310*/ FADD R15, R10, R13 ; /* 0x0000000d0a0f7221 */
/* 0x000fc80000000000 */
/*0320*/ FMUL R11, R6, R15.reuse ; /* 0x0000000f060b7220 */
/* 0x088fe40000400000 */
/*0330*/ FADD R10, -R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x000fe40000000100 */
/*0340*/ FRND R8, R11 ; /* 0x0000000b00087307 */
/* 0x000e220000201000 */
/*0350*/ FFMA R15, R6, R15, -R11 ; /* 0x0000000f060f7223 */
/* 0x000fe2000000080b */
/*0360*/ FSETP.GT.AND P2, PT, |R11|, 152, PT ; /* 0x431800000b00780b */
/* 0x000fe20003f44200 */
/*0370*/ FADD R13, R13, -R10 ; /* 0x8000000a0d0d7221 */
/* 0x000fe20000000000 */
/*0380*/ FSETP.GEU.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x000fc60003f6e000 */
/*0390*/ FFMA R13, R6, R13, R15 ; /* 0x0000000d060d7223 */
/* 0x000fe2000000000f */
/*03a0*/ MOV R15, 0x391fcb8e ; /* 0x391fcb8e000f7802 */
/* 0x000fe20000000f00 */
/*03b0*/ F2I.NTZ R12, R11 ; /* 0x0000000b000c7305 */
/* 0x0002a20000203100 */
/*03c0*/ FADD R10, R11, -R8 ; /* 0x800000080b0a7221 */
/* 0x001fe20000000000 */
/*03d0*/ FSETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe20003f04000 */
/*03e0*/ FMUL R8, R6, 0.5 ; /* 0x3f00000006087820 */
/* 0x000fe20000400000 */
/*03f0*/ MOV R11, 0x3f800000 ; /* 0x3f800000000b7802 */
/* 0x002fe20000000f00 */
/*0400*/ FADD R10, R13, R10 ; /* 0x0000000a0d0a7221 */
/* 0x000fc80000000000 */
/*0410*/ FFMA R13, R10, R15, 0.0013391353422775864601 ; /* 0x3aaf85ed0a0d7423 */
/* 0x000fe2000000000f */
/*0420*/ SEL R15, RZ, 0x83000000, P0 ; /* 0x83000000ff0f7807 */
/* 0x000fe20000000000 */
/*0430*/ FRND.TRUNC R8, R8 ; /* 0x0000000800087307 */
/* 0x000e22000020d000 */
/*0440*/ FSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fe20003f0d000 */
/*0450*/ FFMA R13, R10, R13, 0.0096188392490148544312 ; /* 0x3c1d98560a0d7423 */
/* 0x000fc6000000000d */
/*0460*/ FSETP.EQ.OR P0, PT, R9, 1, !P0 ; /* 0x3f8000000900780b */
/* 0x000fe20004702400 */
/*0470*/ FFMA R13, R10, R13, 0.055503588169813156128 ; /* 0x3d6357bb0a0d7423 */
/* 0x000fc8000000000d */
/*0480*/ FFMA R13, R10, R13, 0.24022644758224487305 ; /* 0x3e75fdec0a0d7423 */
/* 0x000fc8000000000d */
/*0490*/ FFMA R13, R10, R13, 0.69314718246459960938 ; /* 0x3f3172180a0d7423 */
/* 0x000fc8000000000d */
/*04a0*/ FFMA R13, R10, R13, 1 ; /* 0x3f8000000a0d7423 */
/* 0x000fe2000000000d */
/*04b0*/ IADD3 R10, R15, 0x7f000000, RZ ; /* 0x7f0000000f0a7810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ LEA R15, R12, -R15, 0x17 ; /* 0x8000000f0c0f7211 */
/* 0x004fc600078eb8ff */
/*04d0*/ FMUL R10, R13, R10 ; /* 0x0000000a0d0a7220 */
/* 0x000fe40000400000 */
/*04e0*/ FADD R13, R8, R8 ; /* 0x00000008080d7221 */
/* 0x001fe40000000000 */
/*04f0*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fe20000400000 */
/*0500*/ @P2 FSEL R10, RZ, +INF , !P3 ; /* 0x7f800000ff0a2808 */
/* 0x000fe20005800000 */
/*0510*/ @P0 BRA 0x6d0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0520*/ FSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f0c200 */
/*0530*/ FSETP.GTU.OR P0, PT, |R9|, +INF , P0 ; /* 0x7f8000000900780b */
/* 0x000fda000070c600 */
/*0540*/ @P0 BRA 0x6c0 ; /* 0x0000017000000947 */
/* 0x000fea0003800000 */
/*0550*/ FSETP.NEU.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f0d200 */
/*0560*/ FADD R13, R6, -R13 ; /* 0x8000000d060d7221 */
/* 0x000fc60000000000 */
/*0570*/ FSETP.EQ.OR P0, PT, R9, RZ, !P0 ; /* 0x000000ff0900720b */
/* 0x000fda0004702400 */
/*0580*/ @P0 BRA 0x650 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0590*/ FSETP.NEU.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f0d200 */
/*05a0*/ FSETP.EQ.AND P2, PT, R9, -1, PT ; /* 0xbf8000000900780b */
/* 0x000fda0003f42000 */
/*05b0*/ @!P0 BRA P2, 0x6d0 ; /* 0x0000011000008947 */
/* 0x000fea0001000000 */
/*05c0*/ FSETP.GEU.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe40003f0e000 */
/*05d0*/ MOV R11, R10 ; /* 0x0000000a000b7202 */
/* 0x000fd60000000f00 */
/*05e0*/ @P0 BRA 0x6d0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*05f0*/ FRND.FLOOR R9, R6 ; /* 0x0000000600097307 */
/* 0x000e220000205000 */
/*0600*/ FSETP.NEU.AND P2, PT, |R13|, 1, PT ; /* 0x3f8000000d00780b */
/* 0x000fc80003f4d200 */
/*0610*/ FSEL R11, -R10, R10, !P2 ; /* 0x0000000a0a0b7208 */
/* 0x000fe40005000100 */
/*0620*/ FSETP.NEU.AND P0, PT, R9, R6, PT ; /* 0x000000060900720b */
/* 0x001fc80003f0d000 */
/*0630*/ FSEL R11, R11, +QNAN , !P0 ; /* 0x7fffffff0b0b7808 */
/* 0x000fe20004000000 */
/*0640*/ BRA 0x6d0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0650*/ FSETP.GEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fe20003f0e000 */
/*0660*/ FADD R9, R9, R9 ; /* 0x0000000909097221 */
/* 0x000fe20000000000 */
/*0670*/ FSETP.NEU.AND P2, PT, |R13|, 1, PT ; /* 0x3f8000000d00780b */
/* 0x000fd60003f4d200 */
/*0680*/ @!P0 LOP3.LUT R9, R9, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000009098812 */
/* 0x000fc800078e3cff */
/*0690*/ @P2 LOP3.LUT R9, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09092812 */
/* 0x000fc800078ec0ff */
/*06a0*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*06b0*/ BRA 0x6d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06c0*/ FADD R11, R6, R9 ; /* 0x00000009060b7221 */
/* 0x000fe40000000000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*06f0*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x000fc800078e0204 */
/*0700*/ IMAD.WIDE R2, R7, 0x4, R2 ; /* 0x0000000407027825 */
/* 0x001fe200078e0202 */
/*0710*/ @!P1 BRA 0xc0 ; /* 0xfffff9a000009947 */
/* 0x000fea000383ffff */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //****************************************************************************80
//
// file name:
//
// raise_to_power.cu
//
// licensing:
//
// this code is distributed under the mit license.
//
// author:
// bo pace
//
// reference:
// based on https://developer.nvidia.com/blog/even-easier-introduction-cuda/
// an article by mark harris of nvidia
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
//****************************************************************************80
//
// description:
//
// cuda kernal function. raises the elements of one array to the power of the
// elements of another array
//
// last modified:
//
// 17 april 2021
//
// input:
//
// int n - the length of the arrays
// float* arr1 - pointer to array of bases
// float* arr2 - pointer to array of exponents
//
__global__
void raise_to_power(int n, float* arr1, float* arr2)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
arr2[i] = pow(arr1[i], arr2[i]);
}
}
int main(void)
{
int arr_size = 1 << 20; // 1 million
// allocate unified memory -- accessible from cpu or gpu
float* arr1, * arr2;
cudaMallocManaged(&arr1, arr_size * sizeof(float));
cudaMallocManaged(&arr2, arr_size * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < arr_size; i++)
{
arr1[i] = 3.0f;
arr2[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (arr_size + blockSize - 1) / blockSize;
raise_to_power <<<numBlocks, blockSize>>> (arr_size, arr1, arr2);
// wait for gpu to finish before accessing on host
cudaDeviceSynchronize();
// check for errors (all values should be 9.0f)
float maxError = 0.0f;
for (int i = 0; i < arr_size; i++)
{
maxError = fmax(maxError, fabs(arr2[i] - 9.0f));
}
std::cout << "Max error: " << maxError << '\n';
// free memory
cudaFree(arr1);
cudaFree(arr2);
return 0;
} | .file "tmpxft_000ed4a5_00000000-6_raise_to_power.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
.type _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_, @function
_Z37__device_stub__Z14raise_to_poweriPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14raise_to_poweriPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_, .-_Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
.globl _Z14raise_to_poweriPfS_
.type _Z14raise_to_poweriPfS_, @function
_Z14raise_to_poweriPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14raise_to_poweriPfS_, .-_Z14raise_to_poweriPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z14raise_to_poweriPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14raise_to_poweriPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1077936128
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1091567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //****************************************************************************80
//
// file name:
//
// raise_to_power.cu
//
// licensing:
//
// this code is distributed under the mit license.
//
// author:
// bo pace
//
// reference:
// based on https://developer.nvidia.com/blog/even-easier-introduction-cuda/
// an article by mark harris of nvidia
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
//****************************************************************************80
//
// description:
//
// cuda kernal function. raises the elements of one array to the power of the
// elements of another array
//
// last modified:
//
// 17 april 2021
//
// input:
//
// int n - the length of the arrays
// float* arr1 - pointer to array of bases
// float* arr2 - pointer to array of exponents
//
__global__
void raise_to_power(int n, float* arr1, float* arr2)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
arr2[i] = pow(arr1[i], arr2[i]);
}
}
int main(void)
{
int arr_size = 1 << 20; // 1 million
// allocate unified memory -- accessible from cpu or gpu
float* arr1, * arr2;
cudaMallocManaged(&arr1, arr_size * sizeof(float));
cudaMallocManaged(&arr2, arr_size * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < arr_size; i++)
{
arr1[i] = 3.0f;
arr2[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (arr_size + blockSize - 1) / blockSize;
raise_to_power <<<numBlocks, blockSize>>> (arr_size, arr1, arr2);
// wait for gpu to finish before accessing on host
cudaDeviceSynchronize();
// check for errors (all values should be 9.0f)
float maxError = 0.0f;
for (int i = 0; i < arr_size; i++)
{
maxError = fmax(maxError, fabs(arr2[i] - 9.0f));
}
std::cout << "Max error: " << maxError << '\n';
// free memory
cudaFree(arr1);
cudaFree(arr2);
return 0;
} | //****************************************************************************80
//
// file name:
//
// raise_to_power.cu
//
// licensing:
//
// this code is distributed under the mit license.
//
// author:
// bo pace
//
// reference:
// based on https://developer.nvidia.com/blog/even-easier-introduction-cuda/
// an article by mark harris of nvidia
#include "hip/hip_runtime.h"
#include <iostream>
#include <math.h>
//****************************************************************************80
//
// description:
//
// cuda kernal function. raises the elements of one array to the power of the
// elements of another array
//
// last modified:
//
// 17 april 2021
//
// input:
//
// int n - the length of the arrays
// float* arr1 - pointer to array of bases
// float* arr2 - pointer to array of exponents
//
__global__
void raise_to_power(int n, float* arr1, float* arr2)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
arr2[i] = pow(arr1[i], arr2[i]);
}
}
int main(void)
{
int arr_size = 1 << 20; // 1 million
// allocate unified memory -- accessible from cpu or gpu
float* arr1, * arr2;
hipMallocManaged(&arr1, arr_size * sizeof(float));
hipMallocManaged(&arr2, arr_size * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < arr_size; i++)
{
arr1[i] = 3.0f;
arr2[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (arr_size + blockSize - 1) / blockSize;
raise_to_power <<<numBlocks, blockSize>>> (arr_size, arr1, arr2);
// wait for gpu to finish before accessing on host
hipDeviceSynchronize();
// check for errors (all values should be 9.0f)
float maxError = 0.0f;
for (int i = 0; i < arr_size; i++)
{
maxError = fmax(maxError, fabs(arr2[i] - 9.0f));
}
std::cout << "Max error: " << maxError << '\n';
// free memory
hipFree(arr1);
hipFree(arr2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //****************************************************************************80
//
// file name:
//
// raise_to_power.cu
//
// licensing:
//
// this code is distributed under the mit license.
//
// author:
// bo pace
//
// reference:
// based on https://developer.nvidia.com/blog/even-easier-introduction-cuda/
// an article by mark harris of nvidia
#include "hip/hip_runtime.h"
#include <iostream>
#include <math.h>
//****************************************************************************80
//
// description:
//
// cuda kernal function. raises the elements of one array to the power of the
// elements of another array
//
// last modified:
//
// 17 april 2021
//
// input:
//
// int n - the length of the arrays
// float* arr1 - pointer to array of bases
// float* arr2 - pointer to array of exponents
//
__global__
void raise_to_power(int n, float* arr1, float* arr2)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
arr2[i] = pow(arr1[i], arr2[i]);
}
}
int main(void)
{
int arr_size = 1 << 20; // 1 million
// allocate unified memory -- accessible from cpu or gpu
float* arr1, * arr2;
hipMallocManaged(&arr1, arr_size * sizeof(float));
hipMallocManaged(&arr2, arr_size * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < arr_size; i++)
{
arr1[i] = 3.0f;
arr2[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (arr_size + blockSize - 1) / blockSize;
raise_to_power <<<numBlocks, blockSize>>> (arr_size, arr1, arr2);
// wait for gpu to finish before accessing on host
hipDeviceSynchronize();
// check for errors (all values should be 9.0f)
float maxError = 0.0f;
for (int i = 0; i < arr_size; i++)
{
maxError = fmax(maxError, fabs(arr2[i] - 9.0f));
}
std::cout << "Max error: " << maxError << '\n';
// free memory
hipFree(arr1);
hipFree(arr2);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14raise_to_poweriPfS_
.globl _Z14raise_to_poweriPfS_
.p2align 8
.type _Z14raise_to_poweriPfS_,@function
_Z14raise_to_poweriPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s9, 0x3e76c4e1
.LBB0_2:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
s_waitcnt vmcnt(1)
v_cmp_neq_f32_e32 vcc_lo, 1.0, v0
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v4, 1.0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_neq_f32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
v_frexp_mant_f32_e64 v5, |v0|
v_frexp_exp_i32_f32_e32 v8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v9, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v5, v5, v9
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 1.0, v5
v_dual_add_f32 v10, -1.0, v5 :: v_dual_mul_f32 v13, 0x3f317218, v8
v_cmp_neq_f32_e64 s13, v4, |v4|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v14, v10, v11
v_add_f32_e32 v12, -1.0, v9
v_sub_f32_e32 v5, v5, v12
v_fma_f32 v12, v8, 0x3f317218, -v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, 0xb102e308, v8
v_add_f32_e32 v15, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v13, v15, v13 :: v_dual_mul_f32 v8, v9, v14
v_cmp_lt_f32_e64 s14, |v0|, 1.0
v_fma_f32 v9, v14, v9, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s13, s13, s14
v_fmac_f32_e32 v9, v14, v5
v_sub_f32_e32 v5, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v8, v9
v_sub_f32_e32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v13, v10, v12 :: v_dual_sub_f32 v8, v8, v9
v_sub_f32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v10, v12
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v13, v8
v_mul_f32_e32 v8, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v14, v8
v_sub_f32_e32 v10, v9, v14
v_mul_f32_e32 v11, v9, v9
v_ldexp_f32 v12, v9, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v10, v9, v9, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v13, v8, v8
v_ldexp_f32 v14, v8, 1
v_fmac_f32_e32 v10, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v11, v10
v_sub_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v17, v9, v13 :: v_dual_sub_f32 v10, v10, v11
v_fma_f32 v11, v13, v9, -v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v16, s9, v13, 0x3e91f4c4 :: v_dual_fmac_f32 v11, v13, v8
v_dual_fmaak_f32 v16, v13, v16, 0x3ecccdef :: v_dual_fmac_f32 v11, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v18, v13, v16
v_add_f32_e32 v9, v17, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v13, v16, -v18
v_dual_sub_f32 v13, v9, v17 :: v_dual_fmac_f32 v8, v10, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v11, v11, v13 :: v_dual_add_f32 v10, v18, v8
v_add_f32_e32 v17, 0x3f2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v10, v18 :: v_dual_add_f32 v13, 0xbf2aaaaa, v17
v_sub_f32_e32 v8, v8, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v10, v13
v_add_f32_e32 v8, 0x31739010, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v8, v10
v_add_f32_e32 v10, v17, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v13, v17, v10
v_mul_f32_e32 v16, v9, v10
v_add_f32_e32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v9, v10, -v16
v_fmac_f32_e32 v13, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v11, v10
v_add_f32_e32 v8, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v12, v8
v_sub_f32_e32 v10, v8, v16
v_trunc_f32_e32 v16, v4
v_sub_f32_e32 v11, v9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v13, v10
v_cmp_eq_f32_e64 s0, v16, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v8, v8, v11
v_add_f32_e32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v10, v8
v_add_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v15, v10
v_dual_sub_f32 v9, v10, v9 :: v_dual_sub_f32 v12, v11, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v9, v11, v12
v_add_f32_e32 v13, v5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v10, v10, v12 :: v_dual_sub_f32 v9, v15, v9
v_sub_f32_e32 v12, v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v9, v10, v9 :: v_dual_sub_f32 v10, v13, v12
v_dual_sub_f32 v8, v8, v12 :: v_dual_add_f32 v9, v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v5, v10 :: v_dual_add_f32 v10, v11, v9
v_dual_add_f32 v5, v8, v5 :: v_dual_sub_f32 v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v9, v8
v_add_f32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v10, v5
v_sub_f32_e32 v9, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, v4, v8 :: v_dual_sub_f32 v5, v5, v9
v_fma_f32 v8, v4, v8, -v10
v_cmp_class_f32_e64 vcc_lo, v10, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v4, v5
v_add_f32_e32 v5, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v5, v10, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
v_cmp_neq_f32_e64 s1, 0x7f800000, |v9|
v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v9, v11
v_sub_f32_e32 v5, v5, v10
v_mul_f32_e32 v13, 0x3fb8aa3b, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v8, v5
v_fma_f32 v14, v12, 0x3fb8aa3b, -v13
v_rndne_f32_e32 v15, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, v5, s1
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v12
v_dual_fmac_f32 v14, 0x32a5705f, v12 :: v_dual_sub_f32 v13, v13, v15
v_cvt_i32_f32_e32 v10, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v11, v5
v_dual_add_f32 v13, v13, v14 :: v_dual_mul_f32 v14, 0.5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_exp_f32_e32 v13, v13
v_trunc_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_ldexp_f32 v8, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, v8, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v12
v_cndmask_b32_e64 v8, 0x7f800000, v8, s1
v_cmp_neq_f32_e64 s1, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v5, v8, v5, v8
v_cmp_eq_f32_e64 s2, 0x7f800000, v8
s_and_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, 1.0, v0, s1
v_cndmask_b32_e64 v11, 0, v0, s1
v_cndmask_b32_e64 v5, v5, v8, s2
v_cmp_eq_f32_e64 s2, 0, v0
v_cndmask_b32_e64 v8, |v4|, 0, s13
v_cmp_eq_f32_e64 s13, |v0|, 1.0
v_cmp_o_f32_e64 s1, v0, v4
v_bfi_b32 v5, 0x7fffffff, v5, v9
s_xor_b32 s14, vcc_lo, s2
v_cmp_gt_f32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v9, 0x7f800000, 0, s14
v_cndmask_b32_e64 v8, v8, |v0|, s13
v_cndmask_b32_e64 v10, 0x7fc00000, v5, s0
v_cmp_class_f32_e64 s0, v0, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v9, 0x7fffffff, v9, v11
v_cndmask_b32_e32 v5, v5, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_or_b32 vcc_lo, s2, s0
v_cmp_le_i32_e64 s0, s12, v1
v_cndmask_b32_e32 v5, v5, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v0, 0x7fc00000, v5, s1
s_or_b32 s3, s0, s3
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14raise_to_poweriPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14raise_to_poweriPfS_, .Lfunc_end0-_Z14raise_to_poweriPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14raise_to_poweriPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14raise_to_poweriPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //****************************************************************************80
//
// file name:
//
// raise_to_power.cu
//
// licensing:
//
// this code is distributed under the mit license.
//
// author:
// bo pace
//
// reference:
// based on https://developer.nvidia.com/blog/even-easier-introduction-cuda/
// an article by mark harris of nvidia
#include "hip/hip_runtime.h"
#include <iostream>
#include <math.h>
//****************************************************************************80
//
// description:
//
// cuda kernal function. raises the elements of one array to the power of the
// elements of another array
//
// last modified:
//
// 17 april 2021
//
// input:
//
// int n - the length of the arrays
// float* arr1 - pointer to array of bases
// float* arr2 - pointer to array of exponents
//
__global__
void raise_to_power(int n, float* arr1, float* arr2)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
{
arr2[i] = pow(arr1[i], arr2[i]);
}
}
int main(void)
{
int arr_size = 1 << 20; // 1 million
// allocate unified memory -- accessible from cpu or gpu
float* arr1, * arr2;
hipMallocManaged(&arr1, arr_size * sizeof(float));
hipMallocManaged(&arr2, arr_size * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < arr_size; i++)
{
arr1[i] = 3.0f;
arr2[i] = 2.0f;
}
int blockSize = 256;
int numBlocks = (arr_size + blockSize - 1) / blockSize;
raise_to_power <<<numBlocks, blockSize>>> (arr_size, arr1, arr2);
// wait for gpu to finish before accessing on host
hipDeviceSynchronize();
// check for errors (all values should be 9.0f)
float maxError = 0.0f;
for (int i = 0; i < arr_size; i++)
{
maxError = fmax(maxError, fabs(arr2[i] - 9.0f));
}
std::cout << "Max error: " << maxError << '\n';
// free memory
hipFree(arr1);
hipFree(arr2);
return 0;
} | .text
.file "raise_to_power.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__raise_to_poweriPfS_ # -- Begin function _Z29__device_stub__raise_to_poweriPfS_
.p2align 4, 0x90
.type _Z29__device_stub__raise_to_poweriPfS_,@function
_Z29__device_stub__raise_to_poweriPfS_: # @_Z29__device_stub__raise_to_poweriPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14raise_to_poweriPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__raise_to_poweriPfS_, .Lfunc_end0-_Z29__device_stub__raise_to_poweriPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc1100000 # float -9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1077936128, (%rax,%rcx,4) # imm = 0x40400000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z14raise_to_poweriPfS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_8
# %bb.7:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_9
.LBB1_8:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14raise_to_poweriPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14raise_to_poweriPfS_,@object # @_Z14raise_to_poweriPfS_
.section .rodata,"a",@progbits
.globl _Z14raise_to_poweriPfS_
.p2align 3, 0x0
_Z14raise_to_poweriPfS_:
.quad _Z29__device_stub__raise_to_poweriPfS_
.size _Z14raise_to_poweriPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14raise_to_poweriPfS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__raise_to_poweriPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14raise_to_poweriPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14raise_to_poweriPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ MOV R17, 0x3a2c32e4 ; /* 0x3a2c32e400117802 */
/* 0x000fe20000000f00 */
/*00f0*/ BSSY B0, 0x6e0 ; /* 0x000005e000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R0, R7, R0, RZ ; /* 0x0000000007007210 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f26270 */
/*0120*/ FMUL R8, |R9|.reuse, 16777216 ; /* 0x4b80000009087820 */
/* 0x044fe20000400200 */
/*0130*/ FSETP.GEU.AND P0, PT, |R9|, 1.175494350822287508e-38, PT ; /* 0x008000000900780b */
/* 0x000fc80003f0e200 */
/*0140*/ FSEL R8, R8, |R9|, !P0 ; /* 0x4000000908087208 */
/* 0x000fc80004000000 */
/*0150*/ IADD3 R10, R8, -0x3f3504f3, RZ ; /* 0xc0cafb0d080a7810 */
/* 0x000fc80007ffe0ff */
/*0160*/ LOP3.LUT R11, R10, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000a0b7812 */
/* 0x000fe400078ec0ff */
/*0170*/ FSEL R10, RZ, -24, P0 ; /* 0xc1c00000ff0a7808 */
/* 0x000fe40000000000 */
/*0180*/ IADD3 R8, R8, -R11, RZ ; /* 0x8000000b08087210 */
/* 0x000fe40007ffe0ff */
/*0190*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000fe60000201400 */
/*01a0*/ FADD R12, R8.reuse, 1 ; /* 0x3f800000080c7421 */
/* 0x040fe40000000000 */
/*01b0*/ FADD R15, R8, -1 ; /* 0xbf800000080f7421 */
/* 0x000fc80000000000 */
/*01c0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x000e220000001000 */
/*01d0*/ FADD R13, R15, R15 ; /* 0x0000000f0f0d7221 */
/* 0x000fc80000000000 */
/*01e0*/ FMUL R8, R12, R13 ; /* 0x0000000d0c087220 */
/* 0x001fe40000400000 */
/*01f0*/ FFMA R13, R11, 1.1920928955078125e-07, R10 ; /* 0x340000000b0d7823 */
/* 0x000fe4000000000a */
/*0200*/ FADD R10, R15, -R8 ; /* 0x800000080f0a7221 */
/* 0x000fe40000000000 */
/*0210*/ FMUL R14, R8, R8 ; /* 0x00000008080e7220 */
/* 0x000fe40000400000 */
/*0220*/ FADD R16, R10, R10 ; /* 0x0000000a0a107221 */
/* 0x000fe40000000000 */
/*0230*/ FFMA R10, R8, 1.4426950216293334961, R13 ; /* 0x3fb8aa3b080a7823 */
/* 0x000fc4000000000d */
/*0240*/ FFMA R11, R14.reuse, R17, 0.0032181653659790754318 ; /* 0x3b52e7db0e0b7423 */
/* 0x040fe40000000011 */
/*0250*/ FFMA R15, R15, -R8, R16 ; /* 0x800000080f0f7223 */
/* 0x000fe40000000010 */
/*0260*/ FADD R13, R13, -R10 ; /* 0x8000000a0d0d7221 */
/* 0x000fe40000000000 */
/*0270*/ FFMA R11, R14, R11, 0.018033718690276145935 ; /* 0x3c93bb730e0b7423 */
/* 0x000fe4000000000b */
/*0280*/ FMUL R15, R12, R15 ; /* 0x0000000f0c0f7220 */
/* 0x000fe40000400000 */
/*0290*/ FFMA R12, R8, 1.4426950216293334961, R13 ; /* 0x3fb8aa3b080c7823 */
/* 0x000fc4000000000d */
/*02a0*/ FFMA R11, R14.reuse, R11, 0.12022458761930465698 ; /* 0x3df6384f0e0b7423 */
/* 0x040fe4000000000b */
/*02b0*/ FFMA R13, R15, 1.4426950216293334961, R12 ; /* 0x3fb8aa3b0f0d7823 */
/* 0x000fe4000000000c */
/*02c0*/ FMUL R11, R14, R11 ; /* 0x0000000b0e0b7220 */
/* 0x000fe40000400000 */
/*02d0*/ FFMA R12, R8, 1.9251366722983220825e-08, R13 ; /* 0x32a55e34080c7823 */
/* 0x000fe4000000000d */
/*02e0*/ FMUL R13, R11, 3 ; /* 0x404000000b0d7820 */
/* 0x000fc80000400000 */
/*02f0*/ FFMA R12, R15, R13, R12 ; /* 0x0000000d0f0c7223 */
/* 0x000fc8000000000c */
/*0300*/ FFMA R13, R8, R11, R12 ; /* 0x0000000b080d7223 */
/* 0x000fc8000000000c */
/*0310*/ FADD R15, R10, R13 ; /* 0x0000000d0a0f7221 */
/* 0x000fc80000000000 */
/*0320*/ FMUL R11, R6, R15.reuse ; /* 0x0000000f060b7220 */
/* 0x088fe40000400000 */
/*0330*/ FADD R10, -R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x000fe40000000100 */
/*0340*/ FRND R8, R11 ; /* 0x0000000b00087307 */
/* 0x000e220000201000 */
/*0350*/ FFMA R15, R6, R15, -R11 ; /* 0x0000000f060f7223 */
/* 0x000fe2000000080b */
/*0360*/ FSETP.GT.AND P2, PT, |R11|, 152, PT ; /* 0x431800000b00780b */
/* 0x000fe20003f44200 */
/*0370*/ FADD R13, R13, -R10 ; /* 0x8000000a0d0d7221 */
/* 0x000fe20000000000 */
/*0380*/ FSETP.GEU.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x000fc60003f6e000 */
/*0390*/ FFMA R13, R6, R13, R15 ; /* 0x0000000d060d7223 */
/* 0x000fe2000000000f */
/*03a0*/ MOV R15, 0x391fcb8e ; /* 0x391fcb8e000f7802 */
/* 0x000fe20000000f00 */
/*03b0*/ F2I.NTZ R12, R11 ; /* 0x0000000b000c7305 */
/* 0x0002a20000203100 */
/*03c0*/ FADD R10, R11, -R8 ; /* 0x800000080b0a7221 */
/* 0x001fe20000000000 */
/*03d0*/ FSETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe20003f04000 */
/*03e0*/ FMUL R8, R6, 0.5 ; /* 0x3f00000006087820 */
/* 0x000fe20000400000 */
/*03f0*/ MOV R11, 0x3f800000 ; /* 0x3f800000000b7802 */
/* 0x002fe20000000f00 */
/*0400*/ FADD R10, R13, R10 ; /* 0x0000000a0d0a7221 */
/* 0x000fc80000000000 */
/*0410*/ FFMA R13, R10, R15, 0.0013391353422775864601 ; /* 0x3aaf85ed0a0d7423 */
/* 0x000fe2000000000f */
/*0420*/ SEL R15, RZ, 0x83000000, P0 ; /* 0x83000000ff0f7807 */
/* 0x000fe20000000000 */
/*0430*/ FRND.TRUNC R8, R8 ; /* 0x0000000800087307 */
/* 0x000e22000020d000 */
/*0440*/ FSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fe20003f0d000 */
/*0450*/ FFMA R13, R10, R13, 0.0096188392490148544312 ; /* 0x3c1d98560a0d7423 */
/* 0x000fc6000000000d */
/*0460*/ FSETP.EQ.OR P0, PT, R9, 1, !P0 ; /* 0x3f8000000900780b */
/* 0x000fe20004702400 */
/*0470*/ FFMA R13, R10, R13, 0.055503588169813156128 ; /* 0x3d6357bb0a0d7423 */
/* 0x000fc8000000000d */
/*0480*/ FFMA R13, R10, R13, 0.24022644758224487305 ; /* 0x3e75fdec0a0d7423 */
/* 0x000fc8000000000d */
/*0490*/ FFMA R13, R10, R13, 0.69314718246459960938 ; /* 0x3f3172180a0d7423 */
/* 0x000fc8000000000d */
/*04a0*/ FFMA R13, R10, R13, 1 ; /* 0x3f8000000a0d7423 */
/* 0x000fe2000000000d */
/*04b0*/ IADD3 R10, R15, 0x7f000000, RZ ; /* 0x7f0000000f0a7810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ LEA R15, R12, -R15, 0x17 ; /* 0x8000000f0c0f7211 */
/* 0x004fc600078eb8ff */
/*04d0*/ FMUL R10, R13, R10 ; /* 0x0000000a0d0a7220 */
/* 0x000fe40000400000 */
/*04e0*/ FADD R13, R8, R8 ; /* 0x00000008080d7221 */
/* 0x001fe40000000000 */
/*04f0*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fe20000400000 */
/*0500*/ @P2 FSEL R10, RZ, +INF , !P3 ; /* 0x7f800000ff0a2808 */
/* 0x000fe20005800000 */
/*0510*/ @P0 BRA 0x6d0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0520*/ FSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f0c200 */
/*0530*/ FSETP.GTU.OR P0, PT, |R9|, +INF , P0 ; /* 0x7f8000000900780b */
/* 0x000fda000070c600 */
/*0540*/ @P0 BRA 0x6c0 ; /* 0x0000017000000947 */
/* 0x000fea0003800000 */
/*0550*/ FSETP.NEU.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f0d200 */
/*0560*/ FADD R13, R6, -R13 ; /* 0x8000000d060d7221 */
/* 0x000fc60000000000 */
/*0570*/ FSETP.EQ.OR P0, PT, R9, RZ, !P0 ; /* 0x000000ff0900720b */
/* 0x000fda0004702400 */
/*0580*/ @P0 BRA 0x650 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0590*/ FSETP.NEU.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f0d200 */
/*05a0*/ FSETP.EQ.AND P2, PT, R9, -1, PT ; /* 0xbf8000000900780b */
/* 0x000fda0003f42000 */
/*05b0*/ @!P0 BRA P2, 0x6d0 ; /* 0x0000011000008947 */
/* 0x000fea0001000000 */
/*05c0*/ FSETP.GEU.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe40003f0e000 */
/*05d0*/ MOV R11, R10 ; /* 0x0000000a000b7202 */
/* 0x000fd60000000f00 */
/*05e0*/ @P0 BRA 0x6d0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*05f0*/ FRND.FLOOR R9, R6 ; /* 0x0000000600097307 */
/* 0x000e220000205000 */
/*0600*/ FSETP.NEU.AND P2, PT, |R13|, 1, PT ; /* 0x3f8000000d00780b */
/* 0x000fc80003f4d200 */
/*0610*/ FSEL R11, -R10, R10, !P2 ; /* 0x0000000a0a0b7208 */
/* 0x000fe40005000100 */
/*0620*/ FSETP.NEU.AND P0, PT, R9, R6, PT ; /* 0x000000060900720b */
/* 0x001fc80003f0d000 */
/*0630*/ FSEL R11, R11, +QNAN , !P0 ; /* 0x7fffffff0b0b7808 */
/* 0x000fe20004000000 */
/*0640*/ BRA 0x6d0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0650*/ FSETP.GEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fe20003f0e000 */
/*0660*/ FADD R9, R9, R9 ; /* 0x0000000909097221 */
/* 0x000fe20000000000 */
/*0670*/ FSETP.NEU.AND P2, PT, |R13|, 1, PT ; /* 0x3f8000000d00780b */
/* 0x000fd60003f4d200 */
/*0680*/ @!P0 LOP3.LUT R9, R9, 0x7f800000, RZ, 0x3c, !PT ; /* 0x7f80000009098812 */
/* 0x000fc800078e3cff */
/*0690*/ @P2 LOP3.LUT R9, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09092812 */
/* 0x000fc800078ec0ff */
/*06a0*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*06b0*/ BRA 0x6d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06c0*/ FADD R11, R6, R9 ; /* 0x00000009060b7221 */
/* 0x000fe40000000000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*06f0*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x000fc800078e0204 */
/*0700*/ IMAD.WIDE R2, R7, 0x4, R2 ; /* 0x0000000407027825 */
/* 0x001fe200078e0202 */
/*0710*/ @!P1 BRA 0xc0 ; /* 0xfffff9a000009947 */
/* 0x000fea000383ffff */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14raise_to_poweriPfS_
.globl _Z14raise_to_poweriPfS_
.p2align 8
.type _Z14raise_to_poweriPfS_,@function
_Z14raise_to_poweriPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s9, 0x3e76c4e1
.LBB0_2:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
s_waitcnt vmcnt(1)
v_cmp_neq_f32_e32 vcc_lo, 1.0, v0
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v4, 1.0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_neq_f32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v0, 1.0, v0, vcc_lo
v_frexp_mant_f32_e64 v5, |v0|
v_frexp_exp_i32_f32_e32 v8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v9, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v5, v5, v9
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 1.0, v5
v_dual_add_f32 v10, -1.0, v5 :: v_dual_mul_f32 v13, 0x3f317218, v8
v_cmp_neq_f32_e64 s13, v4, |v4|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v14, v10, v11
v_add_f32_e32 v12, -1.0, v9
v_sub_f32_e32 v5, v5, v12
v_fma_f32 v12, v8, 0x3f317218, -v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, 0xb102e308, v8
v_add_f32_e32 v15, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v13, v15, v13 :: v_dual_mul_f32 v8, v9, v14
v_cmp_lt_f32_e64 s14, |v0|, 1.0
v_fma_f32 v9, v14, v9, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s13, s13, s14
v_fmac_f32_e32 v9, v14, v5
v_sub_f32_e32 v5, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v8, v9
v_sub_f32_e32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v13, v10, v12 :: v_dual_sub_f32 v8, v8, v9
v_sub_f32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v10, v12
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v13, v8
v_mul_f32_e32 v8, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v14, v8
v_sub_f32_e32 v10, v9, v14
v_mul_f32_e32 v11, v9, v9
v_ldexp_f32 v12, v9, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v8, v8, v10
v_fma_f32 v10, v9, v9, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v13, v8, v8
v_ldexp_f32 v14, v8, 1
v_fmac_f32_e32 v10, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v11, v10
v_sub_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v17, v9, v13 :: v_dual_sub_f32 v10, v10, v11
v_fma_f32 v11, v13, v9, -v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v16, s9, v13, 0x3e91f4c4 :: v_dual_fmac_f32 v11, v13, v8
v_dual_fmaak_f32 v16, v13, v16, 0x3ecccdef :: v_dual_fmac_f32 v11, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v18, v13, v16
v_add_f32_e32 v9, v17, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v13, v16, -v18
v_dual_sub_f32 v13, v9, v17 :: v_dual_fmac_f32 v8, v10, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v11, v11, v13 :: v_dual_add_f32 v10, v18, v8
v_add_f32_e32 v17, 0x3f2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v10, v18 :: v_dual_add_f32 v13, 0xbf2aaaaa, v17
v_sub_f32_e32 v8, v8, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v10, v13
v_add_f32_e32 v8, 0x31739010, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v8, v10
v_add_f32_e32 v10, v17, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v13, v17, v10
v_mul_f32_e32 v16, v9, v10
v_add_f32_e32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v9, v10, -v16
v_fmac_f32_e32 v13, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v11, v10
v_add_f32_e32 v8, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v12, v8
v_sub_f32_e32 v10, v8, v16
v_trunc_f32_e32 v16, v4
v_sub_f32_e32 v11, v9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v13, v10
v_cmp_eq_f32_e64 s0, v16, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v8, v8, v11
v_add_f32_e32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v10, v8
v_add_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v15, v10
v_dual_sub_f32 v9, v10, v9 :: v_dual_sub_f32 v12, v11, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v9, v11, v12
v_add_f32_e32 v13, v5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v10, v10, v12 :: v_dual_sub_f32 v9, v15, v9
v_sub_f32_e32 v12, v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v9, v10, v9 :: v_dual_sub_f32 v10, v13, v12
v_dual_sub_f32 v8, v8, v12 :: v_dual_add_f32 v9, v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v5, v10 :: v_dual_add_f32 v10, v11, v9
v_dual_add_f32 v5, v8, v5 :: v_dual_sub_f32 v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v9, v8
v_add_f32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v10, v5
v_sub_f32_e32 v9, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, v4, v8 :: v_dual_sub_f32 v5, v5, v9
v_fma_f32 v8, v4, v8, -v10
v_cmp_class_f32_e64 vcc_lo, v10, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v4, v5
v_add_f32_e32 v5, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v5, v10, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
v_cmp_neq_f32_e64 s1, 0x7f800000, |v9|
v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v9, v11
v_sub_f32_e32 v5, v5, v10
v_mul_f32_e32 v13, 0x3fb8aa3b, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v8, v5
v_fma_f32 v14, v12, 0x3fb8aa3b, -v13
v_rndne_f32_e32 v15, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, v5, s1
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v12
v_dual_fmac_f32 v14, 0x32a5705f, v12 :: v_dual_sub_f32 v13, v13, v15
v_cvt_i32_f32_e32 v10, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v11, v5
v_dual_add_f32 v13, v13, v14 :: v_dual_mul_f32 v14, 0.5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_exp_f32_e32 v13, v13
v_trunc_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_ldexp_f32 v8, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, v8, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v12
v_cndmask_b32_e64 v8, 0x7f800000, v8, s1
v_cmp_neq_f32_e64 s1, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v5, v8, v5, v8
v_cmp_eq_f32_e64 s2, 0x7f800000, v8
s_and_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, 1.0, v0, s1
v_cndmask_b32_e64 v11, 0, v0, s1
v_cndmask_b32_e64 v5, v5, v8, s2
v_cmp_eq_f32_e64 s2, 0, v0
v_cndmask_b32_e64 v8, |v4|, 0, s13
v_cmp_eq_f32_e64 s13, |v0|, 1.0
v_cmp_o_f32_e64 s1, v0, v4
v_bfi_b32 v5, 0x7fffffff, v5, v9
s_xor_b32 s14, vcc_lo, s2
v_cmp_gt_f32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v9, 0x7f800000, 0, s14
v_cndmask_b32_e64 v8, v8, |v0|, s13
v_cndmask_b32_e64 v10, 0x7fc00000, v5, s0
v_cmp_class_f32_e64 s0, v0, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v9, 0x7fffffff, v9, v11
v_cndmask_b32_e32 v5, v5, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_or_b32 vcc_lo, s2, s0
v_cmp_le_i32_e64 s0, s12, v1
v_cndmask_b32_e32 v5, v5, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v0, 0x7fc00000, v5, s1
s_or_b32 s3, s0, s3
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14raise_to_poweriPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14raise_to_poweriPfS_, .Lfunc_end0-_Z14raise_to_poweriPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14raise_to_poweriPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14raise_to_poweriPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ed4a5_00000000-6_raise_to_power.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
.type _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_, @function
_Z37__device_stub__Z14raise_to_poweriPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14raise_to_poweriPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_, .-_Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
.globl _Z14raise_to_poweriPfS_
.type _Z14raise_to_poweriPfS_, @function
_Z14raise_to_poweriPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14raise_to_poweriPfS_, .-_Z14raise_to_poweriPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z37__device_stub__Z14raise_to_poweriPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z14raise_to_poweriPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14raise_to_poweriPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1077936128
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1091567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "raise_to_power.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__raise_to_poweriPfS_ # -- Begin function _Z29__device_stub__raise_to_poweriPfS_
.p2align 4, 0x90
.type _Z29__device_stub__raise_to_poweriPfS_,@function
_Z29__device_stub__raise_to_poweriPfS_: # @_Z29__device_stub__raise_to_poweriPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14raise_to_poweriPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__raise_to_poweriPfS_, .Lfunc_end0-_Z29__device_stub__raise_to_poweriPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc1100000 # float -9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1077936128, (%rax,%rcx,4) # imm = 0x40400000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z14raise_to_poweriPfS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $10, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_8
# %bb.7:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_9
.LBB1_8:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14raise_to_poweriPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14raise_to_poweriPfS_,@object # @_Z14raise_to_poweriPfS_
.section .rodata,"a",@progbits
.globl _Z14raise_to_poweriPfS_
.p2align 3, 0x0
_Z14raise_to_poweriPfS_:
.quad _Z29__device_stub__raise_to_poweriPfS_
.size _Z14raise_to_poweriPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14raise_to_poweriPfS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__raise_to_poweriPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14raise_to_poweriPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
//#define N 1000
//#define M 512
//nvcc testing.cu -o test
#define BLOCK_SIZE 128
#define Rd 4
__global__ void stencil_1d(int *in, int *out, int RADIUS) {
__shared__ int temp[BLOCK_SIZE + 2 * Rd];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// Read input elements into shared memory
temp[lindex] = in[gindex];
if (threadIdx.x < RADIUS && blockIdx.x>0) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
else if(threadIdx.x < RADIUS && blockIdx.x<=0) {
temp[lindex - RADIUS] = 0;
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// Synchronize (ensure all the data is available)
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
__global__ void stencil_noMem(int *in, int *out, int RADIUS, int n) {
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
int idx = gindex + offset;
if(idx>0 && idx<n) {
result += in[idx];
}
}
// Store the result
out[gindex] = result;
}
void cpuStencil(int *in, int *out, int RADIUS, int n) {
// Apply the stencil
for (int i=0; i < n; i++) {
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
out[i] += in[i + offset];
}
}
}
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(int argc, char* argv[]) {
int N = atoi(argv[1]);
int R = atoi(argv[2]);
int *in, *out;
// device copies of a, b, c
int size = N * sizeof(int);
// Setup input values
in = (int*)malloc(size); random_ints(in, N);
out = (int*)malloc(size); random_ints(out, N);
if (strcmp(argv[3],"gpu")==0) {
// host copies of a, b, c
int *d_in, *d_out;
float milli;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord( start, 0 );
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_in, size);
cudaMalloc((void **)&d_out, size);
// Copy inputs to device
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
//stencil_1d<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R);
stencil_noMem<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R, N);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &milli, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
// Copy result back to host
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
cudaFree(d_in); cudaFree(d_out);
float nanosec = (milli)*1000000;
std::cout << "N: " << N << " R: " << R << " GPU time: " << nanosec << " ns" << std::endl;
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
cpuStencil(in,out,R, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>( t2 - t1 ).count();
std::cout << "N: " << N << " R: " << R << " CPU time: " << duration << " ns" << std::endl;
//time = 100.0;
}
//printf("a[0]: %i, b[0]: %i, c[0]: %i\nGPU Time: %f\n", a[0], b[0], c[0], time);
//printf("N: %i M: %i Time: %f\n", N, M, time);
// Cleanup
free(in); free(out);
return 0;
} | code for sm_80
Function : _Z13stencil_noMemPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV R7, RZ, RZ, -c[0x0][0x170] ; /* 0x80005c00ff077624 */
/* 0x000fe200078e02ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R6, c[0x0][0x0], R11 ; /* 0x0000000006007a24 */
/* 0x001fd800078e020b */
/*0080*/ @P0 BRA 0x470 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMNMX R9, R7, c[0x0][0x170], !PT ; /* 0x00005c0007097a17 */
/* 0x000fc80007800200 */
/*00a0*/ IADD3 R3, R9, c[0x0][0x170], RZ ; /* 0x00005c0009037a10 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x040fe40003f06070 */
/*00c0*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00e0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fc800078ec0ff */
/*00f0*/ ISETP.NE.AND P4, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f85270 */
/*0100*/ @!P0 BRA 0x360 ; /* 0x0000025000008947 */
/* 0x000ff40003800000 */
/*0110*/ IADD3 R4, R0.reuse, -c[0x0][0x170], RZ ; /* 0x80005c0000047a10 */
/* 0x040fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R8, R0, 0x3, RZ ; /* 0x0000000300087810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R18, R2, -0x1, -R9 ; /* 0xffffffff02127810 */
/* 0x000fe20007ffe809 */
/*0160*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0170*/ IADD3 R8, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008087a10 */
/* 0x000fc60007ffe0ff */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*01a0*/ IMAD.IADD R4, R0, 0x1, R7 ; /* 0x0000000100047824 */
/* 0x000fe200078e0207 */
/*01b0*/ IADD3 R5, R8.reuse, -0x2, RZ ; /* 0xfffffffe08057810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ IADD3 R9, R8, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x040fe40003f06270 */
/*01e0*/ ISETP.GE.AND P1, PT, R5.reuse, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x040fe40003f26270 */
/*01f0*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fe20000701670 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*0210*/ ISETP.LT.OR P1, PT, R5, 0x1, P1 ; /* 0x000000010500780c */
/* 0x000fe20000f21670 */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0230*/ ISETP.GE.AND P2, PT, R9, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x000fc40003f46270 */
/*0240*/ ISETP.GE.AND P3, PT, R8.reuse, c[0x0][0x174], PT ; /* 0x00005d0008007a0c */
/* 0x040fe40003f66270 */
/*0250*/ ISETP.LT.OR P2, PT, R9, 0x1, P2 ; /* 0x000000010900780c */
/* 0x000fe40001741670 */
/*0260*/ ISETP.LT.OR P3, PT, R8, 0x1, P3 ; /* 0x000000010800780c */
/* 0x000fc60001f61670 */
/*0270*/ @!P0 LDG.E R10, [R4.64] ; /* 0x00000004040a8981 */
/* 0x000ea8000c1e1900 */
/*0280*/ @!P1 LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c9981 */
/* 0x000ee8000c1e1900 */
/*0290*/ @!P2 LDG.E R14, [R4.64+0x8] ; /* 0x00000804040ea981 */
/* 0x000f28000c1e1900 */
/*02a0*/ @!P3 LDG.E R16, [R4.64+0xc] ; /* 0x00000c040410b981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007ffe0ff */
/*02d0*/ IMAD.IADD R9, R18, 0x1, R7 ; /* 0x0000000112097824 */
/* 0x000fe400078e0207 */
/*02e0*/ @!P0 IMAD.IADD R3, R3, 0x1, R10 ; /* 0x0000000103038824 */
/* 0x004fc600078e020a */
/*02f0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0300*/ @!P1 IMAD.IADD R3, R3, 0x1, R12 ; /* 0x0000000103039824 */
/* 0x008fe200078e020c */
/*0310*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc60007f3e0ff */
/*0320*/ @!P2 IMAD.IADD R3, R3, 0x1, R14 ; /* 0x000000010303a824 */
/* 0x010fe400078e020e */
/*0330*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0605 */
/*0340*/ @!P3 IMAD.IADD R3, R3, 0x1, R16 ; /* 0x000000010303b824 */
/* 0x020fc800078e0210 */
/*0350*/ @P0 BRA 0x1a0 ; /* 0xfffffe4000000947 */
/* 0x000fea000383ffff */
/*0360*/ @!P4 BRA 0x470 ; /* 0x000001000000c947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fe400078e0207 */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD R6, R6, c[0x0][0x0], R7 ; /* 0x0000000006067a24 */
/* 0x000fc800078e0207 */
/*03a0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0205 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*03c0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fc80003f06270 */
/*03d0*/ ISETP.LT.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000701670 */
/*03e0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff048224 */
/* 0x000fcc00078e0007 */
/*03f0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x0000a2000c1e1900 */
/*0400*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R7, P2, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f5e0ff */
/*0420*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0430*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x001fe400010e0605 */
/*0450*/ @!P0 IMAD.IADD R3, R3, 0x1, R4 ; /* 0x0000000103038824 */
/* 0x004fd000078e0204 */
/*0460*/ @P1 BRA 0x3c0 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0470*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0480*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0490*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10stencil_1dPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R2 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e020b */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IADD3 R8, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002087a10 */
/* 0x040fe20007ffe0ff */
/*0090*/ BSSY B0, 0x1d0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD.SHL.U32 R9, R2.reuse, 0x4, RZ ; /* 0x0000000402097824 */
/* 0x040fe200078e00ff */
/*00c0*/ ISETP.LT.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f21070 */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00e0*/ STS [R8.X4], R7 ; /* 0x0000000708007388 */
/* 0x0041f40000004800 */
/*00f0*/ @P0 BRA P1, 0x160 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0100*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*0110*/ @P0 BRA 0x1c0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R5, [R4.64+0x200] ; /* 0x0002000404057981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0003e80000004800 */
/*0140*/ STS [R8.X4+0x200], R5 ; /* 0x0002000508007388 */
/* 0x0043e20000004800 */
/*0150*/ BRA 0x1c0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000067a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ LDG.E R5, [R4.64+0x200] ; /* 0x0002000404057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x001fcc00078e020b */
/*0190*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0081e80000004800 */
/*01b0*/ STS [R8.X4+0x200], R5 ; /* 0x0002000508007388 */
/* 0x0041e40000004800 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -c[0x0][0x170] ; /* 0x80005c00ff077624 */
/* 0x001fe200078e02ff */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x002fc600078e00ff */
/*0200*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f04270 */
/*0210*/ @P0 BRA 0x7a0 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMNMX R4, R7, c[0x0][0x170], !PT ; /* 0x00005c0007047a17 */
/* 0x000fe20007800200 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*0240*/ IADD3 R11, R4, c[0x0][0x170], RZ ; /* 0x00005c00040b7a10 */
/* 0x000fc80007ffe0ff */
/*0250*/ ISETP.GE.U32.AND P0, PT, R11.reuse, 0x3, PT ; /* 0x000000030b00780c */
/* 0x040fe40003f06070 */
/*0260*/ IADD3 R4, R11, 0x1, RZ ; /* 0x000000010b047810 */
/* 0x000fc80007ffe0ff */
/*0270*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fce00078ec0ff */
/*0280*/ @!P0 BRA 0x700 ; /* 0x0000047000008947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.IADD R6, R11, 0x1, -R4 ; /* 0x000000010b067824 */
/* 0x000fe200078e0a04 */
/*02a0*/ IADD3 R8, R9, 0x8, RZ ; /* 0x0000000809087810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*02c0*/ ISETP.GT.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fda0003f04270 */
/*02d0*/ @!P0 BRA 0x650 ; /* 0x0000037000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0300*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fda0003f24270 */
/*0310*/ @!P1 BRA 0x500 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0330*/ LDS R14, [R8+-0x8] ; /* 0xfffff800080e7984 */
/* 0x000fe20000000800 */
/*0340*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe20007ffe0ff */
/*0360*/ LDS R13, [R8+-0x4] ; /* 0xfffffc00080d7984 */
/* 0x000e220000000800 */
/*0370*/ ISETP.GT.AND P1, PT, R6, 0xb, PT ; /* 0x0000000b0600780c */
/* 0x000fc60003f24270 */
/*0380*/ LDS R16, [R8] ; /* 0x0000000008107984 */
/* 0x000fe80000000800 */
/*0390*/ LDS R15, [R8+0x4] ; /* 0x00000400080f7984 */
/* 0x000e680000000800 */
/*03a0*/ LDS R18, [R8+0x8] ; /* 0x0000080008127984 */
/* 0x000fe80000000800 */
/*03b0*/ LDS R17, [R8+0xc] ; /* 0x00000c0008117984 */
/* 0x000ea80000000800 */
/*03c0*/ LDS R20, [R8+0x10] ; /* 0x0000100008147984 */
/* 0x000fe80000000800 */
/*03d0*/ LDS R19, [R8+0x14] ; /* 0x0000140008137984 */
/* 0x000ee80000000800 */
/*03e0*/ LDS R22, [R8+0x18] ; /* 0x0000180008167984 */
/* 0x000fe80000000800 */
/*03f0*/ LDS R21, [R8+0x1c] ; /* 0x00001c0008157984 */
/* 0x000f280000000800 */
/*0400*/ LDS R24, [R8+0x20] ; /* 0x0000200008187984 */
/* 0x000fe80000000800 */
/*0410*/ LDS R23, [R8+0x24] ; /* 0x0000240008177984 */
/* 0x000f620000000800 */
/*0420*/ IADD3 R13, R13, R14, R5 ; /* 0x0000000e0d0d7210 */
/* 0x001fc60007ffe005 */
/*0430*/ LDS R12, [R8+0x28] ; /* 0x00002800080c7984 */
/* 0x000fe80000000800 */
/*0440*/ LDS R11, [R8+0x2c] ; /* 0x00002c00080b7984 */
/* 0x000e220000000800 */
/*0450*/ IADD3 R13, R15, R16, R13 ; /* 0x000000100f0d7210 */
/* 0x002fc60007ffe00d */
/*0460*/ LDS R10, [R8+0x30] ; /* 0x00003000080a7984 */
/* 0x000fe80000000800 */
/*0470*/ LDS R9, [R8+0x34] ; /* 0x0000340008097984 */
/* 0x0002220000000800 */
/*0480*/ IADD3 R13, R17, R18, R13 ; /* 0x00000012110d7210 */
/* 0x004fc80007ffe00d */
/*0490*/ IADD3 R13, R19, R20, R13 ; /* 0x00000014130d7210 */
/* 0x008fe40007ffe00d */
/*04a0*/ IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x002fe40007ffe0ff */
/*04b0*/ IADD3 R13, R21, R22, R13 ; /* 0x00000016150d7210 */
/* 0x010fc80007ffe00d */
/*04c0*/ IADD3 R13, R23, R24, R13 ; /* 0x00000018170d7210 */
/* 0x020fc80007ffe00d */
/*04d0*/ IADD3 R11, R11, R12, R13 ; /* 0x0000000c0b0b7210 */
/* 0x001fc80007ffe00d */
/*04e0*/ IADD3 R5, R9, R10, R11 ; /* 0x0000000a09057210 */
/* 0x000fe20007ffe00b */
/*04f0*/ @P1 BRA 0x330 ; /* 0xfffffe3000001947 */
/* 0x000fea000383ffff */
/*0500*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0520*/ @!P1 BRA 0x630 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0530*/ LDS R10, [R8+-0x8] ; /* 0xfffff800080a7984 */
/* 0x000fe20000000800 */
/*0540*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0550*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0560*/ LDS R9, [R8+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000e220000000800 */
/*0570*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*0580*/ LDS R12, [R8] ; /* 0x00000000080c7984 */
/* 0x000fe80000000800 */
/*0590*/ LDS R11, [R8+0x4] ; /* 0x00000400080b7984 */
/* 0x000e680000000800 */
/*05a0*/ LDS R14, [R8+0x8] ; /* 0x00000800080e7984 */
/* 0x000fe80000000800 */
/*05b0*/ LDS R13, [R8+0xc] ; /* 0x00000c00080d7984 */
/* 0x000ea80000000800 */
/*05c0*/ LDS R16, [R8+0x10] ; /* 0x0000100008107984 */
/* 0x000fe80000000800 */
/*05d0*/ LDS R15, [R8+0x14] ; /* 0x00001400080f7984 */
/* 0x0007240000000800 */
/*05e0*/ IADD3 R8, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x008fc40007ffe0ff */
/*05f0*/ IADD3 R9, R9, R10, R5 ; /* 0x0000000a09097210 */
/* 0x001fc80007ffe005 */
/*0600*/ IADD3 R9, R11, R12, R9 ; /* 0x0000000c0b097210 */
/* 0x002fc80007ffe009 */
/*0610*/ IADD3 R9, R13, R14, R9 ; /* 0x0000000e0d097210 */
/* 0x004fc80007ffe009 */
/*0620*/ IADD3 R5, R15, R16, R9 ; /* 0x000000100f057210 */
/* 0x010fe40007ffe009 */
/*0630*/ ISETP.NE.OR P0, PT, R6, -0x1, P0 ; /* 0xffffffff0600780c */
/* 0x000fda0000705670 */
/*0640*/ @!P0 BRA 0x700 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0650*/ LDS R10, [R8+-0x8] ; /* 0xfffff800080a7984 */
/* 0x000fe20000000800 */
/*0660*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe40007ffe0ff */
/*0670*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0680*/ LDS R9, [R8+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000e220000000800 */
/*0690*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fc60003f05270 */
/*06a0*/ LDS R12, [R8] ; /* 0x00000000080c7984 */
/* 0x000fe80000000800 */
/*06b0*/ LDS R11, [R8+0x4] ; /* 0x00000400080b7984 */
/* 0x0002a40000000800 */
/*06c0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x002fe40007ffe0ff */
/*06d0*/ IADD3 R5, R9, R10, R5 ; /* 0x0000000a09057210 */
/* 0x001fc80007ffe005 */
/*06e0*/ IADD3 R5, R11, R12, R5 ; /* 0x0000000c0b057210 */
/* 0x004fe20007ffe005 */
/*06f0*/ @P0 BRA 0x650 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0700*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0710*/ @!P0 BRA 0x7a0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R2, R2, c[0x0][0x170], R7 ; /* 0x00005c0002027a10 */
/* 0x000fca0007ffe007 */
/*0730*/ IMAD.SHL.U32 R2, R2, 0x4, RZ ; /* 0x0000000402027824 */
/* 0x000fca00078e00ff */
/*0740*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x0000620000000800 */
/*0750*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0770*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe20007ffe0ff */
/*0780*/ IMAD.IADD R5, R6, 0x1, R5 ; /* 0x0000000106057824 */
/* 0x002fd400078e0205 */
/*0790*/ @P0 BRA 0x740 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*07a0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*07b0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*07c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
//#define N 1000
//#define M 512
//nvcc testing.cu -o test
#define BLOCK_SIZE 128
#define Rd 4
__global__ void stencil_1d(int *in, int *out, int RADIUS) {
__shared__ int temp[BLOCK_SIZE + 2 * Rd];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// Read input elements into shared memory
temp[lindex] = in[gindex];
if (threadIdx.x < RADIUS && blockIdx.x>0) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
else if(threadIdx.x < RADIUS && blockIdx.x<=0) {
temp[lindex - RADIUS] = 0;
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// Synchronize (ensure all the data is available)
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
__global__ void stencil_noMem(int *in, int *out, int RADIUS, int n) {
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
int idx = gindex + offset;
if(idx>0 && idx<n) {
result += in[idx];
}
}
// Store the result
out[gindex] = result;
}
void cpuStencil(int *in, int *out, int RADIUS, int n) {
// Apply the stencil
for (int i=0; i < n; i++) {
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
out[i] += in[i + offset];
}
}
}
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(int argc, char* argv[]) {
int N = atoi(argv[1]);
int R = atoi(argv[2]);
int *in, *out;
// device copies of a, b, c
int size = N * sizeof(int);
// Setup input values
in = (int*)malloc(size); random_ints(in, N);
out = (int*)malloc(size); random_ints(out, N);
if (strcmp(argv[3],"gpu")==0) {
// host copies of a, b, c
int *d_in, *d_out;
float milli;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord( start, 0 );
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_in, size);
cudaMalloc((void **)&d_out, size);
// Copy inputs to device
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
//stencil_1d<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R);
stencil_noMem<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R, N);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &milli, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
// Copy result back to host
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
cudaFree(d_in); cudaFree(d_out);
float nanosec = (milli)*1000000;
std::cout << "N: " << N << " R: " << R << " GPU time: " << nanosec << " ns" << std::endl;
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
cpuStencil(in,out,R, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>( t2 - t1 ).count();
std::cout << "N: " << N << " R: " << R << " CPU time: " << duration << " ns" << std::endl;
//time = 100.0;
}
//printf("a[0]: %i, b[0]: %i, c[0]: %i\nGPU Time: %f\n", a[0], b[0], c[0], time);
//printf("N: %i M: %i Time: %f\n", N, M, time);
// Cleanup
free(in); free(out);
return 0;
} | .file "tmpxft_0009269e_00000000-6_1Dstencil.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3906:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3906:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10cpuStencilPiS_ii
.type _Z10cpuStencilPiS_ii, @function
_Z10cpuStencilPiS_ii:
.LFB3899:
.cfi_startproc
endbr64
movl %edx, %r9d
movl %ecx, %r10d
testl %ecx, %ecx
jle .L3
movl %edx, %r11d
negl %r11d
leal (%r9,%r9), %r8d
movslq %r11d, %rdx
addq %r8, %rdx
leaq 4(%rdi,%rdx,4), %rcx
movl $0, %edi
notq %r8
salq $2, %r8
.L7:
cmpl %r11d, %r9d
jl .L5
leaq (%r8,%rcx), %rax
.L6:
movl (%rax), %edx
addl %edx, (%rsi)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L5:
addl $1, %edi
addq $4, %rsi
addq $4, %rcx
cmpl %edi, %r10d
jne .L7
.L3:
ret
.cfi_endproc
.LFE3899:
.size _Z10cpuStencilPiS_ii, .-_Z10cpuStencilPiS_ii
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3900:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3900:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.type _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, @function
_Z33__device_stub__Z10stencil_1dPiS_iPiS_i:
.LFB3928:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10stencil_1dPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3928:
.size _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, .-_Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.globl _Z10stencil_1dPiS_i
.type _Z10stencil_1dPiS_i, @function
_Z10stencil_1dPiS_i:
.LFB3929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3929:
.size _Z10stencil_1dPiS_i, .-_Z10stencil_1dPiS_i
.globl _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
.type _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii, @function
_Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii:
.LFB3930:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13stencil_noMemPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3930:
.size _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii, .-_Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
.globl _Z13stencil_noMemPiS_ii
.type _Z13stencil_noMemPiS_ii, @function
_Z13stencil_noMemPiS_ii:
.LFB3931:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3931:
.size _Z13stencil_noMemPiS_ii, .-_Z13stencil_noMemPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gpu"
.LC2:
.string "N: "
.LC3:
.string " R: "
.LC4:
.string " GPU time: "
.LC5:
.string " ns"
.LC6:
.string " CPU time: "
.text
.globl main
.type main, @function
main:
.LFB3901:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
movq 16(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
leal 0(,%rbx,4), %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %esi
movq %rax, %rdi
call _Z11random_intsPii
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %esi
movq %rax, %rdi
call _Z11random_intsPii
movq 24(%r14), %rdi
leaq .LC0(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L35
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leal 127(%rbx), %eax
movl $128, %ecx
cltd
idivl %ecx
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movss .LC1(%rip), %xmm0
mulss 60(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L37:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl %ebx, %ecx
movl 8(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
jmp .L36
.L35:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl %ebx, %ecx
movl 8(%rsp), %r14d
movl %r14d, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z10cpuStencilPiS_ii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbp, %rax
movq %rax, %rbx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L37
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3901:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13stencil_noMemPiS_ii"
.LC8:
.string "_Z10stencil_1dPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3933:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13stencil_noMemPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_1dPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3933:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
//#define N 1000
//#define M 512
//nvcc testing.cu -o test
#define BLOCK_SIZE 128
#define Rd 4
__global__ void stencil_1d(int *in, int *out, int RADIUS) {
__shared__ int temp[BLOCK_SIZE + 2 * Rd];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// Read input elements into shared memory
temp[lindex] = in[gindex];
if (threadIdx.x < RADIUS && blockIdx.x>0) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
else if(threadIdx.x < RADIUS && blockIdx.x<=0) {
temp[lindex - RADIUS] = 0;
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// Synchronize (ensure all the data is available)
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
__global__ void stencil_noMem(int *in, int *out, int RADIUS, int n) {
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
int idx = gindex + offset;
if(idx>0 && idx<n) {
result += in[idx];
}
}
// Store the result
out[gindex] = result;
}
void cpuStencil(int *in, int *out, int RADIUS, int n) {
// Apply the stencil
for (int i=0; i < n; i++) {
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
out[i] += in[i + offset];
}
}
}
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(int argc, char* argv[]) {
int N = atoi(argv[1]);
int R = atoi(argv[2]);
int *in, *out;
// device copies of a, b, c
int size = N * sizeof(int);
// Setup input values
in = (int*)malloc(size); random_ints(in, N);
out = (int*)malloc(size); random_ints(out, N);
if (strcmp(argv[3],"gpu")==0) {
// host copies of a, b, c
int *d_in, *d_out;
float milli;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord( start, 0 );
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_in, size);
cudaMalloc((void **)&d_out, size);
// Copy inputs to device
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
//stencil_1d<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R);
stencil_noMem<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R, N);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &milli, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
// Copy result back to host
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
cudaFree(d_in); cudaFree(d_out);
float nanosec = (milli)*1000000;
std::cout << "N: " << N << " R: " << R << " GPU time: " << nanosec << " ns" << std::endl;
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
cpuStencil(in,out,R, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>( t2 - t1 ).count();
std::cout << "N: " << N << " R: " << R << " CPU time: " << duration << " ns" << std::endl;
//time = 100.0;
}
//printf("a[0]: %i, b[0]: %i, c[0]: %i\nGPU Time: %f\n", a[0], b[0], c[0], time);
//printf("N: %i M: %i Time: %f\n", N, M, time);
// Cleanup
free(in); free(out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
//#define N 1000
//#define M 512
//nvcc testing.cu -o test
#define BLOCK_SIZE 128
#define Rd 4
__global__ void stencil_1d(int *in, int *out, int RADIUS) {
__shared__ int temp[BLOCK_SIZE + 2 * Rd];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// Read input elements into shared memory
temp[lindex] = in[gindex];
if (threadIdx.x < RADIUS && blockIdx.x>0) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
else if(threadIdx.x < RADIUS && blockIdx.x<=0) {
temp[lindex - RADIUS] = 0;
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// Synchronize (ensure all the data is available)
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
__global__ void stencil_noMem(int *in, int *out, int RADIUS, int n) {
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
int idx = gindex + offset;
if(idx>0 && idx<n) {
result += in[idx];
}
}
// Store the result
out[gindex] = result;
}
void cpuStencil(int *in, int *out, int RADIUS, int n) {
// Apply the stencil
for (int i=0; i < n; i++) {
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
out[i] += in[i + offset];
}
}
}
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(int argc, char* argv[]) {
int N = atoi(argv[1]);
int R = atoi(argv[2]);
int *in, *out;
// device copies of a, b, c
int size = N * sizeof(int);
// Setup input values
in = (int*)malloc(size); random_ints(in, N);
out = (int*)malloc(size); random_ints(out, N);
if (strcmp(argv[3],"gpu")==0) {
// host copies of a, b, c
int *d_in, *d_out;
float milli;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord( start, 0 );
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_in, size);
hipMalloc((void **)&d_out, size);
// Copy inputs to device
hipMemcpy(d_in, in, size, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU
//stencil_1d<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R);
stencil_noMem<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R, N);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &milli, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
// Copy result back to host
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
hipFree(d_in); hipFree(d_out);
float nanosec = (milli)*1000000;
std::cout << "N: " << N << " R: " << R << " GPU time: " << nanosec << " ns" << std::endl;
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
cpuStencil(in,out,R, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>( t2 - t1 ).count();
std::cout << "N: " << N << " R: " << R << " CPU time: " << duration << " ns" << std::endl;
//time = 100.0;
}
//printf("a[0]: %i, b[0]: %i, c[0]: %i\nGPU Time: %f\n", a[0], b[0], c[0], time);
//printf("N: %i M: %i Time: %f\n", N, M, time);
// Cleanup
free(in); free(out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
//#define N 1000
//#define M 512
//nvcc testing.cu -o test
#define BLOCK_SIZE 128
#define Rd 4
__global__ void stencil_1d(int *in, int *out, int RADIUS) {
__shared__ int temp[BLOCK_SIZE + 2 * Rd];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// Read input elements into shared memory
temp[lindex] = in[gindex];
if (threadIdx.x < RADIUS && blockIdx.x>0) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
else if(threadIdx.x < RADIUS && blockIdx.x<=0) {
temp[lindex - RADIUS] = 0;
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// Synchronize (ensure all the data is available)
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
__global__ void stencil_noMem(int *in, int *out, int RADIUS, int n) {
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
int idx = gindex + offset;
if(idx>0 && idx<n) {
result += in[idx];
}
}
// Store the result
out[gindex] = result;
}
void cpuStencil(int *in, int *out, int RADIUS, int n) {
// Apply the stencil
for (int i=0; i < n; i++) {
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
out[i] += in[i + offset];
}
}
}
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(int argc, char* argv[]) {
int N = atoi(argv[1]);
int R = atoi(argv[2]);
int *in, *out;
// device copies of a, b, c
int size = N * sizeof(int);
// Setup input values
in = (int*)malloc(size); random_ints(in, N);
out = (int*)malloc(size); random_ints(out, N);
if (strcmp(argv[3],"gpu")==0) {
// host copies of a, b, c
int *d_in, *d_out;
float milli;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord( start, 0 );
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_in, size);
hipMalloc((void **)&d_out, size);
// Copy inputs to device
hipMemcpy(d_in, in, size, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU
//stencil_1d<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R);
stencil_noMem<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R, N);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &milli, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
// Copy result back to host
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
hipFree(d_in); hipFree(d_out);
float nanosec = (milli)*1000000;
std::cout << "N: " << N << " R: " << R << " GPU time: " << nanosec << " ns" << std::endl;
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
cpuStencil(in,out,R, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>( t2 - t1 ).count();
std::cout << "N: " << N << " R: " << R << " CPU time: " << duration << " ns" << std::endl;
//time = 100.0;
}
//printf("a[0]: %i, b[0]: %i, c[0]: %i\nGPU Time: %f\n", a[0], b[0], c[0], time);
//printf("N: %i M: %i Time: %f\n", N, M, time);
// Cleanup
free(in); free(out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_1dPiS_i
.globl _Z10stencil_1dPiS_i
.p2align 8
.type _Z10stencil_1dPiS_i,@function
_Z10stencil_1dPiS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_add_nc_u32_e32 v5, s3, v0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_le_u32_e64 s2, s3, v0
s_cmp_eq_u32 s15, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 2, v5
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s3, v0
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v6
s_and_saveexec_b32 s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s8
s_cmp_eq_u32 s15, 0
s_mov_b32 s7, 0
s_cselect_b32 s6, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s6, vcc_lo
s_and_b32 s6, s6, exec_lo
s_or_saveexec_b32 s2, s2
v_mov_b32_e32 v6, s7
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v6, s3, v1
s_or_b32 s6, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_6
global_load_b32 v3, v[3:4], off offset:512
v_lshlrev_b32_e32 v4, 2, v0
v_lshlrev_b32_e32 v5, 2, v5
s_waitcnt vmcnt(1)
ds_store_b32 v4, v6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3 offset:512
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v3, 0
s_cmp_lt_i32 s3, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_lshl_b32 s2, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, 1
.LBB0_8:
ds_load_b32 v4, v0
v_add_nc_u32_e32 v0, 4, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
s_cbranch_scc0 .LBB0_8
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_1dPiS_i
.amdhsa_group_segment_fixed_size 544
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_1dPiS_i, .Lfunc_end0-_Z10stencil_1dPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13stencil_noMemPiS_ii
.globl _Z13stencil_noMemPiS_ii
.p2align 8
.type _Z13stencil_noMemPiS_ii,@function
_Z13stencil_noMemPiS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 0
s_mul_i32 s15, s15, s3
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x14
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v1
v_mov_b32_e32 v3, v2
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s2, 1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, 1, v1
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s7, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB1_2
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
s_branch .LBB1_2
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v0, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13stencil_noMemPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13stencil_noMemPiS_ii, .Lfunc_end1-_Z13stencil_noMemPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 544
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_1dPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_1dPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13stencil_noMemPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13stencil_noMemPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <chrono>
//#define N 1000
//#define M 512
//nvcc testing.cu -o test
#define BLOCK_SIZE 128
#define Rd 4
__global__ void stencil_1d(int *in, int *out, int RADIUS) {
__shared__ int temp[BLOCK_SIZE + 2 * Rd];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
// Read input elements into shared memory
temp[lindex] = in[gindex];
if (threadIdx.x < RADIUS && blockIdx.x>0) {
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
else if(threadIdx.x < RADIUS && blockIdx.x<=0) {
temp[lindex - RADIUS] = 0;
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
// Synchronize (ensure all the data is available)
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
__global__ void stencil_noMem(int *in, int *out, int RADIUS, int n) {
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
// Apply the stencil
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
int idx = gindex + offset;
if(idx>0 && idx<n) {
result += in[idx];
}
}
// Store the result
out[gindex] = result;
}
void cpuStencil(int *in, int *out, int RADIUS, int n) {
// Apply the stencil
for (int i=0; i < n; i++) {
for (int offset = -RADIUS ; offset <= RADIUS ; offset++) {
out[i] += in[i + offset];
}
}
}
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(int argc, char* argv[]) {
int N = atoi(argv[1]);
int R = atoi(argv[2]);
int *in, *out;
// device copies of a, b, c
int size = N * sizeof(int);
// Setup input values
in = (int*)malloc(size); random_ints(in, N);
out = (int*)malloc(size); random_ints(out, N);
if (strcmp(argv[3],"gpu")==0) {
// host copies of a, b, c
int *d_in, *d_out;
float milli;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord( start, 0 );
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_in, size);
hipMalloc((void **)&d_out, size);
// Copy inputs to device
hipMemcpy(d_in, in, size, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU
//stencil_1d<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R);
stencil_noMem<<<(N + BLOCK_SIZE-1) / BLOCK_SIZE,BLOCK_SIZE>>>(d_in, d_out, R, N);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &milli, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
// Copy result back to host
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
hipFree(d_in); hipFree(d_out);
float nanosec = (milli)*1000000;
std::cout << "N: " << N << " R: " << R << " GPU time: " << nanosec << " ns" << std::endl;
}
else {
auto t1 = std::chrono::high_resolution_clock::now();
cpuStencil(in,out,R, N);
auto t2 = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>( t2 - t1 ).count();
std::cout << "N: " << N << " R: " << R << " CPU time: " << duration << " ns" << std::endl;
//time = 100.0;
}
//printf("a[0]: %i, b[0]: %i, c[0]: %i\nGPU Time: %f\n", a[0], b[0], c[0], time);
//printf("N: %i M: %i Time: %f\n", N, M, time);
// Cleanup
free(in); free(out);
return 0;
} | .text
.file "1Dstencil.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__stencil_1dPiS_i # -- Begin function _Z25__device_stub__stencil_1dPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__stencil_1dPiS_i,@function
_Z25__device_stub__stencil_1dPiS_i: # @_Z25__device_stub__stencil_1dPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10stencil_1dPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_1dPiS_i, .Lfunc_end0-_Z25__device_stub__stencil_1dPiS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__stencil_noMemPiS_ii # -- Begin function _Z28__device_stub__stencil_noMemPiS_ii
.p2align 4, 0x90
.type _Z28__device_stub__stencil_noMemPiS_ii,@function
_Z28__device_stub__stencil_noMemPiS_ii: # @_Z28__device_stub__stencil_noMemPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13stencil_noMemPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__stencil_noMemPiS_ii, .Lfunc_end1-_Z28__device_stub__stencil_noMemPiS_ii
.cfi_endproc
# -- End function
.globl _Z10cpuStencilPiS_ii # -- Begin function _Z10cpuStencilPiS_ii
.p2align 4, 0x90
.type _Z10cpuStencilPiS_ii,@function
_Z10cpuStencilPiS_ii: # @_Z10cpuStencilPiS_ii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
testl %ecx, %ecx
jle .LBB2_6
# %bb.1: # %.lr.ph16
movl %edx, %eax
negl %eax
movslq %eax, %r8
movl %ecx, %eax
leaq (%rdi,%r8,4), %rcx
leal (%rdx,%rdx), %edi
orq $1, %rdi
xorl %r8d, %r8d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r8
addq $4, %rcx
cmpq %rax, %r8
je .LBB2_6
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %edx, %edx
js .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl (%rsi,%r8,4), %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rcx,%r10,4), %r9d
movl %r9d, (%rsi,%r8,4)
incq %r10
cmpl %r10d, %edi
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z10cpuStencilPiS_ii, .Lfunc_end2-_Z10cpuStencilPiS_ii
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
retq
.Lfunc_end3:
.size _Z11random_intsPii, .Lfunc_end3-_Z11random_intsPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leal (,%r12,4), %eax
movslq %eax, %rdi
movq %rdi, 8(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
movl %r12d, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB4_2
.LBB4_3: # %_Z11random_intsPii.exit
movq 8(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r14
movq %r12, 32(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB4_6
# %bb.4: # %.lr.ph.preheader.i34
movl 32(%rsp), %r13d # 4-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB4_5
.LBB4_6: # %_Z11random_intsPii.exit40
movq 24(%rbp), %rdi
movl $.L.str, %esi
callq strcmp
testl %eax, %eax
je .LBB4_17
# %bb.7:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movq 32(%rsp), %r12 # 8-byte Reload
testl %r12d, %r12d
jle .LBB4_14
# %bb.8: # %.lr.ph16.i
movq %r15, %rdx
shlq $32, %rdx
negq %rdx
movq %rdx, %rsi
shrq $32, %rsi
movl %r12d, %eax
sarq $30, %rdx
movq %rbx, %rcx
addq %rdx, %rcx
movl %r15d, %edx
subl %esi, %edx
incl %edx
xorl %esi, %esi
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_9: # %._crit_edge.i
# in Loop: Header=BB4_10 Depth=1
incq %rsi
addq $4, %rcx
cmpq %rax, %rsi
je .LBB4_14
.LBB4_10: # =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
testl %r15d, %r15d
js .LBB4_9
# %bb.11: # %.lr.ph.i42
# in Loop: Header=BB4_10 Depth=1
movl (%r14,%rsi,4), %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_10 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rcx,%r8,4), %edi
incq %r8
cmpl %r8d, %edx
jne .LBB4_12
# %bb.13: # %._crit_edge.i.loopexit
# in Loop: Header=BB4_10 Depth=1
movl %edi, (%r14,%rsi,4)
jmp .LBB4_9
.LBB4_14: # %_Z10cpuStencilPiS_ii.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
subq %r13, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movq %rbp, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB4_24
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48
cmpb $0, 56(%r12)
je .LBB4_22
.LBB4_21:
movzbl 67(%r12), %eax
jmp .LBB4_23
.LBB4_17:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movq 8(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %r12 # 8-byte Reload
leal 127(%r12), %eax
leal 254(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $7, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_19
# %bb.18:
movq 48(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r15d, 60(%rsp)
movl %r12d, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13stencil_noMemPiS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_19:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI4_0(%rip), %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB4_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
jne .LBB4_21
.LBB4_22:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_24:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_1dPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13stencil_noMemPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_1dPiS_i,@object # @_Z10stencil_1dPiS_i
.section .rodata,"a",@progbits
.globl _Z10stencil_1dPiS_i
.p2align 3, 0x0
_Z10stencil_1dPiS_i:
.quad _Z25__device_stub__stencil_1dPiS_i
.size _Z10stencil_1dPiS_i, 8
.type _Z13stencil_noMemPiS_ii,@object # @_Z13stencil_noMemPiS_ii
.globl _Z13stencil_noMemPiS_ii
.p2align 3, 0x0
_Z13stencil_noMemPiS_ii:
.quad _Z28__device_stub__stencil_noMemPiS_ii
.size _Z13stencil_noMemPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "gpu"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N: "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " R: "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " GPU time: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " ns"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " CPU time: "
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencil_1dPiS_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13stencil_noMemPiS_ii"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_1dPiS_i
.addrsig_sym _Z28__device_stub__stencil_noMemPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_1dPiS_i
.addrsig_sym _Z13stencil_noMemPiS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13stencil_noMemPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV R7, RZ, RZ, -c[0x0][0x170] ; /* 0x80005c00ff077624 */
/* 0x000fe200078e02ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R6, c[0x0][0x0], R11 ; /* 0x0000000006007a24 */
/* 0x001fd800078e020b */
/*0080*/ @P0 BRA 0x470 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMNMX R9, R7, c[0x0][0x170], !PT ; /* 0x00005c0007097a17 */
/* 0x000fc80007800200 */
/*00a0*/ IADD3 R3, R9, c[0x0][0x170], RZ ; /* 0x00005c0009037a10 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x040fe40003f06070 */
/*00c0*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00e0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fc800078ec0ff */
/*00f0*/ ISETP.NE.AND P4, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f85270 */
/*0100*/ @!P0 BRA 0x360 ; /* 0x0000025000008947 */
/* 0x000ff40003800000 */
/*0110*/ IADD3 R4, R0.reuse, -c[0x0][0x170], RZ ; /* 0x80005c0000047a10 */
/* 0x040fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R8, R0, 0x3, RZ ; /* 0x0000000300087810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R18, R2, -0x1, -R9 ; /* 0xffffffff02127810 */
/* 0x000fe20007ffe809 */
/*0160*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0170*/ IADD3 R8, R8, -c[0x0][0x170], RZ ; /* 0x80005c0008087a10 */
/* 0x000fc60007ffe0ff */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*01a0*/ IMAD.IADD R4, R0, 0x1, R7 ; /* 0x0000000100047824 */
/* 0x000fe200078e0207 */
/*01b0*/ IADD3 R5, R8.reuse, -0x2, RZ ; /* 0xfffffffe08057810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ IADD3 R9, R8, -0x1, RZ ; /* 0xffffffff08097810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x040fe40003f06270 */
/*01e0*/ ISETP.GE.AND P1, PT, R5.reuse, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x040fe40003f26270 */
/*01f0*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fe20000701670 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*0210*/ ISETP.LT.OR P1, PT, R5, 0x1, P1 ; /* 0x000000010500780c */
/* 0x000fe20000f21670 */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0230*/ ISETP.GE.AND P2, PT, R9, c[0x0][0x174], PT ; /* 0x00005d0009007a0c */
/* 0x000fc40003f46270 */
/*0240*/ ISETP.GE.AND P3, PT, R8.reuse, c[0x0][0x174], PT ; /* 0x00005d0008007a0c */
/* 0x040fe40003f66270 */
/*0250*/ ISETP.LT.OR P2, PT, R9, 0x1, P2 ; /* 0x000000010900780c */
/* 0x000fe40001741670 */
/*0260*/ ISETP.LT.OR P3, PT, R8, 0x1, P3 ; /* 0x000000010800780c */
/* 0x000fc60001f61670 */
/*0270*/ @!P0 LDG.E R10, [R4.64] ; /* 0x00000004040a8981 */
/* 0x000ea8000c1e1900 */
/*0280*/ @!P1 LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c9981 */
/* 0x000ee8000c1e1900 */
/*0290*/ @!P2 LDG.E R14, [R4.64+0x8] ; /* 0x00000804040ea981 */
/* 0x000f28000c1e1900 */
/*02a0*/ @!P3 LDG.E R16, [R4.64+0xc] ; /* 0x00000c040410b981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc60007ffe0ff */
/*02d0*/ IMAD.IADD R9, R18, 0x1, R7 ; /* 0x0000000112097824 */
/* 0x000fe400078e0207 */
/*02e0*/ @!P0 IMAD.IADD R3, R3, 0x1, R10 ; /* 0x0000000103038824 */
/* 0x004fc600078e020a */
/*02f0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0300*/ @!P1 IMAD.IADD R3, R3, 0x1, R12 ; /* 0x0000000103039824 */
/* 0x008fe200078e020c */
/*0310*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc60007f3e0ff */
/*0320*/ @!P2 IMAD.IADD R3, R3, 0x1, R14 ; /* 0x000000010303a824 */
/* 0x010fe400078e020e */
/*0330*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0605 */
/*0340*/ @!P3 IMAD.IADD R3, R3, 0x1, R16 ; /* 0x000000010303b824 */
/* 0x020fc800078e0210 */
/*0350*/ @P0 BRA 0x1a0 ; /* 0xfffffe4000000947 */
/* 0x000fea000383ffff */
/*0360*/ @!P4 BRA 0x470 ; /* 0x000001000000c947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fe400078e0207 */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0390*/ IMAD R6, R6, c[0x0][0x0], R7 ; /* 0x0000000006067a24 */
/* 0x000fc800078e0207 */
/*03a0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0205 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*03c0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fc80003f06270 */
/*03d0*/ ISETP.LT.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000701670 */
/*03e0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff048224 */
/* 0x000fcc00078e0007 */
/*03f0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x0000a2000c1e1900 */
/*0400*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R7, P2, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f5e0ff */
/*0420*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0430*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x001fe400010e0605 */
/*0450*/ @!P0 IMAD.IADD R3, R3, 0x1, R4 ; /* 0x0000000103038824 */
/* 0x004fd000078e0204 */
/*0460*/ @P1 BRA 0x3c0 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0470*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0480*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0490*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10stencil_1dPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R2 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e020b */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IADD3 R8, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002087a10 */
/* 0x040fe20007ffe0ff */
/*0090*/ BSSY B0, 0x1d0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD.SHL.U32 R9, R2.reuse, 0x4, RZ ; /* 0x0000000402097824 */
/* 0x040fe200078e00ff */
/*00c0*/ ISETP.LT.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f21070 */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00e0*/ STS [R8.X4], R7 ; /* 0x0000000708007388 */
/* 0x0041f40000004800 */
/*00f0*/ @P0 BRA P1, 0x160 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0100*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*0110*/ @P0 BRA 0x1c0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R5, [R4.64+0x200] ; /* 0x0002000404057981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0003e80000004800 */
/*0140*/ STS [R8.X4+0x200], R5 ; /* 0x0002000508007388 */
/* 0x0043e20000004800 */
/*0150*/ BRA 0x1c0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000067a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ LDG.E R5, [R4.64+0x200] ; /* 0x0002000404057981 */
/* 0x000ea8000c1e1900 */
/*0180*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x001fcc00078e020b */
/*0190*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0081e80000004800 */
/*01b0*/ STS [R8.X4+0x200], R5 ; /* 0x0002000508007388 */
/* 0x0041e40000004800 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -c[0x0][0x170] ; /* 0x80005c00ff077624 */
/* 0x001fe200078e02ff */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x002fc600078e00ff */
/*0200*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f04270 */
/*0210*/ @P0 BRA 0x7a0 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMNMX R4, R7, c[0x0][0x170], !PT ; /* 0x00005c0007047a17 */
/* 0x000fe20007800200 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*0240*/ IADD3 R11, R4, c[0x0][0x170], RZ ; /* 0x00005c00040b7a10 */
/* 0x000fc80007ffe0ff */
/*0250*/ ISETP.GE.U32.AND P0, PT, R11.reuse, 0x3, PT ; /* 0x000000030b00780c */
/* 0x040fe40003f06070 */
/*0260*/ IADD3 R4, R11, 0x1, RZ ; /* 0x000000010b047810 */
/* 0x000fc80007ffe0ff */
/*0270*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fce00078ec0ff */
/*0280*/ @!P0 BRA 0x700 ; /* 0x0000047000008947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.IADD R6, R11, 0x1, -R4 ; /* 0x000000010b067824 */
/* 0x000fe200078e0a04 */
/*02a0*/ IADD3 R8, R9, 0x8, RZ ; /* 0x0000000809087810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*02c0*/ ISETP.GT.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fda0003f04270 */
/*02d0*/ @!P0 BRA 0x650 ; /* 0x0000037000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0300*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fda0003f24270 */
/*0310*/ @!P1 BRA 0x500 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0330*/ LDS R14, [R8+-0x8] ; /* 0xfffff800080e7984 */
/* 0x000fe20000000800 */
/*0340*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe20007ffe0ff */
/*0360*/ LDS R13, [R8+-0x4] ; /* 0xfffffc00080d7984 */
/* 0x000e220000000800 */
/*0370*/ ISETP.GT.AND P1, PT, R6, 0xb, PT ; /* 0x0000000b0600780c */
/* 0x000fc60003f24270 */
/*0380*/ LDS R16, [R8] ; /* 0x0000000008107984 */
/* 0x000fe80000000800 */
/*0390*/ LDS R15, [R8+0x4] ; /* 0x00000400080f7984 */
/* 0x000e680000000800 */
/*03a0*/ LDS R18, [R8+0x8] ; /* 0x0000080008127984 */
/* 0x000fe80000000800 */
/*03b0*/ LDS R17, [R8+0xc] ; /* 0x00000c0008117984 */
/* 0x000ea80000000800 */
/*03c0*/ LDS R20, [R8+0x10] ; /* 0x0000100008147984 */
/* 0x000fe80000000800 */
/*03d0*/ LDS R19, [R8+0x14] ; /* 0x0000140008137984 */
/* 0x000ee80000000800 */
/*03e0*/ LDS R22, [R8+0x18] ; /* 0x0000180008167984 */
/* 0x000fe80000000800 */
/*03f0*/ LDS R21, [R8+0x1c] ; /* 0x00001c0008157984 */
/* 0x000f280000000800 */
/*0400*/ LDS R24, [R8+0x20] ; /* 0x0000200008187984 */
/* 0x000fe80000000800 */
/*0410*/ LDS R23, [R8+0x24] ; /* 0x0000240008177984 */
/* 0x000f620000000800 */
/*0420*/ IADD3 R13, R13, R14, R5 ; /* 0x0000000e0d0d7210 */
/* 0x001fc60007ffe005 */
/*0430*/ LDS R12, [R8+0x28] ; /* 0x00002800080c7984 */
/* 0x000fe80000000800 */
/*0440*/ LDS R11, [R8+0x2c] ; /* 0x00002c00080b7984 */
/* 0x000e220000000800 */
/*0450*/ IADD3 R13, R15, R16, R13 ; /* 0x000000100f0d7210 */
/* 0x002fc60007ffe00d */
/*0460*/ LDS R10, [R8+0x30] ; /* 0x00003000080a7984 */
/* 0x000fe80000000800 */
/*0470*/ LDS R9, [R8+0x34] ; /* 0x0000340008097984 */
/* 0x0002220000000800 */
/*0480*/ IADD3 R13, R17, R18, R13 ; /* 0x00000012110d7210 */
/* 0x004fc80007ffe00d */
/*0490*/ IADD3 R13, R19, R20, R13 ; /* 0x00000014130d7210 */
/* 0x008fe40007ffe00d */
/*04a0*/ IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x002fe40007ffe0ff */
/*04b0*/ IADD3 R13, R21, R22, R13 ; /* 0x00000016150d7210 */
/* 0x010fc80007ffe00d */
/*04c0*/ IADD3 R13, R23, R24, R13 ; /* 0x00000018170d7210 */
/* 0x020fc80007ffe00d */
/*04d0*/ IADD3 R11, R11, R12, R13 ; /* 0x0000000c0b0b7210 */
/* 0x001fc80007ffe00d */
/*04e0*/ IADD3 R5, R9, R10, R11 ; /* 0x0000000a09057210 */
/* 0x000fe20007ffe00b */
/*04f0*/ @P1 BRA 0x330 ; /* 0xfffffe3000001947 */
/* 0x000fea000383ffff */
/*0500*/ IADD3 R9, R6, 0x1, RZ ; /* 0x0000000106097810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0520*/ @!P1 BRA 0x630 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0530*/ LDS R10, [R8+-0x8] ; /* 0xfffff800080a7984 */
/* 0x000fe20000000800 */
/*0540*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0550*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0560*/ LDS R9, [R8+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000e220000000800 */
/*0570*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*0580*/ LDS R12, [R8] ; /* 0x00000000080c7984 */
/* 0x000fe80000000800 */
/*0590*/ LDS R11, [R8+0x4] ; /* 0x00000400080b7984 */
/* 0x000e680000000800 */
/*05a0*/ LDS R14, [R8+0x8] ; /* 0x00000800080e7984 */
/* 0x000fe80000000800 */
/*05b0*/ LDS R13, [R8+0xc] ; /* 0x00000c00080d7984 */
/* 0x000ea80000000800 */
/*05c0*/ LDS R16, [R8+0x10] ; /* 0x0000100008107984 */
/* 0x000fe80000000800 */
/*05d0*/ LDS R15, [R8+0x14] ; /* 0x00001400080f7984 */
/* 0x0007240000000800 */
/*05e0*/ IADD3 R8, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x008fc40007ffe0ff */
/*05f0*/ IADD3 R9, R9, R10, R5 ; /* 0x0000000a09097210 */
/* 0x001fc80007ffe005 */
/*0600*/ IADD3 R9, R11, R12, R9 ; /* 0x0000000c0b097210 */
/* 0x002fc80007ffe009 */
/*0610*/ IADD3 R9, R13, R14, R9 ; /* 0x0000000e0d097210 */
/* 0x004fc80007ffe009 */
/*0620*/ IADD3 R5, R15, R16, R9 ; /* 0x000000100f057210 */
/* 0x010fe40007ffe009 */
/*0630*/ ISETP.NE.OR P0, PT, R6, -0x1, P0 ; /* 0xffffffff0600780c */
/* 0x000fda0000705670 */
/*0640*/ @!P0 BRA 0x700 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0650*/ LDS R10, [R8+-0x8] ; /* 0xfffff800080a7984 */
/* 0x000fe20000000800 */
/*0660*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe40007ffe0ff */
/*0670*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0680*/ LDS R9, [R8+-0x4] ; /* 0xfffffc0008097984 */
/* 0x000e220000000800 */
/*0690*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fc60003f05270 */
/*06a0*/ LDS R12, [R8] ; /* 0x00000000080c7984 */
/* 0x000fe80000000800 */
/*06b0*/ LDS R11, [R8+0x4] ; /* 0x00000400080b7984 */
/* 0x0002a40000000800 */
/*06c0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x002fe40007ffe0ff */
/*06d0*/ IADD3 R5, R9, R10, R5 ; /* 0x0000000a09057210 */
/* 0x001fc80007ffe005 */
/*06e0*/ IADD3 R5, R11, R12, R5 ; /* 0x0000000c0b057210 */
/* 0x004fe20007ffe005 */
/*06f0*/ @P0 BRA 0x650 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0700*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0710*/ @!P0 BRA 0x7a0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R2, R2, c[0x0][0x170], R7 ; /* 0x00005c0002027a10 */
/* 0x000fca0007ffe007 */
/*0730*/ IMAD.SHL.U32 R2, R2, 0x4, RZ ; /* 0x0000000402027824 */
/* 0x000fca00078e00ff */
/*0740*/ LDS R6, [R2] ; /* 0x0000000002067984 */
/* 0x0000620000000800 */
/*0750*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0770*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe20007ffe0ff */
/*0780*/ IMAD.IADD R5, R6, 0x1, R5 ; /* 0x0000000106057824 */
/* 0x002fd400078e0205 */
/*0790*/ @P0 BRA 0x740 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*07a0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*07b0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*07c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_1dPiS_i
.globl _Z10stencil_1dPiS_i
.p2align 8
.type _Z10stencil_1dPiS_i,@function
_Z10stencil_1dPiS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_add_nc_u32_e32 v5, s3, v0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_le_u32_e64 s2, s3, v0
s_cmp_eq_u32 s15, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 2, v5
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s3, v0
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v6
s_and_saveexec_b32 s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s8
s_cmp_eq_u32 s15, 0
s_mov_b32 s7, 0
s_cselect_b32 s6, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s6, vcc_lo
s_and_b32 s6, s6, exec_lo
s_or_saveexec_b32 s2, s2
v_mov_b32_e32 v6, s7
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v6, s3, v1
s_or_b32 s6, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_6
global_load_b32 v3, v[3:4], off offset:512
v_lshlrev_b32_e32 v4, 2, v0
v_lshlrev_b32_e32 v5, 2, v5
s_waitcnt vmcnt(1)
ds_store_b32 v4, v6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3 offset:512
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v3, 0
s_cmp_lt_i32 s3, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_lshl_b32 s2, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, 1
.LBB0_8:
ds_load_b32 v4, v0
v_add_nc_u32_e32 v0, 4, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
s_cbranch_scc0 .LBB0_8
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_1dPiS_i
.amdhsa_group_segment_fixed_size 544
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_1dPiS_i, .Lfunc_end0-_Z10stencil_1dPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13stencil_noMemPiS_ii
.globl _Z13stencil_noMemPiS_ii
.p2align 8
.type _Z13stencil_noMemPiS_ii,@function
_Z13stencil_noMemPiS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 0
s_mul_i32 s15, s15, s3
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x14
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v1
v_mov_b32_e32 v3, v2
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s2, 1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, 1, v1
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s7, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB1_2
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
s_branch .LBB1_2
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v0, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13stencil_noMemPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13stencil_noMemPiS_ii, .Lfunc_end1-_Z13stencil_noMemPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 544
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_1dPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_1dPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13stencil_noMemPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13stencil_noMemPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009269e_00000000-6_1Dstencil.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3906:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3906:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10cpuStencilPiS_ii
.type _Z10cpuStencilPiS_ii, @function
_Z10cpuStencilPiS_ii:
.LFB3899:
.cfi_startproc
endbr64
movl %edx, %r9d
movl %ecx, %r10d
testl %ecx, %ecx
jle .L3
movl %edx, %r11d
negl %r11d
leal (%r9,%r9), %r8d
movslq %r11d, %rdx
addq %r8, %rdx
leaq 4(%rdi,%rdx,4), %rcx
movl $0, %edi
notq %r8
salq $2, %r8
.L7:
cmpl %r11d, %r9d
jl .L5
leaq (%r8,%rcx), %rax
.L6:
movl (%rax), %edx
addl %edx, (%rsi)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L5:
addl $1, %edi
addq $4, %rsi
addq $4, %rcx
cmpl %edi, %r10d
jne .L7
.L3:
ret
.cfi_endproc
.LFE3899:
.size _Z10cpuStencilPiS_ii, .-_Z10cpuStencilPiS_ii
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3900:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3900:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.type _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, @function
_Z33__device_stub__Z10stencil_1dPiS_iPiS_i:
.LFB3928:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10stencil_1dPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3928:
.size _Z33__device_stub__Z10stencil_1dPiS_iPiS_i, .-_Z33__device_stub__Z10stencil_1dPiS_iPiS_i
.globl _Z10stencil_1dPiS_i
.type _Z10stencil_1dPiS_i, @function
_Z10stencil_1dPiS_i:
.LFB3929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10stencil_1dPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3929:
.size _Z10stencil_1dPiS_i, .-_Z10stencil_1dPiS_i
.globl _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
.type _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii, @function
_Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii:
.LFB3930:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13stencil_noMemPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3930:
.size _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii, .-_Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
.globl _Z13stencil_noMemPiS_ii
.type _Z13stencil_noMemPiS_ii, @function
_Z13stencil_noMemPiS_ii:
.LFB3931:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3931:
.size _Z13stencil_noMemPiS_ii, .-_Z13stencil_noMemPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gpu"
.LC2:
.string "N: "
.LC3:
.string " R: "
.LC4:
.string " GPU time: "
.LC5:
.string " ns"
.LC6:
.string " CPU time: "
.text
.globl main
.type main, @function
main:
.LFB3901:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
movq 16(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
leal 0(,%rbx,4), %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %esi
movq %rax, %rdi
call _Z11random_intsPii
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %esi
movq %rax, %rdi
call _Z11random_intsPii
movq 24(%r14), %rdi
leaq .LC0(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L35
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leal 127(%rbx), %eax
movl $128, %ecx
cltd
idivl %ecx
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movss .LC1(%rip), %xmm0
mulss 60(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L37:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl %ebx, %ecx
movl 8(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13stencil_noMemPiS_iiPiS_ii
jmp .L36
.L35:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl %ebx, %ecx
movl 8(%rsp), %r14d
movl %r14d, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z10cpuStencilPiS_ii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbp, %rax
movq %rax, %rbx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L37
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3901:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13stencil_noMemPiS_ii"
.LC8:
.string "_Z10stencil_1dPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3933:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13stencil_noMemPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_1dPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3933:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1Dstencil.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__stencil_1dPiS_i # -- Begin function _Z25__device_stub__stencil_1dPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__stencil_1dPiS_i,@function
_Z25__device_stub__stencil_1dPiS_i: # @_Z25__device_stub__stencil_1dPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10stencil_1dPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_1dPiS_i, .Lfunc_end0-_Z25__device_stub__stencil_1dPiS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__stencil_noMemPiS_ii # -- Begin function _Z28__device_stub__stencil_noMemPiS_ii
.p2align 4, 0x90
.type _Z28__device_stub__stencil_noMemPiS_ii,@function
_Z28__device_stub__stencil_noMemPiS_ii: # @_Z28__device_stub__stencil_noMemPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13stencil_noMemPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__stencil_noMemPiS_ii, .Lfunc_end1-_Z28__device_stub__stencil_noMemPiS_ii
.cfi_endproc
# -- End function
.globl _Z10cpuStencilPiS_ii # -- Begin function _Z10cpuStencilPiS_ii
.p2align 4, 0x90
.type _Z10cpuStencilPiS_ii,@function
_Z10cpuStencilPiS_ii: # @_Z10cpuStencilPiS_ii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
testl %ecx, %ecx
jle .LBB2_6
# %bb.1: # %.lr.ph16
movl %edx, %eax
negl %eax
movslq %eax, %r8
movl %ecx, %eax
leaq (%rdi,%r8,4), %rcx
leal (%rdx,%rdx), %edi
orq $1, %rdi
xorl %r8d, %r8d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r8
addq $4, %rcx
cmpq %rax, %r8
je .LBB2_6
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %edx, %edx
js .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl (%rsi,%r8,4), %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rcx,%r10,4), %r9d
movl %r9d, (%rsi,%r8,4)
incq %r10
cmpl %r10d, %edi
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z10cpuStencilPiS_ii, .Lfunc_end2-_Z10cpuStencilPiS_ii
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
retq
.Lfunc_end3:
.size _Z11random_intsPii, .Lfunc_end3-_Z11random_intsPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leal (,%r12,4), %eax
movslq %eax, %rdi
movq %rdi, 8(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
movl %r12d, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB4_2
.LBB4_3: # %_Z11random_intsPii.exit
movq 8(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r14
movq %r12, 32(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB4_6
# %bb.4: # %.lr.ph.preheader.i34
movl 32(%rsp), %r13d # 4-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB4_5
.LBB4_6: # %_Z11random_intsPii.exit40
movq 24(%rbp), %rdi
movl $.L.str, %esi
callq strcmp
testl %eax, %eax
je .LBB4_17
# %bb.7:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movq 32(%rsp), %r12 # 8-byte Reload
testl %r12d, %r12d
jle .LBB4_14
# %bb.8: # %.lr.ph16.i
movq %r15, %rdx
shlq $32, %rdx
negq %rdx
movq %rdx, %rsi
shrq $32, %rsi
movl %r12d, %eax
sarq $30, %rdx
movq %rbx, %rcx
addq %rdx, %rcx
movl %r15d, %edx
subl %esi, %edx
incl %edx
xorl %esi, %esi
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_9: # %._crit_edge.i
# in Loop: Header=BB4_10 Depth=1
incq %rsi
addq $4, %rcx
cmpq %rax, %rsi
je .LBB4_14
.LBB4_10: # =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
testl %r15d, %r15d
js .LBB4_9
# %bb.11: # %.lr.ph.i42
# in Loop: Header=BB4_10 Depth=1
movl (%r14,%rsi,4), %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_10 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rcx,%r8,4), %edi
incq %r8
cmpl %r8d, %edx
jne .LBB4_12
# %bb.13: # %._crit_edge.i.loopexit
# in Loop: Header=BB4_10 Depth=1
movl %edi, (%r14,%rsi,4)
jmp .LBB4_9
.LBB4_14: # %_Z10cpuStencilPiS_ii.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
subq %r13, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movq %rbp, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB4_24
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48
cmpb $0, 56(%r12)
je .LBB4_22
.LBB4_21:
movzbl 67(%r12), %eax
jmp .LBB4_23
.LBB4_17:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movq 8(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %r12 # 8-byte Reload
leal 127(%r12), %eax
leal 254(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $7, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_19
# %bb.18:
movq 48(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %r15d, 60(%rsp)
movl %r12d, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13stencil_noMemPiS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_19:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI4_0(%rip), %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB4_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
jne .LBB4_21
.LBB4_22:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_24:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_1dPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13stencil_noMemPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_1dPiS_i,@object # @_Z10stencil_1dPiS_i
.section .rodata,"a",@progbits
.globl _Z10stencil_1dPiS_i
.p2align 3, 0x0
_Z10stencil_1dPiS_i:
.quad _Z25__device_stub__stencil_1dPiS_i
.size _Z10stencil_1dPiS_i, 8
.type _Z13stencil_noMemPiS_ii,@object # @_Z13stencil_noMemPiS_ii
.globl _Z13stencil_noMemPiS_ii
.p2align 3, 0x0
_Z13stencil_noMemPiS_ii:
.quad _Z28__device_stub__stencil_noMemPiS_ii
.size _Z13stencil_noMemPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "gpu"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N: "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " R: "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " GPU time: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " ns"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " CPU time: "
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencil_1dPiS_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13stencil_noMemPiS_ii"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_1dPiS_i
.addrsig_sym _Z28__device_stub__stencil_noMemPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_1dPiS_i
.addrsig_sym _Z13stencil_noMemPiS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Using a dataset consisting of three arrays: A, B and C, the operation
Cx = Ax + Bx is performed on each element.
This code is executed on the GPU using CUDA. The result compute time is
displayed at the end of the computing.*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void device_add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
void fill_array(int *data, int size){
/* Fill an array with the index */
for(int i=0; i<size; i++)
data[i] = i;
}
void print_output(int *a, int *b, int *c, int size){
for(int i=0; i<size; i++)
printf("\n %d + %d = %d", a[i], b[i], c[i]);
}
int main(int argc, char *argv[]) {
int sizeOfArray = 512;
if(argc > 1)
sizeOfArray = atoi(argv[1]);
int *a, *b, *c; // Host copies of A, B and C
int *d_a, *d_b, *d_c; // Device copies of A, B and C
int memSize = sizeOfArray * sizeof(int);
struct timespec start, finish;
clock_gettime(CLOCK_REALTIME, &start);
/* Alloc space for host copies of a, b and c. Setup with input values */
a = (int*)malloc(memSize); fill_array(a, sizeOfArray);
b = (int*)malloc(memSize); fill_array(b, sizeOfArray);
c = (int*)malloc(memSize);
/* Alloc space on the GPU */
cudaMalloc((void**)&d_a, memSize);
cudaMalloc((void**)&d_b, memSize);
cudaMalloc((void**)&d_c, memSize);
/* Copy from host to device */
cudaMemcpy(d_a, a, sizeOfArray * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeOfArray * sizeof(int), cudaMemcpyHostToDevice);
/* Compute and copy results back to host */
device_add<<<sizeOfArray,1>>>(d_a,d_b,d_c);
cudaMemcpy(c, d_c, sizeOfArray * sizeof(int), cudaMemcpyDeviceToHost);
/* Get compute time */
clock_gettime(CLOCK_REALTIME, &finish);
long seconds = finish.tv_sec - start.tv_sec;
long ns = finish.tv_nsec - start.tv_nsec;
if (start.tv_nsec > finish.tv_nsec) {
--seconds;
ns += 1000000000;
}
/* Print output */
print_output(a, b, c, sizeOfArray);
printf("\n\nTime to compute: %e seconds \n\n",
(double)seconds + (double)ns/(double)1000000000);
free(a); free(b); free(c); // Free host memory
cudaFree(d_a), cudaFree(d_b), cudaFree(d_c); // Free GPU memory
return 0;
} | code for sm_80
Function : _Z10device_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Using a dataset consisting of three arrays: A, B and C, the operation
Cx = Ax + Bx is performed on each element.
This code is executed on the GPU using CUDA. The result compute time is
displayed at the end of the computing.*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void device_add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
void fill_array(int *data, int size){
/* Fill an array with the index */
for(int i=0; i<size; i++)
data[i] = i;
}
void print_output(int *a, int *b, int *c, int size){
for(int i=0; i<size; i++)
printf("\n %d + %d = %d", a[i], b[i], c[i]);
}
int main(int argc, char *argv[]) {
int sizeOfArray = 512;
if(argc > 1)
sizeOfArray = atoi(argv[1]);
int *a, *b, *c; // Host copies of A, B and C
int *d_a, *d_b, *d_c; // Device copies of A, B and C
int memSize = sizeOfArray * sizeof(int);
struct timespec start, finish;
clock_gettime(CLOCK_REALTIME, &start);
/* Alloc space for host copies of a, b and c. Setup with input values */
a = (int*)malloc(memSize); fill_array(a, sizeOfArray);
b = (int*)malloc(memSize); fill_array(b, sizeOfArray);
c = (int*)malloc(memSize);
/* Alloc space on the GPU */
cudaMalloc((void**)&d_a, memSize);
cudaMalloc((void**)&d_b, memSize);
cudaMalloc((void**)&d_c, memSize);
/* Copy from host to device */
cudaMemcpy(d_a, a, sizeOfArray * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeOfArray * sizeof(int), cudaMemcpyHostToDevice);
/* Compute and copy results back to host */
device_add<<<sizeOfArray,1>>>(d_a,d_b,d_c);
cudaMemcpy(c, d_c, sizeOfArray * sizeof(int), cudaMemcpyDeviceToHost);
/* Get compute time */
clock_gettime(CLOCK_REALTIME, &finish);
long seconds = finish.tv_sec - start.tv_sec;
long ns = finish.tv_nsec - start.tv_nsec;
if (start.tv_nsec > finish.tv_nsec) {
--seconds;
ns += 1000000000;
}
/* Print output */
print_output(a, b, c, sizeOfArray);
printf("\n\nTime to compute: %e seconds \n\n",
(double)seconds + (double)ns/(double)1000000000);
free(a); free(b); free(c); // Free host memory
cudaFree(d_a), cudaFree(d_b), cudaFree(d_c); // Free GPU memory
return 0;
} | .file "tmpxft_0002b29c_00000000-6_arr_add_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fill_arrayPii
.type _Z10fill_arrayPii, @function
_Z10fill_arrayPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10fill_arrayPii, .-_Z10fill_arrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n %d + %d = %d"
.text
.globl _Z12print_outputPiS_S_i
.type _Z12print_outputPiS_S_i, @function
_Z12print_outputPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L12
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rbp
movl $0, %ebx
leaq .LC0(%rip), %r15
.L9:
movl 0(%r13,%rbx), %ecx
movl (%r12,%rbx), %edx
movl (%r14,%rbx), %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z12print_outputPiS_S_i, .-_Z12print_outputPiS_S_i
.globl _Z34__device_stub__Z10device_addPiS_S_PiS_S_
.type _Z34__device_stub__Z10device_addPiS_S_PiS_S_, @function
_Z34__device_stub__Z10device_addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10device_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10device_addPiS_S_PiS_S_, .-_Z34__device_stub__Z10device_addPiS_S_PiS_S_
.globl _Z10device_addPiS_S_
.type _Z10device_addPiS_S_, @function
_Z10device_addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10device_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10device_addPiS_S_, .-_Z10device_addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n\nTime to compute: %e seconds \n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $512, %ebp
cmpl $1, %edi
jg .L30
.L24:
movslq %ebp, %r15
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebp, %esi
movq %rax, %rdi
call _Z10fill_arrayPii
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebp, %esi
movq %rax, %rdi
call _Z10fill_arrayPii
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
salq $2, %r15
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 64(%rsp), %rbx
subq 48(%rsp), %rbx
movq 72(%rsp), %rdx
movq 56(%rsp), %rax
movq %rdx, %r15
subq %rax, %r15
cmpq %rax, %rdx
jge .L26
subq $1, %rbx
addq $1000000000, %r15
.L26:
movl %ebp, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z12print_outputPiS_S_i
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
addsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L24
.L31:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10device_addPiS_S_PiS_S_
jmp .L25
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10device_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10device_addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Using a dataset consisting of three arrays: A, B and C, the operation
Cx = Ax + Bx is performed on each element.
This code is executed on the GPU using CUDA. The result compute time is
displayed at the end of the computing.*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void device_add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
void fill_array(int *data, int size){
/* Fill an array with the index */
for(int i=0; i<size; i++)
data[i] = i;
}
void print_output(int *a, int *b, int *c, int size){
for(int i=0; i<size; i++)
printf("\n %d + %d = %d", a[i], b[i], c[i]);
}
int main(int argc, char *argv[]) {
int sizeOfArray = 512;
if(argc > 1)
sizeOfArray = atoi(argv[1]);
int *a, *b, *c; // Host copies of A, B and C
int *d_a, *d_b, *d_c; // Device copies of A, B and C
int memSize = sizeOfArray * sizeof(int);
struct timespec start, finish;
clock_gettime(CLOCK_REALTIME, &start);
/* Alloc space for host copies of a, b and c. Setup with input values */
a = (int*)malloc(memSize); fill_array(a, sizeOfArray);
b = (int*)malloc(memSize); fill_array(b, sizeOfArray);
c = (int*)malloc(memSize);
/* Alloc space on the GPU */
cudaMalloc((void**)&d_a, memSize);
cudaMalloc((void**)&d_b, memSize);
cudaMalloc((void**)&d_c, memSize);
/* Copy from host to device */
cudaMemcpy(d_a, a, sizeOfArray * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, sizeOfArray * sizeof(int), cudaMemcpyHostToDevice);
/* Compute and copy results back to host */
device_add<<<sizeOfArray,1>>>(d_a,d_b,d_c);
cudaMemcpy(c, d_c, sizeOfArray * sizeof(int), cudaMemcpyDeviceToHost);
/* Get compute time */
clock_gettime(CLOCK_REALTIME, &finish);
long seconds = finish.tv_sec - start.tv_sec;
long ns = finish.tv_nsec - start.tv_nsec;
if (start.tv_nsec > finish.tv_nsec) {
--seconds;
ns += 1000000000;
}
/* Print output */
print_output(a, b, c, sizeOfArray);
printf("\n\nTime to compute: %e seconds \n\n",
(double)seconds + (double)ns/(double)1000000000);
free(a); free(b); free(c); // Free host memory
cudaFree(d_a), cudaFree(d_b), cudaFree(d_c); // Free GPU memory
return 0;
} | /* Using a dataset consisting of three arrays: A, B and C, the operation
Cx = Ax + Bx is performed on each element.
This code is executed on the GPU using CUDA. The result compute time is
displayed at the end of the computing.*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void device_add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
void fill_array(int *data, int size){
/* Fill an array with the index */
for(int i=0; i<size; i++)
data[i] = i;
}
void print_output(int *a, int *b, int *c, int size){
for(int i=0; i<size; i++)
printf("\n %d + %d = %d", a[i], b[i], c[i]);
}
int main(int argc, char *argv[]) {
int sizeOfArray = 512;
if(argc > 1)
sizeOfArray = atoi(argv[1]);
int *a, *b, *c; // Host copies of A, B and C
int *d_a, *d_b, *d_c; // Device copies of A, B and C
int memSize = sizeOfArray * sizeof(int);
struct timespec start, finish;
clock_gettime(CLOCK_REALTIME, &start);
/* Alloc space for host copies of a, b and c. Setup with input values */
a = (int*)malloc(memSize); fill_array(a, sizeOfArray);
b = (int*)malloc(memSize); fill_array(b, sizeOfArray);
c = (int*)malloc(memSize);
/* Alloc space on the GPU */
hipMalloc((void**)&d_a, memSize);
hipMalloc((void**)&d_b, memSize);
hipMalloc((void**)&d_c, memSize);
/* Copy from host to device */
hipMemcpy(d_a, a, sizeOfArray * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeOfArray * sizeof(int), hipMemcpyHostToDevice);
/* Compute and copy results back to host */
device_add<<<sizeOfArray,1>>>(d_a,d_b,d_c);
hipMemcpy(c, d_c, sizeOfArray * sizeof(int), hipMemcpyDeviceToHost);
/* Get compute time */
clock_gettime(CLOCK_REALTIME, &finish);
long seconds = finish.tv_sec - start.tv_sec;
long ns = finish.tv_nsec - start.tv_nsec;
if (start.tv_nsec > finish.tv_nsec) {
--seconds;
ns += 1000000000;
}
/* Print output */
print_output(a, b, c, sizeOfArray);
printf("\n\nTime to compute: %e seconds \n\n",
(double)seconds + (double)ns/(double)1000000000);
free(a); free(b); free(c); // Free host memory
hipFree(d_a), hipFree(d_b), hipFree(d_c); // Free GPU memory
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Using a dataset consisting of three arrays: A, B and C, the operation
Cx = Ax + Bx is performed on each element.
This code is executed on the GPU using CUDA. The result compute time is
displayed at the end of the computing.*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void device_add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
void fill_array(int *data, int size){
/* Fill an array with the index */
for(int i=0; i<size; i++)
data[i] = i;
}
void print_output(int *a, int *b, int *c, int size){
for(int i=0; i<size; i++)
printf("\n %d + %d = %d", a[i], b[i], c[i]);
}
int main(int argc, char *argv[]) {
int sizeOfArray = 512;
if(argc > 1)
sizeOfArray = atoi(argv[1]);
int *a, *b, *c; // Host copies of A, B and C
int *d_a, *d_b, *d_c; // Device copies of A, B and C
int memSize = sizeOfArray * sizeof(int);
struct timespec start, finish;
clock_gettime(CLOCK_REALTIME, &start);
/* Alloc space for host copies of a, b and c. Setup with input values */
a = (int*)malloc(memSize); fill_array(a, sizeOfArray);
b = (int*)malloc(memSize); fill_array(b, sizeOfArray);
c = (int*)malloc(memSize);
/* Alloc space on the GPU */
hipMalloc((void**)&d_a, memSize);
hipMalloc((void**)&d_b, memSize);
hipMalloc((void**)&d_c, memSize);
/* Copy from host to device */
hipMemcpy(d_a, a, sizeOfArray * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeOfArray * sizeof(int), hipMemcpyHostToDevice);
/* Compute and copy results back to host */
device_add<<<sizeOfArray,1>>>(d_a,d_b,d_c);
hipMemcpy(c, d_c, sizeOfArray * sizeof(int), hipMemcpyDeviceToHost);
/* Get compute time */
clock_gettime(CLOCK_REALTIME, &finish);
long seconds = finish.tv_sec - start.tv_sec;
long ns = finish.tv_nsec - start.tv_nsec;
if (start.tv_nsec > finish.tv_nsec) {
--seconds;
ns += 1000000000;
}
/* Print output */
print_output(a, b, c, sizeOfArray);
printf("\n\nTime to compute: %e seconds \n\n",
(double)seconds + (double)ns/(double)1000000000);
free(a); free(b); free(c); // Free host memory
hipFree(d_a), hipFree(d_b), hipFree(d_c); // Free GPU memory
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10device_addPiS_S_
.globl _Z10device_addPiS_S_
.p2align 8
.type _Z10device_addPiS_S_,@function
_Z10device_addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10device_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10device_addPiS_S_, .Lfunc_end0-_Z10device_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10device_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10device_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Using a dataset consisting of three arrays: A, B and C, the operation
Cx = Ax + Bx is performed on each element.
This code is executed on the GPU using CUDA. The result compute time is
displayed at the end of the computing.*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__ void device_add(int *a, int *b, int *c){
c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
}
void fill_array(int *data, int size){
/* Fill an array with the index */
for(int i=0; i<size; i++)
data[i] = i;
}
void print_output(int *a, int *b, int *c, int size){
for(int i=0; i<size; i++)
printf("\n %d + %d = %d", a[i], b[i], c[i]);
}
int main(int argc, char *argv[]) {
int sizeOfArray = 512;
if(argc > 1)
sizeOfArray = atoi(argv[1]);
int *a, *b, *c; // Host copies of A, B and C
int *d_a, *d_b, *d_c; // Device copies of A, B and C
int memSize = sizeOfArray * sizeof(int);
struct timespec start, finish;
clock_gettime(CLOCK_REALTIME, &start);
/* Alloc space for host copies of a, b and c. Setup with input values */
a = (int*)malloc(memSize); fill_array(a, sizeOfArray);
b = (int*)malloc(memSize); fill_array(b, sizeOfArray);
c = (int*)malloc(memSize);
/* Alloc space on the GPU */
hipMalloc((void**)&d_a, memSize);
hipMalloc((void**)&d_b, memSize);
hipMalloc((void**)&d_c, memSize);
/* Copy from host to device */
hipMemcpy(d_a, a, sizeOfArray * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, sizeOfArray * sizeof(int), hipMemcpyHostToDevice);
/* Compute and copy results back to host */
device_add<<<sizeOfArray,1>>>(d_a,d_b,d_c);
hipMemcpy(c, d_c, sizeOfArray * sizeof(int), hipMemcpyDeviceToHost);
/* Get compute time */
clock_gettime(CLOCK_REALTIME, &finish);
long seconds = finish.tv_sec - start.tv_sec;
long ns = finish.tv_nsec - start.tv_nsec;
if (start.tv_nsec > finish.tv_nsec) {
--seconds;
ns += 1000000000;
}
/* Print output */
print_output(a, b, c, sizeOfArray);
printf("\n\nTime to compute: %e seconds \n\n",
(double)seconds + (double)ns/(double)1000000000);
free(a); free(b); free(c); // Free host memory
hipFree(d_a), hipFree(d_b), hipFree(d_c); // Free GPU memory
return 0;
} | .text
.file "arr_add_gpu.hip"
.globl _Z25__device_stub__device_addPiS_S_ # -- Begin function _Z25__device_stub__device_addPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__device_addPiS_S_,@function
_Z25__device_stub__device_addPiS_S_: # @_Z25__device_stub__device_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10device_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__device_addPiS_S_, .Lfunc_end0-_Z25__device_stub__device_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z10fill_arrayPii # -- Begin function _Z10fill_arrayPii
.p2align 4, 0x90
.type _Z10fill_arrayPii,@function
_Z10fill_arrayPii: # @_Z10fill_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10fill_arrayPii, .Lfunc_end1-_Z10fill_arrayPii
.cfi_endproc
# -- End function
.globl _Z12print_outputPiS_S_i # -- Begin function _Z12print_outputPiS_S_i
.p2align 4, 0x90
.type _Z12print_outputPiS_S_i,@function
_Z12print_outputPiS_S_i: # @_Z12print_outputPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl (%r14,%r13,4), %edx
movl (%rbx,%r13,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r12
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z12print_outputPiS_S_i, .Lfunc_end2-_Z12print_outputPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %r14d # imm = 0x200
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.LBB3_2:
movslq %r14d, %r12
leaq 168(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq %r12, %rbp
shlq $34, %rbp
sarq $32, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %r14, 88(%rsp) # 8-byte Spill
movl %r14d, %r15d
testl %r12d, %r12d
jle .LBB3_5
# %bb.3: # %.lr.ph.preheader.i
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB3_4
.LBB3_5: # %_Z10fill_arrayPii.exit
leaq (,%r12,4), %r13
movq %rbp, %rdi
callq malloc
movq %rax, %r14
testl %r12d, %r12d
jle .LBB3_8
# %bb.6: # %.lr.ph.preheader.i34
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB3_7
.LBB3_8: # %_Z10fill_arrayPii.exit40
movq %rbp, %rdi
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%r15,%rdx), %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 152(%rsp), %rax
movq %rax, 40(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10device_addPiS_S_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %r13
movq 40(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 168(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 176(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
cmpl $0, 88(%rsp) # 4-byte Folded Reload
jle .LBB3_13
# %bb.11: # %.lr.ph.i43.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_12: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rbp,4), %esi
movl (%r14,%rbp,4), %edx
movl (%r12,%rbp,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r15
jne .LBB3_12
.LBB3_13: # %_Z12print_outputPiS_S_i.exit
xorl %eax, %eax
movq 72(%rsp), %rdx # 8-byte Reload
subq 64(%rsp), %rdx # 8-byte Folded Reload
setl %al
leaq 1000000000(%rdx), %rcx
cmovgeq %rdx, %rcx
subq 80(%rsp), %r13 # 8-byte Folded Reload
subq %rax, %r13
cvtsi2sd %r13, %xmm1
cvtsi2sd %rcx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10device_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10device_addPiS_S_,@object # @_Z10device_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z10device_addPiS_S_
.p2align 3, 0x0
_Z10device_addPiS_S_:
.quad _Z25__device_stub__device_addPiS_S_
.size _Z10device_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n %d + %d = %d"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\nTime to compute: %e seconds \n\n"
.size .L.str.1, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10device_addPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__device_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10device_addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10device_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10device_addPiS_S_
.globl _Z10device_addPiS_S_
.p2align 8
.type _Z10device_addPiS_S_,@function
_Z10device_addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10device_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10device_addPiS_S_, .Lfunc_end0-_Z10device_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10device_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10device_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b29c_00000000-6_arr_add_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fill_arrayPii
.type _Z10fill_arrayPii, @function
_Z10fill_arrayPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10fill_arrayPii, .-_Z10fill_arrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n %d + %d = %d"
.text
.globl _Z12print_outputPiS_S_i
.type _Z12print_outputPiS_S_i, @function
_Z12print_outputPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L12
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rbp
movl $0, %ebx
leaq .LC0(%rip), %r15
.L9:
movl 0(%r13,%rbx), %ecx
movl (%r12,%rbx), %edx
movl (%r14,%rbx), %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z12print_outputPiS_S_i, .-_Z12print_outputPiS_S_i
.globl _Z34__device_stub__Z10device_addPiS_S_PiS_S_
.type _Z34__device_stub__Z10device_addPiS_S_PiS_S_, @function
_Z34__device_stub__Z10device_addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10device_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10device_addPiS_S_PiS_S_, .-_Z34__device_stub__Z10device_addPiS_S_PiS_S_
.globl _Z10device_addPiS_S_
.type _Z10device_addPiS_S_, @function
_Z10device_addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10device_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10device_addPiS_S_, .-_Z10device_addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n\nTime to compute: %e seconds \n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $512, %ebp
cmpl $1, %edi
jg .L30
.L24:
movslq %ebp, %r15
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebp, %esi
movq %rax, %rdi
call _Z10fill_arrayPii
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebp, %esi
movq %rax, %rdi
call _Z10fill_arrayPii
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
salq $2, %r15
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 64(%rsp), %rbx
subq 48(%rsp), %rbx
movq 72(%rsp), %rdx
movq 56(%rsp), %rax
movq %rdx, %r15
subq %rax, %r15
cmpq %rax, %rdx
jge .L26
subq $1, %rbx
addq $1000000000, %r15
.L26:
movl %ebp, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z12print_outputPiS_S_i
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
addsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L24
.L31:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10device_addPiS_S_PiS_S_
jmp .L25
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10device_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10device_addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "arr_add_gpu.hip"
.globl _Z25__device_stub__device_addPiS_S_ # -- Begin function _Z25__device_stub__device_addPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__device_addPiS_S_,@function
_Z25__device_stub__device_addPiS_S_: # @_Z25__device_stub__device_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10device_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__device_addPiS_S_, .Lfunc_end0-_Z25__device_stub__device_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z10fill_arrayPii # -- Begin function _Z10fill_arrayPii
.p2align 4, 0x90
.type _Z10fill_arrayPii,@function
_Z10fill_arrayPii: # @_Z10fill_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10fill_arrayPii, .Lfunc_end1-_Z10fill_arrayPii
.cfi_endproc
# -- End function
.globl _Z12print_outputPiS_S_i # -- Begin function _Z12print_outputPiS_S_i
.p2align 4, 0x90
.type _Z12print_outputPiS_S_i,@function
_Z12print_outputPiS_S_i: # @_Z12print_outputPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl (%r14,%r13,4), %edx
movl (%rbx,%r13,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r12
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z12print_outputPiS_S_i, .Lfunc_end2-_Z12print_outputPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %r14d # imm = 0x200
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.LBB3_2:
movslq %r14d, %r12
leaq 168(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq %r12, %rbp
shlq $34, %rbp
sarq $32, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %r14, 88(%rsp) # 8-byte Spill
movl %r14d, %r15d
testl %r12d, %r12d
jle .LBB3_5
# %bb.3: # %.lr.ph.preheader.i
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB3_4
.LBB3_5: # %_Z10fill_arrayPii.exit
leaq (,%r12,4), %r13
movq %rbp, %rdi
callq malloc
movq %rax, %r14
testl %r12d, %r12d
jle .LBB3_8
# %bb.6: # %.lr.ph.preheader.i34
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq %rax, %r15
jne .LBB3_7
.LBB3_8: # %_Z10fill_arrayPii.exit40
movq %rbp, %rdi
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%r15,%rdx), %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 152(%rsp), %rax
movq %rax, 40(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10device_addPiS_S_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %r13
movq 40(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 168(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 176(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
cmpl $0, 88(%rsp) # 4-byte Folded Reload
jle .LBB3_13
# %bb.11: # %.lr.ph.i43.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_12: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rbp,4), %esi
movl (%r14,%rbp,4), %edx
movl (%r12,%rbp,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r15
jne .LBB3_12
.LBB3_13: # %_Z12print_outputPiS_S_i.exit
xorl %eax, %eax
movq 72(%rsp), %rdx # 8-byte Reload
subq 64(%rsp), %rdx # 8-byte Folded Reload
setl %al
leaq 1000000000(%rdx), %rcx
cmovgeq %rdx, %rcx
subq 80(%rsp), %r13 # 8-byte Folded Reload
subq %rax, %r13
cvtsi2sd %r13, %xmm1
cvtsi2sd %rcx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10device_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10device_addPiS_S_,@object # @_Z10device_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z10device_addPiS_S_
.p2align 3, 0x0
_Z10device_addPiS_S_:
.quad _Z25__device_stub__device_addPiS_S_
.size _Z10device_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n %d + %d = %d"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\nTime to compute: %e seconds \n\n"
.size .L.str.1, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10device_addPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__device_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10device_addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdexcept>
#include <algorithm>
constexpr int CUDA_NUM_THREADS = 128;
constexpr int MAXIMUM_NUM_BLOCKS = 4096;
inline int GET_BLOCKS(const int N) {
return std::max(std::min((N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS,
MAXIMUM_NUM_BLOCKS), 1);
}
// define the kernel function:
template <typename T>
__global__ void sum(T *a, T *b, T *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i <= N) {
c[i] = a[i] + b[i];
}
}
// define the kernel calling code:
template <typename T>
void AddGPUKernel(T *in_a, T *in_b, T *out_c, int N, cudaStream_t stream) {
sum<T>
<<<GET_BLOCKS(N), CUDA_NUM_THREADS, 0, stream>>>(in_a, in_b, out_c, N);
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
throw std::runtime_error("CUDA kernel failed : " + std::to_string(err));
}
// instantiate the kernel template for T=float:
template void AddGPUKernel<float>(float *in_a, float *in_b, float *out_c, int N, cudaStream_t stream); | code for sm_80
Function : _Z3sumIfEvPT_S1_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdexcept>
#include <algorithm>
constexpr int CUDA_NUM_THREADS = 128;
constexpr int MAXIMUM_NUM_BLOCKS = 4096;
inline int GET_BLOCKS(const int N) {
return std::max(std::min((N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS,
MAXIMUM_NUM_BLOCKS), 1);
}
// define the kernel function:
template <typename T>
__global__ void sum(T *a, T *b, T *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i <= N) {
c[i] = a[i] + b[i];
}
}
// define the kernel calling code:
template <typename T>
void AddGPUKernel(T *in_a, T *in_b, T *out_c, int N, cudaStream_t stream) {
sum<T>
<<<GET_BLOCKS(N), CUDA_NUM_THREADS, 0, stream>>>(in_a, in_b, out_c, N);
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
throw std::runtime_error("CUDA kernel failed : " + std::to_string(err));
}
// instantiate the kernel template for T=float:
template void AddGPUKernel<float>(float *in_a, float *in_b, float *out_c, int N, cudaStream_t stream); | .file "tmpxft_00139c92_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i, @function
_ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i:
.LFB3388:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumIfEvPT_S1_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3388:
.size _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i, .-_ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i
.section .text._Z3sumIfEvPT_S1_S1_i,"axG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.weak _Z3sumIfEvPT_S1_S1_i
.type _Z3sumIfEvPT_S1_S1_i, @function
_Z3sumIfEvPT_S1_S1_i:
.LFB3689:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3689:
.size _Z3sumIfEvPT_S1_S1_i, .-_Z3sumIfEvPT_S1_S1_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3366:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA kernel failed : "
.section .rodata._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.section .text._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,"axG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,comdat
.weak _Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st
.type _Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st, @function
_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st:
.LFB3688:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3688
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $328, %rsp
.cfi_def_cfa_offset 368
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movq %r8, %r9
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $4096, %eax
cmpl $524288, %ecx
jg .L12
leal 254(%rcx), %eax
movl %ecx, %edx
addl $127, %edx
cmovns %edx, %eax
sarl $7, %eax
.L12:
testl %eax, %eax
movl $1, %edx
cmovle %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
.LEHB0:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L13:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i
.LEHE0:
jmp .L13
.L37:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %r12
movl %ebx, %r13d
shrl $31, %r13d
movl %ebx, %eax
negl %eax
cmovns %eax, %ebx
movl %ebx, %eax
movl $1, %ebp
movl $10000, %ecx
.L20:
cmpl $9, %eax
jbe .L16
cmpl $99, %eax
ja .L17
addl $1, %ebp
.L16:
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
leal 0(%r13,%rbp), %esi
movl $45, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r13b, %r8d
addq 32(%rsp), %r8
leaq 96(%rsp), %rdi
leaq .LC0(%rip), %rsi
movl $201, %ecx
rep movsb
subl $1, %ebp
movl $100, %ecx
.L21:
cmpl $99, %ebx
ja .L22
cmpl $9, %ebx
jbe .L23
addl %ebx, %ebx
leal 1(%rbx), %eax
movzbl 96(%rsp,%rax), %eax
movb %al, 1(%r8)
movl %ebx, %ebx
movzbl 96(%rsp,%rbx), %ebx
.L24:
movb %bl, (%r8)
leaq 32(%rsp), %rdi
movl $21, %r8d
leaq .LC1(%rip), %rcx
movl $0, %edx
movl $0, %esi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
.LEHE1:
jmp .L39
.L17:
cmpl $999, %eax
ja .L18
addl $2, %ebp
jmp .L16
.L18:
cmpl $9999, %eax
ja .L19
addl $3, %ebp
jmp .L16
.L19:
movl %eax, %eax
movl $0, %edx
divq %rcx
addl $4, %ebp
jmp .L20
.L22:
movl %ebx, %eax
movl $0, %edx
divl %ecx
movl %eax, %ebx
addl %edx, %edx
movl %ebp, %esi
leal 1(%rdx), %eax
movl %eax, %eax
movzbl 96(%rsp,%rax), %eax
movb %al, (%r8,%rsi)
leal -1(%rbp), %eax
movl %edx, %edx
movzbl 96(%rsp,%rdx), %edx
movb %dl, (%r8,%rax)
subl $2, %ebp
jmp .L21
.L23:
addl $48, %ebx
jmp .L24
.L39:
leaq 80(%rsp), %rdx
movq %rdx, 64(%rsp)
movq (%rax), %rcx
leaq 16(%rax), %rdx
cmpq %rdx, %rcx
jne .L25
leaq 80(%rsp), %r8
movq 8(%rax), %rcx
leal 1(%rcx), %ecx
movq %r8, %rdi
movq %rdx, %rsi
rep movsb
.L26:
movq 8(%rax), %rcx
movq %rcx, 72(%rsp)
movq %rdx, (%rax)
movq $0, 8(%rax)
movb $0, 16(%rax)
leaq 64(%rsp), %rsi
movq %r12, %rdi
.LEHB2:
call _ZNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE2:
jmp .L40
.L25:
movq %rcx, 64(%rsp)
movq 16(%rax), %rcx
movq %rcx, 80(%rsp)
jmp .L26
.L40:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
je .L27
call __stack_chk_fail@PLT
.L27:
movq _ZNSt13runtime_errorD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt13runtime_error(%rip), %rsi
movq %r12, %rdi
.LEHB3:
call __cxa_throw@PLT
.L34:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L29:
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %r12, %rdi
call __cxa_free_exception@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L33:
endbr64
movq %rax, %rbx
jmp .L29
.L30:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3688:
.globl __gxx_personality_v0
.section .gcc_except_table._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,"aG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,comdat
.LLSDA3688:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3688-.LLSDACSB3688
.LLSDACSB3688:
.uleb128 .LEHB0-.LFB3688
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3688
.uleb128 .LEHE1-.LEHB1
.uleb128 .L33-.LFB3688
.uleb128 0
.uleb128 .LEHB2-.LFB3688
.uleb128 .LEHE2-.LEHB2
.uleb128 .L34-.LFB3688
.uleb128 0
.uleb128 .LEHB3-.LFB3688
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3688:
.section .text._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,"axG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,comdat
.size _Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st, .-_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3sumIfEvPT_S1_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3391:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumIfEvPT_S1_S1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3391:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdexcept>
#include <algorithm>
constexpr int CUDA_NUM_THREADS = 128;
constexpr int MAXIMUM_NUM_BLOCKS = 4096;
inline int GET_BLOCKS(const int N) {
return std::max(std::min((N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS,
MAXIMUM_NUM_BLOCKS), 1);
}
// define the kernel function:
template <typename T>
__global__ void sum(T *a, T *b, T *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i <= N) {
c[i] = a[i] + b[i];
}
}
// define the kernel calling code:
template <typename T>
void AddGPUKernel(T *in_a, T *in_b, T *out_c, int N, cudaStream_t stream) {
sum<T>
<<<GET_BLOCKS(N), CUDA_NUM_THREADS, 0, stream>>>(in_a, in_b, out_c, N);
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
throw std::runtime_error("CUDA kernel failed : " + std::to_string(err));
}
// instantiate the kernel template for T=float:
template void AddGPUKernel<float>(float *in_a, float *in_b, float *out_c, int N, cudaStream_t stream); | #include <hip/hip_runtime.h>
#include <stdexcept>
#include <algorithm>
constexpr int CUDA_NUM_THREADS = 128;
constexpr int MAXIMUM_NUM_BLOCKS = 4096;
inline int GET_BLOCKS(const int N) {
return std::max(std::min((N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS,
MAXIMUM_NUM_BLOCKS), 1);
}
// define the kernel function:
template <typename T>
__global__ void sum(T *a, T *b, T *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i <= N) {
c[i] = a[i] + b[i];
}
}
// define the kernel calling code:
template <typename T>
void AddGPUKernel(T *in_a, T *in_b, T *out_c, int N, hipStream_t stream) {
sum<T>
<<<GET_BLOCKS(N), CUDA_NUM_THREADS, 0, stream>>>(in_a, in_b, out_c, N);
hipError_t err = hipGetLastError();
if (hipSuccess != err)
throw std::runtime_error("CUDA kernel failed : " + std::to_string(err));
}
// instantiate the kernel template for T=float:
template void AddGPUKernel<float>(float *in_a, float *in_b, float *out_c, int N, hipStream_t stream); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdexcept>
#include <algorithm>
constexpr int CUDA_NUM_THREADS = 128;
constexpr int MAXIMUM_NUM_BLOCKS = 4096;
inline int GET_BLOCKS(const int N) {
return std::max(std::min((N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS,
MAXIMUM_NUM_BLOCKS), 1);
}
// define the kernel function:
template <typename T>
__global__ void sum(T *a, T *b, T *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i <= N) {
c[i] = a[i] + b[i];
}
}
// define the kernel calling code:
template <typename T>
void AddGPUKernel(T *in_a, T *in_b, T *out_c, int N, hipStream_t stream) {
sum<T>
<<<GET_BLOCKS(N), CUDA_NUM_THREADS, 0, stream>>>(in_a, in_b, out_c, N);
hipError_t err = hipGetLastError();
if (hipSuccess != err)
throw std::runtime_error("CUDA kernel failed : " + std::to_string(err));
}
// instantiate the kernel template for T=float:
template void AddGPUKernel<float>(float *in_a, float *in_b, float *out_c, int N, hipStream_t stream); | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z3sumIfEvPT_S1_S1_i,"axG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.protected _Z3sumIfEvPT_S1_S1_i
.globl _Z3sumIfEvPT_S1_S1_i
.p2align 8
.type _Z3sumIfEvPT_S1_S1_i,@function
_Z3sumIfEvPT_S1_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumIfEvPT_S1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z3sumIfEvPT_S1_S1_i,"axG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.Lfunc_end0:
.size _Z3sumIfEvPT_S1_S1_i, .Lfunc_end0-_Z3sumIfEvPT_S1_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumIfEvPT_S1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumIfEvPT_S1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdexcept>
#include <algorithm>
constexpr int CUDA_NUM_THREADS = 128;
constexpr int MAXIMUM_NUM_BLOCKS = 4096;
inline int GET_BLOCKS(const int N) {
return std::max(std::min((N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS,
MAXIMUM_NUM_BLOCKS), 1);
}
// define the kernel function:
template <typename T>
__global__ void sum(T *a, T *b, T *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i <= N) {
c[i] = a[i] + b[i];
}
}
// define the kernel calling code:
template <typename T>
void AddGPUKernel(T *in_a, T *in_b, T *out_c, int N, hipStream_t stream) {
sum<T>
<<<GET_BLOCKS(N), CUDA_NUM_THREADS, 0, stream>>>(in_a, in_b, out_c, N);
hipError_t err = hipGetLastError();
if (hipSuccess != err)
throw std::runtime_error("CUDA kernel failed : " + std::to_string(err));
}
// instantiate the kernel template for T=float:
template void AddGPUKernel<float>(float *in_a, float *in_b, float *out_c, int N, hipStream_t stream); | .text
.file "add.hip"
.section .text._Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,"axG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,comdat
.weak _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t # -- Begin function _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t
.p2align 4, 0x90
.type _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,@function
_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t: # @_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r9
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
leal 127(%rbx), %eax
leal 254(%rbx), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $7, %ecx
cmpl $4096, %ecx # imm = 0x1000
movl $4096, %edx # imm = 0x1000
cmovll %ecx, %edx
cmpl $2, %edx
movl $1, %eax
cmovgel %edx, %eax
movq %rdi, %r12
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rax
orq $128, %rdx
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r12, 104(%rsp)
movq %r15, 96(%rsp)
movq %r14, 88(%rsp)
movl %ebx, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 12(%rsp), %rax
movq %rax, 40(%rsp)
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z3sumIfEvPT_S1_S1_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
testl %eax, %eax
jne .LBB0_3
# %bb.14:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
.cfi_escape 0x2e, 0x00
movl $16, %edi
movl %eax, %ebp
callq __cxa_allocate_exception
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %r14
movq %r14, %rdi
movl %ebp, %esi
callq _ZNSt7__cxx119to_stringEi
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $.L.str, %esi
movq %r14, %rdx
callq _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.Ltmp1:
# %bb.4:
movb $1, %bpl
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp4:
# %bb.5:
xorl %ebp, %ebp
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $_ZTISt13runtime_error, %esi
movl $_ZNSt13runtime_errorD1Ev, %edx
movq %rbx, %rdi
callq __cxa_throw
.Ltmp6:
# %bb.15:
.LBB0_7:
.Ltmp7:
movq %rax, %r14
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB0_9
.LBB0_6:
.Ltmp2:
movq %rax, %r14
movb $1, %bpl
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
jne .LBB0_10
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit19
testb %bpl, %bpl
jne .LBB0_12
.LBB0_13:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB0_10: # %.critedge.i.i17
.cfi_escape 0x2e, 0x00
callq _ZdlPv
testb %bpl, %bpl
je .LBB0_13
.LBB0_12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq __cxa_free_exception
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t, .Lfunc_end0-_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t
.cfi_endproc
.section .gcc_except_table._Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,"aG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,comdat
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._Z18__device_stub__sumIfEvPT_S1_S1_i,"axG",@progbits,_Z18__device_stub__sumIfEvPT_S1_S1_i,comdat
.weak _Z18__device_stub__sumIfEvPT_S1_S1_i # -- Begin function _Z18__device_stub__sumIfEvPT_S1_S1_i
.p2align 4, 0x90
.type _Z18__device_stub__sumIfEvPT_S1_S1_i,@function
_Z18__device_stub__sumIfEvPT_S1_S1_i: # @_Z18__device_stub__sumIfEvPT_S1_S1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumIfEvPT_S1_S1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__sumIfEvPT_S1_S1_i, .Lfunc_end1-_Z18__device_stub__sumIfEvPT_S1_S1_i
.cfi_endproc
# -- End function
.section .text._ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_,"axG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_,comdat
.weak _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_ # -- Begin function _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.p2align 4, 0x90
.type _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_,@function
_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_: # @_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rsi, %rdi
callq strlen
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
movq %r15, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
movq %rax, %r14
leaq 16(%rbx), %rdi
movq %rdi, (%rbx)
movq (%rax), %rax
movq %r14, %r15
addq $16, %r15
cmpq %r15, %rax
je .LBB2_1
# %bb.2: # %.critedge.i
movq %rax, (%rbx)
movq (%r15), %rax
movq %rax, 16(%rbx)
jmp .LBB2_3
.LBB2_1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i
movq 8(%r14), %rdx
incq %rdx
movq %r15, %rsi
callq memcpy@PLT
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EOS4_.exit
movq 8(%r14), %rax
movq %rax, 8(%rbx)
movq %r15, (%r14)
movq $0, 8(%r14)
movb $0, 16(%r14)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_, .Lfunc_end2-_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx119to_stringEi,"axG",@progbits,_ZNSt7__cxx119to_stringEi,comdat
.weak _ZNSt7__cxx119to_stringEi # -- Begin function _ZNSt7__cxx119to_stringEi
.p2align 4, 0x90
.type _ZNSt7__cxx119to_stringEi,@function
_ZNSt7__cxx119to_stringEi: # @_ZNSt7__cxx119to_stringEi
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movq %rdi, %rbx
movl %esi, %ebp
negl %ebp
cmovsl %esi, %ebp
movl $1, %r12d
cmpl $10, %ebp
jb .LBB3_9
# %bb.1: # %.lr.ph.i.preheader
movl $4, %r12d
movl $3518437209, %eax # imm = 0xD1B71759
movl %ebp, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpl $99, %ecx
jbe .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=1
cmpl $999, %ecx # imm = 0x3E7
jbe .LBB3_5
# %bb.6: # in Loop: Header=BB3_2 Depth=1
cmpl $10000, %ecx # imm = 0x2710
jb .LBB3_9
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movl %ecx, %edx
imulq %rax, %rdx
shrq $45, %rdx
addl $4, %r12d
cmpl $99999, %ecx # imm = 0x1869F
movl %edx, %ecx
ja .LBB3_2
# %bb.8: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.loopexit
addl $-3, %r12d
jmp .LBB3_9
.LBB3_3:
addl $-2, %r12d
jmp .LBB3_9
.LBB3_5:
decl %r12d
.LBB3_9: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit
shrl $31, %r14d
leal (%r12,%r14), %r15d
leaq 16(%rbx), %rax
movq %rax, (%rbx)
cmpl $16, %r15d
jb .LBB3_12
# %bb.10:
leaq 1(%r15), %rdi
.Ltmp8:
callq _Znwm
.Ltmp9:
# %bb.11: # %.noexc
movq %rax, (%rbx)
movq %r15, 16(%rbx)
.LBB3_12:
testq %r15, %r15
je .LBB3_16
# %bb.13:
movq (%rbx), %rdi
cmpl $1, %r15d
jne .LBB3_15
# %bb.14:
movb $45, (%rdi)
jmp .LBB3_16
.LBB3_15:
movl $45, %esi
movq %r15, %rdx
callq memset@PLT
.LBB3_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movl %r14d, %eax
addq (%rbx), %rax
cmpl $100, %ebp
jb .LBB3_17
# %bb.18: # %.lr.ph.preheader.i
addl $-2, %r12d
.p2align 4, 0x90
.LBB3_19: # %.lr.ph.i11
# =>This Inner Loop Header: Depth=1
leal 1(%r12), %edx
movl %ebp, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %esi
movl %ebp, %edi
subl %esi, %edi
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdi,%rdi), %esi
movb %sil, (%rax,%rdx)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rdi,%rdi), %edx
movl %r12d, %esi
movb %dl, (%rax,%rsi)
addl $-2, %r12d
cmpl $9999, %ebp # imm = 0x270F
movl %ecx, %ebp
ja .LBB3_19
# %bb.20: # %._crit_edge.i
cmpl $10, %ecx
jb .LBB3_22
.LBB3_21:
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB3_23
.LBB3_17:
movl %ebp, %ecx
cmpl $10, %ecx
jae .LBB3_21
.LBB3_22:
orb $48, %cl
.LBB3_23: # %_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.exit
movb %cl, (%rax)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_24:
.cfi_def_cfa_offset 48
.Ltmp10:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZNSt7__cxx119to_stringEi, .Lfunc_end3-_ZNSt7__cxx119to_stringEi
.cfi_endproc
.section .gcc_except_table._ZNSt7__cxx119to_stringEi,"aG",@progbits,_ZNSt7__cxx119to_stringEi,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp8-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin1 # jumps to .Ltmp10
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Lfunc_end3-.Ltmp9 # Call between .Ltmp9 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
movq %rdx, %rdi
subq %rax, %rdi
movabsq $9223372036854775807, %r9 # imm = 0x7FFFFFFFFFFFFFFF
addq %rdi, %r9
cmpq %r8, %r9
jb .LBB4_19
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq %r8, %r15
subq %rdx, %r15
addq %rax, %r15
movq (%rbx), %rdi
leaq 16(%rbx), %r10
movl $15, %r9d
cmpq %r10, %rdi
je .LBB4_3
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq 16(%rbx), %r9
.LBB4_3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
cmpq %r9, %r15
jbe .LBB4_4
# %bb.17:
movq %rbx, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
jmp .LBB4_18
.LBB4_4:
leaq (%rdi,%rsi), %r14
addq %rdx, %rsi
movq %rax, %r9
subq %rsi, %r9
cmpq %rcx, %rdi
ja .LBB4_6
# %bb.5:
addq %rax, %rdi
cmpq %rcx, %rdi
jae .LBB4_16
.LBB4_6:
cmpq %rdx, %r8
je .LBB4_12
# %bb.7:
cmpq %rsi, %rax
je .LBB4_12
# %bb.8:
testq %r9, %r9
je .LBB4_12
# %bb.9:
leaq (%r14,%r8), %rdi
addq %r14, %rdx
cmpq $1, %r9
jne .LBB4_11
# %bb.10:
movzbl (%rdx), %eax
movb %al, (%rdi)
.LBB4_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
testq %r8, %r8
je .LBB4_18
.LBB4_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
cmpq $1, %r8
jne .LBB4_15
# %bb.14:
movzbl (%rcx), %eax
movb %al, (%r14)
jmp .LBB4_18
.LBB4_15:
movq %r14, %rdi
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.LBB4_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 48
movq %rdx, %rsi
movq %r9, %rdx
movq %r8, %r12
movq %rcx, %r13
callq memmove@PLT
movq %r13, %rcx
movq %r12, %r8
testq %r8, %r8
jne .LBB4_13
jmp .LBB4_18
.LBB4_16:
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_replace_coldEPcmPKcmm
jmp .LBB4_18
.LBB4_19:
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB5_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB5_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB5_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB5_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB5_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB5_6:
movq %rbp, %rdi
incq %rdi
js .LBB5_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB5_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB5_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB5_11
.LBB5_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB5_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB5_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB5_18
# %bb.13:
je .LBB5_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB5_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB5_17
.LBB5_16:
callq memcpy@PLT
.LBB5_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB5_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB5_23
# %bb.19:
subq %r14, %r12
je .LBB5_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB5_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB5_23
.LBB5_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB5_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB5_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB5_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB5_26:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end5:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end5-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end6:
.size __clang_call_terminate, .Lfunc_end6-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumIfEvPT_S1_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumIfEvPT_S1_S1_i,@object # @_Z3sumIfEvPT_S1_S1_i
.section .rodata._Z3sumIfEvPT_S1_S1_i,"aG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.weak _Z3sumIfEvPT_S1_S1_i
.p2align 3, 0x0
_Z3sumIfEvPT_S1_S1_i:
.quad _Z18__device_stub__sumIfEvPT_S1_S1_i
.size _Z3sumIfEvPT_S1_S1_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : "
.size .L.str, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string::_M_replace"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits,@object # @__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits:
.asciz "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.size .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits, 201
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3sumIfEvPT_S1_S1_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumIfEvPT_S1_S1_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3sumIfEvPT_S1_S1_i
.addrsig_sym _ZTISt13runtime_error
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumIfEvPT_S1_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z3sumIfEvPT_S1_S1_i,"axG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.protected _Z3sumIfEvPT_S1_S1_i
.globl _Z3sumIfEvPT_S1_S1_i
.p2align 8
.type _Z3sumIfEvPT_S1_S1_i,@function
_Z3sumIfEvPT_S1_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumIfEvPT_S1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z3sumIfEvPT_S1_S1_i,"axG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.Lfunc_end0:
.size _Z3sumIfEvPT_S1_S1_i, .Lfunc_end0-_Z3sumIfEvPT_S1_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumIfEvPT_S1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumIfEvPT_S1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00139c92_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i, @function
_ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i:
.LFB3388:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumIfEvPT_S1_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3388:
.size _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i, .-_ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i
.section .text._Z3sumIfEvPT_S1_S1_i,"axG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.weak _Z3sumIfEvPT_S1_S1_i
.type _Z3sumIfEvPT_S1_S1_i, @function
_Z3sumIfEvPT_S1_S1_i:
.LFB3689:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3689:
.size _Z3sumIfEvPT_S1_S1_i, .-_Z3sumIfEvPT_S1_S1_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3366:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA kernel failed : "
.section .rodata._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.section .text._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,"axG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,comdat
.weak _Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st
.type _Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st, @function
_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st:
.LFB3688:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3688
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $328, %rsp
.cfi_def_cfa_offset 368
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movq %r8, %r9
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $4096, %eax
cmpl $524288, %ecx
jg .L12
leal 254(%rcx), %eax
movl %ecx, %edx
addl $127, %edx
cmovns %edx, %eax
sarl $7, %eax
.L12:
testl %eax, %eax
movl $1, %edx
cmovle %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
.LEHB0:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L13:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _ZL34__device_stub__Z3sumIfEvPT_S1_S1_iPfS_S_i
.LEHE0:
jmp .L13
.L37:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %r12
movl %ebx, %r13d
shrl $31, %r13d
movl %ebx, %eax
negl %eax
cmovns %eax, %ebx
movl %ebx, %eax
movl $1, %ebp
movl $10000, %ecx
.L20:
cmpl $9, %eax
jbe .L16
cmpl $99, %eax
ja .L17
addl $1, %ebp
.L16:
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
leal 0(%r13,%rbp), %esi
movl $45, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r13b, %r8d
addq 32(%rsp), %r8
leaq 96(%rsp), %rdi
leaq .LC0(%rip), %rsi
movl $201, %ecx
rep movsb
subl $1, %ebp
movl $100, %ecx
.L21:
cmpl $99, %ebx
ja .L22
cmpl $9, %ebx
jbe .L23
addl %ebx, %ebx
leal 1(%rbx), %eax
movzbl 96(%rsp,%rax), %eax
movb %al, 1(%r8)
movl %ebx, %ebx
movzbl 96(%rsp,%rbx), %ebx
.L24:
movb %bl, (%r8)
leaq 32(%rsp), %rdi
movl $21, %r8d
leaq .LC1(%rip), %rcx
movl $0, %edx
movl $0, %esi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm@PLT
.LEHE1:
jmp .L39
.L17:
cmpl $999, %eax
ja .L18
addl $2, %ebp
jmp .L16
.L18:
cmpl $9999, %eax
ja .L19
addl $3, %ebp
jmp .L16
.L19:
movl %eax, %eax
movl $0, %edx
divq %rcx
addl $4, %ebp
jmp .L20
.L22:
movl %ebx, %eax
movl $0, %edx
divl %ecx
movl %eax, %ebx
addl %edx, %edx
movl %ebp, %esi
leal 1(%rdx), %eax
movl %eax, %eax
movzbl 96(%rsp,%rax), %eax
movb %al, (%r8,%rsi)
leal -1(%rbp), %eax
movl %edx, %edx
movzbl 96(%rsp,%rdx), %edx
movb %dl, (%r8,%rax)
subl $2, %ebp
jmp .L21
.L23:
addl $48, %ebx
jmp .L24
.L39:
leaq 80(%rsp), %rdx
movq %rdx, 64(%rsp)
movq (%rax), %rcx
leaq 16(%rax), %rdx
cmpq %rdx, %rcx
jne .L25
leaq 80(%rsp), %r8
movq 8(%rax), %rcx
leal 1(%rcx), %ecx
movq %r8, %rdi
movq %rdx, %rsi
rep movsb
.L26:
movq 8(%rax), %rcx
movq %rcx, 72(%rsp)
movq %rdx, (%rax)
movq $0, 8(%rax)
movb $0, 16(%rax)
leaq 64(%rsp), %rsi
movq %r12, %rdi
.LEHB2:
call _ZNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE2:
jmp .L40
.L25:
movq %rcx, 64(%rsp)
movq 16(%rax), %rcx
movq %rcx, 80(%rsp)
jmp .L26
.L40:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
je .L27
call __stack_chk_fail@PLT
.L27:
movq _ZNSt13runtime_errorD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt13runtime_error(%rip), %rsi
movq %r12, %rdi
.LEHB3:
call __cxa_throw@PLT
.L34:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L29:
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %r12, %rdi
call __cxa_free_exception@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L33:
endbr64
movq %rax, %rbx
jmp .L29
.L30:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3688:
.globl __gxx_personality_v0
.section .gcc_except_table._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,"aG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,comdat
.LLSDA3688:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3688-.LLSDACSB3688
.LLSDACSB3688:
.uleb128 .LEHB0-.LFB3688
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3688
.uleb128 .LEHE1-.LEHB1
.uleb128 .L33-.LFB3688
.uleb128 0
.uleb128 .LEHB2-.LFB3688
.uleb128 .LEHE2-.LEHB2
.uleb128 .L34-.LFB3688
.uleb128 0
.uleb128 .LEHB3-.LFB3688
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3688:
.section .text._Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,"axG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st,comdat
.size _Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st, .-_Z12AddGPUKernelIfEvPT_S1_S1_iP11CUstream_st
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3sumIfEvPT_S1_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3391:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumIfEvPT_S1_S1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3391:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.section .text._Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,"axG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,comdat
.weak _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t # -- Begin function _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t
.p2align 4, 0x90
.type _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,@function
_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t: # @_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r9
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
leal 127(%rbx), %eax
leal 254(%rbx), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $7, %ecx
cmpl $4096, %ecx # imm = 0x1000
movl $4096, %edx # imm = 0x1000
cmovll %ecx, %edx
cmpl $2, %edx
movl $1, %eax
cmovgel %edx, %eax
movq %rdi, %r12
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rax
orq $128, %rdx
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq %r12, 104(%rsp)
movq %r15, 96(%rsp)
movq %r14, 88(%rsp)
movl %ebx, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 12(%rsp), %rax
movq %rax, 40(%rsp)
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z3sumIfEvPT_S1_S1_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
testl %eax, %eax
jne .LBB0_3
# %bb.14:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
.cfi_escape 0x2e, 0x00
movl $16, %edi
movl %eax, %ebp
callq __cxa_allocate_exception
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %r14
movq %r14, %rdi
movl %ebp, %esi
callq _ZNSt7__cxx119to_stringEi
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $.L.str, %esi
movq %r14, %rdx
callq _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.Ltmp1:
# %bb.4:
movb $1, %bpl
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSt13runtime_errorC1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp4:
# %bb.5:
xorl %ebp, %ebp
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $_ZTISt13runtime_error, %esi
movl $_ZNSt13runtime_errorD1Ev, %edx
movq %rbx, %rdi
callq __cxa_throw
.Ltmp6:
# %bb.15:
.LBB0_7:
.Ltmp7:
movq %rax, %r14
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB0_9
.LBB0_6:
.Ltmp2:
movq %rax, %r14
movb $1, %bpl
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
jne .LBB0_10
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit19
testb %bpl, %bpl
jne .LBB0_12
.LBB0_13:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB0_10: # %.critedge.i.i17
.cfi_escape 0x2e, 0x00
callq _ZdlPv
testb %bpl, %bpl
je .LBB0_13
.LBB0_12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq __cxa_free_exception
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t, .Lfunc_end0-_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t
.cfi_endproc
.section .gcc_except_table._Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,"aG",@progbits,_Z12AddGPUKernelIfEvPT_S1_S1_iP12ihipStream_t,comdat
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._Z18__device_stub__sumIfEvPT_S1_S1_i,"axG",@progbits,_Z18__device_stub__sumIfEvPT_S1_S1_i,comdat
.weak _Z18__device_stub__sumIfEvPT_S1_S1_i # -- Begin function _Z18__device_stub__sumIfEvPT_S1_S1_i
.p2align 4, 0x90
.type _Z18__device_stub__sumIfEvPT_S1_S1_i,@function
_Z18__device_stub__sumIfEvPT_S1_S1_i: # @_Z18__device_stub__sumIfEvPT_S1_S1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumIfEvPT_S1_S1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__sumIfEvPT_S1_S1_i, .Lfunc_end1-_Z18__device_stub__sumIfEvPT_S1_S1_i
.cfi_endproc
# -- End function
.section .text._ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_,"axG",@progbits,_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_,comdat
.weak _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_ # -- Begin function _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.p2align 4, 0x90
.type _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_,@function
_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_: # @_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rsi, %rdi
callq strlen
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
movq %r15, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
movq %rax, %r14
leaq 16(%rbx), %rdi
movq %rdi, (%rbx)
movq (%rax), %rax
movq %r14, %r15
addq $16, %r15
cmpq %r15, %rax
je .LBB2_1
# %bb.2: # %.critedge.i
movq %rax, (%rbx)
movq (%r15), %rax
movq %rax, 16(%rbx)
jmp .LBB2_3
.LBB2_1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i
movq 8(%r14), %rdx
incq %rdx
movq %r15, %rsi
callq memcpy@PLT
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EOS4_.exit
movq 8(%r14), %rax
movq %rax, 8(%rbx)
movq %r15, (%r14)
movq $0, 8(%r14)
movb $0, 16(%r14)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_, .Lfunc_end2-_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_OS8_
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx119to_stringEi,"axG",@progbits,_ZNSt7__cxx119to_stringEi,comdat
.weak _ZNSt7__cxx119to_stringEi # -- Begin function _ZNSt7__cxx119to_stringEi
.p2align 4, 0x90
.type _ZNSt7__cxx119to_stringEi,@function
_ZNSt7__cxx119to_stringEi: # @_ZNSt7__cxx119to_stringEi
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movq %rdi, %rbx
movl %esi, %ebp
negl %ebp
cmovsl %esi, %ebp
movl $1, %r12d
cmpl $10, %ebp
jb .LBB3_9
# %bb.1: # %.lr.ph.i.preheader
movl $4, %r12d
movl $3518437209, %eax # imm = 0xD1B71759
movl %ebp, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpl $99, %ecx
jbe .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=1
cmpl $999, %ecx # imm = 0x3E7
jbe .LBB3_5
# %bb.6: # in Loop: Header=BB3_2 Depth=1
cmpl $10000, %ecx # imm = 0x2710
jb .LBB3_9
# %bb.7: # in Loop: Header=BB3_2 Depth=1
movl %ecx, %edx
imulq %rax, %rdx
shrq $45, %rdx
addl $4, %r12d
cmpl $99999, %ecx # imm = 0x1869F
movl %edx, %ecx
ja .LBB3_2
# %bb.8: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.loopexit
addl $-3, %r12d
jmp .LBB3_9
.LBB3_3:
addl $-2, %r12d
jmp .LBB3_9
.LBB3_5:
decl %r12d
.LBB3_9: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit
shrl $31, %r14d
leal (%r12,%r14), %r15d
leaq 16(%rbx), %rax
movq %rax, (%rbx)
cmpl $16, %r15d
jb .LBB3_12
# %bb.10:
leaq 1(%r15), %rdi
.Ltmp8:
callq _Znwm
.Ltmp9:
# %bb.11: # %.noexc
movq %rax, (%rbx)
movq %r15, 16(%rbx)
.LBB3_12:
testq %r15, %r15
je .LBB3_16
# %bb.13:
movq (%rbx), %rdi
cmpl $1, %r15d
jne .LBB3_15
# %bb.14:
movb $45, (%rdi)
jmp .LBB3_16
.LBB3_15:
movl $45, %esi
movq %r15, %rdx
callq memset@PLT
.LBB3_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movl %r14d, %eax
addq (%rbx), %rax
cmpl $100, %ebp
jb .LBB3_17
# %bb.18: # %.lr.ph.preheader.i
addl $-2, %r12d
.p2align 4, 0x90
.LBB3_19: # %.lr.ph.i11
# =>This Inner Loop Header: Depth=1
leal 1(%r12), %edx
movl %ebp, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %esi
movl %ebp, %edi
subl %esi, %edi
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdi,%rdi), %esi
movb %sil, (%rax,%rdx)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rdi,%rdi), %edx
movl %r12d, %esi
movb %dl, (%rax,%rsi)
addl $-2, %r12d
cmpl $9999, %ebp # imm = 0x270F
movl %ecx, %ebp
ja .LBB3_19
# %bb.20: # %._crit_edge.i
cmpl $10, %ecx
jb .LBB3_22
.LBB3_21:
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB3_23
.LBB3_17:
movl %ebp, %ecx
cmpl $10, %ecx
jae .LBB3_21
.LBB3_22:
orb $48, %cl
.LBB3_23: # %_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.exit
movb %cl, (%rax)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_24:
.cfi_def_cfa_offset 48
.Ltmp10:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZNSt7__cxx119to_stringEi, .Lfunc_end3-_ZNSt7__cxx119to_stringEi
.cfi_endproc
.section .gcc_except_table._ZNSt7__cxx119to_stringEi,"aG",@progbits,_ZNSt7__cxx119to_stringEi,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp8-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin1 # jumps to .Ltmp10
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Lfunc_end3-.Ltmp9 # Call between .Ltmp9 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
movq %rdx, %rdi
subq %rax, %rdi
movabsq $9223372036854775807, %r9 # imm = 0x7FFFFFFFFFFFFFFF
addq %rdi, %r9
cmpq %r8, %r9
jb .LBB4_19
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq %r8, %r15
subq %rdx, %r15
addq %rax, %r15
movq (%rbx), %rdi
leaq 16(%rbx), %r10
movl $15, %r9d
cmpq %r10, %rdi
je .LBB4_3
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq 16(%rbx), %r9
.LBB4_3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
cmpq %r9, %r15
jbe .LBB4_4
# %bb.17:
movq %rbx, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
jmp .LBB4_18
.LBB4_4:
leaq (%rdi,%rsi), %r14
addq %rdx, %rsi
movq %rax, %r9
subq %rsi, %r9
cmpq %rcx, %rdi
ja .LBB4_6
# %bb.5:
addq %rax, %rdi
cmpq %rcx, %rdi
jae .LBB4_16
.LBB4_6:
cmpq %rdx, %r8
je .LBB4_12
# %bb.7:
cmpq %rsi, %rax
je .LBB4_12
# %bb.8:
testq %r9, %r9
je .LBB4_12
# %bb.9:
leaq (%r14,%r8), %rdi
addq %r14, %rdx
cmpq $1, %r9
jne .LBB4_11
# %bb.10:
movzbl (%rdx), %eax
movb %al, (%rdi)
.LBB4_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
testq %r8, %r8
je .LBB4_18
.LBB4_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
cmpq $1, %r8
jne .LBB4_15
# %bb.14:
movzbl (%rcx), %eax
movb %al, (%r14)
jmp .LBB4_18
.LBB4_15:
movq %r14, %rdi
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.LBB4_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 48
movq %rdx, %rsi
movq %r9, %rdx
movq %r8, %r12
movq %rcx, %r13
callq memmove@PLT
movq %r13, %rcx
movq %r12, %r8
testq %r8, %r8
jne .LBB4_13
jmp .LBB4_18
.LBB4_16:
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_replace_coldEPcmPKcmm
jmp .LBB4_18
.LBB4_19:
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB5_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB5_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB5_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB5_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB5_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB5_6:
movq %rbp, %rdi
incq %rdi
js .LBB5_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB5_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB5_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB5_11
.LBB5_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB5_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB5_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB5_18
# %bb.13:
je .LBB5_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB5_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB5_17
.LBB5_16:
callq memcpy@PLT
.LBB5_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB5_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB5_23
# %bb.19:
subq %r14, %r12
je .LBB5_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB5_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB5_23
.LBB5_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB5_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB5_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB5_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB5_26:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end5:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end5-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end6:
.size __clang_call_terminate, .Lfunc_end6-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumIfEvPT_S1_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumIfEvPT_S1_S1_i,@object # @_Z3sumIfEvPT_S1_S1_i
.section .rodata._Z3sumIfEvPT_S1_S1_i,"aG",@progbits,_Z3sumIfEvPT_S1_S1_i,comdat
.weak _Z3sumIfEvPT_S1_S1_i
.p2align 3, 0x0
_Z3sumIfEvPT_S1_S1_i:
.quad _Z18__device_stub__sumIfEvPT_S1_S1_i
.size _Z3sumIfEvPT_S1_S1_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel failed : "
.size .L.str, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string::_M_replace"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "basic_string::_M_create"
.size .L.str.3, 24
.type .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits,@object # @__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits:
.asciz "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.size .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits, 201
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3sumIfEvPT_S1_S1_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumIfEvPT_S1_S1_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3sumIfEvPT_S1_S1_i
.addrsig_sym _ZTISt13runtime_error
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
// Cython function from 'thinc' library
class NumpyOps(Ops):
def backprop_mean_pool(self, float[:, ::1] d_means, int[::1] lengths):
cdef int B = lengths.shape[0]
cdef int O = d_means.shape[1]
cdef int T = 0
for length in lengths[:B]:
T += length
cdef Pool mem = Pool()
dX = <float*>mem.alloc(T * O, sizeof(float))
cpu_backprop_mean_pool(dX,
&d_means[0,0], &lengths[0], B, T, O)
return cpu_floats_ptr2array(dX, (T, O))
cdef void cpu_backprop_mean_pool(float* dX__to,
const float* d_means__bo, const int* lengths__b,
int B, int T, int O) nogil:
cdef float scale = 0.
for length in lengths__b[:B]:
scale = 1./ length
for _ in range(length):
VecVec.add_i(dX__to,
d_means__bo, scale, O)
dX__to += O
d_means__bo += O
*/
void __global__ backprop_mean_pool(float* means, float *words, int *lengths,int *prevLengths, int numdocs, int dims)
{
int bid = blockIdx.x;
__shared__ float local_means[256];
for(int step = bid; step < numdocs; step += gridDim.x )
{
int wordsInDoc = lengths[step];
int blockStarts = prevLengths[step]*dims;
local_means[threadIdx.x] = means[step*dims+threadIdx.x];
for (int i = blockStarts + threadIdx.x; i < blockStarts+(wordsInDoc*dims) ; i += dims)
words[i] = local_means[threadIdx.x]/wordsInDoc;
}
} | code for sm_80
Function : _Z18backprop_mean_poolPfS_PiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.WIDE R8, R0, R11, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e020b */
/*0080*/ IMAD.WIDE R6, R0.reuse, R11, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe400078e020b */
/*0090*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ee2000c1e1900 */
/*00b0*/ IMAD R10, R0, c[0x0][0x184], R3 ; /* 0x00006100000a7a24 */
/* 0x001fc800078e0203 */
/*00c0*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000b */
/*00d0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x020162000c1e1900 */
/*00e0*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fe20007ffe0ff */
/*00f0*/ BSSY B0, 0x2b0 ; /* 0x000001b000007945 */
/* 0x000fe60003800000 */
/*0100*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f46270 */
/*0110*/ IMAD R12, R8, c[0x0][0x184], RZ ; /* 0x00006100080c7a24 */
/* 0x004fc800078e02ff */
/*0120*/ IMAD R4, R13, c[0x0][0x184], R12 ; /* 0x000061000d047a24 */
/* 0x008fe400078e020c */
/*0130*/ IMAD.IADD R5, R12, 0x1, R3 ; /* 0x000000010c057824 */
/* 0x000fca00078e0203 */
/*0140*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f06270 */
/*0150*/ @P0 BRA 0x2a0 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0160*/ I2F R11, R13 ; /* 0x0000000d000b7306 */
/* 0x001e220000201400 */
/*0170*/ BSSY B1, 0x230 ; /* 0x000000b000017945 */
/* 0x000fee0003800000 */
/*0180*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x001e300000001000 */
/*0190*/ FCHK P0, R2, R11 ; /* 0x0000000b02007302 */
/* 0x020e620000000000 */
/*01a0*/ FFMA R7, -R11, R6, 1 ; /* 0x3f8000000b077423 */
/* 0x001fc80000000106 */
/*01b0*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*01c0*/ FFMA R6, R2, R7, RZ ; /* 0x0000000702067223 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R8, -R11, R6, R2 ; /* 0x000000060b087223 */
/* 0x000fc80000000102 */
/*01e0*/ FFMA R9, R7, R8, R6 ; /* 0x0000000807097223 */
/* 0x000fe20000000006 */
/*01f0*/ @!P0 BRA 0x220 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0200*/ MOV R6, 0x220 ; /* 0x0000022000067802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x2e0 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R6, R5, R8, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fc800078e0208 */
/*0250*/ IADD3 R5, R5, c[0x0][0x184], RZ ; /* 0x0000610005057a10 */
/* 0x000fe20007ffe0ff */
/*0260*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e6000c101904 */
/*0270*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe20003f06270 */
/*0280*/ IMAD.WIDE R6, R8, c[0x0][0x184], R6 ; /* 0x0000610008067a25 */
/* 0x001fd800078e0206 */
/*0290*/ @!P0 BRA 0x250 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02b0*/ @!P2 BRA 0x60 ; /* 0xfffffda00000a947 */
/* 0x000fea000383ffff */
/*02c0*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x020fe20000004800 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ SHF.R.U32.HI R9, RZ, 0x17, R11 ; /* 0x00000017ff097819 */
/* 0x000fe2000001160b */
/*02f0*/ BSSY B2, 0x940 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0300*/ SHF.R.U32.HI R7, RZ, 0x17, R2.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011602 */
/*0310*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0320*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fe400078ec0ff */
/*0330*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe400078ec0ff */
/*0340*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R12, R15, -0x1, RZ ; /* 0xffffffff0f0c7810 */
/* 0x000fc40007ffe0ff */
/*0360*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*0370*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0380*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0390*/ @!P0 BRA 0x520 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe20003f1c200 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*03c0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03e0*/ @P0 BRA 0x920 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, R10, 0xc8, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c80a */
/*0400*/ @!P0 BRA 0x900 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0410*/ FSETP.NEU.FTZ.AND P3, PT, |R2|.reuse, +INF , PT ; /* 0x7f8000000200780b */
/* 0x040fe40003f7d200 */
/*0420*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0430*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fd60003f1d200 */
/*0440*/ @!P1 BRA !P3, 0x900 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0450*/ LOP3.LUT P3, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000786c0ff */
/*0460*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0470*/ @P1 BRA 0x8e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*0490*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04a0*/ @P0 BRA 0x8b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04b0*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*04c0*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*04d0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*04e0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*04f0*/ @!P0 FFMA R10, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f800000020a8823 */
/* 0x000fe400000000ff */
/*0500*/ @!P1 FFMA R11, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070b9823 */
/* 0x000fe200000000ff */
/*0510*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0520*/ LEA R12, R9, 0xc0800000, 0x17 ; /* 0xc0800000090c7811 */
/* 0x000fe200078eb8ff */
/*0530*/ BSSY B3, 0x8a0 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0540*/ IMAD.IADD R12, R11, 0x1, -R12 ; /* 0x000000010b0c7824 */
/* 0x000fe200078e0a0c */
/*0550*/ IADD3 R11, R15, -0x7f, RZ ; /* 0xffffff810f0b7810 */
/* 0x000fc60007ffe0ff */
/*0560*/ MUFU.RCP R13, R12 ; /* 0x0000000c000d7308 */
/* 0x000e220000001000 */
/*0570*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fe40000010100 */
/*0580*/ IMAD R7, R11.reuse, -0x800000, R10 ; /* 0xff8000000b077824 */
/* 0x040fe200078e020a */
/*0590*/ IADD3 R11, R11, 0x7f, -R9 ; /* 0x0000007f0b0b7810 */
/* 0x000fca0007ffe809 */
/*05a0*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fe400078e0208 */
/*05b0*/ FFMA R16, R13, R14, 1 ; /* 0x3f8000000d107423 */
/* 0x001fc8000000000e */
/*05c0*/ FFMA R16, R13, R16, R13 ; /* 0x000000100d107223 */
/* 0x000fc8000000000d */
/*05d0*/ FFMA R10, R7, R16, RZ ; /* 0x00000010070a7223 */
/* 0x000fc800000000ff */
/*05e0*/ FFMA R13, R14, R10, R7 ; /* 0x0000000a0e0d7223 */
/* 0x000fc80000000007 */
/*05f0*/ FFMA R13, R16, R13, R10 ; /* 0x0000000d100d7223 */
/* 0x000fc8000000000a */
/*0600*/ FFMA R14, R14, R13, R7 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000007 */
/*0610*/ FFMA R7, R16, R14, R13 ; /* 0x0000000e10077223 */
/* 0x000fca000000000d */
/*0620*/ SHF.R.U32.HI R9, RZ, 0x17, R7 ; /* 0x00000017ff097819 */
/* 0x000fc80000011607 */
/*0630*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fca00078ec0ff */
/*0640*/ IMAD.IADD R12, R9, 0x1, R8 ; /* 0x00000001090c7824 */
/* 0x000fca00078e0208 */
/*0650*/ IADD3 R9, R12, -0x1, RZ ; /* 0xffffffff0c097810 */
/* 0x000fc80007ffe0ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0670*/ @!P0 BRA 0x880 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0690*/ @P0 BRA 0x850 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*06b0*/ @P0 BRA 0x890 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06c0*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*06d0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*06e0*/ @!P0 BRA 0x890 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06f0*/ FFMA.RZ R8, R16, R14.reuse, R13.reuse ; /* 0x0000000e10087223 */
/* 0x180fe2000000c00d */
/*0700*/ IADD3 R11, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fe20007ffe0ff */
/*0710*/ FFMA.RM R9, R16, R14.reuse, R13.reuse ; /* 0x0000000e10097223 */
/* 0x180fe2000000400d */
/*0720*/ ISETP.NE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f65270 */
/*0730*/ LOP3.LUT R10, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff080a7812 */
/* 0x000fe200078ec0ff */
/*0740*/ FFMA.RP R8, R16, R14, R13 ; /* 0x0000000e10087223 */
/* 0x000fe2000000800d */
/*0750*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0760*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0c */
/*0770*/ LOP3.LUT R10, R10, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000a0a7812 */
/* 0x000fe400078efcff */
/*0780*/ FSETP.NEU.FTZ.AND P0, PT, R8, R9, PT ; /* 0x000000090800720b */
/* 0x000fc40003f1d000 */
/*0790*/ SHF.L.U32 R11, R10, R11, RZ ; /* 0x0000000b0a0b7219 */
/* 0x000fe400000006ff */
/*07a0*/ SEL R9, R12, RZ, P3 ; /* 0x000000ff0c097207 */
/* 0x000fe40001800000 */
/*07b0*/ ISETP.NE.AND P1, PT, R11, RZ, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40000f25270 */
/*07c0*/ SHF.R.U32.HI R9, RZ, R9, R10 ; /* 0x00000009ff097219 */
/* 0x000fe4000001160a */
/*07d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07e0*/ SHF.R.U32.HI R11, RZ, 0x1, R9 ; /* 0x00000001ff0b7819 */
/* 0x000fc40000011609 */
/*07f0*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fc80004000000 */
/*0800*/ LOP3.LUT R8, R8, 0x1, R11, 0xf8, !PT ; /* 0x0000000108087812 */
/* 0x000fc800078ef80b */
/*0810*/ LOP3.LUT R8, R8, R9, RZ, 0xc0, !PT ; /* 0x0000000908087212 */
/* 0x000fca00078ec0ff */
/*0820*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fca00078e0208 */
/*0830*/ LOP3.LUT R7, R8, R7, RZ, 0xfc, !PT ; /* 0x0000000708077212 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x890 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0850*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0860*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0870*/ BRA 0x890 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD R7, R8, 0x800000, R7 ; /* 0x0080000008077824 */
/* 0x000fe400078e0207 */
/*0890*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x930 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R7, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fc800078e480a */
/*08c0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*08d0*/ BRA 0x930 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fe200078e480a */
/*08f0*/ BRA 0x930 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0900*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0910*/ BRA 0x930 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0920*/ FADD.FTZ R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x000fe40000010000 */
/*0930*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0940*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0950*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0960*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff69006007950 */
/* 0x000fea0003c3ffff */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
// Cython function from 'thinc' library
class NumpyOps(Ops):
def backprop_mean_pool(self, float[:, ::1] d_means, int[::1] lengths):
cdef int B = lengths.shape[0]
cdef int O = d_means.shape[1]
cdef int T = 0
for length in lengths[:B]:
T += length
cdef Pool mem = Pool()
dX = <float*>mem.alloc(T * O, sizeof(float))
cpu_backprop_mean_pool(dX,
&d_means[0,0], &lengths[0], B, T, O)
return cpu_floats_ptr2array(dX, (T, O))
cdef void cpu_backprop_mean_pool(float* dX__to,
const float* d_means__bo, const int* lengths__b,
int B, int T, int O) nogil:
cdef float scale = 0.
for length in lengths__b[:B]:
scale = 1./ length
for _ in range(length):
VecVec.add_i(dX__to,
d_means__bo, scale, O)
dX__to += O
d_means__bo += O
*/
void __global__ backprop_mean_pool(float* means, float *words, int *lengths,int *prevLengths, int numdocs, int dims)
{
int bid = blockIdx.x;
__shared__ float local_means[256];
for(int step = bid; step < numdocs; step += gridDim.x )
{
int wordsInDoc = lengths[step];
int blockStarts = prevLengths[step]*dims;
local_means[threadIdx.x] = means[step*dims+threadIdx.x];
for (int i = blockStarts + threadIdx.x; i < blockStarts+(wordsInDoc*dims) ; i += dims)
words[i] = local_means[threadIdx.x]/wordsInDoc;
}
} | .file "tmpxft_0019d1c9_00000000-6_backprop_mean_pool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii
.type _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii, @function
_Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18backprop_mean_poolPfS_PiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii, .-_Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii
.globl _Z18backprop_mean_poolPfS_PiS0_ii
.type _Z18backprop_mean_poolPfS_PiS0_ii, @function
_Z18backprop_mean_poolPfS_PiS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18backprop_mean_poolPfS_PiS0_ii, .-_Z18backprop_mean_poolPfS_PiS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18backprop_mean_poolPfS_PiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18backprop_mean_poolPfS_PiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
// Cython function from 'thinc' library
class NumpyOps(Ops):
def backprop_mean_pool(self, float[:, ::1] d_means, int[::1] lengths):
cdef int B = lengths.shape[0]
cdef int O = d_means.shape[1]
cdef int T = 0
for length in lengths[:B]:
T += length
cdef Pool mem = Pool()
dX = <float*>mem.alloc(T * O, sizeof(float))
cpu_backprop_mean_pool(dX,
&d_means[0,0], &lengths[0], B, T, O)
return cpu_floats_ptr2array(dX, (T, O))
cdef void cpu_backprop_mean_pool(float* dX__to,
const float* d_means__bo, const int* lengths__b,
int B, int T, int O) nogil:
cdef float scale = 0.
for length in lengths__b[:B]:
scale = 1./ length
for _ in range(length):
VecVec.add_i(dX__to,
d_means__bo, scale, O)
dX__to += O
d_means__bo += O
*/
void __global__ backprop_mean_pool(float* means, float *words, int *lengths,int *prevLengths, int numdocs, int dims)
{
int bid = blockIdx.x;
__shared__ float local_means[256];
for(int step = bid; step < numdocs; step += gridDim.x )
{
int wordsInDoc = lengths[step];
int blockStarts = prevLengths[step]*dims;
local_means[threadIdx.x] = means[step*dims+threadIdx.x];
for (int i = blockStarts + threadIdx.x; i < blockStarts+(wordsInDoc*dims) ; i += dims)
words[i] = local_means[threadIdx.x]/wordsInDoc;
}
} | #include <hip/hip_runtime.h>
/*
// Cython function from 'thinc' library
class NumpyOps(Ops):
def backprop_mean_pool(self, float[:, ::1] d_means, int[::1] lengths):
cdef int B = lengths.shape[0]
cdef int O = d_means.shape[1]
cdef int T = 0
for length in lengths[:B]:
T += length
cdef Pool mem = Pool()
dX = <float*>mem.alloc(T * O, sizeof(float))
cpu_backprop_mean_pool(dX,
&d_means[0,0], &lengths[0], B, T, O)
return cpu_floats_ptr2array(dX, (T, O))
cdef void cpu_backprop_mean_pool(float* dX__to,
const float* d_means__bo, const int* lengths__b,
int B, int T, int O) nogil:
cdef float scale = 0.
for length in lengths__b[:B]:
scale = 1./ length
for _ in range(length):
VecVec.add_i(dX__to,
d_means__bo, scale, O)
dX__to += O
d_means__bo += O
*/
void __global__ backprop_mean_pool(float* means, float *words, int *lengths,int *prevLengths, int numdocs, int dims)
{
int bid = blockIdx.x;
__shared__ float local_means[256];
for(int step = bid; step < numdocs; step += gridDim.x )
{
int wordsInDoc = lengths[step];
int blockStarts = prevLengths[step]*dims;
local_means[threadIdx.x] = means[step*dims+threadIdx.x];
for (int i = blockStarts + threadIdx.x; i < blockStarts+(wordsInDoc*dims) ; i += dims)
words[i] = local_means[threadIdx.x]/wordsInDoc;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
// Cython function from 'thinc' library
class NumpyOps(Ops):
def backprop_mean_pool(self, float[:, ::1] d_means, int[::1] lengths):
cdef int B = lengths.shape[0]
cdef int O = d_means.shape[1]
cdef int T = 0
for length in lengths[:B]:
T += length
cdef Pool mem = Pool()
dX = <float*>mem.alloc(T * O, sizeof(float))
cpu_backprop_mean_pool(dX,
&d_means[0,0], &lengths[0], B, T, O)
return cpu_floats_ptr2array(dX, (T, O))
cdef void cpu_backprop_mean_pool(float* dX__to,
const float* d_means__bo, const int* lengths__b,
int B, int T, int O) nogil:
cdef float scale = 0.
for length in lengths__b[:B]:
scale = 1./ length
for _ in range(length):
VecVec.add_i(dX__to,
d_means__bo, scale, O)
dX__to += O
d_means__bo += O
*/
void __global__ backprop_mean_pool(float* means, float *words, int *lengths,int *prevLengths, int numdocs, int dims)
{
int bid = blockIdx.x;
__shared__ float local_means[256];
for(int step = bid; step < numdocs; step += gridDim.x )
{
int wordsInDoc = lengths[step];
int blockStarts = prevLengths[step]*dims;
local_means[threadIdx.x] = means[step*dims+threadIdx.x];
for (int i = blockStarts + threadIdx.x; i < blockStarts+(wordsInDoc*dims) ; i += dims)
words[i] = local_means[threadIdx.x]/wordsInDoc;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18backprop_mean_poolPfS_PiS0_ii
.globl _Z18backprop_mean_poolPfS_PiS0_ii
.p2align 8
.type _Z18backprop_mean_poolPfS_PiS0_ii,@function
_Z18backprop_mean_poolPfS_PiS0_ii:
s_load_b32 s16, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s16
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x24
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_ashr_i32 s1, s12, 31
s_mov_b32 s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[0:1], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s13, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s2, s16
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_mov_b32 s3, exec_lo
s_add_u32 s18, s8, s0
s_addc_u32 s19, s9, s1
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_load_b32 s1, s[0:1], 0x0
s_load_b32 s0, s[18:19], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s1, s12, v[0:1]
s_add_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s1, s1, s12
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s1, v1
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, s2, s12, v[0:1]
v_mov_b32_e32 v3, v4
v_cvt_f32_i32_e32 v6, s0
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v2, null, v6, v6, v5
v_div_scale_f32 v8, vcc_lo, v5, v6, v5
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v7, v3
v_mul_f32_e32 v7, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v2, v7, v8
v_fmac_f32_e32 v7, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v2, v7, v8
v_ashrrev_i32_e32 v2, 31, v1
v_div_fmas_f32 v7, v8, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_div_fixup_f32 v5, v7, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB0_5:
v_add_nc_u32_e32 v1, s12, v1
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, s0, v2, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s15, v3, s0
v_cmp_le_i32_e32 vcc_lo, s1, v1
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18backprop_mean_poolPfS_PiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18backprop_mean_poolPfS_PiS0_ii, .Lfunc_end0-_Z18backprop_mean_poolPfS_PiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18backprop_mean_poolPfS_PiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z18backprop_mean_poolPfS_PiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
// Cython function from 'thinc' library
class NumpyOps(Ops):
def backprop_mean_pool(self, float[:, ::1] d_means, int[::1] lengths):
cdef int B = lengths.shape[0]
cdef int O = d_means.shape[1]
cdef int T = 0
for length in lengths[:B]:
T += length
cdef Pool mem = Pool()
dX = <float*>mem.alloc(T * O, sizeof(float))
cpu_backprop_mean_pool(dX,
&d_means[0,0], &lengths[0], B, T, O)
return cpu_floats_ptr2array(dX, (T, O))
cdef void cpu_backprop_mean_pool(float* dX__to,
const float* d_means__bo, const int* lengths__b,
int B, int T, int O) nogil:
cdef float scale = 0.
for length in lengths__b[:B]:
scale = 1./ length
for _ in range(length):
VecVec.add_i(dX__to,
d_means__bo, scale, O)
dX__to += O
d_means__bo += O
*/
void __global__ backprop_mean_pool(float* means, float *words, int *lengths,int *prevLengths, int numdocs, int dims)
{
int bid = blockIdx.x;
__shared__ float local_means[256];
for(int step = bid; step < numdocs; step += gridDim.x )
{
int wordsInDoc = lengths[step];
int blockStarts = prevLengths[step]*dims;
local_means[threadIdx.x] = means[step*dims+threadIdx.x];
for (int i = blockStarts + threadIdx.x; i < blockStarts+(wordsInDoc*dims) ; i += dims)
words[i] = local_means[threadIdx.x]/wordsInDoc;
}
} | .text
.file "backprop_mean_pool.hip"
.globl _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii # -- Begin function _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.p2align 4, 0x90
.type _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii,@function
_Z33__device_stub__backprop_mean_poolPfS_PiS0_ii: # @_Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18backprop_mean_poolPfS_PiS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii, .Lfunc_end0-_Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18backprop_mean_poolPfS_PiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18backprop_mean_poolPfS_PiS0_ii,@object # @_Z18backprop_mean_poolPfS_PiS0_ii
.section .rodata,"a",@progbits
.globl _Z18backprop_mean_poolPfS_PiS0_ii
.p2align 3, 0x0
_Z18backprop_mean_poolPfS_PiS0_ii:
.quad _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.size _Z18backprop_mean_poolPfS_PiS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18backprop_mean_poolPfS_PiS0_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18backprop_mean_poolPfS_PiS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18backprop_mean_poolPfS_PiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.WIDE R8, R0, R11, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e020b */
/*0080*/ IMAD.WIDE R6, R0.reuse, R11, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe400078e020b */
/*0090*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ee2000c1e1900 */
/*00b0*/ IMAD R10, R0, c[0x0][0x184], R3 ; /* 0x00006100000a7a24 */
/* 0x001fc800078e0203 */
/*00c0*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000b */
/*00d0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x020162000c1e1900 */
/*00e0*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fe20007ffe0ff */
/*00f0*/ BSSY B0, 0x2b0 ; /* 0x000001b000007945 */
/* 0x000fe60003800000 */
/*0100*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f46270 */
/*0110*/ IMAD R12, R8, c[0x0][0x184], RZ ; /* 0x00006100080c7a24 */
/* 0x004fc800078e02ff */
/*0120*/ IMAD R4, R13, c[0x0][0x184], R12 ; /* 0x000061000d047a24 */
/* 0x008fe400078e020c */
/*0130*/ IMAD.IADD R5, R12, 0x1, R3 ; /* 0x000000010c057824 */
/* 0x000fca00078e0203 */
/*0140*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f06270 */
/*0150*/ @P0 BRA 0x2a0 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0160*/ I2F R11, R13 ; /* 0x0000000d000b7306 */
/* 0x001e220000201400 */
/*0170*/ BSSY B1, 0x230 ; /* 0x000000b000017945 */
/* 0x000fee0003800000 */
/*0180*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x001e300000001000 */
/*0190*/ FCHK P0, R2, R11 ; /* 0x0000000b02007302 */
/* 0x020e620000000000 */
/*01a0*/ FFMA R7, -R11, R6, 1 ; /* 0x3f8000000b077423 */
/* 0x001fc80000000106 */
/*01b0*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*01c0*/ FFMA R6, R2, R7, RZ ; /* 0x0000000702067223 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R8, -R11, R6, R2 ; /* 0x000000060b087223 */
/* 0x000fc80000000102 */
/*01e0*/ FFMA R9, R7, R8, R6 ; /* 0x0000000807097223 */
/* 0x000fe20000000006 */
/*01f0*/ @!P0 BRA 0x220 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0200*/ MOV R6, 0x220 ; /* 0x0000022000067802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x2e0 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R6, R5, R8, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fc800078e0208 */
/*0250*/ IADD3 R5, R5, c[0x0][0x184], RZ ; /* 0x0000610005057a10 */
/* 0x000fe20007ffe0ff */
/*0260*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e6000c101904 */
/*0270*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe20003f06270 */
/*0280*/ IMAD.WIDE R6, R8, c[0x0][0x184], R6 ; /* 0x0000610008067a25 */
/* 0x001fd800078e0206 */
/*0290*/ @!P0 BRA 0x250 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02b0*/ @!P2 BRA 0x60 ; /* 0xfffffda00000a947 */
/* 0x000fea000383ffff */
/*02c0*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x020fe20000004800 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ SHF.R.U32.HI R9, RZ, 0x17, R11 ; /* 0x00000017ff097819 */
/* 0x000fe2000001160b */
/*02f0*/ BSSY B2, 0x940 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0300*/ SHF.R.U32.HI R7, RZ, 0x17, R2.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011602 */
/*0310*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0320*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fe400078ec0ff */
/*0330*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe400078ec0ff */
/*0340*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R12, R15, -0x1, RZ ; /* 0xffffffff0f0c7810 */
/* 0x000fc40007ffe0ff */
/*0360*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*0370*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0380*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0390*/ @!P0 BRA 0x520 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe20003f1c200 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*03c0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03e0*/ @P0 BRA 0x920 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, R10, 0xc8, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c80a */
/*0400*/ @!P0 BRA 0x900 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0410*/ FSETP.NEU.FTZ.AND P3, PT, |R2|.reuse, +INF , PT ; /* 0x7f8000000200780b */
/* 0x040fe40003f7d200 */
/*0420*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0430*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fd60003f1d200 */
/*0440*/ @!P1 BRA !P3, 0x900 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0450*/ LOP3.LUT P3, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000786c0ff */
/*0460*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0470*/ @P1 BRA 0x8e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*0490*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04a0*/ @P0 BRA 0x8b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04b0*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*04c0*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*04d0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*04e0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*04f0*/ @!P0 FFMA R10, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f800000020a8823 */
/* 0x000fe400000000ff */
/*0500*/ @!P1 FFMA R11, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070b9823 */
/* 0x000fe200000000ff */
/*0510*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0520*/ LEA R12, R9, 0xc0800000, 0x17 ; /* 0xc0800000090c7811 */
/* 0x000fe200078eb8ff */
/*0530*/ BSSY B3, 0x8a0 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0540*/ IMAD.IADD R12, R11, 0x1, -R12 ; /* 0x000000010b0c7824 */
/* 0x000fe200078e0a0c */
/*0550*/ IADD3 R11, R15, -0x7f, RZ ; /* 0xffffff810f0b7810 */
/* 0x000fc60007ffe0ff */
/*0560*/ MUFU.RCP R13, R12 ; /* 0x0000000c000d7308 */
/* 0x000e220000001000 */
/*0570*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fe40000010100 */
/*0580*/ IMAD R7, R11.reuse, -0x800000, R10 ; /* 0xff8000000b077824 */
/* 0x040fe200078e020a */
/*0590*/ IADD3 R11, R11, 0x7f, -R9 ; /* 0x0000007f0b0b7810 */
/* 0x000fca0007ffe809 */
/*05a0*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fe400078e0208 */
/*05b0*/ FFMA R16, R13, R14, 1 ; /* 0x3f8000000d107423 */
/* 0x001fc8000000000e */
/*05c0*/ FFMA R16, R13, R16, R13 ; /* 0x000000100d107223 */
/* 0x000fc8000000000d */
/*05d0*/ FFMA R10, R7, R16, RZ ; /* 0x00000010070a7223 */
/* 0x000fc800000000ff */
/*05e0*/ FFMA R13, R14, R10, R7 ; /* 0x0000000a0e0d7223 */
/* 0x000fc80000000007 */
/*05f0*/ FFMA R13, R16, R13, R10 ; /* 0x0000000d100d7223 */
/* 0x000fc8000000000a */
/*0600*/ FFMA R14, R14, R13, R7 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000007 */
/*0610*/ FFMA R7, R16, R14, R13 ; /* 0x0000000e10077223 */
/* 0x000fca000000000d */
/*0620*/ SHF.R.U32.HI R9, RZ, 0x17, R7 ; /* 0x00000017ff097819 */
/* 0x000fc80000011607 */
/*0630*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fca00078ec0ff */
/*0640*/ IMAD.IADD R12, R9, 0x1, R8 ; /* 0x00000001090c7824 */
/* 0x000fca00078e0208 */
/*0650*/ IADD3 R9, R12, -0x1, RZ ; /* 0xffffffff0c097810 */
/* 0x000fc80007ffe0ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0670*/ @!P0 BRA 0x880 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0690*/ @P0 BRA 0x850 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*06b0*/ @P0 BRA 0x890 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06c0*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*06d0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*06e0*/ @!P0 BRA 0x890 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06f0*/ FFMA.RZ R8, R16, R14.reuse, R13.reuse ; /* 0x0000000e10087223 */
/* 0x180fe2000000c00d */
/*0700*/ IADD3 R11, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fe20007ffe0ff */
/*0710*/ FFMA.RM R9, R16, R14.reuse, R13.reuse ; /* 0x0000000e10097223 */
/* 0x180fe2000000400d */
/*0720*/ ISETP.NE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f65270 */
/*0730*/ LOP3.LUT R10, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff080a7812 */
/* 0x000fe200078ec0ff */
/*0740*/ FFMA.RP R8, R16, R14, R13 ; /* 0x0000000e10087223 */
/* 0x000fe2000000800d */
/*0750*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0760*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0c */
/*0770*/ LOP3.LUT R10, R10, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000a0a7812 */
/* 0x000fe400078efcff */
/*0780*/ FSETP.NEU.FTZ.AND P0, PT, R8, R9, PT ; /* 0x000000090800720b */
/* 0x000fc40003f1d000 */
/*0790*/ SHF.L.U32 R11, R10, R11, RZ ; /* 0x0000000b0a0b7219 */
/* 0x000fe400000006ff */
/*07a0*/ SEL R9, R12, RZ, P3 ; /* 0x000000ff0c097207 */
/* 0x000fe40001800000 */
/*07b0*/ ISETP.NE.AND P1, PT, R11, RZ, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40000f25270 */
/*07c0*/ SHF.R.U32.HI R9, RZ, R9, R10 ; /* 0x00000009ff097219 */
/* 0x000fe4000001160a */
/*07d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07e0*/ SHF.R.U32.HI R11, RZ, 0x1, R9 ; /* 0x00000001ff0b7819 */
/* 0x000fc40000011609 */
/*07f0*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fc80004000000 */
/*0800*/ LOP3.LUT R8, R8, 0x1, R11, 0xf8, !PT ; /* 0x0000000108087812 */
/* 0x000fc800078ef80b */
/*0810*/ LOP3.LUT R8, R8, R9, RZ, 0xc0, !PT ; /* 0x0000000908087212 */
/* 0x000fca00078ec0ff */
/*0820*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fca00078e0208 */
/*0830*/ LOP3.LUT R7, R8, R7, RZ, 0xfc, !PT ; /* 0x0000000708077212 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x890 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0850*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0860*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0870*/ BRA 0x890 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD R7, R8, 0x800000, R7 ; /* 0x0080000008077824 */
/* 0x000fe400078e0207 */
/*0890*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x930 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R7, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fc800078e480a */
/*08c0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*08d0*/ BRA 0x930 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fe200078e480a */
/*08f0*/ BRA 0x930 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0900*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0910*/ BRA 0x930 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0920*/ FADD.FTZ R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x000fe40000010000 */
/*0930*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0940*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0950*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0960*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff69006007950 */
/* 0x000fea0003c3ffff */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18backprop_mean_poolPfS_PiS0_ii
.globl _Z18backprop_mean_poolPfS_PiS0_ii
.p2align 8
.type _Z18backprop_mean_poolPfS_PiS0_ii,@function
_Z18backprop_mean_poolPfS_PiS0_ii:
s_load_b32 s16, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s16
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x24
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_ashr_i32 s1, s12, 31
s_mov_b32 s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[0:1], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s13, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s2, s16
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_mov_b32 s3, exec_lo
s_add_u32 s18, s8, s0
s_addc_u32 s19, s9, s1
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_load_b32 s1, s[0:1], 0x0
s_load_b32 s0, s[18:19], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s1, s12, v[0:1]
s_add_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s1, s1, s12
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s1, v1
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, s2, s12, v[0:1]
v_mov_b32_e32 v3, v4
v_cvt_f32_i32_e32 v6, s0
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v2, null, v6, v6, v5
v_div_scale_f32 v8, vcc_lo, v5, v6, v5
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v7, v3
v_mul_f32_e32 v7, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v2, v7, v8
v_fmac_f32_e32 v7, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v2, v7, v8
v_ashrrev_i32_e32 v2, 31, v1
v_div_fmas_f32 v7, v8, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_div_fixup_f32 v5, v7, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB0_5:
v_add_nc_u32_e32 v1, s12, v1
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, s0, v2, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s15, v3, s0
v_cmp_le_i32_e32 vcc_lo, s1, v1
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18backprop_mean_poolPfS_PiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18backprop_mean_poolPfS_PiS0_ii, .Lfunc_end0-_Z18backprop_mean_poolPfS_PiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18backprop_mean_poolPfS_PiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z18backprop_mean_poolPfS_PiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d1c9_00000000-6_backprop_mean_pool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii
.type _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii, @function
_Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18backprop_mean_poolPfS_PiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii, .-_Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii
.globl _Z18backprop_mean_poolPfS_PiS0_ii
.type _Z18backprop_mean_poolPfS_PiS0_ii, @function
_Z18backprop_mean_poolPfS_PiS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z18backprop_mean_poolPfS_PiS0_iiPfS_PiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18backprop_mean_poolPfS_PiS0_ii, .-_Z18backprop_mean_poolPfS_PiS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18backprop_mean_poolPfS_PiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18backprop_mean_poolPfS_PiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "backprop_mean_pool.hip"
.globl _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii # -- Begin function _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.p2align 4, 0x90
.type _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii,@function
_Z33__device_stub__backprop_mean_poolPfS_PiS0_ii: # @_Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18backprop_mean_poolPfS_PiS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii, .Lfunc_end0-_Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18backprop_mean_poolPfS_PiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18backprop_mean_poolPfS_PiS0_ii,@object # @_Z18backprop_mean_poolPfS_PiS0_ii
.section .rodata,"a",@progbits
.globl _Z18backprop_mean_poolPfS_PiS0_ii
.p2align 3, 0x0
_Z18backprop_mean_poolPfS_PiS0_ii:
.quad _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.size _Z18backprop_mean_poolPfS_PiS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18backprop_mean_poolPfS_PiS0_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__backprop_mean_poolPfS_PiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18backprop_mean_poolPfS_PiS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | namespace nscv01{} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | namespace nscv01{} | .file "tmpxft_001717d4_00000000-6_CV01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | namespace nscv01{} | #pragma once
#include <hip/hip_runtime.h>
namespace nscv01{} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
namespace nscv01{} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
namespace nscv01{} | .text
.file "CV01.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001717d4_00000000-6_CV01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CV01.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float* var_10,float var_11,float var_12,float* var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29) {
if (comp == -1.8217E-35f - +1.8380E35f) {
float tmp_1 = (-1.3938E34f * (+1.3584E36f + (var_3 - var_4)));
float tmp_2 = (var_5 - var_6 + var_7 - var_8 - var_9 + +1.7052E-43f);
float tmp_3 = -1.4184E-37f;
comp += tmp_3 + tmp_2 - tmp_1 - -1.3002E35f + (-1.0984E-35f * -0.0f / -1.0064E-42f + -0.0f);
for (int i=0; i < var_1; ++i) {
var_10[i] = +1.6111E-43f;
comp += var_10[i] / (-1.2321E4f / var_11);
comp += (+1.1547E-42f - var_12 + logf(-1.3089E-35f + +1.2171E-37f));
}
for (int i=0; i < var_2; ++i) {
comp += (-1.6667E-3f - atan2f((-1.9244E3f + (+1.1787E-36f + var_14)), -0.0f));
var_13[i] = -1.0145E-37f;
comp += var_13[i] / var_15 + var_16 - +1.7152E-36f / coshf(expf(-0.0f / +1.8396E-36f * fabsf((var_17 / atan2f(-1.1384E-35f * (var_18 - (var_19 * -1.5425E34f)), +1.6398E-42f)))));
}
if (comp <= (+0.0f / (var_20 + (+1.5149E-37f - (var_21 - var_22))))) {
comp += (var_23 + var_24 + +1.9793E-29f - -1.6197E-36f + -1.5127E35f + var_25);
comp = var_26 / -1.2263E4f;
comp += (var_27 + (var_28 + var_29));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float* tmp_11 = initPointer( atof(argv[11]) );
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000db3ee_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
.type _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff, @function
_Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $392, %rsp
.cfi_def_cfa_offset 400
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm3, 40(%rsp)
movss %xmm4, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm7, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 400(%rsp), %rax
movq %rax, 216(%rsp)
leaq 408(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 464(%rsp), %rax
movq %rax, 288(%rsp)
leaq 472(%rsp), %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
leaq 520(%rsp), %rax
movq %rax, 344(%rsp)
leaq 528(%rsp), %rax
movq %rax, 352(%rsp)
leaq 536(%rsp), %rax
movq %rax, 360(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 408
pushq 72(%rsp)
.cfi_def_cfa_offset 416
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiifffffffPfffS_ffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 400
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff, .-_Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
.globl _Z7computefiifffffffPfffS_ffffffffffffffff
.type _Z7computefiifffffffPfffS_ffffffffffffffff, @function
_Z7computefiifffffffPfffS_ffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss 296(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiifffffffPfffS_ffffffffffffffff, .-_Z7computefiifffffffPfffS_ffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $240, %rsp
.cfi_def_cfa_offset 288
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 228(%rsp)
movl $1, 232(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 228(%rsp), %rdx
movl $1, %ecx
movq 216(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 200(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -144(%rsp), %rsp
.cfi_def_cfa_offset 432
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r14, %rcx
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 288(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 296(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 304(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 312(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 320(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 328(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 336(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
addq $144, %rsp
.cfi_def_cfa_offset 288
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiifffffffPfffS_ffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiifffffffPfffS_ffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float* var_10,float var_11,float var_12,float* var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29) {
if (comp == -1.8217E-35f - +1.8380E35f) {
float tmp_1 = (-1.3938E34f * (+1.3584E36f + (var_3 - var_4)));
float tmp_2 = (var_5 - var_6 + var_7 - var_8 - var_9 + +1.7052E-43f);
float tmp_3 = -1.4184E-37f;
comp += tmp_3 + tmp_2 - tmp_1 - -1.3002E35f + (-1.0984E-35f * -0.0f / -1.0064E-42f + -0.0f);
for (int i=0; i < var_1; ++i) {
var_10[i] = +1.6111E-43f;
comp += var_10[i] / (-1.2321E4f / var_11);
comp += (+1.1547E-42f - var_12 + logf(-1.3089E-35f + +1.2171E-37f));
}
for (int i=0; i < var_2; ++i) {
comp += (-1.6667E-3f - atan2f((-1.9244E3f + (+1.1787E-36f + var_14)), -0.0f));
var_13[i] = -1.0145E-37f;
comp += var_13[i] / var_15 + var_16 - +1.7152E-36f / coshf(expf(-0.0f / +1.8396E-36f * fabsf((var_17 / atan2f(-1.1384E-35f * (var_18 - (var_19 * -1.5425E34f)), +1.6398E-42f)))));
}
if (comp <= (+0.0f / (var_20 + (+1.5149E-37f - (var_21 - var_22))))) {
comp += (var_23 + var_24 + +1.9793E-29f - -1.6197E-36f + -1.5127E35f + var_25);
comp = var_26 / -1.2263E4f;
comp += (var_27 + (var_28 + var_29));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float* tmp_11 = initPointer( atof(argv[11]) );
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float* var_10,float var_11,float var_12,float* var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29) {
if (comp == -1.8217E-35f - +1.8380E35f) {
float tmp_1 = (-1.3938E34f * (+1.3584E36f + (var_3 - var_4)));
float tmp_2 = (var_5 - var_6 + var_7 - var_8 - var_9 + +1.7052E-43f);
float tmp_3 = -1.4184E-37f;
comp += tmp_3 + tmp_2 - tmp_1 - -1.3002E35f + (-1.0984E-35f * -0.0f / -1.0064E-42f + -0.0f);
for (int i=0; i < var_1; ++i) {
var_10[i] = +1.6111E-43f;
comp += var_10[i] / (-1.2321E4f / var_11);
comp += (+1.1547E-42f - var_12 + logf(-1.3089E-35f + +1.2171E-37f));
}
for (int i=0; i < var_2; ++i) {
comp += (-1.6667E-3f - atan2f((-1.9244E3f + (+1.1787E-36f + var_14)), -0.0f));
var_13[i] = -1.0145E-37f;
comp += var_13[i] / var_15 + var_16 - +1.7152E-36f / coshf(expf(-0.0f / +1.8396E-36f * fabsf((var_17 / atan2f(-1.1384E-35f * (var_18 - (var_19 * -1.5425E34f)), +1.6398E-42f)))));
}
if (comp <= (+0.0f / (var_20 + (+1.5149E-37f - (var_21 - var_22))))) {
comp += (var_23 + var_24 + +1.9793E-29f - -1.6197E-36f + -1.5127E35f + var_25);
comp = var_26 / -1.2263E4f;
comp += (var_27 + (var_28 + var_29));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float* tmp_11 = initPointer( atof(argv[11]) );
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float* var_10,float var_11,float var_12,float* var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29) {
if (comp == -1.8217E-35f - +1.8380E35f) {
float tmp_1 = (-1.3938E34f * (+1.3584E36f + (var_3 - var_4)));
float tmp_2 = (var_5 - var_6 + var_7 - var_8 - var_9 + +1.7052E-43f);
float tmp_3 = -1.4184E-37f;
comp += tmp_3 + tmp_2 - tmp_1 - -1.3002E35f + (-1.0984E-35f * -0.0f / -1.0064E-42f + -0.0f);
for (int i=0; i < var_1; ++i) {
var_10[i] = +1.6111E-43f;
comp += var_10[i] / (-1.2321E4f / var_11);
comp += (+1.1547E-42f - var_12 + logf(-1.3089E-35f + +1.2171E-37f));
}
for (int i=0; i < var_2; ++i) {
comp += (-1.6667E-3f - atan2f((-1.9244E3f + (+1.1787E-36f + var_14)), -0.0f));
var_13[i] = -1.0145E-37f;
comp += var_13[i] / var_15 + var_16 - +1.7152E-36f / coshf(expf(-0.0f / +1.8396E-36f * fabsf((var_17 / atan2f(-1.1384E-35f * (var_18 - (var_19 * -1.5425E34f)), +1.6398E-42f)))));
}
if (comp <= (+0.0f / (var_20 + (+1.5149E-37f - (var_21 - var_22))))) {
comp += (var_23 + var_24 + +1.9793E-29f - -1.6197E-36f + -1.5127E35f + var_25);
comp = var_26 / -1.2263E4f;
comp += (var_27 + (var_28 + var_29));
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float* tmp_11 = initPointer( atof(argv[11]) );
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff # -- Begin function _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff,@function
_Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff: # @_Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.cfi_startproc
# %bb.0:
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 368
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 368(%rsp), %rax
movq %rax, 200(%rsp)
leaq 376(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 384(%rsp), %rax
movq %rax, 224(%rsp)
leaq 392(%rsp), %rax
movq %rax, 232(%rsp)
leaq 400(%rsp), %rax
movq %rax, 240(%rsp)
leaq 408(%rsp), %rax
movq %rax, 248(%rsp)
leaq 416(%rsp), %rax
movq %rax, 256(%rsp)
leaq 424(%rsp), %rax
movq %rax, 264(%rsp)
leaq 432(%rsp), %rax
movq %rax, 272(%rsp)
leaq 440(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 488(%rsp), %rax
movq %rax, 328(%rsp)
leaq 496(%rsp), %rax
movq %rax, 336(%rsp)
leaq 504(%rsp), %rax
movq %rax, 344(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiifffffffPfffS_ffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $376, %rsp # imm = 0x178
.cfi_adjust_cfa_offset -376
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 152(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 96(%r15), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 152(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit64
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 240(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 136(%rsp)
movss %xmm9, 128(%rsp)
movss %xmm10, 120(%rsp)
movss %xmm11, 112(%rsp)
movss %xmm12, 104(%rsp)
movss %xmm13, 96(%rsp)
movss %xmm14, 88(%rsp)
movss %xmm15, 80(%rsp)
movss %xmm3, 72(%rsp)
movss %xmm4, 64(%rsp)
movss %xmm5, 56(%rsp)
movss %xmm6, 48(%rsp)
movss %xmm7, 40(%rsp)
movss 168(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 176(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 160(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 184(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 224(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 216(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 208(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 200(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 152(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
movq %r13, %rcx
callq _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiifffffffPfffS_ffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiifffffffPfffS_ffffffffffffffff,@object # @_Z7computefiifffffffPfffS_ffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiifffffffPfffS_ffffffffffffffff
.p2align 3, 0x0
_Z7computefiifffffffPfffS_ffffffffffffffff:
.quad _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.size _Z7computefiifffffffPfffS_ffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiifffffffPfffS_ffffffffffffffff"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiifffffffPfffS_ffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000db3ee_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
.type _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff, @function
_Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $392, %rsp
.cfi_def_cfa_offset 400
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm3, 40(%rsp)
movss %xmm4, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm7, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 400(%rsp), %rax
movq %rax, 216(%rsp)
leaq 408(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 464(%rsp), %rax
movq %rax, 288(%rsp)
leaq 472(%rsp), %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
leaq 520(%rsp), %rax
movq %rax, 344(%rsp)
leaq 528(%rsp), %rax
movq %rax, 352(%rsp)
leaq 536(%rsp), %rax
movq %rax, 360(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 408
pushq 72(%rsp)
.cfi_def_cfa_offset 416
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiifffffffPfffS_ffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 400
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff, .-_Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
.globl _Z7computefiifffffffPfffS_ffffffffffffffff
.type _Z7computefiifffffffPfffS_ffffffffffffffff, @function
_Z7computefiifffffffPfffS_ffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss 296(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiifffffffPfffS_ffffffffffffffff, .-_Z7computefiifffffffPfffS_ffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $240, %rsp
.cfi_def_cfa_offset 288
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 228(%rsp)
movl $1, 232(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 228(%rsp), %rdx
movl $1, %ecx
movq 216(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 200(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -144(%rsp), %rsp
.cfi_def_cfa_offset 432
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r14, %rcx
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 288(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 296(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 304(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 312(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 320(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 328(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 336(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z56__device_stub__Z7computefiifffffffPfffS_fffffffffffffffffiifffffffPfffS_ffffffffffffffff
addq $144, %rsp
.cfi_def_cfa_offset 288
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiifffffffPfffS_ffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiifffffffPfffS_ffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff # -- Begin function _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff,@function
_Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff: # @_Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.cfi_startproc
# %bb.0:
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 368
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 368(%rsp), %rax
movq %rax, 200(%rsp)
leaq 376(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 384(%rsp), %rax
movq %rax, 224(%rsp)
leaq 392(%rsp), %rax
movq %rax, 232(%rsp)
leaq 400(%rsp), %rax
movq %rax, 240(%rsp)
leaq 408(%rsp), %rax
movq %rax, 248(%rsp)
leaq 416(%rsp), %rax
movq %rax, 256(%rsp)
leaq 424(%rsp), %rax
movq %rax, 264(%rsp)
leaq 432(%rsp), %rax
movq %rax, 272(%rsp)
leaq 440(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 488(%rsp), %rax
movq %rax, 328(%rsp)
leaq 496(%rsp), %rax
movq %rax, 336(%rsp)
leaq 504(%rsp), %rax
movq %rax, 344(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiifffffffPfffS_ffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $376, %rsp # imm = 0x178
.cfi_adjust_cfa_offset -376
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 152(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 96(%r15), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 152(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit64
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 240(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 136(%rsp)
movss %xmm9, 128(%rsp)
movss %xmm10, 120(%rsp)
movss %xmm11, 112(%rsp)
movss %xmm12, 104(%rsp)
movss %xmm13, 96(%rsp)
movss %xmm14, 88(%rsp)
movss %xmm15, 80(%rsp)
movss %xmm3, 72(%rsp)
movss %xmm4, 64(%rsp)
movss %xmm5, 56(%rsp)
movss %xmm6, 48(%rsp)
movss %xmm7, 40(%rsp)
movss 168(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 176(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 160(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 184(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 224(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 216(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 208(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 200(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 152(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
movq %r13, %rcx
callq _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiifffffffPfffS_ffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiifffffffPfffS_ffffffffffffffff,@object # @_Z7computefiifffffffPfffS_ffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiifffffffPfffS_ffffffffffffffff
.p2align 3, 0x0
_Z7computefiifffffffPfffS_ffffffffffffffff:
.quad _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.size _Z7computefiifffffffPfffS_ffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiifffffffPfffS_ffffffffffffffff"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiifffffffPfffS_ffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiifffffffPfffS_ffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucket_sort(int* key, int* bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j = 0, k = 0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main()
{
int n = 50;
int range = 5;
int* key;
cudaMallocManaged(&key, n * sizeof(int));
for (int i = 0; i < n; i++) {
key[i] = rand() % range;
printf("%d ", key[i]);
}
printf("\n");
int* bucket;
cudaMallocManaged(&bucket, range * sizeof(int));
int M = 32;
bucket_sort <<<(n + M - 1) / M, M, range>>> (key, bucket, n);
cudaDeviceSynchronize();
for (int i = 0; i < n; i++)
printf("%d ", key[i]);
printf("\n");
cudaFree(key);
cudaFree(bucket);
} | code for sm_80
Function : _Z11bucket_sortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x004fca00078e020b */
/*00d0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.WIDE R4, R7.reuse, R11, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x040fe200078e020b */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ea000c101904 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc40007ffe0ff */
/*0160*/ IADD3 R9, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x004fc80007ffe0ff */
/*0170*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x120 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucket_sort(int* key, int* bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j = 0, k = 0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main()
{
int n = 50;
int range = 5;
int* key;
cudaMallocManaged(&key, n * sizeof(int));
for (int i = 0; i < n; i++) {
key[i] = rand() % range;
printf("%d ", key[i]);
}
printf("\n");
int* bucket;
cudaMallocManaged(&bucket, range * sizeof(int));
int M = 32;
bucket_sort <<<(n + M - 1) / M, M, range>>> (key, bucket, n);
cudaDeviceSynchronize();
for (int i = 0; i < n; i++)
printf("%d ", key[i]);
printf("\n");
cudaFree(key);
cudaFree(bucket);
} | .file "tmpxft_000b5c62_00000000-6_12.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11bucket_sortPiS_iPiS_i
.type _Z34__device_stub__Z11bucket_sortPiS_iPiS_i, @function
_Z34__device_stub__Z11bucket_sortPiS_iPiS_i:
.LFB2951:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11bucket_sortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2951:
.size _Z34__device_stub__Z11bucket_sortPiS_iPiS_i, .-_Z34__device_stub__Z11bucket_sortPiS_iPiS_i
.globl _Z11bucket_sortPiS_i
.type _Z11bucket_sortPiS_i, @function
_Z11bucket_sortPiS_i:
.LFB2952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11bucket_sortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2952:
.size _Z11bucket_sortPiS_i, .-_Z11bucket_sortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2926:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $200, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
movq (%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $20, %esi
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $5, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z11bucket_sortPiS_iPiS_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2926:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11bucket_sortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11bucket_sortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucket_sort(int* key, int* bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j = 0, k = 0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main()
{
int n = 50;
int range = 5;
int* key;
cudaMallocManaged(&key, n * sizeof(int));
for (int i = 0; i < n; i++) {
key[i] = rand() % range;
printf("%d ", key[i]);
}
printf("\n");
int* bucket;
cudaMallocManaged(&bucket, range * sizeof(int));
int M = 32;
bucket_sort <<<(n + M - 1) / M, M, range>>> (key, bucket, n);
cudaDeviceSynchronize();
for (int i = 0; i < n; i++)
printf("%d ", key[i]);
printf("\n");
cudaFree(key);
cudaFree(bucket);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucket_sort(int* key, int* bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j = 0, k = 0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main()
{
int n = 50;
int range = 5;
int* key;
hipMallocManaged(&key, n * sizeof(int));
for (int i = 0; i < n; i++) {
key[i] = rand() % range;
printf("%d ", key[i]);
}
printf("\n");
int* bucket;
hipMallocManaged(&bucket, range * sizeof(int));
int M = 32;
bucket_sort <<<(n + M - 1) / M, M, range>>> (key, bucket, n);
hipDeviceSynchronize();
for (int i = 0; i < n; i++)
printf("%d ", key[i]);
printf("\n");
hipFree(key);
hipFree(bucket);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucket_sort(int* key, int* bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j = 0, k = 0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main()
{
int n = 50;
int range = 5;
int* key;
hipMallocManaged(&key, n * sizeof(int));
for (int i = 0; i < n; i++) {
key[i] = rand() % range;
printf("%d ", key[i]);
}
printf("\n");
int* bucket;
hipMallocManaged(&bucket, range * sizeof(int));
int M = 32;
bucket_sort <<<(n + M - 1) / M, M, range>>> (key, bucket, n);
hipDeviceSynchronize();
for (int i = 0; i < n; i++)
printf("%d ", key[i]);
printf("\n");
hipFree(key);
hipFree(bucket);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11bucket_sortPiS_i
.globl _Z11bucket_sortPiS_i
.p2align 8
.type _Z11bucket_sortPiS_i,@function
_Z11bucket_sortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v1
global_atomic_add_u32 v[4:5], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s1
s_add_i32 s1, s1, 1
global_store_b32 v[2:3], v5, off
global_load_b32 v5, v4, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11bucket_sortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11bucket_sortPiS_i, .Lfunc_end0-_Z11bucket_sortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11bucket_sortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11bucket_sortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucket_sort(int* key, int* bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j = 0, k = 0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main()
{
int n = 50;
int range = 5;
int* key;
hipMallocManaged(&key, n * sizeof(int));
for (int i = 0; i < n; i++) {
key[i] = rand() % range;
printf("%d ", key[i]);
}
printf("\n");
int* bucket;
hipMallocManaged(&bucket, range * sizeof(int));
int M = 32;
bucket_sort <<<(n + M - 1) / M, M, range>>> (key, bucket, n);
hipDeviceSynchronize();
for (int i = 0; i < n; i++)
printf("%d ", key[i]);
printf("\n");
hipFree(key);
hipFree(bucket);
} | .text
.file "12.hip"
.globl _Z26__device_stub__bucket_sortPiS_i # -- Begin function _Z26__device_stub__bucket_sortPiS_i
.p2align 4, 0x90
.type _Z26__device_stub__bucket_sortPiS_i,@function
_Z26__device_stub__bucket_sortPiS_i: # @_Z26__device_stub__bucket_sortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11bucket_sortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__bucket_sortPiS_i, .Lfunc_end0-_Z26__device_stub__bucket_sortPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200, %esi
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $33, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%rbx,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $5, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11bucket_sortPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11bucket_sortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11bucket_sortPiS_i,@object # @_Z11bucket_sortPiS_i
.section .rodata,"a",@progbits
.globl _Z11bucket_sortPiS_i
.p2align 3, 0x0
_Z11bucket_sortPiS_i:
.quad _Z26__device_stub__bucket_sortPiS_i
.size _Z11bucket_sortPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11bucket_sortPiS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__bucket_sortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11bucket_sortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11bucket_sortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x004fca00078e020b */
/*00d0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.WIDE R4, R7.reuse, R11, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x040fe200078e020b */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ea000c101904 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc40007ffe0ff */
/*0160*/ IADD3 R9, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x004fc80007ffe0ff */
/*0170*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x120 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11bucket_sortPiS_i
.globl _Z11bucket_sortPiS_i
.p2align 8
.type _Z11bucket_sortPiS_i,@function
_Z11bucket_sortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v1
global_atomic_add_u32 v[4:5], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s1
s_add_i32 s1, s1, 1
global_store_b32 v[2:3], v5, off
global_load_b32 v5, v4, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11bucket_sortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11bucket_sortPiS_i, .Lfunc_end0-_Z11bucket_sortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11bucket_sortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11bucket_sortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b5c62_00000000-6_12.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11bucket_sortPiS_iPiS_i
.type _Z34__device_stub__Z11bucket_sortPiS_iPiS_i, @function
_Z34__device_stub__Z11bucket_sortPiS_iPiS_i:
.LFB2951:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11bucket_sortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2951:
.size _Z34__device_stub__Z11bucket_sortPiS_iPiS_i, .-_Z34__device_stub__Z11bucket_sortPiS_iPiS_i
.globl _Z11bucket_sortPiS_i
.type _Z11bucket_sortPiS_i, @function
_Z11bucket_sortPiS_i:
.LFB2952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11bucket_sortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2952:
.size _Z11bucket_sortPiS_i, .-_Z11bucket_sortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2926:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $200, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
movq (%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $20, %esi
call cudaMallocManaged@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $5, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z11bucket_sortPiS_iPiS_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2926:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11bucket_sortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11bucket_sortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "12.hip"
.globl _Z26__device_stub__bucket_sortPiS_i # -- Begin function _Z26__device_stub__bucket_sortPiS_i
.p2align 4, 0x90
.type _Z26__device_stub__bucket_sortPiS_i,@function
_Z26__device_stub__bucket_sortPiS_i: # @_Z26__device_stub__bucket_sortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11bucket_sortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__bucket_sortPiS_i, .Lfunc_end0-_Z26__device_stub__bucket_sortPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200, %esi
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $33, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%rbx,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $5, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11bucket_sortPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11bucket_sortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11bucket_sortPiS_i,@object # @_Z11bucket_sortPiS_i
.section .rodata,"a",@progbits
.globl _Z11bucket_sortPiS_i
.p2align 3, 0x0
_Z11bucket_sortPiS_i:
.quad _Z26__device_stub__bucket_sortPiS_i
.size _Z11bucket_sortPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11bucket_sortPiS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__bucket_sortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11bucket_sortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda_runtime.h>
__global__ void matrixMulKernel(float *C, float *A, float *B, int width, int height){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
if(tx >= width || ty >= height)
return;
float sum = 0;
for(int i=0; i<width; ++i){
sum += A[ty * width + i] * B[i * width + tx];
}
C[ty * width + tx] = sum;
}
void constantInit(float *data, int size, float val){
for (int i = 0; i < size; ++i){
//data[i] = val;
data[i] = rand() * 1.0 / (RAND_MAX);
}
}
void matrixMul(){
unsigned int width = 2;
unsigned int height = 2;
unsigned int size = width * height * sizeof(float);
float *h_A = (float*)malloc(size);
float *h_B = (float*)malloc(size);
float *h_C = (float*)malloc(size);
// Initialize host memory
const float valB = 0.01f;
constantInit(h_A, width*height, 1.0f);
constantInit(h_B, width*height, valB);
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
//copy host memory to device
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//config dims
dim3 block(16, 16);
// dim3 grid(width / block.x, height / block.y);
dim3 grid(1, 1);
// Excute the kernel
matrixMulKernel<<<grid, block>>>(d_C, d_A, d_B, width, height);
// Copy the memory from device to host
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("Checking computed result for correctness: \n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_A[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_B[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_C[i]);
}
printf("\n");
bool correct = true;
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6 ; // machine zero
for (int i = 0; i < width*height; i++){
double abs_err = fabs(h_C[i] - (width * valB));
double dot_length = width;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err/abs_val/dot_length ;
if (rel_err > eps)
{
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n", i, h_C[i], (float)(width*height), eps);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Free
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main(){
matrixMul();
} | code for sm_80
Function : _Z15matrixMulKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x170] ; /* 0x00005c0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda_runtime.h>
__global__ void matrixMulKernel(float *C, float *A, float *B, int width, int height){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
if(tx >= width || ty >= height)
return;
float sum = 0;
for(int i=0; i<width; ++i){
sum += A[ty * width + i] * B[i * width + tx];
}
C[ty * width + tx] = sum;
}
void constantInit(float *data, int size, float val){
for (int i = 0; i < size; ++i){
//data[i] = val;
data[i] = rand() * 1.0 / (RAND_MAX);
}
}
void matrixMul(){
unsigned int width = 2;
unsigned int height = 2;
unsigned int size = width * height * sizeof(float);
float *h_A = (float*)malloc(size);
float *h_B = (float*)malloc(size);
float *h_C = (float*)malloc(size);
// Initialize host memory
const float valB = 0.01f;
constantInit(h_A, width*height, 1.0f);
constantInit(h_B, width*height, valB);
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
//copy host memory to device
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//config dims
dim3 block(16, 16);
// dim3 grid(width / block.x, height / block.y);
dim3 grid(1, 1);
// Excute the kernel
matrixMulKernel<<<grid, block>>>(d_C, d_A, d_B, width, height);
// Copy the memory from device to host
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("Checking computed result for correctness: \n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_A[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_B[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_C[i]);
}
printf("\n");
bool correct = true;
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6 ; // machine zero
for (int i = 0; i < width*height; i++){
double abs_err = fabs(h_C[i] - (width * valB));
double dot_length = width;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err/abs_val/dot_length ;
if (rel_err > eps)
{
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n", i, h_C[i], (float)(width*height), eps);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Free
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main(){
matrixMul();
} | .file "tmpxft_0019650f_00000000-6_testmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12constantInitPfif
.type _Z12constantInitPfif, @function
_Z12constantInitPfif:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z12constantInitPfif, .-_Z12constantInitPfif
.globl _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
.type _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii, @function
_Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMulKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii, .-_Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
.globl _Z15matrixMulKernelPfS_S_ii
.type _Z15matrixMulKernelPfS_S_ii, @function
_Z15matrixMulKernelPfS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15matrixMulKernelPfS_S_ii, .-_Z15matrixMulKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Result = PASS"
.LC2:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Checking computed result for correctness: \n"
.section .rodata.str1.1
.LC6:
.string "%f "
.LC7:
.string "\n"
.section .rodata.str1.8
.align 8
.LC13:
.string "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.section .rodata.str1.1
.LC14:
.string "%s\n"
.text
.globl _Z9matrixMulv
.type _Z9matrixMulv, @function
_Z9matrixMulv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movss .LC3(%rip), %xmm0
movl $4, %esi
movq %r13, %rdi
call _Z12constantInitPfif
movss .LC4(%rip), %xmm0
movl $4, %esi
movq %r12, %rdi
call _Z12constantInitPfif
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 16(%r13), %r15
leaq .LC6(%rip), %r14
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L21
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 16(%r12), %r15
leaq .LC6(%rip), %r14
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L22
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 16(%rbp), %r15
leaq .LC6(%rip), %r14
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L23
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movl $1, %eax
jmp .L26
.L36:
movl $2, %r8d
movl $2, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
jmp .L20
.L24:
addq $1, %rbx
cmpq $4, %rbx
je .L37
.L26:
movss 0(%rbp,%rbx,4), %xmm0
movaps %xmm0, %xmm1
subss .LC8(%rip), %xmm1
andps .LC9(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
andps .LC9(%rip), %xmm2
cvtss2sd %xmm2, %xmm2
divsd %xmm2, %xmm1
mulsd .LC10(%rip), %xmm1
comisd .LC11(%rip), %xmm1
jbe .L24
cvtss2sd %xmm0, %xmm0
movsd .LC11(%rip), %xmm2
movsd .LC12(%rip), %xmm1
movl %ebx, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L24
.L37:
testb %al, %al
leaq .LC2(%rip), %rdx
leaq .LC1(%rip), %rax
cmovne %rax, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z9matrixMulv, .-_Z9matrixMulv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9matrixMulv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z15matrixMulKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1008981770
.align 4
.LC8:
.long 1017370378
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC10:
.long 0
.long 1071644672
.align 8
.LC11:
.long -1598689907
.long 1051772663
.align 8
.LC12:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda_runtime.h>
__global__ void matrixMulKernel(float *C, float *A, float *B, int width, int height){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
if(tx >= width || ty >= height)
return;
float sum = 0;
for(int i=0; i<width; ++i){
sum += A[ty * width + i] * B[i * width + tx];
}
C[ty * width + tx] = sum;
}
void constantInit(float *data, int size, float val){
for (int i = 0; i < size; ++i){
//data[i] = val;
data[i] = rand() * 1.0 / (RAND_MAX);
}
}
void matrixMul(){
unsigned int width = 2;
unsigned int height = 2;
unsigned int size = width * height * sizeof(float);
float *h_A = (float*)malloc(size);
float *h_B = (float*)malloc(size);
float *h_C = (float*)malloc(size);
// Initialize host memory
const float valB = 0.01f;
constantInit(h_A, width*height, 1.0f);
constantInit(h_B, width*height, valB);
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
//copy host memory to device
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//config dims
dim3 block(16, 16);
// dim3 grid(width / block.x, height / block.y);
dim3 grid(1, 1);
// Excute the kernel
matrixMulKernel<<<grid, block>>>(d_C, d_A, d_B, width, height);
// Copy the memory from device to host
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
printf("Checking computed result for correctness: \n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_A[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_B[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_C[i]);
}
printf("\n");
bool correct = true;
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6 ; // machine zero
for (int i = 0; i < width*height; i++){
double abs_err = fabs(h_C[i] - (width * valB));
double dot_length = width;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err/abs_val/dot_length ;
if (rel_err > eps)
{
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n", i, h_C[i], (float)(width*height), eps);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Free
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main(){
matrixMul();
} | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void matrixMulKernel(float *C, float *A, float *B, int width, int height){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
if(tx >= width || ty >= height)
return;
float sum = 0;
for(int i=0; i<width; ++i){
sum += A[ty * width + i] * B[i * width + tx];
}
C[ty * width + tx] = sum;
}
void constantInit(float *data, int size, float val){
for (int i = 0; i < size; ++i){
//data[i] = val;
data[i] = rand() * 1.0 / (RAND_MAX);
}
}
void matrixMul(){
unsigned int width = 2;
unsigned int height = 2;
unsigned int size = width * height * sizeof(float);
float *h_A = (float*)malloc(size);
float *h_B = (float*)malloc(size);
float *h_C = (float*)malloc(size);
// Initialize host memory
const float valB = 0.01f;
constantInit(h_A, width*height, 1.0f);
constantInit(h_B, width*height, valB);
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
//copy host memory to device
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//config dims
dim3 block(16, 16);
// dim3 grid(width / block.x, height / block.y);
dim3 grid(1, 1);
// Excute the kernel
matrixMulKernel<<<grid, block>>>(d_C, d_A, d_B, width, height);
// Copy the memory from device to host
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("Checking computed result for correctness: \n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_A[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_B[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_C[i]);
}
printf("\n");
bool correct = true;
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6 ; // machine zero
for (int i = 0; i < width*height; i++){
double abs_err = fabs(h_C[i] - (width * valB));
double dot_length = width;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err/abs_val/dot_length ;
if (rel_err > eps)
{
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n", i, h_C[i], (float)(width*height), eps);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Free
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main(){
matrixMul();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void matrixMulKernel(float *C, float *A, float *B, int width, int height){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
if(tx >= width || ty >= height)
return;
float sum = 0;
for(int i=0; i<width; ++i){
sum += A[ty * width + i] * B[i * width + tx];
}
C[ty * width + tx] = sum;
}
void constantInit(float *data, int size, float val){
for (int i = 0; i < size; ++i){
//data[i] = val;
data[i] = rand() * 1.0 / (RAND_MAX);
}
}
void matrixMul(){
unsigned int width = 2;
unsigned int height = 2;
unsigned int size = width * height * sizeof(float);
float *h_A = (float*)malloc(size);
float *h_B = (float*)malloc(size);
float *h_C = (float*)malloc(size);
// Initialize host memory
const float valB = 0.01f;
constantInit(h_A, width*height, 1.0f);
constantInit(h_B, width*height, valB);
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
//copy host memory to device
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//config dims
dim3 block(16, 16);
// dim3 grid(width / block.x, height / block.y);
dim3 grid(1, 1);
// Excute the kernel
matrixMulKernel<<<grid, block>>>(d_C, d_A, d_B, width, height);
// Copy the memory from device to host
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("Checking computed result for correctness: \n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_A[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_B[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_C[i]);
}
printf("\n");
bool correct = true;
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6 ; // machine zero
for (int i = 0; i < width*height; i++){
double abs_err = fabs(h_C[i] - (width * valB));
double dot_length = width;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err/abs_val/dot_length ;
if (rel_err > eps)
{
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n", i, h_C[i], (float)(width*height), eps);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Free
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main(){
matrixMul();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMulKernelPfS_S_ii
.globl _Z15matrixMulKernelPfS_S_ii
.p2align 8
.type _Z15matrixMulKernelPfS_S_ii,@function
_Z15matrixMulKernelPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s8
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMulKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMulKernelPfS_S_ii, .Lfunc_end0-_Z15matrixMulKernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMulKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMulKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void matrixMulKernel(float *C, float *A, float *B, int width, int height){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
if(tx >= width || ty >= height)
return;
float sum = 0;
for(int i=0; i<width; ++i){
sum += A[ty * width + i] * B[i * width + tx];
}
C[ty * width + tx] = sum;
}
void constantInit(float *data, int size, float val){
for (int i = 0; i < size; ++i){
//data[i] = val;
data[i] = rand() * 1.0 / (RAND_MAX);
}
}
void matrixMul(){
unsigned int width = 2;
unsigned int height = 2;
unsigned int size = width * height * sizeof(float);
float *h_A = (float*)malloc(size);
float *h_B = (float*)malloc(size);
float *h_C = (float*)malloc(size);
// Initialize host memory
const float valB = 0.01f;
constantInit(h_A, width*height, 1.0f);
constantInit(h_B, width*height, valB);
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
//copy host memory to device
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//config dims
dim3 block(16, 16);
// dim3 grid(width / block.x, height / block.y);
dim3 grid(1, 1);
// Excute the kernel
matrixMulKernel<<<grid, block>>>(d_C, d_A, d_B, width, height);
// Copy the memory from device to host
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
printf("Checking computed result for correctness: \n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_A[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_B[i]);
}
printf("\n");
for(int i = 0; i < width * height; i++){
printf("%f ", h_C[i]);
}
printf("\n");
bool correct = true;
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6 ; // machine zero
for (int i = 0; i < width*height; i++){
double abs_err = fabs(h_C[i] - (width * valB));
double dot_length = width;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err/abs_val/dot_length ;
if (rel_err > eps)
{
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n", i, h_C[i], (float)(width*height), eps);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Free
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main(){
matrixMul();
} | .text
.file "testmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__matrixMulKernelPfS_S_ii # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_ii
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPfS_S_ii,@function
_Z30__device_stub__matrixMulKernelPfS_S_ii: # @_Z30__device_stub__matrixMulKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMulKernelPfS_S_ii, .Lfunc_end0-_Z30__device_stub__matrixMulKernelPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12constantInitPfif
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z12constantInitPfif
.p2align 4, 0x90
.type _Z12constantInitPfif,@function
_Z12constantInitPfif: # @_Z12constantInitPfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12constantInitPfif, .Lfunc_end1-_Z12constantInitPfif
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9matrixMulv
.LCPI2_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI2_4:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI2_6:
.quad 0x4010000000000000 # double 4
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0xbca3d70a # float -0.0199999996
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI2_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z9matrixMulv
.p2align 4, 0x90
.type _Z9matrixMulv,@function
_Z9matrixMulv: # @_Z9matrixMulv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB2_1
# %bb.2: # %.lr.ph.i78.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i78
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB2_3
# %bb.4: # %_Z12constantInitPfif.exit82
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $2, 36(%rsp)
movl $2, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $16, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_11
# %bb.12:
movl $10, %edi
callq putchar@PLT
movb $1, %al
xorl %r12d, %r12d
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps .LCPI2_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN]
movaps .LCPI2_3(%rip), %xmm5 # xmm5 = [NaN,NaN]
movsd .LCPI2_4(%rip), %xmm6 # xmm6 = mem[0],zero
movsd .LCPI2_5(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
incq %r12
cmpq $4, %r12
je .LBB2_16
.LBB2_13: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addss %xmm3, %xmm1
andps %xmm4, %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm7
andps %xmm5, %xmm7
divsd %xmm7, %xmm1
mulsd %xmm6, %xmm1
ucomisd %xmm2, %xmm1
jbe .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
movsd .LCPI2_6(%rip), %xmm1 # xmm1 = mem[0],zero
movb $3, %al
callq printf
movsd .LCPI2_5(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_4(%rip), %xmm6 # xmm6 = mem[0],zero
movaps .LCPI2_3(%rip), %xmm5 # xmm5 = [NaN,NaN]
movaps .LCPI2_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorl %eax, %eax
jmp .LBB2_15
.LBB2_16:
testb $1, %al
movl $.L.str.6, %eax
movl $.L.str.5, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9matrixMulv, .Lfunc_end2-_Z9matrixMulv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9matrixMulv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMulKernelPfS_S_ii,@object # @_Z15matrixMulKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z15matrixMulKernelPfS_S_ii
.p2align 3, 0x0
_Z15matrixMulKernelPfS_S_ii:
.quad _Z30__device_stub__matrixMulKernelPfS_S_ii
.size _Z15matrixMulKernelPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.size .L.str.3, 55
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result = PASS"
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Result = FAIL"
.size .L.str.6, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMulKernelPfS_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Checking computed result for correctness: "
.size .Lstr, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMulKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMulKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrixMulKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x170] ; /* 0x00005c0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMulKernelPfS_S_ii
.globl _Z15matrixMulKernelPfS_S_ii
.p2align 8
.type _Z15matrixMulKernelPfS_S_ii,@function
_Z15matrixMulKernelPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v1, s8
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMulKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMulKernelPfS_S_ii, .Lfunc_end0-_Z15matrixMulKernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMulKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMulKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019650f_00000000-6_testmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12constantInitPfif
.type _Z12constantInitPfif, @function
_Z12constantInitPfif:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z12constantInitPfif, .-_Z12constantInitPfif
.globl _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
.type _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii, @function
_Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMulKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii, .-_Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
.globl _Z15matrixMulKernelPfS_S_ii
.type _Z15matrixMulKernelPfS_S_ii, @function
_Z15matrixMulKernelPfS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15matrixMulKernelPfS_S_ii, .-_Z15matrixMulKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Result = PASS"
.LC2:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Checking computed result for correctness: \n"
.section .rodata.str1.1
.LC6:
.string "%f "
.LC7:
.string "\n"
.section .rodata.str1.8
.align 8
.LC13:
.string "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.section .rodata.str1.1
.LC14:
.string "%s\n"
.text
.globl _Z9matrixMulv
.type _Z9matrixMulv, @function
_Z9matrixMulv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movss .LC3(%rip), %xmm0
movl $4, %esi
movq %r13, %rdi
call _Z12constantInitPfif
movss .LC4(%rip), %xmm0
movl $4, %esi
movq %r12, %rdi
call _Z12constantInitPfif
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 16(%r13), %r15
leaq .LC6(%rip), %r14
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L21
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 16(%r12), %r15
leaq .LC6(%rip), %r14
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L22
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 16(%rbp), %r15
leaq .LC6(%rip), %r14
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L23
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movl $1, %eax
jmp .L26
.L36:
movl $2, %r8d
movl $2, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
jmp .L20
.L24:
addq $1, %rbx
cmpq $4, %rbx
je .L37
.L26:
movss 0(%rbp,%rbx,4), %xmm0
movaps %xmm0, %xmm1
subss .LC8(%rip), %xmm1
andps .LC9(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
andps .LC9(%rip), %xmm2
cvtss2sd %xmm2, %xmm2
divsd %xmm2, %xmm1
mulsd .LC10(%rip), %xmm1
comisd .LC11(%rip), %xmm1
jbe .L24
cvtss2sd %xmm0, %xmm0
movsd .LC11(%rip), %xmm2
movsd .LC12(%rip), %xmm1
movl %ebx, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L24
.L37:
testb %al, %al
leaq .LC2(%rip), %rdx
leaq .LC1(%rip), %rax
cmovne %rax, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z9matrixMulv, .-_Z9matrixMulv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9matrixMulv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z15matrixMulKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1008981770
.align 4
.LC8:
.long 1017370378
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC10:
.long 0
.long 1071644672
.align 8
.LC11:
.long -1598689907
.long 1051772663
.align 8
.LC12:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__matrixMulKernelPfS_S_ii # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_ii
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPfS_S_ii,@function
_Z30__device_stub__matrixMulKernelPfS_S_ii: # @_Z30__device_stub__matrixMulKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMulKernelPfS_S_ii, .Lfunc_end0-_Z30__device_stub__matrixMulKernelPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12constantInitPfif
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z12constantInitPfif
.p2align 4, 0x90
.type _Z12constantInitPfif,@function
_Z12constantInitPfif: # @_Z12constantInitPfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12constantInitPfif, .Lfunc_end1-_Z12constantInitPfif
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9matrixMulv
.LCPI2_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI2_4:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI2_6:
.quad 0x4010000000000000 # double 4
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0xbca3d70a # float -0.0199999996
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI2_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z9matrixMulv
.p2align 4, 0x90
.type _Z9matrixMulv,@function
_Z9matrixMulv: # @_Z9matrixMulv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB2_1
# %bb.2: # %.lr.ph.i78.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i78
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB2_3
# %bb.4: # %_Z12constantInitPfif.exit82
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $2, 36(%rsp)
movl $2, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $16, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_11
# %bb.12:
movl $10, %edi
callq putchar@PLT
movb $1, %al
xorl %r12d, %r12d
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps .LCPI2_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN]
movaps .LCPI2_3(%rip), %xmm5 # xmm5 = [NaN,NaN]
movsd .LCPI2_4(%rip), %xmm6 # xmm6 = mem[0],zero
movsd .LCPI2_5(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
incq %r12
cmpq $4, %r12
je .LBB2_16
.LBB2_13: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addss %xmm3, %xmm1
andps %xmm4, %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm7
andps %xmm5, %xmm7
divsd %xmm7, %xmm1
mulsd %xmm6, %xmm1
ucomisd %xmm2, %xmm1
jbe .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
movsd .LCPI2_6(%rip), %xmm1 # xmm1 = mem[0],zero
movb $3, %al
callq printf
movsd .LCPI2_5(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_4(%rip), %xmm6 # xmm6 = mem[0],zero
movaps .LCPI2_3(%rip), %xmm5 # xmm5 = [NaN,NaN]
movaps .LCPI2_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorl %eax, %eax
jmp .LBB2_15
.LBB2_16:
testb $1, %al
movl $.L.str.6, %eax
movl $.L.str.5, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9matrixMulv, .Lfunc_end2-_Z9matrixMulv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9matrixMulv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMulKernelPfS_S_ii,@object # @_Z15matrixMulKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z15matrixMulKernelPfS_S_ii
.p2align 3, 0x0
_Z15matrixMulKernelPfS_S_ii:
.quad _Z30__device_stub__matrixMulKernelPfS_S_ii
.size _Z15matrixMulKernelPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.size .L.str.3, 55
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result = PASS"
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Result = FAIL"
.size .L.str.6, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMulKernelPfS_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Checking computed result for correctness: "
.size .Lstr, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMulKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMulKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
#include <iostream>
// nvcc -std=c++14 -O3 tarefa1.cu -o t1 && ./t1
int main()
{
int seed;
std::cin >> seed;
// default_random_engine is currently an alias for minstd_rand, and may change in a future version.
thrust::minstd_rand rng(seed);
// thrust::uniform_int_distribution<int> dist(-7, 13);
thrust::uniform_real_distribution<double> dist(25, 40);
for (int i = 0; i < 10; i++)
std::cout << dist(rng) << " ";
std::cout << "\n";
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
#include <iostream>
// nvcc -std=c++14 -O3 tarefa1.cu -o t1 && ./t1
int main()
{
int seed;
std::cin >> seed;
// default_random_engine is currently an alias for minstd_rand, and may change in a future version.
thrust::minstd_rand rng(seed);
// thrust::uniform_int_distribution<int> dist(-7, 13);
thrust::uniform_real_distribution<double> dist(25, 40);
for (int i = 0; i < 10; i++)
std::cout << dist(rng) << " ";
std::cout << "\n";
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
#include <iostream>
// nvcc -std=c++14 -O3 tarefa1.cu -o t1 && ./t1
int main()
{
int seed;
std::cin >> seed;
// default_random_engine is currently an alias for minstd_rand, and may change in a future version.
thrust::minstd_rand rng(seed);
// thrust::uniform_int_distribution<int> dist(-7, 13);
thrust::uniform_real_distribution<double> dist(25, 40);
for (int i = 0; i < 10; i++)
std::cout << dist(rng) << " ";
std::cout << "\n";
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
#include <iostream>
// nvcc -std=c++14 -O3 tarefa1.cu -o t1 && ./t1
int main()
{
int seed;
std::cin >> seed;
// default_random_engine is currently an alias for minstd_rand, and may change in a future version.
thrust::minstd_rand rng(seed);
// thrust::uniform_int_distribution<int> dist(-7, 13);
thrust::uniform_real_distribution<double> dist(25, 40);
for (int i = 0; i < 10; i++)
std::cout << dist(rng) << " ";
std::cout << "\n";
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random/uniform_real_distribution.h>
#include <iostream>
// nvcc -std=c++14 -O3 tarefa1.cu -o t1 && ./t1
int main()
{
int seed;
std::cin >> seed;
// default_random_engine is currently an alias for minstd_rand, and may change in a future version.
thrust::minstd_rand rng(seed);
// thrust::uniform_int_distribution<int> dist(-7, 13);
thrust::uniform_real_distribution<double> dist(25, 40);
for (int i = 0; i < 10; i++)
std::cout << dist(rng) << " ";
std::cout << "\n";
} | .text
.file "tarefa1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41dfffffff800000 # double 2147483646
.LCPI0_1:
.quad 0x402e000000000000 # double 15
.LCPI0_2:
.quad 0x4039000000000000 # double 25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 12(%rsp), %eax
leaq (%rax,%rax,2), %rcx
shrq $32, %rcx
movl %eax, %edx
subl %ecx, %edx
shrl %edx
addl %ecx, %edx
shrl $30, %edx
movl %edx, %r15d
shll $31, %r15d
orl %edx, %r15d
leal (%rax,%r15), %ecx
cmpl $1, %ecx
adcl %eax, %r15d
movl $10, %ebx
movl $3163493265, %r14d # imm = 0xBC8F1391
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %r15d, %eax
imulq %r14, %rax
shrq $47, %rax
imull $44488, %eax, %ecx # imm = 0xADC8
subl %ecx, %r15d
imull $48271, %r15d, %ecx # imm = 0xBC8F
imull $3399, %eax, %eax # imm = 0xD47
movl %eax, %edx
xorl $2147483647, %edx # imm = 0x7FFFFFFF
movl %eax, %r15d
negl %r15d
cmpl %eax, %ecx
cmovbl %edx, %r15d
leal -1(%r15,%rcx), %eax
# kill: def $r15d killed $r15d killed $r15 def $r15
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addl %ecx, %r15d
divsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
addsd .LCPI0_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
decl %ebx
jne .LBB0_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// curand
#define N 100
#define T 4
void llenarMatriz(int*);
__global__ void multiplicacion( int *a, int *b, int *c ) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
c[j+i*N] = 0; // 4,194,303
for(int k=0 ; k < N ; k++ ){
c[j+i*N] += a[k+i*N] * b[j+k*N];
}
} | .file "tmpxft_0013f682_00000000-6_multiplicacion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_
.type _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_, @function
_Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14multiplicacionPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_, .-_Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_
.globl _Z14multiplicacionPiS_S_
.type _Z14multiplicacionPiS_S_, @function
_Z14multiplicacionPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14multiplicacionPiS_S_, .-_Z14multiplicacionPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14multiplicacionPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplicacionPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// curand
#define N 100
#define T 4
void llenarMatriz(int*);
__global__ void multiplicacion( int *a, int *b, int *c ) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
c[j+i*N] = 0; // 4,194,303
for(int k=0 ; k < N ; k++ ){
c[j+i*N] += a[k+i*N] * b[j+k*N];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// curand
#define N 100
#define T 4
void llenarMatriz(int*);
__global__ void multiplicacion( int *a, int *b, int *c ) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
c[j+i*N] = 0; // 4,194,303
for(int k=0 ; k < N ; k++ ){
c[j+i*N] += a[k+i*N] * b[j+k*N];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// curand
#define N 100
#define T 4
void llenarMatriz(int*);
__global__ void multiplicacion( int *a, int *b, int *c ) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
c[j+i*N] = 0; // 4,194,303
for(int k=0 ; k < N ; k++ ){
c[j+i*N] += a[k+i*N] * b[j+k*N];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplicacionPiS_S_
.globl _Z14multiplicacionPiS_S_
.p2align 8
.type _Z14multiplicacionPiS_S_,@function
_Z14multiplicacionPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_bfe_u32 v3, v0, 10, 10
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, 0x64
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, v0, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v8, vcc_lo
s_mov_b64 s[0:1], 0
global_store_b32 v[2:3], v4, off
.p2align 6
.LBB0_1:
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v7, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_nc_u32_e32 v0, 0x64, v0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x190
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v7
global_store_b32 v[2:3], v7, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplicacionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplicacionPiS_S_, .Lfunc_end0-_Z14multiplicacionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplicacionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14multiplicacionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// curand
#define N 100
#define T 4
void llenarMatriz(int*);
__global__ void multiplicacion( int *a, int *b, int *c ) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
c[j+i*N] = 0; // 4,194,303
for(int k=0 ; k < N ; k++ ){
c[j+i*N] += a[k+i*N] * b[j+k*N];
}
} | .text
.file "multiplicacion.hip"
.globl _Z29__device_stub__multiplicacionPiS_S_ # -- Begin function _Z29__device_stub__multiplicacionPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__multiplicacionPiS_S_,@function
_Z29__device_stub__multiplicacionPiS_S_: # @_Z29__device_stub__multiplicacionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14multiplicacionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__multiplicacionPiS_S_, .Lfunc_end0-_Z29__device_stub__multiplicacionPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplicacionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14multiplicacionPiS_S_,@object # @_Z14multiplicacionPiS_S_
.section .rodata,"a",@progbits
.globl _Z14multiplicacionPiS_S_
.p2align 3, 0x0
_Z14multiplicacionPiS_S_:
.quad _Z29__device_stub__multiplicacionPiS_S_
.size _Z14multiplicacionPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14multiplicacionPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplicacionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14multiplicacionPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f682_00000000-6_multiplicacion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_
.type _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_, @function
_Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14multiplicacionPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_, .-_Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_
.globl _Z14multiplicacionPiS_S_
.type _Z14multiplicacionPiS_S_, @function
_Z14multiplicacionPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14multiplicacionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14multiplicacionPiS_S_, .-_Z14multiplicacionPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14multiplicacionPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplicacionPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiplicacion.hip"
.globl _Z29__device_stub__multiplicacionPiS_S_ # -- Begin function _Z29__device_stub__multiplicacionPiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__multiplicacionPiS_S_,@function
_Z29__device_stub__multiplicacionPiS_S_: # @_Z29__device_stub__multiplicacionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14multiplicacionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__multiplicacionPiS_S_, .Lfunc_end0-_Z29__device_stub__multiplicacionPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplicacionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14multiplicacionPiS_S_,@object # @_Z14multiplicacionPiS_S_
.section .rodata,"a",@progbits
.globl _Z14multiplicacionPiS_S_
.p2align 3, 0x0
_Z14multiplicacionPiS_S_:
.quad _Z29__device_stub__multiplicacionPiS_S_
.size _Z14multiplicacionPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14multiplicacionPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplicacionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14multiplicacionPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* compile with: nvcc -O3 hw1.cu -o hw1 */
#include <stdio.h>
#include <sys/time.h>
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
#define IMG_HEIGHT 256
#define IMG_WIDTH 256
#define N_IMAGES 10000
#define HISTOGRAM_SIZE 256
#define THREADS_PER_BLOCK_SERIAL 1024
#define THREADS_PER_BLOCK_BULK 256
typedef unsigned char uchar;
#define CUDA_CHECK(f) do { \
cudaError_t e = f; \
if (e != cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n", __FILE__, __LINE__, cudaGetErrorString(e)); \
exit(1); \
} \
} while (0)
#define SQR(a) ((a) * (a))
void process_image(uchar *img_in, uchar *img_out) {
int histogram[256] = { 0 };
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
histogram[img_in[i]]++;
}
int cdf[256] = { 0 };
int hist_sum = 0;
for (int i = 0; i < 256; i++) {
hist_sum += histogram[i];
cdf[i] = hist_sum;
}
int cdf_min = 0;
for (int i = 0; i < 256; i++) {
if (cdf[i] != 0) {
cdf_min = cdf[i];
break;
}
}
uchar map[256] = { 0 };
for (int i = 0; i < 256; i++) {
int map_value = (float)(cdf[i] - cdf_min) / (IMG_WIDTH * IMG_HEIGHT - cdf_min) * 255;
map[i] = (uchar)map_value;
}
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
img_out[i] = map[img_in[i]];
}
}
double static inline get_time_msec(void) {
struct timeval t;
gettimeofday(&t, NULL);
return t.tv_sec * 1e+3 + t.tv_usec * 1e-3;
}
long long int distance_sqr_between_image_arrays(uchar *img_arr1, uchar *img_arr2) {
long long int distance_sqr = 0;
for (int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
distance_sqr += SQR(img_arr1[i] - img_arr2[i]);
}
return distance_sqr;
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////
__device__ int array_min_positive(int *arr, int len){
int tid = threadIdx.x;
__shared__ int min_arr[HISTOGRAM_SIZE];
if (tid < len) {
min_arr[tid] = arr[tid]; //copy the arr to preserve it
}
__syncthreads();
int half_size = len /2;
while (half_size >=1){
if (tid < half_size) {
bool change_flag = (min_arr[tid + half_size] > 0 && min_arr[tid]
> min_arr[tid + half_size] || min_arr[tid] == 0);
min_arr[tid] = change_flag * min_arr[tid + half_size] +
(!change_flag) * min_arr[tid];
}
__syncthreads();
half_size /=2;
}
return min_arr[0];
}
__device__ void prefix_sum(int *arr, int len){
int tid = threadIdx.x;
int increment;
for (int stride = 1; stride < len; stride *= 2) {
if (tid < len && tid >= stride) { // in case # threads bigger than array length
increment = arr[tid - stride];
}
__syncthreads();
if (tid < len && tid >= stride) { // in case # threads bigger than array length
arr[tid] += increment;
}
__syncthreads();
}
return;
}
__device__ void map(int *cdf, int cdfMin, uchar* mapOut, int len){
int tid = threadIdx.x;
if (tid < len) {
int map_value = (float)(cdf[tid] - cdfMin) / (IMG_WIDTH * IMG_HEIGHT - cdfMin) * 255;
mapOut[tid] =(uchar)map_value;
}
return;
}
__global__ void process_image_kernel(uchar *in, uchar *out) {
int tid = threadIdx.x;
int imageStartIndex = IMG_WIDTH * IMG_HEIGHT * blockIdx.x;
__shared__ int hist_shared[HISTOGRAM_SIZE];
__shared__ uchar mapOut[HISTOGRAM_SIZE];
if (tid < HISTOGRAM_SIZE) {
hist_shared[tid] = 0;
}
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
atomicAdd(hist_shared + pixelValue, 1);
}
__syncthreads();
prefix_sum(hist_shared, HISTOGRAM_SIZE);
__syncthreads();
int * cdf = hist_shared;
int cdfMin = array_min_positive(cdf, HISTOGRAM_SIZE);
__syncthreads();
map(cdf, cdfMin, mapOut, HISTOGRAM_SIZE);
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
out[imageStartIndex + startOffset + tid] = mapOut[pixelValue];
}
return;
}
int main() {
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
uchar *images_in;
uchar *images_out_cpu; //output of CPU computation. In CPU memory.
uchar *images_out_gpu_serial; //output of GPU task serial computation. In CPU memory.
uchar *images_out_gpu_bulk; //output of GPU bulk computation. In CPU memory.
CUDA_CHECK( cudaHostAlloc(&images_in, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( cudaHostAlloc(&images_out_cpu, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( cudaHostAlloc(&images_out_gpu_serial, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( cudaHostAlloc(&images_out_gpu_bulk, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
/* instead of loading real images, we'll load the arrays with random data */
srand(0);
for (long long int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
images_in[i] = rand() % 256;
}
double t_start, t_finish;
// CPU computation. For reference. Do not change
printf("\n=== CPU ===\n");
t_start = get_time_msec();
for (int i = 0; i < N_IMAGES; i++) {
uchar *img_in = &images_in[i * IMG_WIDTH * IMG_HEIGHT];
uchar *img_out = &images_out_cpu[i * IMG_WIDTH * IMG_HEIGHT];
process_image(img_in, img_out);
}
t_finish = get_time_msec();
printf("total time %f [msec]\n", t_finish - t_start);
long long int distance_sqr;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// GPU task serial computation
printf("\n=== GPU Task Serial ===\n"); //Do not change
uchar *image_in_device_serial, *image_out_device_serial;
/* allocating device memory for one image */
CUDA_CHECK(cudaMalloc((void **)&image_in_device_serial,IMG_HEIGHT * IMG_WIDTH ));
CUDA_CHECK(cudaMalloc((void **)&image_out_device_serial,IMG_HEIGHT * IMG_WIDTH ));
t_start = get_time_msec(); //Do not change
for (int i = 0; i < N_IMAGES; i++) {
int imageStartIndex = IMG_HEIGHT * IMG_WIDTH * i;
CUDA_CHECK(cudaMemcpy(image_in_device_serial, images_in + imageStartIndex,
IMG_HEIGHT * IMG_WIDTH,
cudaMemcpyHostToDevice));
process_image_kernel <<< 1, THREADS_PER_BLOCK_SERIAL >>> (image_in_device_serial, image_out_device_serial);
CUDA_CHECK(cudaMemcpy(images_out_gpu_serial + imageStartIndex, image_out_device_serial,
IMG_HEIGHT * IMG_WIDTH, cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
}
t_finish = get_time_msec(); //Do not change
/* free device memory for one image */
CUDA_CHECK(cudaFree(image_out_device_serial));
CUDA_CHECK(cudaFree(image_in_device_serial));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_serial); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
// GPU bulk
printf("\n=== GPU Bulk ===\n"); //Do not change
uchar *image_in_device_bulk, *image_out_device_bulk;
/* allocate device memory for all image */
CUDA_CHECK(cudaMalloc((void **)&image_in_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
CUDA_CHECK(cudaMalloc((void **)&image_out_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
t_start = get_time_msec(); //Do not change
CUDA_CHECK(cudaMemcpy(image_in_device_bulk, images_in, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, cudaMemcpyHostToDevice));
process_image_kernel <<< N_IMAGES, THREADS_PER_BLOCK_BULK >>> (image_in_device_bulk, image_out_device_bulk);
CUDA_CHECK(cudaMemcpy(images_out_gpu_bulk, image_out_device_bulk, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
t_finish = get_time_msec(); //Do not change
/* free device memory for all image */
CUDA_CHECK(cudaFree(image_out_device_bulk));
CUDA_CHECK(cudaFree(image_in_device_bulk));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_bulk); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
CUDA_CHECK(cudaFreeHost(images_out_gpu_bulk));
CUDA_CHECK(cudaFreeHost(images_out_gpu_serial));
CUDA_CHECK(cudaFreeHost(images_out_cpu));
CUDA_CHECK(cudaFreeHost(images_in));
return 0;
} | .file "tmpxft_0008a12c_00000000-6_hw1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL13get_time_msecv, @function
_ZL13get_time_msecv:
.LFB2058:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LC1(%rip), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L4
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL13get_time_msecv, .-_ZL13get_time_msecv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13process_imagePhS_
.type _Z13process_imagePhS_, @function
_Z13process_imagePhS_:
.LFB2057:
.cfi_startproc
endbr64
subq $2328, %rsp
.cfi_def_cfa_offset 2336
movq %rdi, %r8
movq %fs:40, %rax
movq %rax, 2312(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $128, %ecx
rep stosq
movq %r8, %rax
leaq 65536(%r8), %rcx
.L8:
movzbl (%rax), %edx
addl $1, (%rsp,%rdx,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L8
leaq 1024(%rsp), %rdi
movl $128, %ecx
movl $0, %eax
rep stosq
.L9:
addl (%rsp,%rax), %ecx
movl %ecx, 1024(%rsp,%rax)
addq $4, %rax
cmpq $1024, %rax
jne .L9
leaq 1024(%rsp), %rax
leaq 2048(%rsp), %rdx
.L11:
movl (%rax), %ecx
testl %ecx, %ecx
jne .L10
addq $4, %rax
cmpq %rdx, %rax
jne .L11
.L10:
movq $0, 2048(%rsp)
movq $0, 2056(%rsp)
movq $0, 2064(%rsp)
movq $0, 2072(%rsp)
movq $0, 2080(%rsp)
movq $0, 2088(%rsp)
movq $0, 2096(%rsp)
movq $0, 2104(%rsp)
movq $0, 2112(%rsp)
movq $0, 2120(%rsp)
movq $0, 2128(%rsp)
movq $0, 2136(%rsp)
movq $0, 2144(%rsp)
movq $0, 2152(%rsp)
movq $0, 2160(%rsp)
movq $0, 2168(%rsp)
movq $0, 2176(%rsp)
movq $0, 2184(%rsp)
movq $0, 2192(%rsp)
movq $0, 2200(%rsp)
movq $0, 2208(%rsp)
movq $0, 2216(%rsp)
movq $0, 2224(%rsp)
movq $0, 2232(%rsp)
movq $0, 2240(%rsp)
movq $0, 2248(%rsp)
movq $0, 2256(%rsp)
movq $0, 2264(%rsp)
movq $0, 2272(%rsp)
movq $0, 2280(%rsp)
movq $0, 2288(%rsp)
movq $0, 2296(%rsp)
movl $0, %eax
movl $65536, %edx
subl %ecx, %edx
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movss .LC2(%rip), %xmm1
.L12:
movl 1024(%rsp,%rax,4), %edx
subl %ecx, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
cvttss2sil %xmm0, %edx
movb %dl, 2048(%rsp,%rax)
addq $1, %rax
cmpq $256, %rax
jne .L12
movl $0, %eax
.L13:
movzbl (%r8,%rax), %edx
movzbl 2048(%rsp,%rdx), %edx
movb %dl, (%rsi,%rax)
addq $1, %rax
cmpq $65536, %rax
jne .L13
movq 2312(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $2328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z13process_imagePhS_, .-_Z13process_imagePhS_
.globl _Z33distance_sqr_between_image_arraysPhS_
.type _Z33distance_sqr_between_image_arraysPhS_, @function
_Z33distance_sqr_between_image_arraysPhS_:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %edx
movl $0, %ecx
.L23:
movzbl (%rdi,%rdx), %eax
movzbl (%rsi,%rdx), %r8d
subl %r8d, %eax
imull %eax, %eax
cltq
addq %rax, %rcx
addq $1, %rdx
cmpq $655360000, %rdx
jne .L23
movq %rcx, %rax
ret
.cfi_endproc
.LFE2059:
.size _Z33distance_sqr_between_image_arraysPhS_, .-_Z33distance_sqr_between_image_arraysPhS_
.globl _Z18array_min_positivePii
.type _Z18array_min_positivePii, @function
_Z18array_min_positivePii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z18array_min_positivePii, .-_Z18array_min_positivePii
.globl _Z10prefix_sumPii
.type _Z10prefix_sumPii, @function
_Z10prefix_sumPii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z10prefix_sumPii, .-_Z10prefix_sumPii
.globl _Z3mapPiiPhi
.type _Z3mapPiiPhi, @function
_Z3mapPiiPhi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z3mapPiiPhi, .-_Z3mapPiiPhi
.globl _Z42__device_stub__Z20process_image_kernelPhS_PhS_
.type _Z42__device_stub__Z20process_image_kernelPhS_PhS_, @function
_Z42__device_stub__Z20process_image_kernelPhS_PhS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20process_image_kernelPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z20process_image_kernelPhS_PhS_, .-_Z42__device_stub__Z20process_image_kernelPhS_PhS_
.globl _Z20process_image_kernelPhS_
.type _Z20process_image_kernelPhS_, @function
_Z20process_image_kernelPhS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20process_image_kernelPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z20process_image_kernelPhS_, .-_Z20process_image_kernelPhS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/idoyehe/Computational_Accelerators_and_Accelerated_Systems_046278/master/HW_1/hw1.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Cuda failure %s:%d: '%s'\n"
.LC5:
.string "\n=== CPU ===\n"
.LC6:
.string "total time %f [msec]\n"
.LC7:
.string "\n=== GPU Task Serial ===\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "total time %f [msec] distance from baseline %lld (should be zero)\n"
.section .rodata.str1.1
.LC9:
.string "\n=== GPU Bulk ===\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L70
leaq 24(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L71
leaq 32(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L72
leaq 40(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L73
movl $0, %edi
call srand@PLT
movl $0, %ebx
.L44:
call rand@PLT
cltd
shrl $24, %edx
addl %edx, %eax
movzbl %al, %eax
subl %edx, %eax
movq 16(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq $655360000, %rbx
jne .L44
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZL13get_time_msecv
movsd %xmm0, (%rsp)
movl $0, %ebx
.L45:
movq %rbx, %rsi
addq 24(%rsp), %rsi
movq %rbx, %rdi
addq 16(%rsp), %rdi
call _Z13process_imagePhS_
addq $65536, %rbx
cmpq $655360000, %rbx
jne .L45
call _ZL13get_time_msecv
subsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L74
leaq 56(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L75
call _ZL13get_time_msecv
movsd %xmm0, (%rsp)
movl $0, %ebx
jmp .L51
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $154, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $155, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $156, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $157, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $186, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $187, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $192, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movq %rbx, %rdi
addq 32(%rsp), %rdi
movl $2, %ecx
movl $65536, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L76
call cudaDeviceSynchronize@PLT
addq $65536, %rbx
cmpq $655360000, %rbx
je .L77
.L51:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movl $1, %ecx
movl $65536, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L78
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z42__device_stub__Z20process_image_kernelPhS_PhS_
jmp .L49
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $196, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
call _ZL13get_time_msecv
movsd %xmm0, 8(%rsp)
movq 56(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L79
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L80
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33distance_sqr_between_image_arraysPhS_
movq %rax, %rdx
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $655360000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L81
leaq 72(%rsp), %rdi
movl $655360000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L82
call _ZL13get_time_msecv
movsd %xmm0, (%rsp)
movl $1, %ecx
movl $655360000, %edx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L83
movl $256, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $10000, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L57:
movl $2, %ecx
movl $655360000, %edx
movq 72(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L85
call cudaDeviceSynchronize@PLT
call _ZL13get_time_msecv
movsd %xmm0, 8(%rsp)
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L86
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L87
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33distance_sqr_between_image_arraysPhS_
movq %rax, %rdx
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L88
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L89
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L90
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L91
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L92
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $203, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $204, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $213, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $214, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $217, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L84:
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z42__device_stub__Z20process_image_kernelPhS_PhS_
jmp .L57
.L85:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $219, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $224, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $225, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $229, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $230, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $231, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $232, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z20process_image_kernelPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z20process_image_kernelPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1132396544
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* compile with: nvcc -O3 hw1.cu -o hw1 */
#include <stdio.h>
#include <sys/time.h>
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
#define IMG_HEIGHT 256
#define IMG_WIDTH 256
#define N_IMAGES 10000
#define HISTOGRAM_SIZE 256
#define THREADS_PER_BLOCK_SERIAL 1024
#define THREADS_PER_BLOCK_BULK 256
typedef unsigned char uchar;
#define CUDA_CHECK(f) do { \
cudaError_t e = f; \
if (e != cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n", __FILE__, __LINE__, cudaGetErrorString(e)); \
exit(1); \
} \
} while (0)
#define SQR(a) ((a) * (a))
void process_image(uchar *img_in, uchar *img_out) {
int histogram[256] = { 0 };
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
histogram[img_in[i]]++;
}
int cdf[256] = { 0 };
int hist_sum = 0;
for (int i = 0; i < 256; i++) {
hist_sum += histogram[i];
cdf[i] = hist_sum;
}
int cdf_min = 0;
for (int i = 0; i < 256; i++) {
if (cdf[i] != 0) {
cdf_min = cdf[i];
break;
}
}
uchar map[256] = { 0 };
for (int i = 0; i < 256; i++) {
int map_value = (float)(cdf[i] - cdf_min) / (IMG_WIDTH * IMG_HEIGHT - cdf_min) * 255;
map[i] = (uchar)map_value;
}
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
img_out[i] = map[img_in[i]];
}
}
double static inline get_time_msec(void) {
struct timeval t;
gettimeofday(&t, NULL);
return t.tv_sec * 1e+3 + t.tv_usec * 1e-3;
}
long long int distance_sqr_between_image_arrays(uchar *img_arr1, uchar *img_arr2) {
long long int distance_sqr = 0;
for (int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
distance_sqr += SQR(img_arr1[i] - img_arr2[i]);
}
return distance_sqr;
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////
__device__ int array_min_positive(int *arr, int len){
int tid = threadIdx.x;
__shared__ int min_arr[HISTOGRAM_SIZE];
if (tid < len) {
min_arr[tid] = arr[tid]; //copy the arr to preserve it
}
__syncthreads();
int half_size = len /2;
while (half_size >=1){
if (tid < half_size) {
bool change_flag = (min_arr[tid + half_size] > 0 && min_arr[tid]
> min_arr[tid + half_size] || min_arr[tid] == 0);
min_arr[tid] = change_flag * min_arr[tid + half_size] +
(!change_flag) * min_arr[tid];
}
__syncthreads();
half_size /=2;
}
return min_arr[0];
}
__device__ void prefix_sum(int *arr, int len){
int tid = threadIdx.x;
int increment;
for (int stride = 1; stride < len; stride *= 2) {
if (tid < len && tid >= stride) { // in case # threads bigger than array length
increment = arr[tid - stride];
}
__syncthreads();
if (tid < len && tid >= stride) { // in case # threads bigger than array length
arr[tid] += increment;
}
__syncthreads();
}
return;
}
__device__ void map(int *cdf, int cdfMin, uchar* mapOut, int len){
int tid = threadIdx.x;
if (tid < len) {
int map_value = (float)(cdf[tid] - cdfMin) / (IMG_WIDTH * IMG_HEIGHT - cdfMin) * 255;
mapOut[tid] =(uchar)map_value;
}
return;
}
__global__ void process_image_kernel(uchar *in, uchar *out) {
int tid = threadIdx.x;
int imageStartIndex = IMG_WIDTH * IMG_HEIGHT * blockIdx.x;
__shared__ int hist_shared[HISTOGRAM_SIZE];
__shared__ uchar mapOut[HISTOGRAM_SIZE];
if (tid < HISTOGRAM_SIZE) {
hist_shared[tid] = 0;
}
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
atomicAdd(hist_shared + pixelValue, 1);
}
__syncthreads();
prefix_sum(hist_shared, HISTOGRAM_SIZE);
__syncthreads();
int * cdf = hist_shared;
int cdfMin = array_min_positive(cdf, HISTOGRAM_SIZE);
__syncthreads();
map(cdf, cdfMin, mapOut, HISTOGRAM_SIZE);
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
out[imageStartIndex + startOffset + tid] = mapOut[pixelValue];
}
return;
}
int main() {
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
uchar *images_in;
uchar *images_out_cpu; //output of CPU computation. In CPU memory.
uchar *images_out_gpu_serial; //output of GPU task serial computation. In CPU memory.
uchar *images_out_gpu_bulk; //output of GPU bulk computation. In CPU memory.
CUDA_CHECK( cudaHostAlloc(&images_in, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( cudaHostAlloc(&images_out_cpu, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( cudaHostAlloc(&images_out_gpu_serial, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( cudaHostAlloc(&images_out_gpu_bulk, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
/* instead of loading real images, we'll load the arrays with random data */
srand(0);
for (long long int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
images_in[i] = rand() % 256;
}
double t_start, t_finish;
// CPU computation. For reference. Do not change
printf("\n=== CPU ===\n");
t_start = get_time_msec();
for (int i = 0; i < N_IMAGES; i++) {
uchar *img_in = &images_in[i * IMG_WIDTH * IMG_HEIGHT];
uchar *img_out = &images_out_cpu[i * IMG_WIDTH * IMG_HEIGHT];
process_image(img_in, img_out);
}
t_finish = get_time_msec();
printf("total time %f [msec]\n", t_finish - t_start);
long long int distance_sqr;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// GPU task serial computation
printf("\n=== GPU Task Serial ===\n"); //Do not change
uchar *image_in_device_serial, *image_out_device_serial;
/* allocating device memory for one image */
CUDA_CHECK(cudaMalloc((void **)&image_in_device_serial,IMG_HEIGHT * IMG_WIDTH ));
CUDA_CHECK(cudaMalloc((void **)&image_out_device_serial,IMG_HEIGHT * IMG_WIDTH ));
t_start = get_time_msec(); //Do not change
for (int i = 0; i < N_IMAGES; i++) {
int imageStartIndex = IMG_HEIGHT * IMG_WIDTH * i;
CUDA_CHECK(cudaMemcpy(image_in_device_serial, images_in + imageStartIndex,
IMG_HEIGHT * IMG_WIDTH,
cudaMemcpyHostToDevice));
process_image_kernel <<< 1, THREADS_PER_BLOCK_SERIAL >>> (image_in_device_serial, image_out_device_serial);
CUDA_CHECK(cudaMemcpy(images_out_gpu_serial + imageStartIndex, image_out_device_serial,
IMG_HEIGHT * IMG_WIDTH, cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
}
t_finish = get_time_msec(); //Do not change
/* free device memory for one image */
CUDA_CHECK(cudaFree(image_out_device_serial));
CUDA_CHECK(cudaFree(image_in_device_serial));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_serial); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
// GPU bulk
printf("\n=== GPU Bulk ===\n"); //Do not change
uchar *image_in_device_bulk, *image_out_device_bulk;
/* allocate device memory for all image */
CUDA_CHECK(cudaMalloc((void **)&image_in_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
CUDA_CHECK(cudaMalloc((void **)&image_out_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
t_start = get_time_msec(); //Do not change
CUDA_CHECK(cudaMemcpy(image_in_device_bulk, images_in, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, cudaMemcpyHostToDevice));
process_image_kernel <<< N_IMAGES, THREADS_PER_BLOCK_BULK >>> (image_in_device_bulk, image_out_device_bulk);
CUDA_CHECK(cudaMemcpy(images_out_gpu_bulk, image_out_device_bulk, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
t_finish = get_time_msec(); //Do not change
/* free device memory for all image */
CUDA_CHECK(cudaFree(image_out_device_bulk));
CUDA_CHECK(cudaFree(image_in_device_bulk));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_bulk); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
CUDA_CHECK(cudaFreeHost(images_out_gpu_bulk));
CUDA_CHECK(cudaFreeHost(images_out_gpu_serial));
CUDA_CHECK(cudaFreeHost(images_out_cpu));
CUDA_CHECK(cudaFreeHost(images_in));
return 0;
} | /* compile with: nvcc -O3 hw1.cu -o hw1 */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
#define IMG_HEIGHT 256
#define IMG_WIDTH 256
#define N_IMAGES 10000
#define HISTOGRAM_SIZE 256
#define THREADS_PER_BLOCK_SERIAL 1024
#define THREADS_PER_BLOCK_BULK 256
typedef unsigned char uchar;
#define CUDA_CHECK(f) do { \
hipError_t e = f; \
if (e != hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n", __FILE__, __LINE__, hipGetErrorString(e)); \
exit(1); \
} \
} while (0)
#define SQR(a) ((a) * (a))
void process_image(uchar *img_in, uchar *img_out) {
int histogram[256] = { 0 };
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
histogram[img_in[i]]++;
}
int cdf[256] = { 0 };
int hist_sum = 0;
for (int i = 0; i < 256; i++) {
hist_sum += histogram[i];
cdf[i] = hist_sum;
}
int cdf_min = 0;
for (int i = 0; i < 256; i++) {
if (cdf[i] != 0) {
cdf_min = cdf[i];
break;
}
}
uchar map[256] = { 0 };
for (int i = 0; i < 256; i++) {
int map_value = (float)(cdf[i] - cdf_min) / (IMG_WIDTH * IMG_HEIGHT - cdf_min) * 255;
map[i] = (uchar)map_value;
}
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
img_out[i] = map[img_in[i]];
}
}
double static inline get_time_msec(void) {
struct timeval t;
gettimeofday(&t, NULL);
return t.tv_sec * 1e+3 + t.tv_usec * 1e-3;
}
long long int distance_sqr_between_image_arrays(uchar *img_arr1, uchar *img_arr2) {
long long int distance_sqr = 0;
for (int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
distance_sqr += SQR(img_arr1[i] - img_arr2[i]);
}
return distance_sqr;
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////
__device__ int array_min_positive(int *arr, int len){
int tid = threadIdx.x;
__shared__ int min_arr[HISTOGRAM_SIZE];
if (tid < len) {
min_arr[tid] = arr[tid]; //copy the arr to preserve it
}
__syncthreads();
int half_size = len /2;
while (half_size >=1){
if (tid < half_size) {
bool change_flag = (min_arr[tid + half_size] > 0 && min_arr[tid]
> min_arr[tid + half_size] || min_arr[tid] == 0);
min_arr[tid] = change_flag * min_arr[tid + half_size] +
(!change_flag) * min_arr[tid];
}
__syncthreads();
half_size /=2;
}
return min_arr[0];
}
__device__ void prefix_sum(int *arr, int len){
int tid = threadIdx.x;
int increment;
for (int stride = 1; stride < len; stride *= 2) {
if (tid < len && tid >= stride) { // in case # threads bigger than array length
increment = arr[tid - stride];
}
__syncthreads();
if (tid < len && tid >= stride) { // in case # threads bigger than array length
arr[tid] += increment;
}
__syncthreads();
}
return;
}
__device__ void map(int *cdf, int cdfMin, uchar* mapOut, int len){
int tid = threadIdx.x;
if (tid < len) {
int map_value = (float)(cdf[tid] - cdfMin) / (IMG_WIDTH * IMG_HEIGHT - cdfMin) * 255;
mapOut[tid] =(uchar)map_value;
}
return;
}
__global__ void process_image_kernel(uchar *in, uchar *out) {
int tid = threadIdx.x;
int imageStartIndex = IMG_WIDTH * IMG_HEIGHT * blockIdx.x;
__shared__ int hist_shared[HISTOGRAM_SIZE];
__shared__ uchar mapOut[HISTOGRAM_SIZE];
if (tid < HISTOGRAM_SIZE) {
hist_shared[tid] = 0;
}
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
atomicAdd(hist_shared + pixelValue, 1);
}
__syncthreads();
prefix_sum(hist_shared, HISTOGRAM_SIZE);
__syncthreads();
int * cdf = hist_shared;
int cdfMin = array_min_positive(cdf, HISTOGRAM_SIZE);
__syncthreads();
map(cdf, cdfMin, mapOut, HISTOGRAM_SIZE);
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
out[imageStartIndex + startOffset + tid] = mapOut[pixelValue];
}
return;
}
int main() {
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
uchar *images_in;
uchar *images_out_cpu; //output of CPU computation. In CPU memory.
uchar *images_out_gpu_serial; //output of GPU task serial computation. In CPU memory.
uchar *images_out_gpu_bulk; //output of GPU bulk computation. In CPU memory.
CUDA_CHECK( hipHostAlloc(&images_in, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_cpu, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_gpu_serial, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_gpu_bulk, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
/* instead of loading real images, we'll load the arrays with random data */
srand(0);
for (long long int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
images_in[i] = rand() % 256;
}
double t_start, t_finish;
// CPU computation. For reference. Do not change
printf("\n=== CPU ===\n");
t_start = get_time_msec();
for (int i = 0; i < N_IMAGES; i++) {
uchar *img_in = &images_in[i * IMG_WIDTH * IMG_HEIGHT];
uchar *img_out = &images_out_cpu[i * IMG_WIDTH * IMG_HEIGHT];
process_image(img_in, img_out);
}
t_finish = get_time_msec();
printf("total time %f [msec]\n", t_finish - t_start);
long long int distance_sqr;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// GPU task serial computation
printf("\n=== GPU Task Serial ===\n"); //Do not change
uchar *image_in_device_serial, *image_out_device_serial;
/* allocating device memory for one image */
CUDA_CHECK(hipMalloc((void **)&image_in_device_serial,IMG_HEIGHT * IMG_WIDTH ));
CUDA_CHECK(hipMalloc((void **)&image_out_device_serial,IMG_HEIGHT * IMG_WIDTH ));
t_start = get_time_msec(); //Do not change
for (int i = 0; i < N_IMAGES; i++) {
int imageStartIndex = IMG_HEIGHT * IMG_WIDTH * i;
CUDA_CHECK(hipMemcpy(image_in_device_serial, images_in + imageStartIndex,
IMG_HEIGHT * IMG_WIDTH,
hipMemcpyHostToDevice));
process_image_kernel <<< 1, THREADS_PER_BLOCK_SERIAL >>> (image_in_device_serial, image_out_device_serial);
CUDA_CHECK(hipMemcpy(images_out_gpu_serial + imageStartIndex, image_out_device_serial,
IMG_HEIGHT * IMG_WIDTH, hipMemcpyDeviceToHost));
hipDeviceSynchronize();
}
t_finish = get_time_msec(); //Do not change
/* free device memory for one image */
CUDA_CHECK(hipFree(image_out_device_serial));
CUDA_CHECK(hipFree(image_in_device_serial));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_serial); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
// GPU bulk
printf("\n=== GPU Bulk ===\n"); //Do not change
uchar *image_in_device_bulk, *image_out_device_bulk;
/* allocate device memory for all image */
CUDA_CHECK(hipMalloc((void **)&image_in_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
CUDA_CHECK(hipMalloc((void **)&image_out_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
t_start = get_time_msec(); //Do not change
CUDA_CHECK(hipMemcpy(image_in_device_bulk, images_in, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, hipMemcpyHostToDevice));
process_image_kernel <<< N_IMAGES, THREADS_PER_BLOCK_BULK >>> (image_in_device_bulk, image_out_device_bulk);
CUDA_CHECK(hipMemcpy(images_out_gpu_bulk, image_out_device_bulk, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, hipMemcpyDeviceToHost));
hipDeviceSynchronize();
t_finish = get_time_msec(); //Do not change
/* free device memory for all image */
CUDA_CHECK(hipFree(image_out_device_bulk));
CUDA_CHECK(hipFree(image_in_device_bulk));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_bulk); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
CUDA_CHECK(hipHostFree(images_out_gpu_bulk));
CUDA_CHECK(hipHostFree(images_out_gpu_serial));
CUDA_CHECK(hipHostFree(images_out_cpu));
CUDA_CHECK(hipHostFree(images_in));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* compile with: nvcc -O3 hw1.cu -o hw1 */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
#define IMG_HEIGHT 256
#define IMG_WIDTH 256
#define N_IMAGES 10000
#define HISTOGRAM_SIZE 256
#define THREADS_PER_BLOCK_SERIAL 1024
#define THREADS_PER_BLOCK_BULK 256
typedef unsigned char uchar;
#define CUDA_CHECK(f) do { \
hipError_t e = f; \
if (e != hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n", __FILE__, __LINE__, hipGetErrorString(e)); \
exit(1); \
} \
} while (0)
#define SQR(a) ((a) * (a))
void process_image(uchar *img_in, uchar *img_out) {
int histogram[256] = { 0 };
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
histogram[img_in[i]]++;
}
int cdf[256] = { 0 };
int hist_sum = 0;
for (int i = 0; i < 256; i++) {
hist_sum += histogram[i];
cdf[i] = hist_sum;
}
int cdf_min = 0;
for (int i = 0; i < 256; i++) {
if (cdf[i] != 0) {
cdf_min = cdf[i];
break;
}
}
uchar map[256] = { 0 };
for (int i = 0; i < 256; i++) {
int map_value = (float)(cdf[i] - cdf_min) / (IMG_WIDTH * IMG_HEIGHT - cdf_min) * 255;
map[i] = (uchar)map_value;
}
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
img_out[i] = map[img_in[i]];
}
}
double static inline get_time_msec(void) {
struct timeval t;
gettimeofday(&t, NULL);
return t.tv_sec * 1e+3 + t.tv_usec * 1e-3;
}
long long int distance_sqr_between_image_arrays(uchar *img_arr1, uchar *img_arr2) {
long long int distance_sqr = 0;
for (int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
distance_sqr += SQR(img_arr1[i] - img_arr2[i]);
}
return distance_sqr;
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////
__device__ int array_min_positive(int *arr, int len){
int tid = threadIdx.x;
__shared__ int min_arr[HISTOGRAM_SIZE];
if (tid < len) {
min_arr[tid] = arr[tid]; //copy the arr to preserve it
}
__syncthreads();
int half_size = len /2;
while (half_size >=1){
if (tid < half_size) {
bool change_flag = (min_arr[tid + half_size] > 0 && min_arr[tid]
> min_arr[tid + half_size] || min_arr[tid] == 0);
min_arr[tid] = change_flag * min_arr[tid + half_size] +
(!change_flag) * min_arr[tid];
}
__syncthreads();
half_size /=2;
}
return min_arr[0];
}
__device__ void prefix_sum(int *arr, int len){
int tid = threadIdx.x;
int increment;
for (int stride = 1; stride < len; stride *= 2) {
if (tid < len && tid >= stride) { // in case # threads bigger than array length
increment = arr[tid - stride];
}
__syncthreads();
if (tid < len && tid >= stride) { // in case # threads bigger than array length
arr[tid] += increment;
}
__syncthreads();
}
return;
}
__device__ void map(int *cdf, int cdfMin, uchar* mapOut, int len){
int tid = threadIdx.x;
if (tid < len) {
int map_value = (float)(cdf[tid] - cdfMin) / (IMG_WIDTH * IMG_HEIGHT - cdfMin) * 255;
mapOut[tid] =(uchar)map_value;
}
return;
}
__global__ void process_image_kernel(uchar *in, uchar *out) {
int tid = threadIdx.x;
int imageStartIndex = IMG_WIDTH * IMG_HEIGHT * blockIdx.x;
__shared__ int hist_shared[HISTOGRAM_SIZE];
__shared__ uchar mapOut[HISTOGRAM_SIZE];
if (tid < HISTOGRAM_SIZE) {
hist_shared[tid] = 0;
}
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
atomicAdd(hist_shared + pixelValue, 1);
}
__syncthreads();
prefix_sum(hist_shared, HISTOGRAM_SIZE);
__syncthreads();
int * cdf = hist_shared;
int cdfMin = array_min_positive(cdf, HISTOGRAM_SIZE);
__syncthreads();
map(cdf, cdfMin, mapOut, HISTOGRAM_SIZE);
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
out[imageStartIndex + startOffset + tid] = mapOut[pixelValue];
}
return;
}
int main() {
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
uchar *images_in;
uchar *images_out_cpu; //output of CPU computation. In CPU memory.
uchar *images_out_gpu_serial; //output of GPU task serial computation. In CPU memory.
uchar *images_out_gpu_bulk; //output of GPU bulk computation. In CPU memory.
CUDA_CHECK( hipHostAlloc(&images_in, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_cpu, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_gpu_serial, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_gpu_bulk, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
/* instead of loading real images, we'll load the arrays with random data */
srand(0);
for (long long int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
images_in[i] = rand() % 256;
}
double t_start, t_finish;
// CPU computation. For reference. Do not change
printf("\n=== CPU ===\n");
t_start = get_time_msec();
for (int i = 0; i < N_IMAGES; i++) {
uchar *img_in = &images_in[i * IMG_WIDTH * IMG_HEIGHT];
uchar *img_out = &images_out_cpu[i * IMG_WIDTH * IMG_HEIGHT];
process_image(img_in, img_out);
}
t_finish = get_time_msec();
printf("total time %f [msec]\n", t_finish - t_start);
long long int distance_sqr;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// GPU task serial computation
printf("\n=== GPU Task Serial ===\n"); //Do not change
uchar *image_in_device_serial, *image_out_device_serial;
/* allocating device memory for one image */
CUDA_CHECK(hipMalloc((void **)&image_in_device_serial,IMG_HEIGHT * IMG_WIDTH ));
CUDA_CHECK(hipMalloc((void **)&image_out_device_serial,IMG_HEIGHT * IMG_WIDTH ));
t_start = get_time_msec(); //Do not change
for (int i = 0; i < N_IMAGES; i++) {
int imageStartIndex = IMG_HEIGHT * IMG_WIDTH * i;
CUDA_CHECK(hipMemcpy(image_in_device_serial, images_in + imageStartIndex,
IMG_HEIGHT * IMG_WIDTH,
hipMemcpyHostToDevice));
process_image_kernel <<< 1, THREADS_PER_BLOCK_SERIAL >>> (image_in_device_serial, image_out_device_serial);
CUDA_CHECK(hipMemcpy(images_out_gpu_serial + imageStartIndex, image_out_device_serial,
IMG_HEIGHT * IMG_WIDTH, hipMemcpyDeviceToHost));
hipDeviceSynchronize();
}
t_finish = get_time_msec(); //Do not change
/* free device memory for one image */
CUDA_CHECK(hipFree(image_out_device_serial));
CUDA_CHECK(hipFree(image_in_device_serial));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_serial); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
// GPU bulk
printf("\n=== GPU Bulk ===\n"); //Do not change
uchar *image_in_device_bulk, *image_out_device_bulk;
/* allocate device memory for all image */
CUDA_CHECK(hipMalloc((void **)&image_in_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
CUDA_CHECK(hipMalloc((void **)&image_out_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
t_start = get_time_msec(); //Do not change
CUDA_CHECK(hipMemcpy(image_in_device_bulk, images_in, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, hipMemcpyHostToDevice));
process_image_kernel <<< N_IMAGES, THREADS_PER_BLOCK_BULK >>> (image_in_device_bulk, image_out_device_bulk);
CUDA_CHECK(hipMemcpy(images_out_gpu_bulk, image_out_device_bulk, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, hipMemcpyDeviceToHost));
hipDeviceSynchronize();
t_finish = get_time_msec(); //Do not change
/* free device memory for all image */
CUDA_CHECK(hipFree(image_out_device_bulk));
CUDA_CHECK(hipFree(image_in_device_bulk));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_bulk); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
CUDA_CHECK(hipHostFree(images_out_gpu_bulk));
CUDA_CHECK(hipHostFree(images_out_gpu_serial));
CUDA_CHECK(hipHostFree(images_out_cpu));
CUDA_CHECK(hipHostFree(images_in));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20process_image_kernelPhS_
.globl _Z20process_image_kernelPhS_
.p2align 8
.type _Z20process_image_kernelPhS_,@function
_Z20process_image_kernelPhS_:
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2 offset:1024
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_lshl_b32 s3, s15, 16
v_mov_b32_e32 v1, 1
v_or_b32_e32 v2, s3, v0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s6, s2, 0xffff
.LBB0_3:
v_add_nc_u32_e32 v3, s7, v2
s_add_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmpk_gt_u32 s7, 0xffff
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v3, 2, v3
ds_add_u32 v3, v1 offset:1024
s_cbranch_scc0 .LBB0_3
v_cmp_lt_u32_e64 s2, 0xff, v0
v_lshl_add_u32 v1, v0, 2, 0x400
s_mov_b32 s7, 1
s_waitcnt lgkmcnt(0)
s_barrier
s_xor_b32 s6, s2, -1
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b32 s2, s7, 1
s_cmpk_lt_u32 s7, 0x80
s_mov_b32 s7, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_6:
v_cmp_le_u32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s6, s2
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_8
v_subrev_nc_u32_e32 v2, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v2, v2 offset:1024
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_5
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v2
ds_store_b32 v1, v3
s_branch .LBB0_5
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
ds_load_b32 v2, v1
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v2, 2, v0
s_movk_i32 s6, 0x80
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s10
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v3, v4, v3, s8
ds_store_b32 v2, v3
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s2, s6, 1
s_cmp_gt_u32 s6, 1
s_mov_b32 s6, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_20
.LBB0_15:
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_14
v_add_lshl_u32 v3, s6, v0, 2
s_mov_b32 s10, exec_lo
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s9, 1, v3
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB0_18
ds_load_b32 v4, v2
s_and_not1_b32 s9, s9, exec_lo
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e64 s2, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s9, s9, s2
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s10, s9
s_cbranch_execz .LBB0_13
ds_load_b32 v4, v2
s_and_not1_b32 s8, s8, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s8, s8, s2
s_branch .LBB0_13
.LBB0_20:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v2, 0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_22
ds_load_b32 v1, v1
v_sub_nc_u32_e32 v3, 0x10000, v2
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v3
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v1, v2, v1
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v3, v2, v1
v_mul_f32_e32 v1, 0x437f0000, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v1, v1
ds_store_b8 v0, v1 offset:2048
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v0, s3, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
.p2align 6
.LBB0_23:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s3, v0
s_add_i32 s3, s3, s2
s_cmpk_gt_u32 s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v4, vcc_lo
global_load_u8 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_load_u8 v5, v1 offset:2048
v_add_co_u32 v1, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b8 v[1:2], v5, off
s_cbranch_scc0 .LBB0_23
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20process_image_kernelPhS_
.amdhsa_group_segment_fixed_size 2304
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20process_image_kernelPhS_, .Lfunc_end0-_Z20process_image_kernelPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2304
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20process_image_kernelPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20process_image_kernelPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* compile with: nvcc -O3 hw1.cu -o hw1 */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
#define IMG_HEIGHT 256
#define IMG_WIDTH 256
#define N_IMAGES 10000
#define HISTOGRAM_SIZE 256
#define THREADS_PER_BLOCK_SERIAL 1024
#define THREADS_PER_BLOCK_BULK 256
typedef unsigned char uchar;
#define CUDA_CHECK(f) do { \
hipError_t e = f; \
if (e != hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n", __FILE__, __LINE__, hipGetErrorString(e)); \
exit(1); \
} \
} while (0)
#define SQR(a) ((a) * (a))
void process_image(uchar *img_in, uchar *img_out) {
int histogram[256] = { 0 };
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
histogram[img_in[i]]++;
}
int cdf[256] = { 0 };
int hist_sum = 0;
for (int i = 0; i < 256; i++) {
hist_sum += histogram[i];
cdf[i] = hist_sum;
}
int cdf_min = 0;
for (int i = 0; i < 256; i++) {
if (cdf[i] != 0) {
cdf_min = cdf[i];
break;
}
}
uchar map[256] = { 0 };
for (int i = 0; i < 256; i++) {
int map_value = (float)(cdf[i] - cdf_min) / (IMG_WIDTH * IMG_HEIGHT - cdf_min) * 255;
map[i] = (uchar)map_value;
}
for (int i = 0; i < IMG_WIDTH * IMG_HEIGHT; i++) {
img_out[i] = map[img_in[i]];
}
}
double static inline get_time_msec(void) {
struct timeval t;
gettimeofday(&t, NULL);
return t.tv_sec * 1e+3 + t.tv_usec * 1e-3;
}
long long int distance_sqr_between_image_arrays(uchar *img_arr1, uchar *img_arr2) {
long long int distance_sqr = 0;
for (int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
distance_sqr += SQR(img_arr1[i] - img_arr2[i]);
}
return distance_sqr;
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////
__device__ int array_min_positive(int *arr, int len){
int tid = threadIdx.x;
__shared__ int min_arr[HISTOGRAM_SIZE];
if (tid < len) {
min_arr[tid] = arr[tid]; //copy the arr to preserve it
}
__syncthreads();
int half_size = len /2;
while (half_size >=1){
if (tid < half_size) {
bool change_flag = (min_arr[tid + half_size] > 0 && min_arr[tid]
> min_arr[tid + half_size] || min_arr[tid] == 0);
min_arr[tid] = change_flag * min_arr[tid + half_size] +
(!change_flag) * min_arr[tid];
}
__syncthreads();
half_size /=2;
}
return min_arr[0];
}
__device__ void prefix_sum(int *arr, int len){
int tid = threadIdx.x;
int increment;
for (int stride = 1; stride < len; stride *= 2) {
if (tid < len && tid >= stride) { // in case # threads bigger than array length
increment = arr[tid - stride];
}
__syncthreads();
if (tid < len && tid >= stride) { // in case # threads bigger than array length
arr[tid] += increment;
}
__syncthreads();
}
return;
}
__device__ void map(int *cdf, int cdfMin, uchar* mapOut, int len){
int tid = threadIdx.x;
if (tid < len) {
int map_value = (float)(cdf[tid] - cdfMin) / (IMG_WIDTH * IMG_HEIGHT - cdfMin) * 255;
mapOut[tid] =(uchar)map_value;
}
return;
}
__global__ void process_image_kernel(uchar *in, uchar *out) {
int tid = threadIdx.x;
int imageStartIndex = IMG_WIDTH * IMG_HEIGHT * blockIdx.x;
__shared__ int hist_shared[HISTOGRAM_SIZE];
__shared__ uchar mapOut[HISTOGRAM_SIZE];
if (tid < HISTOGRAM_SIZE) {
hist_shared[tid] = 0;
}
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
atomicAdd(hist_shared + pixelValue, 1);
}
__syncthreads();
prefix_sum(hist_shared, HISTOGRAM_SIZE);
__syncthreads();
int * cdf = hist_shared;
int cdfMin = array_min_positive(cdf, HISTOGRAM_SIZE);
__syncthreads();
map(cdf, cdfMin, mapOut, HISTOGRAM_SIZE);
__syncthreads();
for(int startOffset = 0; startOffset < IMG_WIDTH * IMG_HEIGHT; startOffset += blockDim.x){
int pixelValue = in[imageStartIndex + startOffset + tid];
out[imageStartIndex + startOffset + tid] = mapOut[pixelValue];
}
return;
}
int main() {
///////////////////////////////////////////////// DO NOT CHANGE ///////////////////////////////////////
uchar *images_in;
uchar *images_out_cpu; //output of CPU computation. In CPU memory.
uchar *images_out_gpu_serial; //output of GPU task serial computation. In CPU memory.
uchar *images_out_gpu_bulk; //output of GPU bulk computation. In CPU memory.
CUDA_CHECK( hipHostAlloc(&images_in, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_cpu, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_gpu_serial, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
CUDA_CHECK( hipHostAlloc(&images_out_gpu_bulk, N_IMAGES * IMG_HEIGHT * IMG_WIDTH, 0) );
/* instead of loading real images, we'll load the arrays with random data */
srand(0);
for (long long int i = 0; i < N_IMAGES * IMG_WIDTH * IMG_HEIGHT; i++) {
images_in[i] = rand() % 256;
}
double t_start, t_finish;
// CPU computation. For reference. Do not change
printf("\n=== CPU ===\n");
t_start = get_time_msec();
for (int i = 0; i < N_IMAGES; i++) {
uchar *img_in = &images_in[i * IMG_WIDTH * IMG_HEIGHT];
uchar *img_out = &images_out_cpu[i * IMG_WIDTH * IMG_HEIGHT];
process_image(img_in, img_out);
}
t_finish = get_time_msec();
printf("total time %f [msec]\n", t_finish - t_start);
long long int distance_sqr;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
// GPU task serial computation
printf("\n=== GPU Task Serial ===\n"); //Do not change
uchar *image_in_device_serial, *image_out_device_serial;
/* allocating device memory for one image */
CUDA_CHECK(hipMalloc((void **)&image_in_device_serial,IMG_HEIGHT * IMG_WIDTH ));
CUDA_CHECK(hipMalloc((void **)&image_out_device_serial,IMG_HEIGHT * IMG_WIDTH ));
t_start = get_time_msec(); //Do not change
for (int i = 0; i < N_IMAGES; i++) {
int imageStartIndex = IMG_HEIGHT * IMG_WIDTH * i;
CUDA_CHECK(hipMemcpy(image_in_device_serial, images_in + imageStartIndex,
IMG_HEIGHT * IMG_WIDTH,
hipMemcpyHostToDevice));
process_image_kernel <<< 1, THREADS_PER_BLOCK_SERIAL >>> (image_in_device_serial, image_out_device_serial);
CUDA_CHECK(hipMemcpy(images_out_gpu_serial + imageStartIndex, image_out_device_serial,
IMG_HEIGHT * IMG_WIDTH, hipMemcpyDeviceToHost));
hipDeviceSynchronize();
}
t_finish = get_time_msec(); //Do not change
/* free device memory for one image */
CUDA_CHECK(hipFree(image_out_device_serial));
CUDA_CHECK(hipFree(image_in_device_serial));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_serial); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
// GPU bulk
printf("\n=== GPU Bulk ===\n"); //Do not change
uchar *image_in_device_bulk, *image_out_device_bulk;
/* allocate device memory for all image */
CUDA_CHECK(hipMalloc((void **)&image_in_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
CUDA_CHECK(hipMalloc((void **)&image_out_device_bulk,IMG_HEIGHT * IMG_WIDTH * N_IMAGES ));
t_start = get_time_msec(); //Do not change
CUDA_CHECK(hipMemcpy(image_in_device_bulk, images_in, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, hipMemcpyHostToDevice));
process_image_kernel <<< N_IMAGES, THREADS_PER_BLOCK_BULK >>> (image_in_device_bulk, image_out_device_bulk);
CUDA_CHECK(hipMemcpy(images_out_gpu_bulk, image_out_device_bulk, IMG_HEIGHT * IMG_WIDTH * N_IMAGES, hipMemcpyDeviceToHost));
hipDeviceSynchronize();
t_finish = get_time_msec(); //Do not change
/* free device memory for all image */
CUDA_CHECK(hipFree(image_out_device_bulk));
CUDA_CHECK(hipFree(image_in_device_bulk));
distance_sqr = distance_sqr_between_image_arrays(images_out_cpu, images_out_gpu_bulk); // Do not change
printf("total time %f [msec] distance from baseline %lld (should be zero)\n", t_finish - t_start, distance_sqr); //Do not change
CUDA_CHECK(hipHostFree(images_out_gpu_bulk));
CUDA_CHECK(hipHostFree(images_out_gpu_serial));
CUDA_CHECK(hipHostFree(images_out_cpu));
CUDA_CHECK(hipHostFree(images_in));
return 0;
} | .text
.file "hw1.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13process_imagePhS_
.LCPI0_0:
.long 0x437f0000 # float 255
.text
.globl _Z13process_imagePhS_
.p2align 4, 0x90
.type _Z13process_imagePhS_,@function
_Z13process_imagePhS_: # @_Z13process_imagePhS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $2304, %rsp # imm = 0x900
.cfi_def_cfa_offset 2336
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 1280(%rsp), %rdi
xorl %r15d, %r15d
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movzbl (%r14,%r15), %eax
incl 1280(%rsp,%rax,4)
incq %r15
cmpq $65536, %r15 # imm = 0x10000
jne .LBB0_1
# %bb.2:
leaq 256(%rsp), %rdi
xorl %r15d, %r15d
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
addl 1280(%rsp,%r15,4), %eax
movl %eax, 256(%rsp,%r15,4)
incq %r15
cmpq $256, %r15 # imm = 0x100
jne .LBB0_3
# %bb.4: # %.preheader33.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_5: # %.preheader33
# =>This Inner Loop Header: Depth=1
movl 256(%rsp,%rcx,4), %eax
testl %eax, %eax
jne .LBB0_8
# %bb.6: # in Loop: Header=BB0_5 Depth=1
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB0_5
# %bb.7:
xorl %eax, %eax
.LBB0_8:
xorps %xmm1, %xmm1
movaps %xmm1, 240(%rsp)
movaps %xmm1, 224(%rsp)
movaps %xmm1, 208(%rsp)
movaps %xmm1, 192(%rsp)
movaps %xmm1, 176(%rsp)
movaps %xmm1, 160(%rsp)
movaps %xmm1, 144(%rsp)
movaps %xmm1, 128(%rsp)
movaps %xmm1, 112(%rsp)
movaps %xmm1, 96(%rsp)
movaps %xmm1, 80(%rsp)
movaps %xmm1, 64(%rsp)
movaps %xmm1, 48(%rsp)
movaps %xmm1, 32(%rsp)
movl $65536, %ecx # imm = 0x10000
subl %eax, %ecx
cvtsi2ss %ecx, %xmm0
movaps %xmm1, 16(%rsp)
movaps %xmm1, (%rsp)
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movl 256(%rsp,%rcx,4), %edx
subl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
divss %xmm0, %xmm2
mulss %xmm1, %xmm2
cvttss2si %xmm2, %edx
movb %dl, (%rsp,%rcx)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB0_9
# %bb.10: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movzbl (%r14,%rax), %ecx
movzbl (%rsp,%rcx), %ecx
movb %cl, (%rbx,%rax)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB0_11
# %bb.12:
addq $2304, %rsp # imm = 0x900
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13process_imagePhS_, .Lfunc_end0-_Z13process_imagePhS_
.cfi_endproc
# -- End function
.globl _Z33distance_sqr_between_image_arraysPhS_ # -- Begin function _Z33distance_sqr_between_image_arraysPhS_
.p2align 4, 0x90
.type _Z33distance_sqr_between_image_arraysPhS_,@function
_Z33distance_sqr_between_image_arraysPhS_: # @_Z33distance_sqr_between_image_arraysPhS_
.cfi_startproc
# %bb.0:
xorl %ecx, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rcx), %edx
movzbl (%rsi,%rcx), %r8d
subl %r8d, %edx
imull %edx, %edx
addq %rdx, %rax
incq %rcx
cmpq $655360000, %rcx # imm = 0x27100000
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z33distance_sqr_between_image_arraysPhS_, .Lfunc_end1-_Z33distance_sqr_between_image_arraysPhS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__process_image_kernelPhS_ # -- Begin function _Z35__device_stub__process_image_kernelPhS_
.p2align 4, 0x90
.type _Z35__device_stub__process_image_kernelPhS_,@function
_Z35__device_stub__process_image_kernelPhS_: # @_Z35__device_stub__process_image_kernelPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20process_image_kernelPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z35__device_stub__process_image_kernelPhS_, .Lfunc_end2-_Z35__device_stub__process_image_kernelPhS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI3_2:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x437f0000 # float 255
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2440, %rsp # imm = 0x988
.cfi_def_cfa_offset 2496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 24(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 80(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_6
# %bb.7:
leaq 72(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_8
# %bb.9:
xorl %ebx, %ebx
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB3_10: # =>This Inner Loop Header: Depth=1
callq rand
movq 16(%rsp), %rcx
movb %al, (%rcx,%rbx)
incq %rbx
cmpq $655360000, %rbx # imm = 0x27100000
jne .LBB3_10
# %bb.11:
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 1408(%rsp), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_12: # =>This Loop Header: Depth=1
# Child Loop BB3_13 Depth 2
# Child Loop BB3_15 Depth 2
# Child Loop BB3_17 Depth 2
# Child Loop BB3_21 Depth 2
# Child Loop BB3_23 Depth 2
movq 16(%rsp), %r13
movq 24(%rsp), %rbp
movl $1024, %edx # imm = 0x400
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq memset@PLT
addq %r15, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_13: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r13,%rax), %ecx
incl 384(%rsp,%rcx,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB3_13
# %bb.14: # in Loop: Header=BB3_12 Depth=1
xorl %ebx, %ebx
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
addl 384(%rsp,%rbx,4), %eax
movl %eax, 1408(%rsp,%rbx,4)
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB3_15
# %bb.16: # %.preheader33.i.preheader
# in Loop: Header=BB3_12 Depth=1
xorl %ecx, %ecx
movss .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_17: # %.preheader33.i
# Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movl 1408(%rsp,%rcx,4), %eax
testl %eax, %eax
jne .LBB3_20
# %bb.18: # in Loop: Header=BB3_17 Depth=2
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB3_17
# %bb.19: # in Loop: Header=BB3_12 Depth=1
xorl %eax, %eax
.LBB3_20: # in Loop: Header=BB3_12 Depth=1
xorpd %xmm0, %xmm0
movapd %xmm0, 368(%rsp)
movapd %xmm0, 352(%rsp)
movapd %xmm0, 336(%rsp)
movapd %xmm0, 320(%rsp)
movapd %xmm0, 304(%rsp)
movapd %xmm0, 288(%rsp)
movapd %xmm0, 272(%rsp)
movapd %xmm0, 256(%rsp)
movapd %xmm0, 240(%rsp)
movapd %xmm0, 224(%rsp)
movapd %xmm0, 208(%rsp)
movapd %xmm0, 192(%rsp)
movapd %xmm0, 176(%rsp)
movapd %xmm0, 160(%rsp)
movapd %xmm0, 144(%rsp)
movapd %xmm0, 128(%rsp)
movl $65536, %ecx # imm = 0x10000
subl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_21: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movl 1408(%rsp,%rcx,4), %edx
subl %eax, %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
divss %xmm0, %xmm1
mulss %xmm2, %xmm1
cvttss2si %xmm1, %edx
movb %dl, 128(%rsp,%rcx)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB3_21
# %bb.22: # %.preheader.i.preheader
# in Loop: Header=BB3_12 Depth=1
addq %r15, %rbp
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_23: # %.preheader.i
# Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r13,%rax), %ecx
movzbl 128(%rsp,%rcx), %ecx
movb %cl, (%rbp,%rax)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB3_23
# %bb.24: # %_Z13process_imagePhS_.exit
# in Loop: Header=BB3_12 Depth=1
incq %r12
addq $65536, %r15 # imm = 0x10000
cmpq $10000, %r12 # imm = 0x2710
jne .LBB3_12
# %bb.25:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm0
addsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 384(%rsp), %xmm1
mulsd .LCPI3_2(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 64(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB3_26
# %bb.27:
leaq 56(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB3_28
# %bb.29:
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r12d, %r12d
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
mulsd .LCPI3_2(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 392(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
leaq 1023(%rbx), %r15
leaq 128(%rsp), %r13
leaq 96(%rsp), %rbp
leaq 88(%rsp), %r14
.p2align 4, 0x90
.LBB3_30: # =>This Inner Loop Header: Depth=1
movq 64(%rsp), %rdi
movq 16(%rsp), %rsi
addq %r12, %rsi
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_31
# %bb.32: # in Loop: Header=BB3_30 Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_34
# %bb.33: # in Loop: Header=BB3_30 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 384(%rsp)
leaq 104(%rsp), %rax
movq %rax, 392(%rsp)
leaq 1408(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 1408(%rsp), %rsi
movl 1416(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z20process_image_kernelPhS_, %edi
leaq 384(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_34: # in Loop: Header=BB3_30 Depth=1
movq 80(%rsp), %rdi
addq %r12, %rdi
movq 56(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_35
# %bb.36: # in Loop: Header=BB3_30 Depth=1
callq hipDeviceSynchronize
addq $65536, %r12 # imm = 0x10000
cmpq $655360000, %r12 # imm = 0x27100000
jne .LBB3_30
# %bb.37:
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_38
# %bb.39:
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_40
# %bb.41:
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
movq 80(%rsp), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_42: # =>This Inner Loop Header: Depth=1
movzbl (%rax,%rdx), %edi
movzbl (%rcx,%rdx), %r8d
subl %r8d, %edi
imull %edi, %edi
addq %rdi, %rsi
incq %rdx
cmpq $655360000, %rdx # imm = 0x27100000
jne .LBB3_42
# %bb.43: # %_Z33distance_sqr_between_image_arraysPhS_.exit
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
leaq 48(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
callq hipMalloc
testl %eax, %eax
jne .LBB3_44
# %bb.45:
leaq 40(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
callq hipMalloc
testl %eax, %eax
jne .LBB3_46
# %bb.47:
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi
movl $655360000, %edx # imm = 0x27100000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_48
# %bb.49:
leaq 255(%rbx), %rdx
addq $9999, %rbx # imm = 0x270F
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_51
# %bb.50:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 384(%rsp)
leaq 104(%rsp), %rax
movq %rax, 392(%rsp)
leaq 1408(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1408(%rsp), %rsi
movl 1416(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 384(%rsp), %r9
movl $_Z20process_image_kernelPhS_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_51:
movq 72(%rsp), %rdi
movq 40(%rsp), %rsi
movl $655360000, %edx # imm = 0x27100000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_52
# %bb.53:
callq hipDeviceSynchronize
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, 120(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_54
# %bb.55:
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_56
# %bb.57:
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm1
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm2
movsd 120(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm3
addsd %xmm1, %xmm2
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm3, %xmm0
movq 24(%rsp), %rax
movq 72(%rsp), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_58: # =>This Inner Loop Header: Depth=1
movzbl (%rax,%rdx), %edi
movzbl (%rcx,%rdx), %r8d
subl %r8d, %edi
imull %edi, %edi
addq %rdi, %rsi
incq %rdx
cmpq $655360000, %rdx # imm = 0x27100000
jne .LBB3_58
# %bb.59: # %_Z33distance_sqr_between_image_arraysPhS_.exit125
subsd %xmm2, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 72(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_60
# %bb.61:
movq 80(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_62
# %bb.63:
movq 24(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_64
# %bb.65:
movq 16(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_66
# %bb.67:
xorl %eax, %eax
addq $2440, %rsp # imm = 0x988
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_35:
.cfi_def_cfa_offset 2496
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $199, %edx
jmp .LBB3_2
.LBB3_31:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $196, %edx
.LBB3_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $156, %edx
jmp .LBB3_2
.LBB3_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $157, %edx
jmp .LBB3_2
.LBB3_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $158, %edx
jmp .LBB3_2
.LBB3_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $159, %edx
jmp .LBB3_2
.LBB3_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $188, %edx
jmp .LBB3_2
.LBB3_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $189, %edx
jmp .LBB3_2
.LBB3_38:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $205, %edx
jmp .LBB3_2
.LBB3_40:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $206, %edx
jmp .LBB3_2
.LBB3_44:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $215, %edx
jmp .LBB3_2
.LBB3_46:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $216, %edx
jmp .LBB3_2
.LBB3_48:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $219, %edx
jmp .LBB3_2
.LBB3_52:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $221, %edx
jmp .LBB3_2
.LBB3_54:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $226, %edx
jmp .LBB3_2
.LBB3_56:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $227, %edx
jmp .LBB3_2
.LBB3_60:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $231, %edx
jmp .LBB3_2
.LBB3_62:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $232, %edx
jmp .LBB3_2
.LBB3_64:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $233, %edx
jmp .LBB3_2
.LBB3_66:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $234, %edx
jmp .LBB3_2
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20process_image_kernelPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20process_image_kernelPhS_,@object # @_Z20process_image_kernelPhS_
.section .rodata,"a",@progbits
.globl _Z20process_image_kernelPhS_
.p2align 3, 0x0
_Z20process_image_kernelPhS_:
.quad _Z35__device_stub__process_image_kernelPhS_
.size _Z20process_image_kernelPhS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/idoyehe/Computational_Accelerators_and_Accelerated_Systems_046278/master/HW_1/hw1.hip"
.size .L.str.1, 143
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total time %f [msec]\n"
.size .L.str.3, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "total time %f [msec] distance from baseline %lld (should be zero)\n"
.size .L.str.5, 68
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20process_image_kernelPhS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n=== CPU ==="
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n=== GPU Task Serial ==="
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n=== GPU Bulk ==="
.size .Lstr.2, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__process_image_kernelPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20process_image_kernelPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008a12c_00000000-6_hw1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL13get_time_msecv, @function
_ZL13get_time_msecv:
.LFB2058:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LC1(%rip), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L4
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL13get_time_msecv, .-_ZL13get_time_msecv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13process_imagePhS_
.type _Z13process_imagePhS_, @function
_Z13process_imagePhS_:
.LFB2057:
.cfi_startproc
endbr64
subq $2328, %rsp
.cfi_def_cfa_offset 2336
movq %rdi, %r8
movq %fs:40, %rax
movq %rax, 2312(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $128, %ecx
rep stosq
movq %r8, %rax
leaq 65536(%r8), %rcx
.L8:
movzbl (%rax), %edx
addl $1, (%rsp,%rdx,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L8
leaq 1024(%rsp), %rdi
movl $128, %ecx
movl $0, %eax
rep stosq
.L9:
addl (%rsp,%rax), %ecx
movl %ecx, 1024(%rsp,%rax)
addq $4, %rax
cmpq $1024, %rax
jne .L9
leaq 1024(%rsp), %rax
leaq 2048(%rsp), %rdx
.L11:
movl (%rax), %ecx
testl %ecx, %ecx
jne .L10
addq $4, %rax
cmpq %rdx, %rax
jne .L11
.L10:
movq $0, 2048(%rsp)
movq $0, 2056(%rsp)
movq $0, 2064(%rsp)
movq $0, 2072(%rsp)
movq $0, 2080(%rsp)
movq $0, 2088(%rsp)
movq $0, 2096(%rsp)
movq $0, 2104(%rsp)
movq $0, 2112(%rsp)
movq $0, 2120(%rsp)
movq $0, 2128(%rsp)
movq $0, 2136(%rsp)
movq $0, 2144(%rsp)
movq $0, 2152(%rsp)
movq $0, 2160(%rsp)
movq $0, 2168(%rsp)
movq $0, 2176(%rsp)
movq $0, 2184(%rsp)
movq $0, 2192(%rsp)
movq $0, 2200(%rsp)
movq $0, 2208(%rsp)
movq $0, 2216(%rsp)
movq $0, 2224(%rsp)
movq $0, 2232(%rsp)
movq $0, 2240(%rsp)
movq $0, 2248(%rsp)
movq $0, 2256(%rsp)
movq $0, 2264(%rsp)
movq $0, 2272(%rsp)
movq $0, 2280(%rsp)
movq $0, 2288(%rsp)
movq $0, 2296(%rsp)
movl $0, %eax
movl $65536, %edx
subl %ecx, %edx
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movss .LC2(%rip), %xmm1
.L12:
movl 1024(%rsp,%rax,4), %edx
subl %ecx, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
divss %xmm2, %xmm0
mulss %xmm1, %xmm0
cvttss2sil %xmm0, %edx
movb %dl, 2048(%rsp,%rax)
addq $1, %rax
cmpq $256, %rax
jne .L12
movl $0, %eax
.L13:
movzbl (%r8,%rax), %edx
movzbl 2048(%rsp,%rdx), %edx
movb %dl, (%rsi,%rax)
addq $1, %rax
cmpq $65536, %rax
jne .L13
movq 2312(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $2328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z13process_imagePhS_, .-_Z13process_imagePhS_
.globl _Z33distance_sqr_between_image_arraysPhS_
.type _Z33distance_sqr_between_image_arraysPhS_, @function
_Z33distance_sqr_between_image_arraysPhS_:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %edx
movl $0, %ecx
.L23:
movzbl (%rdi,%rdx), %eax
movzbl (%rsi,%rdx), %r8d
subl %r8d, %eax
imull %eax, %eax
cltq
addq %rax, %rcx
addq $1, %rdx
cmpq $655360000, %rdx
jne .L23
movq %rcx, %rax
ret
.cfi_endproc
.LFE2059:
.size _Z33distance_sqr_between_image_arraysPhS_, .-_Z33distance_sqr_between_image_arraysPhS_
.globl _Z18array_min_positivePii
.type _Z18array_min_positivePii, @function
_Z18array_min_positivePii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z18array_min_positivePii, .-_Z18array_min_positivePii
.globl _Z10prefix_sumPii
.type _Z10prefix_sumPii, @function
_Z10prefix_sumPii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z10prefix_sumPii, .-_Z10prefix_sumPii
.globl _Z3mapPiiPhi
.type _Z3mapPiiPhi, @function
_Z3mapPiiPhi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z3mapPiiPhi, .-_Z3mapPiiPhi
.globl _Z42__device_stub__Z20process_image_kernelPhS_PhS_
.type _Z42__device_stub__Z20process_image_kernelPhS_PhS_, @function
_Z42__device_stub__Z20process_image_kernelPhS_PhS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20process_image_kernelPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z20process_image_kernelPhS_PhS_, .-_Z42__device_stub__Z20process_image_kernelPhS_PhS_
.globl _Z20process_image_kernelPhS_
.type _Z20process_image_kernelPhS_, @function
_Z20process_image_kernelPhS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20process_image_kernelPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z20process_image_kernelPhS_, .-_Z20process_image_kernelPhS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/idoyehe/Computational_Accelerators_and_Accelerated_Systems_046278/master/HW_1/hw1.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Cuda failure %s:%d: '%s'\n"
.LC5:
.string "\n=== CPU ===\n"
.LC6:
.string "total time %f [msec]\n"
.LC7:
.string "\n=== GPU Task Serial ===\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "total time %f [msec] distance from baseline %lld (should be zero)\n"
.section .rodata.str1.1
.LC9:
.string "\n=== GPU Bulk ===\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L70
leaq 24(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L71
leaq 32(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L72
leaq 40(%rsp), %rdi
movl $0, %edx
movl $655360000, %esi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L73
movl $0, %edi
call srand@PLT
movl $0, %ebx
.L44:
call rand@PLT
cltd
shrl $24, %edx
addl %edx, %eax
movzbl %al, %eax
subl %edx, %eax
movq 16(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq $655360000, %rbx
jne .L44
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZL13get_time_msecv
movsd %xmm0, (%rsp)
movl $0, %ebx
.L45:
movq %rbx, %rsi
addq 24(%rsp), %rsi
movq %rbx, %rdi
addq 16(%rsp), %rdi
call _Z13process_imagePhS_
addq $65536, %rbx
cmpq $655360000, %rbx
jne .L45
call _ZL13get_time_msecv
subsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L74
leaq 56(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L75
call _ZL13get_time_msecv
movsd %xmm0, (%rsp)
movl $0, %ebx
jmp .L51
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $154, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $155, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $156, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $157, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $186, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $187, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $192, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movq %rbx, %rdi
addq 32(%rsp), %rdi
movl $2, %ecx
movl $65536, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L76
call cudaDeviceSynchronize@PLT
addq $65536, %rbx
cmpq $655360000, %rbx
je .L77
.L51:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movl $1, %ecx
movl $65536, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L78
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z42__device_stub__Z20process_image_kernelPhS_PhS_
jmp .L49
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $196, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
call _ZL13get_time_msecv
movsd %xmm0, 8(%rsp)
movq 56(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L79
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L80
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33distance_sqr_between_image_arraysPhS_
movq %rax, %rdx
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $655360000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L81
leaq 72(%rsp), %rdi
movl $655360000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L82
call _ZL13get_time_msecv
movsd %xmm0, (%rsp)
movl $1, %ecx
movl $655360000, %edx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L83
movl $256, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $10000, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L57:
movl $2, %ecx
movl $655360000, %edx
movq 72(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L85
call cudaDeviceSynchronize@PLT
call _ZL13get_time_msecv
movsd %xmm0, 8(%rsp)
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L86
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L87
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33distance_sqr_between_image_arraysPhS_
movq %rax, %rdx
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L88
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L89
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L90
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L91
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L92
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $203, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $204, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $213, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $214, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $217, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L84:
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z42__device_stub__Z20process_image_kernelPhS_PhS_
jmp .L57
.L85:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $219, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $224, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $225, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $229, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $230, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $231, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $232, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z20process_image_kernelPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z20process_image_kernelPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1132396544
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw1.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13process_imagePhS_
.LCPI0_0:
.long 0x437f0000 # float 255
.text
.globl _Z13process_imagePhS_
.p2align 4, 0x90
.type _Z13process_imagePhS_,@function
_Z13process_imagePhS_: # @_Z13process_imagePhS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $2304, %rsp # imm = 0x900
.cfi_def_cfa_offset 2336
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 1280(%rsp), %rdi
xorl %r15d, %r15d
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movzbl (%r14,%r15), %eax
incl 1280(%rsp,%rax,4)
incq %r15
cmpq $65536, %r15 # imm = 0x10000
jne .LBB0_1
# %bb.2:
leaq 256(%rsp), %rdi
xorl %r15d, %r15d
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
addl 1280(%rsp,%r15,4), %eax
movl %eax, 256(%rsp,%r15,4)
incq %r15
cmpq $256, %r15 # imm = 0x100
jne .LBB0_3
# %bb.4: # %.preheader33.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_5: # %.preheader33
# =>This Inner Loop Header: Depth=1
movl 256(%rsp,%rcx,4), %eax
testl %eax, %eax
jne .LBB0_8
# %bb.6: # in Loop: Header=BB0_5 Depth=1
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB0_5
# %bb.7:
xorl %eax, %eax
.LBB0_8:
xorps %xmm1, %xmm1
movaps %xmm1, 240(%rsp)
movaps %xmm1, 224(%rsp)
movaps %xmm1, 208(%rsp)
movaps %xmm1, 192(%rsp)
movaps %xmm1, 176(%rsp)
movaps %xmm1, 160(%rsp)
movaps %xmm1, 144(%rsp)
movaps %xmm1, 128(%rsp)
movaps %xmm1, 112(%rsp)
movaps %xmm1, 96(%rsp)
movaps %xmm1, 80(%rsp)
movaps %xmm1, 64(%rsp)
movaps %xmm1, 48(%rsp)
movaps %xmm1, 32(%rsp)
movl $65536, %ecx # imm = 0x10000
subl %eax, %ecx
cvtsi2ss %ecx, %xmm0
movaps %xmm1, 16(%rsp)
movaps %xmm1, (%rsp)
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movl 256(%rsp,%rcx,4), %edx
subl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
divss %xmm0, %xmm2
mulss %xmm1, %xmm2
cvttss2si %xmm2, %edx
movb %dl, (%rsp,%rcx)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB0_9
# %bb.10: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movzbl (%r14,%rax), %ecx
movzbl (%rsp,%rcx), %ecx
movb %cl, (%rbx,%rax)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB0_11
# %bb.12:
addq $2304, %rsp # imm = 0x900
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13process_imagePhS_, .Lfunc_end0-_Z13process_imagePhS_
.cfi_endproc
# -- End function
.globl _Z33distance_sqr_between_image_arraysPhS_ # -- Begin function _Z33distance_sqr_between_image_arraysPhS_
.p2align 4, 0x90
.type _Z33distance_sqr_between_image_arraysPhS_,@function
_Z33distance_sqr_between_image_arraysPhS_: # @_Z33distance_sqr_between_image_arraysPhS_
.cfi_startproc
# %bb.0:
xorl %ecx, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movzbl (%rdi,%rcx), %edx
movzbl (%rsi,%rcx), %r8d
subl %r8d, %edx
imull %edx, %edx
addq %rdx, %rax
incq %rcx
cmpq $655360000, %rcx # imm = 0x27100000
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z33distance_sqr_between_image_arraysPhS_, .Lfunc_end1-_Z33distance_sqr_between_image_arraysPhS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__process_image_kernelPhS_ # -- Begin function _Z35__device_stub__process_image_kernelPhS_
.p2align 4, 0x90
.type _Z35__device_stub__process_image_kernelPhS_,@function
_Z35__device_stub__process_image_kernelPhS_: # @_Z35__device_stub__process_image_kernelPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20process_image_kernelPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z35__device_stub__process_image_kernelPhS_, .Lfunc_end2-_Z35__device_stub__process_image_kernelPhS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI3_2:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x437f0000 # float 255
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2440, %rsp # imm = 0x988
.cfi_def_cfa_offset 2496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 24(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 80(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_6
# %bb.7:
leaq 72(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB3_8
# %bb.9:
xorl %ebx, %ebx
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB3_10: # =>This Inner Loop Header: Depth=1
callq rand
movq 16(%rsp), %rcx
movb %al, (%rcx,%rbx)
incq %rbx
cmpq $655360000, %rbx # imm = 0x27100000
jne .LBB3_10
# %bb.11:
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 1408(%rsp), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_12: # =>This Loop Header: Depth=1
# Child Loop BB3_13 Depth 2
# Child Loop BB3_15 Depth 2
# Child Loop BB3_17 Depth 2
# Child Loop BB3_21 Depth 2
# Child Loop BB3_23 Depth 2
movq 16(%rsp), %r13
movq 24(%rsp), %rbp
movl $1024, %edx # imm = 0x400
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq memset@PLT
addq %r15, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_13: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r13,%rax), %ecx
incl 384(%rsp,%rcx,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB3_13
# %bb.14: # in Loop: Header=BB3_12 Depth=1
xorl %ebx, %ebx
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
addl 384(%rsp,%rbx,4), %eax
movl %eax, 1408(%rsp,%rbx,4)
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB3_15
# %bb.16: # %.preheader33.i.preheader
# in Loop: Header=BB3_12 Depth=1
xorl %ecx, %ecx
movss .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_17: # %.preheader33.i
# Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movl 1408(%rsp,%rcx,4), %eax
testl %eax, %eax
jne .LBB3_20
# %bb.18: # in Loop: Header=BB3_17 Depth=2
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB3_17
# %bb.19: # in Loop: Header=BB3_12 Depth=1
xorl %eax, %eax
.LBB3_20: # in Loop: Header=BB3_12 Depth=1
xorpd %xmm0, %xmm0
movapd %xmm0, 368(%rsp)
movapd %xmm0, 352(%rsp)
movapd %xmm0, 336(%rsp)
movapd %xmm0, 320(%rsp)
movapd %xmm0, 304(%rsp)
movapd %xmm0, 288(%rsp)
movapd %xmm0, 272(%rsp)
movapd %xmm0, 256(%rsp)
movapd %xmm0, 240(%rsp)
movapd %xmm0, 224(%rsp)
movapd %xmm0, 208(%rsp)
movapd %xmm0, 192(%rsp)
movapd %xmm0, 176(%rsp)
movapd %xmm0, 160(%rsp)
movapd %xmm0, 144(%rsp)
movapd %xmm0, 128(%rsp)
movl $65536, %ecx # imm = 0x10000
subl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_21: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movl 1408(%rsp,%rcx,4), %edx
subl %eax, %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
divss %xmm0, %xmm1
mulss %xmm2, %xmm1
cvttss2si %xmm1, %edx
movb %dl, 128(%rsp,%rcx)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB3_21
# %bb.22: # %.preheader.i.preheader
# in Loop: Header=BB3_12 Depth=1
addq %r15, %rbp
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_23: # %.preheader.i
# Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r13,%rax), %ecx
movzbl 128(%rsp,%rcx), %ecx
movb %cl, (%rbp,%rax)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB3_23
# %bb.24: # %_Z13process_imagePhS_.exit
# in Loop: Header=BB3_12 Depth=1
incq %r12
addq $65536, %r15 # imm = 0x10000
cmpq $10000, %r12 # imm = 0x2710
jne .LBB3_12
# %bb.25:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm0
addsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 384(%rsp), %xmm1
mulsd .LCPI3_2(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 64(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB3_26
# %bb.27:
leaq 56(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB3_28
# %bb.29:
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r12d, %r12d
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
mulsd .LCPI3_2(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 392(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
leaq 1023(%rbx), %r15
leaq 128(%rsp), %r13
leaq 96(%rsp), %rbp
leaq 88(%rsp), %r14
.p2align 4, 0x90
.LBB3_30: # =>This Inner Loop Header: Depth=1
movq 64(%rsp), %rdi
movq 16(%rsp), %rsi
addq %r12, %rsi
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_31
# %bb.32: # in Loop: Header=BB3_30 Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_34
# %bb.33: # in Loop: Header=BB3_30 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 384(%rsp)
leaq 104(%rsp), %rax
movq %rax, 392(%rsp)
leaq 1408(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 1408(%rsp), %rsi
movl 1416(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z20process_image_kernelPhS_, %edi
leaq 384(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_34: # in Loop: Header=BB3_30 Depth=1
movq 80(%rsp), %rdi
addq %r12, %rdi
movq 56(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_35
# %bb.36: # in Loop: Header=BB3_30 Depth=1
callq hipDeviceSynchronize
addq $65536, %r12 # imm = 0x10000
cmpq $655360000, %r12 # imm = 0x27100000
jne .LBB3_30
# %bb.37:
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_38
# %bb.39:
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_40
# %bb.41:
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
movq 80(%rsp), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_42: # =>This Inner Loop Header: Depth=1
movzbl (%rax,%rdx), %edi
movzbl (%rcx,%rdx), %r8d
subl %r8d, %edi
imull %edi, %edi
addq %rdi, %rsi
incq %rdx
cmpq $655360000, %rdx # imm = 0x27100000
jne .LBB3_42
# %bb.43: # %_Z33distance_sqr_between_image_arraysPhS_.exit
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
leaq 48(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
callq hipMalloc
testl %eax, %eax
jne .LBB3_44
# %bb.45:
leaq 40(%rsp), %rdi
movl $655360000, %esi # imm = 0x27100000
callq hipMalloc
testl %eax, %eax
jne .LBB3_46
# %bb.47:
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi
movl $655360000, %edx # imm = 0x27100000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_48
# %bb.49:
leaq 255(%rbx), %rdx
addq $9999, %rbx # imm = 0x270F
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_51
# %bb.50:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 384(%rsp)
leaq 104(%rsp), %rax
movq %rax, 392(%rsp)
leaq 1408(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1408(%rsp), %rsi
movl 1416(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 384(%rsp), %r9
movl $_Z20process_image_kernelPhS_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_51:
movq 72(%rsp), %rdi
movq 40(%rsp), %rsi
movl $655360000, %edx # imm = 0x27100000
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_52
# %bb.53:
callq hipDeviceSynchronize
leaq 384(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 384(%rsp), %xmm0
movsd %xmm0, 120(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 392(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_54
# %bb.55:
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_56
# %bb.57:
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm1
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm2
movsd 120(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd .LCPI3_2(%rip), %xmm3
addsd %xmm1, %xmm2
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm3, %xmm0
movq 24(%rsp), %rax
movq 72(%rsp), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_58: # =>This Inner Loop Header: Depth=1
movzbl (%rax,%rdx), %edi
movzbl (%rcx,%rdx), %r8d
subl %r8d, %edi
imull %edi, %edi
addq %rdi, %rsi
incq %rdx
cmpq $655360000, %rdx # imm = 0x27100000
jne .LBB3_58
# %bb.59: # %_Z33distance_sqr_between_image_arraysPhS_.exit125
subsd %xmm2, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 72(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_60
# %bb.61:
movq 80(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_62
# %bb.63:
movq 24(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_64
# %bb.65:
movq 16(%rsp), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB3_66
# %bb.67:
xorl %eax, %eax
addq $2440, %rsp # imm = 0x988
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_35:
.cfi_def_cfa_offset 2496
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $199, %edx
jmp .LBB3_2
.LBB3_31:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $196, %edx
.LBB3_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $156, %edx
jmp .LBB3_2
.LBB3_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $157, %edx
jmp .LBB3_2
.LBB3_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $158, %edx
jmp .LBB3_2
.LBB3_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $159, %edx
jmp .LBB3_2
.LBB3_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $188, %edx
jmp .LBB3_2
.LBB3_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $189, %edx
jmp .LBB3_2
.LBB3_38:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $205, %edx
jmp .LBB3_2
.LBB3_40:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $206, %edx
jmp .LBB3_2
.LBB3_44:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $215, %edx
jmp .LBB3_2
.LBB3_46:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $216, %edx
jmp .LBB3_2
.LBB3_48:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $219, %edx
jmp .LBB3_2
.LBB3_52:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $221, %edx
jmp .LBB3_2
.LBB3_54:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $226, %edx
jmp .LBB3_2
.LBB3_56:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $227, %edx
jmp .LBB3_2
.LBB3_60:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $231, %edx
jmp .LBB3_2
.LBB3_62:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $232, %edx
jmp .LBB3_2
.LBB3_64:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $233, %edx
jmp .LBB3_2
.LBB3_66:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $234, %edx
jmp .LBB3_2
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20process_image_kernelPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20process_image_kernelPhS_,@object # @_Z20process_image_kernelPhS_
.section .rodata,"a",@progbits
.globl _Z20process_image_kernelPhS_
.p2align 3, 0x0
_Z20process_image_kernelPhS_:
.quad _Z35__device_stub__process_image_kernelPhS_
.size _Z20process_image_kernelPhS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/idoyehe/Computational_Accelerators_and_Accelerated_Systems_046278/master/HW_1/hw1.hip"
.size .L.str.1, 143
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total time %f [msec]\n"
.size .L.str.3, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "total time %f [msec] distance from baseline %lld (should be zero)\n"
.size .L.str.5, 68
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20process_image_kernelPhS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n=== CPU ==="
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n=== GPU Task Serial ==="
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n=== GPU Bulk ==="
.size .Lstr.2, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__process_image_kernelPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20process_image_kernelPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
int iRow = blockIdx.y*blockDim.y+threadIdx.y;
int iCol = blockIdx.x*blockDim.x+threadIdx.x;
if(( iRow < numARows) && (iCol < numBColumns)) {
float Cvalue = 0.0;
for (int i = 0;i< numAColumns;++i)
{
Cvalue += A[iRow*numAColumns+i]*B[iCol+i*numBColumns];
}
C[iRow*numBColumns+iCol] = Cvalue;
}
} | code for sm_80
Function : _Z14matrixMultiplyPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x184], R0 ; /* 0x0000610002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x184] ; /* 0x00006100000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
int iRow = blockIdx.y*blockDim.y+threadIdx.y;
int iCol = blockIdx.x*blockDim.x+threadIdx.x;
if(( iRow < numARows) && (iCol < numBColumns)) {
float Cvalue = 0.0;
for (int i = 0;i< numAColumns;++i)
{
Cvalue += A[iRow*numAColumns+i]*B[iCol+i*numBColumns];
}
C[iRow*numBColumns+iCol] = Cvalue;
}
} | .file "tmpxft_00093b4f_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.type _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, .-_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.type _Z14matrixMultiplyPfS_S_iiiiii, @function
_Z14matrixMultiplyPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14matrixMultiplyPfS_S_iiiiii, .-_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14matrixMultiplyPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
int iRow = blockIdx.y*blockDim.y+threadIdx.y;
int iCol = blockIdx.x*blockDim.x+threadIdx.x;
if(( iRow < numARows) && (iCol < numBColumns)) {
float Cvalue = 0.0;
for (int i = 0;i< numAColumns;++i)
{
Cvalue += A[iRow*numAColumns+i]*B[iCol+i*numBColumns];
}
C[iRow*numBColumns+iCol] = Cvalue;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
int iRow = blockIdx.y*blockDim.y+threadIdx.y;
int iCol = blockIdx.x*blockDim.x+threadIdx.x;
if(( iRow < numARows) && (iCol < numBColumns)) {
float Cvalue = 0.0;
for (int i = 0;i< numAColumns;++i)
{
Cvalue += A[iRow*numAColumns+i]*B[iCol+i*numBColumns];
}
C[iRow*numBColumns+iCol] = Cvalue;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
int iRow = blockIdx.y*blockDim.y+threadIdx.y;
int iCol = blockIdx.x*blockDim.x+threadIdx.x;
if(( iRow < numARows) && (iCol < numBColumns)) {
float Cvalue = 0.0;
for (int i = 0;i< numAColumns;++i)
{
Cvalue += A[iRow*numAColumns+i]*B[iCol+i*numBColumns];
}
C[iRow*numBColumns+iCol] = Cvalue;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMultiplyPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 8
.type _Z14matrixMultiplyPfS_S_iiiiii,@function
_Z14matrixMultiplyPfS_S_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMultiplyPfS_S_iiiiii, .Lfunc_end0-_Z14matrixMultiplyPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
int iRow = blockIdx.y*blockDim.y+threadIdx.y;
int iCol = blockIdx.x*blockDim.x+threadIdx.x;
if(( iRow < numARows) && (iCol < numBColumns)) {
float Cvalue = 0.0;
for (int i = 0;i< numAColumns;++i)
{
Cvalue += A[iRow*numAColumns+i]*B[iCol+i*numBColumns];
}
C[iRow*numBColumns+iCol] = Cvalue;
}
} | .text
.file "matrixMultiply.hip"
.globl _Z29__device_stub__matrixMultiplyPfS_S_iiiiii # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPfS_S_iiiiii,@function
_Z29__device_stub__matrixMultiplyPfS_S_iiiiii: # @_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMultiplyPfS_S_iiiiii, .Lfunc_end0-_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMultiplyPfS_S_iiiiii,@object # @_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 3, 0x0
_Z14matrixMultiplyPfS_S_iiiiii:
.quad _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.size _Z14matrixMultiplyPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrixMultiplyPfS_S_iiiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14matrixMultiplyPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x184] ; /* 0x0000610000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x184], R0 ; /* 0x0000610002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x184] ; /* 0x00006100000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMultiplyPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 8
.type _Z14matrixMultiplyPfS_S_iiiiii,@function
_Z14matrixMultiplyPfS_S_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMultiplyPfS_S_iiiiii, .Lfunc_end0-_Z14matrixMultiplyPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00093b4f_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.type _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, .-_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.type _Z14matrixMultiplyPfS_S_iiiiii, @function
_Z14matrixMultiplyPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14matrixMultiplyPfS_S_iiiiii, .-_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14matrixMultiplyPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiply.hip"
.globl _Z29__device_stub__matrixMultiplyPfS_S_iiiiii # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPfS_S_iiiiii,@function
_Z29__device_stub__matrixMultiplyPfS_S_iiiiii: # @_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMultiplyPfS_S_iiiiii, .Lfunc_end0-_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMultiplyPfS_S_iiiiii,@object # @_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 3, 0x0
_Z14matrixMultiplyPfS_S_iiiiii:
.quad _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.size _Z14matrixMultiplyPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrixMultiplyPfS_S_iiiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true) {
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define CUDA_ERR_CHECK \
gpuErrchk(cudaPeekAtLastError());\
gpuErrchk(cudaDeviceSynchronize());\
__global__ void MyKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
}
void launchMyKernel(int *array, int arrayCount)
{
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the
// maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize( &minGridSize, &blockSize,
MyKernel, 0, 0);
// Round up according to array size
gridSize = (arrayCount + blockSize - 1) / blockSize;
MyKernel<<< gridSize, blockSize >>>(array, arrayCount);
cudaDeviceSynchronize();
// calculate theoretical occupancy
int maxActiveBlocks;
cudaOccupancyMaxActiveBlocksPerMultiprocessor( &maxActiveBlocks,
MyKernel, blockSize,
0);
int device;
cudaDeviceProp props;
cudaGetDevice(&device);
cudaGetDeviceProperties(&props, device);
float occupancy = (maxActiveBlocks * blockSize / props.warpSize) /
(float)(props.maxThreadsPerMultiProcessor /
props.warpSize);
printf("Launched blocks of size %d. Theoretical occupancy: %f\n",
blockSize, occupancy);
}
int main() {
cudaError_t err;
int *array, arrayCount = 10000;
err = cudaMalloc((void **)&array, (arrayCount + 1) * sizeof(int));
CUDA_ERR_CHECK;
launchMyKernel(array, arrayCount);
return 1;
} | code for sm_80
Function : _Z8MyKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true) {
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define CUDA_ERR_CHECK \
gpuErrchk(cudaPeekAtLastError());\
gpuErrchk(cudaDeviceSynchronize());\
__global__ void MyKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
}
void launchMyKernel(int *array, int arrayCount)
{
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the
// maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize( &minGridSize, &blockSize,
MyKernel, 0, 0);
// Round up according to array size
gridSize = (arrayCount + blockSize - 1) / blockSize;
MyKernel<<< gridSize, blockSize >>>(array, arrayCount);
cudaDeviceSynchronize();
// calculate theoretical occupancy
int maxActiveBlocks;
cudaOccupancyMaxActiveBlocksPerMultiprocessor( &maxActiveBlocks,
MyKernel, blockSize,
0);
int device;
cudaDeviceProp props;
cudaGetDevice(&device);
cudaGetDeviceProperties(&props, device);
float occupancy = (maxActiveBlocks * blockSize / props.warpSize) /
(float)(props.maxThreadsPerMultiProcessor /
props.warpSize);
printf("Launched blocks of size %d. Theoretical occupancy: %f\n",
blockSize, occupancy);
}
int main() {
cudaError_t err;
int *array, arrayCount = 10000;
err = cudaMalloc((void **)&array, (arrayCount + 1) * sizeof(int));
CUDA_ERR_CHECK;
launchMyKernel(array, arrayCount);
return 1;
} | .file "tmpxft_00199c17_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z28__device_stub__Z8MyKernelPiiPii
.type _Z28__device_stub__Z8MyKernelPiiPii, @function
_Z28__device_stub__Z8MyKernelPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8MyKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z8MyKernelPiiPii, .-_Z28__device_stub__Z8MyKernelPiiPii
.globl _Z8MyKernelPii
.type _Z8MyKernelPii, @function
_Z8MyKernelPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8MyKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8MyKernelPii, .-_Z8MyKernelPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Launched blocks of size %d. Theoretical occupancy: %f\n"
.text
.globl _Z14launchMyKernelPii
.type _Z14launchMyKernelPii, @function
_Z14launchMyKernelPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L31
.L20:
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
leal -1(%rbx,%rbp), %eax
cltd
idivl %ebx
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L23:
call cudaDeviceSynchronize@PLT
leaq 56(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
leaq 68(%rsp), %rdi
call cudaGetDevice@PLT
leaq 80(%rsp), %rdi
movl 68(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 388(%rsp), %ecx
movl %ebx, %eax
imull 56(%rsp), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 704(%rsp), %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq 44(%rsp), %rdi
movl 40(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 48(%rsp), %rdi
movl 40(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 52(%rsp), %rdi
movl 40(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 56(%rsp), %rdi
movl 40(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 80(%rsp), %rdi
leaq _Z8MyKernelPii(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L20
movl 44(%rsp), %esi
movl 48(%rsp), %ecx
movl 104(%rsp), %r15d
movl 52(%rsp), %eax
cmpl %eax, %r15d
cmovg %eax, %r15d
leal -1(%rcx,%r15), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r13d
testl %eax, %eax
jle .L25
movl $0, 12(%rsp)
movl $0, %eax
movl %ecx, %r14d
movl %ebx, 28(%rsp)
movq %r12, 16(%rsp)
movl %esi, %r12d
movl %ebp, 24(%rsp)
movl %eax, %ebp
jmp .L22
.L21:
cmpl %ebp, %r12d
je .L27
subl %r14d, %r13d
testl %r13d, %r13d
jle .L34
.L22:
cmpl %r13d, %r15d
movl %r13d, %ebx
cmovle %r15d, %ebx
leaq 68(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L29
movl %ebx, %eax
imull 68(%rsp), %eax
cmpl %eax, %ebp
jge .L21
movl %eax, %ebp
movl %ebx, 12(%rsp)
jmp .L21
.L34:
movq 16(%rsp), %r12
movl 24(%rsp), %ebp
movl 12(%rsp), %ebx
jmp .L20
.L25:
movl $0, %ebx
jmp .L20
.L27:
movq 16(%rsp), %r12
movl 24(%rsp), %ebp
movl 12(%rsp), %ebx
jmp .L20
.L29:
movl 28(%rsp), %ebx
movq 16(%rsp), %r12
movl 24(%rsp), %ebp
jmp .L20
.L32:
movl %ebp, %esi
movq %r12, %rdi
call _Z28__device_stub__Z8MyKernelPiiPii
jmp .L23
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14launchMyKernelPii, .-_Z14launchMyKernelPii
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gshashidhar125/LightHouse/master/apps/src/occupancyRelatedFixedCode/test.cu"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40004, %esi
call cudaMalloc@PLT
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $64, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $10000, %esi
movq (%rsp), %rdi
call _Z14launchMyKernelPii
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $1, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z8MyKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true) {
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define CUDA_ERR_CHECK \
gpuErrchk(cudaPeekAtLastError());\
gpuErrchk(cudaDeviceSynchronize());\
__global__ void MyKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
}
void launchMyKernel(int *array, int arrayCount)
{
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the
// maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize( &minGridSize, &blockSize,
MyKernel, 0, 0);
// Round up according to array size
gridSize = (arrayCount + blockSize - 1) / blockSize;
MyKernel<<< gridSize, blockSize >>>(array, arrayCount);
cudaDeviceSynchronize();
// calculate theoretical occupancy
int maxActiveBlocks;
cudaOccupancyMaxActiveBlocksPerMultiprocessor( &maxActiveBlocks,
MyKernel, blockSize,
0);
int device;
cudaDeviceProp props;
cudaGetDevice(&device);
cudaGetDeviceProperties(&props, device);
float occupancy = (maxActiveBlocks * blockSize / props.warpSize) /
(float)(props.maxThreadsPerMultiProcessor /
props.warpSize);
printf("Launched blocks of size %d. Theoretical occupancy: %f\n",
blockSize, occupancy);
}
int main() {
cudaError_t err;
int *array, arrayCount = 10000;
err = cudaMalloc((void **)&array, (arrayCount + 1) * sizeof(int));
CUDA_ERR_CHECK;
launchMyKernel(array, arrayCount);
return 1;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true) {
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define CUDA_ERR_CHECK \
gpuErrchk(hipPeekAtLastError());\
gpuErrchk(hipDeviceSynchronize());\
__global__ void MyKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
}
void launchMyKernel(int *array, int arrayCount)
{
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the
// maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize( &minGridSize, &blockSize,
MyKernel, 0, 0);
// Round up according to array size
gridSize = (arrayCount + blockSize - 1) / blockSize;
MyKernel<<< gridSize, blockSize >>>(array, arrayCount);
hipDeviceSynchronize();
// calculate theoretical occupancy
int maxActiveBlocks;
hipOccupancyMaxActiveBlocksPerMultiprocessor( &maxActiveBlocks,
MyKernel, blockSize,
0);
int device;
hipDeviceProp_t props;
hipGetDevice(&device);
hipGetDeviceProperties(&props, device);
float occupancy = (maxActiveBlocks * blockSize / props.warpSize) /
(float)(props.maxThreadsPerMultiProcessor /
props.warpSize);
printf("Launched blocks of size %d. Theoretical occupancy: %f\n",
blockSize, occupancy);
}
int main() {
hipError_t err;
int *array, arrayCount = 10000;
err = hipMalloc((void **)&array, (arrayCount + 1) * sizeof(int));
CUDA_ERR_CHECK;
launchMyKernel(array, arrayCount);
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true) {
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define CUDA_ERR_CHECK \
gpuErrchk(hipPeekAtLastError());\
gpuErrchk(hipDeviceSynchronize());\
__global__ void MyKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
}
void launchMyKernel(int *array, int arrayCount)
{
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the
// maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize( &minGridSize, &blockSize,
MyKernel, 0, 0);
// Round up according to array size
gridSize = (arrayCount + blockSize - 1) / blockSize;
MyKernel<<< gridSize, blockSize >>>(array, arrayCount);
hipDeviceSynchronize();
// calculate theoretical occupancy
int maxActiveBlocks;
hipOccupancyMaxActiveBlocksPerMultiprocessor( &maxActiveBlocks,
MyKernel, blockSize,
0);
int device;
hipDeviceProp_t props;
hipGetDevice(&device);
hipGetDeviceProperties(&props, device);
float occupancy = (maxActiveBlocks * blockSize / props.warpSize) /
(float)(props.maxThreadsPerMultiProcessor /
props.warpSize);
printf("Launched blocks of size %d. Theoretical occupancy: %f\n",
blockSize, occupancy);
}
int main() {
hipError_t err;
int *array, arrayCount = 10000;
err = hipMalloc((void **)&array, (arrayCount + 1) * sizeof(int));
CUDA_ERR_CHECK;
launchMyKernel(array, arrayCount);
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelPii
.globl _Z8MyKernelPii
.p2align 8
.type _Z8MyKernelPii,@function
_Z8MyKernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelPii, .Lfunc_end0-_Z8MyKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MyKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true) {
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
#define CUDA_ERR_CHECK \
gpuErrchk(hipPeekAtLastError());\
gpuErrchk(hipDeviceSynchronize());\
__global__ void MyKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
}
void launchMyKernel(int *array, int arrayCount)
{
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the
// maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize( &minGridSize, &blockSize,
MyKernel, 0, 0);
// Round up according to array size
gridSize = (arrayCount + blockSize - 1) / blockSize;
MyKernel<<< gridSize, blockSize >>>(array, arrayCount);
hipDeviceSynchronize();
// calculate theoretical occupancy
int maxActiveBlocks;
hipOccupancyMaxActiveBlocksPerMultiprocessor( &maxActiveBlocks,
MyKernel, blockSize,
0);
int device;
hipDeviceProp_t props;
hipGetDevice(&device);
hipGetDeviceProperties(&props, device);
float occupancy = (maxActiveBlocks * blockSize / props.warpSize) /
(float)(props.maxThreadsPerMultiProcessor /
props.warpSize);
printf("Launched blocks of size %d. Theoretical occupancy: %f\n",
blockSize, occupancy);
}
int main() {
hipError_t err;
int *array, arrayCount = 10000;
err = hipMalloc((void **)&array, (arrayCount + 1) * sizeof(int));
CUDA_ERR_CHECK;
launchMyKernel(array, arrayCount);
return 1;
} | .text
.file "test.hip"
.globl _Z23__device_stub__MyKernelPii # -- Begin function _Z23__device_stub__MyKernelPii
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelPii,@function
_Z23__device_stub__MyKernelPii: # @_Z23__device_stub__MyKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8MyKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelPii, .Lfunc_end0-_Z23__device_stub__MyKernelPii
.cfi_endproc
# -- End function
.globl _Z14launchMyKernelPii # -- Begin function _Z14launchMyKernelPii
.p2align 4, 0x90
.type _Z14launchMyKernelPii,@function
_Z14launchMyKernelPii: # @_Z14launchMyKernelPii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
leaq 76(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $_Z8MyKernelPii, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 8(%rsp), %ecx
leal (%rbx,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8MyKernelPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl 8(%rsp), %edx
leaq 32(%rsp), %rdi
movl $_Z8MyKernelPii, %esi
xorl %ecx, %ecx
callq hipOccupancyMaxActiveBlocksPerMultiprocessor
leaq 16(%rsp), %rdi
callq hipGetDevice
movl 16(%rsp), %esi
leaq 80(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 8(%rsp), %esi
movl 32(%rsp), %eax
imull %esi, %eax
movl 388(%rsp), %edi
movl 704(%rsp), %ecx
cltd
idivl %edi
cvtsi2ss %eax, %xmm0
movl %ecx, %eax
cltd
idivl %edi
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14launchMyKernelPii, .Lfunc_end1-_Z14launchMyKernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $40004, %esi # imm = 0x9C44
callq hipMalloc
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB2_3
# %bb.1: # %_Z9gpuAssert10hipError_tPKcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_3
# %bb.2: # %_Z9gpuAssert10hipError_tPKcib.exit3
movq (%rsp), %rdi
movl $10000, %esi # imm = 0x2710
callq _Z14launchMyKernelPii
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_3:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelPii,@object # @_Z8MyKernelPii
.section .rodata,"a",@progbits
.globl _Z8MyKernelPii
.p2align 3, 0x0
_Z8MyKernelPii:
.quad _Z23__device_stub__MyKernelPii
.size _Z8MyKernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Launched blocks of size %d. Theoretical occupancy: %f\n"
.size .L.str, 55
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gshashidhar125/LightHouse/master/apps/src/occupancyRelatedFixedCode/test.hip"
.size .L.str.1, 134
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8MyKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelPii
.globl _Z8MyKernelPii
.p2align 8
.type _Z8MyKernelPii,@function
_Z8MyKernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelPii, .Lfunc_end0-_Z8MyKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MyKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199c17_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z28__device_stub__Z8MyKernelPiiPii
.type _Z28__device_stub__Z8MyKernelPiiPii, @function
_Z28__device_stub__Z8MyKernelPiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8MyKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z8MyKernelPiiPii, .-_Z28__device_stub__Z8MyKernelPiiPii
.globl _Z8MyKernelPii
.type _Z8MyKernelPii, @function
_Z8MyKernelPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8MyKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8MyKernelPii, .-_Z8MyKernelPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Launched blocks of size %d. Theoretical occupancy: %f\n"
.text
.globl _Z14launchMyKernelPii
.type _Z14launchMyKernelPii, @function
_Z14launchMyKernelPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L31
.L20:
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
leal -1(%rbx,%rbp), %eax
cltd
idivl %ebx
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L23:
call cudaDeviceSynchronize@PLT
leaq 56(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
leaq 68(%rsp), %rdi
call cudaGetDevice@PLT
leaq 80(%rsp), %rdi
movl 68(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 388(%rsp), %ecx
movl %ebx, %eax
imull 56(%rsp), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 704(%rsp), %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq 44(%rsp), %rdi
movl 40(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 48(%rsp), %rdi
movl 40(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 52(%rsp), %rdi
movl 40(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 56(%rsp), %rdi
movl 40(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L20
leaq 80(%rsp), %rdi
leaq _Z8MyKernelPii(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L20
movl 44(%rsp), %esi
movl 48(%rsp), %ecx
movl 104(%rsp), %r15d
movl 52(%rsp), %eax
cmpl %eax, %r15d
cmovg %eax, %r15d
leal -1(%rcx,%r15), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r13d
testl %eax, %eax
jle .L25
movl $0, 12(%rsp)
movl $0, %eax
movl %ecx, %r14d
movl %ebx, 28(%rsp)
movq %r12, 16(%rsp)
movl %esi, %r12d
movl %ebp, 24(%rsp)
movl %eax, %ebp
jmp .L22
.L21:
cmpl %ebp, %r12d
je .L27
subl %r14d, %r13d
testl %r13d, %r13d
jle .L34
.L22:
cmpl %r13d, %r15d
movl %r13d, %ebx
cmovle %r15d, %ebx
leaq 68(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L29
movl %ebx, %eax
imull 68(%rsp), %eax
cmpl %eax, %ebp
jge .L21
movl %eax, %ebp
movl %ebx, 12(%rsp)
jmp .L21
.L34:
movq 16(%rsp), %r12
movl 24(%rsp), %ebp
movl 12(%rsp), %ebx
jmp .L20
.L25:
movl $0, %ebx
jmp .L20
.L27:
movq 16(%rsp), %r12
movl 24(%rsp), %ebp
movl 12(%rsp), %ebx
jmp .L20
.L29:
movl 28(%rsp), %ebx
movq 16(%rsp), %r12
movl 24(%rsp), %ebp
jmp .L20
.L32:
movl %ebp, %esi
movq %r12, %rdi
call _Z28__device_stub__Z8MyKernelPiiPii
jmp .L23
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14launchMyKernelPii, .-_Z14launchMyKernelPii
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gshashidhar125/LightHouse/master/apps/src/occupancyRelatedFixedCode/test.cu"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40004, %esi
call cudaMalloc@PLT
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $64, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $10000, %esi
movq (%rsp), %rdi
call _Z14launchMyKernelPii
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $1, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z8MyKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z23__device_stub__MyKernelPii # -- Begin function _Z23__device_stub__MyKernelPii
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelPii,@function
_Z23__device_stub__MyKernelPii: # @_Z23__device_stub__MyKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8MyKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelPii, .Lfunc_end0-_Z23__device_stub__MyKernelPii
.cfi_endproc
# -- End function
.globl _Z14launchMyKernelPii # -- Begin function _Z14launchMyKernelPii
.p2align 4, 0x90
.type _Z14launchMyKernelPii,@function
_Z14launchMyKernelPii: # @_Z14launchMyKernelPii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
leaq 76(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $_Z8MyKernelPii, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 8(%rsp), %ecx
leal (%rbx,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8MyKernelPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl 8(%rsp), %edx
leaq 32(%rsp), %rdi
movl $_Z8MyKernelPii, %esi
xorl %ecx, %ecx
callq hipOccupancyMaxActiveBlocksPerMultiprocessor
leaq 16(%rsp), %rdi
callq hipGetDevice
movl 16(%rsp), %esi
leaq 80(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 8(%rsp), %esi
movl 32(%rsp), %eax
imull %esi, %eax
movl 388(%rsp), %edi
movl 704(%rsp), %ecx
cltd
idivl %edi
cvtsi2ss %eax, %xmm0
movl %ecx, %eax
cltd
idivl %edi
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14launchMyKernelPii, .Lfunc_end1-_Z14launchMyKernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $40004, %esi # imm = 0x9C44
callq hipMalloc
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB2_3
# %bb.1: # %_Z9gpuAssert10hipError_tPKcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_3
# %bb.2: # %_Z9gpuAssert10hipError_tPKcib.exit3
movq (%rsp), %rdi
movl $10000, %esi # imm = 0x2710
callq _Z14launchMyKernelPii
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_3:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelPii,@object # @_Z8MyKernelPii
.section .rodata,"a",@progbits
.globl _Z8MyKernelPii
.p2align 3, 0x0
_Z8MyKernelPii:
.quad _Z23__device_stub__MyKernelPii
.size _Z8MyKernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Launched blocks of size %d. Theoretical occupancy: %f\n"
.size .L.str, 55
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gshashidhar125/LightHouse/master/apps/src/occupancyRelatedFixedCode/test.hip"
.size .L.str.1, 134
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
#include <time.h>
int main(void) {
typedef uint type_t;
int max_count = 50'000'000;
thrust::host_vector<int> host(max_count);
for(int i = 0; i < max_count; ++i)
host[i] = rand() + 2 * rand(); // fill all 32 bits.
// Copy in host data.
thrust::device_vector<int> gpu = host;
int sizes[] { 1, 2, 4, 6, 8, 10, 12, 14, 16, 20, 25, 30, 35, 40, 45, 50 };
for(int size : sizes) {
// Sort 5 billion keys at least.
int count = 1'000'000 * size;
int num_iterations = (int)ceil(5.0e9 / count);
cudaDeviceSynchronize();
timespec start;
clock_gettime(CLOCK_REALTIME, &start);
for(int i = 0; i < num_iterations; ++i)
thrust::sort(gpu.begin(), gpu.begin() + count);
cudaDeviceSynchronize();
timespec end;
clock_gettime(CLOCK_REALTIME, &end);
double elapsed = (end.tv_sec - start.tv_sec) +
(end.tv_nsec - start.tv_nsec) * 1.0e-9;
double rate = (double)count * num_iterations / elapsed / 1.0e6;
printf("%9d: %20.5f time=%f, iterations=%d\n", count, rate, elapsed,
num_iterations);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
#include <cstdlib>
#include <time.h>
int main(void) {
typedef uint type_t;
int max_count = 50'000'000;
thrust::host_vector<int> host(max_count);
for(int i = 0; i < max_count; ++i)
host[i] = rand() + 2 * rand(); // fill all 32 bits.
// Copy in host data.
thrust::device_vector<int> gpu = host;
int sizes[] { 1, 2, 4, 6, 8, 10, 12, 14, 16, 20, 25, 30, 35, 40, 45, 50 };
for(int size : sizes) {
// Sort 5 billion keys at least.
int count = 1'000'000 * size;
int num_iterations = (int)ceil(5.0e9 / count);
hipDeviceSynchronize();
timespec start;
clock_gettime(CLOCK_REALTIME, &start);
for(int i = 0; i < num_iterations; ++i)
thrust::sort(gpu.begin(), gpu.begin() + count);
hipDeviceSynchronize();
timespec end;
clock_gettime(CLOCK_REALTIME, &end);
double elapsed = (end.tv_sec - start.tv_sec) +
(end.tv_nsec - start.tv_nsec) * 1.0e-9;
double rate = (double)count * num_iterations / elapsed / 1.0e6;
printf("%9d: %20.5f time=%f, iterations=%d\n", count, rate, elapsed,
num_iterations);
}
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void grayScale(uchar3 *input, uchar3 *output) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | code for sm_80
Function : _Z9grayScaleP6uchar3S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0207 */
/*0070*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1100 */
/*0080*/ LDG.E.U8 R5, [R2.64+0x1] ; /* 0x0000010402057981 */
/* 0x000ea8000c1e1100 */
/*0090*/ LDG.E.U8 R4, [R2.64+0x2] ; /* 0x0000020402047981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R4, R4, R5, R0 ; /* 0x0000000504047210 */
/* 0x004fca0007ffe000 */
/*00c0*/ IMAD.WIDE.U32 R4, R4, -0x55555555, RZ ; /* 0xaaaaaaab04047825 */
/* 0x000fca00078e00ff */
/*00d0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011605 */
/*00e0*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe8000c101104 */
/*00f0*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*0100*/ STG.E.U8 [R6.64+0x2], R5 ; /* 0x0000020506007986 */
/* 0x000fe2000c101104 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void grayScale(uchar3 *input, uchar3 *output) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
} | .file "tmpxft_001afa38_00000000-6_grayScale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z9grayScaleP6uchar3S0_P6uchar3S0_
.type _Z37__device_stub__Z9grayScaleP6uchar3S0_P6uchar3S0_, @function
_Z37__device_stub__Z9grayScaleP6uchar3S0_P6uchar3S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9grayScaleP6uchar3S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z9grayScaleP6uchar3S0_P6uchar3S0_, .-_Z37__device_stub__Z9grayScaleP6uchar3S0_P6uchar3S0_
.globl _Z9grayScaleP6uchar3S0_
.type _Z9grayScaleP6uchar3S0_, @function
_Z9grayScaleP6uchar3S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9grayScaleP6uchar3S0_P6uchar3S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9grayScaleP6uchar3S0_, .-_Z9grayScaleP6uchar3S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9grayScaleP6uchar3S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9grayScaleP6uchar3S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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