system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ThresholdKernel(float min, float max, int mode, float* input, float* output, int size, int count)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
__shared__ float delta;
if(id < size)
{
if (threadIdx.x == 0)
delta = (max - min)/count;
__syncthreads();
for (int i = 0; i < count; i++)
output[i * size + id] = 0;
int idx;
float fidx = ((input[id] - min) / delta);
switch (mode)
{
case 0: // consider values outside of the interval <min,max>
idx = (int)floor(fmaxf(0, fminf(fidx, count - 1)));
break;
case 1: // strict threshold
if (fidx < 0.0f || fidx >= count)
{
return;
}
idx = (int)fidx;
break;
}
output[idx * size + id] = 1.0f;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15ThresholdKernelffiPfS_ii
.globl _Z15ThresholdKernelffiPfS_ii
.p2align 8
.type _Z15ThresholdKernelffiPfS_ii,@function
_Z15ThresholdKernelffiPfS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_21
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x24
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v0, s5
v_sub_f32_e64 v2, s3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v0, v0, v2
v_div_scale_f32 v6, vcc_lo, v2, v0, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v0, v2
v_mov_b32_e32 v2, 0
ds_store_b32 v2, v0
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
s_mov_b32 s7, s5
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s7, s7, -1
s_cmp_eq_u32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s4, v2
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v0, off
s_cbranch_scc0 .LBB0_5
.LBB0_6:
s_load_b64 s[8:9], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s1, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_cmp_lt_i32 s1, 1
global_load_b32 v0, v[2:3], off
v_mov_b32_e32 v2, 0
ds_load_b32 v2, v2
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v0, s6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, v0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v0, v2, v0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v2, v0
s_cbranch_scc1 .LBB0_11
s_cmp_eq_u32 s1, 1
s_cbranch_scc0 .LBB0_12
v_cvt_f32_i32_e32 v2, s5
v_cmp_ngt_f32_e32 vcc_lo, 0, v0
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_nge_f32_e64 s0, v0, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s0
s_xor_b32 s0, exec_lo, s7
s_mov_b32 s6, exec_lo
v_cvt_i32_f32_e32 v2, v0
s_or_b32 exec_lo, exec_lo, s0
s_branch .LBB0_13
.LBB0_11:
s_mov_b32 s0, -1
s_mov_b32 s6, 0
s_branch .LBB0_14
.LBB0_12:
s_mov_b32 s6, -1
.LBB0_13:
s_mov_b32 s0, 0
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_19
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_17
s_branch .LBB0_18
.LBB0_17:
s_add_i32 s5, s5, -1
v_max_f32_e32 v0, v0, v0
v_cvt_f32_i32_e32 v2, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_minmax_f32 v0, v0, v2, 0
v_floor_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v0
.LBB0_18:
s_mov_b32 s6, -1
.LBB0_19:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_mov_b32_e32 v2, 1.0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15ThresholdKernelffiPfS_ii
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15ThresholdKernelffiPfS_ii, .Lfunc_end0-_Z15ThresholdKernelffiPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15ThresholdKernelffiPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15ThresholdKernelffiPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ThresholdKernel(float min, float max, int mode, float* input, float* output, int size, int count)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
__shared__ float delta;
if(id < size)
{
if (threadIdx.x == 0)
delta = (max - min)/count;
__syncthreads();
for (int i = 0; i < count; i++)
output[i * size + id] = 0;
int idx;
float fidx = ((input[id] - min) / delta);
switch (mode)
{
case 0: // consider values outside of the interval <min,max>
idx = (int)floor(fmaxf(0, fminf(fidx, count - 1)));
break;
case 1: // strict threshold
if (fidx < 0.0f || fidx >= count)
{
return;
}
idx = (int)fidx;
break;
}
output[idx * size + id] = 1.0f;
}
} | .text
.file "ThresholdKernel.hip"
.globl _Z30__device_stub__ThresholdKernelffiPfS_ii # -- Begin function _Z30__device_stub__ThresholdKernelffiPfS_ii
.p2align 4, 0x90
.type _Z30__device_stub__ThresholdKernelffiPfS_ii,@function
_Z30__device_stub__ThresholdKernelffiPfS_ii: # @_Z30__device_stub__ThresholdKernelffiPfS_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15ThresholdKernelffiPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__ThresholdKernelffiPfS_ii, .Lfunc_end0-_Z30__device_stub__ThresholdKernelffiPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15ThresholdKernelffiPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15ThresholdKernelffiPfS_ii,@object # @_Z15ThresholdKernelffiPfS_ii
.section .rodata,"a",@progbits
.globl _Z15ThresholdKernelffiPfS_ii
.p2align 3, 0x0
_Z15ThresholdKernelffiPfS_ii:
.quad _Z30__device_stub__ThresholdKernelffiPfS_ii
.size _Z15ThresholdKernelffiPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15ThresholdKernelffiPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__ThresholdKernelffiPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15ThresholdKernelffiPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000b441_00000000-6_ThresholdKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15ThresholdKernelffiPfS_iiffiPfS_ii
.type _Z42__device_stub__Z15ThresholdKernelffiPfS_iiffiPfS_ii, @function
_Z42__device_stub__Z15ThresholdKernelffiPfS_iiffiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movl %edi, 36(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15ThresholdKernelffiPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15ThresholdKernelffiPfS_iiffiPfS_ii, .-_Z42__device_stub__Z15ThresholdKernelffiPfS_iiffiPfS_ii
.globl _Z15ThresholdKernelffiPfS_ii
.type _Z15ThresholdKernelffiPfS_ii, @function
_Z15ThresholdKernelffiPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15ThresholdKernelffiPfS_iiffiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15ThresholdKernelffiPfS_ii, .-_Z15ThresholdKernelffiPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15ThresholdKernelffiPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15ThresholdKernelffiPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ThresholdKernel.hip"
.globl _Z30__device_stub__ThresholdKernelffiPfS_ii # -- Begin function _Z30__device_stub__ThresholdKernelffiPfS_ii
.p2align 4, 0x90
.type _Z30__device_stub__ThresholdKernelffiPfS_ii,@function
_Z30__device_stub__ThresholdKernelffiPfS_ii: # @_Z30__device_stub__ThresholdKernelffiPfS_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15ThresholdKernelffiPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__ThresholdKernelffiPfS_ii, .Lfunc_end0-_Z30__device_stub__ThresholdKernelffiPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15ThresholdKernelffiPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15ThresholdKernelffiPfS_ii,@object # @_Z15ThresholdKernelffiPfS_ii
.section .rodata,"a",@progbits
.globl _Z15ThresholdKernelffiPfS_ii
.p2align 3, 0x0
_Z15ThresholdKernelffiPfS_ii:
.quad _Z30__device_stub__ThresholdKernelffiPfS_ii
.size _Z15ThresholdKernelffiPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15ThresholdKernelffiPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__ThresholdKernelffiPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15ThresholdKernelffiPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define PI 3.141592
void write_file(char* filename, int size, float* image){
// writing the file
int i;
FILE* fptr = fopen(filename, "w");
if(fptr == NULL){
printf("Error: could not open the image file\n");
}
fprintf(fptr, "P2\n");
fprintf(fptr, "%d %d\n", size, size);
for(i = 0; i < size*size; i++){
fprintf(fptr, "%d\n", (int)image[i]);
}
fclose(fptr);
}
struct Myimage
{
int size;
int * image;
};
__host__ Myimage read_file(char* filename){
FILE* file = fopen(filename, "r");
char* n;
int i;
Myimage img;
int j = 0;
if(file == NULL){
printf("Error: could not open the image file\n");
}
fscanf(file, "%s", &n);
fscanf (file, "%d %d", &img.size, &img.size);
img.image = (int *)malloc(img.size * img.size * sizeof(int));
while (!feof (file)){
fscanf(file, "%d", &i);
img.image[j] = i;
j++;
}
fclose (file);
return img;
}
__host__ void kernel_gauss(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1/(s*sqrt(2*PI))*exp(-y/(2*(s^2)));
}
}
__host__ void kernel_boite(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1;
}
}
__host__ void kernel_bilateral(int r, float* w){
for (int y=0; y<256; y++){
w[y] = 1/(r*sqrt(2*PI))*exp(-(y^2)/(2*(r^2)));
}
}
__global__ void Filtre(int N, int s, float* S, float* w){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2];
sum2 += w[(x1-y1)^2 + (x2-y2)^2];
}
}
S[i]= sum1/sum2;
}
}
__global__ void filtre_dilat(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = max(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void filtre_erosion(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = min(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void Filtre_bilateral(int N, int s, float* S, float* w, float* w_r){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
sum2 += w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
}
}
S[i]= sum1/sum2;
}
}
int main(int argc, char *argv[]){
int s = atoi(argv[1]);
int r = (argc==6)? atoi(argv[5]): 25;
char* kernel = argv[2];
char* input_image = argv[3];
char* output_image = argv[4];
Myimage img = read_file(input_image);
int numFilter = s*sizeof(float);
int N=img.size;
int numBytes = N*sizeof(float);
float* S_cpu=(float *)malloc(N * N * sizeof(float));
for(int i = 0; i < N*N; ++i) {
S_cpu[i] = (float)img.image[i];
}
float* S_GPU;
cudaMalloc((void**)&S_GPU, numBytes);
cudaMemcpy(S_GPU, S_cpu, numBytes, cudaMemcpyHostToDevice);
float* w_cpu= (float*) calloc(s, sizeof(float));
float* w_GPU;
if (strcmp(kernel, "g")==0){
kernel_gauss(s, w_cpu);
}else if(strcmp(kernel, "b")==0){
kernel_boite(s, w_cpu);
}else if(strcmp(kernel, "bl")==0){
int numFilter_bl = 256*sizeof(float);
float w_r_cpu[256];
float w_r_GPU[256];
kernel_gauss(s, w_cpu);
kernel_bilateral(r, w_r_cpu);
cudaMalloc((void**)&w_GPU, numFilter);
cudaMemcpy(w_GPU, w_cpu, numFilter, cudaMemcpyHostToDevice);
cudaMalloc((void**)&w_r_GPU, numFilter_bl);
cudaMemcpy(w_r_GPU, w_r_cpu, numFilter_bl, cudaMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre_bilateral<<<nblocks,256>>>(N, s, S_GPU, w_GPU, w_r_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "e")==0){
int nblocks = (N + 255)/256;
filtre_erosion<<<nblocks,256>>>(N, s, S_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "d")==0){
int nblocks = (N + 255)/256;
filtre_dilat<<<nblocks,256>>>(N, s, S_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else{
printf("Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'.");
return EXIT_FAILURE;
}
cudaMalloc((void**)&w_GPU, numFilter);
cudaMemcpy(w_GPU, w_cpu, numFilter, cudaMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre<<<nblocks,256>>>(N, s, S_GPU, w_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
} | .file "tmpxft_0012e7d5_00000000-6_image.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error: could not open the image file\n"
.section .rodata.str1.1
.LC2:
.string "P2\n"
.LC3:
.string "%d %d\n"
.LC4:
.string "%d\n"
.text
.globl _Z10write_filePciPf
.type _Z10write_filePciPf, @function
_Z10write_filePciPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %esi, %ebx
movq %rdx, %r12
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L9
.L4:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %r8d
movl %ebx, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %eax
imull %ebx, %eax
testl %eax, %eax
jle .L5
movq %r12, %rbx
cltq
leaq (%r12,%rax,4), %r13
leaq .LC4(%rip), %r12
.L6:
cvttss2sil (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L6
.L5:
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z10write_filePciPf, .-_Z10write_filePciPf
.section .rodata.str1.1
.LC5:
.string "r"
.LC6:
.string "%s"
.LC7:
.string "%d %d"
.LC8:
.string "%d"
.text
.globl _Z9read_filePc
.type _Z9read_filePc, @function
_Z9read_filePc:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L16
.L11:
leaq 8(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 16(%rsp), %rdx
movq %rdx, %rcx
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 16(%rsp), %edi
imull %edi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movl $0, %ebx
leaq .LC8(%rip), %r12
jmp .L12
.L16:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L13:
leaq 4(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %edx
movq 24(%rsp), %rax
movl %edx, (%rax,%rbx)
addq $4, %rbx
.L12:
movq %rbp, %rdi
call feof@PLT
testl %eax, %eax
je .L13
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
movq 40(%rsp), %rcx
subq %fs:40, %rcx
jne .L17
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9read_filePc, .-_Z9read_filePc
.globl _Z12kernel_gaussiPf
.type _Z12kernel_gaussiPf, @function
_Z12kernel_gaussiPf:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L23
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %r13
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
mulsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
movl %edi, %ebp
xorl $2, %ebp
addl %ebp, %ebp
movslq %edi, %r12
movl $0, %ebx
.L20:
movl %ebx, %eax
negl %eax
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
call exp@PLT
mulsd 8(%rsp), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rbx,4)
addq $1, %rbx
cmpq %r12, %rbx
jne .L20
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2059:
.size _Z12kernel_gaussiPf, .-_Z12kernel_gaussiPf
.globl _Z12kernel_boiteiPf
.type _Z12kernel_boiteiPf, @function
_Z12kernel_boiteiPf:
.LFB2060:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L26
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,4), %rdx
movss .LC11(%rip), %xmm0
.L28:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L28
.L26:
ret
.cfi_endproc
.LFE2060:
.size _Z12kernel_boiteiPf, .-_Z12kernel_boiteiPf
.globl _Z16kernel_bilateraliPf
.type _Z16kernel_bilateraliPf, @function
_Z16kernel_bilateraliPf:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
mulsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
xorl $2, %edi
leal (%rdi,%rdi), %ebp
movl $0, %ebx
.L31:
movl %ebx, %eax
xorl $2, %eax
negl %eax
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
call exp@PLT
mulsd 8(%rsp), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq $256, %rbx
jne .L31
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16kernel_bilateraliPf, .-_Z16kernel_bilateraliPf
.globl _Z29__device_stub__Z6FiltreiiPfS_iiPfS_
.type _Z29__device_stub__Z6FiltreiiPfS_iiPfS_, @function
_Z29__device_stub__Z6FiltreiiPfS_iiPfS_:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6FiltreiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z29__device_stub__Z6FiltreiiPfS_iiPfS_, .-_Z29__device_stub__Z6FiltreiiPfS_iiPfS_
.globl _Z6FiltreiiPfS_
.type _Z6FiltreiiPfS_, @function
_Z6FiltreiiPfS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6FiltreiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z6FiltreiiPfS_, .-_Z6FiltreiiPfS_
.globl _Z34__device_stub__Z12filtre_dilatiiPfiiPf
.type _Z34__device_stub__Z12filtre_dilatiiPfiiPf, @function
_Z34__device_stub__Z12filtre_dilatiiPfiiPf:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12filtre_dilatiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z34__device_stub__Z12filtre_dilatiiPfiiPf, .-_Z34__device_stub__Z12filtre_dilatiiPfiiPf
.globl _Z12filtre_dilatiiPf
.type _Z12filtre_dilatiiPf, @function
_Z12filtre_dilatiiPf:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12filtre_dilatiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z12filtre_dilatiiPf, .-_Z12filtre_dilatiiPf
.globl _Z36__device_stub__Z14filtre_erosioniiPfiiPf
.type _Z36__device_stub__Z14filtre_erosioniiPfiiPf, @function
_Z36__device_stub__Z14filtre_erosioniiPfiiPf:
.LFB2091:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14filtre_erosioniiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z36__device_stub__Z14filtre_erosioniiPfiiPf, .-_Z36__device_stub__Z14filtre_erosioniiPfiiPf
.globl _Z14filtre_erosioniiPf
.type _Z14filtre_erosioniiPf, @function
_Z14filtre_erosioniiPf:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14filtre_erosioniiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z14filtre_erosioniiPf, .-_Z14filtre_erosioniiPf
.globl _Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_
.type _Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_, @function
_Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16Filtre_bilateraliiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_, .-_Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_
.globl _Z16Filtre_bilateraliiPfS_S_
.type _Z16Filtre_bilateraliiPfS_S_, @function
_Z16Filtre_bilateraliiPfS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z16Filtre_bilateraliiPfS_S_, .-_Z16Filtre_bilateraliiPfS_S_
.section .rodata.str1.1
.LC12:
.string "g"
.LC13:
.string "b"
.LC14:
.string "bl"
.LC15:
.string "e"
.LC16:
.string "d"
.section .rodata.str1.8
.align 8
.LC17:
.string "Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'."
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2168, %rsp
.cfi_def_cfa_offset 2224
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 2152(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 28(%rsp)
movl $25, 44(%rsp)
cmpl $6, %r12d
je .L85
.L67:
movq 16(%rbp), %r14
movq 32(%rbp), %rax
movq %rax, 32(%rsp)
movq 24(%rbp), %rdi
call _Z9read_filePc
movq %rdx, %r13
movq %rax, %r12
movslq %ebx, %rax
movq %rax, 16(%rsp)
leal 0(,%rbx,4), %eax
movl %eax, 40(%rsp)
movl %r12d, 12(%rsp)
leal 0(,%r12,4), %eax
movl %eax, 24(%rsp)
movl %r12d, %r15d
imull %r12d, %r15d
movslq %r15d, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L68
movl $0, %eax
.L69:
pxor %xmm0, %xmm0
cvtsi2ssl 0(%r13,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rax, %rbp
jne .L69
.L68:
movslq 24(%rsp), %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %esi
movq 16(%rsp), %rdi
call calloc@PLT
movq %rax, %r15
leaq .LC12(%rip), %rsi
movq %r14, %rdi
call strcmp@PLT
testl %eax, %eax
je .L86
leaq .LC13(%rip), %rsi
movq %r14, %rdi
call strcmp@PLT
testl %eax, %eax
je .L87
leaq .LC14(%rip), %rsi
movq %r14, %rdi
call strcmp@PLT
movl %eax, %r13d
testl %eax, %eax
je .L88
leaq .LC15(%rip), %rsi
movq %r14, %rdi
call strcmp@PLT
movl %eax, %r13d
testl %eax, %eax
je .L89
leaq .LC16(%rip), %rsi
movq %r14, %rdi
call strcmp@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L78
movl $256, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leal 255(%r12), %eax
movl $256, %ecx
cltd
idivl %ecx
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L90
.L79:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl 12(%rsp), %esi
movq 32(%rsp), %rdi
call _Z10write_filePciPf
jmp .L75
.L85:
movq 40(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 44(%rsp)
jmp .L67
.L86:
movq %r15, %rsi
movl 28(%rsp), %edi
call _Z12kernel_gaussiPf
.L71:
movslq 40(%rsp), %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leal 255(%r12), %eax
movl $256, %ecx
cltd
idivl %ecx
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L91
.L80:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl 12(%rsp), %esi
movq 32(%rsp), %rdi
call _Z10write_filePciPf
movl $0, %r13d
.L75:
movq 2152(%rsp), %rax
subq %fs:40, %rax
jne .L92
movl %r13d, %eax
addq $2168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
movq %r15, %rsi
movl 28(%rsp), %edi
call _Z12kernel_boiteiPf
jmp .L71
.L88:
movq %r15, %rsi
movl 28(%rsp), %edi
call _Z12kernel_gaussiPf
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
movq %rax, %rsi
movl 44(%rsp), %edi
call _Z16kernel_bilateraliPf
movslq 40(%rsp), %r14
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1120(%rsp), %r14
movl $1024, %esi
movq %r14, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $256, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leal 255(%r12), %eax
movl $256, %ecx
cltd
idivl %ecx
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L74:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl 12(%rsp), %esi
movq 32(%rsp), %rdi
call _Z10write_filePciPf
jmp .L75
.L93:
movq %r14, %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl 28(%rsp), %esi
movl 12(%rsp), %edi
call _Z42__device_stub__Z16Filtre_bilateraliiPfS_S_iiPfS_S_
jmp .L74
.L89:
movl $256, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leal 255(%r12), %eax
movl $256, %ecx
cltd
idivl %ecx
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L77:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl 12(%rsp), %esi
movq 32(%rsp), %rdi
call _Z10write_filePciPf
jmp .L75
.L94:
movq 56(%rsp), %rdx
movl 28(%rsp), %esi
movl 12(%rsp), %edi
call _Z36__device_stub__Z14filtre_erosioniiPfiiPf
jmp .L77
.L90:
movq 56(%rsp), %rdx
movl 28(%rsp), %esi
movl 12(%rsp), %edi
call _Z34__device_stub__Z12filtre_dilatiiPfiiPf
jmp .L79
.L78:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r13d
jmp .L75
.L91:
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl 28(%rsp), %esi
movl 12(%rsp), %edi
call _Z29__device_stub__Z6FiltreiiPfS_iiPfS_
jmp .L80
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z16Filtre_bilateraliiPfS_S_"
.LC19:
.string "_Z14filtre_erosioniiPf"
.LC20:
.string "_Z12filtre_dilatiiPf"
.LC21:
.string "_Z6FiltreiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z16Filtre_bilateraliiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z14filtre_erosioniiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z12filtre_dilatiiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z6FiltreiiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long -50919136
.long 1074007442
.align 8
.LC10:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define PI 3.141592
void write_file(char* filename, int size, float* image){
// writing the file
int i;
FILE* fptr = fopen(filename, "w");
if(fptr == NULL){
printf("Error: could not open the image file\n");
}
fprintf(fptr, "P2\n");
fprintf(fptr, "%d %d\n", size, size);
for(i = 0; i < size*size; i++){
fprintf(fptr, "%d\n", (int)image[i]);
}
fclose(fptr);
}
struct Myimage
{
int size;
int * image;
};
__host__ Myimage read_file(char* filename){
FILE* file = fopen(filename, "r");
char* n;
int i;
Myimage img;
int j = 0;
if(file == NULL){
printf("Error: could not open the image file\n");
}
fscanf(file, "%s", &n);
fscanf (file, "%d %d", &img.size, &img.size);
img.image = (int *)malloc(img.size * img.size * sizeof(int));
while (!feof (file)){
fscanf(file, "%d", &i);
img.image[j] = i;
j++;
}
fclose (file);
return img;
}
__host__ void kernel_gauss(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1/(s*sqrt(2*PI))*exp(-y/(2*(s^2)));
}
}
__host__ void kernel_boite(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1;
}
}
__host__ void kernel_bilateral(int r, float* w){
for (int y=0; y<256; y++){
w[y] = 1/(r*sqrt(2*PI))*exp(-(y^2)/(2*(r^2)));
}
}
__global__ void Filtre(int N, int s, float* S, float* w){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2];
sum2 += w[(x1-y1)^2 + (x2-y2)^2];
}
}
S[i]= sum1/sum2;
}
}
__global__ void filtre_dilat(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = max(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void filtre_erosion(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = min(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void Filtre_bilateral(int N, int s, float* S, float* w, float* w_r){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
sum2 += w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
}
}
S[i]= sum1/sum2;
}
}
int main(int argc, char *argv[]){
int s = atoi(argv[1]);
int r = (argc==6)? atoi(argv[5]): 25;
char* kernel = argv[2];
char* input_image = argv[3];
char* output_image = argv[4];
Myimage img = read_file(input_image);
int numFilter = s*sizeof(float);
int N=img.size;
int numBytes = N*sizeof(float);
float* S_cpu=(float *)malloc(N * N * sizeof(float));
for(int i = 0; i < N*N; ++i) {
S_cpu[i] = (float)img.image[i];
}
float* S_GPU;
cudaMalloc((void**)&S_GPU, numBytes);
cudaMemcpy(S_GPU, S_cpu, numBytes, cudaMemcpyHostToDevice);
float* w_cpu= (float*) calloc(s, sizeof(float));
float* w_GPU;
if (strcmp(kernel, "g")==0){
kernel_gauss(s, w_cpu);
}else if(strcmp(kernel, "b")==0){
kernel_boite(s, w_cpu);
}else if(strcmp(kernel, "bl")==0){
int numFilter_bl = 256*sizeof(float);
float w_r_cpu[256];
float w_r_GPU[256];
kernel_gauss(s, w_cpu);
kernel_bilateral(r, w_r_cpu);
cudaMalloc((void**)&w_GPU, numFilter);
cudaMemcpy(w_GPU, w_cpu, numFilter, cudaMemcpyHostToDevice);
cudaMalloc((void**)&w_r_GPU, numFilter_bl);
cudaMemcpy(w_r_GPU, w_r_cpu, numFilter_bl, cudaMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre_bilateral<<<nblocks,256>>>(N, s, S_GPU, w_GPU, w_r_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "e")==0){
int nblocks = (N + 255)/256;
filtre_erosion<<<nblocks,256>>>(N, s, S_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "d")==0){
int nblocks = (N + 255)/256;
filtre_dilat<<<nblocks,256>>>(N, s, S_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else{
printf("Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'.");
return EXIT_FAILURE;
}
cudaMalloc((void**)&w_GPU, numFilter);
cudaMemcpy(w_GPU, w_cpu, numFilter, cudaMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre<<<nblocks,256>>>(N, s, S_GPU, w_GPU);
cudaMemcpy(S_cpu, S_GPU, numBytes, cudaMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define PI 3.141592
void write_file(char* filename, int size, float* image){
// writing the file
int i;
FILE* fptr = fopen(filename, "w");
if(fptr == NULL){
printf("Error: could not open the image file\n");
}
fprintf(fptr, "P2\n");
fprintf(fptr, "%d %d\n", size, size);
for(i = 0; i < size*size; i++){
fprintf(fptr, "%d\n", (int)image[i]);
}
fclose(fptr);
}
struct Myimage
{
int size;
int * image;
};
__host__ Myimage read_file(char* filename){
FILE* file = fopen(filename, "r");
char* n;
int i;
Myimage img;
int j = 0;
if(file == NULL){
printf("Error: could not open the image file\n");
}
fscanf(file, "%s", &n);
fscanf (file, "%d %d", &img.size, &img.size);
img.image = (int *)malloc(img.size * img.size * sizeof(int));
while (!feof (file)){
fscanf(file, "%d", &i);
img.image[j] = i;
j++;
}
fclose (file);
return img;
}
__host__ void kernel_gauss(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1/(s*sqrt(2*PI))*exp(-y/(2*(s^2)));
}
}
__host__ void kernel_boite(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1;
}
}
__host__ void kernel_bilateral(int r, float* w){
for (int y=0; y<256; y++){
w[y] = 1/(r*sqrt(2*PI))*exp(-(y^2)/(2*(r^2)));
}
}
__global__ void Filtre(int N, int s, float* S, float* w){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2];
sum2 += w[(x1-y1)^2 + (x2-y2)^2];
}
}
S[i]= sum1/sum2;
}
}
__global__ void filtre_dilat(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = max(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void filtre_erosion(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = min(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void Filtre_bilateral(int N, int s, float* S, float* w, float* w_r){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
sum2 += w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
}
}
S[i]= sum1/sum2;
}
}
int main(int argc, char *argv[]){
int s = atoi(argv[1]);
int r = (argc==6)? atoi(argv[5]): 25;
char* kernel = argv[2];
char* input_image = argv[3];
char* output_image = argv[4];
Myimage img = read_file(input_image);
int numFilter = s*sizeof(float);
int N=img.size;
int numBytes = N*sizeof(float);
float* S_cpu=(float *)malloc(N * N * sizeof(float));
for(int i = 0; i < N*N; ++i) {
S_cpu[i] = (float)img.image[i];
}
float* S_GPU;
hipMalloc((void**)&S_GPU, numBytes);
hipMemcpy(S_GPU, S_cpu, numBytes, hipMemcpyHostToDevice);
float* w_cpu= (float*) calloc(s, sizeof(float));
float* w_GPU;
if (strcmp(kernel, "g")==0){
kernel_gauss(s, w_cpu);
}else if(strcmp(kernel, "b")==0){
kernel_boite(s, w_cpu);
}else if(strcmp(kernel, "bl")==0){
int numFilter_bl = 256*sizeof(float);
float w_r_cpu[256];
float w_r_GPU[256];
kernel_gauss(s, w_cpu);
kernel_bilateral(r, w_r_cpu);
hipMalloc((void**)&w_GPU, numFilter);
hipMemcpy(w_GPU, w_cpu, numFilter, hipMemcpyHostToDevice);
hipMalloc((void**)&w_r_GPU, numFilter_bl);
hipMemcpy(w_r_GPU, w_r_cpu, numFilter_bl, hipMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre_bilateral<<<nblocks,256>>>(N, s, S_GPU, w_GPU, w_r_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "e")==0){
int nblocks = (N + 255)/256;
filtre_erosion<<<nblocks,256>>>(N, s, S_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "d")==0){
int nblocks = (N + 255)/256;
filtre_dilat<<<nblocks,256>>>(N, s, S_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else{
printf("Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'.");
return EXIT_FAILURE;
}
hipMalloc((void**)&w_GPU, numFilter);
hipMemcpy(w_GPU, w_cpu, numFilter, hipMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre<<<nblocks,256>>>(N, s, S_GPU, w_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define PI 3.141592
void write_file(char* filename, int size, float* image){
// writing the file
int i;
FILE* fptr = fopen(filename, "w");
if(fptr == NULL){
printf("Error: could not open the image file\n");
}
fprintf(fptr, "P2\n");
fprintf(fptr, "%d %d\n", size, size);
for(i = 0; i < size*size; i++){
fprintf(fptr, "%d\n", (int)image[i]);
}
fclose(fptr);
}
struct Myimage
{
int size;
int * image;
};
__host__ Myimage read_file(char* filename){
FILE* file = fopen(filename, "r");
char* n;
int i;
Myimage img;
int j = 0;
if(file == NULL){
printf("Error: could not open the image file\n");
}
fscanf(file, "%s", &n);
fscanf (file, "%d %d", &img.size, &img.size);
img.image = (int *)malloc(img.size * img.size * sizeof(int));
while (!feof (file)){
fscanf(file, "%d", &i);
img.image[j] = i;
j++;
}
fclose (file);
return img;
}
__host__ void kernel_gauss(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1/(s*sqrt(2*PI))*exp(-y/(2*(s^2)));
}
}
__host__ void kernel_boite(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1;
}
}
__host__ void kernel_bilateral(int r, float* w){
for (int y=0; y<256; y++){
w[y] = 1/(r*sqrt(2*PI))*exp(-(y^2)/(2*(r^2)));
}
}
__global__ void Filtre(int N, int s, float* S, float* w){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2];
sum2 += w[(x1-y1)^2 + (x2-y2)^2];
}
}
S[i]= sum1/sum2;
}
}
__global__ void filtre_dilat(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = max(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void filtre_erosion(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = min(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void Filtre_bilateral(int N, int s, float* S, float* w, float* w_r){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
sum2 += w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
}
}
S[i]= sum1/sum2;
}
}
int main(int argc, char *argv[]){
int s = atoi(argv[1]);
int r = (argc==6)? atoi(argv[5]): 25;
char* kernel = argv[2];
char* input_image = argv[3];
char* output_image = argv[4];
Myimage img = read_file(input_image);
int numFilter = s*sizeof(float);
int N=img.size;
int numBytes = N*sizeof(float);
float* S_cpu=(float *)malloc(N * N * sizeof(float));
for(int i = 0; i < N*N; ++i) {
S_cpu[i] = (float)img.image[i];
}
float* S_GPU;
hipMalloc((void**)&S_GPU, numBytes);
hipMemcpy(S_GPU, S_cpu, numBytes, hipMemcpyHostToDevice);
float* w_cpu= (float*) calloc(s, sizeof(float));
float* w_GPU;
if (strcmp(kernel, "g")==0){
kernel_gauss(s, w_cpu);
}else if(strcmp(kernel, "b")==0){
kernel_boite(s, w_cpu);
}else if(strcmp(kernel, "bl")==0){
int numFilter_bl = 256*sizeof(float);
float w_r_cpu[256];
float w_r_GPU[256];
kernel_gauss(s, w_cpu);
kernel_bilateral(r, w_r_cpu);
hipMalloc((void**)&w_GPU, numFilter);
hipMemcpy(w_GPU, w_cpu, numFilter, hipMemcpyHostToDevice);
hipMalloc((void**)&w_r_GPU, numFilter_bl);
hipMemcpy(w_r_GPU, w_r_cpu, numFilter_bl, hipMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre_bilateral<<<nblocks,256>>>(N, s, S_GPU, w_GPU, w_r_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "e")==0){
int nblocks = (N + 255)/256;
filtre_erosion<<<nblocks,256>>>(N, s, S_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "d")==0){
int nblocks = (N + 255)/256;
filtre_dilat<<<nblocks,256>>>(N, s, S_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else{
printf("Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'.");
return EXIT_FAILURE;
}
hipMalloc((void**)&w_GPU, numFilter);
hipMemcpy(w_GPU, w_cpu, numFilter, hipMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre<<<nblocks,256>>>(N, s, S_GPU, w_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6FiltreiiPfS_
.globl _Z6FiltreiiPfS_
.p2align 8
.type _Z6FiltreiiPfS_,@function
_Z6FiltreiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_10
s_add_i32 s2, s6, 1
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s3, s2, 31
s_load_b32 s9, s[0:1], 0x4
s_add_i32 s2, s2, s3
s_mov_b32 s8, 0
s_xor_b32 s2, s2, s3
s_mov_b32 s7, exec_lo
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s4, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s4, v0
v_mul_hi_u32 v4, v0, v3
v_add_nc_u32_e32 v3, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v2
v_add_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v3, v0
v_mul_lo_u32 v4, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v3, v4
v_subrev_nc_u32_e32 v6, s2, v4
v_cmp_le_u32_e32 vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v6, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s2, v4
v_add_nc_u32_e32 v5, 1, v0
s_load_b64 s[2:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v6
v_mov_b32_e32 v6, 0x7fc00000
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v4, s9, v0
v_add_nc_u32_e32 v5, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB0_9
s_ashr_i32 s4, s6, 31
v_mul_lo_u32 v10, s6, v4
s_add_i32 s5, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s5, s4
v_cvt_f32_u32_e32 v6, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_cvt_u32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, s5, v6
v_mul_hi_u32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, v6, v7
v_mul_hi_u32 v6, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v6, s4
v_sub_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_load_b64 s[4:5], s[0:1], 0x10
s_add_i32 s1, s9, 2
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_mov_b32 v6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v2
v_sub_nc_u32_e32 v2, v3, v2
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v8, s9, v2
v_add_nc_u32_e32 v9, s9, v2
v_cmp_lt_i32_e32 vcc_lo, v8, v9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v4, 1, v4
v_add_nc_u32_e32 v10, s6, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v4, v5
s_or_b32 s8, s0, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_8
.LBB0_4:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_3
v_sub_nc_u32_e32 v11, v0, v4
v_mov_b32_e32 v12, v8
s_mov_b32 s10, 0
s_mov_b32 s11, s1
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v10, v12
v_xor3_b32 v13, s11, 2, v11
s_add_i32 s11, s11, -1
v_sub_nc_u32_e32 v15, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v13
v_max_i32_e32 v2, v2, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_lshlrev_b64 v[15:16], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s0, s4, v13
v_add_co_ci_u32_e64 v14, s0, s5, v14, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v15, s0, s2, v15
v_add_co_ci_u32_e64 v16, s0, s3, v16, s0
global_load_b32 v2, v[13:14], off
global_load_b32 v13, v[15:16], off
s_waitcnt vmcnt(1)
v_dual_add_f32 v7, v7, v2 :: v_dual_add_nc_u32 v12, 1, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e64 s0, v12, v9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v13, v2
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s10
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
v_div_scale_f32 v0, null, v7, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v0, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
v_div_scale_f32 v3, vcc_lo, v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v3, v2
v_fma_f32 v5, -v0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v2
v_fma_f32 v0, -v0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v0, v0, v2, v4
v_div_fixup_f32 v6, v0, v7, v6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6FiltreiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6FiltreiiPfS_, .Lfunc_end0-_Z6FiltreiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12filtre_dilatiiPf
.globl _Z12filtre_dilatiiPf
.p2align 8
.type _Z12filtre_dilatiiPf,@function
_Z12filtre_dilatiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB1_10
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s5, s4, 1
s_load_b32 s0, s[0:1], 0x4
s_ashr_i32 s6, s5, 31
s_mov_b32 s1, exec_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s6
v_cvt_f32_u32_e32 v3, s5
s_sub_i32 s7, 0, s5
s_delay_alu instid0(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
global_load_b32 v4, v[0:1], off
v_cvt_u32_f32_e32 v5, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s7, v5
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v3
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v5, s5
v_add_nc_u32_e32 v7, 1, v5
v_sub_nc_u32_e32 v6, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s5, v6
v_cmp_le_u32_e32 vcc_lo, s5, v6
v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v5, v5, v7
v_xor_b32_e32 v8, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v6
v_add_nc_u32_e32 v7, 1, v5
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_xor_b32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v5, v8
v_subrev_nc_u32_e32 v5, s0, v6
v_add_nc_u32_e32 v6, s0, v6
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e64 v5, v6
s_cbranch_execz .LBB1_9
s_ashr_i32 s6, s4, 31
v_mul_lo_u32 v9, s4, v5
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v7, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x4f7ffffe, v7
v_cvt_u32_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, s7, v7
v_mul_hi_u32 v8, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v8
v_mul_hi_u32 v7, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, v7, s6
v_sub_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v7, s0, v2
v_add_nc_u32_e32 v8, s0, v2
v_cmp_lt_i32_e32 vcc_lo, v7, v8
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v5, 1, v5
v_add_nc_u32_e32 v9, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v5, v6
s_or_b32 s5, s0, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_8
.LBB1_4:
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_3
v_mov_b32_e32 v10, v7
s_mov_b32 s7, 0
.p2align 6
.LBB1_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v9, v10
v_add_nc_u32_e32 v10, 1, v10
v_sub_nc_u32_e32 v11, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v2, v11
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s2, v11
v_add_co_ci_u32_e64 v12, s0, s3, v12, s0
v_cmp_ge_i32_e64 s0, v10, v8
global_load_b32 v2, v[11:12], off
s_or_b32 s7, s0, s7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v4, v4, v2
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_6
s_or_b32 exec_lo, exec_lo, s7
s_branch .LBB1_3
.LBB1_8:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB1_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s1
v_cvt_f32_i32_e32 v2, v4
global_store_b32 v[0:1], v2, off
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12filtre_dilatiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12filtre_dilatiiPf, .Lfunc_end1-_Z12filtre_dilatiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14filtre_erosioniiPf
.globl _Z14filtre_erosioniiPf
.p2align 8
.type _Z14filtre_erosioniiPf,@function
_Z14filtre_erosioniiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB2_10
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s5, s4, 1
s_load_b32 s0, s[0:1], 0x4
s_ashr_i32 s6, s5, 31
s_mov_b32 s1, exec_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s6
v_cvt_f32_u32_e32 v3, s5
s_sub_i32 s7, 0, s5
s_delay_alu instid0(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
global_load_b32 v4, v[0:1], off
v_cvt_u32_f32_e32 v5, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s7, v5
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v3
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v5, s5
v_add_nc_u32_e32 v7, 1, v5
v_sub_nc_u32_e32 v6, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s5, v6
v_cmp_le_u32_e32 vcc_lo, s5, v6
v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v5, v5, v7
v_xor_b32_e32 v8, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v6
v_add_nc_u32_e32 v7, 1, v5
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_xor_b32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v5, v8
v_subrev_nc_u32_e32 v5, s0, v6
v_add_nc_u32_e32 v6, s0, v6
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e64 v5, v6
s_cbranch_execz .LBB2_9
s_ashr_i32 s6, s4, 31
v_mul_lo_u32 v9, s4, v5
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v7, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x4f7ffffe, v7
v_cvt_u32_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, s7, v7
v_mul_hi_u32 v8, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v8
v_mul_hi_u32 v7, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, v7, s6
v_sub_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v7, s0, v2
v_add_nc_u32_e32 v8, s0, v2
v_cmp_lt_i32_e32 vcc_lo, v7, v8
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v5, 1, v5
v_add_nc_u32_e32 v9, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v5, v6
s_or_b32 s5, s0, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB2_8
.LBB2_4:
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB2_3
v_mov_b32_e32 v10, v7
s_mov_b32 s7, 0
.p2align 6
.LBB2_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v9, v10
v_add_nc_u32_e32 v10, 1, v10
v_sub_nc_u32_e32 v11, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v2, v11
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s2, v11
v_add_co_ci_u32_e64 v12, s0, s3, v12, s0
v_cmp_ge_i32_e64 s0, v10, v8
global_load_b32 v2, v[11:12], off
s_or_b32 s7, s0, s7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v4, v4, v2
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB2_6
s_or_b32 exec_lo, exec_lo, s7
s_branch .LBB2_3
.LBB2_8:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB2_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s1
v_cvt_f32_i32_e32 v2, v4
global_store_b32 v[0:1], v2, off
.LBB2_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14filtre_erosioniiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14filtre_erosioniiPf, .Lfunc_end2-_Z14filtre_erosioniiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16Filtre_bilateraliiPfS_S_
.globl _Z16Filtre_bilateraliiPfS_S_
.p2align 8
.type _Z16Filtre_bilateraliiPfS_S_,@function
_Z16Filtre_bilateraliiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB3_10
s_add_i32 s2, s8, 1
v_ashrrev_i32_e32 v3, 31, v1
s_ashr_i32 s3, s2, 31
s_load_b32 s11, s[0:1], 0x4
s_add_i32 s2, s2, s3
s_mov_b32 s10, 0
s_xor_b32 s2, s2, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s4, 0, s2
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v6, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v6, s3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_add_nc_u32_e32 v5, 1, v0
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_mov_b32 v5, 0x7fc00000
v_xor_b32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v6
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v10, s11, v0
v_add_nc_u32_e32 v11, s11, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v10, v11
s_cbranch_execz .LBB3_9
s_ashr_i32 s4, s8, 31
v_mul_lo_u32 v13, s8, v10
s_add_i32 s5, s8, s4
v_mov_b32_e32 v14, 0
s_xor_b32 s4, s5, s4
v_mov_b32_e32 v12, 0
v_cvt_f32_u32_e32 v5, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s5, v5
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s4
v_sub_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
s_load_b128 s[4:7], s[0:1], 0x10
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_sub_nc_u32_e32 v7, v4, v3
v_add_nc_u32_e32 v8, v4, v13
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v15, s11, v7
v_add_nc_u32_e32 v16, s11, v7
v_sub_nc_u32_e32 v3, v8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, v15, v16
v_subrev_nc_u32_e32 v7, s11, v3
s_add_i32 s11, s11, 2
s_branch .LBB3_4
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v10, 1, v10
v_add_nc_u32_e32 v13, s8, v13
v_add_nc_u32_e32 v7, s8, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v10, v11
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB3_8
.LBB3_4:
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB3_3
global_load_b32 v17, v[5:6], off
v_ashrrev_i32_e32 v8, 31, v7
v_sub_nc_u32_e32 v18, v0, v10
v_mov_b32_e32 v19, v15
s_mov_b32 s13, 0
s_mov_b32 s14, s11
v_lshlrev_b64 v[8:9], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s2, v8
v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
.LBB3_6:
global_load_b32 v24, v[8:9], off
v_add_nc_u32_e32 v3, v13, v19
v_xor3_b32 v20, s14, 2, v18
s_add_i32 s14, s14, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v22, 0, v3
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_i32_e32 v3, v3, v22
v_lshlrev_b64 v[20:21], 2, v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[22:23], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v20, s0, s4, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v21, s0, s5, v21, s0
v_add_co_u32 v22, s0, s2, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v23, s0, s3, v23, s0
global_load_b32 v22, v[22:23], off
s_waitcnt vmcnt(1)
v_sub_f32_e32 v3, v17, v24
v_cvt_i32_f32_e64 v24, |v3|
global_load_b32 v3, v[20:21], off
v_ashrrev_i32_e32 v25, 31, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[20:21], 2, v[24:25]
v_add_co_u32 v20, s0, s6, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v21, s0, s7, v21, s0
v_add_co_u32 v8, s0, v8, 4
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
global_load_b32 v20, v[20:21], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v21, v22, v3 :: v_dual_fmac_f32 v14, v3, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v12, v21, v20 :: v_dual_add_nc_u32 v19, 1, v19
v_cmp_ge_i32_e64 s1, v19, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s13, s1, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB3_6
s_or_b32 exec_lo, exec_lo, s13
s_branch .LBB3_3
.LBB3_8:
s_or_b32 exec_lo, exec_lo, s10
v_div_scale_f32 v0, null, v14, v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v0, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v12, v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v3
v_fma_f32 v6, -v0, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v3
v_fma_f32 v0, -v0, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v0, v0, v3, v5
v_div_fixup_f32 v5, v0, v14, v12
.LBB3_9:
s_or_b32 exec_lo, exec_lo, s9
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB3_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16Filtre_bilateraliiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16Filtre_bilateraliiPfS_S_, .Lfunc_end3-_Z16Filtre_bilateraliiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6FiltreiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6FiltreiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12filtre_dilatiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12filtre_dilatiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14filtre_erosioniiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14filtre_erosioniiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16Filtre_bilateraliiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16Filtre_bilateraliiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define PI 3.141592
void write_file(char* filename, int size, float* image){
// writing the file
int i;
FILE* fptr = fopen(filename, "w");
if(fptr == NULL){
printf("Error: could not open the image file\n");
}
fprintf(fptr, "P2\n");
fprintf(fptr, "%d %d\n", size, size);
for(i = 0; i < size*size; i++){
fprintf(fptr, "%d\n", (int)image[i]);
}
fclose(fptr);
}
struct Myimage
{
int size;
int * image;
};
__host__ Myimage read_file(char* filename){
FILE* file = fopen(filename, "r");
char* n;
int i;
Myimage img;
int j = 0;
if(file == NULL){
printf("Error: could not open the image file\n");
}
fscanf(file, "%s", &n);
fscanf (file, "%d %d", &img.size, &img.size);
img.image = (int *)malloc(img.size * img.size * sizeof(int));
while (!feof (file)){
fscanf(file, "%d", &i);
img.image[j] = i;
j++;
}
fclose (file);
return img;
}
__host__ void kernel_gauss(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1/(s*sqrt(2*PI))*exp(-y/(2*(s^2)));
}
}
__host__ void kernel_boite(int s, float* w){
for (int y=0; y<s; y++){
w[y] = 1;
}
}
__host__ void kernel_bilateral(int r, float* w){
for (int y=0; y<256; y++){
w[y] = 1/(r*sqrt(2*PI))*exp(-(y^2)/(2*(r^2)));
}
}
__global__ void Filtre(int N, int s, float* S, float* w){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2];
sum2 += w[(x1-y1)^2 + (x2-y2)^2];
}
}
S[i]= sum1/sum2;
}
}
__global__ void filtre_dilat(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = max(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void filtre_erosion(int N, int s, float* S){
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tmp = S[i];
if (i<N){
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
tmp = min(tmp ,(int)S[abs(y1*N+y2)]);
}
}
S[i] = tmp;
}
}
__global__ void Filtre_bilateral(int N, int s, float* S, float* w, float* w_r){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<N){
float sum1 = 0;
float sum2 = 0;
int y1;
int y2;
int x1 = i/(N+1);
int x2 = i%N;
for (y1=x1-s; y1<x1+s; y1++){
for (y2=x2-s; y2<x2+s; y2++){
sum1 += S[abs(y1*N+y2)]*w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
sum2 += w[(x1-y1)^2 + (x2-y2)^2]*w_r[(int)abs(S[i]-S[y1*N+y2])];
}
}
S[i]= sum1/sum2;
}
}
int main(int argc, char *argv[]){
int s = atoi(argv[1]);
int r = (argc==6)? atoi(argv[5]): 25;
char* kernel = argv[2];
char* input_image = argv[3];
char* output_image = argv[4];
Myimage img = read_file(input_image);
int numFilter = s*sizeof(float);
int N=img.size;
int numBytes = N*sizeof(float);
float* S_cpu=(float *)malloc(N * N * sizeof(float));
for(int i = 0; i < N*N; ++i) {
S_cpu[i] = (float)img.image[i];
}
float* S_GPU;
hipMalloc((void**)&S_GPU, numBytes);
hipMemcpy(S_GPU, S_cpu, numBytes, hipMemcpyHostToDevice);
float* w_cpu= (float*) calloc(s, sizeof(float));
float* w_GPU;
if (strcmp(kernel, "g")==0){
kernel_gauss(s, w_cpu);
}else if(strcmp(kernel, "b")==0){
kernel_boite(s, w_cpu);
}else if(strcmp(kernel, "bl")==0){
int numFilter_bl = 256*sizeof(float);
float w_r_cpu[256];
float w_r_GPU[256];
kernel_gauss(s, w_cpu);
kernel_bilateral(r, w_r_cpu);
hipMalloc((void**)&w_GPU, numFilter);
hipMemcpy(w_GPU, w_cpu, numFilter, hipMemcpyHostToDevice);
hipMalloc((void**)&w_r_GPU, numFilter_bl);
hipMemcpy(w_r_GPU, w_r_cpu, numFilter_bl, hipMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre_bilateral<<<nblocks,256>>>(N, s, S_GPU, w_GPU, w_r_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "e")==0){
int nblocks = (N + 255)/256;
filtre_erosion<<<nblocks,256>>>(N, s, S_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else if(strcmp(kernel, "d")==0){
int nblocks = (N + 255)/256;
filtre_dilat<<<nblocks,256>>>(N, s, S_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
}else{
printf("Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'.");
return EXIT_FAILURE;
}
hipMalloc((void**)&w_GPU, numFilter);
hipMemcpy(w_GPU, w_cpu, numFilter, hipMemcpyHostToDevice);
int nblocks = (N + 255)/256;
Filtre<<<nblocks,256>>>(N, s, S_GPU, w_GPU);
hipMemcpy(S_cpu, S_GPU, numBytes, hipMemcpyDeviceToHost);
write_file(output_image, N, S_cpu);
return 0;
} | .text
.file "image.hip"
.globl _Z10write_filePciPf # -- Begin function _Z10write_filePciPf
.p2align 4, 0x90
.type _Z10write_filePciPf,@function
_Z10write_filePciPf: # @_Z10write_filePciPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movl %esi, %r14d
movl $.L.str, %esi
callq fopen
movq %rax, %r15
testq %rax, %rax
jne .LBB0_2
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB0_2:
movl $.L.str.2, %edi
movl $3, %esi
movl $1, %edx
movq %r15, %rcx
callq fwrite@PLT
movl $.L.str.3, %esi
movq %r15, %rdi
movl %r14d, %edx
movl %r14d, %ecx
xorl %eax, %eax
callq fprintf
testl %r14d, %r14d
je .LBB0_5
# %bb.3: # %.lr.ph.preheader
imull %r14d, %r14d
cmpl $1, %r14d
adcl $0, %r14d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cvttss2si (%rbx,%r12,4), %edx
movl $.L.str.4, %esi
movq %r15, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
cmpq %r12, %r14
jne .LBB0_4
.LBB0_5: # %._crit_edge
movq %r15, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z10write_filePciPf, .Lfunc_end0-_Z10write_filePciPf
.cfi_endproc
# -- End function
.globl _Z9read_filePc # -- Begin function _Z9read_filePc
.p2align 4, 0x90
.type _Z9read_filePc,@function
_Z9read_filePc: # @_Z9read_filePc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB1_2
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_2:
leaq 24(%rsp), %rdx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
leaq 8(%rsp), %rcx
movl $.L.str.7, %esi
movq %rbx, %rdi
movq %rcx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, 16(%rsp)
movq %rbx, %rdi
callq feof
testl %eax, %eax
jne .LBB1_5
# %bb.3: # %.lr.ph.preheader
leaq 4(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
movq 16(%rsp), %rcx
movl %eax, (%rcx,%r15)
movq %rbx, %rdi
callq feof
addq $4, %r15
testl %eax, %eax
je .LBB1_4
.LBB1_5: # %._crit_edge
movq %rbx, %rdi
callq fclose
movl 8(%rsp), %eax
movq 16(%rsp), %rdx
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9read_filePc, .Lfunc_end1-_Z9read_filePc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12kernel_gaussiPf
.LCPI2_0:
.quad 0x40040d92fcf70920 # double 2.5066280138863846
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z12kernel_gaussiPf
.p2align 4, 0x90
.type _Z12kernel_gaussiPf,@function
_Z12kernel_gaussiPf: # @_Z12kernel_gaussiPf
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB2_4
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cvtsi2sd %edi, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
leal (%rdi,%rdi), %ebp
xorl $4, %ebp
movl %edi, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
cltd
idivl %ebp
negl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
callq exp
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z12kernel_gaussiPf, .Lfunc_end2-_Z12kernel_gaussiPf
.cfi_endproc
# -- End function
.globl _Z12kernel_boiteiPf # -- Begin function _Z12kernel_boiteiPf
.p2align 4, 0x90
.type _Z12kernel_boiteiPf,@function
_Z12kernel_boiteiPf: # @_Z12kernel_boiteiPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsi,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z12kernel_boiteiPf, .Lfunc_end3-_Z12kernel_boiteiPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16kernel_bilateraliPf
.LCPI4_0:
.quad 0x40040d92fcf70920 # double 2.5066280138863846
.LCPI4_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z16kernel_bilateraliPf
.p2align 4, 0x90
.type _Z16kernel_bilateraliPf,@function
_Z16kernel_bilateraliPf: # @_Z16kernel_bilateraliPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %ebx
cvtsi2sd %edi, %xmm0
movq %rsi, %r14
mulsd .LCPI4_0(%rip), %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
addl %edi, %ebx
xorl $4, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %r15d, %eax
xorl $-3, %eax
incl %eax
cltd
idivl %ebx
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $256, %r15 # imm = 0x100
jne .LBB4_1
# %bb.2:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16kernel_bilateraliPf, .Lfunc_end4-_Z16kernel_bilateraliPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__FiltreiiPfS_ # -- Begin function _Z21__device_stub__FiltreiiPfS_
.p2align 4, 0x90
.type _Z21__device_stub__FiltreiiPfS_,@function
_Z21__device_stub__FiltreiiPfS_: # @_Z21__device_stub__FiltreiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6FiltreiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z21__device_stub__FiltreiiPfS_, .Lfunc_end5-_Z21__device_stub__FiltreiiPfS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__filtre_dilatiiPf # -- Begin function _Z27__device_stub__filtre_dilatiiPf
.p2align 4, 0x90
.type _Z27__device_stub__filtre_dilatiiPf,@function
_Z27__device_stub__filtre_dilatiiPf: # @_Z27__device_stub__filtre_dilatiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12filtre_dilatiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z27__device_stub__filtre_dilatiiPf, .Lfunc_end6-_Z27__device_stub__filtre_dilatiiPf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__filtre_erosioniiPf # -- Begin function _Z29__device_stub__filtre_erosioniiPf
.p2align 4, 0x90
.type _Z29__device_stub__filtre_erosioniiPf,@function
_Z29__device_stub__filtre_erosioniiPf: # @_Z29__device_stub__filtre_erosioniiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14filtre_erosioniiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size _Z29__device_stub__filtre_erosioniiPf, .Lfunc_end7-_Z29__device_stub__filtre_erosioniiPf
.cfi_endproc
# -- End function
.globl _Z31__device_stub__Filtre_bilateraliiPfS_S_ # -- Begin function _Z31__device_stub__Filtre_bilateraliiPfS_S_
.p2align 4, 0x90
.type _Z31__device_stub__Filtre_bilateraliiPfS_S_,@function
_Z31__device_stub__Filtre_bilateraliiPfS_S_: # @_Z31__device_stub__Filtre_bilateraliiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16Filtre_bilateraliiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z31__device_stub__Filtre_bilateraliiPfS_S_, .Lfunc_end8-_Z31__device_stub__Filtre_bilateraliiPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x40040d92fcf70920 # double 2.5066280138863846
.LCPI9_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2232, %rsp # imm = 0x8B8
.cfi_def_cfa_offset 2288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $25, %ebx
cmpl $6, %ebp
jne .LBB9_2
# %bb.1:
movq 40(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB9_2:
movq 16(%r14), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
movq 32(%r14), %rax
movq %rax, 88(%rsp) # 8-byte Spill
callq _Z9read_filePc
movl %eax, %ebp
movq %rdx, %r13
movq %r15, 40(%rsp) # 8-byte Spill
movslq %r15d, %rax
movq %rax, 96(%rsp) # 8-byte Spill
leal (,%rbp,4), %r14d
movl %ebp, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r15
movq %rbp, 104(%rsp) # 8-byte Spill
testl %ebp, %ebp
je .LBB9_5
# %bb.3: # %.lr.ph.preheader
cmpl $1, %r12d
adcl $0, %r12d
xorl %eax, %eax
.p2align 4, 0x90
.LBB9_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%r13,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB9_4
.LBB9_5: # %._crit_edge
movq 40(%rsp), %r12 # 8-byte Reload
leal (,%r12,4), %eax
movl %eax, 84(%rsp) # 4-byte Spill
movslq %r14d, %r13
movq %rsp, %rdi
movq %r13, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $4, %esi
movq 96(%rsp), %rdi # 8-byte Reload
callq calloc
movq %rax, %rbp
movl $.L.str.9, %esi
movq 8(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB9_6
# %bb.9:
movl $.L.str.10, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB9_10
# %bb.18:
movl $.L.str.11, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB9_19
# %bb.27:
movl $.L.str.12, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
movq 104(%rsp), %rbx # 8-byte Reload
je .LBB9_28
# %bb.31:
movl $.L.str.13, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB9_32
# %bb.34:
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl $1, %ebp
jmp .LBB9_35
.LBB9_6:
testl %r12d, %r12d
jle .LBB9_13
# %bb.7: # %.lr.ph.i
movq 40(%rsp), %rax # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI9_0(%rip), %xmm0
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
leal (%rax,%rax), %r14d
xorl $4, %r14d
movl %eax, %r12d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB9_8: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
cltd
idivl %r14d
negl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r12
jne .LBB9_8
jmp .LBB9_13
.LBB9_10:
testl %r12d, %r12d
jle .LBB9_13
# %bb.11: # %.lr.ph.preheader.i
movl 40(%rsp), %eax # 4-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB9_12: # %.lr.ph.i99
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbp,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB9_12
.LBB9_13: # %_Z12kernel_gaussiPf.exit
movslq 84(%rsp), %rbx # 4-byte Folded Reload
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rbx # 8-byte Reload
leal 255(%rbx), %eax
movl %ebx, %edi
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
xorl %ebp, %ebp
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_16
# %bb.14:
movq (%rsp), %rax
movq 48(%rsp), %rcx
movl %ebx, 16(%rsp)
movq 40(%rsp), %rdx # 8-byte Reload
movl %edx, 112(%rsp)
movq %rax, 72(%rsp)
movq %rcx, 56(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 1200(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1200(%rsp), %rsi
movl 1208(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z6FiltreiiPfS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
.LBB9_15:
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_16:
movq (%rsp), %rsi
movq %r15, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi # 8-byte Reload
movl %ebx, %esi
.LBB9_17:
movq %r15, %rdx
callq _Z10write_filePciPf
.LBB9_35:
movl %ebp, %eax
addq $2232, %rsp # imm = 0x8B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB9_19:
.cfi_def_cfa_offset 2288
movq %r13, 96(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB9_22
# %bb.20: # %.lr.ph.i103
movq 40(%rsp), %rax # 8-byte Reload
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI9_0(%rip), %xmm0
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
leal (%rax,%rax), %r14d
xorl $4, %r14d
movl %eax, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_21: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %r14d
negl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB9_21
.LBB9_22: # %_Z12kernel_gaussiPf.exit108
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
mulsd .LCPI9_0(%rip), %xmm0
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
addl %ebx, %ebx
xorl $4, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_23: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
xorl $-3, %eax
incl %eax
cltd
idivl %ebx
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
callq exp
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp,%r14,4)
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB9_23
# %bb.24: # %_Z16kernel_bilateraliPf.exit
movslq 84(%rsp), %rbx # 4-byte Folded Reload
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1200(%rsp), %rbx
movl $1024, %esi # imm = 0x400
movq %rbx, %rdi
callq hipMalloc
leaq 176(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %r14 # 8-byte Reload
leal 255(%r14), %eax
movl %r14d, %edi
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
xorl %ebp, %ebp
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 96(%rsp), %r12 # 8-byte Reload
jne .LBB9_26
# %bb.25:
movq (%rsp), %rax
movq 48(%rsp), %rcx
movl %r14d, 124(%rsp)
movq 40(%rsp), %rdx # 8-byte Reload
movl %edx, 120(%rsp)
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rbx, 16(%rsp)
leaq 124(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z16Filtre_bilateraliiPfS_S_, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_26:
movq (%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi # 8-byte Reload
movl %r14d, %esi
jmp .LBB9_17
.LBB9_28:
leal 255(%rbx), %eax
movl %ebx, %edi
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
xorl %ebp, %ebp
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_16
# %bb.29:
movq (%rsp), %rax
movl %ebx, 24(%rsp)
movl %r12d, 16(%rsp)
movq %rax, 72(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 1200(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1200(%rsp), %rsi
movl 1208(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z14filtre_erosioniiPf, %edi
jmp .LBB9_30
.LBB9_32:
leal 255(%rbx), %eax
movl %ebx, %edi
addl $510, %edi # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
xorl %ebp, %ebp
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_16
# %bb.33:
movq (%rsp), %rax
movl %ebx, 24(%rsp)
movl %r12d, 16(%rsp)
movq %rax, 72(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 1200(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1200(%rsp), %rsi
movl 1208(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z12filtre_dilatiiPf, %edi
.LBB9_30:
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
jmp .LBB9_15
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6FiltreiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12filtre_dilatiiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14filtre_erosioniiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16Filtre_bilateraliiPfS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "w"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "P2\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "r"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d"
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type _Z6FiltreiiPfS_,@object # @_Z6FiltreiiPfS_
.section .rodata,"a",@progbits
.globl _Z6FiltreiiPfS_
.p2align 3, 0x0
_Z6FiltreiiPfS_:
.quad _Z21__device_stub__FiltreiiPfS_
.size _Z6FiltreiiPfS_, 8
.type _Z12filtre_dilatiiPf,@object # @_Z12filtre_dilatiiPf
.globl _Z12filtre_dilatiiPf
.p2align 3, 0x0
_Z12filtre_dilatiiPf:
.quad _Z27__device_stub__filtre_dilatiiPf
.size _Z12filtre_dilatiiPf, 8
.type _Z14filtre_erosioniiPf,@object # @_Z14filtre_erosioniiPf
.globl _Z14filtre_erosioniiPf
.p2align 3, 0x0
_Z14filtre_erosioniiPf:
.quad _Z29__device_stub__filtre_erosioniiPf
.size _Z14filtre_erosioniiPf, 8
.type _Z16Filtre_bilateraliiPfS_S_,@object # @_Z16Filtre_bilateraliiPfS_S_
.globl _Z16Filtre_bilateraliiPfS_S_
.p2align 3, 0x0
_Z16Filtre_bilateraliiPfS_S_:
.quad _Z31__device_stub__Filtre_bilateraliiPfS_S_
.size _Z16Filtre_bilateraliiPfS_S_, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "g"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "b"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "bl"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "e"
.size .L.str.12, 2
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "d"
.size .L.str.13, 2
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Please recheck the kernel type! Value must be equal to : b for 'boite' or g for 'gaussian'."
.size .L.str.14, 92
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6FiltreiiPfS_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12filtre_dilatiiPf"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14filtre_erosioniiPf"
.size .L__unnamed_3, 23
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16Filtre_bilateraliiPfS_S_"
.size .L__unnamed_4, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Error: could not open the image file"
.size .Lstr.1, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__FiltreiiPfS_
.addrsig_sym _Z27__device_stub__filtre_dilatiiPf
.addrsig_sym _Z29__device_stub__filtre_erosioniiPf
.addrsig_sym _Z31__device_stub__Filtre_bilateraliiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6FiltreiiPfS_
.addrsig_sym _Z12filtre_dilatiiPf
.addrsig_sym _Z14filtre_erosioniiPf
.addrsig_sym _Z16Filtre_bilateraliiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
#define ArraySize 1314
// #define n 256
__global__ void vecMultiply(int *A) {
int i;
int threadID = threadIdx.x;
int start = (threadID * ArraySize) / 256;
int end = ( ( (threadID + 1 ) * ArraySize) / 256) - 1;
for(i = start ; i < end ; i++)
{
A[i] = A[i] * 2;
}
}
int main (int argc, char *argv[]){
int i;
int size = ArraySize*sizeof(int);
int a[size], *devA;
for (i=0; i< ArraySize; i++)
{
a[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecMultiply<<<1, 256>>>(devA); // 1 , 256 mean send each data with total thread 256 threads
printf("Before\n");
for (i=0; i< ArraySize; i++)
{
printf("%d ", a[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
printf("After\n");
for (i=0; i < ArraySize; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | code for sm_80
Function : _Z11vecMultiplyPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ IMAD R0, R0, 0x522, RZ ; /* 0x0000052200007824 */
/* 0x001fca00078e02ff */
/*0030*/ IADD3 R2, R0, 0x522, RZ ; /* 0x0000052200027810 */
/* 0x000fe40007ffe0ff */
/*0040*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fe40000011402 */
/*0060*/ LEA.HI R3, R3, R0, RZ, 0x8 ; /* 0x0000000003037211 */
/* 0x000fe400078f40ff */
/*0070*/ LEA.HI R2, R5, R2, RZ, 0x8 ; /* 0x0000000205027211 */
/* 0x000fe400078f40ff */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x8, R3 ; /* 0x00000008ff057819 */
/* 0x000fc40000011403 */
/*0090*/ LEA.HI.SX32 R0, R2, 0xffffffff, 0x18 ; /* 0xffffffff02007811 */
/* 0x000fc800078fc2ff */
/*00a0*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff037212 */
/* 0x000fe200078e33ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ LEA.HI.SX32 R4, R2.reuse, 0xfffffffe, 0x18 ; /* 0xfffffffe02047811 */
/* 0x040fe200078fc2ff */
/*00f0*/ BSSY B0, 0x250 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0100*/ LEA.HI.SX32 R3, R2, R3, 0x18 ; /* 0x0000000302037211 */
/* 0x000fc600078fc2ff */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe200078e0a05 */
/*0120*/ LOP3.LUT P1, R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fc8000782c0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd20003f06070 */
/*0140*/ @!P1 BRA 0x240 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0180*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0009 */
/*01b0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*01f0*/ IMAD.SHL.U32 R7, R6, 0x2, RZ ; /* 0x0000000206077824 */
/* 0x004fe200078e00ff */
/*0200*/ IADD3 R6, P2, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007f5e0ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0220*/ IADD3.X R9, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff097210 */
/* 0x000fcc00017fe4ff */
/*0230*/ @P1 BRA 0x190 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*0270*/ BSSY B0, 0x690 ; /* 0x0000041000007945 */
/* 0x000fe20003800000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x001fc600078e00ff */
/*0290*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*02a0*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*02b0*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*02c0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*02e0*/ @!P1 BRA 0x680 ; /* 0x0000039000009947 */
/* 0x000fee0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ IADD3 R4, R0, -0xc, RZ ; /* 0xfffffff400047810 */
/* 0x000fc60007ffe0ff */
/*0310*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ee8000c1e1900 */
/*0330*/ LDG.E R14, [R2.64+-0x4] ; /* 0xfffffc04020e7981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R11, [R2.64+0x20] ; /* 0x00002004020b7981 */
/* 0x000f68000c1e1900 */
/*0360*/ LDG.E R6, [R2.64+0x28] ; /* 0x0000280402067981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R26, [R2.64+0x18] ; /* 0x00001804021a7981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R12, [R2.64+0x1c] ; /* 0x00001c04020c7981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R10, [R2.64+0x24] ; /* 0x00002404020a7981 */
/* 0x000f68000c1e1900 */
/*03e0*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000f68000c1e1900 */
/*03f0*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300402087981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R7, [R2.64+0x34] ; /* 0x0000340402077981 */
/* 0x000f62000c1e1900 */
/*0410*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe20003f26270 */
/*0430*/ IMAD.SHL.U32 R17, R16, 0x2, RZ ; /* 0x0000000210117824 */
/* 0x004fe200078e00ff */
/*0440*/ SHF.L.U32 R13, R13, 0x1, RZ ; /* 0x000000010d0d7819 */
/* 0x008fc800000006ff */
/*0450*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e2000c101904 */
/*0460*/ IMAD.SHL.U32 R15, R14, 0x2, RZ ; /* 0x000000020e0f7824 */
/* 0x010fe400078e00ff */
/*0470*/ IMAD.SHL.U32 R19, R18, 0x2, RZ ; /* 0x0000000212137824 */
/* 0x020fe400078e00ff */
/*0480*/ IMAD.SHL.U32 R11, R11, 0x2, RZ ; /* 0x000000020b0b7824 */
/* 0x000fe200078e00ff */
/*0490*/ STG.E [R2.64+-0x8], R13 ; /* 0xfffff80d02007986 */
/* 0x0003e2000c101904 */
/*04a0*/ SHF.L.U32 R17, R6, 0x1, RZ ; /* 0x0000000106117819 */
/* 0x001fe400000006ff */
/*04b0*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe20007f5e0ff */
/*04c0*/ STG.E [R2.64+-0x4], R15 ; /* 0xfffffc0f02007986 */
/* 0x000fe2000c101904 */
/*04d0*/ SHF.L.U32 R21, R20, 0x1, RZ ; /* 0x0000000114157819 */
/* 0x000fc600000006ff */
/*04e0*/ STG.E [R2.64+0x4], R19 ; /* 0x0000041302007986 */
/* 0x000fe2000c101904 */
/*04f0*/ IMAD.SHL.U32 R23, R22, 0x2, RZ ; /* 0x0000000216177824 */
/* 0x000fc600078e00ff */
/*0500*/ STG.E [R2.64+0x20], R11 ; /* 0x0000200b02007986 */
/* 0x0001e2000c101904 */
/*0510*/ IMAD.SHL.U32 R13, R24, 0x2, RZ ; /* 0x00000002180d7824 */
/* 0x002fe400078e00ff */
/*0520*/ IMAD.SHL.U32 R25, R25, 0x2, RZ ; /* 0x0000000219197824 */
/* 0x000fe200078e00ff */
/*0530*/ SHF.L.U32 R27, R26, 0x1, RZ ; /* 0x000000011a1b7819 */
/* 0x000fe400000006ff */
/*0540*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200017fe4ff */
/*0550*/ IMAD.SHL.U32 R29, R12, 0x2, RZ ; /* 0x000000020c1d7824 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.SHL.U32 R15, R10, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fc400078e00ff */
/*0580*/ IMAD.SHL.U32 R19, R8, 0x2, RZ ; /* 0x0000000208137824 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*05a0*/ STG.E [R2.64+0x8], R21 ; /* 0x0000081502007986 */
/* 0x000fe8000c101904 */
/*05b0*/ STG.E [R2.64+0xc], R23 ; /* 0x00000c1702007986 */
/* 0x000fe8000c101904 */
/*05c0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe8000c101904 */
/*05d0*/ STG.E [R2.64+0x14], R25 ; /* 0x0000141902007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0x18], R27 ; /* 0x0000181b02007986 */
/* 0x000fe8000c101904 */
/*05f0*/ STG.E [R2.64+0x1c], R29 ; /* 0x00001c1d02007986 */
/* 0x000fe8000c101904 */
/*0600*/ STG.E [R2.64+0x24], R15 ; /* 0x0000240f02007986 */
/* 0x000fe8000c101904 */
/*0610*/ STG.E [R2.64+0x28], R17 ; /* 0x0000281102007986 */
/* 0x000fe8000c101904 */
/*0620*/ STG.E [R2.64+0x2c], R9 ; /* 0x00002c0902007986 */
/* 0x000fe8000c101904 */
/*0630*/ STG.E [R2.64+0x30], R19 ; /* 0x0000301302007986 */
/* 0x000fe8000c101904 */
/*0640*/ STG.E [R2.64+0x34], R7 ; /* 0x0000340702007986 */
/* 0x0001e4000c101904 */
/*0650*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0660*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000b */
/*0670*/ @!P1 BRA 0x310 ; /* 0xfffffc9000009947 */
/* 0x000fea000383ffff */
/*0680*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*06a0*/ BSSY B0, 0x8c0 ; /* 0x0000021000007945 */
/* 0x000fe80003800000 */
/*06b0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x8b0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*06d0*/ LDG.E R4, [R2.64+-0x8] ; /* 0xfffff80402047981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402067981 */
/* 0x000ee8000c1e1900 */
/*06f0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000f28000c1e1900 */
/*0700*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000f68000c1e1900 */
/*0710*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000f68000c1e1900 */
/*0720*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x000f68000c1e1900 */
/*0730*/ LDG.E R16, [R2.64+0x10] ; /* 0x0000100402107981 */
/* 0x000f68000c1e1900 */
/*0740*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000f62000c1e1900 */
/*0750*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0760*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0770*/ SHF.L.U32 R7, R4, 0x1, RZ ; /* 0x0000000104077819 */
/* 0x004fe400000006ff */
/*0780*/ IADD3 R4, P1, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe20007f3e0ff */
/*0790*/ IMAD.SHL.U32 R9, R6, 0x2, RZ ; /* 0x0000000206097824 */
/* 0x008fe400078e00ff */
/*07a0*/ STG.E [R2.64+-0x8], R7 ; /* 0xfffff80702007986 */
/* 0x0001e2000c101904 */
/*07b0*/ IMAD.SHL.U32 R11, R8, 0x2, RZ ; /* 0x00000002080b7824 */
/* 0x010fc600078e00ff */
/*07c0*/ STG.E [R2.64+-0x4], R9 ; /* 0xfffffc0902007986 */
/* 0x000fe2000c101904 */
/*07d0*/ IMAD.SHL.U32 R13, R10, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x020fc600078e00ff */
/*07e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*07f0*/ SHF.L.U32 R15, R12, 0x1, RZ ; /* 0x000000010c0f7819 */
/* 0x000fc600000006ff */
/*0800*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe2000c101904 */
/*0810*/ IADD3.X R7, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff077210 */
/* 0x001fe20000ffe4ff */
/*0820*/ IMAD.SHL.U32 R17, R14, 0x2, RZ ; /* 0x000000020e117824 */
/* 0x000fe400078e00ff */
/*0830*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*0840*/ IMAD.SHL.U32 R19, R16, 0x2, RZ ; /* 0x0000000210137824 */
/* 0x000fc600078e00ff */
/*0850*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x000fe2000c101904 */
/*0860*/ IMAD.SHL.U32 R21, R18, 0x2, RZ ; /* 0x0000000212157824 */
/* 0x000fc600078e00ff */
/*0870*/ STG.E [R2.64+0x10], R19 ; /* 0x0000101302007986 */
/* 0x000fe8000c101904 */
/*0880*/ STG.E [R2.64+0x14], R21 ; /* 0x0000141502007986 */
/* 0x0001e4000c101904 */
/*0890*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0004 */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*08b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.LT.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x000fda0000701670 */
/*08d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E R0, [R2.64+-0x8] ; /* 0xfffff80402007981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R4, [R2.64+-0x4] ; /* 0xfffffc0402047981 */
/* 0x000ee8000c1e1900 */
/*0900*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000f28000c1e1900 */
/*0910*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000f62000c1e1900 */
/*0920*/ IMAD.SHL.U32 R5, R0, 0x2, RZ ; /* 0x0000000200057824 */
/* 0x004fe200078e00ff */
/*0930*/ SHF.L.U32 R7, R4, 0x1, RZ ; /* 0x0000000104077819 */
/* 0x008fc800000006ff */
/*0940*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*0950*/ IMAD.SHL.U32 R9, R6, 0x2, RZ ; /* 0x0000000206097824 */
/* 0x010fc600078e00ff */
/*0960*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x000fe2000c101904 */
/*0970*/ IMAD.SHL.U32 R11, R8, 0x2, RZ ; /* 0x00000002080b7824 */
/* 0x020fc600078e00ff */
/*0980*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0990*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe2000c101904 */
/*09a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
#define ArraySize 1314
// #define n 256
__global__ void vecMultiply(int *A) {
int i;
int threadID = threadIdx.x;
int start = (threadID * ArraySize) / 256;
int end = ( ( (threadID + 1 ) * ArraySize) / 256) - 1;
for(i = start ; i < end ; i++)
{
A[i] = A[i] * 2;
}
}
int main (int argc, char *argv[]){
int i;
int size = ArraySize*sizeof(int);
int a[size], *devA;
for (i=0; i< ArraySize; i++)
{
a[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecMultiply<<<1, 256>>>(devA); // 1 , 256 mean send each data with total thread 256 threads
printf("Before\n");
for (i=0; i< ArraySize; i++)
{
printf("%d ", a[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
printf("After\n");
for (i=0; i < ArraySize; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | .file "tmpxft_001270a7_00000000-6_cuda2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11vecMultiplyPiPi
.type _Z31__device_stub__Z11vecMultiplyPiPi, @function
_Z31__device_stub__Z11vecMultiplyPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11vecMultiplyPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z11vecMultiplyPiPi, .-_Z31__device_stub__Z11vecMultiplyPiPi
.globl _Z11vecMultiplyPi
.type _Z11vecMultiplyPi, @function
_Z11vecMultiplyPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11vecMultiplyPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11vecMultiplyPi, .-_Z11vecMultiplyPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Before\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "After\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -20480(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
subq $544, %rsp
orq $0, 536(%rsp)
movq %rsp, %r14
movl $1, %eax
.L15:
movl %eax, -4(%r14,%rax,4)
addq $1, %rax
cmpq $1315, %rax
jne .L15
leaq -88(%rbp), %rdi
movl $5256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $5256, %edx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $256, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rbx
leaq 5256(%r14), %r13
movq %r14, %r12
leaq .LC1(%rip), %r15
.L17:
movl (%r12), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r13, %r12
jne .L17
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $5256, %edx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %r12
.L18:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L18
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L24:
.cfi_restore_state
movq -88(%rbp), %rdi
call _Z31__device_stub__Z11vecMultiplyPiPi
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11vecMultiplyPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vecMultiplyPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
#define ArraySize 1314
// #define n 256
__global__ void vecMultiply(int *A) {
int i;
int threadID = threadIdx.x;
int start = (threadID * ArraySize) / 256;
int end = ( ( (threadID + 1 ) * ArraySize) / 256) - 1;
for(i = start ; i < end ; i++)
{
A[i] = A[i] * 2;
}
}
int main (int argc, char *argv[]){
int i;
int size = ArraySize*sizeof(int);
int a[size], *devA;
for (i=0; i< ArraySize; i++)
{
a[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecMultiply<<<1, 256>>>(devA); // 1 , 256 mean send each data with total thread 256 threads
printf("Before\n");
for (i=0; i< ArraySize; i++)
{
printf("%d ", a[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
printf("After\n");
for (i=0; i < ArraySize; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
#define ArraySize 1314
// #define n 256
__global__ void vecMultiply(int *A) {
int i;
int threadID = threadIdx.x;
int start = (threadID * ArraySize) / 256;
int end = ( ( (threadID + 1 ) * ArraySize) / 256) - 1;
for(i = start ; i < end ; i++)
{
A[i] = A[i] * 2;
}
}
int main (int argc, char *argv[]){
int i;
int size = ArraySize*sizeof(int);
int a[size], *devA;
for (i=0; i< ArraySize; i++)
{
a[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecMultiply<<<1, 256>>>(devA); // 1 , 256 mean send each data with total thread 256 threads
printf("Before\n");
for (i=0; i< ArraySize; i++)
{
printf("%d ", a[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipFree(devA);
printf("After\n");
for (i=0; i < ArraySize; i++) {
printf("%d ",a[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
#define ArraySize 1314
// #define n 256
__global__ void vecMultiply(int *A) {
int i;
int threadID = threadIdx.x;
int start = (threadID * ArraySize) / 256;
int end = ( ( (threadID + 1 ) * ArraySize) / 256) - 1;
for(i = start ; i < end ; i++)
{
A[i] = A[i] * 2;
}
}
int main (int argc, char *argv[]){
int i;
int size = ArraySize*sizeof(int);
int a[size], *devA;
for (i=0; i< ArraySize; i++)
{
a[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecMultiply<<<1, 256>>>(devA); // 1 , 256 mean send each data with total thread 256 threads
printf("Before\n");
for (i=0; i< ArraySize; i++)
{
printf("%d ", a[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipFree(devA);
printf("After\n");
for (i=0; i < ArraySize; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11vecMultiplyPi
.globl _Z11vecMultiplyPi
.p2align 8
.type _Z11vecMultiplyPi,@function
_Z11vecMultiplyPi:
v_mad_u32_u24 v1, v0, 0x522, 0x522
v_mul_u32_u24_e32 v0, 0x522, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v1, 8, v1
v_lshrrev_b32_e32 v2, 8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, -1, v1
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshrrev_b32_e32 v0, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0x7ffc, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
s_mov_b32 s1, 0
.LBB0_2:
global_load_b32 v4, v[0:1], off
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 1, v4
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, s0, v0, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11vecMultiplyPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11vecMultiplyPi, .Lfunc_end0-_Z11vecMultiplyPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11vecMultiplyPi
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z11vecMultiplyPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
#define ArraySize 1314
// #define n 256
__global__ void vecMultiply(int *A) {
int i;
int threadID = threadIdx.x;
int start = (threadID * ArraySize) / 256;
int end = ( ( (threadID + 1 ) * ArraySize) / 256) - 1;
for(i = start ; i < end ; i++)
{
A[i] = A[i] * 2;
}
}
int main (int argc, char *argv[]){
int i;
int size = ArraySize*sizeof(int);
int a[size], *devA;
for (i=0; i< ArraySize; i++)
{
a[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecMultiply<<<1, 256>>>(devA); // 1 , 256 mean send each data with total thread 256 threads
printf("Before\n");
for (i=0; i< ArraySize; i++)
{
printf("%d ", a[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipFree(devA);
printf("After\n");
for (i=0; i < ArraySize; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | .text
.file "cuda2.hip"
.globl _Z26__device_stub__vecMultiplyPi # -- Begin function _Z26__device_stub__vecMultiplyPi
.p2align 4, 0x90
.type _Z26__device_stub__vecMultiplyPi,@function
_Z26__device_stub__vecMultiplyPi: # @_Z26__device_stub__vecMultiplyPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11vecMultiplyPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__vecMultiplyPi, .Lfunc_end0-_Z26__device_stub__vecMultiplyPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $21104, %rsp # imm = 0x5270
.cfi_def_cfa_offset 21120
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 80(%rsp,%rax,4)
movq %rcx, %rax
cmpq $1314, %rcx # imm = 0x522
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $5256, %esi # imm = 0x1488
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $5256, %edx # imm = 0x1488
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11vecMultiplyPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1314, %rbx # imm = 0x522
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $5256, %edx # imm = 0x1488
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1314, %rbx # imm = 0x522
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $21104, %rsp # imm = 0x5270
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11vecMultiplyPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11vecMultiplyPi,@object # @_Z11vecMultiplyPi
.section .rodata,"a",@progbits
.globl _Z11vecMultiplyPi
.p2align 3, 0x0
_Z11vecMultiplyPi:
.quad _Z26__device_stub__vecMultiplyPi
.size _Z11vecMultiplyPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11vecMultiplyPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Before"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "After"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__vecMultiplyPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11vecMultiplyPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11vecMultiplyPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ IMAD R0, R0, 0x522, RZ ; /* 0x0000052200007824 */
/* 0x001fca00078e02ff */
/*0030*/ IADD3 R2, R0, 0x522, RZ ; /* 0x0000052200027810 */
/* 0x000fe40007ffe0ff */
/*0040*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fe40000011402 */
/*0060*/ LEA.HI R3, R3, R0, RZ, 0x8 ; /* 0x0000000003037211 */
/* 0x000fe400078f40ff */
/*0070*/ LEA.HI R2, R5, R2, RZ, 0x8 ; /* 0x0000000205027211 */
/* 0x000fe400078f40ff */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x8, R3 ; /* 0x00000008ff057819 */
/* 0x000fc40000011403 */
/*0090*/ LEA.HI.SX32 R0, R2, 0xffffffff, 0x18 ; /* 0xffffffff02007811 */
/* 0x000fc800078fc2ff */
/*00a0*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff037212 */
/* 0x000fe200078e33ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ LEA.HI.SX32 R4, R2.reuse, 0xfffffffe, 0x18 ; /* 0xfffffffe02047811 */
/* 0x040fe200078fc2ff */
/*00f0*/ BSSY B0, 0x250 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0100*/ LEA.HI.SX32 R3, R2, R3, 0x18 ; /* 0x0000000302037211 */
/* 0x000fc600078fc2ff */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe200078e0a05 */
/*0120*/ LOP3.LUT P1, R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fc8000782c0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd20003f06070 */
/*0140*/ @!P1 BRA 0x240 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0180*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0009 */
/*01b0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*01f0*/ IMAD.SHL.U32 R7, R6, 0x2, RZ ; /* 0x0000000206077824 */
/* 0x004fe200078e00ff */
/*0200*/ IADD3 R6, P2, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007f5e0ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0220*/ IADD3.X R9, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff097210 */
/* 0x000fcc00017fe4ff */
/*0230*/ @P1 BRA 0x190 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*0270*/ BSSY B0, 0x690 ; /* 0x0000041000007945 */
/* 0x000fe20003800000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x001fc600078e00ff */
/*0290*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*02a0*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*02b0*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*02c0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*02e0*/ @!P1 BRA 0x680 ; /* 0x0000039000009947 */
/* 0x000fee0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ IADD3 R4, R0, -0xc, RZ ; /* 0xfffffff400047810 */
/* 0x000fc60007ffe0ff */
/*0310*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ee8000c1e1900 */
/*0330*/ LDG.E R14, [R2.64+-0x4] ; /* 0xfffffc04020e7981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R11, [R2.64+0x20] ; /* 0x00002004020b7981 */
/* 0x000f68000c1e1900 */
/*0360*/ LDG.E R6, [R2.64+0x28] ; /* 0x0000280402067981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R26, [R2.64+0x18] ; /* 0x00001804021a7981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R12, [R2.64+0x1c] ; /* 0x00001c04020c7981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R10, [R2.64+0x24] ; /* 0x00002404020a7981 */
/* 0x000f68000c1e1900 */
/*03e0*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000f68000c1e1900 */
/*03f0*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300402087981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R7, [R2.64+0x34] ; /* 0x0000340402077981 */
/* 0x000f62000c1e1900 */
/*0410*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe20003f26270 */
/*0430*/ IMAD.SHL.U32 R17, R16, 0x2, RZ ; /* 0x0000000210117824 */
/* 0x004fe200078e00ff */
/*0440*/ SHF.L.U32 R13, R13, 0x1, RZ ; /* 0x000000010d0d7819 */
/* 0x008fc800000006ff */
/*0450*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e2000c101904 */
/*0460*/ IMAD.SHL.U32 R15, R14, 0x2, RZ ; /* 0x000000020e0f7824 */
/* 0x010fe400078e00ff */
/*0470*/ IMAD.SHL.U32 R19, R18, 0x2, RZ ; /* 0x0000000212137824 */
/* 0x020fe400078e00ff */
/*0480*/ IMAD.SHL.U32 R11, R11, 0x2, RZ ; /* 0x000000020b0b7824 */
/* 0x000fe200078e00ff */
/*0490*/ STG.E [R2.64+-0x8], R13 ; /* 0xfffff80d02007986 */
/* 0x0003e2000c101904 */
/*04a0*/ SHF.L.U32 R17, R6, 0x1, RZ ; /* 0x0000000106117819 */
/* 0x001fe400000006ff */
/*04b0*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe20007f5e0ff */
/*04c0*/ STG.E [R2.64+-0x4], R15 ; /* 0xfffffc0f02007986 */
/* 0x000fe2000c101904 */
/*04d0*/ SHF.L.U32 R21, R20, 0x1, RZ ; /* 0x0000000114157819 */
/* 0x000fc600000006ff */
/*04e0*/ STG.E [R2.64+0x4], R19 ; /* 0x0000041302007986 */
/* 0x000fe2000c101904 */
/*04f0*/ IMAD.SHL.U32 R23, R22, 0x2, RZ ; /* 0x0000000216177824 */
/* 0x000fc600078e00ff */
/*0500*/ STG.E [R2.64+0x20], R11 ; /* 0x0000200b02007986 */
/* 0x0001e2000c101904 */
/*0510*/ IMAD.SHL.U32 R13, R24, 0x2, RZ ; /* 0x00000002180d7824 */
/* 0x002fe400078e00ff */
/*0520*/ IMAD.SHL.U32 R25, R25, 0x2, RZ ; /* 0x0000000219197824 */
/* 0x000fe200078e00ff */
/*0530*/ SHF.L.U32 R27, R26, 0x1, RZ ; /* 0x000000011a1b7819 */
/* 0x000fe400000006ff */
/*0540*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200017fe4ff */
/*0550*/ IMAD.SHL.U32 R29, R12, 0x2, RZ ; /* 0x000000020c1d7824 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.SHL.U32 R15, R10, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fc400078e00ff */
/*0580*/ IMAD.SHL.U32 R19, R8, 0x2, RZ ; /* 0x0000000208137824 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*05a0*/ STG.E [R2.64+0x8], R21 ; /* 0x0000081502007986 */
/* 0x000fe8000c101904 */
/*05b0*/ STG.E [R2.64+0xc], R23 ; /* 0x00000c1702007986 */
/* 0x000fe8000c101904 */
/*05c0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe8000c101904 */
/*05d0*/ STG.E [R2.64+0x14], R25 ; /* 0x0000141902007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0x18], R27 ; /* 0x0000181b02007986 */
/* 0x000fe8000c101904 */
/*05f0*/ STG.E [R2.64+0x1c], R29 ; /* 0x00001c1d02007986 */
/* 0x000fe8000c101904 */
/*0600*/ STG.E [R2.64+0x24], R15 ; /* 0x0000240f02007986 */
/* 0x000fe8000c101904 */
/*0610*/ STG.E [R2.64+0x28], R17 ; /* 0x0000281102007986 */
/* 0x000fe8000c101904 */
/*0620*/ STG.E [R2.64+0x2c], R9 ; /* 0x00002c0902007986 */
/* 0x000fe8000c101904 */
/*0630*/ STG.E [R2.64+0x30], R19 ; /* 0x0000301302007986 */
/* 0x000fe8000c101904 */
/*0640*/ STG.E [R2.64+0x34], R7 ; /* 0x0000340702007986 */
/* 0x0001e4000c101904 */
/*0650*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0660*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000b */
/*0670*/ @!P1 BRA 0x310 ; /* 0xfffffc9000009947 */
/* 0x000fea000383ffff */
/*0680*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*06a0*/ BSSY B0, 0x8c0 ; /* 0x0000021000007945 */
/* 0x000fe80003800000 */
/*06b0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x8b0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*06d0*/ LDG.E R4, [R2.64+-0x8] ; /* 0xfffff80402047981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402067981 */
/* 0x000ee8000c1e1900 */
/*06f0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000f28000c1e1900 */
/*0700*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000f68000c1e1900 */
/*0710*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000f68000c1e1900 */
/*0720*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x000f68000c1e1900 */
/*0730*/ LDG.E R16, [R2.64+0x10] ; /* 0x0000100402107981 */
/* 0x000f68000c1e1900 */
/*0740*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000f62000c1e1900 */
/*0750*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0760*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0770*/ SHF.L.U32 R7, R4, 0x1, RZ ; /* 0x0000000104077819 */
/* 0x004fe400000006ff */
/*0780*/ IADD3 R4, P1, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe20007f3e0ff */
/*0790*/ IMAD.SHL.U32 R9, R6, 0x2, RZ ; /* 0x0000000206097824 */
/* 0x008fe400078e00ff */
/*07a0*/ STG.E [R2.64+-0x8], R7 ; /* 0xfffff80702007986 */
/* 0x0001e2000c101904 */
/*07b0*/ IMAD.SHL.U32 R11, R8, 0x2, RZ ; /* 0x00000002080b7824 */
/* 0x010fc600078e00ff */
/*07c0*/ STG.E [R2.64+-0x4], R9 ; /* 0xfffffc0902007986 */
/* 0x000fe2000c101904 */
/*07d0*/ IMAD.SHL.U32 R13, R10, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x020fc600078e00ff */
/*07e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*07f0*/ SHF.L.U32 R15, R12, 0x1, RZ ; /* 0x000000010c0f7819 */
/* 0x000fc600000006ff */
/*0800*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe2000c101904 */
/*0810*/ IADD3.X R7, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff077210 */
/* 0x001fe20000ffe4ff */
/*0820*/ IMAD.SHL.U32 R17, R14, 0x2, RZ ; /* 0x000000020e117824 */
/* 0x000fe400078e00ff */
/*0830*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*0840*/ IMAD.SHL.U32 R19, R16, 0x2, RZ ; /* 0x0000000210137824 */
/* 0x000fc600078e00ff */
/*0850*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x000fe2000c101904 */
/*0860*/ IMAD.SHL.U32 R21, R18, 0x2, RZ ; /* 0x0000000212157824 */
/* 0x000fc600078e00ff */
/*0870*/ STG.E [R2.64+0x10], R19 ; /* 0x0000101302007986 */
/* 0x000fe8000c101904 */
/*0880*/ STG.E [R2.64+0x14], R21 ; /* 0x0000141502007986 */
/* 0x0001e4000c101904 */
/*0890*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0004 */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*08b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.LT.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x000fda0000701670 */
/*08d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E R0, [R2.64+-0x8] ; /* 0xfffff80402007981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R4, [R2.64+-0x4] ; /* 0xfffffc0402047981 */
/* 0x000ee8000c1e1900 */
/*0900*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000f28000c1e1900 */
/*0910*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000f62000c1e1900 */
/*0920*/ IMAD.SHL.U32 R5, R0, 0x2, RZ ; /* 0x0000000200057824 */
/* 0x004fe200078e00ff */
/*0930*/ SHF.L.U32 R7, R4, 0x1, RZ ; /* 0x0000000104077819 */
/* 0x008fc800000006ff */
/*0940*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*0950*/ IMAD.SHL.U32 R9, R6, 0x2, RZ ; /* 0x0000000206097824 */
/* 0x010fc600078e00ff */
/*0960*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x000fe2000c101904 */
/*0970*/ IMAD.SHL.U32 R11, R8, 0x2, RZ ; /* 0x00000002080b7824 */
/* 0x020fc600078e00ff */
/*0980*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0990*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe2000c101904 */
/*09a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11vecMultiplyPi
.globl _Z11vecMultiplyPi
.p2align 8
.type _Z11vecMultiplyPi,@function
_Z11vecMultiplyPi:
v_mad_u32_u24 v1, v0, 0x522, 0x522
v_mul_u32_u24_e32 v0, 0x522, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v1, 8, v1
v_lshrrev_b32_e32 v2, 8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, -1, v1
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshrrev_b32_e32 v0, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0x7ffc, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
s_mov_b32 s1, 0
.LBB0_2:
global_load_b32 v4, v[0:1], off
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 1, v4
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, s0, v0, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11vecMultiplyPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11vecMultiplyPi, .Lfunc_end0-_Z11vecMultiplyPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11vecMultiplyPi
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z11vecMultiplyPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001270a7_00000000-6_cuda2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11vecMultiplyPiPi
.type _Z31__device_stub__Z11vecMultiplyPiPi, @function
_Z31__device_stub__Z11vecMultiplyPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11vecMultiplyPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z11vecMultiplyPiPi, .-_Z31__device_stub__Z11vecMultiplyPiPi
.globl _Z11vecMultiplyPi
.type _Z11vecMultiplyPi, @function
_Z11vecMultiplyPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11vecMultiplyPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11vecMultiplyPi, .-_Z11vecMultiplyPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Before\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "After\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -20480(%rsp), %rax
.L12:
cmpq %rax, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
subq $544, %rsp
orq $0, 536(%rsp)
movq %rsp, %r14
movl $1, %eax
.L15:
movl %eax, -4(%r14,%rax,4)
addq $1, %rax
cmpq $1315, %rax
jne .L15
leaq -88(%rbp), %rdi
movl $5256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $5256, %edx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl $256, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rbx
leaq 5256(%r14), %r13
movq %r14, %r12
leaq .LC1(%rip), %r15
.L17:
movl (%r12), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r13, %r12
jne .L17
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $5256, %edx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %r12
.L18:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L18
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L24:
.cfi_restore_state
movq -88(%rbp), %rdi
call _Z31__device_stub__Z11vecMultiplyPiPi
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11vecMultiplyPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vecMultiplyPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda2.hip"
.globl _Z26__device_stub__vecMultiplyPi # -- Begin function _Z26__device_stub__vecMultiplyPi
.p2align 4, 0x90
.type _Z26__device_stub__vecMultiplyPi,@function
_Z26__device_stub__vecMultiplyPi: # @_Z26__device_stub__vecMultiplyPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11vecMultiplyPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__vecMultiplyPi, .Lfunc_end0-_Z26__device_stub__vecMultiplyPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $21104, %rsp # imm = 0x5270
.cfi_def_cfa_offset 21120
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 80(%rsp,%rax,4)
movq %rcx, %rax
cmpq $1314, %rcx # imm = 0x522
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $5256, %esi # imm = 0x1488
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $5256, %edx # imm = 0x1488
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11vecMultiplyPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1314, %rbx # imm = 0x522
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $5256, %edx # imm = 0x1488
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1314, %rbx # imm = 0x522
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $21104, %rsp # imm = 0x5270
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11vecMultiplyPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11vecMultiplyPi,@object # @_Z11vecMultiplyPi
.section .rodata,"a",@progbits
.globl _Z11vecMultiplyPi
.p2align 3, 0x0
_Z11vecMultiplyPi:
.quad _Z26__device_stub__vecMultiplyPi
.size _Z11vecMultiplyPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11vecMultiplyPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Before"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "After"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__vecMultiplyPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11vecMultiplyPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<thrust/host_vector.h>
#include<thrust/device_vector.h>
#include<thrust/generate.h>
#include<thrust/sort.h>
#include<thrust/copy.h>
#include<cstdlib>
int main()
{
thrust::host_vector<int> H(22);
thrust::generate(H.begin(), H.end(), rand);
thrust::device_vector<int> D = H;
thrust::sort(D.begin(), D.end());
thrust::copy(D.begin(), D.end(), H.begin());
for(int i=0; i<H.size(); i++)
printf("%d ",H[i]);
return 0;
} | #include <hip/hip_runtime.h>
#include<thrust/host_vector.h>
#include<thrust/device_vector.h>
#include<thrust/generate.h>
#include<thrust/sort.h>
#include<thrust/copy.h>
#include<cstdlib>
int main()
{
thrust::host_vector<int> H(22);
thrust::generate(H.begin(), H.end(), rand);
thrust::device_vector<int> D = H;
thrust::sort(D.begin(), D.end());
thrust::copy(D.begin(), D.end(), H.begin());
for(int i=0; i<H.size(); i++)
printf("%d ",H[i]);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void init_i32 (int* vector, int value, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
vector[idx] = value;
}
} | code for sm_80
Function : _Z8init_i32Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void init_i32 (int* vector, int value, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
vector[idx] = value;
}
} | .file "tmpxft_00036221_00000000-6_init_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8init_i32PiiiPiii
.type _Z29__device_stub__Z8init_i32PiiiPiii, @function
_Z29__device_stub__Z8init_i32PiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8init_i32Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8init_i32PiiiPiii, .-_Z29__device_stub__Z8init_i32PiiiPiii
.globl _Z8init_i32Piii
.type _Z8init_i32Piii, @function
_Z8init_i32Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8init_i32PiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8init_i32Piii, .-_Z8init_i32Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8init_i32Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8init_i32Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void init_i32 (int* vector, int value, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
vector[idx] = value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_i32 (int* vector, int value, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
vector[idx] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_i32 (int* vector, int value, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
vector[idx] = value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8init_i32Piii
.globl _Z8init_i32Piii
.p2align 8
.type _Z8init_i32Piii,@function
_Z8init_i32Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8init_i32Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8init_i32Piii, .Lfunc_end0-_Z8init_i32Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8init_i32Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8init_i32Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_i32 (int* vector, int value, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
vector[idx] = value;
}
} | .text
.file "init_i32.hip"
.globl _Z23__device_stub__init_i32Piii # -- Begin function _Z23__device_stub__init_i32Piii
.p2align 4, 0x90
.type _Z23__device_stub__init_i32Piii,@function
_Z23__device_stub__init_i32Piii: # @_Z23__device_stub__init_i32Piii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8init_i32Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__init_i32Piii, .Lfunc_end0-_Z23__device_stub__init_i32Piii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8init_i32Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8init_i32Piii,@object # @_Z8init_i32Piii
.section .rodata,"a",@progbits
.globl _Z8init_i32Piii
.p2align 3, 0x0
_Z8init_i32Piii:
.quad _Z23__device_stub__init_i32Piii
.size _Z8init_i32Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8init_i32Piii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__init_i32Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8init_i32Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8init_i32Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8init_i32Piii
.globl _Z8init_i32Piii
.p2align 8
.type _Z8init_i32Piii,@function
_Z8init_i32Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8init_i32Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8init_i32Piii, .Lfunc_end0-_Z8init_i32Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8init_i32Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8init_i32Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036221_00000000-6_init_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8init_i32PiiiPiii
.type _Z29__device_stub__Z8init_i32PiiiPiii, @function
_Z29__device_stub__Z8init_i32PiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8init_i32Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8init_i32PiiiPiii, .-_Z29__device_stub__Z8init_i32PiiiPiii
.globl _Z8init_i32Piii
.type _Z8init_i32Piii, @function
_Z8init_i32Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8init_i32PiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8init_i32Piii, .-_Z8init_i32Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8init_i32Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8init_i32Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init_i32.hip"
.globl _Z23__device_stub__init_i32Piii # -- Begin function _Z23__device_stub__init_i32Piii
.p2align 4, 0x90
.type _Z23__device_stub__init_i32Piii,@function
_Z23__device_stub__init_i32Piii: # @_Z23__device_stub__init_i32Piii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8init_i32Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__init_i32Piii, .Lfunc_end0-_Z23__device_stub__init_i32Piii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8init_i32Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8init_i32Piii,@object # @_Z8init_i32Piii
.section .rodata,"a",@progbits
.globl _Z8init_i32Piii
.p2align 3, 0x0
_Z8init_i32Piii:
.quad _Z23__device_stub__init_i32Piii
.size _Z8init_i32Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8init_i32Piii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__init_i32Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8init_i32Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include <cuda_runtime.h>
//#include <cutil_inline.h>
using namespace std;
#define SUBMATRIX_SIZE 10000
//#define NUM_BIN 5000
//#define HIST_MIN 0.0
//#define HIST_MAX 3.5
#define NUM_BIN 27 // for log binning
#define HIST_MIN 0.0 // for degrees
#define HIST_MAX 100.0 // for degrees
#define CONV_FACTOR 57.2957795 // 180/pi
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
////////////////////////////////////////////////////////////////////////
__global__ void distance(float *a0, float *d0, float *a1, float *d1, int xind, int yind, int *dev_hist, float* dev_bin_edges)
{
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int thread_idx = idx;
idx += xind;
float alpha = a0[idx], delta0 = d0[idx];
float cos_d0 = cos(delta0), sin_d0 = sin(delta0), dist;
int ymax = yind + SUBMATRIX_SIZE;
int bin_index = 0;
int offset = 0;
float a_diff, sin_a_diff, cos_a_diff;
float cos_d1, sin_d1, numer, denom, mult1, mult2;
for(int i=yind; i<ymax; i++)
{
//if(idx > i) ///////// CHECK THIS
//if(idx >= i)
{
a_diff = a1[i] - alpha;
sin_a_diff = sin(a_diff);
cos_a_diff = cos(a_diff);
sin_d1 = sin(d1[i]);
cos_d1 = cos(d1[i]);
mult1 = cos_d1 * cos_d1 * sin_a_diff * sin_a_diff;
mult2 = cos_d0 * sin_d1 - sin_d0 * cos_d1 * cos_a_diff;
mult2 = mult2 * mult2;
numer = sqrt(mult1 + mult2);
denom = sin_d0 *sin_d1 + cos_d0 * cos_d1 * cos_a_diff;
//dist = atan(num);
dist = atan2(numer,denom);
dist *= CONV_FACTOR; // Convert to degrees
if(dist < HIST_MIN)
bin_index = 0;
else if(dist >= HIST_MAX)
bin_index = NUM_BIN + 1;
else
{
//bin_index = int(((dist - HIST_MIN) * NUM_BIN / HIST_MAX) +1);
bin_index = 0;
for (int j=0;j<NUM_BIN-1;j++)
{
//bin_index = 5;
//if (dist>=0.1*j && dist<0.1*(j+1))
//if (dist>=dev_bin_edges[j] && dist<dev_bin_edges[j+1])
if (dist>=bin_edges[j] && dist<bin_edges[j+1])
{
bin_index = j+1;
break;
}
}
}
offset = ((NUM_BIN+2)*thread_idx);
bin_index += offset;
dev_hist[bin_index]++;
}
}
}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv)
{
float *d_alpha0, *d_delta0;
float *h_alpha0, *h_delta0;
float *d_alpha1, *d_delta1;
float *h_alpha1, *h_delta1;
int NUM_PARTICLES;
if (argc < 4)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
FILE *infile0, *infile1, *outfile ;
infile0 = fopen(argv[1],"r");
infile1 = fopen(argv[2],"r");
outfile = fopen(argv[3], "w");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
////////////////////////////////////////////////////////////////////////////
// Read in the first file
////////////////////////////////////////////////////////////////////////////
fscanf(infile0, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile0, "%d", &NUM_PARTICLES);
int size = NUM_PARTICLES * sizeof(float);
printf("SIZE0 # particles: %d\n",NUM_PARTICLES);
h_alpha0 = (float*)malloc(size);
h_delta0 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile0, "%f %s %f %s ", &h_alpha0[i], &dummy, &h_delta0[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
//printf("%e %s %e\n", h_alpha0[i], dummy, h_delta0[i]);
}
////////////////////////////////////////////////////////////////////////////
// Read in the second file
////////////////////////////////////////////////////////////////////////////
fscanf(infile1, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile1, "%d", &NUM_PARTICLES);
printf("SIZE1 # particles: %d\n",NUM_PARTICLES);
h_alpha1 = (float*)malloc(size);
h_delta1 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile1, "%f %s %f %s ", &h_alpha1[i], &dummy, &h_delta1[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
// printf("%e %s %e\n", h_alpha[i], dummy, h_delta[i]);
}
////////////////////////////////////////////////////////////////////////////
//allocation of histogram
///////////////////////////////////////////////////////////////////////////
int *hist, *dev_hist;
// Original
//int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
//int size_hist_bytes = size_hist*sizeof(int);
// Log binning
//float h_bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float h_bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
for (int i=0;i<NUM_BIN;i++)
{
printf("%d %f\n",i,h_bin_edges[i]);
}
printf("\n");
float *dev_bin_edges;
cudaMalloc((void **) &dev_bin_edges, (NUM_BIN*sizeof(float)));
cudaMemset(dev_bin_edges, 0, NUM_BIN);
cudaMemcpy(dev_bin_edges, h_bin_edges, NUM_BIN, cudaMemcpyHostToDevice );
//int nbins = 30;
int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
int size_hist_bytes = size_hist*sizeof(int);
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
printf("size_hist: %d\n",size_hist_bytes);
cudaMalloc((void **) &dev_hist, (size_hist_bytes));
cudaMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
hist_array = (unsigned long*)malloc((NUM_BIN+2) * sizeof(unsigned long));
memset(hist_array, 0, (NUM_BIN+2)*sizeof(unsigned long));
////////////////////////////////////////////////////////////////////////////
// Define the grid and block size
////////////////////////////////////////////////////////////////////////////
dim3 grid, block;
grid.x =100;
block.x = SUBMATRIX_SIZE/grid.x; //NUM_PARTICLES/block.x;
////////////////////////////////////////////////////////////////////////////
cudaMalloc((void **) &d_alpha0, size );
cudaMalloc((void **) &d_delta0, size );
cudaMalloc((void **) &d_alpha1, size );
cudaMalloc((void **) &d_delta1, size );
// Check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(d_alpha0,0,size);
cudaMemset(d_delta0,0,size);
cudaMemset(d_alpha1,0,size);
cudaMemset(d_delta1,0,size);
cudaMemcpy(d_alpha0, h_alpha0, size, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta0, h_delta0, size, cudaMemcpyHostToDevice );
cudaMemcpy(d_alpha1, h_alpha1, size, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta1, h_delta1, size, cudaMemcpyHostToDevice );
int x, y;
int num_submatrices = NUM_PARTICLES / SUBMATRIX_SIZE;
int bin_index = 0;
for(int k = 0; k < num_submatrices; k++)
{
y = k*SUBMATRIX_SIZE;
// printf("%d %d\n",k,y);
for(int j = 0; j < num_submatrices; j++)
{
x = j *SUBMATRIX_SIZE;
//printf("----\n");
//printf("%d %d\t\t%d %d\n",k,y,j,x);
//printf("----\n");
cudaMemset(dev_hist,0,size_hist_bytes);
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, dev_hist, dev_bin_edges);
cudaMemcpy(hist, dev_hist, size_hist_bytes, cudaMemcpyDeviceToHost);
for(int m=0; m<size_hist; m++)
{
bin_index = m%(NUM_BIN+2);
//if(bin_index == 0)
//printf("\n");
//printf("%3i:%3i ", m, hist[m]);
//printf("%3i ", hist[m]);
hist_array[bin_index] += hist[m];
}
//printf("\n");
}
}
unsigned long total = 0;
float bin_width = (HIST_MAX - HIST_MIN) / NUM_BIN;
float bins_mid = 0;
fprintf(outfile, "%s %s\n", "Angular Distance(radians)","Number of Entries");
for(int k=0; k<NUM_BIN+1; k++)
{
//bins_mid = bin_width*(k - 0.5);
float lo = h_bin_edges[k];
float hi = h_bin_edges[k+1];
bins_mid = (hi+lo)/2.0;
fprintf(outfile, "%.3e %s %lu \n", bins_mid, ",", hist_array[k]);
total += hist_array[k];
}
printf("total: %lu \n", total);
fclose(infile0);
fclose(infile1);
fclose(outfile);
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
cudaFree(d_alpha0);
cudaFree(d_delta0);
cudaFree(d_alpha1);
cudaFree(d_delta1);
cudaFree(dev_hist);
cudaFree(dev_bin_edges);
return 0;
}
////////////////////////////////////////////////////////////////////// | .file "tmpxft_00102ea9_00000000-6_Calculate_arc_length_two_datasets.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
.type _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_, @function
_Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8distancePfS_S_S_iiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_, .-_Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
.globl _Z8distancePfS_S_S_iiPiS_
.type _Z8distancePfS_S_S_iiPiS_, @function
_Z8distancePfS_S_S_iiPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8distancePfS_S_S_iiPiS_, .-_Z8distancePfS_S_S_iiPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nMust pass in cluster_data file on command line!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nUsage: "
.section .rodata.str1.8
.align 8
.LC2:
.string " <cluster_data file> <distances file> \n\n"
.section .rodata.str1.1
.LC3:
.string "r"
.LC4:
.string "w"
.LC5:
.string "%s %s %s"
.LC6:
.string "%d"
.LC7:
.string "SIZE0 # particles: %d\n"
.LC8:
.string "%f %s %f %s "
.LC9:
.string "SIZE1 # particles: %d\n"
.LC37:
.string "%d %f\n"
.LC38:
.string "\n"
.LC39:
.string "size_hist: %d\n"
.LC40:
.string "couldn't allocate memory\n"
.LC41:
.string "Number of Entries"
.LC42:
.string "Angular Distance(radians)"
.LC43:
.string "%s %s\n"
.LC44:
.string ","
.LC46:
.string "%.3e %s %lu \n"
.LC47:
.string "total: %lu \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $792, %rsp
.cfi_def_cfa_offset 848
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 776(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L36
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r15
movq %rax, 48(%rsp)
movq 16(%rbx), %rdi
movq %rbp, %rsi
call fopen@PLT
movq %rax, 8(%rsp)
movq 24(%rbx), %rdi
leaq .LC4(%rip), %rsi
call fopen@PLT
movq %rax, (%rsp)
leaq 256(%rsp), %rdx
leaq 512(%rsp), %rcx
movq %rdx, %r8
leaq .LC5(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 68(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %ebx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
sall $2, %ebx
movslq %ebx, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 24(%rsp)
cmpl $0, 68(%rsp)
jle .L13
movl $0, %ebx
leaq .LC8(%rip), %r14
.L14:
leaq 512(%rsp), %rcx
movq %rcx, %r9
movq %rbp, %r8
movq %r13, %rdx
movq %r14, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %r13
addq $4, %rbp
cmpl %ebx, 68(%rsp)
jg .L14
.L13:
leaq 256(%rsp), %rdx
leaq 512(%rsp), %rcx
movq %rdx, %r8
leaq .LC5(%rip), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 68(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 40(%rsp)
cmpl $0, 68(%rsp)
jle .L15
movl $0, %ebx
leaq .LC8(%rip), %r14
.L16:
leaq 512(%rsp), %rcx
movq %rcx, %r9
movq %rbp, %r8
movq %r13, %rdx
movq %r14, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %r13
addq $4, %rbp
cmpl %ebx, 68(%rsp)
jg .L16
.L15:
movl $0x00000000, 144(%rsp)
movl $0x3a83126f, 148(%rsp)
movl $0x3acfbfc6, 152(%rsp)
movl $0x3b24a05e, 156(%rsp)
movl $0x3b82730c, 160(%rsp)
movl $0x3bcec41e, 164(%rsp)
movl $0x3c23d70a, 168(%rsp)
movl $0x3c81d5c3, 172(%rsp)
movl $0x3ccdc65c, 176(%rsp)
movl $0x3d2310dc, 180(%rsp)
movl $0x3d81387a, 184(%rsp)
movl $0x3dcccccd, 188(%rsp)
movl $0x3e224af1, 192(%rsp)
movl $0x3e809bd8, 196(%rsp)
movl $0x3ecbd4ae, 200(%rsp)
movl $0x3f218666, 204(%rsp)
movl $0x3f800000, 208(%rsp)
movl $0x3fcaddc6, 212(%rsp)
movl $0x4020c2bd, 216(%rsp)
movl $0x407ec9e2, 220(%rsp)
movl $0x40c9e806, 224(%rsp)
movl $0x41200000, 228(%rsp)
movl $0x417d953a, 232(%rsp)
movl $0x41c8f36f, 236(%rsp)
movl $0x421f3e2d, 240(%rsp)
movl $0x427c6208, 244(%rsp)
movl $0x42c80000, 248(%rsp)
movl $0, %ebx
leaq .LC37(%rip), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 144(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $27, %rbx
jne .L17
leaq .LC38(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rdi
movl $108, %esi
call cudaMalloc@PLT
movl $27, %edx
movl $0, %esi
movq 112(%rsp), %rdi
call cudaMemset@PLT
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $27, %edx
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1160000, %edi
call malloc@PLT
movq %rax, %rbp
movl $1160000, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movl $1160000, %edx
leaq .LC39(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 104(%rsp), %rdi
movl $1160000, %esi
call cudaMalloc@PLT
movl $1160000, %edx
movl $0, %esi
movq 104(%rsp), %rdi
call cudaMemset@PLT
movl $232, %edi
call malloc@PLT
movq %rax, %rbx
movl $29, %ecx
movl $0, %eax
movq %rbx, %rdi
rep stosq
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $100, 132(%rsp)
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .L18
cmpq $0, 80(%rsp)
je .L18
cmpq $0, 88(%rsp)
je .L18
cmpq $0, 96(%rsp)
je .L18
cmpq $0, 104(%rsp)
je .L18
movq %r12, %rdx
movl $0, %esi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $10000, %esi
movl %ecx, %eax
cltd
idivl %esi
movl %eax, %r14d
cmpl $9999, %ecx
jle .L21
movl $0, %esi
movl $0, %ecx
jmp .L25
.L36:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
leaq .LC40(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L11:
movq 776(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $792, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl $2, %ecx
movl $1160000, %edx
movq 104(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %edx
.L23:
movslq %edx, %rax
imulq $-1925330167, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $4, %eax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $29, %eax, %eax
movl %edx, %ecx
subl %eax, %ecx
movslq %ecx, %rax
movslq 0(%rbp,%rdx,4), %rcx
addq %rcx, (%rbx,%rax,8)
addq $1, %rdx
cmpq $290000, %rdx
jne .L23
addl $1, %r12d
addl $10000, %r13d
cmpl %r12d, %r14d
jle .L38
.L24:
movl $1160000, %edx
movl $0, %esi
movq 104(%rsp), %rdi
call cudaMemset@PLT
movl $100, 120(%rsp)
movl 140(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movq 120(%rsp), %rdi
movl 128(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
pushq 112(%rsp)
.cfi_def_cfa_offset 856
pushq 112(%rsp)
.cfi_def_cfa_offset 864
movl %r15d, %r9d
movl %r13d, %r8d
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
addq $16, %rsp
.cfi_def_cfa_offset 848
jmp .L22
.L38:
movl 56(%rsp), %ecx
movl 60(%rsp), %esi
addl $1, %ecx
addl $10000, %esi
cmpl %ecx, %r14d
jle .L21
.L25:
movl %esi, %r15d
movl $0, %r13d
movl $0, %r12d
movl %ecx, 56(%rsp)
movl %esi, 60(%rsp)
jmp .L24
.L21:
leaq .LC41(%rip), %r8
leaq .LC42(%rip), %rcx
leaq .LC43(%rip), %rdx
movl $2, %esi
movq (%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 148(%rsp), %r12
leaq 260(%rsp), %r15
movl $0, %r14d
.L26:
movq (%rbx), %r13
movss -4(%r12), %xmm0
addss (%r12), %xmm0
mulss .LC45(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r13, %r8
leaq .LC44(%rip), %rcx
leaq .LC46(%rip), %rdx
movl $2, %esi
movq (%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq %r13, %r14
addq $8, %rbx
addq $4, %r12
cmpq %r12, %r15
jne .L26
movq %r14, %rdx
leaq .LC47(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movq (%rsp), %rdi
call fclose@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L11
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC48:
.string "_Z8distancePfS_S_S_iiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC48(%rip), %rdx
movq %rdx, %rcx
leaq _Z8distancePfS_S_S_iiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC45:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include <cuda_runtime.h>
//#include <cutil_inline.h>
using namespace std;
#define SUBMATRIX_SIZE 10000
//#define NUM_BIN 5000
//#define HIST_MIN 0.0
//#define HIST_MAX 3.5
#define NUM_BIN 27 // for log binning
#define HIST_MIN 0.0 // for degrees
#define HIST_MAX 100.0 // for degrees
#define CONV_FACTOR 57.2957795 // 180/pi
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
////////////////////////////////////////////////////////////////////////
__global__ void distance(float *a0, float *d0, float *a1, float *d1, int xind, int yind, int *dev_hist, float* dev_bin_edges)
{
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int thread_idx = idx;
idx += xind;
float alpha = a0[idx], delta0 = d0[idx];
float cos_d0 = cos(delta0), sin_d0 = sin(delta0), dist;
int ymax = yind + SUBMATRIX_SIZE;
int bin_index = 0;
int offset = 0;
float a_diff, sin_a_diff, cos_a_diff;
float cos_d1, sin_d1, numer, denom, mult1, mult2;
for(int i=yind; i<ymax; i++)
{
//if(idx > i) ///////// CHECK THIS
//if(idx >= i)
{
a_diff = a1[i] - alpha;
sin_a_diff = sin(a_diff);
cos_a_diff = cos(a_diff);
sin_d1 = sin(d1[i]);
cos_d1 = cos(d1[i]);
mult1 = cos_d1 * cos_d1 * sin_a_diff * sin_a_diff;
mult2 = cos_d0 * sin_d1 - sin_d0 * cos_d1 * cos_a_diff;
mult2 = mult2 * mult2;
numer = sqrt(mult1 + mult2);
denom = sin_d0 *sin_d1 + cos_d0 * cos_d1 * cos_a_diff;
//dist = atan(num);
dist = atan2(numer,denom);
dist *= CONV_FACTOR; // Convert to degrees
if(dist < HIST_MIN)
bin_index = 0;
else if(dist >= HIST_MAX)
bin_index = NUM_BIN + 1;
else
{
//bin_index = int(((dist - HIST_MIN) * NUM_BIN / HIST_MAX) +1);
bin_index = 0;
for (int j=0;j<NUM_BIN-1;j++)
{
//bin_index = 5;
//if (dist>=0.1*j && dist<0.1*(j+1))
//if (dist>=dev_bin_edges[j] && dist<dev_bin_edges[j+1])
if (dist>=bin_edges[j] && dist<bin_edges[j+1])
{
bin_index = j+1;
break;
}
}
}
offset = ((NUM_BIN+2)*thread_idx);
bin_index += offset;
dev_hist[bin_index]++;
}
}
}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv)
{
float *d_alpha0, *d_delta0;
float *h_alpha0, *h_delta0;
float *d_alpha1, *d_delta1;
float *h_alpha1, *h_delta1;
int NUM_PARTICLES;
if (argc < 4)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
FILE *infile0, *infile1, *outfile ;
infile0 = fopen(argv[1],"r");
infile1 = fopen(argv[2],"r");
outfile = fopen(argv[3], "w");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
////////////////////////////////////////////////////////////////////////////
// Read in the first file
////////////////////////////////////////////////////////////////////////////
fscanf(infile0, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile0, "%d", &NUM_PARTICLES);
int size = NUM_PARTICLES * sizeof(float);
printf("SIZE0 # particles: %d\n",NUM_PARTICLES);
h_alpha0 = (float*)malloc(size);
h_delta0 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile0, "%f %s %f %s ", &h_alpha0[i], &dummy, &h_delta0[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
//printf("%e %s %e\n", h_alpha0[i], dummy, h_delta0[i]);
}
////////////////////////////////////////////////////////////////////////////
// Read in the second file
////////////////////////////////////////////////////////////////////////////
fscanf(infile1, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile1, "%d", &NUM_PARTICLES);
printf("SIZE1 # particles: %d\n",NUM_PARTICLES);
h_alpha1 = (float*)malloc(size);
h_delta1 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile1, "%f %s %f %s ", &h_alpha1[i], &dummy, &h_delta1[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
// printf("%e %s %e\n", h_alpha[i], dummy, h_delta[i]);
}
////////////////////////////////////////////////////////////////////////////
//allocation of histogram
///////////////////////////////////////////////////////////////////////////
int *hist, *dev_hist;
// Original
//int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
//int size_hist_bytes = size_hist*sizeof(int);
// Log binning
//float h_bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float h_bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
for (int i=0;i<NUM_BIN;i++)
{
printf("%d %f\n",i,h_bin_edges[i]);
}
printf("\n");
float *dev_bin_edges;
cudaMalloc((void **) &dev_bin_edges, (NUM_BIN*sizeof(float)));
cudaMemset(dev_bin_edges, 0, NUM_BIN);
cudaMemcpy(dev_bin_edges, h_bin_edges, NUM_BIN, cudaMemcpyHostToDevice );
//int nbins = 30;
int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
int size_hist_bytes = size_hist*sizeof(int);
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
printf("size_hist: %d\n",size_hist_bytes);
cudaMalloc((void **) &dev_hist, (size_hist_bytes));
cudaMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
hist_array = (unsigned long*)malloc((NUM_BIN+2) * sizeof(unsigned long));
memset(hist_array, 0, (NUM_BIN+2)*sizeof(unsigned long));
////////////////////////////////////////////////////////////////////////////
// Define the grid and block size
////////////////////////////////////////////////////////////////////////////
dim3 grid, block;
grid.x =100;
block.x = SUBMATRIX_SIZE/grid.x; //NUM_PARTICLES/block.x;
////////////////////////////////////////////////////////////////////////////
cudaMalloc((void **) &d_alpha0, size );
cudaMalloc((void **) &d_delta0, size );
cudaMalloc((void **) &d_alpha1, size );
cudaMalloc((void **) &d_delta1, size );
// Check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(d_alpha0,0,size);
cudaMemset(d_delta0,0,size);
cudaMemset(d_alpha1,0,size);
cudaMemset(d_delta1,0,size);
cudaMemcpy(d_alpha0, h_alpha0, size, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta0, h_delta0, size, cudaMemcpyHostToDevice );
cudaMemcpy(d_alpha1, h_alpha1, size, cudaMemcpyHostToDevice );
cudaMemcpy(d_delta1, h_delta1, size, cudaMemcpyHostToDevice );
int x, y;
int num_submatrices = NUM_PARTICLES / SUBMATRIX_SIZE;
int bin_index = 0;
for(int k = 0; k < num_submatrices; k++)
{
y = k*SUBMATRIX_SIZE;
// printf("%d %d\n",k,y);
for(int j = 0; j < num_submatrices; j++)
{
x = j *SUBMATRIX_SIZE;
//printf("----\n");
//printf("%d %d\t\t%d %d\n",k,y,j,x);
//printf("----\n");
cudaMemset(dev_hist,0,size_hist_bytes);
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, dev_hist, dev_bin_edges);
cudaMemcpy(hist, dev_hist, size_hist_bytes, cudaMemcpyDeviceToHost);
for(int m=0; m<size_hist; m++)
{
bin_index = m%(NUM_BIN+2);
//if(bin_index == 0)
//printf("\n");
//printf("%3i:%3i ", m, hist[m]);
//printf("%3i ", hist[m]);
hist_array[bin_index] += hist[m];
}
//printf("\n");
}
}
unsigned long total = 0;
float bin_width = (HIST_MAX - HIST_MIN) / NUM_BIN;
float bins_mid = 0;
fprintf(outfile, "%s %s\n", "Angular Distance(radians)","Number of Entries");
for(int k=0; k<NUM_BIN+1; k++)
{
//bins_mid = bin_width*(k - 0.5);
float lo = h_bin_edges[k];
float hi = h_bin_edges[k+1];
bins_mid = (hi+lo)/2.0;
fprintf(outfile, "%.3e %s %lu \n", bins_mid, ",", hist_array[k]);
total += hist_array[k];
}
printf("total: %lu \n", total);
fclose(infile0);
fclose(infile1);
fclose(outfile);
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
cudaFree(d_alpha0);
cudaFree(d_delta0);
cudaFree(d_alpha1);
cudaFree(d_delta1);
cudaFree(dev_hist);
cudaFree(dev_bin_edges);
return 0;
}
////////////////////////////////////////////////////////////////////// | #include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include <hip/hip_runtime.h>
//#include <cutil_inline.h>
using namespace std;
#define SUBMATRIX_SIZE 10000
//#define NUM_BIN 5000
//#define HIST_MIN 0.0
//#define HIST_MAX 3.5
#define NUM_BIN 27 // for log binning
#define HIST_MIN 0.0 // for degrees
#define HIST_MAX 100.0 // for degrees
#define CONV_FACTOR 57.2957795 // 180/pi
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
////////////////////////////////////////////////////////////////////////
__global__ void distance(float *a0, float *d0, float *a1, float *d1, int xind, int yind, int *dev_hist, float* dev_bin_edges)
{
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int thread_idx = idx;
idx += xind;
float alpha = a0[idx], delta0 = d0[idx];
float cos_d0 = cos(delta0), sin_d0 = sin(delta0), dist;
int ymax = yind + SUBMATRIX_SIZE;
int bin_index = 0;
int offset = 0;
float a_diff, sin_a_diff, cos_a_diff;
float cos_d1, sin_d1, numer, denom, mult1, mult2;
for(int i=yind; i<ymax; i++)
{
//if(idx > i) ///////// CHECK THIS
//if(idx >= i)
{
a_diff = a1[i] - alpha;
sin_a_diff = sin(a_diff);
cos_a_diff = cos(a_diff);
sin_d1 = sin(d1[i]);
cos_d1 = cos(d1[i]);
mult1 = cos_d1 * cos_d1 * sin_a_diff * sin_a_diff;
mult2 = cos_d0 * sin_d1 - sin_d0 * cos_d1 * cos_a_diff;
mult2 = mult2 * mult2;
numer = sqrt(mult1 + mult2);
denom = sin_d0 *sin_d1 + cos_d0 * cos_d1 * cos_a_diff;
//dist = atan(num);
dist = atan2(numer,denom);
dist *= CONV_FACTOR; // Convert to degrees
if(dist < HIST_MIN)
bin_index = 0;
else if(dist >= HIST_MAX)
bin_index = NUM_BIN + 1;
else
{
//bin_index = int(((dist - HIST_MIN) * NUM_BIN / HIST_MAX) +1);
bin_index = 0;
for (int j=0;j<NUM_BIN-1;j++)
{
//bin_index = 5;
//if (dist>=0.1*j && dist<0.1*(j+1))
//if (dist>=dev_bin_edges[j] && dist<dev_bin_edges[j+1])
if (dist>=bin_edges[j] && dist<bin_edges[j+1])
{
bin_index = j+1;
break;
}
}
}
offset = ((NUM_BIN+2)*thread_idx);
bin_index += offset;
dev_hist[bin_index]++;
}
}
}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv)
{
float *d_alpha0, *d_delta0;
float *h_alpha0, *h_delta0;
float *d_alpha1, *d_delta1;
float *h_alpha1, *h_delta1;
int NUM_PARTICLES;
if (argc < 4)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
FILE *infile0, *infile1, *outfile ;
infile0 = fopen(argv[1],"r");
infile1 = fopen(argv[2],"r");
outfile = fopen(argv[3], "w");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
////////////////////////////////////////////////////////////////////////////
// Read in the first file
////////////////////////////////////////////////////////////////////////////
fscanf(infile0, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile0, "%d", &NUM_PARTICLES);
int size = NUM_PARTICLES * sizeof(float);
printf("SIZE0 # particles: %d\n",NUM_PARTICLES);
h_alpha0 = (float*)malloc(size);
h_delta0 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile0, "%f %s %f %s ", &h_alpha0[i], &dummy, &h_delta0[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
//printf("%e %s %e\n", h_alpha0[i], dummy, h_delta0[i]);
}
////////////////////////////////////////////////////////////////////////////
// Read in the second file
////////////////////////////////////////////////////////////////////////////
fscanf(infile1, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile1, "%d", &NUM_PARTICLES);
printf("SIZE1 # particles: %d\n",NUM_PARTICLES);
h_alpha1 = (float*)malloc(size);
h_delta1 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile1, "%f %s %f %s ", &h_alpha1[i], &dummy, &h_delta1[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
// printf("%e %s %e\n", h_alpha[i], dummy, h_delta[i]);
}
////////////////////////////////////////////////////////////////////////////
//allocation of histogram
///////////////////////////////////////////////////////////////////////////
int *hist, *dev_hist;
// Original
//int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
//int size_hist_bytes = size_hist*sizeof(int);
// Log binning
//float h_bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float h_bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
for (int i=0;i<NUM_BIN;i++)
{
printf("%d %f\n",i,h_bin_edges[i]);
}
printf("\n");
float *dev_bin_edges;
hipMalloc((void **) &dev_bin_edges, (NUM_BIN*sizeof(float)));
hipMemset(dev_bin_edges, 0, NUM_BIN);
hipMemcpy(dev_bin_edges, h_bin_edges, NUM_BIN, hipMemcpyHostToDevice );
//int nbins = 30;
int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
int size_hist_bytes = size_hist*sizeof(int);
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
printf("size_hist: %d\n",size_hist_bytes);
hipMalloc((void **) &dev_hist, (size_hist_bytes));
hipMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
hist_array = (unsigned long*)malloc((NUM_BIN+2) * sizeof(unsigned long));
memset(hist_array, 0, (NUM_BIN+2)*sizeof(unsigned long));
////////////////////////////////////////////////////////////////////////////
// Define the grid and block size
////////////////////////////////////////////////////////////////////////////
dim3 grid, block;
grid.x =100;
block.x = SUBMATRIX_SIZE/grid.x; //NUM_PARTICLES/block.x;
////////////////////////////////////////////////////////////////////////////
hipMalloc((void **) &d_alpha0, size );
hipMalloc((void **) &d_delta0, size );
hipMalloc((void **) &d_alpha1, size );
hipMalloc((void **) &d_delta1, size );
// Check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(d_alpha0,0,size);
hipMemset(d_delta0,0,size);
hipMemset(d_alpha1,0,size);
hipMemset(d_delta1,0,size);
hipMemcpy(d_alpha0, h_alpha0, size, hipMemcpyHostToDevice );
hipMemcpy(d_delta0, h_delta0, size, hipMemcpyHostToDevice );
hipMemcpy(d_alpha1, h_alpha1, size, hipMemcpyHostToDevice );
hipMemcpy(d_delta1, h_delta1, size, hipMemcpyHostToDevice );
int x, y;
int num_submatrices = NUM_PARTICLES / SUBMATRIX_SIZE;
int bin_index = 0;
for(int k = 0; k < num_submatrices; k++)
{
y = k*SUBMATRIX_SIZE;
// printf("%d %d\n",k,y);
for(int j = 0; j < num_submatrices; j++)
{
x = j *SUBMATRIX_SIZE;
//printf("----\n");
//printf("%d %d\t\t%d %d\n",k,y,j,x);
//printf("----\n");
hipMemset(dev_hist,0,size_hist_bytes);
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, dev_hist, dev_bin_edges);
hipMemcpy(hist, dev_hist, size_hist_bytes, hipMemcpyDeviceToHost);
for(int m=0; m<size_hist; m++)
{
bin_index = m%(NUM_BIN+2);
//if(bin_index == 0)
//printf("\n");
//printf("%3i:%3i ", m, hist[m]);
//printf("%3i ", hist[m]);
hist_array[bin_index] += hist[m];
}
//printf("\n");
}
}
unsigned long total = 0;
float bin_width = (HIST_MAX - HIST_MIN) / NUM_BIN;
float bins_mid = 0;
fprintf(outfile, "%s %s\n", "Angular Distance(radians)","Number of Entries");
for(int k=0; k<NUM_BIN+1; k++)
{
//bins_mid = bin_width*(k - 0.5);
float lo = h_bin_edges[k];
float hi = h_bin_edges[k+1];
bins_mid = (hi+lo)/2.0;
fprintf(outfile, "%.3e %s %lu \n", bins_mid, ",", hist_array[k]);
total += hist_array[k];
}
printf("total: %lu \n", total);
fclose(infile0);
fclose(infile1);
fclose(outfile);
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
hipFree(d_alpha0);
hipFree(d_delta0);
hipFree(d_alpha1);
hipFree(d_delta1);
hipFree(dev_hist);
hipFree(dev_bin_edges);
return 0;
}
////////////////////////////////////////////////////////////////////// |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<string.h>
#include<stdlib.h>
#include<math.h>
#include <hip/hip_runtime.h>
//#include <cutil_inline.h>
using namespace std;
#define SUBMATRIX_SIZE 10000
//#define NUM_BIN 5000
//#define HIST_MIN 0.0
//#define HIST_MAX 3.5
#define NUM_BIN 27 // for log binning
#define HIST_MIN 0.0 // for degrees
#define HIST_MAX 100.0 // for degrees
#define CONV_FACTOR 57.2957795 // 180/pi
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
////////////////////////////////////////////////////////////////////////
__global__ void distance(float *a0, float *d0, float *a1, float *d1, int xind, int yind, int *dev_hist, float* dev_bin_edges)
{
//float bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int thread_idx = idx;
idx += xind;
float alpha = a0[idx], delta0 = d0[idx];
float cos_d0 = cos(delta0), sin_d0 = sin(delta0), dist;
int ymax = yind + SUBMATRIX_SIZE;
int bin_index = 0;
int offset = 0;
float a_diff, sin_a_diff, cos_a_diff;
float cos_d1, sin_d1, numer, denom, mult1, mult2;
for(int i=yind; i<ymax; i++)
{
//if(idx > i) ///////// CHECK THIS
//if(idx >= i)
{
a_diff = a1[i] - alpha;
sin_a_diff = sin(a_diff);
cos_a_diff = cos(a_diff);
sin_d1 = sin(d1[i]);
cos_d1 = cos(d1[i]);
mult1 = cos_d1 * cos_d1 * sin_a_diff * sin_a_diff;
mult2 = cos_d0 * sin_d1 - sin_d0 * cos_d1 * cos_a_diff;
mult2 = mult2 * mult2;
numer = sqrt(mult1 + mult2);
denom = sin_d0 *sin_d1 + cos_d0 * cos_d1 * cos_a_diff;
//dist = atan(num);
dist = atan2(numer,denom);
dist *= CONV_FACTOR; // Convert to degrees
if(dist < HIST_MIN)
bin_index = 0;
else if(dist >= HIST_MAX)
bin_index = NUM_BIN + 1;
else
{
//bin_index = int(((dist - HIST_MIN) * NUM_BIN / HIST_MAX) +1);
bin_index = 0;
for (int j=0;j<NUM_BIN-1;j++)
{
//bin_index = 5;
//if (dist>=0.1*j && dist<0.1*(j+1))
//if (dist>=dev_bin_edges[j] && dist<dev_bin_edges[j+1])
if (dist>=bin_edges[j] && dist<bin_edges[j+1])
{
bin_index = j+1;
break;
}
}
}
offset = ((NUM_BIN+2)*thread_idx);
bin_index += offset;
dev_hist[bin_index]++;
}
}
}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv)
{
float *d_alpha0, *d_delta0;
float *h_alpha0, *h_delta0;
float *d_alpha1, *d_delta1;
float *h_alpha1, *h_delta1;
int NUM_PARTICLES;
if (argc < 4)
{
printf("\nMust pass in cluster_data file on command line!\n");
printf("\nUsage: ", argv[0] );
printf(" <cluster_data file> <distances file> \n\n");
exit(1);
}
FILE *infile0, *infile1, *outfile ;
infile0 = fopen(argv[1],"r");
infile1 = fopen(argv[2],"r");
outfile = fopen(argv[3], "w");
//////////////////////////////////////////////////////////////////////
// Read in the cluster_data file
////////////////////////////////////////////////////////////////////////////
char axis_titles[256];
char dummy[256];
////////////////////////////////////////////////////////////////////////////
// Read in the first file
////////////////////////////////////////////////////////////////////////////
fscanf(infile0, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile0, "%d", &NUM_PARTICLES);
int size = NUM_PARTICLES * sizeof(float);
printf("SIZE0 # particles: %d\n",NUM_PARTICLES);
h_alpha0 = (float*)malloc(size);
h_delta0 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile0, "%f %s %f %s ", &h_alpha0[i], &dummy, &h_delta0[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
//printf("%e %s %e\n", h_alpha0[i], dummy, h_delta0[i]);
}
////////////////////////////////////////////////////////////////////////////
// Read in the second file
////////////////////////////////////////////////////////////////////////////
fscanf(infile1, "%s %s %s", &axis_titles, &dummy, &axis_titles);
fscanf(infile1, "%d", &NUM_PARTICLES);
printf("SIZE1 # particles: %d\n",NUM_PARTICLES);
h_alpha1 = (float*)malloc(size);
h_delta1 = (float*)malloc(size);
for(int i=0; i<NUM_PARTICLES; i++)
{
fscanf(infile1, "%f %s %f %s ", &h_alpha1[i], &dummy, &h_delta1[i], &dummy);
//fscanf(infile, "%f%s %f ", &h_alpha[i], &dummy, &h_delta[i]);
// printf("%e %s %e\n", h_alpha[i], dummy, h_delta[i]);
}
////////////////////////////////////////////////////////////////////////////
//allocation of histogram
///////////////////////////////////////////////////////////////////////////
int *hist, *dev_hist;
// Original
//int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
//int size_hist_bytes = size_hist*sizeof(int);
// Log binning
//float h_bin_edges[30] = {0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
float h_bin_edges[NUM_BIN] = {0.0000,0.001000,0.001585,0.002512,0.003981,0.006310,0.010000,0.015849,0.025119,0.039811,0.063096,0.100000,0.158489,0.251189,0.398107,0.630957,1.000000,1.584893,2.511886,3.981072,6.309573,10.000000,15.848932,25.118864,39.810717,63.095734,100.000000};
for (int i=0;i<NUM_BIN;i++)
{
printf("%d %f\n",i,h_bin_edges[i]);
}
printf("\n");
float *dev_bin_edges;
hipMalloc((void **) &dev_bin_edges, (NUM_BIN*sizeof(float)));
hipMemset(dev_bin_edges, 0, NUM_BIN);
hipMemcpy(dev_bin_edges, h_bin_edges, NUM_BIN, hipMemcpyHostToDevice );
//int nbins = 30;
int size_hist = SUBMATRIX_SIZE * (NUM_BIN+2);
int size_hist_bytes = size_hist*sizeof(int);
hist = (int*)malloc(size_hist_bytes);
memset(hist, 0, size_hist_bytes);
printf("size_hist: %d\n",size_hist_bytes);
hipMalloc((void **) &dev_hist, (size_hist_bytes));
hipMemset(dev_hist, 0, size_hist_bytes);
unsigned long *hist_array;
hist_array = (unsigned long*)malloc((NUM_BIN+2) * sizeof(unsigned long));
memset(hist_array, 0, (NUM_BIN+2)*sizeof(unsigned long));
////////////////////////////////////////////////////////////////////////////
// Define the grid and block size
////////////////////////////////////////////////////////////////////////////
dim3 grid, block;
grid.x =100;
block.x = SUBMATRIX_SIZE/grid.x; //NUM_PARTICLES/block.x;
////////////////////////////////////////////////////////////////////////////
hipMalloc((void **) &d_alpha0, size );
hipMalloc((void **) &d_delta0, size );
hipMalloc((void **) &d_alpha1, size );
hipMalloc((void **) &d_delta1, size );
// Check to see if we allocated enough memory.
if (0==d_alpha0 || 0==d_delta0 || 0==d_alpha1 || 0==d_delta1 || 0==dev_hist)
{
printf("couldn't allocate memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(d_alpha0,0,size);
hipMemset(d_delta0,0,size);
hipMemset(d_alpha1,0,size);
hipMemset(d_delta1,0,size);
hipMemcpy(d_alpha0, h_alpha0, size, hipMemcpyHostToDevice );
hipMemcpy(d_delta0, h_delta0, size, hipMemcpyHostToDevice );
hipMemcpy(d_alpha1, h_alpha1, size, hipMemcpyHostToDevice );
hipMemcpy(d_delta1, h_delta1, size, hipMemcpyHostToDevice );
int x, y;
int num_submatrices = NUM_PARTICLES / SUBMATRIX_SIZE;
int bin_index = 0;
for(int k = 0; k < num_submatrices; k++)
{
y = k*SUBMATRIX_SIZE;
// printf("%d %d\n",k,y);
for(int j = 0; j < num_submatrices; j++)
{
x = j *SUBMATRIX_SIZE;
//printf("----\n");
//printf("%d %d\t\t%d %d\n",k,y,j,x);
//printf("----\n");
hipMemset(dev_hist,0,size_hist_bytes);
distance<<<grid,block>>>(d_alpha0, d_delta0,d_alpha1, d_delta1, x, y, dev_hist, dev_bin_edges);
hipMemcpy(hist, dev_hist, size_hist_bytes, hipMemcpyDeviceToHost);
for(int m=0; m<size_hist; m++)
{
bin_index = m%(NUM_BIN+2);
//if(bin_index == 0)
//printf("\n");
//printf("%3i:%3i ", m, hist[m]);
//printf("%3i ", hist[m]);
hist_array[bin_index] += hist[m];
}
//printf("\n");
}
}
unsigned long total = 0;
float bin_width = (HIST_MAX - HIST_MIN) / NUM_BIN;
float bins_mid = 0;
fprintf(outfile, "%s %s\n", "Angular Distance(radians)","Number of Entries");
for(int k=0; k<NUM_BIN+1; k++)
{
//bins_mid = bin_width*(k - 0.5);
float lo = h_bin_edges[k];
float hi = h_bin_edges[k+1];
bins_mid = (hi+lo)/2.0;
fprintf(outfile, "%.3e %s %lu \n", bins_mid, ",", hist_array[k]);
total += hist_array[k];
}
printf("total: %lu \n", total);
fclose(infile0);
fclose(infile1);
fclose(outfile);
free(h_alpha0);
free(h_delta0);
free(h_alpha1);
free(h_delta1);
free(hist);
hipFree(d_alpha0);
hipFree(d_delta0);
hipFree(d_alpha1);
hipFree(d_delta1);
hipFree(dev_hist);
hipFree(dev_bin_edges);
return 0;
}
////////////////////////////////////////////////////////////////////// | .text
.file "Calculate_arc_length_two_datasets.hip"
.globl _Z23__device_stub__distancePfS_S_S_iiPiS_ # -- Begin function _Z23__device_stub__distancePfS_S_S_iiPiS_
.p2align 4, 0x90
.type _Z23__device_stub__distancePfS_S_S_iiPiS_,@function
_Z23__device_stub__distancePfS_S_S_iiPiS_: # @_Z23__device_stub__distancePfS_S_S_iiPiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8distancePfS_S_S_iiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z23__device_stub__distancePfS_S_S_iiPiS_, .Lfunc_end0-_Z23__device_stub__distancePfS_S_S_iiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $3, %edi
jle .LBB1_28
# %bb.1:
movq 8(%rbx), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r13
movq 16(%rbx), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, 112(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, 120(%rsp) # 8-byte Spill
leaq 416(%rsp), %rcx
leaq 672(%rsp), %rdx
movl $.L.str.5, %esi
movq %r13, %rdi
movq %rdx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
leaq 12(%rsp), %rdx
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %esi
leal (,%rsi,4), %ebx
movl $.L.str.7, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movslq %ebx, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %rbx, 24(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
leaq 416(%rsp), %rbx
movq 96(%rsp), %r14 # 8-byte Reload
movq 88(%rsp), %r15 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %r13, %rdi
movq %r14, %rdx
movq %rbx, %rcx
movq %r15, %r8
movq %rbx, %r9
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 12(%rsp), %rax
addq $4, %r15
addq $4, %r14
cmpq %rax, %r12
jl .LBB1_3
.LBB1_4: # %._crit_edge
leaq 416(%rsp), %rcx
leaq 672(%rsp), %rdx
movl $.L.str.5, %esi
movq 112(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %rdx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
leaq 12(%rsp), %rdx
movl $.L.str.6, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB1_7
# %bb.5: # %.lr.ph135.preheader
leaq 416(%rsp), %rbx
movq 80(%rsp), %r14 # 8-byte Reload
movq 72(%rsp), %r15 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph135
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %rbp, %rdi
movq %r14, %rdx
movq %rbx, %rcx
movq %r15, %r8
movq %rbx, %r9
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 12(%rsp), %rax
addq $4, %r15
addq $4, %r14
cmpq %rax, %r12
jl .LBB1_6
.LBB1_7: # %._crit_edge136
movq %r13, 128(%rsp) # 8-byte Spill
movups .L__const.main.h_bin_edges+92(%rip), %xmm0
movups %xmm0, 396(%rsp)
movaps .L__const.main.h_bin_edges+80(%rip), %xmm0
movaps %xmm0, 384(%rsp)
movaps .L__const.main.h_bin_edges+64(%rip), %xmm0
movaps %xmm0, 368(%rsp)
movaps .L__const.main.h_bin_edges+48(%rip), %xmm0
movaps %xmm0, 352(%rsp)
movaps .L__const.main.h_bin_edges+32(%rip), %xmm0
movaps %xmm0, 336(%rsp)
movaps .L__const.main.h_bin_edges+16(%rip), %xmm0
movaps %xmm0, 320(%rsp)
movaps .L__const.main.h_bin_edges(%rip), %xmm0
movaps %xmm0, 304(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movss 304(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $27, %rbx
jne .LBB1_8
# %bb.9:
movl $10, %edi
callq putchar@PLT
leaq 56(%rsp), %rdi
movl $108, %esi
callq hipMalloc
movq 56(%rsp), %rdi
movl $27, %edx
xorl %esi, %esi
callq hipMemset
movq 56(%rsp), %rdi
leaq 304(%rsp), %rsi
movl $1, %r14d
movl $27, %edx
movl $1, %ecx
callq hipMemcpy
movl $1160000, %edi # imm = 0x11B340
callq malloc
movq %rax, %r13
movl $1160000, %edx # imm = 0x11B340
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $.L.str.12, %edi
movl $1160000, %esi # imm = 0x11B340
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $1160000, %esi # imm = 0x11B340
callq hipMalloc
movq 16(%rsp), %rdi
movl $1160000, %edx # imm = 0x11B340
xorl %esi, %esi
callq hipMemset
movl $232, %edi
callq malloc
movq %rax, %r12
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movups %xmm0, 192(%rax)
movups %xmm0, 208(%rax)
movq $0, 224(%rax)
leaq 64(%rsp), %rdi
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_14
# %bb.10:
cmpq $0, 48(%rsp)
je .LBB1_14
# %bb.11:
cmpq $0, 40(%rsp)
je .LBB1_14
# %bb.12:
cmpq $0, 32(%rsp)
je .LBB1_14
# %bb.13:
cmpq $0, 16(%rsp)
je .LBB1_14
# %bb.15:
xorl %esi, %esi
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
callq hipMemset
movq 48(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 40(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 32(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 64(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %ecx, %ecx
movslq 12(%rsp), %rax
cmpq $10000, %rax # imm = 0x2710
jl .LBB1_24
# %bb.16: # %.lr.ph145
imulq $1759218605, %rax, %r14 # imm = 0x68DB8BAD
movq %r14, %rax
shrq $63, %rax
sarq $44, %r14
addl %eax, %r14d
movabsq $4294967396, %rbp # imm = 0x100000064
movabsq $1908283869694091547, %r15 # imm = 0x1A7B9611A7B9611B
.p2align 4, 0x90
.LBB1_17: # %.lr.ph141.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
# Child Loop BB1_21 Depth 3
movq %rcx, 136(%rsp) # 8-byte Spill
imull $10000, %ecx, %eax # imm = 0x2710
movl %eax, 24(%rsp) # 4-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_18: # %.lr.ph141
# Parent Loop BB1_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_21 Depth 3
movq 16(%rsp), %rdi
movl $1160000, %edx # imm = 0x11B340
xorl %esi, %esi
callq hipMemset
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19: # in Loop: Header=BB1_18 Depth=2
movq 64(%rsp), %rax
movq %rax, 232(%rsp)
movq 48(%rsp), %rax
movq %rax, 224(%rsp)
movq 40(%rsp), %rax
movq %rax, 216(%rsp)
movq 32(%rsp), %rax
movq %rax, 208(%rsp)
imull $10000, %ebx, %eax # imm = 0x2710
movl %eax, 108(%rsp)
movq 16(%rsp), %rax
movq %rax, 200(%rsp)
movq 56(%rsp), %rax
movq %rax, 192(%rsp)
movl 24(%rsp), %eax # 4-byte Reload
movl %eax, 104(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 108(%rsp), %rax
movq %rax, 272(%rsp)
leaq 104(%rsp), %rax
movq %rax, 280(%rsp)
leaq 200(%rsp), %rax
movq %rax, 288(%rsp)
leaq 192(%rsp), %rax
movq %rax, 296(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z8distancePfS_S_S_iiPiS_, %edi
leaq 240(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20: # in Loop: Header=BB1_18 Depth=2
movq 16(%rsp), %rsi
movl $1160000, %edx # imm = 0x11B340
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rsi
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_21: # Parent Loop BB1_17 Depth=1
# Parent Loop BB1_18 Depth=2
# => This Inner Loop Header: Depth=3
movq %rcx, %rax
mulq %r15
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $4, %rax
imulq $-232, %rax, %rax
movslq (%r13,%rcx,4), %rdx
addq %rdx, (%rsi,%rax)
incq %rcx
addq $8, %rsi
cmpq $290000, %rcx # imm = 0x46CD0
jne .LBB1_21
# %bb.22: # in Loop: Header=BB1_18 Depth=2
incl %ebx
cmpl %r14d, %ebx
jne .LBB1_18
# %bb.23: # %._crit_edge142
# in Loop: Header=BB1_17 Depth=1
movq 136(%rsp), %rcx # 8-byte Reload
incl %ecx
cmpl %r14d, %ecx
jne .LBB1_17
.LBB1_24: # %._crit_edge146
xorl %r14d, %r14d
movl $.L.str.14, %esi
movl $.L.str.15, %edx
movl $.L.str.16, %ecx
movq 120(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
xorl %eax, %eax
callq fprintf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_25: # =>This Inner Loop Header: Depth=1
movss 304(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 308(%rsp,%r14,4), %xmm0
leaq 1(%r14), %r15
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq (%r12,%r14,8), %r14
movl $.L.str.17, %esi
movl $.L.str.18, %edx
movq %rbp, %rdi
movq %r14, %rcx
movb $1, %al
callq fprintf
addq %r14, %rbx
movq %r15, %r14
cmpq $28, %r15
jne .LBB1_25
# %bb.26:
xorl %r14d, %r14d
movl $.L.str.19, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 128(%rsp), %rdi # 8-byte Reload
callq fclose
movq 112(%rsp), %rdi # 8-byte Reload
callq fclose
movq %rbp, %rdi
callq fclose
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
jmp .LBB1_27
.LBB1_14:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_27:
movl %r14d, %eax
addq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_28:
.cfi_def_cfa_offset 992
movl $.Lstr.1, %edi
callq puts@PLT
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8distancePfS_S_S_iiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8distancePfS_S_S_iiPiS_,@object # @_Z8distancePfS_S_S_iiPiS_
.section .rodata,"a",@progbits
.globl _Z8distancePfS_S_S_iiPiS_
.p2align 3, 0x0
_Z8distancePfS_S_S_iiPiS_:
.quad _Z23__device_stub__distancePfS_S_S_iiPiS_
.size _Z8distancePfS_S_S_iiPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nUsage: "
.size .L.str.1, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "w"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s %s %s"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "SIZE0 # particles: %d\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f %s %f %s "
.size .L.str.8, 13
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "SIZE1 # particles: %d\n"
.size .L.str.9, 23
.type .L__const.main.h_bin_edges,@object # @__const.main.h_bin_edges
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.h_bin_edges:
.long 0x00000000 # float 0
.long 0x3a83126f # float 0.00100000005
.long 0x3acfbfc6 # float 0.00158499996
.long 0x3b24a05e # float 0.00251200004
.long 0x3b82730c # float 0.00398099981
.long 0x3bcec41e # float 0.00631000008
.long 0x3c23d70a # float 0.00999999977
.long 0x3c81d5c3 # float 0.0158489998
.long 0x3ccdc65c # float 0.0251189992
.long 0x3d2310dc # float 0.0398110002
.long 0x3d81387a # float 0.0630960017
.long 0x3dcccccd # float 0.100000001
.long 0x3e224af1 # float 0.158489004
.long 0x3e809bd8 # float 0.251188993
.long 0x3ecbd4ae # float 0.398106992
.long 0x3f218666 # float 0.630957007
.long 0x3f800000 # float 1
.long 0x3fcaddc6 # float 1.58489299
.long 0x4020c2bd # float 2.51188588
.long 0x407ec9e2 # float 3.98107195
.long 0x40c9e806 # float 6.30957317
.long 0x41200000 # float 10
.long 0x417d953a # float 15.8489323
.long 0x41c8f36f # float 25.1188641
.long 0x421f3e2d # float 39.8107185
.long 0x427c6208 # float 63.0957336
.long 0x42c80000 # float 100
.size .L__const.main.h_bin_edges, 108
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz "%d %f\n"
.size .L.str.10, 7
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "size_hist: %d\n"
.size .L.str.12, 15
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%s %s\n"
.size .L.str.14, 7
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Angular Distance(radians)"
.size .L.str.15, 26
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Number of Entries"
.size .L.str.16, 18
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%.3e %s %lu \n"
.size .L.str.17, 14
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz ","
.size .L.str.18, 2
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "total: %lu \n"
.size .L.str.19, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8distancePfS_S_S_iiPiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nMust pass in cluster_data file on command line!"
.size .Lstr.1, 50
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " <cluster_data file> <distances file> \n"
.size .Lstr.2, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__distancePfS_S_S_iiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8distancePfS_S_S_iiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00102ea9_00000000-6_Calculate_arc_length_two_datasets.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
.type _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_, @function
_Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8distancePfS_S_S_iiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_, .-_Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
.globl _Z8distancePfS_S_S_iiPiS_
.type _Z8distancePfS_S_S_iiPiS_, @function
_Z8distancePfS_S_S_iiPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8distancePfS_S_S_iiPiS_, .-_Z8distancePfS_S_S_iiPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nMust pass in cluster_data file on command line!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nUsage: "
.section .rodata.str1.8
.align 8
.LC2:
.string " <cluster_data file> <distances file> \n\n"
.section .rodata.str1.1
.LC3:
.string "r"
.LC4:
.string "w"
.LC5:
.string "%s %s %s"
.LC6:
.string "%d"
.LC7:
.string "SIZE0 # particles: %d\n"
.LC8:
.string "%f %s %f %s "
.LC9:
.string "SIZE1 # particles: %d\n"
.LC37:
.string "%d %f\n"
.LC38:
.string "\n"
.LC39:
.string "size_hist: %d\n"
.LC40:
.string "couldn't allocate memory\n"
.LC41:
.string "Number of Entries"
.LC42:
.string "Angular Distance(radians)"
.LC43:
.string "%s %s\n"
.LC44:
.string ","
.LC46:
.string "%.3e %s %lu \n"
.LC47:
.string "total: %lu \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $792, %rsp
.cfi_def_cfa_offset 848
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 776(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L36
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rbp
movq %rbp, %rsi
call fopen@PLT
movq %rax, %r15
movq %rax, 48(%rsp)
movq 16(%rbx), %rdi
movq %rbp, %rsi
call fopen@PLT
movq %rax, 8(%rsp)
movq 24(%rbx), %rdi
leaq .LC4(%rip), %rsi
call fopen@PLT
movq %rax, (%rsp)
leaq 256(%rsp), %rdx
leaq 512(%rsp), %rcx
movq %rdx, %r8
leaq .LC5(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 68(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %ebx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
sall $2, %ebx
movslq %ebx, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 24(%rsp)
cmpl $0, 68(%rsp)
jle .L13
movl $0, %ebx
leaq .LC8(%rip), %r14
.L14:
leaq 512(%rsp), %rcx
movq %rcx, %r9
movq %rbp, %r8
movq %r13, %rdx
movq %r14, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %r13
addq $4, %rbp
cmpl %ebx, 68(%rsp)
jg .L14
.L13:
leaq 256(%rsp), %rdx
leaq 512(%rsp), %rcx
movq %rdx, %r8
leaq .LC5(%rip), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 68(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 68(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 40(%rsp)
cmpl $0, 68(%rsp)
jle .L15
movl $0, %ebx
leaq .LC8(%rip), %r14
.L16:
leaq 512(%rsp), %rcx
movq %rcx, %r9
movq %rbp, %r8
movq %r13, %rdx
movq %r14, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %r13
addq $4, %rbp
cmpl %ebx, 68(%rsp)
jg .L16
.L15:
movl $0x00000000, 144(%rsp)
movl $0x3a83126f, 148(%rsp)
movl $0x3acfbfc6, 152(%rsp)
movl $0x3b24a05e, 156(%rsp)
movl $0x3b82730c, 160(%rsp)
movl $0x3bcec41e, 164(%rsp)
movl $0x3c23d70a, 168(%rsp)
movl $0x3c81d5c3, 172(%rsp)
movl $0x3ccdc65c, 176(%rsp)
movl $0x3d2310dc, 180(%rsp)
movl $0x3d81387a, 184(%rsp)
movl $0x3dcccccd, 188(%rsp)
movl $0x3e224af1, 192(%rsp)
movl $0x3e809bd8, 196(%rsp)
movl $0x3ecbd4ae, 200(%rsp)
movl $0x3f218666, 204(%rsp)
movl $0x3f800000, 208(%rsp)
movl $0x3fcaddc6, 212(%rsp)
movl $0x4020c2bd, 216(%rsp)
movl $0x407ec9e2, 220(%rsp)
movl $0x40c9e806, 224(%rsp)
movl $0x41200000, 228(%rsp)
movl $0x417d953a, 232(%rsp)
movl $0x41c8f36f, 236(%rsp)
movl $0x421f3e2d, 240(%rsp)
movl $0x427c6208, 244(%rsp)
movl $0x42c80000, 248(%rsp)
movl $0, %ebx
leaq .LC37(%rip), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 144(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $27, %rbx
jne .L17
leaq .LC38(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rdi
movl $108, %esi
call cudaMalloc@PLT
movl $27, %edx
movl $0, %esi
movq 112(%rsp), %rdi
call cudaMemset@PLT
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $27, %edx
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1160000, %edi
call malloc@PLT
movq %rax, %rbp
movl $1160000, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movl $1160000, %edx
leaq .LC39(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 104(%rsp), %rdi
movl $1160000, %esi
call cudaMalloc@PLT
movl $1160000, %edx
movl $0, %esi
movq 104(%rsp), %rdi
call cudaMemset@PLT
movl $232, %edi
call malloc@PLT
movq %rax, %rbx
movl $29, %ecx
movl $0, %eax
movq %rbx, %rdi
rep stosq
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $100, 132(%rsp)
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .L18
cmpq $0, 80(%rsp)
je .L18
cmpq $0, 88(%rsp)
je .L18
cmpq $0, 96(%rsp)
je .L18
cmpq $0, 104(%rsp)
je .L18
movq %r12, %rdx
movl $0, %esi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $10000, %esi
movl %ecx, %eax
cltd
idivl %esi
movl %eax, %r14d
cmpl $9999, %ecx
jle .L21
movl $0, %esi
movl $0, %ecx
jmp .L25
.L36:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
leaq .LC40(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L11:
movq 776(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $792, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl $2, %ecx
movl $1160000, %edx
movq 104(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %edx
.L23:
movslq %edx, %rax
imulq $-1925330167, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $4, %eax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $29, %eax, %eax
movl %edx, %ecx
subl %eax, %ecx
movslq %ecx, %rax
movslq 0(%rbp,%rdx,4), %rcx
addq %rcx, (%rbx,%rax,8)
addq $1, %rdx
cmpq $290000, %rdx
jne .L23
addl $1, %r12d
addl $10000, %r13d
cmpl %r12d, %r14d
jle .L38
.L24:
movl $1160000, %edx
movl $0, %esi
movq 104(%rsp), %rdi
call cudaMemset@PLT
movl $100, 120(%rsp)
movl 140(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movq 120(%rsp), %rdi
movl 128(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
pushq 112(%rsp)
.cfi_def_cfa_offset 856
pushq 112(%rsp)
.cfi_def_cfa_offset 864
movl %r15d, %r9d
movl %r13d, %r8d
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z39__device_stub__Z8distancePfS_S_S_iiPiS_PfS_S_S_iiPiS_
addq $16, %rsp
.cfi_def_cfa_offset 848
jmp .L22
.L38:
movl 56(%rsp), %ecx
movl 60(%rsp), %esi
addl $1, %ecx
addl $10000, %esi
cmpl %ecx, %r14d
jle .L21
.L25:
movl %esi, %r15d
movl $0, %r13d
movl $0, %r12d
movl %ecx, 56(%rsp)
movl %esi, 60(%rsp)
jmp .L24
.L21:
leaq .LC41(%rip), %r8
leaq .LC42(%rip), %rcx
leaq .LC43(%rip), %rdx
movl $2, %esi
movq (%rsp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 148(%rsp), %r12
leaq 260(%rsp), %r15
movl $0, %r14d
.L26:
movq (%rbx), %r13
movss -4(%r12), %xmm0
addss (%r12), %xmm0
mulss .LC45(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r13, %r8
leaq .LC44(%rip), %rcx
leaq .LC46(%rip), %rdx
movl $2, %esi
movq (%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq %r13, %r14
addq $8, %rbx
addq $4, %r12
cmpq %r12, %r15
jne .L26
movq %r14, %rdx
leaq .LC47(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movq (%rsp), %rdi
call fclose@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L11
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC48:
.string "_Z8distancePfS_S_S_iiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC48(%rip), %rdx
movq %rdx, %rcx
leaq _Z8distancePfS_S_S_iiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC45:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Calculate_arc_length_two_datasets.hip"
.globl _Z23__device_stub__distancePfS_S_S_iiPiS_ # -- Begin function _Z23__device_stub__distancePfS_S_S_iiPiS_
.p2align 4, 0x90
.type _Z23__device_stub__distancePfS_S_S_iiPiS_,@function
_Z23__device_stub__distancePfS_S_S_iiPiS_: # @_Z23__device_stub__distancePfS_S_S_iiPiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8distancePfS_S_S_iiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z23__device_stub__distancePfS_S_S_iiPiS_, .Lfunc_end0-_Z23__device_stub__distancePfS_S_S_iiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $3, %edi
jle .LBB1_28
# %bb.1:
movq 8(%rbx), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r13
movq 16(%rbx), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, 112(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, 120(%rsp) # 8-byte Spill
leaq 416(%rsp), %rcx
leaq 672(%rsp), %rdx
movl $.L.str.5, %esi
movq %r13, %rdi
movq %rdx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
leaq 12(%rsp), %rdx
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %esi
leal (,%rsi,4), %ebx
movl $.L.str.7, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movslq %ebx, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %rbx, 24(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
leaq 416(%rsp), %rbx
movq 96(%rsp), %r14 # 8-byte Reload
movq 88(%rsp), %r15 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %r13, %rdi
movq %r14, %rdx
movq %rbx, %rcx
movq %r15, %r8
movq %rbx, %r9
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 12(%rsp), %rax
addq $4, %r15
addq $4, %r14
cmpq %rax, %r12
jl .LBB1_3
.LBB1_4: # %._crit_edge
leaq 416(%rsp), %rcx
leaq 672(%rsp), %rdx
movl $.L.str.5, %esi
movq 112(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %rdx, %r8
xorl %eax, %eax
callq __isoc23_fscanf
leaq 12(%rsp), %rdx
movl $.L.str.6, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB1_7
# %bb.5: # %.lr.ph135.preheader
leaq 416(%rsp), %rbx
movq 80(%rsp), %r14 # 8-byte Reload
movq 72(%rsp), %r15 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph135
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %rbp, %rdi
movq %r14, %rdx
movq %rbx, %rcx
movq %r15, %r8
movq %rbx, %r9
xorl %eax, %eax
callq __isoc23_fscanf
incq %r12
movslq 12(%rsp), %rax
addq $4, %r15
addq $4, %r14
cmpq %rax, %r12
jl .LBB1_6
.LBB1_7: # %._crit_edge136
movq %r13, 128(%rsp) # 8-byte Spill
movups .L__const.main.h_bin_edges+92(%rip), %xmm0
movups %xmm0, 396(%rsp)
movaps .L__const.main.h_bin_edges+80(%rip), %xmm0
movaps %xmm0, 384(%rsp)
movaps .L__const.main.h_bin_edges+64(%rip), %xmm0
movaps %xmm0, 368(%rsp)
movaps .L__const.main.h_bin_edges+48(%rip), %xmm0
movaps %xmm0, 352(%rsp)
movaps .L__const.main.h_bin_edges+32(%rip), %xmm0
movaps %xmm0, 336(%rsp)
movaps .L__const.main.h_bin_edges+16(%rip), %xmm0
movaps %xmm0, 320(%rsp)
movaps .L__const.main.h_bin_edges(%rip), %xmm0
movaps %xmm0, 304(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movss 304(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $27, %rbx
jne .LBB1_8
# %bb.9:
movl $10, %edi
callq putchar@PLT
leaq 56(%rsp), %rdi
movl $108, %esi
callq hipMalloc
movq 56(%rsp), %rdi
movl $27, %edx
xorl %esi, %esi
callq hipMemset
movq 56(%rsp), %rdi
leaq 304(%rsp), %rsi
movl $1, %r14d
movl $27, %edx
movl $1, %ecx
callq hipMemcpy
movl $1160000, %edi # imm = 0x11B340
callq malloc
movq %rax, %r13
movl $1160000, %edx # imm = 0x11B340
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $.L.str.12, %edi
movl $1160000, %esi # imm = 0x11B340
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $1160000, %esi # imm = 0x11B340
callq hipMalloc
movq 16(%rsp), %rdi
movl $1160000, %edx # imm = 0x11B340
xorl %esi, %esi
callq hipMemset
movl $232, %edi
callq malloc
movq %rax, %r12
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movups %xmm0, 192(%rax)
movups %xmm0, 208(%rax)
movq $0, 224(%rax)
leaq 64(%rsp), %rdi
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_14
# %bb.10:
cmpq $0, 48(%rsp)
je .LBB1_14
# %bb.11:
cmpq $0, 40(%rsp)
je .LBB1_14
# %bb.12:
cmpq $0, 32(%rsp)
je .LBB1_14
# %bb.13:
cmpq $0, 16(%rsp)
je .LBB1_14
# %bb.15:
xorl %esi, %esi
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
callq hipMemset
movq 48(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 40(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 32(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 64(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %ecx, %ecx
movslq 12(%rsp), %rax
cmpq $10000, %rax # imm = 0x2710
jl .LBB1_24
# %bb.16: # %.lr.ph145
imulq $1759218605, %rax, %r14 # imm = 0x68DB8BAD
movq %r14, %rax
shrq $63, %rax
sarq $44, %r14
addl %eax, %r14d
movabsq $4294967396, %rbp # imm = 0x100000064
movabsq $1908283869694091547, %r15 # imm = 0x1A7B9611A7B9611B
.p2align 4, 0x90
.LBB1_17: # %.lr.ph141.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
# Child Loop BB1_21 Depth 3
movq %rcx, 136(%rsp) # 8-byte Spill
imull $10000, %ecx, %eax # imm = 0x2710
movl %eax, 24(%rsp) # 4-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_18: # %.lr.ph141
# Parent Loop BB1_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_21 Depth 3
movq 16(%rsp), %rdi
movl $1160000, %edx # imm = 0x11B340
xorl %esi, %esi
callq hipMemset
movq %rbp, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19: # in Loop: Header=BB1_18 Depth=2
movq 64(%rsp), %rax
movq %rax, 232(%rsp)
movq 48(%rsp), %rax
movq %rax, 224(%rsp)
movq 40(%rsp), %rax
movq %rax, 216(%rsp)
movq 32(%rsp), %rax
movq %rax, 208(%rsp)
imull $10000, %ebx, %eax # imm = 0x2710
movl %eax, 108(%rsp)
movq 16(%rsp), %rax
movq %rax, 200(%rsp)
movq 56(%rsp), %rax
movq %rax, 192(%rsp)
movl 24(%rsp), %eax # 4-byte Reload
movl %eax, 104(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 108(%rsp), %rax
movq %rax, 272(%rsp)
leaq 104(%rsp), %rax
movq %rax, 280(%rsp)
leaq 200(%rsp), %rax
movq %rax, 288(%rsp)
leaq 192(%rsp), %rax
movq %rax, 296(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z8distancePfS_S_S_iiPiS_, %edi
leaq 240(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20: # in Loop: Header=BB1_18 Depth=2
movq 16(%rsp), %rsi
movl $1160000, %edx # imm = 0x11B340
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rsi
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_21: # Parent Loop BB1_17 Depth=1
# Parent Loop BB1_18 Depth=2
# => This Inner Loop Header: Depth=3
movq %rcx, %rax
mulq %r15
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $4, %rax
imulq $-232, %rax, %rax
movslq (%r13,%rcx,4), %rdx
addq %rdx, (%rsi,%rax)
incq %rcx
addq $8, %rsi
cmpq $290000, %rcx # imm = 0x46CD0
jne .LBB1_21
# %bb.22: # in Loop: Header=BB1_18 Depth=2
incl %ebx
cmpl %r14d, %ebx
jne .LBB1_18
# %bb.23: # %._crit_edge142
# in Loop: Header=BB1_17 Depth=1
movq 136(%rsp), %rcx # 8-byte Reload
incl %ecx
cmpl %r14d, %ecx
jne .LBB1_17
.LBB1_24: # %._crit_edge146
xorl %r14d, %r14d
movl $.L.str.14, %esi
movl $.L.str.15, %edx
movl $.L.str.16, %ecx
movq 120(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
xorl %eax, %eax
callq fprintf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_25: # =>This Inner Loop Header: Depth=1
movss 304(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 308(%rsp,%r14,4), %xmm0
leaq 1(%r14), %r15
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq (%r12,%r14,8), %r14
movl $.L.str.17, %esi
movl $.L.str.18, %edx
movq %rbp, %rdi
movq %r14, %rcx
movb $1, %al
callq fprintf
addq %r14, %rbx
movq %r15, %r14
cmpq $28, %r15
jne .LBB1_25
# %bb.26:
xorl %r14d, %r14d
movl $.L.str.19, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 128(%rsp), %rdi # 8-byte Reload
callq fclose
movq 112(%rsp), %rdi # 8-byte Reload
callq fclose
movq %rbp, %rdi
callq fclose
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
jmp .LBB1_27
.LBB1_14:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_27:
movl %r14d, %eax
addq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_28:
.cfi_def_cfa_offset 992
movl $.Lstr.1, %edi
callq puts@PLT
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8distancePfS_S_S_iiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8distancePfS_S_S_iiPiS_,@object # @_Z8distancePfS_S_S_iiPiS_
.section .rodata,"a",@progbits
.globl _Z8distancePfS_S_S_iiPiS_
.p2align 3, 0x0
_Z8distancePfS_S_S_iiPiS_:
.quad _Z23__device_stub__distancePfS_S_S_iiPiS_
.size _Z8distancePfS_S_S_iiPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nUsage: "
.size .L.str.1, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "w"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s %s %s"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "SIZE0 # particles: %d\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f %s %f %s "
.size .L.str.8, 13
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "SIZE1 # particles: %d\n"
.size .L.str.9, 23
.type .L__const.main.h_bin_edges,@object # @__const.main.h_bin_edges
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.h_bin_edges:
.long 0x00000000 # float 0
.long 0x3a83126f # float 0.00100000005
.long 0x3acfbfc6 # float 0.00158499996
.long 0x3b24a05e # float 0.00251200004
.long 0x3b82730c # float 0.00398099981
.long 0x3bcec41e # float 0.00631000008
.long 0x3c23d70a # float 0.00999999977
.long 0x3c81d5c3 # float 0.0158489998
.long 0x3ccdc65c # float 0.0251189992
.long 0x3d2310dc # float 0.0398110002
.long 0x3d81387a # float 0.0630960017
.long 0x3dcccccd # float 0.100000001
.long 0x3e224af1 # float 0.158489004
.long 0x3e809bd8 # float 0.251188993
.long 0x3ecbd4ae # float 0.398106992
.long 0x3f218666 # float 0.630957007
.long 0x3f800000 # float 1
.long 0x3fcaddc6 # float 1.58489299
.long 0x4020c2bd # float 2.51188588
.long 0x407ec9e2 # float 3.98107195
.long 0x40c9e806 # float 6.30957317
.long 0x41200000 # float 10
.long 0x417d953a # float 15.8489323
.long 0x41c8f36f # float 25.1188641
.long 0x421f3e2d # float 39.8107185
.long 0x427c6208 # float 63.0957336
.long 0x42c80000 # float 100
.size .L__const.main.h_bin_edges, 108
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz "%d %f\n"
.size .L.str.10, 7
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "size_hist: %d\n"
.size .L.str.12, 15
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%s %s\n"
.size .L.str.14, 7
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Angular Distance(radians)"
.size .L.str.15, 26
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Number of Entries"
.size .L.str.16, 18
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%.3e %s %lu \n"
.size .L.str.17, 14
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz ","
.size .L.str.18, 2
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "total: %lu \n"
.size .L.str.19, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8distancePfS_S_S_iiPiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nMust pass in cluster_data file on command line!"
.size .Lstr.1, 50
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " <cluster_data file> <distances file> \n"
.size .Lstr.2, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__distancePfS_S_S_iiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8distancePfS_S_S_iiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_stencil2D_4pt_hack5_cp_rows(double * dst, double * shared_cols, double *shared_rows,int tile_y,int M, int N){
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows begin!\n");
}
#endif
int base_global_row = (tile_y * blockIdx.y );
int base_global_col = blockDim.x*blockIdx.x;
int base_global_idx = N*base_global_row + base_global_col ;
int nextRow = base_global_row+1;
bool legalNextRow = (nextRow<M)?1:0;
int t = threadIdx.x;
bool legalCurCol = (base_global_col + t)<N;
int idx = (base_global_row/tile_y)*2*N + t+base_global_col;
int idx_nextrow = idx + N;
if(legalCurCol){
shared_rows[idx] = dst[base_global_idx + t];
}
if(legalNextRow&&legalCurCol){
shared_rows[idx_nextrow] = dst[base_global_idx + N+t];
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
// if(threadIdx.x==0){
// printf("blockIdx.x = %d,blockIdx.y = %d\n",blockIdx.x,blockIdx.y);
// }
// if(blockIdx.y==1 && threadIdx.x==0){
// printf("addr: %d\n",idx_nextrow);
// }
if(blockIdx.y==0 && blockIdx.x==2 && (t==0 || t==1)){
printf("addr:%d, val = %f\n", idx_nextrow,shared_rows[idx_nextrow]);
}
#endif
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows finish!\n");
}
#endif
} | code for sm_80
Function : _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea20000002600 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x001fc800078e02ff */
/*0060*/ IMAD.IADD R4, R5, 0x1, R0 ; /* 0x0000000105047824 */
/* 0x002fe400078e0200 */
/*0070*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x004fc600078e02ff */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R5, R7, c[0x0][0x180], R5 ; /* 0x0000600007057a24 */
/* 0x000fd800078e0205 */
/*00a0*/ @!P0 IADD3 R3, R5, R0, RZ ; /* 0x0000000005038210 */
/* 0x000fe20007ffe0ff */
/*00b0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff068424 */
/* 0x000fc800078e00ff */
/*00c0*/ @!P0 IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003028625 */
/* 0x000fcc00078e0206 */
/*00d0*/ @!P0 LDG.E.64 R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IABS R11, c[0x0][0x178] ; /* 0x00005e00000b7a13 */
/* 0x000fe20000000000 */
/*00f0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ BSSY B0, 0x360 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0110*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0120*/ I2F.RP R10, R11 ; /* 0x0000000b000a7306 */
/* 0x000e300000209400 */
/*0130*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*0170*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0180*/ IMAD R13, R12, R11, RZ ; /* 0x0000000b0c0d7224 */
/* 0x000fe200078e02ff */
/*0190*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fc80000000000 */
/*01a0*/ IMAD.HI.U32 R9, R9, R13, R8 ; /* 0x0000000d09097227 */
/* 0x000fe200078e0008 */
/*01b0*/ LOP3.LUT R8, R7.reuse, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0007087a12 */
/* 0x040fe400078e3cff */
/*01c0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f46270 */
/*01e0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a09 */
/*0200*/ IMAD R10, R11, R10, R12 ; /* 0x0000000a0b0a7224 */
/* 0x000fca00078e020c */
/*0210*/ ISETP.GT.U32.AND P3, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f64070 */
/*0220*/ @!P3 IADD3 R10, R10, -R11.reuse, RZ ; /* 0x8000000b0a0ab210 */
/* 0x080fe40007ffe0ff */
/*0230*/ @!P3 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909b810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P1, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe40003f26070 */
/*0250*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fd60003f65270 */
/*0260*/ @P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109091810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GE.OR P1, PT, R7, c[0x0][0x17c], P0 ; /* 0x00005f0007007a0c */
/* 0x000fc60000726670 */
/*0280*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0290*/ @!P3 LOP3.LUT R9, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff09ba12 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD R9, R9, UR4, R4 ; /* 0x0000000409097c24 */
/* 0x000fc8000f8e0204 */
/*02b0*/ @!P0 IMAD.WIDE R6, R9, R6, c[0x0][0x170] ; /* 0x00005c0009068625 */
/* 0x000fca00078e0206 */
/*02c0*/ @!P0 STG.E.64 [R6.64], R2 ; /* 0x0000000206008986 */
/* 0x0041e2000c101b06 */
/*02d0*/ @P1 BRA 0x350 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R2, R5, c[0x0][0x180], R0 ; /* 0x0000600005027a10 */
/* 0x001fe40007ffe000 */
/*02f0*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0310*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0320*/ IADD3 R4, R9, c[0x0][0x180], RZ ; /* 0x0000600009047a10 */
/* 0x000fca0007ffe0ff */
/*0330*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0340*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0041e4000c101b06 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_stencil2D_4pt_hack5_cp_rows(double * dst, double * shared_cols, double *shared_rows,int tile_y,int M, int N){
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows begin!\n");
}
#endif
int base_global_row = (tile_y * blockIdx.y );
int base_global_col = blockDim.x*blockIdx.x;
int base_global_idx = N*base_global_row + base_global_col ;
int nextRow = base_global_row+1;
bool legalNextRow = (nextRow<M)?1:0;
int t = threadIdx.x;
bool legalCurCol = (base_global_col + t)<N;
int idx = (base_global_row/tile_y)*2*N + t+base_global_col;
int idx_nextrow = idx + N;
if(legalCurCol){
shared_rows[idx] = dst[base_global_idx + t];
}
if(legalNextRow&&legalCurCol){
shared_rows[idx_nextrow] = dst[base_global_idx + N+t];
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
// if(threadIdx.x==0){
// printf("blockIdx.x = %d,blockIdx.y = %d\n",blockIdx.x,blockIdx.y);
// }
// if(blockIdx.y==1 && threadIdx.x==0){
// printf("addr: %d\n",idx_nextrow);
// }
if(blockIdx.y==0 && blockIdx.x==2 && (t==0 || t==1)){
printf("addr:%d, val = %f\n", idx_nextrow,shared_rows[idx_nextrow]);
}
#endif
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows finish!\n");
}
#endif
} | .file "tmpxft_00009775_00000000-6_gpu_stencil2D_4pt_hack5_cp_rows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii
.type _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii, @function
_Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii, .-_Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii
.globl _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.type _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, @function
_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, .-_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_stencil2D_4pt_hack5_cp_rows(double * dst, double * shared_cols, double *shared_rows,int tile_y,int M, int N){
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows begin!\n");
}
#endif
int base_global_row = (tile_y * blockIdx.y );
int base_global_col = blockDim.x*blockIdx.x;
int base_global_idx = N*base_global_row + base_global_col ;
int nextRow = base_global_row+1;
bool legalNextRow = (nextRow<M)?1:0;
int t = threadIdx.x;
bool legalCurCol = (base_global_col + t)<N;
int idx = (base_global_row/tile_y)*2*N + t+base_global_col;
int idx_nextrow = idx + N;
if(legalCurCol){
shared_rows[idx] = dst[base_global_idx + t];
}
if(legalNextRow&&legalCurCol){
shared_rows[idx_nextrow] = dst[base_global_idx + N+t];
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
// if(threadIdx.x==0){
// printf("blockIdx.x = %d,blockIdx.y = %d\n",blockIdx.x,blockIdx.y);
// }
// if(blockIdx.y==1 && threadIdx.x==0){
// printf("addr: %d\n",idx_nextrow);
// }
if(blockIdx.y==0 && blockIdx.x==2 && (t==0 || t==1)){
printf("addr:%d, val = %f\n", idx_nextrow,shared_rows[idx_nextrow]);
}
#endif
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows finish!\n");
}
#endif
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil2D_4pt_hack5_cp_rows(double * dst, double * shared_cols, double *shared_rows,int tile_y,int M, int N){
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows begin!\n");
}
#endif
int base_global_row = (tile_y * blockIdx.y );
int base_global_col = blockDim.x*blockIdx.x;
int base_global_idx = N*base_global_row + base_global_col ;
int nextRow = base_global_row+1;
bool legalNextRow = (nextRow<M)?1:0;
int t = threadIdx.x;
bool legalCurCol = (base_global_col + t)<N;
int idx = (base_global_row/tile_y)*2*N + t+base_global_col;
int idx_nextrow = idx + N;
if(legalCurCol){
shared_rows[idx] = dst[base_global_idx + t];
}
if(legalNextRow&&legalCurCol){
shared_rows[idx_nextrow] = dst[base_global_idx + N+t];
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
// if(threadIdx.x==0){
// printf("blockIdx.x = %d,blockIdx.y = %d\n",blockIdx.x,blockIdx.y);
// }
// if(blockIdx.y==1 && threadIdx.x==0){
// printf("addr: %d\n",idx_nextrow);
// }
if(blockIdx.y==0 && blockIdx.x==2 && (t==0 || t==1)){
printf("addr:%d, val = %f\n", idx_nextrow,shared_rows[idx_nextrow]);
}
#endif
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows finish!\n");
}
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil2D_4pt_hack5_cp_rows(double * dst, double * shared_cols, double *shared_rows,int tile_y,int M, int N){
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows begin!\n");
}
#endif
int base_global_row = (tile_y * blockIdx.y );
int base_global_col = blockDim.x*blockIdx.x;
int base_global_idx = N*base_global_row + base_global_col ;
int nextRow = base_global_row+1;
bool legalNextRow = (nextRow<M)?1:0;
int t = threadIdx.x;
bool legalCurCol = (base_global_col + t)<N;
int idx = (base_global_row/tile_y)*2*N + t+base_global_col;
int idx_nextrow = idx + N;
if(legalCurCol){
shared_rows[idx] = dst[base_global_idx + t];
}
if(legalNextRow&&legalCurCol){
shared_rows[idx_nextrow] = dst[base_global_idx + N+t];
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
// if(threadIdx.x==0){
// printf("blockIdx.x = %d,blockIdx.y = %d\n",blockIdx.x,blockIdx.y);
// }
// if(blockIdx.y==1 && threadIdx.x==0){
// printf("addr: %d\n",idx_nextrow);
// }
if(blockIdx.y==0 && blockIdx.x==2 && (t==0 || t==1)){
printf("addr:%d, val = %f\n", idx_nextrow,shared_rows[idx_nextrow]);
}
#endif
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows finish!\n");
}
#endif
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.globl _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.p2align 8
.type _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii,@function
_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s10, s2, 31
s_mul_i32 s9, s15, s2
s_add_i32 s4, s2, s10
s_and_b32 s8, s8, 0xffff
s_xor_b32 s11, s4, s10
s_mul_i32 s2, s14, s8
v_cvt_f32_u32_e32 v1, s11
s_sub_i32 s8, 0, s11
s_ashr_i32 s13, s9, 31
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_add_i32 s14, s9, s13
v_rcp_iflag_f32_e32 v1, v1
s_xor_b32 s14, s14, s13
s_xor_b32 s10, s13, s10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s12, v1
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s8, s8, s12
v_cmp_le_i32_e32 vcc_lo, s3, v1
s_mul_hi_u32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, s8
s_mul_i32 s8, s9, s3
s_mul_hi_u32 s12, s14, s12
s_add_i32 s8, s2, s8
s_mul_i32 s15, s12, s11
s_sub_i32 s13, s14, s15
s_add_i32 s14, s12, 1
s_sub_i32 s15, s13, s11
s_cmp_ge_u32 s13, s11
s_cselect_b32 s12, s14, s12
s_cselect_b32 s13, s15, s13
s_add_i32 s14, s12, 1
s_cmp_ge_u32 s13, s11
s_cselect_b32 s2, s14, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s10
s_sub_i32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_mul_i32 s10, s3, s2
v_cmp_gt_i32_e64 s2, s3, v1
v_lshl_add_u32 v1, s10, 1, v1
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s2, s6, v2
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
global_load_b64 v[3:4], v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_co_u32 v5, s2, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s5, v6, s2
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
s_load_b32 s0, s[0:1], 0x1c
s_add_i32 s9, s9, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, s0
s_cselect_b32 s0, -1, 0
s_xor_b32 s1, vcc_lo, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_add3_u32 v2, s3, s8, v0
v_add_nc_u32_e32 v0, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, .Lfunc_end0-_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil2D_4pt_hack5_cp_rows(double * dst, double * shared_cols, double *shared_rows,int tile_y,int M, int N){
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows begin!\n");
}
#endif
int base_global_row = (tile_y * blockIdx.y );
int base_global_col = blockDim.x*blockIdx.x;
int base_global_idx = N*base_global_row + base_global_col ;
int nextRow = base_global_row+1;
bool legalNextRow = (nextRow<M)?1:0;
int t = threadIdx.x;
bool legalCurCol = (base_global_col + t)<N;
int idx = (base_global_row/tile_y)*2*N + t+base_global_col;
int idx_nextrow = idx + N;
if(legalCurCol){
shared_rows[idx] = dst[base_global_idx + t];
}
if(legalNextRow&&legalCurCol){
shared_rows[idx_nextrow] = dst[base_global_idx + N+t];
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
// if(threadIdx.x==0){
// printf("blockIdx.x = %d,blockIdx.y = %d\n",blockIdx.x,blockIdx.y);
// }
// if(blockIdx.y==1 && threadIdx.x==0){
// printf("addr: %d\n",idx_nextrow);
// }
if(blockIdx.y==0 && blockIdx.x==2 && (t==0 || t==1)){
printf("addr:%d, val = %f\n", idx_nextrow,shared_rows[idx_nextrow]);
}
#endif
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(threadIdx.x==0)){
printf("copy rows finish!\n");
}
#endif
} | .text
.file "gpu_stencil2D_4pt_hack5_cp_rows.hip"
.globl _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii # -- Begin function _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.p2align 4, 0x90
.type _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii,@function
_Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii: # @_Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, .Lfunc_end0-_Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii,@object # @_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.p2align 3, 0x0
_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii:
.quad _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.size _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea20000002600 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x001fc800078e02ff */
/*0060*/ IMAD.IADD R4, R5, 0x1, R0 ; /* 0x0000000105047824 */
/* 0x002fe400078e0200 */
/*0070*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x004fc600078e02ff */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R5, R7, c[0x0][0x180], R5 ; /* 0x0000600007057a24 */
/* 0x000fd800078e0205 */
/*00a0*/ @!P0 IADD3 R3, R5, R0, RZ ; /* 0x0000000005038210 */
/* 0x000fe20007ffe0ff */
/*00b0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff068424 */
/* 0x000fc800078e00ff */
/*00c0*/ @!P0 IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003028625 */
/* 0x000fcc00078e0206 */
/*00d0*/ @!P0 LDG.E.64 R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IABS R11, c[0x0][0x178] ; /* 0x00005e00000b7a13 */
/* 0x000fe20000000000 */
/*00f0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ BSSY B0, 0x360 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0110*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0120*/ I2F.RP R10, R11 ; /* 0x0000000b000a7306 */
/* 0x000e300000209400 */
/*0130*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*0170*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0180*/ IMAD R13, R12, R11, RZ ; /* 0x0000000b0c0d7224 */
/* 0x000fe200078e02ff */
/*0190*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fc80000000000 */
/*01a0*/ IMAD.HI.U32 R9, R9, R13, R8 ; /* 0x0000000d09097227 */
/* 0x000fe200078e0008 */
/*01b0*/ LOP3.LUT R8, R7.reuse, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0007087a12 */
/* 0x040fe400078e3cff */
/*01c0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f46270 */
/*01e0*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a09 */
/*0200*/ IMAD R10, R11, R10, R12 ; /* 0x0000000a0b0a7224 */
/* 0x000fca00078e020c */
/*0210*/ ISETP.GT.U32.AND P3, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f64070 */
/*0220*/ @!P3 IADD3 R10, R10, -R11.reuse, RZ ; /* 0x8000000b0a0ab210 */
/* 0x080fe40007ffe0ff */
/*0230*/ @!P3 IADD3 R9, R9, 0x1, RZ ; /* 0x000000010909b810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P1, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe40003f26070 */
/*0250*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fd60003f65270 */
/*0260*/ @P1 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109091810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GE.OR P1, PT, R7, c[0x0][0x17c], P0 ; /* 0x00005f0007007a0c */
/* 0x000fc60000726670 */
/*0280*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0290*/ @!P3 LOP3.LUT R9, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff09ba12 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD R9, R9, UR4, R4 ; /* 0x0000000409097c24 */
/* 0x000fc8000f8e0204 */
/*02b0*/ @!P0 IMAD.WIDE R6, R9, R6, c[0x0][0x170] ; /* 0x00005c0009068625 */
/* 0x000fca00078e0206 */
/*02c0*/ @!P0 STG.E.64 [R6.64], R2 ; /* 0x0000000206008986 */
/* 0x0041e2000c101b06 */
/*02d0*/ @P1 BRA 0x350 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R2, R5, c[0x0][0x180], R0 ; /* 0x0000600005027a10 */
/* 0x001fe40007ffe000 */
/*02f0*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0310*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*0320*/ IADD3 R4, R9, c[0x0][0x180], RZ ; /* 0x0000600009047a10 */
/* 0x000fca0007ffe0ff */
/*0330*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0340*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0041e4000c101b06 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.globl _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.p2align 8
.type _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii,@function
_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s10, s2, 31
s_mul_i32 s9, s15, s2
s_add_i32 s4, s2, s10
s_and_b32 s8, s8, 0xffff
s_xor_b32 s11, s4, s10
s_mul_i32 s2, s14, s8
v_cvt_f32_u32_e32 v1, s11
s_sub_i32 s8, 0, s11
s_ashr_i32 s13, s9, 31
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_add_i32 s14, s9, s13
v_rcp_iflag_f32_e32 v1, v1
s_xor_b32 s14, s14, s13
s_xor_b32 s10, s13, s10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s12, v1
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s8, s8, s12
v_cmp_le_i32_e32 vcc_lo, s3, v1
s_mul_hi_u32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, s8
s_mul_i32 s8, s9, s3
s_mul_hi_u32 s12, s14, s12
s_add_i32 s8, s2, s8
s_mul_i32 s15, s12, s11
s_sub_i32 s13, s14, s15
s_add_i32 s14, s12, 1
s_sub_i32 s15, s13, s11
s_cmp_ge_u32 s13, s11
s_cselect_b32 s12, s14, s12
s_cselect_b32 s13, s15, s13
s_add_i32 s14, s12, 1
s_cmp_ge_u32 s13, s11
s_cselect_b32 s2, s14, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s10
s_sub_i32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_mul_i32 s10, s3, s2
v_cmp_gt_i32_e64 s2, s3, v1
v_lshl_add_u32 v1, s10, 1, v1
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s2, s6, v2
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
global_load_b64 v[3:4], v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_co_u32 v5, s2, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s5, v6, s2
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
s_load_b32 s0, s[0:1], 0x1c
s_add_i32 s9, s9, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, s0
s_cselect_b32 s0, -1, 0
s_xor_b32 s1, vcc_lo, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_add3_u32 v2, s3, s8, v0
v_add_nc_u32_e32 v0, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, .Lfunc_end0-_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00009775_00000000-6_gpu_stencil2D_4pt_hack5_cp_rows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii
.type _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii, @function
_Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii, .-_Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii
.globl _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.type _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, @function
_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, .-_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_stencil2D_4pt_hack5_cp_rows.hip"
.globl _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii # -- Begin function _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.p2align 4, 0x90
.type _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii,@function
_Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii: # @_Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, .Lfunc_end0-_Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii,@object # @_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.p2align 3, 0x0
_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii:
.quad _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.size _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31gpu_stencil2D_4pt_hack5_cp_rowsPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
int XDIM;
int YDIM;
/*
* NXN Matrix Multiplication
*/
__global__ void
matMult(const int *A, const int *B, int *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
for(int j = 0; j < numElements; j++){
int idx = (i*numElements)+j;
for(int k = 0; k < numElements; k++){
C[idx] += A[(i*numElements)+k] * B[(k*numElements)+j];
}
}
//printf("---→test: %d", i);
}
}
void printMat(int * M, int XDIM){
int i;
int j;
for(i = 0; i < XDIM; i++){
for(j = 0; j < XDIM; j++){
printf(" %d ", M[i*XDIM+j]);
}
printf("\n");
}
}
int main(int argc, char **argv){
XDIM = 40;
YDIM = 40;
if(argc > 1){
XDIM = atoi(argv[1]);
YDIM = XDIM;
}
//STEP 1 : Allocate in host
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the mat size to be used, and compute its size
size_t size = sizeof(int*)*YDIM*XDIM;
//printf("[Mat multiplication of %d elements]\n", YDIM);
// Allocate the host input vector A
int * h_A = (int *)malloc(size);
// Allocate the host input vector B
int * h_B = (int *)malloc(size);
// Allocate the host output vector C
int * h_C = (int *)malloc(size);
// Initialize h_A and h_B with random numbers, h_C with 0's
for(int i = 0; i < XDIM*XDIM; i++){
h_A[i] = rand() & 0xF;
h_B[i] = rand() & 0xF;
h_C[i] = 0;
}
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
//STEP 2: ALLOCATE IN CUDA
// Allocate device memory
int *d_A = NULL;
int *d_B = NULL;
int *d_C = NULL;
cudaError_t error;
error = cudaMalloc((void **) &d_A, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_A returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **) &d_B, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_B returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **) &d_C, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_C returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// copy host memory to device
error = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_A,h_A) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// Launch the Mat mult CUDA Kernel
int threadsPerBlock = 1024;
int blocksPerGrid =(XDIM + threadsPerBlock - 1) / threadsPerBlock;
//printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
matMult<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, XDIM);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
//printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free device global memory
err = cudaFree(d_A);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_B);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_C);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
//printMat(h_A,XDIM);
//printMat(h_B,XDIM);
//printMat(h_C,XDIM);
free(h_A);
free(h_B);
free(h_C);
// Reset the device and exit
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//printf("Done\n");
return 0;
} | code for sm_80
Function : _Z7matMultPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R13, c[0x0][0x178] ; /* 0x00005e00000d7a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x178], !P0 ; /* 0x00005e000b007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0090*/ IADD3 R0, R13, -0x1, RZ ; /* 0xffffffff0d007810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD R11, R11, c[0x0][0x178], RZ ; /* 0x00005e000b0b7a24 */
/* 0x000fe200078e02ff */
/*00b0*/ LOP3.LUT R16, R13.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d107812 */
/* 0x040fe200078ec0ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*00e0*/ SHF.L.U32 R13, R13, 0x2, RZ ; /* 0x000000020d0d7819 */
/* 0x000fe400000006ff */
/*00f0*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fe200078e0202 */
/*0110*/ IADD3 R12, -R16, c[0x0][0x178], RZ ; /* 0x00005e00100c7a10 */
/* 0x000fc60007ffe1ff */
/*0120*/ IADD3 R7, R11, R15, RZ ; /* 0x0000000f0b077210 */
/* 0x003fe40007ffe0ff */
/*0130*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc60000000f00 */
/*0150*/ IMAD.WIDE R6, R7, R14, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e020e */
/*0160*/ @!P1 BRA 0xd10 ; /* 0x00000ba000009947 */
/* 0x020fea0003800000 */
/*0170*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f04270 */
/*0180*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000162000c1e1900 */
/*0190*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*01a0*/ IADD3 R17, R15, c[0x0][0x178], RZ ; /* 0x00005e000f117a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ MOV R0, R12 ; /* 0x0000000c00007202 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc40000000f00 */
/*01e0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0200*/ @!P0 BRA 0xb50 ; /* 0x0000094000008947 */
/* 0x001fea0003800000 */
/*0210*/ ISETP.GT.AND P2, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f44270 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0230*/ @!P2 BRA 0x800 ; /* 0x000005c00000a947 */
/* 0x000fea0003800000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fe200078e0204 */
/*0260*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000eaa000c1e1900 */
/*0270*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD R25, R18, R20, R21 ; /* 0x0000001412197224 */
/* 0x025fe400078e0215 */
/*0290*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*02a0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x004fc400078e0219 */
/*02e0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*02f0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc800078e0216 */
/*0330*/ IMAD R29, R24, R26, R27 ; /* 0x0000001a181d7224 */
/* 0x004fca00078e021b */
/*0340*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0350*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e28000c1e1900 */
/*0360*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x000e22000c1e1900 */
/*0370*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*0380*/ IMAD.WIDE R20, R15, 0x4, R4 ; /* 0x000000040f147825 */
/* 0x000fc800078e0204 */
/*0390*/ IMAD R25, R18, R24, R29 ; /* 0x0000001812197224 */
/* 0x001fca00078e021d */
/*03a0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e68000c1e1900 */
/*03c0*/ LDG.E R22, [R8.64+0x10] ; /* 0x0000100408167981 */
/* 0x000e64000c1e1900 */
/*03d0*/ IMAD R27, R20, R22, R25 ; /* 0x00000016141b7224 */
/* 0x002fc400078e0219 */
/*03e0*/ IMAD.WIDE R22, R17, 0x4, R4 ; /* 0x0000000411167825 */
/* 0x000fc600078e0204 */
/*03f0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0400*/ LDG.E R19, [R8.64+0x14] ; /* 0x0000140408137981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea4000c1e1900 */
/*0420*/ IMAD R29, R18, R19, R27 ; /* 0x00000013121d7224 */
/* 0x004fc400078e021b */
/*0430*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc600078e0216 */
/*0440*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0450*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000e28000c1e1900 */
/*0460*/ LDG.E R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000e24000c1e1900 */
/*0470*/ IMAD R25, R24, R20, R29 ; /* 0x0000001418197224 */
/* 0x001fc400078e021d */
/*0480*/ IMAD.WIDE R20, R14, c[0x0][0x178], R18 ; /* 0x00005e000e147a25 */
/* 0x000fc600078e0212 */
/*0490*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e68000c1e1900 */
/*04b0*/ LDG.E R24, [R8.64+0x1c] ; /* 0x00001c0408187981 */
/* 0x000e62000c1e1900 */
/*04c0*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*04d0*/ IMAD.WIDE R22, R15, 0x4, R4 ; /* 0x000000040f167825 */
/* 0x000fc800078e0204 */
/*04e0*/ IMAD R27, R20, R24, R25 ; /* 0x00000018141b7224 */
/* 0x002fca00078e0219 */
/*04f0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0500*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R18, [R8.64+0x20] ; /* 0x0000200408127981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IMAD R29, R22, R18, R27 ; /* 0x00000012161d7224 */
/* 0x004fc400078e021b */
/*0530*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0540*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0550*/ LDG.E R21, [R8.64+0x24] ; /* 0x0000240408157981 */
/* 0x000e28000c1e1900 */
/*0560*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e24000c1e1900 */
/*0570*/ IMAD R25, R20, R21, R29 ; /* 0x0000001514197224 */
/* 0x001fc400078e021d */
/*0580*/ IMAD.WIDE R20, R14, c[0x0][0x178], R18 ; /* 0x00005e000e147a25 */
/* 0x000fc600078e0212 */
/*0590*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000e68000c1e1900 */
/*05b0*/ LDG.E R22, [R8.64+0x28] ; /* 0x0000280408167981 */
/* 0x000e64000c1e1900 */
/*05c0*/ IMAD R27, R24, R22, R25 ; /* 0x00000016181b7224 */
/* 0x002fc400078e0219 */
/*05d0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*05e0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*05f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R24, [R8.64+0x2c] ; /* 0x00002c0408187981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*0620*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fc800078e0204 */
/*0630*/ IMAD R29, R22, R24, R27 ; /* 0x00000018161d7224 */
/* 0x004fca00078e021b */
/*0640*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R20, [R8.64+0x30] ; /* 0x0000300408147981 */
/* 0x000e24000c1e1900 */
/*0670*/ IMAD R25, R18, R20, R29 ; /* 0x0000001412197224 */
/* 0x001fc400078e021d */
/*0680*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*0690*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*06a0*/ LDG.E R23, [R8.64+0x34] ; /* 0x0000340408177981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000e64000c1e1900 */
/*06c0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x002fc400078e0219 */
/*06d0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*06e0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0001e8000c101904 */
/*06f0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R18, [R8.64+0x38] ; /* 0x0000380408127981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD R29, R24, R18, R27 ; /* 0x00000012181d7224 */
/* 0x004fc400078e021b */
/*0730*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc600078e0216 */
/*0740*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0001e8000c101904 */
/*0750*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R24, [R8.64+0x3c] ; /* 0x00003c0408187981 */
/* 0x0002a2000c1e1900 */
/*0770*/ ISETP.GT.AND P2, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f44270 */
/*0780*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*0790*/ IADD3 R20, P3, R8, 0x40, RZ ; /* 0x0000004008147810 */
/* 0x000fc40007f7e0ff */
/*07a0*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ IADD3.X R9, RZ, R9, RZ, P3, !PT ; /* 0x00000009ff097210 */
/* 0x002fe40001ffe4ff */
/*07c0*/ MOV R8, R20 ; /* 0x0000001400087202 */
/* 0x000fe20000000f00 */
/*07d0*/ IMAD R21, R18, R24, R29 ; /* 0x0000001812157224 */
/* 0x004fca00078e021d */
/*07e0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001e2000c101904 */
/*07f0*/ @P2 BRA 0x250 ; /* 0xfffffa5000002947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.GT.AND P2, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f44270 */
/*0810*/ @!P2 BRA 0xb30 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fe200078e0204 */
/*0830*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000eaa000c1e1900 */
/*0840*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0850*/ IMAD R25, R18, R20, R21 ; /* 0x0000001412197224 */
/* 0x025fe400078e0215 */
/*0860*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*0870*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*0880*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x004fc400078e0219 */
/*08b0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*08c0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*08d0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc800078e0216 */
/*0900*/ IMAD R29, R24, R26, R27 ; /* 0x0000001a181d7224 */
/* 0x004fca00078e021b */
/*0910*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0920*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e28000c1e1900 */
/*0930*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x000e22000c1e1900 */
/*0940*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*0950*/ IMAD.WIDE R20, R15, 0x4, R4 ; /* 0x000000040f147825 */
/* 0x000fc800078e0204 */
/*0960*/ IMAD R25, R18, R24, R29 ; /* 0x0000001812197224 */
/* 0x001fca00078e021d */
/*0970*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*0980*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e68000c1e1900 */
/*0990*/ LDG.E R22, [R8.64+0x10] ; /* 0x0000100408167981 */
/* 0x000e64000c1e1900 */
/*09a0*/ IMAD R27, R20, R22, R25 ; /* 0x00000016141b7224 */
/* 0x002fc400078e0219 */
/*09b0*/ IMAD.WIDE R22, R17, 0x4, R4 ; /* 0x0000000411167825 */
/* 0x000fc600078e0204 */
/*09c0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R19, [R8.64+0x14] ; /* 0x0000140408137981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD R29, R18, R19, R27 ; /* 0x00000013121d7224 */
/* 0x004fc400078e021b */
/*0a00*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc600078e0216 */
/*0a10*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000ea4000c1e1900 */
/*0a40*/ IMAD R20, R24, R20, R29 ; /* 0x0000001418147224 */
/* 0x004fc400078e021d */
/*0a50*/ IMAD.WIDE R24, R14, c[0x0][0x178], R18 ; /* 0x00005e000e187a25 */
/* 0x001fc600078e0212 */
/*0a60*/ STG.E [R6.64], R20 ; /* 0x0000001406007986 */
/* 0x0003e8000c101904 */
/*0a70*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0a80*/ LDG.E R21, [R8.64+0x1c] ; /* 0x00001c0408157981 */
/* 0x0000a2000c1e1900 */
/*0a90*/ IADD3 R22, P2, R8, 0x20, RZ ; /* 0x0000002008167810 */
/* 0x000fe20007f5e0ff */
/*0aa0*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*0ab0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0ac0*/ IADD3.X R23, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff177210 */
/* 0x000fe400017fe4ff */
/*0ad0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe40007ffe0ff */
/*0af0*/ MOV R8, R22 ; /* 0x0000001600087202 */
/* 0x001fe40000000f00 */
/*0b00*/ MOV R9, R23 ; /* 0x0000001700097202 */
/* 0x000fe20000000f00 */
/*0b10*/ IMAD R21, R25, R21, R20 ; /* 0x0000001519157224 */
/* 0x004fca00078e0214 */
/*0b20*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0003e4000c101904 */
/*0b30*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0b40*/ @!P0 BRA 0xd10 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fe200078e0204 */
/*0b60*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x002eaa000c1e1900 */
/*0b70*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD R25, R18, R20, R21 ; /* 0x0000001412197224 */
/* 0x025fe400078e0215 */
/*0b90*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*0ba0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea4000c1e1900 */
/*0bd0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x004fc400078e0219 */
/*0be0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*0bf0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0001e8000c101904 */
/*0c00*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*0c10*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000ea2000c1e1900 */
/*0c20*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fe200078e0216 */
/*0c30*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc60007ffe0ff */
/*0c40*/ IMAD R29, R24, R26, R27 ; /* 0x0000001a181d7224 */
/* 0x004fca00078e021b */
/*0c50*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0001e8000c101904 */
/*0c60*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*0c70*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x0002a2000c1e1900 */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*0ca0*/ IADD3 R20, P2, R8, 0x10, RZ ; /* 0x0000001008147810 */
/* 0x000fc40007f5e0ff */
/*0cb0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x002fe400017fe4ff */
/*0cd0*/ MOV R8, R20 ; /* 0x0000001400087202 */
/* 0x000fe20000000f00 */
/*0ce0*/ IMAD R21, R18, R24, R29 ; /* 0x0000001812157224 */
/* 0x004fca00078e021d */
/*0cf0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001e4000c101904 */
/*0d00*/ @P0 BRA 0xb50 ; /* 0xfffffe4000000947 */
/* 0x001fea000383ffff */
/*0d10*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fda0003f05270 */
/*0d20*/ @!P0 BRA 0xec0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0d30*/ IADD3 R5, R11, R10, RZ ; /* 0x0000000a0b057210 */
/* 0x000fe20007ffe0ff */
/*0d40*/ IMAD R19, R10, c[0x0][0x178], R15 ; /* 0x00005e000a137a24 */
/* 0x000fe200078e020f */
/*0d50*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea6000c1e1900 */
/*0d60*/ IMAD.WIDE R8, R19, R14, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x000fc800078e020e */
/*0d70*/ IMAD.WIDE R4, R5, R14, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e020e */
/*0d80*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0d90*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0da0*/ ISETP.NE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f05270 */
/*0db0*/ IMAD R21, R8, R17, R0 ; /* 0x0000001108157224 */
/* 0x027fca00078e0200 */
/*0dc0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001ee000c101904 */
/*0dd0*/ @!P0 BRA 0xec0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0de0*/ IADD3 R19, R19, c[0x0][0x178], RZ ; /* 0x00005e0013137a10 */
/* 0x000fe20007ffe0ff */
/*0df0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea8000c1e1900 */
/*0e00*/ IMAD.WIDE R8, R19, R14, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x000fcc00078e020e */
/*0e10*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0e20*/ ISETP.NE.AND P0, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe20003f05270 */
/*0e30*/ IMAD R17, R8, R17, R21 ; /* 0x0000001108117224 */
/* 0x004fca00078e0215 */
/*0e40*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003ee000c101904 */
/*0e50*/ @!P0 BRA 0xec0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0e60*/ IADD3 R9, R19, c[0x0][0x178], RZ ; /* 0x00005e0013097a10 */
/* 0x000fe20007ffe0ff */
/*0e70*/ LDG.E R5, [R4.64+0x8] ; /* 0x0000080404057981 */
/* 0x000ea8000c1e1900 */
/*0e80*/ IMAD.WIDE R8, R9, R14, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fcc00078e020e */
/*0e90*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*0ea0*/ IMAD R17, R8, R5, R17 ; /* 0x0000000508117224 */
/* 0x006fca00078e0211 */
/*0eb0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003e4000c101904 */
/*0ec0*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*0ed0*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fda0003f06270 */
/*0ee0*/ @!P0 BRA 0x120 ; /* 0xfffff23000008947 */
/* 0x000fea000383ffff */
/*0ef0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f00*/ BRA 0xf00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
int XDIM;
int YDIM;
/*
* NXN Matrix Multiplication
*/
__global__ void
matMult(const int *A, const int *B, int *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
for(int j = 0; j < numElements; j++){
int idx = (i*numElements)+j;
for(int k = 0; k < numElements; k++){
C[idx] += A[(i*numElements)+k] * B[(k*numElements)+j];
}
}
//printf("---→test: %d", i);
}
}
void printMat(int * M, int XDIM){
int i;
int j;
for(i = 0; i < XDIM; i++){
for(j = 0; j < XDIM; j++){
printf(" %d ", M[i*XDIM+j]);
}
printf("\n");
}
}
int main(int argc, char **argv){
XDIM = 40;
YDIM = 40;
if(argc > 1){
XDIM = atoi(argv[1]);
YDIM = XDIM;
}
//STEP 1 : Allocate in host
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the mat size to be used, and compute its size
size_t size = sizeof(int*)*YDIM*XDIM;
//printf("[Mat multiplication of %d elements]\n", YDIM);
// Allocate the host input vector A
int * h_A = (int *)malloc(size);
// Allocate the host input vector B
int * h_B = (int *)malloc(size);
// Allocate the host output vector C
int * h_C = (int *)malloc(size);
// Initialize h_A and h_B with random numbers, h_C with 0's
for(int i = 0; i < XDIM*XDIM; i++){
h_A[i] = rand() & 0xF;
h_B[i] = rand() & 0xF;
h_C[i] = 0;
}
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
//STEP 2: ALLOCATE IN CUDA
// Allocate device memory
int *d_A = NULL;
int *d_B = NULL;
int *d_C = NULL;
cudaError_t error;
error = cudaMalloc((void **) &d_A, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_A returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **) &d_B, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_B returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **) &d_C, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_C returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// copy host memory to device
error = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_A,h_A) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// Launch the Mat mult CUDA Kernel
int threadsPerBlock = 1024;
int blocksPerGrid =(XDIM + threadsPerBlock - 1) / threadsPerBlock;
//printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
matMult<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, XDIM);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
//printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free device global memory
err = cudaFree(d_A);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_B);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_C);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
//printMat(h_A,XDIM);
//printMat(h_B,XDIM);
//printMat(h_C,XDIM);
free(h_A);
free(h_B);
free(h_C);
// Reset the device and exit
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//printf("Done\n");
return 0;
} | .file "tmpxft_0015f56a_00000000-6_p2-matrixMult_gpu-threads.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %d "
.LC1:
.string "\n"
.text
.globl _Z8printMatPii
.type _Z8printMatPii, @function
_Z8printMatPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8printMatPii, .-_Z8printMatPii
.globl _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
.type _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii, @function
_Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7matMultPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii, .-_Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
.globl _Z7matMultPKiS0_Pii
.type _Z7matMultPKiS0_Pii, @function
_Z7matMultPKiS0_Pii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7matMultPKiS0_Pii, .-_Z7matMultPKiS0_Pii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Failed to allocate host vectors!\n"
.align 8
.LC3:
.string "cudaMalloc d_A returned error code %d, line(%d)\n"
.align 8
.LC4:
.string "cudaMalloc d_B returned error code %d, line(%d)\n"
.align 8
.LC5:
.string "cudaMalloc d_C returned error code %d, line(%d)\n"
.align 8
.LC6:
.string "cudaMemcpy (d_A,h_A) returned error code %d, line(%d)\n"
.align 8
.LC7:
.string "cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n"
.align 8
.LC8:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC9:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC10:
.string "Failed to free device vector A (error code %s)!\n"
.align 8
.LC11:
.string "Failed to free device vector B (error code %s)!\n"
.align 8
.LC12:
.string "Failed to free device vector C (error code %s)!\n"
.align 8
.LC13:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, XDIM(%rip)
movl $40, YDIM(%rip)
cmpl $1, %edi
jg .L43
movslq YDIM(%rip), %rbp
movslq XDIM(%rip), %rax
imulq %rax, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
.L37:
movl $0, %ebx
.L20:
call rand@PLT
andl $15, %eax
movl %eax, (%r14,%rbx,4)
call rand@PLT
andl $15, %eax
movl %eax, 0(%r13,%rbx,4)
movl $0, (%r12,%rbx,4)
movl XDIM(%rip), %eax
addq $1, %rbx
imull %eax, %eax
cmpl %ebx, %eax
jg .L20
.L21:
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L49
movl XDIM(%rip), %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L29:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L51
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L55
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L56
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L57
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, XDIM(%rip)
movl %eax, YDIM(%rip)
movslq %eax, %rbp
imulq %rbp, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
imull %ebx, %ebx
testl %ebx, %ebx
jg .L37
testq %r14, %r14
sete %al
testq %r13, %r13
sete %dl
orb %dl, %al
jne .L39
testq %r12, %r12
jne .L21
.L39:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl $82, %ecx
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl $88, %ecx
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $94, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $102, %ecx
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl $108, %ecx
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl $114, %ecx
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl XDIM(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
jmp .L29
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z7matMultPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7matMultPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl YDIM
.bss
.align 4
.type YDIM, @object
.size YDIM, 4
YDIM:
.zero 4
.globl XDIM
.align 4
.type XDIM, @object
.size XDIM, 4
XDIM:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
int XDIM;
int YDIM;
/*
* NXN Matrix Multiplication
*/
__global__ void
matMult(const int *A, const int *B, int *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
for(int j = 0; j < numElements; j++){
int idx = (i*numElements)+j;
for(int k = 0; k < numElements; k++){
C[idx] += A[(i*numElements)+k] * B[(k*numElements)+j];
}
}
//printf("---→test: %d", i);
}
}
void printMat(int * M, int XDIM){
int i;
int j;
for(i = 0; i < XDIM; i++){
for(j = 0; j < XDIM; j++){
printf(" %d ", M[i*XDIM+j]);
}
printf("\n");
}
}
int main(int argc, char **argv){
XDIM = 40;
YDIM = 40;
if(argc > 1){
XDIM = atoi(argv[1]);
YDIM = XDIM;
}
//STEP 1 : Allocate in host
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
// Print the mat size to be used, and compute its size
size_t size = sizeof(int*)*YDIM*XDIM;
//printf("[Mat multiplication of %d elements]\n", YDIM);
// Allocate the host input vector A
int * h_A = (int *)malloc(size);
// Allocate the host input vector B
int * h_B = (int *)malloc(size);
// Allocate the host output vector C
int * h_C = (int *)malloc(size);
// Initialize h_A and h_B with random numbers, h_C with 0's
for(int i = 0; i < XDIM*XDIM; i++){
h_A[i] = rand() & 0xF;
h_B[i] = rand() & 0xF;
h_C[i] = 0;
}
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
//STEP 2: ALLOCATE IN CUDA
// Allocate device memory
int *d_A = NULL;
int *d_B = NULL;
int *d_C = NULL;
cudaError_t error;
error = cudaMalloc((void **) &d_A, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_A returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **) &d_B, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_B returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **) &d_C, size);
if (error != cudaSuccess)
{
printf("cudaMalloc d_C returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// copy host memory to device
error = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_A,h_A) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// Launch the Mat mult CUDA Kernel
int threadsPerBlock = 1024;
int blocksPerGrid =(XDIM + threadsPerBlock - 1) / threadsPerBlock;
//printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
matMult<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, XDIM);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
//printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free device global memory
err = cudaFree(d_A);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_B);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_C);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
//printMat(h_A,XDIM);
//printMat(h_B,XDIM);
//printMat(h_C,XDIM);
free(h_A);
free(h_B);
free(h_C);
// Reset the device and exit
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//printf("Done\n");
return 0;
} | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
int XDIM;
int YDIM;
/*
* NXN Matrix Multiplication
*/
__global__ void
matMult(const int *A, const int *B, int *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
for(int j = 0; j < numElements; j++){
int idx = (i*numElements)+j;
for(int k = 0; k < numElements; k++){
C[idx] += A[(i*numElements)+k] * B[(k*numElements)+j];
}
}
//printf("---→test: %d", i);
}
}
void printMat(int * M, int XDIM){
int i;
int j;
for(i = 0; i < XDIM; i++){
for(j = 0; j < XDIM; j++){
printf(" %d ", M[i*XDIM+j]);
}
printf("\n");
}
}
int main(int argc, char **argv){
XDIM = 40;
YDIM = 40;
if(argc > 1){
XDIM = atoi(argv[1]);
YDIM = XDIM;
}
//STEP 1 : Allocate in host
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the mat size to be used, and compute its size
size_t size = sizeof(int*)*YDIM*XDIM;
//printf("[Mat multiplication of %d elements]\n", YDIM);
// Allocate the host input vector A
int * h_A = (int *)malloc(size);
// Allocate the host input vector B
int * h_B = (int *)malloc(size);
// Allocate the host output vector C
int * h_C = (int *)malloc(size);
// Initialize h_A and h_B with random numbers, h_C with 0's
for(int i = 0; i < XDIM*XDIM; i++){
h_A[i] = rand() & 0xF;
h_B[i] = rand() & 0xF;
h_C[i] = 0;
}
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
//STEP 2: ALLOCATE IN CUDA
// Allocate device memory
int *d_A = NULL;
int *d_B = NULL;
int *d_C = NULL;
hipError_t error;
error = hipMalloc((void **) &d_A, size);
if (error != hipSuccess)
{
printf("hipMalloc d_A returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **) &d_B, size);
if (error != hipSuccess)
{
printf("hipMalloc d_B returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **) &d_C, size);
if (error != hipSuccess)
{
printf("hipMalloc d_C returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// copy host memory to device
error = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_A,h_A) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// Launch the Mat mult CUDA Kernel
int threadsPerBlock = 1024;
int blocksPerGrid =(XDIM + threadsPerBlock - 1) / threadsPerBlock;
//printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
matMult<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, XDIM);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
//printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free device global memory
err = hipFree(d_A);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_B);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_C);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
//printMat(h_A,XDIM);
//printMat(h_B,XDIM);
//printMat(h_C,XDIM);
free(h_A);
free(h_B);
free(h_C);
// Reset the device and exit
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//printf("Done\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
int XDIM;
int YDIM;
/*
* NXN Matrix Multiplication
*/
__global__ void
matMult(const int *A, const int *B, int *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
for(int j = 0; j < numElements; j++){
int idx = (i*numElements)+j;
for(int k = 0; k < numElements; k++){
C[idx] += A[(i*numElements)+k] * B[(k*numElements)+j];
}
}
//printf("---→test: %d", i);
}
}
void printMat(int * M, int XDIM){
int i;
int j;
for(i = 0; i < XDIM; i++){
for(j = 0; j < XDIM; j++){
printf(" %d ", M[i*XDIM+j]);
}
printf("\n");
}
}
int main(int argc, char **argv){
XDIM = 40;
YDIM = 40;
if(argc > 1){
XDIM = atoi(argv[1]);
YDIM = XDIM;
}
//STEP 1 : Allocate in host
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the mat size to be used, and compute its size
size_t size = sizeof(int*)*YDIM*XDIM;
//printf("[Mat multiplication of %d elements]\n", YDIM);
// Allocate the host input vector A
int * h_A = (int *)malloc(size);
// Allocate the host input vector B
int * h_B = (int *)malloc(size);
// Allocate the host output vector C
int * h_C = (int *)malloc(size);
// Initialize h_A and h_B with random numbers, h_C with 0's
for(int i = 0; i < XDIM*XDIM; i++){
h_A[i] = rand() & 0xF;
h_B[i] = rand() & 0xF;
h_C[i] = 0;
}
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
//STEP 2: ALLOCATE IN CUDA
// Allocate device memory
int *d_A = NULL;
int *d_B = NULL;
int *d_C = NULL;
hipError_t error;
error = hipMalloc((void **) &d_A, size);
if (error != hipSuccess)
{
printf("hipMalloc d_A returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **) &d_B, size);
if (error != hipSuccess)
{
printf("hipMalloc d_B returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **) &d_C, size);
if (error != hipSuccess)
{
printf("hipMalloc d_C returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// copy host memory to device
error = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_A,h_A) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// Launch the Mat mult CUDA Kernel
int threadsPerBlock = 1024;
int blocksPerGrid =(XDIM + threadsPerBlock - 1) / threadsPerBlock;
//printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
matMult<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, XDIM);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
//printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free device global memory
err = hipFree(d_A);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_B);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_C);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
//printMat(h_A,XDIM);
//printMat(h_B,XDIM);
//printMat(h_C,XDIM);
free(h_A);
free(h_B);
free(h_C);
// Reset the device and exit
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//printf("Done\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7matMultPKiS0_Pii
.globl _Z7matMultPKiS0_Pii
.p2align 8
.type _Z7matMultPKiS0_Pii,@function
_Z7matMultPKiS0_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v8, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v3, s10, v0
v_mov_b32_e32 v5, v1
s_mov_b64 s[8:9], s[6:7]
s_mov_b32 s3, s2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
.p2align 6
.LBB0_3:
global_load_b32 v11, v[5:6], off
global_load_b32 v12, v8, s[8:9]
v_add_co_u32 v5, vcc_lo, v5, 4
s_add_i32 s3, s3, -1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_u32 s8, s8, s4
s_addc_u32 s9, s9, s5
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v12, v11, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v7, v9
global_store_b32 v[3:4], v9, off
s_cbranch_scc0 .LBB0_3
s_add_i32 s10, s10, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s10, s2
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7matMultPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7matMultPKiS0_Pii, .Lfunc_end0-_Z7matMultPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7matMultPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7matMultPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
int XDIM;
int YDIM;
/*
* NXN Matrix Multiplication
*/
__global__ void
matMult(const int *A, const int *B, int *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
for(int j = 0; j < numElements; j++){
int idx = (i*numElements)+j;
for(int k = 0; k < numElements; k++){
C[idx] += A[(i*numElements)+k] * B[(k*numElements)+j];
}
}
//printf("---→test: %d", i);
}
}
void printMat(int * M, int XDIM){
int i;
int j;
for(i = 0; i < XDIM; i++){
for(j = 0; j < XDIM; j++){
printf(" %d ", M[i*XDIM+j]);
}
printf("\n");
}
}
int main(int argc, char **argv){
XDIM = 40;
YDIM = 40;
if(argc > 1){
XDIM = atoi(argv[1]);
YDIM = XDIM;
}
//STEP 1 : Allocate in host
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
// Print the mat size to be used, and compute its size
size_t size = sizeof(int*)*YDIM*XDIM;
//printf("[Mat multiplication of %d elements]\n", YDIM);
// Allocate the host input vector A
int * h_A = (int *)malloc(size);
// Allocate the host input vector B
int * h_B = (int *)malloc(size);
// Allocate the host output vector C
int * h_C = (int *)malloc(size);
// Initialize h_A and h_B with random numbers, h_C with 0's
for(int i = 0; i < XDIM*XDIM; i++){
h_A[i] = rand() & 0xF;
h_B[i] = rand() & 0xF;
h_C[i] = 0;
}
// Verify that allocations succeeded
if (h_A == NULL || h_B == NULL || h_C == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
//STEP 2: ALLOCATE IN CUDA
// Allocate device memory
int *d_A = NULL;
int *d_B = NULL;
int *d_C = NULL;
hipError_t error;
error = hipMalloc((void **) &d_A, size);
if (error != hipSuccess)
{
printf("hipMalloc d_A returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **) &d_B, size);
if (error != hipSuccess)
{
printf("hipMalloc d_B returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **) &d_C, size);
if (error != hipSuccess)
{
printf("hipMalloc d_C returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// copy host memory to device
error = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_A,h_A) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
error = hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
// Launch the Mat mult CUDA Kernel
int threadsPerBlock = 1024;
int blocksPerGrid =(XDIM + threadsPerBlock - 1) / threadsPerBlock;
//printf("CUDA kernel launch with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
matMult<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, XDIM);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch vectorAdd kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
//printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free device global memory
err = hipFree(d_A);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_B);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_C);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
//printMat(h_A,XDIM);
//printMat(h_B,XDIM);
//printMat(h_C,XDIM);
free(h_A);
free(h_B);
free(h_C);
// Reset the device and exit
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//printf("Done\n");
return 0;
} | .text
.file "p2-matrixMult_gpu-threads.hip"
.globl _Z22__device_stub__matMultPKiS0_Pii # -- Begin function _Z22__device_stub__matMultPKiS0_Pii
.p2align 4, 0x90
.type _Z22__device_stub__matMultPKiS0_Pii,@function
_Z22__device_stub__matMultPKiS0_Pii: # @_Z22__device_stub__matMultPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7matMultPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__matMultPKiS0_Pii, .Lfunc_end0-_Z22__device_stub__matMultPKiS0_Pii
.cfi_endproc
# -- End function
.globl _Z8printMatPii # -- Begin function _Z8printMatPii
.p2align 4, 0x90
.type _Z8printMatPii,@function
_Z8printMatPii: # @_Z8printMatPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %ebp
cmpq %r15, %r12
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8printMatPii, .Lfunc_end1-_Z8printMatPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, XDIM(%rip)
movl $40, YDIM(%rip)
cmpl $2, %edi
jl .LBB2_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, XDIM(%rip)
movl %eax, YDIM(%rip)
.LBB2_2:
movslq YDIM(%rip), %r12
movslq XDIM(%rip), %r13
imulq %r13, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
je .LBB2_5
# %bb.3: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
andl $15, %eax
movl %eax, (%rbx,%r13,4)
callq rand
andl $15, %eax
movl %eax, (%r14,%r13,4)
movl $0, (%r15,%r13,4)
incq %r13
movl XDIM(%rip), %eax
imull %eax, %eax
cmpq %rax, %r13
jb .LBB2_4
.LBB2_5: # %._crit_edge
testq %rbx, %rbx
je .LBB2_38
# %bb.6: # %._crit_edge
testq %r14, %r14
je .LBB2_38
# %bb.7: # %._crit_edge
testq %r15, %r15
je .LBB2_38
# %bb.8:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_9
# %bb.11:
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.13:
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_16
# %bb.17:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.19:
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_20
# %bb.21:
movl XDIM(%rip), %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl XDIM(%rip), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7matMultPKiS0_Pii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.26:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.27:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_28
# %bb.29:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_30
# %bb.31:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_32
# %bb.33:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_34
# %bb.35:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_36
# %bb.37:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_25
.LBB2_38:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_9:
movl $.L.str.3, %edi
movl %eax, %esi
movl $82, %edx
jmp .LBB2_10
.LBB2_12:
movl $.L.str.4, %edi
movl %eax, %esi
movl $88, %edx
jmp .LBB2_10
.LBB2_14:
movl $.L.str.5, %edi
movl %eax, %esi
movl $94, %edx
jmp .LBB2_10
.LBB2_16:
movl $.L.str.6, %edi
movl %eax, %esi
movl $102, %edx
jmp .LBB2_10
.LBB2_18:
movl $.L.str.7, %edi
movl %eax, %esi
movl $108, %edx
jmp .LBB2_10
.LBB2_20:
movl $.L.str.7, %edi
movl %eax, %esi
movl $114, %edx
.LBB2_10:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_25
.LBB2_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_25
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB2_25
.LBB2_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB2_25
.LBB2_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
.LBB2_25:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7matMultPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type XDIM,@object # @XDIM
.bss
.globl XDIM
.p2align 2, 0x0
XDIM:
.long 0 # 0x0
.size XDIM, 4
.type YDIM,@object # @YDIM
.globl YDIM
.p2align 2, 0x0
YDIM:
.long 0 # 0x0
.size YDIM, 4
.type _Z7matMultPKiS0_Pii,@object # @_Z7matMultPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z7matMultPKiS0_Pii
.p2align 3, 0x0
_Z7matMultPKiS0_Pii:
.quad _Z22__device_stub__matMultPKiS0_Pii
.size _Z7matMultPKiS0_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %d "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc d_A returned error code %d, line(%d)\n"
.size .L.str.3, 48
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc d_B returned error code %d, line(%d)\n"
.size .L.str.4, 48
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc d_C returned error code %d, line(%d)\n"
.size .L.str.5, 48
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy (d_A,h_A) returned error code %d, line(%d)\n"
.size .L.str.6, 54
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n"
.size .L.str.7, 54
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.8, 52
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to free device vector A (error code %s)!\n"
.size .L.str.10, 49
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to free device vector B (error code %s)!\n"
.size .L.str.11, 49
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to free device vector C (error code %s)!\n"
.size .L.str.12, 49
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.13, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7matMultPKiS0_Pii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__matMultPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7matMultPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7matMultPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R13, c[0x0][0x178] ; /* 0x00005e00000d7a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x178], !P0 ; /* 0x00005e000b007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0090*/ IADD3 R0, R13, -0x1, RZ ; /* 0xffffffff0d007810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD R11, R11, c[0x0][0x178], RZ ; /* 0x00005e000b0b7a24 */
/* 0x000fe200078e02ff */
/*00b0*/ LOP3.LUT R16, R13.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d107812 */
/* 0x040fe200078ec0ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*00e0*/ SHF.L.U32 R13, R13, 0x2, RZ ; /* 0x000000020d0d7819 */
/* 0x000fe400000006ff */
/*00f0*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fe200078e0202 */
/*0110*/ IADD3 R12, -R16, c[0x0][0x178], RZ ; /* 0x00005e00100c7a10 */
/* 0x000fc60007ffe1ff */
/*0120*/ IADD3 R7, R11, R15, RZ ; /* 0x0000000f0b077210 */
/* 0x003fe40007ffe0ff */
/*0130*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc60000000f00 */
/*0150*/ IMAD.WIDE R6, R7, R14, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e020e */
/*0160*/ @!P1 BRA 0xd10 ; /* 0x00000ba000009947 */
/* 0x020fea0003800000 */
/*0170*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f04270 */
/*0180*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000162000c1e1900 */
/*0190*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*01a0*/ IADD3 R17, R15, c[0x0][0x178], RZ ; /* 0x00005e000f117a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ MOV R0, R12 ; /* 0x0000000c00007202 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc40000000f00 */
/*01e0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0200*/ @!P0 BRA 0xb50 ; /* 0x0000094000008947 */
/* 0x001fea0003800000 */
/*0210*/ ISETP.GT.AND P2, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f44270 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0230*/ @!P2 BRA 0x800 ; /* 0x000005c00000a947 */
/* 0x000fea0003800000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fe200078e0204 */
/*0260*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000eaa000c1e1900 */
/*0270*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD R25, R18, R20, R21 ; /* 0x0000001412197224 */
/* 0x025fe400078e0215 */
/*0290*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*02a0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x004fc400078e0219 */
/*02e0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*02f0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc800078e0216 */
/*0330*/ IMAD R29, R24, R26, R27 ; /* 0x0000001a181d7224 */
/* 0x004fca00078e021b */
/*0340*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0350*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e28000c1e1900 */
/*0360*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x000e22000c1e1900 */
/*0370*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*0380*/ IMAD.WIDE R20, R15, 0x4, R4 ; /* 0x000000040f147825 */
/* 0x000fc800078e0204 */
/*0390*/ IMAD R25, R18, R24, R29 ; /* 0x0000001812197224 */
/* 0x001fca00078e021d */
/*03a0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e68000c1e1900 */
/*03c0*/ LDG.E R22, [R8.64+0x10] ; /* 0x0000100408167981 */
/* 0x000e64000c1e1900 */
/*03d0*/ IMAD R27, R20, R22, R25 ; /* 0x00000016141b7224 */
/* 0x002fc400078e0219 */
/*03e0*/ IMAD.WIDE R22, R17, 0x4, R4 ; /* 0x0000000411167825 */
/* 0x000fc600078e0204 */
/*03f0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0400*/ LDG.E R19, [R8.64+0x14] ; /* 0x0000140408137981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea4000c1e1900 */
/*0420*/ IMAD R29, R18, R19, R27 ; /* 0x00000013121d7224 */
/* 0x004fc400078e021b */
/*0430*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc600078e0216 */
/*0440*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0450*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000e28000c1e1900 */
/*0460*/ LDG.E R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000e24000c1e1900 */
/*0470*/ IMAD R25, R24, R20, R29 ; /* 0x0000001418197224 */
/* 0x001fc400078e021d */
/*0480*/ IMAD.WIDE R20, R14, c[0x0][0x178], R18 ; /* 0x00005e000e147a25 */
/* 0x000fc600078e0212 */
/*0490*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e68000c1e1900 */
/*04b0*/ LDG.E R24, [R8.64+0x1c] ; /* 0x00001c0408187981 */
/* 0x000e62000c1e1900 */
/*04c0*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*04d0*/ IMAD.WIDE R22, R15, 0x4, R4 ; /* 0x000000040f167825 */
/* 0x000fc800078e0204 */
/*04e0*/ IMAD R27, R20, R24, R25 ; /* 0x00000018141b7224 */
/* 0x002fca00078e0219 */
/*04f0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0500*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R18, [R8.64+0x20] ; /* 0x0000200408127981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IMAD R29, R22, R18, R27 ; /* 0x00000012161d7224 */
/* 0x004fc400078e021b */
/*0530*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0540*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0550*/ LDG.E R21, [R8.64+0x24] ; /* 0x0000240408157981 */
/* 0x000e28000c1e1900 */
/*0560*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e24000c1e1900 */
/*0570*/ IMAD R25, R20, R21, R29 ; /* 0x0000001514197224 */
/* 0x001fc400078e021d */
/*0580*/ IMAD.WIDE R20, R14, c[0x0][0x178], R18 ; /* 0x00005e000e147a25 */
/* 0x000fc600078e0212 */
/*0590*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000e68000c1e1900 */
/*05b0*/ LDG.E R22, [R8.64+0x28] ; /* 0x0000280408167981 */
/* 0x000e64000c1e1900 */
/*05c0*/ IMAD R27, R24, R22, R25 ; /* 0x00000016181b7224 */
/* 0x002fc400078e0219 */
/*05d0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*05e0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*05f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R24, [R8.64+0x2c] ; /* 0x00002c0408187981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*0620*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fc800078e0204 */
/*0630*/ IMAD R29, R22, R24, R27 ; /* 0x00000018161d7224 */
/* 0x004fca00078e021b */
/*0640*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R20, [R8.64+0x30] ; /* 0x0000300408147981 */
/* 0x000e24000c1e1900 */
/*0670*/ IMAD R25, R18, R20, R29 ; /* 0x0000001412197224 */
/* 0x001fc400078e021d */
/*0680*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*0690*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*06a0*/ LDG.E R23, [R8.64+0x34] ; /* 0x0000340408177981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000e64000c1e1900 */
/*06c0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x002fc400078e0219 */
/*06d0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*06e0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0001e8000c101904 */
/*06f0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R18, [R8.64+0x38] ; /* 0x0000380408127981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD R29, R24, R18, R27 ; /* 0x00000012181d7224 */
/* 0x004fc400078e021b */
/*0730*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc600078e0216 */
/*0740*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0001e8000c101904 */
/*0750*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R24, [R8.64+0x3c] ; /* 0x00003c0408187981 */
/* 0x0002a2000c1e1900 */
/*0770*/ ISETP.GT.AND P2, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f44270 */
/*0780*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*0790*/ IADD3 R20, P3, R8, 0x40, RZ ; /* 0x0000004008147810 */
/* 0x000fc40007f7e0ff */
/*07a0*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ IADD3.X R9, RZ, R9, RZ, P3, !PT ; /* 0x00000009ff097210 */
/* 0x002fe40001ffe4ff */
/*07c0*/ MOV R8, R20 ; /* 0x0000001400087202 */
/* 0x000fe20000000f00 */
/*07d0*/ IMAD R21, R18, R24, R29 ; /* 0x0000001812157224 */
/* 0x004fca00078e021d */
/*07e0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001e2000c101904 */
/*07f0*/ @P2 BRA 0x250 ; /* 0xfffffa5000002947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.GT.AND P2, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f44270 */
/*0810*/ @!P2 BRA 0xb30 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fe200078e0204 */
/*0830*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000eaa000c1e1900 */
/*0840*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0850*/ IMAD R25, R18, R20, R21 ; /* 0x0000001412197224 */
/* 0x025fe400078e0215 */
/*0860*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*0870*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*0880*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x004fc400078e0219 */
/*08b0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*08c0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*08d0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc800078e0216 */
/*0900*/ IMAD R29, R24, R26, R27 ; /* 0x0000001a181d7224 */
/* 0x004fca00078e021b */
/*0910*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0005e8000c101904 */
/*0920*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e28000c1e1900 */
/*0930*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x000e22000c1e1900 */
/*0940*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fcc00078e0204 */
/*0950*/ IMAD.WIDE R20, R15, 0x4, R4 ; /* 0x000000040f147825 */
/* 0x000fc800078e0204 */
/*0960*/ IMAD R25, R18, R24, R29 ; /* 0x0000001812197224 */
/* 0x001fca00078e021d */
/*0970*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*0980*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e68000c1e1900 */
/*0990*/ LDG.E R22, [R8.64+0x10] ; /* 0x0000100408167981 */
/* 0x000e64000c1e1900 */
/*09a0*/ IMAD R27, R20, R22, R25 ; /* 0x00000016141b7224 */
/* 0x002fc400078e0219 */
/*09b0*/ IMAD.WIDE R22, R17, 0x4, R4 ; /* 0x0000000411167825 */
/* 0x000fc600078e0204 */
/*09c0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R19, [R8.64+0x14] ; /* 0x0000140408137981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD R29, R18, R19, R27 ; /* 0x00000013121d7224 */
/* 0x004fc400078e021b */
/*0a00*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fc600078e0216 */
/*0a10*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000ea4000c1e1900 */
/*0a40*/ IMAD R20, R24, R20, R29 ; /* 0x0000001418147224 */
/* 0x004fc400078e021d */
/*0a50*/ IMAD.WIDE R24, R14, c[0x0][0x178], R18 ; /* 0x00005e000e187a25 */
/* 0x001fc600078e0212 */
/*0a60*/ STG.E [R6.64], R20 ; /* 0x0000001406007986 */
/* 0x0003e8000c101904 */
/*0a70*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0a80*/ LDG.E R21, [R8.64+0x1c] ; /* 0x00001c0408157981 */
/* 0x0000a2000c1e1900 */
/*0a90*/ IADD3 R22, P2, R8, 0x20, RZ ; /* 0x0000002008167810 */
/* 0x000fe20007f5e0ff */
/*0aa0*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*0ab0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0ac0*/ IADD3.X R23, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff177210 */
/* 0x000fe400017fe4ff */
/*0ad0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe40007ffe0ff */
/*0af0*/ MOV R8, R22 ; /* 0x0000001600087202 */
/* 0x001fe40000000f00 */
/*0b00*/ MOV R9, R23 ; /* 0x0000001700097202 */
/* 0x000fe20000000f00 */
/*0b10*/ IMAD R21, R25, R21, R20 ; /* 0x0000001519157224 */
/* 0x004fca00078e0214 */
/*0b20*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0003e4000c101904 */
/*0b30*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0b40*/ @!P0 BRA 0xd10 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.WIDE R18, R15, 0x4, R4 ; /* 0x000000040f127825 */
/* 0x000fe200078e0204 */
/*0b60*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x002eaa000c1e1900 */
/*0b70*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD R25, R18, R20, R21 ; /* 0x0000001412197224 */
/* 0x025fe400078e0215 */
/*0b90*/ IMAD.WIDE R20, R17, 0x4, R4 ; /* 0x0000000411147825 */
/* 0x000fc600078e0204 */
/*0ba0*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea4000c1e1900 */
/*0bd0*/ IMAD R27, R22, R23, R25 ; /* 0x00000017161b7224 */
/* 0x004fc400078e0219 */
/*0be0*/ IMAD.WIDE R22, R14, c[0x0][0x178], R20 ; /* 0x00005e000e167a25 */
/* 0x000fc600078e0214 */
/*0bf0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0001e8000c101904 */
/*0c00*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea8000c1e1900 */
/*0c10*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000ea2000c1e1900 */
/*0c20*/ IMAD.WIDE R18, R14, c[0x0][0x178], R22 ; /* 0x00005e000e127a25 */
/* 0x000fe200078e0216 */
/*0c30*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc60007ffe0ff */
/*0c40*/ IMAD R29, R24, R26, R27 ; /* 0x0000001a181d7224 */
/* 0x004fca00078e021b */
/*0c50*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0001e8000c101904 */
/*0c60*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*0c70*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x0002a2000c1e1900 */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x000fe200078e0204 */
/*0ca0*/ IADD3 R20, P2, R8, 0x10, RZ ; /* 0x0000001008147810 */
/* 0x000fc40007f5e0ff */
/*0cb0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x002fe400017fe4ff */
/*0cd0*/ MOV R8, R20 ; /* 0x0000001400087202 */
/* 0x000fe20000000f00 */
/*0ce0*/ IMAD R21, R18, R24, R29 ; /* 0x0000001812157224 */
/* 0x004fca00078e021d */
/*0cf0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001e4000c101904 */
/*0d00*/ @P0 BRA 0xb50 ; /* 0xfffffe4000000947 */
/* 0x001fea000383ffff */
/*0d10*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fda0003f05270 */
/*0d20*/ @!P0 BRA 0xec0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0d30*/ IADD3 R5, R11, R10, RZ ; /* 0x0000000a0b057210 */
/* 0x000fe20007ffe0ff */
/*0d40*/ IMAD R19, R10, c[0x0][0x178], R15 ; /* 0x00005e000a137a24 */
/* 0x000fe200078e020f */
/*0d50*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea6000c1e1900 */
/*0d60*/ IMAD.WIDE R8, R19, R14, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x000fc800078e020e */
/*0d70*/ IMAD.WIDE R4, R5, R14, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e020e */
/*0d80*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0d90*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0da0*/ ISETP.NE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe20003f05270 */
/*0db0*/ IMAD R21, R8, R17, R0 ; /* 0x0000001108157224 */
/* 0x027fca00078e0200 */
/*0dc0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001ee000c101904 */
/*0dd0*/ @!P0 BRA 0xec0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0de0*/ IADD3 R19, R19, c[0x0][0x178], RZ ; /* 0x00005e0013137a10 */
/* 0x000fe20007ffe0ff */
/*0df0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea8000c1e1900 */
/*0e00*/ IMAD.WIDE R8, R19, R14, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x000fcc00078e020e */
/*0e10*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0e20*/ ISETP.NE.AND P0, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe20003f05270 */
/*0e30*/ IMAD R17, R8, R17, R21 ; /* 0x0000001108117224 */
/* 0x004fca00078e0215 */
/*0e40*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003ee000c101904 */
/*0e50*/ @!P0 BRA 0xec0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0e60*/ IADD3 R9, R19, c[0x0][0x178], RZ ; /* 0x00005e0013097a10 */
/* 0x000fe20007ffe0ff */
/*0e70*/ LDG.E R5, [R4.64+0x8] ; /* 0x0000080404057981 */
/* 0x000ea8000c1e1900 */
/*0e80*/ IMAD.WIDE R8, R9, R14, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fcc00078e020e */
/*0e90*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*0ea0*/ IMAD R17, R8, R5, R17 ; /* 0x0000000508117224 */
/* 0x006fca00078e0211 */
/*0eb0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0003e4000c101904 */
/*0ec0*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*0ed0*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fda0003f06270 */
/*0ee0*/ @!P0 BRA 0x120 ; /* 0xfffff23000008947 */
/* 0x000fea000383ffff */
/*0ef0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f00*/ BRA 0xf00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7matMultPKiS0_Pii
.globl _Z7matMultPKiS0_Pii
.p2align 8
.type _Z7matMultPKiS0_Pii,@function
_Z7matMultPKiS0_Pii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v8, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v3, s10, v0
v_mov_b32_e32 v5, v1
s_mov_b64 s[8:9], s[6:7]
s_mov_b32 s3, s2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v7, v[3:4], off
.p2align 6
.LBB0_3:
global_load_b32 v11, v[5:6], off
global_load_b32 v12, v8, s[8:9]
v_add_co_u32 v5, vcc_lo, v5, 4
s_add_i32 s3, s3, -1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_u32 s8, s8, s4
s_addc_u32 s9, s9, s5
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v12, v11, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v7, v9
global_store_b32 v[3:4], v9, off
s_cbranch_scc0 .LBB0_3
s_add_i32 s10, s10, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s10, s2
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7matMultPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7matMultPKiS0_Pii, .Lfunc_end0-_Z7matMultPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7matMultPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7matMultPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015f56a_00000000-6_p2-matrixMult_gpu-threads.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " %d "
.LC1:
.string "\n"
.text
.globl _Z8printMatPii
.type _Z8printMatPii, @function
_Z8printMatPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8printMatPii, .-_Z8printMatPii
.globl _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
.type _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii, @function
_Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7matMultPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii, .-_Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
.globl _Z7matMultPKiS0_Pii
.type _Z7matMultPKiS0_Pii, @function
_Z7matMultPKiS0_Pii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7matMultPKiS0_Pii, .-_Z7matMultPKiS0_Pii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Failed to allocate host vectors!\n"
.align 8
.LC3:
.string "cudaMalloc d_A returned error code %d, line(%d)\n"
.align 8
.LC4:
.string "cudaMalloc d_B returned error code %d, line(%d)\n"
.align 8
.LC5:
.string "cudaMalloc d_C returned error code %d, line(%d)\n"
.align 8
.LC6:
.string "cudaMemcpy (d_A,h_A) returned error code %d, line(%d)\n"
.align 8
.LC7:
.string "cudaMemcpy (d_B,h_B) returned error code %d, line(%d)\n"
.align 8
.LC8:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC9:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC10:
.string "Failed to free device vector A (error code %s)!\n"
.align 8
.LC11:
.string "Failed to free device vector B (error code %s)!\n"
.align 8
.LC12:
.string "Failed to free device vector C (error code %s)!\n"
.align 8
.LC13:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, XDIM(%rip)
movl $40, YDIM(%rip)
cmpl $1, %edi
jg .L43
movslq YDIM(%rip), %rbp
movslq XDIM(%rip), %rax
imulq %rax, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
.L37:
movl $0, %ebx
.L20:
call rand@PLT
andl $15, %eax
movl %eax, (%r14,%rbx,4)
call rand@PLT
andl $15, %eax
movl %eax, 0(%r13,%rbx,4)
movl $0, (%r12,%rbx,4)
movl XDIM(%rip), %eax
addq $1, %rbx
imull %eax, %eax
cmpl %ebx, %eax
jg .L20
.L21:
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L49
movl XDIM(%rip), %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L29:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L51
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L55
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L56
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L57
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, XDIM(%rip)
movl %eax, YDIM(%rip)
movslq %eax, %rbp
imulq %rbp, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
imull %ebx, %ebx
testl %ebx, %ebx
jg .L37
testq %r14, %r14
sete %al
testq %r13, %r13
sete %dl
orb %dl, %al
jne .L39
testq %r12, %r12
jne .L21
.L39:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl $82, %ecx
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl $88, %ecx
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $94, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $102, %ecx
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl $108, %ecx
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl $114, %ecx
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl XDIM(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z7matMultPKiS0_PiiPKiS0_Pii
jmp .L29
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z7matMultPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7matMultPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl YDIM
.bss
.align 4
.type YDIM, @object
.size YDIM, 4
YDIM:
.zero 4
.globl XDIM
.align 4
.type XDIM, @object
.size XDIM, 4
XDIM:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p2-matrixMult_gpu-threads.hip"
.globl _Z22__device_stub__matMultPKiS0_Pii # -- Begin function _Z22__device_stub__matMultPKiS0_Pii
.p2align 4, 0x90
.type _Z22__device_stub__matMultPKiS0_Pii,@function
_Z22__device_stub__matMultPKiS0_Pii: # @_Z22__device_stub__matMultPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7matMultPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__matMultPKiS0_Pii, .Lfunc_end0-_Z22__device_stub__matMultPKiS0_Pii
.cfi_endproc
# -- End function
.globl _Z8printMatPii # -- Begin function _Z8printMatPii
.p2align 4, 0x90
.type _Z8printMatPii,@function
_Z8printMatPii: # @_Z8printMatPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %ebp
cmpq %r15, %r12
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8printMatPii, .Lfunc_end1-_Z8printMatPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, XDIM(%rip)
movl $40, YDIM(%rip)
cmpl $2, %edi
jl .LBB2_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, XDIM(%rip)
movl %eax, YDIM(%rip)
.LBB2_2:
movslq YDIM(%rip), %r12
movslq XDIM(%rip), %r13
imulq %r13, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
je .LBB2_5
# %bb.3: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
andl $15, %eax
movl %eax, (%rbx,%r13,4)
callq rand
andl $15, %eax
movl %eax, (%r14,%r13,4)
movl $0, (%r15,%r13,4)
incq %r13
movl XDIM(%rip), %eax
imull %eax, %eax
cmpq %rax, %r13
jb .LBB2_4
.LBB2_5: # %._crit_edge
testq %rbx, %rbx
je .LBB2_38
# %bb.6: # %._crit_edge
testq %r14, %r14
je .LBB2_38
# %bb.7: # %._crit_edge
testq %r15, %r15
je .LBB2_38
# %bb.8:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_9
# %bb.11:
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.13:
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_16
# %bb.17:
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.19:
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_20
# %bb.21:
movl XDIM(%rip), %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl XDIM(%rip), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7matMultPKiS0_Pii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.26:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.27:
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_28
# %bb.29:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_30
# %bb.31:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_32
# %bb.33:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_34
# %bb.35:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_36
# %bb.37:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_25
.LBB2_38:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_9:
movl $.L.str.3, %edi
movl %eax, %esi
movl $82, %edx
jmp .LBB2_10
.LBB2_12:
movl $.L.str.4, %edi
movl %eax, %esi
movl $88, %edx
jmp .LBB2_10
.LBB2_14:
movl $.L.str.5, %edi
movl %eax, %esi
movl $94, %edx
jmp .LBB2_10
.LBB2_16:
movl $.L.str.6, %edi
movl %eax, %esi
movl $102, %edx
jmp .LBB2_10
.LBB2_18:
movl $.L.str.7, %edi
movl %eax, %esi
movl $108, %edx
jmp .LBB2_10
.LBB2_20:
movl $.L.str.7, %edi
movl %eax, %esi
movl $114, %edx
.LBB2_10:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_25
.LBB2_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_25
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB2_25
.LBB2_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB2_25
.LBB2_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
.LBB2_25:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7matMultPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type XDIM,@object # @XDIM
.bss
.globl XDIM
.p2align 2, 0x0
XDIM:
.long 0 # 0x0
.size XDIM, 4
.type YDIM,@object # @YDIM
.globl YDIM
.p2align 2, 0x0
YDIM:
.long 0 # 0x0
.size YDIM, 4
.type _Z7matMultPKiS0_Pii,@object # @_Z7matMultPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z7matMultPKiS0_Pii
.p2align 3, 0x0
_Z7matMultPKiS0_Pii:
.quad _Z22__device_stub__matMultPKiS0_Pii
.size _Z7matMultPKiS0_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %d "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc d_A returned error code %d, line(%d)\n"
.size .L.str.3, 48
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc d_B returned error code %d, line(%d)\n"
.size .L.str.4, 48
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc d_C returned error code %d, line(%d)\n"
.size .L.str.5, 48
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy (d_A,h_A) returned error code %d, line(%d)\n"
.size .L.str.6, 54
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy (d_B,h_B) returned error code %d, line(%d)\n"
.size .L.str.7, 54
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.8, 52
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to free device vector A (error code %s)!\n"
.size .L.str.10, 49
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to free device vector B (error code %s)!\n"
.size .L.str.11, 49
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to free device vector C (error code %s)!\n"
.size .L.str.12, 49
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.13, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7matMultPKiS0_Pii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__matMultPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7matMultPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | code for sm_80
Function : _Z6VecAddPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | .file "tmpxft_000d92ef_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.type _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, @function
_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, .-_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.type _Z6VecAddPKiS0_Pii, @function
_Z6VecAddPKiS0_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPKiS0_Pii, .-_Z6VecAddPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.p2align 8
.type _Z6VecAddPKiS0_Pii,@function
_Z6VecAddPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPKiS0_Pii, .Lfunc_end0-_Z6VecAddPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
} | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPKiS0_Pii # -- Begin function _Z21__device_stub__VecAddPKiS0_Pii
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPKiS0_Pii,@function
_Z21__device_stub__VecAddPKiS0_Pii: # @_Z21__device_stub__VecAddPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPKiS0_Pii, .Lfunc_end0-_Z21__device_stub__VecAddPKiS0_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPKiS0_Pii,@object # @_Z6VecAddPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z6VecAddPKiS0_Pii
.p2align 3, 0x0
_Z6VecAddPKiS0_Pii:
.quad _Z21__device_stub__VecAddPKiS0_Pii
.size _Z6VecAddPKiS0_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPKiS0_Pii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.p2align 8
.type _Z6VecAddPKiS0_Pii,@function
_Z6VecAddPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPKiS0_Pii, .Lfunc_end0-_Z6VecAddPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d92ef_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.type _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, @function
_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, .-_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.type _Z6VecAddPKiS0_Pii, @function
_Z6VecAddPKiS0_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPKiS0_Pii, .-_Z6VecAddPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPKiS0_Pii # -- Begin function _Z21__device_stub__VecAddPKiS0_Pii
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPKiS0_Pii,@function
_Z21__device_stub__VecAddPKiS0_Pii: # @_Z21__device_stub__VecAddPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPKiS0_Pii, .Lfunc_end0-_Z21__device_stub__VecAddPKiS0_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPKiS0_Pii,@object # @_Z6VecAddPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z6VecAddPKiS0_Pii
.p2align 3, 0x0
_Z6VecAddPKiS0_Pii:
.quad _Z21__device_stub__VecAddPKiS0_Pii
.size _Z6VecAddPKiS0_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPKiS0_Pii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define T 8 // As Threads
#define N 16
__global__ void vecMatrix(int *A, int *B)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int id = (i * N) + j;
if(i < N && j < N)
{
B[id] = A[id] + 1;
}
}
int main (int argc, char *argv[])
{
int i,j;
int size[N*N];
int A[N][N];
int sizearr = N*N *sizeof(int);
int *Adefault,*B;
for (i=0; i< N; i++)
{
for(j = 0 ; j<N ; j++ )
{
A[i][j] = ((i*i) +1) * (j+1);
printf("%5d ", A[i][j]);
}
}
printf("\n");
cudaMalloc( (void**)&Adefault,sizearr);
cudaMalloc( (void**)&B,sizearr);
cudaMemcpy( Adefault, A, sizearr, cudaMemcpyHostToDevice);
dim3 dimBlock(T,T);
dim3 dimGrid((N+ dimBlock.x - 1)/ dimBlock.x ,(N + dimBlock.y - 1) / dimBlock.y);
vecMatrix<<<dimGrid,dimBlock>>>(Adefault,B);
cudaMemcpy(size, B, sizearr, cudaMemcpyDeviceToHost);
cudaFree(Adefault);
cudaFree(B);
printf("Result\n");
for (i=0; i < N * N; i++)
{
printf("%5d ",size[i]);
}
printf("\n");
return 0;
} | code for sm_80
Function : _Z9vecMatrixPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0.reuse, 0xf, P0 ; /* 0x0000000f0000780c */
/* 0x040fe40000704670 */
/*0090*/ LEA R0, R0, R3, 0x4 ; /* 0x0000000300007211 */
/* 0x000fd600078e20ff */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*0100*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define T 8 // As Threads
#define N 16
__global__ void vecMatrix(int *A, int *B)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int id = (i * N) + j;
if(i < N && j < N)
{
B[id] = A[id] + 1;
}
}
int main (int argc, char *argv[])
{
int i,j;
int size[N*N];
int A[N][N];
int sizearr = N*N *sizeof(int);
int *Adefault,*B;
for (i=0; i< N; i++)
{
for(j = 0 ; j<N ; j++ )
{
A[i][j] = ((i*i) +1) * (j+1);
printf("%5d ", A[i][j]);
}
}
printf("\n");
cudaMalloc( (void**)&Adefault,sizearr);
cudaMalloc( (void**)&B,sizearr);
cudaMemcpy( Adefault, A, sizearr, cudaMemcpyHostToDevice);
dim3 dimBlock(T,T);
dim3 dimGrid((N+ dimBlock.x - 1)/ dimBlock.x ,(N + dimBlock.y - 1) / dimBlock.y);
vecMatrix<<<dimGrid,dimBlock>>>(Adefault,B);
cudaMemcpy(size, B, sizearr, cudaMemcpyDeviceToHost);
cudaFree(Adefault);
cudaFree(B);
printf("Result\n");
for (i=0; i < N * N; i++)
{
printf("%5d ",size[i]);
}
printf("\n");
return 0;
} | .file "tmpxft_0014198c_00000000-6_cuda4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9vecMatrixPiS_PiS_
.type _Z30__device_stub__Z9vecMatrixPiS_PiS_, @function
_Z30__device_stub__Z9vecMatrixPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9vecMatrixPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9vecMatrixPiS_PiS_, .-_Z30__device_stub__Z9vecMatrixPiS_PiS_
.globl _Z9vecMatrixPiS_
.type _Z9vecMatrixPiS_, @function
_Z9vecMatrixPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9vecMatrixPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9vecMatrixPiS_, .-_Z9vecMatrixPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5d "
.LC1:
.string "\n"
.LC2:
.string "Result\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2120, %rsp
.cfi_def_cfa_offset 2176
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
leaq 1136(%rsp), %r13
movl $0, %r15d
leaq .LC0(%rip), %r14
.L12:
movl %r15d, %r12d
imull %r15d, %r12d
addl $1, %r12d
leaq -64(%r13), %rbp
movl %r12d, %ebx
.L13:
movl %ebx, 0(%rbp)
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl %r12d, %ebx
addq $4, %rbp
cmpq %r13, %rbp
jne .L13
addl $1, %r15d
addq $64, %r13
cmpl $16, %r15d
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1072(%rsp), %r12
leaq .LC0(%rip), %rbp
.L16:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $2120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9vecMatrixPiS_PiS_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9vecMatrixPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vecMatrixPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define T 8 // As Threads
#define N 16
__global__ void vecMatrix(int *A, int *B)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int id = (i * N) + j;
if(i < N && j < N)
{
B[id] = A[id] + 1;
}
}
int main (int argc, char *argv[])
{
int i,j;
int size[N*N];
int A[N][N];
int sizearr = N*N *sizeof(int);
int *Adefault,*B;
for (i=0; i< N; i++)
{
for(j = 0 ; j<N ; j++ )
{
A[i][j] = ((i*i) +1) * (j+1);
printf("%5d ", A[i][j]);
}
}
printf("\n");
cudaMalloc( (void**)&Adefault,sizearr);
cudaMalloc( (void**)&B,sizearr);
cudaMemcpy( Adefault, A, sizearr, cudaMemcpyHostToDevice);
dim3 dimBlock(T,T);
dim3 dimGrid((N+ dimBlock.x - 1)/ dimBlock.x ,(N + dimBlock.y - 1) / dimBlock.y);
vecMatrix<<<dimGrid,dimBlock>>>(Adefault,B);
cudaMemcpy(size, B, sizearr, cudaMemcpyDeviceToHost);
cudaFree(Adefault);
cudaFree(B);
printf("Result\n");
for (i=0; i < N * N; i++)
{
printf("%5d ",size[i]);
}
printf("\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define T 8 // As Threads
#define N 16
__global__ void vecMatrix(int *A, int *B)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int id = (i * N) + j;
if(i < N && j < N)
{
B[id] = A[id] + 1;
}
}
int main (int argc, char *argv[])
{
int i,j;
int size[N*N];
int A[N][N];
int sizearr = N*N *sizeof(int);
int *Adefault,*B;
for (i=0; i< N; i++)
{
for(j = 0 ; j<N ; j++ )
{
A[i][j] = ((i*i) +1) * (j+1);
printf("%5d ", A[i][j]);
}
}
printf("\n");
hipMalloc( (void**)&Adefault,sizearr);
hipMalloc( (void**)&B,sizearr);
hipMemcpy( Adefault, A, sizearr, hipMemcpyHostToDevice);
dim3 dimBlock(T,T);
dim3 dimGrid((N+ dimBlock.x - 1)/ dimBlock.x ,(N + dimBlock.y - 1) / dimBlock.y);
vecMatrix<<<dimGrid,dimBlock>>>(Adefault,B);
hipMemcpy(size, B, sizearr, hipMemcpyDeviceToHost);
hipFree(Adefault);
hipFree(B);
printf("Result\n");
for (i=0; i < N * N; i++)
{
printf("%5d ",size[i]);
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define T 8 // As Threads
#define N 16
__global__ void vecMatrix(int *A, int *B)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int id = (i * N) + j;
if(i < N && j < N)
{
B[id] = A[id] + 1;
}
}
int main (int argc, char *argv[])
{
int i,j;
int size[N*N];
int A[N][N];
int sizearr = N*N *sizeof(int);
int *Adefault,*B;
for (i=0; i< N; i++)
{
for(j = 0 ; j<N ; j++ )
{
A[i][j] = ((i*i) +1) * (j+1);
printf("%5d ", A[i][j]);
}
}
printf("\n");
hipMalloc( (void**)&Adefault,sizearr);
hipMalloc( (void**)&B,sizearr);
hipMemcpy( Adefault, A, sizearr, hipMemcpyHostToDevice);
dim3 dimBlock(T,T);
dim3 dimGrid((N+ dimBlock.x - 1)/ dimBlock.x ,(N + dimBlock.y - 1) / dimBlock.y);
vecMatrix<<<dimGrid,dimBlock>>>(Adefault,B);
hipMemcpy(size, B, sizearr, hipMemcpyDeviceToHost);
hipFree(Adefault);
hipFree(B);
printf("Result\n");
for (i=0; i < N * N; i++)
{
printf("%5d ",size[i]);
}
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vecMatrixPiS_
.globl _Z9vecMatrixPiS_
.p2align 8
.type _Z9vecMatrixPiS_,@function
_Z9vecMatrixPiS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 16, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vecMatrixPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vecMatrixPiS_, .Lfunc_end0-_Z9vecMatrixPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vecMatrixPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vecMatrixPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define T 8 // As Threads
#define N 16
__global__ void vecMatrix(int *A, int *B)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int id = (i * N) + j;
if(i < N && j < N)
{
B[id] = A[id] + 1;
}
}
int main (int argc, char *argv[])
{
int i,j;
int size[N*N];
int A[N][N];
int sizearr = N*N *sizeof(int);
int *Adefault,*B;
for (i=0; i< N; i++)
{
for(j = 0 ; j<N ; j++ )
{
A[i][j] = ((i*i) +1) * (j+1);
printf("%5d ", A[i][j]);
}
}
printf("\n");
hipMalloc( (void**)&Adefault,sizearr);
hipMalloc( (void**)&B,sizearr);
hipMemcpy( Adefault, A, sizearr, hipMemcpyHostToDevice);
dim3 dimBlock(T,T);
dim3 dimGrid((N+ dimBlock.x - 1)/ dimBlock.x ,(N + dimBlock.y - 1) / dimBlock.y);
vecMatrix<<<dimGrid,dimBlock>>>(Adefault,B);
hipMemcpy(size, B, sizearr, hipMemcpyDeviceToHost);
hipFree(Adefault);
hipFree(B);
printf("Result\n");
for (i=0; i < N * N; i++)
{
printf("%5d ",size[i]);
}
printf("\n");
return 0;
} | .text
.file "cuda4.hip"
.globl _Z24__device_stub__vecMatrixPiS_ # -- Begin function _Z24__device_stub__vecMatrixPiS_
.p2align 4, 0x90
.type _Z24__device_stub__vecMatrixPiS_,@function
_Z24__device_stub__vecMatrixPiS_: # @_Z24__device_stub__vecMatrixPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9vecMatrixPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__vecMatrixPiS_, .Lfunc_end0-_Z24__device_stub__vecMatrixPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2136, %rsp # imm = 0x858
.cfi_def_cfa_offset 2192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 1104(%rsp), %r14
movl $1, %ebp
movl $1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl %ebp, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%r14,%r13,4)
incq %r13
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
addl %ebp, %ebx
cmpq $16, %r13
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $64, %r14
addl %r15d, %ebp
addl $2, %r15d
cmpq $16, %r12
jne .LBB1_1
# %bb.4:
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 1104(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vecMatrixPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $2136, %rsp # imm = 0x858
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vecMatrixPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vecMatrixPiS_,@object # @_Z9vecMatrixPiS_
.section .rodata,"a",@progbits
.globl _Z9vecMatrixPiS_
.p2align 3, 0x0
_Z9vecMatrixPiS_:
.quad _Z24__device_stub__vecMatrixPiS_
.size _Z9vecMatrixPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vecMatrixPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Result"
.size .Lstr, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vecMatrixPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vecMatrixPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vecMatrixPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0.reuse, 0xf, P0 ; /* 0x0000000f0000780c */
/* 0x040fe40000704670 */
/*0090*/ LEA R0, R0, R3, 0x4 ; /* 0x0000000300007211 */
/* 0x000fd600078e20ff */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*0100*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vecMatrixPiS_
.globl _Z9vecMatrixPiS_
.p2align 8
.type _Z9vecMatrixPiS_,@function
_Z9vecMatrixPiS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 16, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vecMatrixPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vecMatrixPiS_, .Lfunc_end0-_Z9vecMatrixPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vecMatrixPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vecMatrixPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014198c_00000000-6_cuda4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9vecMatrixPiS_PiS_
.type _Z30__device_stub__Z9vecMatrixPiS_PiS_, @function
_Z30__device_stub__Z9vecMatrixPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9vecMatrixPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9vecMatrixPiS_PiS_, .-_Z30__device_stub__Z9vecMatrixPiS_PiS_
.globl _Z9vecMatrixPiS_
.type _Z9vecMatrixPiS_, @function
_Z9vecMatrixPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9vecMatrixPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9vecMatrixPiS_, .-_Z9vecMatrixPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5d "
.LC1:
.string "\n"
.LC2:
.string "Result\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2120, %rsp
.cfi_def_cfa_offset 2176
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
leaq 1136(%rsp), %r13
movl $0, %r15d
leaq .LC0(%rip), %r14
.L12:
movl %r15d, %r12d
imull %r15d, %r12d
addl $1, %r12d
leaq -64(%r13), %rbp
movl %r12d, %ebx
.L13:
movl %ebx, 0(%rbp)
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl %r12d, %ebx
addq $4, %rbp
cmpq %r13, %rbp
jne .L13
addl $1, %r15d
addq $64, %r13
cmpl $16, %r15d
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1072(%rsp), %r12
leaq .LC0(%rip), %rbp
.L16:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $2120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9vecMatrixPiS_PiS_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9vecMatrixPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vecMatrixPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda4.hip"
.globl _Z24__device_stub__vecMatrixPiS_ # -- Begin function _Z24__device_stub__vecMatrixPiS_
.p2align 4, 0x90
.type _Z24__device_stub__vecMatrixPiS_,@function
_Z24__device_stub__vecMatrixPiS_: # @_Z24__device_stub__vecMatrixPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9vecMatrixPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__vecMatrixPiS_, .Lfunc_end0-_Z24__device_stub__vecMatrixPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2136, %rsp # imm = 0x858
.cfi_def_cfa_offset 2192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 1104(%rsp), %r14
movl $1, %ebp
movl $1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl %ebp, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%r14,%r13,4)
incq %r13
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
addl %ebp, %ebx
cmpq $16, %r13
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $64, %r14
addl %r15d, %ebp
addl $2, %r15d
cmpq $16, %r12
jne .LBB1_1
# %bb.4:
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 1104(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vecMatrixPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $2136, %rsp # imm = 0x858
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vecMatrixPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vecMatrixPiS_,@object # @_Z9vecMatrixPiS_
.section .rodata,"a",@progbits
.globl _Z9vecMatrixPiS_
.p2align 3, 0x0
_Z9vecMatrixPiS_:
.quad _Z24__device_stub__vecMatrixPiS_
.size _Z9vecMatrixPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vecMatrixPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Result"
.size .Lstr, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vecMatrixPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vecMatrixPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <math.h>
using namespace std;
// 1 byte is stored in 2 pixels
// extract 1 byte per thread
__global__ void decode_per_byte(uchar4* const d_encodedImage, unsigned char* d_encodedData, int numBytes) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int curr_pixel = 2*idx;
if (curr_pixel+1 >= numBytes) {
// We don't have a complete byte, return
return;
}
bool bits[8];
// Let's bring the pixels to local memory
uchar4 pixel1 = d_encodedImage[curr_pixel];
uchar4 pixel2 = d_encodedImage[curr_pixel + 1];
bits[7] = pixel1.x & 1;
bits[6] = pixel1.y & 1;
bits[5] = pixel1.z & 1;
bits[4] = pixel1.w & 1;
bits[3] = pixel2.x & 1;
bits[2] = pixel2.y & 1;
bits[1] = pixel2.z & 1;
bits[0] = pixel2.w & 1;
unsigned char byte = 0;
for(int i = 0; i < 8; ++i) byte |= ((unsigned char)bits[i] << i);
// 0,1 = byte 0
// 2,3 = byte 1
// 4,5 = byte 2
d_encodedData[idx] = (unsigned char)byte;
}
/**
| 11 11 12 16 ; 11 0 13 0 |
| 15 11 14 6 ; 15 14 19 80 | Encoded image (each set of 4 is 1 pixel)
| 13 14 16 21 ; 14 19 10 17 |
| 10 11 10 10 ; 11 11 10 10 |
=
[ 1100 1010 1100 1010 1001 0101 0100 1100] Data file
Taking the last bit from each channel
*/
void decode_parallel(const uchar4* const h_encodedImage,
unsigned char* h_encodedData,
const size_t numRowsSource, const size_t numColsSource)
{
int numBytes = numRowsSource * numColsSource / 2;
unsigned char* d_encodedData;
cudaMalloc(&d_encodedData, (sizeof(unsigned char) * numBytes));
uchar4* d_encodedImage;
cudaMalloc(&d_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource);
cudaMemcpy(d_encodedImage, h_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyHostToDevice);
int threadsPerBlock = 1024;
int totalNumThreads = numBytes;
int numBlocks = ceil((float)totalNumThreads / threadsPerBlock);
decode_per_byte<<<numBlocks, threadsPerBlock>>>(d_encodedImage, d_encodedData, numBytes);
cudaMemcpy(h_encodedData, d_encodedData, sizeof(unsigned char) * numBytes, cudaMemcpyDeviceToHost);
cudaFree(d_encodedData);
} | code for sm_80
Function : _Z15decode_per_byteP6uchar4Phi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fca00078e00ff */
/*0050*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ PRMT R4, R7.reuse, 0x7772, RZ ; /* 0x0000777207047816 */
/* 0x044fe400000000ff */
/*00e0*/ PRMT R5, R7, 0x7773, RZ ; /* 0x0000777307057816 */
/* 0x000fe400000000ff */
/*00f0*/ PRMT R3, R8, 0x7772, RZ ; /* 0x0000777208037816 */
/* 0x008fe200000000ff */
/*0100*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fe200078e00ff */
/*0110*/ PRMT R2, R8, 0x7771, RZ ; /* 0x0000777108027816 */
/* 0x000fc600000000ff */
/*0120*/ IMAD.SHL.U32 R3, R3, 0x20, RZ ; /* 0x0000002003037824 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R6, R4, 0x2, RZ, 0xc0, !PT ; /* 0x0000000204067812 */
/* 0x000fe400078ec0ff */
/*0140*/ PRMT R4, R7.reuse, 0x7771, RZ ; /* 0x0000777107047816 */
/* 0x040fe400000000ff */
/*0150*/ LOP3.LUT R6, R6, 0x1, R5, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fe400078ef805 */
/*0160*/ PRMT R5, R7, 0x7770, RZ ; /* 0x0000777007057816 */
/* 0x000fe200000000ff */
/*0170*/ IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404077824 */
/* 0x000fe200078e00ff */
/*0180*/ PRMT R4, R8, 0x7773, RZ ; /* 0x0000777308047816 */
/* 0x000fc600000000ff */
/*0190*/ IMAD.SHL.U32 R5, R5, 0x8, RZ ; /* 0x0000000805057824 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R6, R6, 0x4, R7, 0xf8, !PT ; /* 0x0000000406067812 */
/* 0x000fe200078ef807 */
/*01b0*/ IMAD.SHL.U32 R4, R4, 0x10, RZ ; /* 0x0000001004047824 */
/* 0x000fc600078e00ff */
/*01c0*/ LOP3.LUT R5, R6, 0x8, R5, 0xf8, !PT ; /* 0x0000000806057812 */
/* 0x000fe200078ef805 */
/*01d0*/ IMAD.SHL.U32 R6, R2, 0x40, RZ ; /* 0x0000004002067824 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fe40007f1e0ff */
/*01f0*/ LOP3.LUT R4, R5, 0x10, R4, 0xf8, !PT ; /* 0x0000001005047812 */
/* 0x000fc800078ef804 */
/*0200*/ LOP3.LUT R3, R4, 0x20, R3, 0xf8, !PT ; /* 0x0000002004037812 */
/* 0x000fe400078ef803 */
/*0210*/ PRMT R4, R8, 0x7770, RZ ; /* 0x0000777008047816 */
/* 0x000fe400000000ff */
/*0220*/ LOP3.LUT R5, R3, 0x40, R6, 0xf8, !PT ; /* 0x0000004003057812 */
/* 0x000fe400078ef806 */
/*0230*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fc600000f0eff */
/*0240*/ IMAD R5, R4, 0x80, R5 ; /* 0x0000008004057824 */
/* 0x000fca00078e0205 */
/*0250*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <math.h>
using namespace std;
// 1 byte is stored in 2 pixels
// extract 1 byte per thread
__global__ void decode_per_byte(uchar4* const d_encodedImage, unsigned char* d_encodedData, int numBytes) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int curr_pixel = 2*idx;
if (curr_pixel+1 >= numBytes) {
// We don't have a complete byte, return
return;
}
bool bits[8];
// Let's bring the pixels to local memory
uchar4 pixel1 = d_encodedImage[curr_pixel];
uchar4 pixel2 = d_encodedImage[curr_pixel + 1];
bits[7] = pixel1.x & 1;
bits[6] = pixel1.y & 1;
bits[5] = pixel1.z & 1;
bits[4] = pixel1.w & 1;
bits[3] = pixel2.x & 1;
bits[2] = pixel2.y & 1;
bits[1] = pixel2.z & 1;
bits[0] = pixel2.w & 1;
unsigned char byte = 0;
for(int i = 0; i < 8; ++i) byte |= ((unsigned char)bits[i] << i);
// 0,1 = byte 0
// 2,3 = byte 1
// 4,5 = byte 2
d_encodedData[idx] = (unsigned char)byte;
}
/**
| 11 11 12 16 ; 11 0 13 0 |
| 15 11 14 6 ; 15 14 19 80 | Encoded image (each set of 4 is 1 pixel)
| 13 14 16 21 ; 14 19 10 17 |
| 10 11 10 10 ; 11 11 10 10 |
=
[ 1100 1010 1100 1010 1001 0101 0100 1100] Data file
Taking the last bit from each channel
*/
void decode_parallel(const uchar4* const h_encodedImage,
unsigned char* h_encodedData,
const size_t numRowsSource, const size_t numColsSource)
{
int numBytes = numRowsSource * numColsSource / 2;
unsigned char* d_encodedData;
cudaMalloc(&d_encodedData, (sizeof(unsigned char) * numBytes));
uchar4* d_encodedImage;
cudaMalloc(&d_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource);
cudaMemcpy(d_encodedImage, h_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyHostToDevice);
int threadsPerBlock = 1024;
int totalNumThreads = numBytes;
int numBlocks = ceil((float)totalNumThreads / threadsPerBlock);
decode_per_byte<<<numBlocks, threadsPerBlock>>>(d_encodedImage, d_encodedData, numBytes);
cudaMemcpy(h_encodedData, d_encodedData, sizeof(unsigned char) * numBytes, cudaMemcpyDeviceToHost);
cudaFree(d_encodedData);
} | .file "tmpxft_0002add6_00000000-6_decode.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
.type _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi, @function
_Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi:
.LFB4064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15decode_per_byteP6uchar4Phi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi, .-_Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
.globl _Z15decode_per_byteP6uchar4Phi
.type _Z15decode_per_byteP6uchar4Phi, @function
_Z15decode_per_byteP6uchar4Phi:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z15decode_per_byteP6uchar4Phi, .-_Z15decode_per_byteP6uchar4Phi
.globl _Z15decode_parallelPK6uchar4Phmm
.type _Z15decode_parallelPK6uchar4Phmm, @function
_Z15decode_parallelPK6uchar4Phmm:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rdx, %rbx
imulq %rcx, %rbx
movq %rbx, %r12
shrq %r12
movl %r12d, %r14d
movslq %r12d, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r14d, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.size _Z15decode_parallelPK6uchar4Phmm, .-_Z15decode_parallelPK6uchar4Phmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z15decode_per_byteP6uchar4Phi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15decode_per_byteP6uchar4Phi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <math.h>
using namespace std;
// 1 byte is stored in 2 pixels
// extract 1 byte per thread
__global__ void decode_per_byte(uchar4* const d_encodedImage, unsigned char* d_encodedData, int numBytes) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int curr_pixel = 2*idx;
if (curr_pixel+1 >= numBytes) {
// We don't have a complete byte, return
return;
}
bool bits[8];
// Let's bring the pixels to local memory
uchar4 pixel1 = d_encodedImage[curr_pixel];
uchar4 pixel2 = d_encodedImage[curr_pixel + 1];
bits[7] = pixel1.x & 1;
bits[6] = pixel1.y & 1;
bits[5] = pixel1.z & 1;
bits[4] = pixel1.w & 1;
bits[3] = pixel2.x & 1;
bits[2] = pixel2.y & 1;
bits[1] = pixel2.z & 1;
bits[0] = pixel2.w & 1;
unsigned char byte = 0;
for(int i = 0; i < 8; ++i) byte |= ((unsigned char)bits[i] << i);
// 0,1 = byte 0
// 2,3 = byte 1
// 4,5 = byte 2
d_encodedData[idx] = (unsigned char)byte;
}
/**
| 11 11 12 16 ; 11 0 13 0 |
| 15 11 14 6 ; 15 14 19 80 | Encoded image (each set of 4 is 1 pixel)
| 13 14 16 21 ; 14 19 10 17 |
| 10 11 10 10 ; 11 11 10 10 |
=
[ 1100 1010 1100 1010 1001 0101 0100 1100] Data file
Taking the last bit from each channel
*/
void decode_parallel(const uchar4* const h_encodedImage,
unsigned char* h_encodedData,
const size_t numRowsSource, const size_t numColsSource)
{
int numBytes = numRowsSource * numColsSource / 2;
unsigned char* d_encodedData;
cudaMalloc(&d_encodedData, (sizeof(unsigned char) * numBytes));
uchar4* d_encodedImage;
cudaMalloc(&d_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource);
cudaMemcpy(d_encodedImage, h_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyHostToDevice);
int threadsPerBlock = 1024;
int totalNumThreads = numBytes;
int numBlocks = ceil((float)totalNumThreads / threadsPerBlock);
decode_per_byte<<<numBlocks, threadsPerBlock>>>(d_encodedImage, d_encodedData, numBytes);
cudaMemcpy(h_encodedData, d_encodedData, sizeof(unsigned char) * numBytes, cudaMemcpyDeviceToHost);
cudaFree(d_encodedData);
} | #include <fstream>
#include <iostream>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
using namespace std;
// 1 byte is stored in 2 pixels
// extract 1 byte per thread
__global__ void decode_per_byte(uchar4* const d_encodedImage, unsigned char* d_encodedData, int numBytes) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int curr_pixel = 2*idx;
if (curr_pixel+1 >= numBytes) {
// We don't have a complete byte, return
return;
}
bool bits[8];
// Let's bring the pixels to local memory
uchar4 pixel1 = d_encodedImage[curr_pixel];
uchar4 pixel2 = d_encodedImage[curr_pixel + 1];
bits[7] = pixel1.x & 1;
bits[6] = pixel1.y & 1;
bits[5] = pixel1.z & 1;
bits[4] = pixel1.w & 1;
bits[3] = pixel2.x & 1;
bits[2] = pixel2.y & 1;
bits[1] = pixel2.z & 1;
bits[0] = pixel2.w & 1;
unsigned char byte = 0;
for(int i = 0; i < 8; ++i) byte |= ((unsigned char)bits[i] << i);
// 0,1 = byte 0
// 2,3 = byte 1
// 4,5 = byte 2
d_encodedData[idx] = (unsigned char)byte;
}
/**
| 11 11 12 16 ; 11 0 13 0 |
| 15 11 14 6 ; 15 14 19 80 | Encoded image (each set of 4 is 1 pixel)
| 13 14 16 21 ; 14 19 10 17 |
| 10 11 10 10 ; 11 11 10 10 |
=
[ 1100 1010 1100 1010 1001 0101 0100 1100] Data file
Taking the last bit from each channel
*/
void decode_parallel(const uchar4* const h_encodedImage,
unsigned char* h_encodedData,
const size_t numRowsSource, const size_t numColsSource)
{
int numBytes = numRowsSource * numColsSource / 2;
unsigned char* d_encodedData;
hipMalloc(&d_encodedData, (sizeof(unsigned char) * numBytes));
uchar4* d_encodedImage;
hipMalloc(&d_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource);
hipMemcpy(d_encodedImage, h_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyHostToDevice);
int threadsPerBlock = 1024;
int totalNumThreads = numBytes;
int numBlocks = ceil((float)totalNumThreads / threadsPerBlock);
decode_per_byte<<<numBlocks, threadsPerBlock>>>(d_encodedImage, d_encodedData, numBytes);
hipMemcpy(h_encodedData, d_encodedData, sizeof(unsigned char) * numBytes, hipMemcpyDeviceToHost);
hipFree(d_encodedData);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
using namespace std;
// 1 byte is stored in 2 pixels
// extract 1 byte per thread
__global__ void decode_per_byte(uchar4* const d_encodedImage, unsigned char* d_encodedData, int numBytes) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int curr_pixel = 2*idx;
if (curr_pixel+1 >= numBytes) {
// We don't have a complete byte, return
return;
}
bool bits[8];
// Let's bring the pixels to local memory
uchar4 pixel1 = d_encodedImage[curr_pixel];
uchar4 pixel2 = d_encodedImage[curr_pixel + 1];
bits[7] = pixel1.x & 1;
bits[6] = pixel1.y & 1;
bits[5] = pixel1.z & 1;
bits[4] = pixel1.w & 1;
bits[3] = pixel2.x & 1;
bits[2] = pixel2.y & 1;
bits[1] = pixel2.z & 1;
bits[0] = pixel2.w & 1;
unsigned char byte = 0;
for(int i = 0; i < 8; ++i) byte |= ((unsigned char)bits[i] << i);
// 0,1 = byte 0
// 2,3 = byte 1
// 4,5 = byte 2
d_encodedData[idx] = (unsigned char)byte;
}
/**
| 11 11 12 16 ; 11 0 13 0 |
| 15 11 14 6 ; 15 14 19 80 | Encoded image (each set of 4 is 1 pixel)
| 13 14 16 21 ; 14 19 10 17 |
| 10 11 10 10 ; 11 11 10 10 |
=
[ 1100 1010 1100 1010 1001 0101 0100 1100] Data file
Taking the last bit from each channel
*/
void decode_parallel(const uchar4* const h_encodedImage,
unsigned char* h_encodedData,
const size_t numRowsSource, const size_t numColsSource)
{
int numBytes = numRowsSource * numColsSource / 2;
unsigned char* d_encodedData;
hipMalloc(&d_encodedData, (sizeof(unsigned char) * numBytes));
uchar4* d_encodedImage;
hipMalloc(&d_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource);
hipMemcpy(d_encodedImage, h_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyHostToDevice);
int threadsPerBlock = 1024;
int totalNumThreads = numBytes;
int numBlocks = ceil((float)totalNumThreads / threadsPerBlock);
decode_per_byte<<<numBlocks, threadsPerBlock>>>(d_encodedImage, d_encodedData, numBytes);
hipMemcpy(h_encodedData, d_encodedData, sizeof(unsigned char) * numBytes, hipMemcpyDeviceToHost);
hipFree(d_encodedData);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.globl _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.p2align 8
.type _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi,@function
_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshlrev_b32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, 1, v4
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_clause 0x7
global_load_u8 v0, v[4:5], off
global_load_u8 v6, v[4:5], off offset:1
global_load_u8 v7, v[4:5], off offset:2
global_load_u8 v8, v[2:3], off offset:2
global_load_u8 v9, v[2:3], off
global_load_u8 v4, v[4:5], off offset:3
global_load_u8 v5, v[2:3], off offset:1
global_load_u8 v2, v[2:3], off offset:3
s_mov_b64 s[2:3], 0
s_waitcnt vmcnt(7)
v_and_b32_e32 v0, 1, v0
s_waitcnt vmcnt(6)
v_and_b32_e32 v3, 1, v6
s_waitcnt vmcnt(5)
v_and_b32_e32 v6, 1, v7
s_waitcnt vmcnt(4)
v_and_b32_e32 v7, 1, v8
s_waitcnt vmcnt(3)
v_and_b32_e32 v8, 1, v9
s_waitcnt vmcnt(2)
v_and_b32_e32 v4, 1, v4
s_waitcnt vmcnt(1)
v_and_b32_e32 v5, 1, v5
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_lshlrev_b16 v7, 8, v7
v_lshlrev_b16 v8, 8, v8
v_lshlrev_b16 v6, 8, v6
v_lshlrev_b16 v0, 8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v2, v2, v7
v_or_b32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, v4, v6
v_or_b32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v2, 0xffff, v2
v_lshlrev_b32_e32 v3, 16, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v4, 0xffff, v4
v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v5, 16, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v2, v2, v3
v_or_b32_e32 v3, v4, v5
.LBB0_2:
s_lshl_b32 s4, s2, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_lshrrev_b64 v[4:5], s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, s2, v4
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 8
v_or_b32_e32 v0, v0, v4
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, .Lfunc_end0-_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
using namespace std;
// 1 byte is stored in 2 pixels
// extract 1 byte per thread
__global__ void decode_per_byte(uchar4* const d_encodedImage, unsigned char* d_encodedData, int numBytes) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int curr_pixel = 2*idx;
if (curr_pixel+1 >= numBytes) {
// We don't have a complete byte, return
return;
}
bool bits[8];
// Let's bring the pixels to local memory
uchar4 pixel1 = d_encodedImage[curr_pixel];
uchar4 pixel2 = d_encodedImage[curr_pixel + 1];
bits[7] = pixel1.x & 1;
bits[6] = pixel1.y & 1;
bits[5] = pixel1.z & 1;
bits[4] = pixel1.w & 1;
bits[3] = pixel2.x & 1;
bits[2] = pixel2.y & 1;
bits[1] = pixel2.z & 1;
bits[0] = pixel2.w & 1;
unsigned char byte = 0;
for(int i = 0; i < 8; ++i) byte |= ((unsigned char)bits[i] << i);
// 0,1 = byte 0
// 2,3 = byte 1
// 4,5 = byte 2
d_encodedData[idx] = (unsigned char)byte;
}
/**
| 11 11 12 16 ; 11 0 13 0 |
| 15 11 14 6 ; 15 14 19 80 | Encoded image (each set of 4 is 1 pixel)
| 13 14 16 21 ; 14 19 10 17 |
| 10 11 10 10 ; 11 11 10 10 |
=
[ 1100 1010 1100 1010 1001 0101 0100 1100] Data file
Taking the last bit from each channel
*/
void decode_parallel(const uchar4* const h_encodedImage,
unsigned char* h_encodedData,
const size_t numRowsSource, const size_t numColsSource)
{
int numBytes = numRowsSource * numColsSource / 2;
unsigned char* d_encodedData;
hipMalloc(&d_encodedData, (sizeof(unsigned char) * numBytes));
uchar4* d_encodedImage;
hipMalloc(&d_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource);
hipMemcpy(d_encodedImage, h_encodedImage, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyHostToDevice);
int threadsPerBlock = 1024;
int totalNumThreads = numBytes;
int numBlocks = ceil((float)totalNumThreads / threadsPerBlock);
decode_per_byte<<<numBlocks, threadsPerBlock>>>(d_encodedImage, d_encodedData, numBytes);
hipMemcpy(h_encodedData, d_encodedData, sizeof(unsigned char) * numBytes, hipMemcpyDeviceToHost);
hipFree(d_encodedData);
} | .text
.file "decode.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi # -- Begin function _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.p2align 4, 0x90
.type _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi,@function
_Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi: # @_Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi, .Lfunc_end0-_Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.p2align 4, 0x90
.type _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm,@function
_Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm: # @_Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r12
imulq %rcx, %r15
movq %r15, %r13
shrq %r13
movslq %r13d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
shlq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r14d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r13d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm, .Lfunc_end1-_Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi,@object # @_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.section .rodata,"a",@progbits
.globl _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.p2align 3, 0x0
_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi:
.quad _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.size _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15decode_per_byteP6uchar4Phi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fca00078e00ff */
/*0050*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ PRMT R4, R7.reuse, 0x7772, RZ ; /* 0x0000777207047816 */
/* 0x044fe400000000ff */
/*00e0*/ PRMT R5, R7, 0x7773, RZ ; /* 0x0000777307057816 */
/* 0x000fe400000000ff */
/*00f0*/ PRMT R3, R8, 0x7772, RZ ; /* 0x0000777208037816 */
/* 0x008fe200000000ff */
/*0100*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fe200078e00ff */
/*0110*/ PRMT R2, R8, 0x7771, RZ ; /* 0x0000777108027816 */
/* 0x000fc600000000ff */
/*0120*/ IMAD.SHL.U32 R3, R3, 0x20, RZ ; /* 0x0000002003037824 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R6, R4, 0x2, RZ, 0xc0, !PT ; /* 0x0000000204067812 */
/* 0x000fe400078ec0ff */
/*0140*/ PRMT R4, R7.reuse, 0x7771, RZ ; /* 0x0000777107047816 */
/* 0x040fe400000000ff */
/*0150*/ LOP3.LUT R6, R6, 0x1, R5, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fe400078ef805 */
/*0160*/ PRMT R5, R7, 0x7770, RZ ; /* 0x0000777007057816 */
/* 0x000fe200000000ff */
/*0170*/ IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404077824 */
/* 0x000fe200078e00ff */
/*0180*/ PRMT R4, R8, 0x7773, RZ ; /* 0x0000777308047816 */
/* 0x000fc600000000ff */
/*0190*/ IMAD.SHL.U32 R5, R5, 0x8, RZ ; /* 0x0000000805057824 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R6, R6, 0x4, R7, 0xf8, !PT ; /* 0x0000000406067812 */
/* 0x000fe200078ef807 */
/*01b0*/ IMAD.SHL.U32 R4, R4, 0x10, RZ ; /* 0x0000001004047824 */
/* 0x000fc600078e00ff */
/*01c0*/ LOP3.LUT R5, R6, 0x8, R5, 0xf8, !PT ; /* 0x0000000806057812 */
/* 0x000fe200078ef805 */
/*01d0*/ IMAD.SHL.U32 R6, R2, 0x40, RZ ; /* 0x0000004002067824 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fe40007f1e0ff */
/*01f0*/ LOP3.LUT R4, R5, 0x10, R4, 0xf8, !PT ; /* 0x0000001005047812 */
/* 0x000fc800078ef804 */
/*0200*/ LOP3.LUT R3, R4, 0x20, R3, 0xf8, !PT ; /* 0x0000002004037812 */
/* 0x000fe400078ef803 */
/*0210*/ PRMT R4, R8, 0x7770, RZ ; /* 0x0000777008047816 */
/* 0x000fe400000000ff */
/*0220*/ LOP3.LUT R5, R3, 0x40, R6, 0xf8, !PT ; /* 0x0000004003057812 */
/* 0x000fe400078ef806 */
/*0230*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fc600000f0eff */
/*0240*/ IMAD R5, R4, 0x80, R5 ; /* 0x0000008004057824 */
/* 0x000fca00078e0205 */
/*0250*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.globl _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.p2align 8
.type _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi,@function
_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshlrev_b32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, 1, v4
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_clause 0x7
global_load_u8 v0, v[4:5], off
global_load_u8 v6, v[4:5], off offset:1
global_load_u8 v7, v[4:5], off offset:2
global_load_u8 v8, v[2:3], off offset:2
global_load_u8 v9, v[2:3], off
global_load_u8 v4, v[4:5], off offset:3
global_load_u8 v5, v[2:3], off offset:1
global_load_u8 v2, v[2:3], off offset:3
s_mov_b64 s[2:3], 0
s_waitcnt vmcnt(7)
v_and_b32_e32 v0, 1, v0
s_waitcnt vmcnt(6)
v_and_b32_e32 v3, 1, v6
s_waitcnt vmcnt(5)
v_and_b32_e32 v6, 1, v7
s_waitcnt vmcnt(4)
v_and_b32_e32 v7, 1, v8
s_waitcnt vmcnt(3)
v_and_b32_e32 v8, 1, v9
s_waitcnt vmcnt(2)
v_and_b32_e32 v4, 1, v4
s_waitcnt vmcnt(1)
v_and_b32_e32 v5, 1, v5
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 1, v2
v_lshlrev_b16 v7, 8, v7
v_lshlrev_b16 v8, 8, v8
v_lshlrev_b16 v6, 8, v6
v_lshlrev_b16 v0, 8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v2, v2, v7
v_or_b32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, v4, v6
v_or_b32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v2, 0xffff, v2
v_lshlrev_b32_e32 v3, 16, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v4, 0xffff, v4
v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v5, 16, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v2, v2, v3
v_or_b32_e32 v3, v4, v5
.LBB0_2:
s_lshl_b32 s4, s2, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_lshrrev_b64 v[4:5], s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, s2, v4
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 8
v_or_b32_e32 v0, v0, v4
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, .Lfunc_end0-_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002add6_00000000-6_decode.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
.type _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi, @function
_Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi:
.LFB4064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15decode_per_byteP6uchar4Phi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi, .-_Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
.globl _Z15decode_per_byteP6uchar4Phi
.type _Z15decode_per_byteP6uchar4Phi, @function
_Z15decode_per_byteP6uchar4Phi:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z15decode_per_byteP6uchar4Phi, .-_Z15decode_per_byteP6uchar4Phi
.globl _Z15decode_parallelPK6uchar4Phmm
.type _Z15decode_parallelPK6uchar4Phmm, @function
_Z15decode_parallelPK6uchar4Phmm:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rdx, %rbx
imulq %rcx, %rbx
movq %rbx, %r12
shrq %r12
movl %r12d, %r14d
movslq %r12d, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r14d, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z15decode_per_byteP6uchar4PhiP6uchar4Phi
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.size _Z15decode_parallelPK6uchar4Phmm, .-_Z15decode_parallelPK6uchar4Phmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z15decode_per_byteP6uchar4Phi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15decode_per_byteP6uchar4Phi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "decode.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi # -- Begin function _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.p2align 4, 0x90
.type _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi,@function
_Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi: # @_Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi, .Lfunc_end0-_Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.p2align 4, 0x90
.type _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm,@function
_Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm: # @_Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r12
imulq %rcx, %r15
movq %r15, %r13
shrq %r13
movslq %r13d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
shlq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r14d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r13d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm, .Lfunc_end1-_Z15decode_parallelPK15HIP_vector_typeIhLj4EEPhmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi,@object # @_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.section .rodata,"a",@progbits
.globl _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.p2align 3, 0x0
_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi:
.quad _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.size _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15decode_per_byteP15HIP_vector_typeIhLj4EEPhi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
__device__ int cracks(char * passcrack){
char pswd1[]="RD1234";
char pswd2[]="MN4567";
char pswd3[]="SS9867";
char pswd4[]="CD5493";
char *m1 = passcrack;
char *m2 = passcrack;
char *m3 = passcrack;
char *m4 = passcrack;
char *p1 = pswd1;
char *p2 = pswd2;
char *p3 = pswd3;
char *p4 = pswd4;
while(*m1 == *p1){
if(*m1 == '\0'){
return 1;
}
m1++;
p1++;
}
while(*m2 == *p2){
if(*m2 == '\0'){
return 1;
}
m2++;
p2++;
}
while(*m3 == *p3){
if(*m3 == '\0'){
return 1;
}
m3++;
p3++;
}
while(*m4 == *p4){
if(*m4 == '\0'){
return 1;
}
m4++;
p4++;
}
return 0;
}
__global__ void cracks() {
char word[26] = {'A','B','C','D','E','F','G','H','I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
char numb[10] = {'0','1','2','3','4','5','6','7','8','9'};
char passcrack[7];
passcrack[6] = '\0';
int m, n, o, p;
for(m=0;m<10;m++){
for(n=0; n<10; n++){
for(o=0; o<10; o++){
for(p=0; p<10; p++){
passcrack[0] = word[blockIdx.x];
passcrack[1] = word[threadIdx.x];
passcrack[2] = numb[m];
passcrack[3] = numb[n];
passcrack[4] = numb[o];
passcrack[5] = numb[p];
if(cracks(passcrack)){
printf("Password successfully cracked: %s\n", passcrack);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 )
{
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main(int argc, char *argv[])
{
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cracks <<<26, 26>>>();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .file "tmpxft_00041994_00000000-6_Password024.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6cracksPc
.type _Z6cracksPc, @function
_Z6cracksPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6cracksPc, .-_Z6cracksPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2058:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6cracksvv
.type _Z24__device_stub__Z6cracksvv, @function
_Z24__device_stub__Z6cracksvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6cracksv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6cracksvv, .-_Z24__device_stub__Z6cracksvv
.globl _Z6cracksv
.type _Z6cracksv, @function
_Z6cracksv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6cracksvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6cracksv, .-_Z6cracksv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6cracksvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6cracksv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6cracksv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
__device__ int cracks(char * passcrack){
char pswd1[]="RD1234";
char pswd2[]="MN4567";
char pswd3[]="SS9867";
char pswd4[]="CD5493";
char *m1 = passcrack;
char *m2 = passcrack;
char *m3 = passcrack;
char *m4 = passcrack;
char *p1 = pswd1;
char *p2 = pswd2;
char *p3 = pswd3;
char *p4 = pswd4;
while(*m1 == *p1){
if(*m1 == '\0'){
return 1;
}
m1++;
p1++;
}
while(*m2 == *p2){
if(*m2 == '\0'){
return 1;
}
m2++;
p2++;
}
while(*m3 == *p3){
if(*m3 == '\0'){
return 1;
}
m3++;
p3++;
}
while(*m4 == *p4){
if(*m4 == '\0'){
return 1;
}
m4++;
p4++;
}
return 0;
}
__global__ void cracks() {
char word[26] = {'A','B','C','D','E','F','G','H','I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
char numb[10] = {'0','1','2','3','4','5','6','7','8','9'};
char passcrack[7];
passcrack[6] = '\0';
int m, n, o, p;
for(m=0;m<10;m++){
for(n=0; n<10; n++){
for(o=0; o<10; o++){
for(p=0; p<10; p++){
passcrack[0] = word[blockIdx.x];
passcrack[1] = word[threadIdx.x];
passcrack[2] = numb[m];
passcrack[3] = numb[n];
passcrack[4] = numb[o];
passcrack[5] = numb[p];
if(cracks(passcrack)){
printf("Password successfully cracked: %s\n", passcrack);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 )
{
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main(int argc, char *argv[])
{
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cracks <<<26, 26>>>();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__device__ int cracks(char * passcrack){
char pswd1[]="RD1234";
char pswd2[]="MN4567";
char pswd3[]="SS9867";
char pswd4[]="CD5493";
char *m1 = passcrack;
char *m2 = passcrack;
char *m3 = passcrack;
char *m4 = passcrack;
char *p1 = pswd1;
char *p2 = pswd2;
char *p3 = pswd3;
char *p4 = pswd4;
while(*m1 == *p1){
if(*m1 == '\0'){
return 1;
}
m1++;
p1++;
}
while(*m2 == *p2){
if(*m2 == '\0'){
return 1;
}
m2++;
p2++;
}
while(*m3 == *p3){
if(*m3 == '\0'){
return 1;
}
m3++;
p3++;
}
while(*m4 == *p4){
if(*m4 == '\0'){
return 1;
}
m4++;
p4++;
}
return 0;
}
__global__ void cracks() {
char word[26] = {'A','B','C','D','E','F','G','H','I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
char numb[10] = {'0','1','2','3','4','5','6','7','8','9'};
char passcrack[7];
passcrack[6] = '\0';
int m, n, o, p;
for(m=0;m<10;m++){
for(n=0; n<10; n++){
for(o=0; o<10; o++){
for(p=0; p<10; p++){
passcrack[0] = word[blockIdx.x];
passcrack[1] = word[threadIdx.x];
passcrack[2] = numb[m];
passcrack[3] = numb[n];
passcrack[4] = numb[o];
passcrack[5] = numb[p];
if(cracks(passcrack)){
printf("Password successfully cracked: %s\n", passcrack);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 )
{
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main(int argc, char *argv[])
{
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cracks <<<26, 26>>>();
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__device__ int cracks(char * passcrack){
char pswd1[]="RD1234";
char pswd2[]="MN4567";
char pswd3[]="SS9867";
char pswd4[]="CD5493";
char *m1 = passcrack;
char *m2 = passcrack;
char *m3 = passcrack;
char *m4 = passcrack;
char *p1 = pswd1;
char *p2 = pswd2;
char *p3 = pswd3;
char *p4 = pswd4;
while(*m1 == *p1){
if(*m1 == '\0'){
return 1;
}
m1++;
p1++;
}
while(*m2 == *p2){
if(*m2 == '\0'){
return 1;
}
m2++;
p2++;
}
while(*m3 == *p3){
if(*m3 == '\0'){
return 1;
}
m3++;
p3++;
}
while(*m4 == *p4){
if(*m4 == '\0'){
return 1;
}
m4++;
p4++;
}
return 0;
}
__global__ void cracks() {
char word[26] = {'A','B','C','D','E','F','G','H','I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
char numb[10] = {'0','1','2','3','4','5','6','7','8','9'};
char passcrack[7];
passcrack[6] = '\0';
int m, n, o, p;
for(m=0;m<10;m++){
for(n=0; n<10; n++){
for(o=0; o<10; o++){
for(p=0; p<10; p++){
passcrack[0] = word[blockIdx.x];
passcrack[1] = word[threadIdx.x];
passcrack[2] = numb[m];
passcrack[3] = numb[n];
passcrack[4] = numb[o];
passcrack[5] = numb[p];
if(cracks(passcrack)){
printf("Password successfully cracked: %s\n", passcrack);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 )
{
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main(int argc, char *argv[])
{
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cracks <<<26, 26>>>();
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .text
.file "Password024.hip"
.globl _Z21__device_stub__cracksv # -- Begin function _Z21__device_stub__cracksv
.p2align 4, 0x90
.type _Z21__device_stub__cracksv,@function
_Z21__device_stub__cracksv: # @_Z21__device_stub__cracksv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6cracksv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__cracksv, .Lfunc_end0-_Z21__device_stub__cracksv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6cracksv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6cracksv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6cracksv,@object # @_Z6cracksv
.section .rodata,"a",@progbits
.globl _Z6cracksv
.p2align 3, 0x0
_Z6cracksv:
.quad _Z21__device_stub__cracksv
.size _Z6cracksv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6cracksv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__cracksv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6cracksv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041994_00000000-6_Password024.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6cracksPc
.type _Z6cracksPc, @function
_Z6cracksPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6cracksPc, .-_Z6cracksPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2058:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6cracksvv
.type _Z24__device_stub__Z6cracksvv, @function
_Z24__device_stub__Z6cracksvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6cracksv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6cracksvv, .-_Z24__device_stub__Z6cracksvv
.globl _Z6cracksv
.type _Z6cracksv, @function
_Z6cracksv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6cracksvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6cracksv, .-_Z6cracksv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6cracksvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6cracksv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6cracksv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Password024.hip"
.globl _Z21__device_stub__cracksv # -- Begin function _Z21__device_stub__cracksv
.p2align 4, 0x90
.type _Z21__device_stub__cracksv,@function
_Z21__device_stub__cracksv: # @_Z21__device_stub__cracksv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6cracksv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__cracksv, .Lfunc_end0-_Z21__device_stub__cracksv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6cracksv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6cracksv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6cracksv,@object # @_Z6cracksv
.section .rodata,"a",@progbits
.globl _Z6cracksv
.p2align 3, 0x0
_Z6cracksv:
.quad _Z21__device_stub__cracksv
.size _Z6cracksv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6cracksv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__cracksv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6cracksv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addArray( float *d_a, float *d_b, float *d_c, int size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i >= size)
{
return;
}
d_c[i] = d_a[i] + d_b[i];
} | code for sm_80
Function : _Z8addArrayPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addArray( float *d_a, float *d_b, float *d_c, int size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i >= size)
{
return;
}
d_c[i] = d_a[i] + d_b[i];
} | .file "tmpxft_00144e02_00000000-6_addArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8addArrayPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i
.globl _Z8addArrayPfS_S_i
.type _Z8addArrayPfS_S_i, @function
_Z8addArrayPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8addArrayPfS_S_i, .-_Z8addArrayPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8addArrayPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8addArrayPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addArray( float *d_a, float *d_b, float *d_c, int size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i >= size)
{
return;
}
d_c[i] = d_a[i] + d_b[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addArray( float *d_a, float *d_b, float *d_c, int size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i >= size)
{
return;
}
d_c[i] = d_a[i] + d_b[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addArray( float *d_a, float *d_b, float *d_c, int size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i >= size)
{
return;
}
d_c[i] = d_a[i] + d_b[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8addArrayPfS_S_i
.globl _Z8addArrayPfS_S_i
.p2align 8
.type _Z8addArrayPfS_S_i,@function
_Z8addArrayPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8addArrayPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8addArrayPfS_S_i, .Lfunc_end0-_Z8addArrayPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8addArrayPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8addArrayPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addArray( float *d_a, float *d_b, float *d_c, int size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i >= size)
{
return;
}
d_c[i] = d_a[i] + d_b[i];
} | .text
.file "addArray.hip"
.globl _Z23__device_stub__addArrayPfS_S_i # -- Begin function _Z23__device_stub__addArrayPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__addArrayPfS_S_i,@function
_Z23__device_stub__addArrayPfS_S_i: # @_Z23__device_stub__addArrayPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8addArrayPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__addArrayPfS_S_i, .Lfunc_end0-_Z23__device_stub__addArrayPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8addArrayPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8addArrayPfS_S_i,@object # @_Z8addArrayPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8addArrayPfS_S_i
.p2align 3, 0x0
_Z8addArrayPfS_S_i:
.quad _Z23__device_stub__addArrayPfS_S_i
.size _Z8addArrayPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8addArrayPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__addArrayPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8addArrayPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8addArrayPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8addArrayPfS_S_i
.globl _Z8addArrayPfS_S_i
.p2align 8
.type _Z8addArrayPfS_S_i,@function
_Z8addArrayPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8addArrayPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8addArrayPfS_S_i, .Lfunc_end0-_Z8addArrayPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8addArrayPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8addArrayPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144e02_00000000-6_addArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8addArrayPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i
.globl _Z8addArrayPfS_S_i
.type _Z8addArrayPfS_S_i, @function
_Z8addArrayPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8addArrayPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8addArrayPfS_S_i, .-_Z8addArrayPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8addArrayPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8addArrayPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addArray.hip"
.globl _Z23__device_stub__addArrayPfS_S_i # -- Begin function _Z23__device_stub__addArrayPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__addArrayPfS_S_i,@function
_Z23__device_stub__addArrayPfS_S_i: # @_Z23__device_stub__addArrayPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8addArrayPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__addArrayPfS_S_i, .Lfunc_end0-_Z23__device_stub__addArrayPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8addArrayPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8addArrayPfS_S_i,@object # @_Z8addArrayPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8addArrayPfS_S_i
.p2align 3, 0x0
_Z8addArrayPfS_S_i:
.quad _Z23__device_stub__addArrayPfS_S_i
.size _Z8addArrayPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8addArrayPfS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__addArrayPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8addArrayPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 1024*4
// Device Kernel
//host Function
__global__ void amean(float *A, float *S)
{
//holds intermediates in shared memory reduction
__shared__ int sdata[N];
int tid=threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid]=A[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid==0)
S[blockIdx.x]=sdata[0];
} | code for sm_80
Function : _Z5ameanPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ F2I.TRUNC.NTZ R0, R2 ; /* 0x0000000200007305 */
/* 0x004e24000020f100 */
/*00d0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0011e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P1 BRA 0x1c0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0130*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0140*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0150*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0160*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0170*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0180*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01b0*/ @P1 BRA 0x120 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01d0*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e220000000800 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fe200078e0003 */
/*0200*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x001e280000201400 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 1024*4
// Device Kernel
//host Function
__global__ void amean(float *A, float *S)
{
//holds intermediates in shared memory reduction
__shared__ int sdata[N];
int tid=threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid]=A[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid==0)
S[blockIdx.x]=sdata[0];
} | .file "tmpxft_000a70e4_00000000-6_amean.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5ameanPfS_PfS_
.type _Z26__device_stub__Z5ameanPfS_PfS_, @function
_Z26__device_stub__Z5ameanPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5ameanPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z5ameanPfS_PfS_, .-_Z26__device_stub__Z5ameanPfS_PfS_
.globl _Z5ameanPfS_
.type _Z5ameanPfS_, @function
_Z5ameanPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5ameanPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5ameanPfS_, .-_Z5ameanPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5ameanPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5ameanPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 1024*4
// Device Kernel
//host Function
__global__ void amean(float *A, float *S)
{
//holds intermediates in shared memory reduction
__shared__ int sdata[N];
int tid=threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid]=A[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid==0)
S[blockIdx.x]=sdata[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1024*4
// Device Kernel
//host Function
__global__ void amean(float *A, float *S)
{
//holds intermediates in shared memory reduction
__shared__ int sdata[N];
int tid=threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid]=A[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid==0)
S[blockIdx.x]=sdata[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1024*4
// Device Kernel
//host Function
__global__ void amean(float *A, float *S)
{
//holds intermediates in shared memory reduction
__shared__ int sdata[N];
int tid=threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid]=A[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid==0)
S[blockIdx.x]=sdata[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5ameanPfS_
.globl _Z5ameanPfS_
.p2align 8
.type _Z5ameanPfS_,@function
_Z5ameanPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cvt_f32_i32_e32 v1, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5ameanPfS_
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5ameanPfS_, .Lfunc_end0-_Z5ameanPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5ameanPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5ameanPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1024*4
// Device Kernel
//host Function
__global__ void amean(float *A, float *S)
{
//holds intermediates in shared memory reduction
__shared__ int sdata[N];
int tid=threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid]=A[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid==0)
S[blockIdx.x]=sdata[0];
} | .text
.file "amean.hip"
.globl _Z20__device_stub__ameanPfS_ # -- Begin function _Z20__device_stub__ameanPfS_
.p2align 4, 0x90
.type _Z20__device_stub__ameanPfS_,@function
_Z20__device_stub__ameanPfS_: # @_Z20__device_stub__ameanPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5ameanPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__ameanPfS_, .Lfunc_end0-_Z20__device_stub__ameanPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5ameanPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5ameanPfS_,@object # @_Z5ameanPfS_
.section .rodata,"a",@progbits
.globl _Z5ameanPfS_
.p2align 3, 0x0
_Z5ameanPfS_:
.quad _Z20__device_stub__ameanPfS_
.size _Z5ameanPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5ameanPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__ameanPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5ameanPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5ameanPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ F2I.TRUNC.NTZ R0, R2 ; /* 0x0000000200007305 */
/* 0x004e24000020f100 */
/*00d0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0011e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P1 BRA 0x1c0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0130*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0140*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0150*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0160*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0170*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0180*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01b0*/ @P1 BRA 0x120 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01d0*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e220000000800 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fe200078e0003 */
/*0200*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x001e280000201400 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5ameanPfS_
.globl _Z5ameanPfS_
.p2align 8
.type _Z5ameanPfS_,@function
_Z5ameanPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cvt_f32_i32_e32 v1, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5ameanPfS_
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5ameanPfS_, .Lfunc_end0-_Z5ameanPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5ameanPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5ameanPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a70e4_00000000-6_amean.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5ameanPfS_PfS_
.type _Z26__device_stub__Z5ameanPfS_PfS_, @function
_Z26__device_stub__Z5ameanPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5ameanPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z5ameanPfS_PfS_, .-_Z26__device_stub__Z5ameanPfS_PfS_
.globl _Z5ameanPfS_
.type _Z5ameanPfS_, @function
_Z5ameanPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5ameanPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5ameanPfS_, .-_Z5ameanPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5ameanPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5ameanPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "amean.hip"
.globl _Z20__device_stub__ameanPfS_ # -- Begin function _Z20__device_stub__ameanPfS_
.p2align 4, 0x90
.type _Z20__device_stub__ameanPfS_,@function
_Z20__device_stub__ameanPfS_: # @_Z20__device_stub__ameanPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5ameanPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__ameanPfS_, .Lfunc_end0-_Z20__device_stub__ameanPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5ameanPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5ameanPfS_,@object # @_Z5ameanPfS_
.section .rodata,"a",@progbits
.globl _Z5ameanPfS_
.p2align 3, 0x0
_Z5ameanPfS_:
.quad _Z20__device_stub__ameanPfS_
.size _Z5ameanPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5ameanPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__ameanPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5ameanPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // This is a generated file, do not edit it!
#pragma once
#include <stdint.h>
typedef struct DataPoint DataPoint;
typedef struct Node Node;
typedef struct DecisionLearnerContext {
DataPoint *DataPoints;
int32_t NumDataPoints;
float TotalWeight;
int32_t NumAttributeAxes;
int32_t NumCategoricalAxes;
int32_t *DataPointIds;
Node *Nodes;
int32_t CurrentLevel;
int32_t *OpenNodeIds;
int32_t NumOpenNodes;
int32_t *NextOpenNodeIds;
int32_t NumNextOpenNodes;
int32_t MaxOpenNodes;
} DecisionLearnerContext; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This is a generated file, do not edit it!
#pragma once
#include <stdint.h>
typedef struct DataPoint DataPoint;
typedef struct Node Node;
typedef struct DecisionLearnerContext {
DataPoint *DataPoints;
int32_t NumDataPoints;
float TotalWeight;
int32_t NumAttributeAxes;
int32_t NumCategoricalAxes;
int32_t *DataPointIds;
Node *Nodes;
int32_t CurrentLevel;
int32_t *OpenNodeIds;
int32_t NumOpenNodes;
int32_t *NextOpenNodeIds;
int32_t NumNextOpenNodes;
int32_t MaxOpenNodes;
} DecisionLearnerContext; | .file "tmpxft_0012e490_00000000-6_GPUDecisionLearnerContext.generated.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This is a generated file, do not edit it!
#pragma once
#include <stdint.h>
typedef struct DataPoint DataPoint;
typedef struct Node Node;
typedef struct DecisionLearnerContext {
DataPoint *DataPoints;
int32_t NumDataPoints;
float TotalWeight;
int32_t NumAttributeAxes;
int32_t NumCategoricalAxes;
int32_t *DataPointIds;
Node *Nodes;
int32_t CurrentLevel;
int32_t *OpenNodeIds;
int32_t NumOpenNodes;
int32_t *NextOpenNodeIds;
int32_t NumNextOpenNodes;
int32_t MaxOpenNodes;
} DecisionLearnerContext; | // This is a generated file, do not edit it!
#pragma once
#include <hip/hip_runtime.h>
#include <stdint.h>
typedef struct DataPoint DataPoint;
typedef struct Node Node;
typedef struct DecisionLearnerContext {
DataPoint *DataPoints;
int32_t NumDataPoints;
float TotalWeight;
int32_t NumAttributeAxes;
int32_t NumCategoricalAxes;
int32_t *DataPointIds;
Node *Nodes;
int32_t CurrentLevel;
int32_t *OpenNodeIds;
int32_t NumOpenNodes;
int32_t *NextOpenNodeIds;
int32_t NumNextOpenNodes;
int32_t MaxOpenNodes;
} DecisionLearnerContext; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // This is a generated file, do not edit it!
#pragma once
#include <hip/hip_runtime.h>
#include <stdint.h>
typedef struct DataPoint DataPoint;
typedef struct Node Node;
typedef struct DecisionLearnerContext {
DataPoint *DataPoints;
int32_t NumDataPoints;
float TotalWeight;
int32_t NumAttributeAxes;
int32_t NumCategoricalAxes;
int32_t *DataPointIds;
Node *Nodes;
int32_t CurrentLevel;
int32_t *OpenNodeIds;
int32_t NumOpenNodes;
int32_t *NextOpenNodeIds;
int32_t NumNextOpenNodes;
int32_t MaxOpenNodes;
} DecisionLearnerContext; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // This is a generated file, do not edit it!
#pragma once
#include <hip/hip_runtime.h>
#include <stdint.h>
typedef struct DataPoint DataPoint;
typedef struct Node Node;
typedef struct DecisionLearnerContext {
DataPoint *DataPoints;
int32_t NumDataPoints;
float TotalWeight;
int32_t NumAttributeAxes;
int32_t NumCategoricalAxes;
int32_t *DataPointIds;
Node *Nodes;
int32_t CurrentLevel;
int32_t *OpenNodeIds;
int32_t NumOpenNodes;
int32_t *NextOpenNodeIds;
int32_t NumNextOpenNodes;
int32_t MaxOpenNodes;
} DecisionLearnerContext; | .text
.file "GPUDecisionLearnerContext.generated.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012e490_00000000-6_GPUDecisionLearnerContext.generated.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GPUDecisionLearnerContext.generated.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* @file pctdemo_processMandelbrotElement.cu
*
* CUDA code to calculate the Mandelbrot Set on a GPU.
*
* Copyright 2011 The MathWorks, Inc.
*/
/** Work out which piece of the global array this thread should operate on */
__device__ size_t calculateGlobalIndex() {
// Which block are we?
size_t const globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
// Which thread are we within the block?
size_t const localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
// How big is each block?
size_t const threadsPerBlock = blockDim.x*blockDim.y;
// Which thread are we overall?
return localThreadIdx + globalBlockIndex*threadsPerBlock;
}
/** The mandelbrot or julia algorithm for a single location */
__device__ unsigned int doIterations( double const x0,
double const y0,
double const a,
double const b,
unsigned int const k,
unsigned int const maxIters ) {
// Initialise: z = z0
// depending on x0, y0 we calc the mandelbrot or julia set
double x = x0;
double y = y0;
unsigned int count = 0;
// Loop until escape
while ( ( count <= maxIters )
&& ((x*x + y*y) <= 4.0) ) {
++count;
// Update: z = z*z + z0;
double const oldx = x;
// real part
x = x*x - y*y + a;
// imaginary part
y = 2.0*oldx*y + b;
}
return count;
}
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
*/
__global__ void processMandelbrotElementTest(
double * out,
const double * x,
const double * y,
const double a,
const double b,
const unsigned int k,
const unsigned int maxIters,
const unsigned int mandelbrot,
const unsigned int numel ) {
// Work out which thread we are
size_t const globalThreadIdx = calculateGlobalIndex();
// If we're off the end, return now
if (globalThreadIdx >= numel) {
return;
}
// Get our X and Y coords
double x0 = x[globalThreadIdx];
double y0 = y[globalThreadIdx];
double aVal = a;
double bVal = b;
if(mandelbrot == 1){
aVal = a*x0;
bVal = b*y0;
}
// Run the itearations on this location
unsigned int const count = doIterations( x0, y0, aVal, bVal, k, maxIters );
out[globalThreadIdx] = log( double( count + 1 ) );
} | code for sm_80
Function : _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R5, R5, c[0x0][0x4], RZ ; /* 0x0000010005057a24 */
/* 0x000fe400078e02ff */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00a0*/ UIMAD UR4, UR5, UR6, UR4 ; /* 0x00000006050472a4 */
/* 0x001fcc000f8e0204 */
/*00b0*/ IMAD.WIDE.U32 R4, R5, UR4, R2 ; /* 0x0000000405047c25 */
/* 0x000fca000f8e0002 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x194], PT ; /* 0x0000650004007a0c */
/* 0x000fc80003f06070 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f06100 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R2, R4.reuse, 0x8, RZ ; /* 0x0000000804027824 */
/* 0x040fe200078e00ff */
/*0100*/ SHF.L.U64.HI R0, R4, 0x3, R5 ; /* 0x0000000304007819 */
/* 0x000fe20000010205 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0120*/ IADD3 R10, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a00020a7a10 */
/* 0x040fe40007f1e0ff */
/*0130*/ IADD3 R4, P1, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fe40007f3e0ff */
/*0140*/ IADD3.X R11, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00000b7a10 */
/* 0x040fe400007fe4ff */
/*0150*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000057a10 */
/* 0x000fc80000ffe4ff */
/*0160*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*0180*/ BSSY B0, 0x3a0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0190*/ DMUL R14, R10, R10 ; /* 0x0000000a0a0e7228 */
/* 0x004fc80000000000 */
/*01a0*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x008e0c0000000000 */
/*01b0*/ DADD R6, R14, R12 ; /* 0x000000000e067229 */
/* 0x001e0c000000000c */
/*01c0*/ DSETP.GTU.AND P0, PT, R6, 4, PT ; /* 0x401000000600742a */
/* 0x0010640003f0c000 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff077424 */
/* 0x000fd400078e00ff */
/*01f0*/ @P0 BRA 0x390 ; /* 0x0000019000000947 */
/* 0x002fea0003800000 */
/*0200*/ DMUL R6, R4, c[0x0][0x180] ; /* 0x0000600004067a28 */
/* 0x000e220000000000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff037624 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B1, 0x370 ; /* 0x0000014000017945 */
/* 0x000fe40003800000 */
/*0230*/ DMUL R16, R10, c[0x0][0x178] ; /* 0x00005e000a107a28 */
/* 0x000e640000000000 */
/*0240*/ ISETP.NE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0260*/ FSEL R8, R6, c[0x0][0x180], !P0 ; /* 0x0000600006087a08 */
/* 0x001fe40004000000 */
/*0270*/ FSEL R9, R7, c[0x0][0x184], !P0 ; /* 0x0000610007097a08 */
/* 0x000fe40004000000 */
/*0280*/ FSEL R6, R16, c[0x0][0x178], !P0 ; /* 0x00005e0010067a08 */
/* 0x002fe40004000000 */
/*0290*/ FSEL R7, R17, c[0x0][0x17c], !P0 ; /* 0x00005f0011077a08 */
/* 0x000fe40004000000 */
/*02a0*/ DADD R12, -R12, R14 ; /* 0x000000000c0c7229 */
/* 0x000e22000000010e */
/*02b0*/ IMAD.MOV.U32 R16, RZ, RZ, R3 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0003 */
/*02c0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ DADD R14, R10, R10 ; /* 0x000000000a0e7229 */
/* 0x000e44000000000a */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fe40003f04070 */
/*02f0*/ DADD R10, R12, R6 ; /* 0x000000000c0a7229 */
/* 0x001e080000000006 */
/*0300*/ DFMA R4, R14, R4, R8 ; /* 0x000000040e04722b */
/* 0x002e480000000008 */
/*0310*/ DMUL R14, R10, R10 ; /* 0x0000000a0a0e7228 */
/* 0x001fc80000000000 */
/*0320*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x002e0c0000000000 */
/*0330*/ DADD R18, R14, R12 ; /* 0x000000000e127229 */
/* 0x001e0c000000000c */
/*0340*/ DSETP.LE.AND P1, PT, R18, 4, PT ; /* 0x401000001200742a */
/* 0x001e1c0003f23000 */
/*0350*/ @!P0 BRA P1, 0x2a0 ; /* 0xffffff4000008947 */
/* 0x001fea000083ffff */
/*0360*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R6, R16, 0x2, RZ ; /* 0x0000000210067810 */
/* 0x000fcc0007ffe0ff */
/*0380*/ I2F.F64.U32 R6, R6 ; /* 0x0000000600067312 */
/* 0x000e240000201800 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GT.AND P0, PT, R7, 0xfffff, PT ; /* 0x000fffff0700780c */
/* 0x001fe20003f04270 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*03c0*/ IADD3 R2, P3, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe20007f7e0ff */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*03e0*/ BSSY B0, 0x790 ; /* 0x000003a000007945 */
/* 0x000fe20003800000 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, -0x3ff ; /* 0xfffffc01ff047424 */
/* 0x000fd000078e00ff */
/*0400*/ @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006068828 */
/* 0x000e220000000000 */
/*0410*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, -0x435 ; /* 0xfffffbcbff048424 */
/* 0x000fd200078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x001fe400078e0007 */
/*0430*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a8224 */
/* 0x000fc600078e0006 */
/*0440*/ IADD3 R3, R5, -0x1, RZ ; /* 0xffffffff05037810 */
/* 0x000fc80007ffe0ff */
/*0450*/ ISETP.GE.U32.AND P1, PT, R3, 0x7fefffff, PT ; /* 0x7fefffff0300780c */
/* 0x000fe40003f26070 */
/*0460*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P3, !PT ; /* 0x0000590000037a10 */
/* 0x000fd60001ffe4ff */
/*0470*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff081424 */
/* 0x000fe200078e00ff */
/*0480*/ @P1 FSETP.NEU.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700120b */
/* 0x000fe20003f4d000 */
/*0490*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff091424 */
/* 0x000fcc00078e00ff */
/*04a0*/ @P1 DFMA R8, R6, R8, +INF ; /* 0x7ff000000608142b */
/* 0x000e140000000008 */
/*04b0*/ @P1 FSEL R14, R8, RZ, P2 ; /* 0x000000ff080e1208 */
/* 0x001fe40001000000 */
/*04c0*/ @P1 FSEL R15, R9, -QNAN , P2 ; /* 0xfff00000090f1808 */
/* 0x000fe20001000000 */
/*04d0*/ @P1 BRA 0x780 ; /* 0x000002a000001947 */
/* 0x000fea0003800000 */
/*04e0*/ LOP3.LUT R0, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05007812 */
/* 0x040fe200078ec0ff */
/*04f0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0500*/ LEA.HI R4, R5, R4, RZ, 0xc ; /* 0x0000000405047211 */
/* 0x000fe200078f60ff */
/*0510*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0520*/ LOP3.LUT R7, R0, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000000077812 */
/* 0x000fe200078efcff */
/*0530*/ IMAD.MOV.U32 R16, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff107424 */
/* 0x000fe400078e00ff */
/*0540*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff117424 */
/* 0x000fe200078e00ff */
/*0550*/ ISETP.GE.AND P0, PT, R7, 0x3ff6a09f, PT ; /* 0x3ff6a09f0700780c */
/* 0x000fe20003f06270 */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; /* 0x43300000ff057424 */
/* 0x000fd800078e00ff */
/*0570*/ @P0 IADD3 R9, R7, -0x100000, RZ ; /* 0xfff0000007090810 */
/* 0x000fe40007ffe0ff */
/*0580*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc60007ffe0ff */
/*0590*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0009 */
/*05a0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000004047812 */
/* 0x000fca00078e3cff */
/*05b0*/ DADD R14, R6, 1 ; /* 0x3ff00000060e7429 */
/* 0x000e080000000000 */
/*05c0*/ DADD R6, R6, -1 ; /* 0xbff0000006067429 */
/* 0x000fe40000000000 */
/*05d0*/ MUFU.RCP64H R9, R15 ; /* 0x0000000f00097308 */
/* 0x001e240000001800 */
/*05e0*/ DADD R4, R4, c[0x2][0x38] ; /* 0x00800e0004047629 */
/* 0x000fc80000000000 */
/*05f0*/ DFMA R10, -R14, R8, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c0000000108 */
/*0600*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0610*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x001e0c0000000008 */
/*0620*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*0630*/ DFMA R10, R8, R6, R10 ; /* 0x00000006080a722b */
/* 0x001e0c000000000a */
/*0640*/ DMUL R12, R10, R10 ; /* 0x0000000a0a0c7228 */
/* 0x001e080000000000 */
/*0650*/ DADD R14, R6, -R10 ; /* 0x00000000060e7229 */
/* 0x000e48000000080a */
/*0660*/ DFMA R16, R12, R16, c[0x2][0x0] ; /* 0x008000000c10762b */
/* 0x001e080000000010 */
/*0670*/ DADD R18, R14, R14 ; /* 0x000000000e127229 */
/* 0x002fc8000000000e */
/*0680*/ DFMA R16, R12, R16, c[0x2][0x8] ; /* 0x008002000c10762b */
/* 0x001e080000000010 */
/*0690*/ DFMA R14, R4, c[0x2][0x40], R10 ; /* 0x00801000040e7a2b */
/* 0x000fc8000000000a */
/*06a0*/ DFMA R16, R12, R16, c[0x2][0x10] ; /* 0x008004000c10762b */
/* 0x001e080000000010 */
/*06b0*/ DFMA R18, R6, -R10, R18 ; /* 0x8000000a0612722b */
/* 0x000fc80000000012 */
/*06c0*/ DFMA R16, R12, R16, c[0x2][0x18] ; /* 0x008006000c10762b */
/* 0x001e080000000010 */
/*06d0*/ DFMA R6, -R4, c[0x2][0x40], R14 ; /* 0x0080100004067a2b */
/* 0x000fc8000000010e */
/*06e0*/ DFMA R16, R12, R16, c[0x2][0x20] ; /* 0x008008000c10762b */
/* 0x001e080000000010 */
/*06f0*/ DMUL R18, R8, R18 ; /* 0x0000001208127228 */
/* 0x000fc80000000000 */
/*0700*/ DFMA R16, R12, R16, c[0x2][0x28] ; /* 0x00800a000c10762b */
/* 0x001e080000000010 */
/*0710*/ DADD R6, -R10, R6 ; /* 0x000000000a067229 */
/* 0x000fc80000000106 */
/*0720*/ DFMA R16, R12, R16, c[0x2][0x30] ; /* 0x00800c000c10762b */
/* 0x001e0c0000000010 */
/*0730*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x001e0c0000000000 */
/*0740*/ DFMA R16, R10, R16, R18 ; /* 0x000000100a10722b */
/* 0x001e0c0000000012 */
/*0750*/ DADD R6, R16, -R6 ; /* 0x0000000010067229 */
/* 0x001e0c0000000806 */
/*0760*/ DFMA R6, R4, c[0x2][0x48], R6 ; /* 0x0080120004067a2b */
/* 0x001e0c0000000006 */
/*0770*/ DADD R14, R14, R6 ; /* 0x000000000e0e7229 */
/* 0x00104c0000000006 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x002fe2000c101b04 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* @file pctdemo_processMandelbrotElement.cu
*
* CUDA code to calculate the Mandelbrot Set on a GPU.
*
* Copyright 2011 The MathWorks, Inc.
*/
/** Work out which piece of the global array this thread should operate on */
__device__ size_t calculateGlobalIndex() {
// Which block are we?
size_t const globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
// Which thread are we within the block?
size_t const localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
// How big is each block?
size_t const threadsPerBlock = blockDim.x*blockDim.y;
// Which thread are we overall?
return localThreadIdx + globalBlockIndex*threadsPerBlock;
}
/** The mandelbrot or julia algorithm for a single location */
__device__ unsigned int doIterations( double const x0,
double const y0,
double const a,
double const b,
unsigned int const k,
unsigned int const maxIters ) {
// Initialise: z = z0
// depending on x0, y0 we calc the mandelbrot or julia set
double x = x0;
double y = y0;
unsigned int count = 0;
// Loop until escape
while ( ( count <= maxIters )
&& ((x*x + y*y) <= 4.0) ) {
++count;
// Update: z = z*z + z0;
double const oldx = x;
// real part
x = x*x - y*y + a;
// imaginary part
y = 2.0*oldx*y + b;
}
return count;
}
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
*/
__global__ void processMandelbrotElementTest(
double * out,
const double * x,
const double * y,
const double a,
const double b,
const unsigned int k,
const unsigned int maxIters,
const unsigned int mandelbrot,
const unsigned int numel ) {
// Work out which thread we are
size_t const globalThreadIdx = calculateGlobalIndex();
// If we're off the end, return now
if (globalThreadIdx >= numel) {
return;
}
// Get our X and Y coords
double x0 = x[globalThreadIdx];
double y0 = y[globalThreadIdx];
double aVal = a;
double bVal = b;
if(mandelbrot == 1){
aVal = a*x0;
bVal = b*y0;
}
// Run the itearations on this location
unsigned int const count = doIterations( x0, y0, aVal, bVal, k, maxIters );
out[globalThreadIdx] = log( double( count + 1 ) );
} | .file "tmpxft_0002df45_00000000-6_processMandelbrotElement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20calculateGlobalIndexv
.type _Z20calculateGlobalIndexv, @function
_Z20calculateGlobalIndexv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z20calculateGlobalIndexv, .-_Z20calculateGlobalIndexv
.globl _Z12doIterationsddddjj
.type _Z12doIterationsddddjj, @function
_Z12doIterationsddddjj:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z12doIterationsddddjj, .-_Z12doIterationsddddjj
.globl _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj
.type _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj, @function
_Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28processMandelbrotElementTestPdPKdS1_ddjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj, .-_Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj
.globl _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.type _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, @function
_Z28processMandelbrotElementTestPdPKdS1_ddjjjj:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, .-_Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28processMandelbrotElementTestPdPKdS1_ddjjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28processMandelbrotElementTestPdPKdS1_ddjjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* @file pctdemo_processMandelbrotElement.cu
*
* CUDA code to calculate the Mandelbrot Set on a GPU.
*
* Copyright 2011 The MathWorks, Inc.
*/
/** Work out which piece of the global array this thread should operate on */
__device__ size_t calculateGlobalIndex() {
// Which block are we?
size_t const globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
// Which thread are we within the block?
size_t const localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
// How big is each block?
size_t const threadsPerBlock = blockDim.x*blockDim.y;
// Which thread are we overall?
return localThreadIdx + globalBlockIndex*threadsPerBlock;
}
/** The mandelbrot or julia algorithm for a single location */
__device__ unsigned int doIterations( double const x0,
double const y0,
double const a,
double const b,
unsigned int const k,
unsigned int const maxIters ) {
// Initialise: z = z0
// depending on x0, y0 we calc the mandelbrot or julia set
double x = x0;
double y = y0;
unsigned int count = 0;
// Loop until escape
while ( ( count <= maxIters )
&& ((x*x + y*y) <= 4.0) ) {
++count;
// Update: z = z*z + z0;
double const oldx = x;
// real part
x = x*x - y*y + a;
// imaginary part
y = 2.0*oldx*y + b;
}
return count;
}
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
*/
__global__ void processMandelbrotElementTest(
double * out,
const double * x,
const double * y,
const double a,
const double b,
const unsigned int k,
const unsigned int maxIters,
const unsigned int mandelbrot,
const unsigned int numel ) {
// Work out which thread we are
size_t const globalThreadIdx = calculateGlobalIndex();
// If we're off the end, return now
if (globalThreadIdx >= numel) {
return;
}
// Get our X and Y coords
double x0 = x[globalThreadIdx];
double y0 = y[globalThreadIdx];
double aVal = a;
double bVal = b;
if(mandelbrot == 1){
aVal = a*x0;
bVal = b*y0;
}
// Run the itearations on this location
unsigned int const count = doIterations( x0, y0, aVal, bVal, k, maxIters );
out[globalThreadIdx] = log( double( count + 1 ) );
} | #include <hip/hip_runtime.h>
/**
* @file pctdemo_processMandelbrotElement.cu
*
* CUDA code to calculate the Mandelbrot Set on a GPU.
*
* Copyright 2011 The MathWorks, Inc.
*/
/** Work out which piece of the global array this thread should operate on */
__device__ size_t calculateGlobalIndex() {
// Which block are we?
size_t const globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
// Which thread are we within the block?
size_t const localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
// How big is each block?
size_t const threadsPerBlock = blockDim.x*blockDim.y;
// Which thread are we overall?
return localThreadIdx + globalBlockIndex*threadsPerBlock;
}
/** The mandelbrot or julia algorithm for a single location */
__device__ unsigned int doIterations( double const x0,
double const y0,
double const a,
double const b,
unsigned int const k,
unsigned int const maxIters ) {
// Initialise: z = z0
// depending on x0, y0 we calc the mandelbrot or julia set
double x = x0;
double y = y0;
unsigned int count = 0;
// Loop until escape
while ( ( count <= maxIters )
&& ((x*x + y*y) <= 4.0) ) {
++count;
// Update: z = z*z + z0;
double const oldx = x;
// real part
x = x*x - y*y + a;
// imaginary part
y = 2.0*oldx*y + b;
}
return count;
}
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
*/
__global__ void processMandelbrotElementTest(
double * out,
const double * x,
const double * y,
const double a,
const double b,
const unsigned int k,
const unsigned int maxIters,
const unsigned int mandelbrot,
const unsigned int numel ) {
// Work out which thread we are
size_t const globalThreadIdx = calculateGlobalIndex();
// If we're off the end, return now
if (globalThreadIdx >= numel) {
return;
}
// Get our X and Y coords
double x0 = x[globalThreadIdx];
double y0 = y[globalThreadIdx];
double aVal = a;
double bVal = b;
if(mandelbrot == 1){
aVal = a*x0;
bVal = b*y0;
}
// Run the itearations on this location
unsigned int const count = doIterations( x0, y0, aVal, bVal, k, maxIters );
out[globalThreadIdx] = log( double( count + 1 ) );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/**
* @file pctdemo_processMandelbrotElement.cu
*
* CUDA code to calculate the Mandelbrot Set on a GPU.
*
* Copyright 2011 The MathWorks, Inc.
*/
/** Work out which piece of the global array this thread should operate on */
__device__ size_t calculateGlobalIndex() {
// Which block are we?
size_t const globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
// Which thread are we within the block?
size_t const localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
// How big is each block?
size_t const threadsPerBlock = blockDim.x*blockDim.y;
// Which thread are we overall?
return localThreadIdx + globalBlockIndex*threadsPerBlock;
}
/** The mandelbrot or julia algorithm for a single location */
__device__ unsigned int doIterations( double const x0,
double const y0,
double const a,
double const b,
unsigned int const k,
unsigned int const maxIters ) {
// Initialise: z = z0
// depending on x0, y0 we calc the mandelbrot or julia set
double x = x0;
double y = y0;
unsigned int count = 0;
// Loop until escape
while ( ( count <= maxIters )
&& ((x*x + y*y) <= 4.0) ) {
++count;
// Update: z = z*z + z0;
double const oldx = x;
// real part
x = x*x - y*y + a;
// imaginary part
y = 2.0*oldx*y + b;
}
return count;
}
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
*/
__global__ void processMandelbrotElementTest(
double * out,
const double * x,
const double * y,
const double a,
const double b,
const unsigned int k,
const unsigned int maxIters,
const unsigned int mandelbrot,
const unsigned int numel ) {
// Work out which thread we are
size_t const globalThreadIdx = calculateGlobalIndex();
// If we're off the end, return now
if (globalThreadIdx >= numel) {
return;
}
// Get our X and Y coords
double x0 = x[globalThreadIdx];
double y0 = y[globalThreadIdx];
double aVal = a;
double bVal = b;
if(mandelbrot == 1){
aVal = a*x0;
bVal = b*y0;
}
// Run the itearations on this location
unsigned int const count = doIterations( x0, y0, aVal, bVal, k, maxIters );
out[globalThreadIdx] = log( double( count + 1 ) );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.globl _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.p2align 8
.type _Z28processMandelbrotElementTestPdPKdS1_ddjjjj,@function
_Z28processMandelbrotElementTestPdPKdS1_ddjjjj:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x44
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s14
s_cmp_lt_u32 s14, s3
s_cselect_b32 s3, 12, 18
v_mov_b32_e32 v1, s3
s_lshr_b32 s3, s6, 16
global_load_u16 v1, v1, s[4:5]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, s3, v1
v_mad_u32_u24 v2, v0, v1, v2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v4, s7, v[2:3]
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b256 s[4:11], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_load_b32 s2, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
global_load_b64 v[8:9], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
s_cmp_lg_u32 s2, 1
s_cbranch_scc1 .LBB0_3
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[8:9], s[8:9]
s_waitcnt vmcnt(0)
v_mul_f64 v[6:7], v[2:3], s[10:11]
.LBB0_3:
s_load_b32 s3, s[0:1], 0x2c
s_mov_b32 s2, 0
s_mov_b32 s4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s2, s6, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
.LBB0_5:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[2:3], v[2:3]
s_or_b32 s5, s5, exec_lo
v_fma_f64 v[12:13], v[8:9], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_f64_e32 vcc_lo, 4.0, v[12:13]
v_mov_b32_e32 v12, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_f64 v[12:13], v[8:9], v[8:9]
v_add_f64 v[8:9], v[8:9], v[8:9]
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s4, s3
s_cselect_b32 s7, -1, 0
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s5, s5, s7
v_add_f64 v[10:11], v[12:13], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[8:9], v[2:3], v[6:7]
v_add_f64 v[10:11], v[4:5], v[10:11]
v_mov_b32_e32 v12, s4
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v2, s8, v12, 1
s_waitcnt lgkmcnt(0)
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s5, 0x3fc38538
v_cvt_f64_u32_e32 v[2:3], v2
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[4:5], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_mov_b32 s2, 0x55555780
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[6:7], v[10:11]
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], -v[4:5]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[6:7], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[6:7], v[6:7]
v_fma_f64 v[12:13], v[8:9], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fc7474d
s_mov_b32 s4, 0xd7f4df2e
v_mul_f64 v[14:15], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[12:13], s[2:3]
v_frexp_exp_i32_f64_e32 v12, v[2:3]
v_ldexp_f64 v[2:3], v[6:7], 1
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_mov_b32 s3, 0x3fe62e42
s_mov_b32 s2, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[14:15], v[8:9]
v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], -v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_cvt_f64_i32_e32 v[12:13], v12
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_f64 v[10:11], v[2:3], v[8:9]
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[14:15], v[12:13], s[2:3]
v_add_f64 v[2:3], v[10:11], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[12:13], s[2:3], -v[14:15]
s_mov_b32 s3, 0x3c7abc9e
s_mov_b32 s2, 0x3b39803f
v_add_f64 v[2:3], v[8:9], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[12:13], s[2:3], v[6:7]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[14:15], v[6:7]
v_add_f64 v[8:9], v[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[4:5], -v[14:15]
v_add_f64 v[12:13], v[4:5], v[8:9]
v_add_f64 v[10:11], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], -v[14:15]
v_add_f64 v[16:17], v[12:13], -v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[10:11]
v_add_f64 v[18:19], v[12:13], -v[16:17]
v_add_f64 v[8:9], v[8:9], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[6:7], v[2:3]
v_add_f64 v[4:5], v[4:5], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[8:9], v[10:11], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[10:11], v[4:5]
v_add_f64 v[10:11], v[10:11], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[12:13], v[4:5]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[14:15], -v[12:13]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[14:15], v[2:3]
v_cndmask_b32_e64 v3, v3, 0xfff00000, s8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v2, v2, 0, s8
global_store_b64 v[0:1], v[2:3], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, .Lfunc_end0-_Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28processMandelbrotElementTestPdPKdS1_ddjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/**
* @file pctdemo_processMandelbrotElement.cu
*
* CUDA code to calculate the Mandelbrot Set on a GPU.
*
* Copyright 2011 The MathWorks, Inc.
*/
/** Work out which piece of the global array this thread should operate on */
__device__ size_t calculateGlobalIndex() {
// Which block are we?
size_t const globalBlockIndex = blockIdx.x + blockIdx.y * gridDim.x;
// Which thread are we within the block?
size_t const localThreadIdx = threadIdx.x + blockDim.x * threadIdx.y;
// How big is each block?
size_t const threadsPerBlock = blockDim.x*blockDim.y;
// Which thread are we overall?
return localThreadIdx + globalBlockIndex*threadsPerBlock;
}
/** The mandelbrot or julia algorithm for a single location */
__device__ unsigned int doIterations( double const x0,
double const y0,
double const a,
double const b,
unsigned int const k,
unsigned int const maxIters ) {
// Initialise: z = z0
// depending on x0, y0 we calc the mandelbrot or julia set
double x = x0;
double y = y0;
unsigned int count = 0;
// Loop until escape
while ( ( count <= maxIters )
&& ((x*x + y*y) <= 4.0) ) {
++count;
// Update: z = z*z + z0;
double const oldx = x;
// real part
x = x*x - y*y + a;
// imaginary part
y = 2.0*oldx*y + b;
}
return count;
}
/** Main entry point.
* Works out where the current thread should read/write to global memory
* and calls doIterations to do the actual work.
*/
__global__ void processMandelbrotElementTest(
double * out,
const double * x,
const double * y,
const double a,
const double b,
const unsigned int k,
const unsigned int maxIters,
const unsigned int mandelbrot,
const unsigned int numel ) {
// Work out which thread we are
size_t const globalThreadIdx = calculateGlobalIndex();
// If we're off the end, return now
if (globalThreadIdx >= numel) {
return;
}
// Get our X and Y coords
double x0 = x[globalThreadIdx];
double y0 = y[globalThreadIdx];
double aVal = a;
double bVal = b;
if(mandelbrot == 1){
aVal = a*x0;
bVal = b*y0;
}
// Run the itearations on this location
unsigned int const count = doIterations( x0, y0, aVal, bVal, k, maxIters );
out[globalThreadIdx] = log( double( count + 1 ) );
} | .text
.file "processMandelbrotElement.hip"
.globl _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj # -- Begin function _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.p2align 4, 0x90
.type _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj,@function
_Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj: # @_Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28processMandelbrotElementTestPdPKdS1_ddjjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj, .Lfunc_end0-_Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28processMandelbrotElementTestPdPKdS1_ddjjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28processMandelbrotElementTestPdPKdS1_ddjjjj,@object # @_Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.section .rodata,"a",@progbits
.globl _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.p2align 3, 0x0
_Z28processMandelbrotElementTestPdPKdS1_ddjjjj:
.quad _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.size _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28processMandelbrotElementTestPdPKdS1_ddjjjj"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R5, R5, c[0x0][0x4], RZ ; /* 0x0000010005057a24 */
/* 0x000fe400078e02ff */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00a0*/ UIMAD UR4, UR5, UR6, UR4 ; /* 0x00000006050472a4 */
/* 0x001fcc000f8e0204 */
/*00b0*/ IMAD.WIDE.U32 R4, R5, UR4, R2 ; /* 0x0000000405047c25 */
/* 0x000fca000f8e0002 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x194], PT ; /* 0x0000650004007a0c */
/* 0x000fc80003f06070 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f06100 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R2, R4.reuse, 0x8, RZ ; /* 0x0000000804027824 */
/* 0x040fe200078e00ff */
/*0100*/ SHF.L.U64.HI R0, R4, 0x3, R5 ; /* 0x0000000304007819 */
/* 0x000fe20000010205 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0120*/ IADD3 R10, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a00020a7a10 */
/* 0x040fe40007f1e0ff */
/*0130*/ IADD3 R4, P1, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fe40007f3e0ff */
/*0140*/ IADD3.X R11, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00000b7a10 */
/* 0x040fe400007fe4ff */
/*0150*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000057a10 */
/* 0x000fc80000ffe4ff */
/*0160*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*0180*/ BSSY B0, 0x3a0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0190*/ DMUL R14, R10, R10 ; /* 0x0000000a0a0e7228 */
/* 0x004fc80000000000 */
/*01a0*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x008e0c0000000000 */
/*01b0*/ DADD R6, R14, R12 ; /* 0x000000000e067229 */
/* 0x001e0c000000000c */
/*01c0*/ DSETP.GTU.AND P0, PT, R6, 4, PT ; /* 0x401000000600742a */
/* 0x0010640003f0c000 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff077424 */
/* 0x000fd400078e00ff */
/*01f0*/ @P0 BRA 0x390 ; /* 0x0000019000000947 */
/* 0x002fea0003800000 */
/*0200*/ DMUL R6, R4, c[0x0][0x180] ; /* 0x0000600004067a28 */
/* 0x000e220000000000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff037624 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B1, 0x370 ; /* 0x0000014000017945 */
/* 0x000fe40003800000 */
/*0230*/ DMUL R16, R10, c[0x0][0x178] ; /* 0x00005e000a107a28 */
/* 0x000e640000000000 */
/*0240*/ ISETP.NE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0260*/ FSEL R8, R6, c[0x0][0x180], !P0 ; /* 0x0000600006087a08 */
/* 0x001fe40004000000 */
/*0270*/ FSEL R9, R7, c[0x0][0x184], !P0 ; /* 0x0000610007097a08 */
/* 0x000fe40004000000 */
/*0280*/ FSEL R6, R16, c[0x0][0x178], !P0 ; /* 0x00005e0010067a08 */
/* 0x002fe40004000000 */
/*0290*/ FSEL R7, R17, c[0x0][0x17c], !P0 ; /* 0x00005f0011077a08 */
/* 0x000fe40004000000 */
/*02a0*/ DADD R12, -R12, R14 ; /* 0x000000000c0c7229 */
/* 0x000e22000000010e */
/*02b0*/ IMAD.MOV.U32 R16, RZ, RZ, R3 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0003 */
/*02c0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ DADD R14, R10, R10 ; /* 0x000000000a0e7229 */
/* 0x000e44000000000a */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fe40003f04070 */
/*02f0*/ DADD R10, R12, R6 ; /* 0x000000000c0a7229 */
/* 0x001e080000000006 */
/*0300*/ DFMA R4, R14, R4, R8 ; /* 0x000000040e04722b */
/* 0x002e480000000008 */
/*0310*/ DMUL R14, R10, R10 ; /* 0x0000000a0a0e7228 */
/* 0x001fc80000000000 */
/*0320*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x002e0c0000000000 */
/*0330*/ DADD R18, R14, R12 ; /* 0x000000000e127229 */
/* 0x001e0c000000000c */
/*0340*/ DSETP.LE.AND P1, PT, R18, 4, PT ; /* 0x401000001200742a */
/* 0x001e1c0003f23000 */
/*0350*/ @!P0 BRA P1, 0x2a0 ; /* 0xffffff4000008947 */
/* 0x001fea000083ffff */
/*0360*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R6, R16, 0x2, RZ ; /* 0x0000000210067810 */
/* 0x000fcc0007ffe0ff */
/*0380*/ I2F.F64.U32 R6, R6 ; /* 0x0000000600067312 */
/* 0x000e240000201800 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GT.AND P0, PT, R7, 0xfffff, PT ; /* 0x000fffff0700780c */
/* 0x001fe20003f04270 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*03c0*/ IADD3 R2, P3, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe20007f7e0ff */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*03e0*/ BSSY B0, 0x790 ; /* 0x000003a000007945 */
/* 0x000fe20003800000 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, -0x3ff ; /* 0xfffffc01ff047424 */
/* 0x000fd000078e00ff */
/*0400*/ @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006068828 */
/* 0x000e220000000000 */
/*0410*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, -0x435 ; /* 0xfffffbcbff048424 */
/* 0x000fd200078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x001fe400078e0007 */
/*0430*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a8224 */
/* 0x000fc600078e0006 */
/*0440*/ IADD3 R3, R5, -0x1, RZ ; /* 0xffffffff05037810 */
/* 0x000fc80007ffe0ff */
/*0450*/ ISETP.GE.U32.AND P1, PT, R3, 0x7fefffff, PT ; /* 0x7fefffff0300780c */
/* 0x000fe40003f26070 */
/*0460*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P3, !PT ; /* 0x0000590000037a10 */
/* 0x000fd60001ffe4ff */
/*0470*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff081424 */
/* 0x000fe200078e00ff */
/*0480*/ @P1 FSETP.NEU.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700120b */
/* 0x000fe20003f4d000 */
/*0490*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff091424 */
/* 0x000fcc00078e00ff */
/*04a0*/ @P1 DFMA R8, R6, R8, +INF ; /* 0x7ff000000608142b */
/* 0x000e140000000008 */
/*04b0*/ @P1 FSEL R14, R8, RZ, P2 ; /* 0x000000ff080e1208 */
/* 0x001fe40001000000 */
/*04c0*/ @P1 FSEL R15, R9, -QNAN , P2 ; /* 0xfff00000090f1808 */
/* 0x000fe20001000000 */
/*04d0*/ @P1 BRA 0x780 ; /* 0x000002a000001947 */
/* 0x000fea0003800000 */
/*04e0*/ LOP3.LUT R0, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05007812 */
/* 0x040fe200078ec0ff */
/*04f0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0500*/ LEA.HI R4, R5, R4, RZ, 0xc ; /* 0x0000000405047211 */
/* 0x000fe200078f60ff */
/*0510*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0520*/ LOP3.LUT R7, R0, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000000077812 */
/* 0x000fe200078efcff */
/*0530*/ IMAD.MOV.U32 R16, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff107424 */
/* 0x000fe400078e00ff */
/*0540*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff117424 */
/* 0x000fe200078e00ff */
/*0550*/ ISETP.GE.AND P0, PT, R7, 0x3ff6a09f, PT ; /* 0x3ff6a09f0700780c */
/* 0x000fe20003f06270 */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; /* 0x43300000ff057424 */
/* 0x000fd800078e00ff */
/*0570*/ @P0 IADD3 R9, R7, -0x100000, RZ ; /* 0xfff0000007090810 */
/* 0x000fe40007ffe0ff */
/*0580*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc60007ffe0ff */
/*0590*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0009 */
/*05a0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000004047812 */
/* 0x000fca00078e3cff */
/*05b0*/ DADD R14, R6, 1 ; /* 0x3ff00000060e7429 */
/* 0x000e080000000000 */
/*05c0*/ DADD R6, R6, -1 ; /* 0xbff0000006067429 */
/* 0x000fe40000000000 */
/*05d0*/ MUFU.RCP64H R9, R15 ; /* 0x0000000f00097308 */
/* 0x001e240000001800 */
/*05e0*/ DADD R4, R4, c[0x2][0x38] ; /* 0x00800e0004047629 */
/* 0x000fc80000000000 */
/*05f0*/ DFMA R10, -R14, R8, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c0000000108 */
/*0600*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0610*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x001e0c0000000008 */
/*0620*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*0630*/ DFMA R10, R8, R6, R10 ; /* 0x00000006080a722b */
/* 0x001e0c000000000a */
/*0640*/ DMUL R12, R10, R10 ; /* 0x0000000a0a0c7228 */
/* 0x001e080000000000 */
/*0650*/ DADD R14, R6, -R10 ; /* 0x00000000060e7229 */
/* 0x000e48000000080a */
/*0660*/ DFMA R16, R12, R16, c[0x2][0x0] ; /* 0x008000000c10762b */
/* 0x001e080000000010 */
/*0670*/ DADD R18, R14, R14 ; /* 0x000000000e127229 */
/* 0x002fc8000000000e */
/*0680*/ DFMA R16, R12, R16, c[0x2][0x8] ; /* 0x008002000c10762b */
/* 0x001e080000000010 */
/*0690*/ DFMA R14, R4, c[0x2][0x40], R10 ; /* 0x00801000040e7a2b */
/* 0x000fc8000000000a */
/*06a0*/ DFMA R16, R12, R16, c[0x2][0x10] ; /* 0x008004000c10762b */
/* 0x001e080000000010 */
/*06b0*/ DFMA R18, R6, -R10, R18 ; /* 0x8000000a0612722b */
/* 0x000fc80000000012 */
/*06c0*/ DFMA R16, R12, R16, c[0x2][0x18] ; /* 0x008006000c10762b */
/* 0x001e080000000010 */
/*06d0*/ DFMA R6, -R4, c[0x2][0x40], R14 ; /* 0x0080100004067a2b */
/* 0x000fc8000000010e */
/*06e0*/ DFMA R16, R12, R16, c[0x2][0x20] ; /* 0x008008000c10762b */
/* 0x001e080000000010 */
/*06f0*/ DMUL R18, R8, R18 ; /* 0x0000001208127228 */
/* 0x000fc80000000000 */
/*0700*/ DFMA R16, R12, R16, c[0x2][0x28] ; /* 0x00800a000c10762b */
/* 0x001e080000000010 */
/*0710*/ DADD R6, -R10, R6 ; /* 0x000000000a067229 */
/* 0x000fc80000000106 */
/*0720*/ DFMA R16, R12, R16, c[0x2][0x30] ; /* 0x00800c000c10762b */
/* 0x001e0c0000000010 */
/*0730*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x001e0c0000000000 */
/*0740*/ DFMA R16, R10, R16, R18 ; /* 0x000000100a10722b */
/* 0x001e0c0000000012 */
/*0750*/ DADD R6, R16, -R6 ; /* 0x0000000010067229 */
/* 0x001e0c0000000806 */
/*0760*/ DFMA R6, R4, c[0x2][0x48], R6 ; /* 0x0080120004067a2b */
/* 0x001e0c0000000006 */
/*0770*/ DADD R14, R14, R6 ; /* 0x000000000e0e7229 */
/* 0x00104c0000000006 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x002fe2000c101b04 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.globl _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.p2align 8
.type _Z28processMandelbrotElementTestPdPKdS1_ddjjjj,@function
_Z28processMandelbrotElementTestPdPKdS1_ddjjjj:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x44
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s14
s_cmp_lt_u32 s14, s3
s_cselect_b32 s3, 12, 18
v_mov_b32_e32 v1, s3
s_lshr_b32 s3, s6, 16
global_load_u16 v1, v1, s[4:5]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, s3, v1
v_mad_u32_u24 v2, v0, v1, v2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v4, s7, v[2:3]
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b256 s[4:11], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_load_b32 s2, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
global_load_b64 v[8:9], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
s_cmp_lg_u32 s2, 1
s_cbranch_scc1 .LBB0_3
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[8:9], s[8:9]
s_waitcnt vmcnt(0)
v_mul_f64 v[6:7], v[2:3], s[10:11]
.LBB0_3:
s_load_b32 s3, s[0:1], 0x2c
s_mov_b32 s2, 0
s_mov_b32 s4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s2, s6, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
.LBB0_5:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[2:3], v[2:3]
s_or_b32 s5, s5, exec_lo
v_fma_f64 v[12:13], v[8:9], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_f64_e32 vcc_lo, 4.0, v[12:13]
v_mov_b32_e32 v12, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_f64 v[12:13], v[8:9], v[8:9]
v_add_f64 v[8:9], v[8:9], v[8:9]
s_add_i32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s4, s3
s_cselect_b32 s7, -1, 0
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s5, s5, s7
v_add_f64 v[10:11], v[12:13], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[8:9], v[2:3], v[6:7]
v_add_f64 v[10:11], v[4:5], v[10:11]
v_mov_b32_e32 v12, s4
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v2, s8, v12, 1
s_waitcnt lgkmcnt(0)
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s5, 0x3fc38538
v_cvt_f64_u32_e32 v[2:3], v2
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[4:5], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[4:5]
s_mov_b32 s2, 0x55555780
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[6:7], v[10:11]
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], -v[4:5]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[6:7], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[6:7], v[6:7]
v_fma_f64 v[12:13], v[8:9], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fc7474d
s_mov_b32 s4, 0xd7f4df2e
v_mul_f64 v[14:15], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[8:9], v[12:13], s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[12:13], s[2:3]
v_frexp_exp_i32_f64_e32 v12, v[2:3]
v_ldexp_f64 v[2:3], v[6:7], 1
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_mov_b32 s3, 0x3fe62e42
s_mov_b32 s2, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[14:15], v[8:9]
v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], -v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_cvt_f64_i32_e32 v[12:13], v12
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_f64 v[10:11], v[2:3], v[8:9]
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[14:15], v[12:13], s[2:3]
v_add_f64 v[2:3], v[10:11], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[12:13], s[2:3], -v[14:15]
s_mov_b32 s3, 0x3c7abc9e
s_mov_b32 s2, 0x3b39803f
v_add_f64 v[2:3], v[8:9], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[12:13], s[2:3], v[6:7]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[14:15], v[6:7]
v_add_f64 v[8:9], v[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[4:5], -v[14:15]
v_add_f64 v[12:13], v[4:5], v[8:9]
v_add_f64 v[10:11], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], -v[14:15]
v_add_f64 v[16:17], v[12:13], -v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[10:11]
v_add_f64 v[18:19], v[12:13], -v[16:17]
v_add_f64 v[8:9], v[8:9], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[6:7], v[2:3]
v_add_f64 v[4:5], v[4:5], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[8:9], v[10:11], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[10:11], v[4:5]
v_add_f64 v[10:11], v[10:11], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[12:13], v[4:5]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[14:15], -v[12:13]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[14:15], v[2:3]
v_cndmask_b32_e64 v3, v3, 0xfff00000, s8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v2, v2, 0, s8
global_store_b64 v[0:1], v[2:3], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, .Lfunc_end0-_Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28processMandelbrotElementTestPdPKdS1_ddjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002df45_00000000-6_processMandelbrotElement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20calculateGlobalIndexv
.type _Z20calculateGlobalIndexv, @function
_Z20calculateGlobalIndexv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z20calculateGlobalIndexv, .-_Z20calculateGlobalIndexv
.globl _Z12doIterationsddddjj
.type _Z12doIterationsddddjj, @function
_Z12doIterationsddddjj:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z12doIterationsddddjj, .-_Z12doIterationsddddjj
.globl _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj
.type _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj, @function
_Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z28processMandelbrotElementTestPdPKdS1_ddjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj, .-_Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj
.globl _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.type _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, @function
_Z28processMandelbrotElementTestPdPKdS1_ddjjjj:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z28processMandelbrotElementTestPdPKdS1_ddjjjjPdPKdS1_ddjjjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, .-_Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28processMandelbrotElementTestPdPKdS1_ddjjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28processMandelbrotElementTestPdPKdS1_ddjjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "processMandelbrotElement.hip"
.globl _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj # -- Begin function _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.p2align 4, 0x90
.type _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj,@function
_Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj: # @_Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z28processMandelbrotElementTestPdPKdS1_ddjjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj, .Lfunc_end0-_Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28processMandelbrotElementTestPdPKdS1_ddjjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28processMandelbrotElementTestPdPKdS1_ddjjjj,@object # @_Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.section .rodata,"a",@progbits
.globl _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.p2align 3, 0x0
_Z28processMandelbrotElementTestPdPKdS1_ddjjjj:
.quad _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.size _Z28processMandelbrotElementTestPdPKdS1_ddjjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28processMandelbrotElementTestPdPKdS1_ddjjjj"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__processMandelbrotElementTestPdPKdS1_ddjjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28processMandelbrotElementTestPdPKdS1_ddjjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A, int Acount, int Acols, float * out0, int out0count, int out0cols, float row_id) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < Acols) {
out0[id] = A[id + (int)row_id*Acols];
}
} | code for sm_80
Function : _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ F2I.TRUNC.NTZ R3, c[0x0][0x180] ; /* 0x0000600000037b05 */
/* 0x000e22000020f100 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x001fd000078e0200 */
/*00c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0204 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A, int Acount, int Acols, float * out0, int out0count, int out0cols, float row_id) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < Acols) {
out0[id] = A[id + (int)row_id*Acols];
}
} | .file "tmpxft_0018937d_00000000-6_Matrix_getRow_FloatId_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.type _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, @function
_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, .-_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, @function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A, int Acount, int Acols, float * out0, int out0count, int out0cols, float row_id) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < Acols) {
out0[id] = A[id + (int)row_id*Acols];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A, int Acount, int Acols, float * out0, int out0count, int out0cols, float row_id) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < Acols) {
out0[id] = A[id + (int)row_id*Acols];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A, int Acount, int Acols, float * out0, int out0count, int out0cols, float row_id) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < Acols) {
out0[id] = A[id + (int)row_id*Acols];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 8
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A, int Acount, int Acols, float * out0, int out0count, int out0cols, float row_id) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < Acols) {
out0[id] = A[id + (int)row_id*Acols];
}
} | .text
.file "Matrix_getRow_FloatId_naive.hip"
.globl _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif # -- Begin function _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 4, 0x90
.type _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif: # @_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@object # @_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata,"a",@progbits
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 3, 0x0
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.quad _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ F2I.TRUNC.NTZ R3, c[0x0][0x180] ; /* 0x0000600000037b05 */
/* 0x000e22000020f100 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x001fd000078e0200 */
/*00c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0204 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 8
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018937d_00000000-6_Matrix_getRow_FloatId_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.type _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, @function
_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, .-_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, @function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix_getRow_FloatId_naive.hip"
.globl _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif # -- Begin function _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 4, 0x90
.type _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif: # @_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@object # @_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata,"a",@progbits
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 3, 0x0
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.quad _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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