system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void update_e(int objs,double* e,double* kval,double b_old,double b_new,int i,int j,int yi,int yj,double ai_old,double ai_new,double aj_old,double aj_new){
int id=blockDim.x * blockIdx.x + threadIdx.x;
if (id<objs){
double val=e[id];
val+=(b_new-b_old);
double ti=yi*kval[i*objs+id];
double tj=yj*kval[j*objs+id];
val += ti*(ai_new-ai_old);
val += tj*(aj_new-aj_old);
e[id]=val;
}
} | code for sm_80
Function : _Z8update_eiPdS_ddiiiidddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R3, c[0x0][0x188] ; /* 0x0000620000037a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R5, c[0x0][0x18c] ; /* 0x0000630000057a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R8, R3, c[0x0][0x160], R0 ; /* 0x0000580003087a24 */
/* 0x000fc800078e0200 */
/*00b0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e020d */
/*00c0*/ IMAD.WIDE R8, R8, R13.reuse, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x080fe200078e020d */
/*00d0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea6000c1e1b00 */
/*00e0*/ IMAD R12, R5, c[0x0][0x160], R0 ; /* 0x00005800050c7a24 */
/* 0x000fe400078e0200 */
/*00f0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1b00 */
/*0100*/ IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fcc00078e020d */
/*0110*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1b00 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R5, c[0x0][0x184] ; /* 0x0000610000057a02 */
/* 0x000fe20000000f00 */
/*0140*/ I2F.F64 R10, c[0x0][0x190] ; /* 0x00006400000a7b12 */
/* 0x000ee20000201c00 */
/*0150*/ MOV R16, c[0x0][0x1b0] ; /* 0x00006c0000107a02 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R17, c[0x0][0x1b4] ; /* 0x00006d0000117a02 */
/* 0x000fe40000000f00 */
/*0170*/ DADD R4, R4, -c[0x0][0x178] ; /* 0x80005e0004047629 */
/* 0x000e860000000000 */
/*0180*/ I2F.F64 R14, c[0x0][0x194] ; /* 0x00006500000e7b12 */
/* 0x000f260000201c00 */
/*0190*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x0041e40000000006 */
/*01a0*/ MOV R6, c[0x0][0x1a0] ; /* 0x0000680000067a02 */
/* 0x001fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff077624 */
/* 0x000fe200078e00ff */
/*01c0*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x008fca0000000000 */
/*01d0*/ DADD R6, R6, -c[0x0][0x198] ; /* 0x8000660006067629 */
/* 0x000e080000000000 */
/*01e0*/ DMUL R14, R12, R14 ; /* 0x0000000e0c0e7228 */
/* 0x010fc80000000000 */
/*01f0*/ DADD R8, R16, -c[0x0][0x1a8] ; /* 0x80006a0010087629 */
/* 0x000fc80000000000 */
/*0200*/ DFMA R4, R10, R6, R4 ; /* 0x000000060a04722b */
/* 0x001e0c0000000004 */
/*0210*/ DFMA R4, R14, R8, R4 ; /* 0x000000080e04722b */
/* 0x001e0e0000000004 */
/*0220*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void update_e(int objs,double* e,double* kval,double b_old,double b_new,int i,int j,int yi,int yj,double ai_old,double ai_new,double aj_old,double aj_new){
int id=blockDim.x * blockIdx.x + threadIdx.x;
if (id<objs){
double val=e[id];
val+=(b_new-b_old);
double ti=yi*kval[i*objs+id];
double tj=yj*kval[j*objs+id];
val += ti*(ai_new-ai_old);
val += tj*(aj_new-aj_old);
e[id]=val;
}
} | .file "tmpxft_0002212b_00000000-6_update_e.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL8update_eiPdS_ddiiiidddd, @function
_ZL8update_eiPdS_ddiiiidddd:
.LFB2052:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl %edi, 12(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 56(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 24(%rsp)
movl 288(%rsp), %eax
movl %eax, 28(%rsp)
movsd %xmm2, 64(%rsp)
movsd %xmm3, 72(%rsp)
movsd %xmm4, 80(%rsp)
movsd %xmm5, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 24(%rsp), %rax
movq %rax, 216(%rsp)
leaq 28(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 80(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _ZL8update_eiPdS_ddiiiidddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL8update_eiPdS_ddiiiidddd, .-_ZL8update_eiPdS_ddiiiidddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_eiPdS_ddiiiidddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8update_eiPdS_ddiiiidddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void update_e(int objs,double* e,double* kval,double b_old,double b_new,int i,int j,int yi,int yj,double ai_old,double ai_new,double aj_old,double aj_new){
int id=blockDim.x * blockIdx.x + threadIdx.x;
if (id<objs){
double val=e[id];
val+=(b_new-b_old);
double ti=yi*kval[i*objs+id];
double tj=yj*kval[j*objs+id];
val += ti*(ai_new-ai_old);
val += tj*(aj_new-aj_old);
e[id]=val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void update_e(int objs,double* e,double* kval,double b_old,double b_new,int i,int j,int yi,int yj,double ai_old,double ai_new,double aj_old,double aj_new){
int id=blockDim.x * blockIdx.x + threadIdx.x;
if (id<objs){
double val=e[id];
val+=(b_new-b_old);
double ti=yi*kval[i*objs+id];
double tj=yj*kval[j*objs+id];
val += ti*(ai_new-ai_old);
val += tj*(aj_new-aj_old);
e[id]=val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void update_e(int objs,double* e,double* kval,double b_old,double b_new,int i,int j,int yi,int yj,double ai_old,double ai_new,double aj_old,double aj_new){
int id=blockDim.x * blockIdx.x + threadIdx.x;
if (id<objs){
double val=e[id];
val+=(b_new-b_old);
double ti=yi*kval[i*objs+id];
double tj=yj*kval[j*objs+id];
val += ti*(ai_new-ai_old);
val += tj*(aj_new-aj_old);
e[id]=val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL8update_eiPdS_ddiiiidddd,"axG",@progbits,_ZL8update_eiPdS_ddiiiidddd,comdat
.globl _ZL8update_eiPdS_ddiiiidddd
.p2align 8
.type _ZL8update_eiPdS_ddiiiidddd,@function
_ZL8update_eiPdS_ddiiiidddd:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x64
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s12, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 3, v[3:4]
v_add_co_u32 v4, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[8:9], null, s13, s2, v[1:2]
s_clause 0x1
s_load_b256 s[12:19], s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x50
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[0:1], 3, v[8:9]
v_add_f64 v[8:9], s[10:11], -s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[10:11], s12
v_cvt_f64_i32_e32 v[12:13], s13
v_add_f64 v[14:15], s[16:17], -s[14:15]
global_load_b64 v[0:1], v[0:1], off
v_add_f64 v[6:7], v[8:9], v[6:7]
v_mul_f64 v[2:3], v[2:3], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[14:15], v[2:3], v[6:7]
v_add_f64 v[6:7], s[0:1], -s[18:19]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], v[12:13]
v_fma_f64 v[0:1], v[6:7], v[0:1], v[2:3]
global_store_b64 v[4:5], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL8update_eiPdS_ddiiiidddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL8update_eiPdS_ddiiiidddd,"axG",@progbits,_ZL8update_eiPdS_ddiiiidddd,comdat
.Lfunc_end0:
.size _ZL8update_eiPdS_ddiiiidddd, .Lfunc_end0-_ZL8update_eiPdS_ddiiiidddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL8update_eiPdS_ddiiiidddd
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _ZL8update_eiPdS_ddiiiidddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void update_e(int objs,double* e,double* kval,double b_old,double b_new,int i,int j,int yi,int yj,double ai_old,double ai_new,double aj_old,double aj_new){
int id=blockDim.x * blockIdx.x + threadIdx.x;
if (id<objs){
double val=e[id];
val+=(b_new-b_old);
double ti=yi*kval[i*objs+id];
double tj=yj*kval[j*objs+id];
val += ti*(ai_new-ai_old);
val += tj*(aj_new-aj_old);
e[id]=val;
}
} | .text
.file "update_e.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8update_eiPdS_ddiiiidddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R3, c[0x0][0x188] ; /* 0x0000620000037a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R5, c[0x0][0x18c] ; /* 0x0000630000057a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R8, R3, c[0x0][0x160], R0 ; /* 0x0000580003087a24 */
/* 0x000fc800078e0200 */
/*00b0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e020d */
/*00c0*/ IMAD.WIDE R8, R8, R13.reuse, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x080fe200078e020d */
/*00d0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea6000c1e1b00 */
/*00e0*/ IMAD R12, R5, c[0x0][0x160], R0 ; /* 0x00005800050c7a24 */
/* 0x000fe400078e0200 */
/*00f0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1b00 */
/*0100*/ IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fcc00078e020d */
/*0110*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1b00 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R5, c[0x0][0x184] ; /* 0x0000610000057a02 */
/* 0x000fe20000000f00 */
/*0140*/ I2F.F64 R10, c[0x0][0x190] ; /* 0x00006400000a7b12 */
/* 0x000ee20000201c00 */
/*0150*/ MOV R16, c[0x0][0x1b0] ; /* 0x00006c0000107a02 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R17, c[0x0][0x1b4] ; /* 0x00006d0000117a02 */
/* 0x000fe40000000f00 */
/*0170*/ DADD R4, R4, -c[0x0][0x178] ; /* 0x80005e0004047629 */
/* 0x000e860000000000 */
/*0180*/ I2F.F64 R14, c[0x0][0x194] ; /* 0x00006500000e7b12 */
/* 0x000f260000201c00 */
/*0190*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x0041e40000000006 */
/*01a0*/ MOV R6, c[0x0][0x1a0] ; /* 0x0000680000067a02 */
/* 0x001fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff077624 */
/* 0x000fe200078e00ff */
/*01c0*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x008fca0000000000 */
/*01d0*/ DADD R6, R6, -c[0x0][0x198] ; /* 0x8000660006067629 */
/* 0x000e080000000000 */
/*01e0*/ DMUL R14, R12, R14 ; /* 0x0000000e0c0e7228 */
/* 0x010fc80000000000 */
/*01f0*/ DADD R8, R16, -c[0x0][0x1a8] ; /* 0x80006a0010087629 */
/* 0x000fc80000000000 */
/*0200*/ DFMA R4, R10, R6, R4 ; /* 0x000000060a04722b */
/* 0x001e0c0000000004 */
/*0210*/ DFMA R4, R14, R8, R4 ; /* 0x000000080e04722b */
/* 0x001e0e0000000004 */
/*0220*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL8update_eiPdS_ddiiiidddd,"axG",@progbits,_ZL8update_eiPdS_ddiiiidddd,comdat
.globl _ZL8update_eiPdS_ddiiiidddd
.p2align 8
.type _ZL8update_eiPdS_ddiiiidddd,@function
_ZL8update_eiPdS_ddiiiidddd:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x64
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s12, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 3, v[3:4]
v_add_co_u32 v4, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[8:9], null, s13, s2, v[1:2]
s_clause 0x1
s_load_b256 s[12:19], s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x50
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[0:1], 3, v[8:9]
v_add_f64 v[8:9], s[10:11], -s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[10:11], s12
v_cvt_f64_i32_e32 v[12:13], s13
v_add_f64 v[14:15], s[16:17], -s[14:15]
global_load_b64 v[0:1], v[0:1], off
v_add_f64 v[6:7], v[8:9], v[6:7]
v_mul_f64 v[2:3], v[2:3], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[14:15], v[2:3], v[6:7]
v_add_f64 v[6:7], s[0:1], -s[18:19]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[0:1], v[12:13]
v_fma_f64 v[0:1], v[6:7], v[0:1], v[2:3]
global_store_b64 v[4:5], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL8update_eiPdS_ddiiiidddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL8update_eiPdS_ddiiiidddd,"axG",@progbits,_ZL8update_eiPdS_ddiiiidddd,comdat
.Lfunc_end0:
.size _ZL8update_eiPdS_ddiiiidddd, .Lfunc_end0-_ZL8update_eiPdS_ddiiiidddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL8update_eiPdS_ddiiiidddd
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _ZL8update_eiPdS_ddiiiidddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002212b_00000000-6_update_e.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL8update_eiPdS_ddiiiidddd, @function
_ZL8update_eiPdS_ddiiiidddd:
.LFB2052:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl %edi, 12(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 56(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 24(%rsp)
movl 288(%rsp), %eax
movl %eax, 28(%rsp)
movsd %xmm2, 64(%rsp)
movsd %xmm3, 72(%rsp)
movsd %xmm4, 80(%rsp)
movsd %xmm5, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 24(%rsp), %rax
movq %rax, 216(%rsp)
leaq 28(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 80(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _ZL8update_eiPdS_ddiiiidddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL8update_eiPdS_ddiiiidddd, .-_ZL8update_eiPdS_ddiiiidddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_eiPdS_ddiiiidddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8update_eiPdS_ddiiiidddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_e.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
/***
__shared__ 通过共享内存来完成线程间的通信
这一段代码 通过共享内存
***/
cudaError_t addWithCuda(int *c, const int *a, size_t size);
__global__ void addKernel(int *c, const int *a){
int i = threadIdx.x;
extern __shared__ int seme []; //声明一个全局的 共享内存的变量
seme[i] = a[i];
__syncthreads(); //同一个块的线程同步 等待seme将所有数据加载进来
if(i==0){ //第一个线程进行二次方
c[0] = 0;
for (int d=0; d<5; d++){
printf("seme[d] * seme [d] %d \n", d);
c[0] += seme[d] * seme [d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==1){
c[1] = 0;
for (int d=0; d<5; d++){
printf("c[1] += seme[d] %d \n", d);
c[1] += seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==2){
c[2] = 1;
for(int d=0; d<5; d++){
printf("c[2] *= seme[d] %d \n", d);
c[2] *= seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
}
int main(){
const int arraySize = 5;
const int a[arraySize] = {1, 2, 3, 4, 5};
int c[arraySize] = {0};
cudaError_t cudaStatus = addWithCuda(c, a, arraySize);
if (cudaStatus != cudaSuccess){
fprintf(stderr, "addWithCuda 失败");
return 1;
}
printf("\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n", c[1], c[0], c[2]);
cudaStatus = cudaThreadExit();
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cudaThreadExit 失败");
return 1;
}
return 0;
}
cudaError_t addWithCuda(int *c,const int *a, size_t size){
int *dev_a = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
addKernel<<<1, size, size * sizeof(int), 0>>>(dev_c, dev_a);
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cuda线程同步异常");
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
return cudaStatus;
} | .file "tmpxft_000a9f9b_00000000-6_SM_basic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9addKernelPiPKiPiPKi
.type _Z31__device_stub__Z9addKernelPiPKiPiPKi, @function
_Z31__device_stub__Z9addKernelPiPKiPiPKi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z9addKernelPiPKiPiPKi, .-_Z31__device_stub__Z9addKernelPiPKiPiPKi
.globl _Z9addKernelPiPKi
.type _Z9addKernelPiPKi, @function
_Z9addKernelPiPKi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPiPKi, .-_Z9addKernelPiPKi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cuda \345\210\206\351\205\215\345\206\205\345\255\230\345\244\261\350\264\245"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\344\273\216Device\345\220\221Hostcopy\346\225\260\346\215\256\345\244\261\350\264\245"
.section .rodata.str1.1
.LC2:
.string "cuda\347\272\277\347\250\213\345\220\214\346\255\245\345\274\202\345\270\270"
.text
.globl _Z11addWithCudaPiPKim
.type _Z11addWithCudaPiPKim, @function
_Z11addWithCudaPiPKim:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
leaq 0(,%rdx,4), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L20
movq %rsp, %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L21
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L22
movl %ebp, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
movl $2, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L20:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L22:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L23:
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
jmp .L16
.L24:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11addWithCudaPiPKim, .-_Z11addWithCudaPiPKim
.section .rodata.str1.1
.LC3:
.string "addWithCuda \345\244\261\350\264\245"
.section .rodata.str1.8
.align 8
.LC4:
.string "\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n"
.section .rodata.str1.1
.LC5:
.string "cudaThreadExit \345\244\261\350\264\245"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, (%rsp)
movl $2, 4(%rsp)
movl $3, 8(%rsp)
movl $4, 12(%rsp)
movl $5, 16(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movl $0, 48(%rsp)
movq %rsp, %rsi
leaq 32(%rsp), %rdi
movl $5, %edx
call _Z11addWithCudaPiPKim
testl %eax, %eax
jne .L32
movl 40(%rsp), %r8d
movl 32(%rsp), %ecx
movl 36(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadExit@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L33
.L26:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L34
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L26
.L33:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L26
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9addKernelPiPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
/***
__shared__ 通过共享内存来完成线程间的通信
这一段代码 通过共享内存
***/
cudaError_t addWithCuda(int *c, const int *a, size_t size);
__global__ void addKernel(int *c, const int *a){
int i = threadIdx.x;
extern __shared__ int seme []; //声明一个全局的 共享内存的变量
seme[i] = a[i];
__syncthreads(); //同一个块的线程同步 等待seme将所有数据加载进来
if(i==0){ //第一个线程进行二次方
c[0] = 0;
for (int d=0; d<5; d++){
printf("seme[d] * seme [d] %d \n", d);
c[0] += seme[d] * seme [d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==1){
c[1] = 0;
for (int d=0; d<5; d++){
printf("c[1] += seme[d] %d \n", d);
c[1] += seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==2){
c[2] = 1;
for(int d=0; d<5; d++){
printf("c[2] *= seme[d] %d \n", d);
c[2] *= seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
}
int main(){
const int arraySize = 5;
const int a[arraySize] = {1, 2, 3, 4, 5};
int c[arraySize] = {0};
cudaError_t cudaStatus = addWithCuda(c, a, arraySize);
if (cudaStatus != cudaSuccess){
fprintf(stderr, "addWithCuda 失败");
return 1;
}
printf("\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n", c[1], c[0], c[2]);
cudaStatus = cudaThreadExit();
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cudaThreadExit 失败");
return 1;
}
return 0;
}
cudaError_t addWithCuda(int *c,const int *a, size_t size){
int *dev_a = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
addKernel<<<1, size, size * sizeof(int), 0>>>(dev_c, dev_a);
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess){
fprintf(stderr, "cuda线程同步异常");
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
return cudaStatus;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
/***
__shared__ 通过共享内存来完成线程间的通信
这一段代码 通过共享内存
***/
hipError_t addWithCuda(int *c, const int *a, size_t size);
__global__ void addKernel(int *c, const int *a){
int i = threadIdx.x;
extern __shared__ int seme []; //声明一个全局的 共享内存的变量
seme[i] = a[i];
__syncthreads(); //同一个块的线程同步 等待seme将所有数据加载进来
if(i==0){ //第一个线程进行二次方
c[0] = 0;
for (int d=0; d<5; d++){
printf("seme[d] * seme [d] %d \n", d);
c[0] += seme[d] * seme [d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==1){
c[1] = 0;
for (int d=0; d<5; d++){
printf("c[1] += seme[d] %d \n", d);
c[1] += seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==2){
c[2] = 1;
for(int d=0; d<5; d++){
printf("c[2] *= seme[d] %d \n", d);
c[2] *= seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
}
int main(){
const int arraySize = 5;
const int a[arraySize] = {1, 2, 3, 4, 5};
int c[arraySize] = {0};
hipError_t cudaStatus = addWithCuda(c, a, arraySize);
if (cudaStatus != hipSuccess){
fprintf(stderr, "addWithCuda 失败");
return 1;
}
printf("\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n", c[1], c[0], c[2]);
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess){
fprintf(stderr, "hipDeviceReset 失败");
return 1;
}
return 0;
}
hipError_t addWithCuda(int *c,const int *a, size_t size){
int *dev_a = 0;
int *dev_c = 0;
hipError_t cudaStatus;
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
addKernel<<<1, size, size * sizeof(int), 0>>>(dev_c, dev_a);
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess){
fprintf(stderr, "cuda线程同步异常");
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/***
__shared__ 通过共享内存来完成线程间的通信
这一段代码 通过共享内存
***/
hipError_t addWithCuda(int *c, const int *a, size_t size);
__global__ void addKernel(int *c, const int *a){
int i = threadIdx.x;
extern __shared__ int seme []; //声明一个全局的 共享内存的变量
seme[i] = a[i];
__syncthreads(); //同一个块的线程同步 等待seme将所有数据加载进来
if(i==0){ //第一个线程进行二次方
c[0] = 0;
for (int d=0; d<5; d++){
printf("seme[d] * seme [d] %d \n", d);
c[0] += seme[d] * seme [d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==1){
c[1] = 0;
for (int d=0; d<5; d++){
printf("c[1] += seme[d] %d \n", d);
c[1] += seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
if(i==2){
c[2] = 1;
for(int d=0; d<5; d++){
printf("c[2] *= seme[d] %d \n", d);
c[2] *= seme[d];
}
printf("给 seme 赋值 %d ", i);
seme[i] = 0;
}
}
int main(){
const int arraySize = 5;
const int a[arraySize] = {1, 2, 3, 4, 5};
int c[arraySize] = {0};
hipError_t cudaStatus = addWithCuda(c, a, arraySize);
if (cudaStatus != hipSuccess){
fprintf(stderr, "addWithCuda 失败");
return 1;
}
printf("\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n", c[1], c[0], c[2]);
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess){
fprintf(stderr, "hipDeviceReset 失败");
return 1;
}
return 0;
}
hipError_t addWithCuda(int *c,const int *a, size_t size){
int *dev_a = 0;
int *dev_c = 0;
hipError_t cudaStatus;
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess){
fprintf(stderr, "cuda 分配内存失败");
goto Error;
}
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
addKernel<<<1, size, size * sizeof(int), 0>>>(dev_c, dev_a);
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess){
fprintf(stderr, "cuda线程同步异常");
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess){
fprintf(stderr, "从Device向Hostcopy数据失败");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
return cudaStatus;
} | .text
.file "SM_basic.hip"
.globl _Z24__device_stub__addKernelPiPKi # -- Begin function _Z24__device_stub__addKernelPiPKi
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKi,@function
_Z24__device_stub__addKernelPiPKi: # @_Z24__device_stub__addKernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKi, .Lfunc_end0-_Z24__device_stub__addKernelPiPKi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 32(%rsp)
movl $5, 48(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movl $5, %edx
callq _Z11addWithCudaPiPKim
testl %eax, %eax
jne .LBB1_1
# %bb.2:
movl (%rsp), %edx
movl 4(%rsp), %esi
movl 8(%rsp), %ecx
xorl %ebx, %ebx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_3
.LBB1_5:
movl %ebx, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB1_4
.LBB1_3:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $21, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB1_5
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKim # -- Begin function _Z11addWithCudaPiPKim
.p2align 4, 0x90
.type _Z11addWithCudaPiPKim,@function
_Z11addWithCudaPiPKim: # @_Z11addWithCudaPiPKim
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq (,%rdx,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.1:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.2:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_9
# %bb.3:
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_10
# %bb.6:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_13
# %bb.7:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $32, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_12
.LBB2_8:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $23, %esi
jmp .LBB2_11
.LBB2_9:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $32, %esi
jmp .LBB2_11
.LBB2_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
.LBB2_11:
movl $1, %edx
.LBB2_12:
callq fwrite@PLT
.LBB2_13:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11addWithCudaPiPKim, .Lfunc_end2-_Z11addWithCudaPiPKim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKi,@object # @_Z9addKernelPiPKi
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKi
.p2align 3, 0x0
_Z9addKernelPiPKi:
.quad _Z24__device_stub__addKernelPiPKi
.size _Z9addKernelPiPKi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda \345\244\261\350\264\245"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n"
.size .L.str.1, 64
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset \345\244\261\350\264\245"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cuda \345\210\206\351\205\215\345\206\205\345\255\230\345\244\261\350\264\245"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\344\273\216Device\345\220\221Hostcopy\346\225\260\346\215\256\345\244\261\350\264\245"
.size .L.str.4, 33
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "cuda\347\272\277\347\250\213\345\220\214\346\255\245\345\274\202\345\270\270"
.size .L.str.5, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a9f9b_00000000-6_SM_basic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9addKernelPiPKiPiPKi
.type _Z31__device_stub__Z9addKernelPiPKiPiPKi, @function
_Z31__device_stub__Z9addKernelPiPKiPiPKi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z9addKernelPiPKiPiPKi, .-_Z31__device_stub__Z9addKernelPiPKiPiPKi
.globl _Z9addKernelPiPKi
.type _Z9addKernelPiPKi, @function
_Z9addKernelPiPKi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPiPKi, .-_Z9addKernelPiPKi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cuda \345\210\206\351\205\215\345\206\205\345\255\230\345\244\261\350\264\245"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\344\273\216Device\345\220\221Hostcopy\346\225\260\346\215\256\345\244\261\350\264\245"
.section .rodata.str1.1
.LC2:
.string "cuda\347\272\277\347\250\213\345\220\214\346\255\245\345\274\202\345\270\270"
.text
.globl _Z11addWithCudaPiPKim
.type _Z11addWithCudaPiPKim, @function
_Z11addWithCudaPiPKim:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
leaq 0(,%rdx,4), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L20
movq %rsp, %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L21
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L22
movl %ebp, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
movl $2, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L20:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L22:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L23:
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
jmp .L16
.L24:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11addWithCudaPiPKim, .-_Z11addWithCudaPiPKim
.section .rodata.str1.1
.LC3:
.string "addWithCuda \345\244\261\350\264\245"
.section .rodata.str1.8
.align 8
.LC4:
.string "\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n"
.section .rodata.str1.1
.LC5:
.string "cudaThreadExit \345\244\261\350\264\245"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, (%rsp)
movl $2, 4(%rsp)
movl $3, 8(%rsp)
movl $4, 12(%rsp)
movl $5, 16(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movl $0, 48(%rsp)
movq %rsp, %rsi
leaq 32(%rsp), %rdi
movl $5, %edx
call _Z11addWithCudaPiPKim
testl %eax, %eax
jne .L32
movl 40(%rsp), %r8d
movl 32(%rsp), %ecx
movl 36(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadExit@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L33
.L26:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L34
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L26
.L33:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L26
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9addKernelPiPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SM_basic.hip"
.globl _Z24__device_stub__addKernelPiPKi # -- Begin function _Z24__device_stub__addKernelPiPKi
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKi,@function
_Z24__device_stub__addKernelPiPKi: # @_Z24__device_stub__addKernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKi, .Lfunc_end0-_Z24__device_stub__addKernelPiPKi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 32(%rsp)
movl $5, 48(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movl $5, %edx
callq _Z11addWithCudaPiPKim
testl %eax, %eax
jne .LBB1_1
# %bb.2:
movl (%rsp), %edx
movl 4(%rsp), %esi
movl 8(%rsp), %ecx
xorl %ebx, %ebx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_3
.LBB1_5:
movl %ebx, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB1_4
.LBB1_3:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $21, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB1_5
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKim # -- Begin function _Z11addWithCudaPiPKim
.p2align 4, 0x90
.type _Z11addWithCudaPiPKim,@function
_Z11addWithCudaPiPKim: # @_Z11addWithCudaPiPKim
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq (,%rdx,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.1:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.2:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_9
# %bb.3:
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_10
# %bb.6:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_13
# %bb.7:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $32, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_12
.LBB2_8:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $23, %esi
jmp .LBB2_11
.LBB2_9:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $32, %esi
jmp .LBB2_11
.LBB2_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
.LBB2_11:
movl $1, %edx
.LBB2_12:
callq fwrite@PLT
.LBB2_13:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11addWithCudaPiPKim, .Lfunc_end2-_Z11addWithCudaPiPKim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKi,@object # @_Z9addKernelPiPKi
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKi
.p2align 3, 0x0
_Z9addKernelPiPKi:
.quad _Z24__device_stub__addKernelPiPKi
.size _Z9addKernelPiPKi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda \345\244\261\350\264\245"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t1+2+3+4+5 = %d\n\t1^2+2^2+3^2+4^2+5^2 = %d\n\t1*2*3*4*5 = %d\n\n\n\n\n\n"
.size .L.str.1, 64
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset \345\244\261\350\264\245"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cuda \345\210\206\351\205\215\345\206\205\345\255\230\345\244\261\350\264\245"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\344\273\216Device\345\220\221Hostcopy\346\225\260\346\215\256\345\244\261\350\264\245"
.size .L.str.4, 33
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "cuda\347\272\277\347\250\213\345\220\214\346\255\245\345\274\202\345\270\270"
.size .L.str.5, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_copy_box.h"
// #define CUDA_DBG
// #define CUDA_DBG1
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
__global__ void d_do_copy_box ( int *fdp, int *tdp, int tbl_size,
int cx, int cy, int ex, int ey, int xy_size, int exy_size )
{
int *otdp, f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int block, i, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / xy_size ;
tdp += block * exy_size ;
i = f_idx % xy_size ;
y = i / cx ;
x = i % cx ;
if (( y >= ey ) && ( x >= ex ) && (( cy - y ) > ey ) && (( cx -x ) > ex ))
{
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
// edge_x/y are the distance from the cube_x/y to the embedded box ( defined
// by edge_x/y )
int
h_do_copy_box ( int *fromp, int *top, int tbl_size, int cube_x,
int cube_y, int edge_x, int edge_y )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int cube_xy = cube_y * cube_x ;
int edge_xy = (( cube_x - ( edge_x * 2 )) *
(( cube_y - ( edge_y * 2 )))) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d cube %d %d edge %d %d csize %d"
" esize %d\n",
__func__, fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
#endif
if ( tbl_size % cube_xy )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, cube_xy ) ;
return ( 0 ) ;
}
if ((( cube_x - ( edge_x * 2 )) < 0 ) ||
(( cube_y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cube_x, cube_y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
cudaThreadSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_box", top, ( tbl_size / cube_xy ) * edge_xy ) ;
#endif
return ( 1 ) ;
}
__global__ void d_do_copy_vec ( int *fdp, int *tdp, int tbl_size,
int from_size, int to_size )
{
int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
int k ;
while ( t_idx < tbl_size )
{
k = ( t_idx / to_size ) * from_size + ( t_idx % to_size ) ;
tdp[ t_idx ] = fdp[ k ] ;
t_idx += CUDA_MAX_THREADS ;
}
}
// total_size is the size of the copy ... in element
// copy the first from_size elements from fromp to top for every frame
int
h_do_copy_vec ( int *fromp, int *top, int total_size, int from_size,
int to_size )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( total_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p total %d from %d to %d \n",
__func__, fromp, top, total_size, from_size, to_size ) ;
#endif
if (( total_size % to_size ) || ( to_size > from_size ))
{
fprintf( stderr, "%s: size %d %d %d\n", total_size, from_size, to_size ) ;
return ( 0 ) ;
}
h_block_adj ( total_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_vec <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, total_size, from_size, to_size ) ;
cudaThreadSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_vec", top, total_size ) ;
#endif
return ( 1 ) ;
}
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
// obxyz_size is the old inner block size
// nbxyz_size is the new inner block size
// tbl_size is the old size
__global__ void d_do_copy_box_v2 ( int *fdp, int *tdp, int tbl_size,
int ex, int ey, int obxyz_size, int nbxyz_size, struct cs_xyz *d_xyzp,
int blk_in_x, int blk_in_y )
{
int f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int *otdp, cx, cy, cz, xy_size, exy_size, blk_idx, frame, block, i, j, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / obxyz_size ; // which block
i = block % blk_in_x ; // 0..blk_in_x-1
j = block / blk_in_x ; // 0..blk_in_y-1
if (( i == 0 ) || ( i == ( blk_in_x - 1 )))
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 2 ;
else
blk_idx = 1 ;
} else
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 1 ;
else
blk_idx = 0 ;
}
i = f_idx % obxyz_size ; // mea offset in the block
cx = d_xyzp[ blk_idx ].x ;
cy = d_xyzp[ blk_idx ].y ;
cz = d_xyzp[ blk_idx ].z ;
xy_size = cx * cy ;
exy_size = ( cx - ex * 2 ) * ( cy - ey * 2 ) ;
frame = i / xy_size ;
i = i % xy_size ;
y = i / cx ;
x = i % cx ;
if (( frame < cz ) && ( y >= ey ) && ( x >= ex ) &&
(( cy - y ) > ey ) && (( cx - x ) > ex ))
{
tdp += block * nbxyz_size + frame * exy_size ;
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
int
h_do_copy_box_v2 ( int *fromp, int *top, int tbl_size,
int edge_x, int edge_y, int blk_in_x, int blk_in_y, struct cs_xyz *d_cp,
struct cube *cp )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int obxyz_size = cp[0].x * cp[0].y * cp[0].z ;
int nbxyz_size = (( cp[0].x - ( edge_x * 2 )) *
(( cp[0].y - ( edge_y * 2 ))) * cp[0].z ) ;
#ifdef CUDA_DBG
int i ;
#endif
struct cube temp_cube[ CUBE_INFO_CNT ] ;
memcpy ( &temp_cube, cp, sizeof ( *cp )) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d edge %d %d blk %d %d cubep %p\n",
__func__, fromp, top, tbl_size, edge_x, edge_y, blk_in_x,
blk_in_y, cp ) ;
fprintf(stderr, " nsize %d osize %d\n", nbxyz_size, obxyz_size ) ;
#endif
if ( tbl_size % obxyz_size )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, obxyz_size ) ;
return ( 0 ) ;
}
if ((( cp[2].x - ( edge_x * 2 )) < 0 ) ||
(( cp[2].y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cp[2].x, cp[2].y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box_v2 <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, edge_x, edge_y, obxyz_size, nbxyz_size,
d_cp, blk_in_x, blk_in_y ) ;
cudaThreadSynchronize() ;
#ifdef CUDA_DBG
for ( i = 0 ; i < CUBE_INFO_CNT ; i++ )
{
temp_cube[i].x -= edge_x * 2 ;
temp_cube[i].y -= edge_y * 2 ;
}
dbg_p_d_data_i_mn_v2("copy_box_v2 done", top, ( tbl_size / obxyz_size ) *
nbxyz_size, 100, temp_cube, blk_in_x, blk_in_y ) ;
#endif
return ( 1 ) ;
} | .file "tmpxft_0019b713_00000000-6_cs_copy_box.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
.type _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii, @function
_Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii:
.LFB2104:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13d_do_copy_boxPiS_iiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii, .-_Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
.globl _Z13d_do_copy_boxPiS_iiiiiii
.type _Z13d_do_copy_boxPiS_iiiiiii, @function
_Z13d_do_copy_boxPiS_iiiiiii:
.LFB2105:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z13d_do_copy_boxPiS_iiiiiii, .-_Z13d_do_copy_boxPiS_iiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_do_copy_box"
.LC1:
.string "%s: error size %d cube %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "%s: error cube %d %d edge %d %d\n"
.text
.globl _Z13h_do_copy_boxPiS_iiiii
.type _Z13h_do_copy_boxPiS_iiiii, @function
_Z13h_do_copy_boxPiS_iiiii:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %r8d, %r13d
imull %ecx, %r13d
leal (%r9,%r9), %eax
movl %ecx, %r15d
subl %eax, %r15d
movl 144(%rsp), %eax
addl %eax, %eax
movl %r8d, %r14d
subl %eax, %r14d
movl %edx, %eax
cltd
idivl %r13d
movl %edx, 8(%rsp)
testl %edx, %edx
jne .L18
movl %ecx, %ebx
movl %r8d, %ebp
movl %r9d, %r12d
movl %r15d, %eax
orl %r14d, %eax
jns .L14
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
pushq %r9
.cfi_def_cfa_offset 160
movl %r8d, %r9d
movl %ecx, %r8d
leaq .LC0(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl 8(%rsp), %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %r13d, %r9d
movl 12(%rsp), %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, 8(%rsp)
jmp .L11
.L14:
leaq 44(%rsp), %rdx
movl $512, %esi
movl 12(%rsp), %edi
call _Z11h_block_adjiiPi@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl 44(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
call cudaThreadSynchronize@PLT
movl $1, 8(%rsp)
jmp .L11
.L20:
subq $8, %rsp
.cfi_def_cfa_offset 152
imull %r14d, %r15d
pushq %r15
.cfi_def_cfa_offset 160
pushq %r13
.cfi_def_cfa_offset 168
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl %r12d, %r9d
movl %ebp, %r8d
movl %ebx, %ecx
movl 44(%rsp), %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
addq $32, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z13h_do_copy_boxPiS_iiiii, .-_Z13h_do_copy_boxPiS_iiiii
.globl _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
.type _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii, @function
_Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii:
.LFB2106:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13d_do_copy_vecPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii, .-_Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
.globl _Z13d_do_copy_vecPiS_iii
.type _Z13d_do_copy_vecPiS_iii, @function
_Z13d_do_copy_vecPiS_iii:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z13d_do_copy_vecPiS_iii, .-_Z13d_do_copy_vecPiS_iii
.section .rodata.str1.1
.LC3:
.string "%s: size %d %d %d\n"
.text
.globl _Z13h_do_copy_vecPiS_iii
.type _Z13h_do_copy_vecPiS_iii, @function
_Z13h_do_copy_vecPiS_iii:
.LFB2078:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movl %edx, %ebp
movl %ecx, %r12d
movl %r8d, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %eax
cltd
idivl %r8d
testl %edx, %edx
jne .L35
movq %rdi, %r13
movq %rsi, %r14
cmpl %ecx, %r8d
jg .L35
leaq 12(%rsp), %rdx
movl $512, %esi
movl %ebp, %edi
call _Z11h_block_adjiiPi@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
call cudaThreadSynchronize@PLT
movl $1, %eax
jmp .L29
.L35:
movl %ebx, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
.L29:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl %ebx, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2078:
.size _Z13h_do_copy_vecPiS_iii, .-_Z13h_do_copy_vecPiS_iii
.globl _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
.type _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii, @function
_Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii:
.LFB2108:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii, .-_Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
.globl _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.type _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, @function
_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, .-_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.section .rodata.str1.1
.LC4:
.string "h_do_copy_box_v2"
.text
.globl _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.type _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, @function
_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube:
.LFB2079:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
movl %ecx, %r12d
movl %r8d, 8(%rsp)
movl %r9d, 40(%rsp)
movq 280(%rsp), %rax
movq %rax, 32(%rsp)
movq 288(%rsp), %rcx
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl 8(%rcx), %ebp
movl 12(%rcx), %r13d
movl 16(%rcx), %r14d
movl %ebp, %ebx
imull %r13d, %ebx
imull %r14d, %ebx
movdqu (%rcx), %xmm0
movaps %xmm0, 80(%rsp)
movdqu 16(%rcx), %xmm1
movaps %xmm1, 96(%rsp)
movq 32(%rcx), %rax
movq %rax, 112(%rsp)
movl %edx, %eax
cltd
idivl %ebx
movl %edx, 4(%rsp)
testl %edx, %edx
jne .L55
leal (%r12,%r12), %r15d
movl 88(%rcx), %r8d
cmpl %r15d, %r8d
jl .L50
movl 8(%rsp), %eax
addl %eax, %eax
movl %eax, 44(%rsp)
cmpl %eax, 92(%rcx)
jl .L50
leaq 52(%rsp), %rdx
movl $512, %esi
movl 12(%rsp), %edi
call _Z11h_block_adjiiPi@PLT
movl $512, 68(%rsp)
movl $1, 72(%rsp)
movl 52(%rsp), %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
call cudaThreadSynchronize@PLT
movl $1, 4(%rsp)
jmp .L47
.L55:
movl %ebx, %r9d
movl 12(%rsp), %r8d
leaq .LC4(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, 4(%rsp)
jmp .L47
.L50:
movl 8(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 280
pushq %r12
.cfi_def_cfa_offset 288
movl 92(%rcx), %r9d
leaq .LC4(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
.L47:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl 4(%rsp), %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movl 272(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 280
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 288
pushq 48(%rsp)
.cfi_def_cfa_offset 296
subl %r15d, %ebp
movl 68(%rsp), %eax
subl %eax, %r13d
imull %r13d, %ebp
imull %r14d, %ebp
pushq %rbp
.cfi_def_cfa_offset 304
movl %ebx, %r9d
movl 40(%rsp), %r8d
movl %r12d, %ecx
movl 44(%rsp), %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
addq $32, %rsp
.cfi_def_cfa_offset 272
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, .-_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii"
.section .rodata.str1.1
.LC6:
.string "_Z13d_do_copy_vecPiS_iii"
.LC7:
.string "_Z13d_do_copy_boxPiS_iiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2111:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13d_do_copy_vecPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13d_do_copy_boxPiS_iiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_copy_box.h"
// #define CUDA_DBG
// #define CUDA_DBG1
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
__global__ void d_do_copy_box ( int *fdp, int *tdp, int tbl_size,
int cx, int cy, int ex, int ey, int xy_size, int exy_size )
{
int *otdp, f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int block, i, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / xy_size ;
tdp += block * exy_size ;
i = f_idx % xy_size ;
y = i / cx ;
x = i % cx ;
if (( y >= ey ) && ( x >= ex ) && (( cy - y ) > ey ) && (( cx -x ) > ex ))
{
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
// edge_x/y are the distance from the cube_x/y to the embedded box ( defined
// by edge_x/y )
int
h_do_copy_box ( int *fromp, int *top, int tbl_size, int cube_x,
int cube_y, int edge_x, int edge_y )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int cube_xy = cube_y * cube_x ;
int edge_xy = (( cube_x - ( edge_x * 2 )) *
(( cube_y - ( edge_y * 2 )))) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d cube %d %d edge %d %d csize %d"
" esize %d\n",
__func__, fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
#endif
if ( tbl_size % cube_xy )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, cube_xy ) ;
return ( 0 ) ;
}
if ((( cube_x - ( edge_x * 2 )) < 0 ) ||
(( cube_y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cube_x, cube_y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
cudaThreadSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_box", top, ( tbl_size / cube_xy ) * edge_xy ) ;
#endif
return ( 1 ) ;
}
__global__ void d_do_copy_vec ( int *fdp, int *tdp, int tbl_size,
int from_size, int to_size )
{
int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
int k ;
while ( t_idx < tbl_size )
{
k = ( t_idx / to_size ) * from_size + ( t_idx % to_size ) ;
tdp[ t_idx ] = fdp[ k ] ;
t_idx += CUDA_MAX_THREADS ;
}
}
// total_size is the size of the copy ... in element
// copy the first from_size elements from fromp to top for every frame
int
h_do_copy_vec ( int *fromp, int *top, int total_size, int from_size,
int to_size )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( total_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p total %d from %d to %d \n",
__func__, fromp, top, total_size, from_size, to_size ) ;
#endif
if (( total_size % to_size ) || ( to_size > from_size ))
{
fprintf( stderr, "%s: size %d %d %d\n", total_size, from_size, to_size ) ;
return ( 0 ) ;
}
h_block_adj ( total_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_vec <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, total_size, from_size, to_size ) ;
cudaThreadSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_vec", top, total_size ) ;
#endif
return ( 1 ) ;
}
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
// obxyz_size is the old inner block size
// nbxyz_size is the new inner block size
// tbl_size is the old size
__global__ void d_do_copy_box_v2 ( int *fdp, int *tdp, int tbl_size,
int ex, int ey, int obxyz_size, int nbxyz_size, struct cs_xyz *d_xyzp,
int blk_in_x, int blk_in_y )
{
int f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int *otdp, cx, cy, cz, xy_size, exy_size, blk_idx, frame, block, i, j, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / obxyz_size ; // which block
i = block % blk_in_x ; // 0..blk_in_x-1
j = block / blk_in_x ; // 0..blk_in_y-1
if (( i == 0 ) || ( i == ( blk_in_x - 1 )))
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 2 ;
else
blk_idx = 1 ;
} else
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 1 ;
else
blk_idx = 0 ;
}
i = f_idx % obxyz_size ; // mea offset in the block
cx = d_xyzp[ blk_idx ].x ;
cy = d_xyzp[ blk_idx ].y ;
cz = d_xyzp[ blk_idx ].z ;
xy_size = cx * cy ;
exy_size = ( cx - ex * 2 ) * ( cy - ey * 2 ) ;
frame = i / xy_size ;
i = i % xy_size ;
y = i / cx ;
x = i % cx ;
if (( frame < cz ) && ( y >= ey ) && ( x >= ex ) &&
(( cy - y ) > ey ) && (( cx - x ) > ex ))
{
tdp += block * nbxyz_size + frame * exy_size ;
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
int
h_do_copy_box_v2 ( int *fromp, int *top, int tbl_size,
int edge_x, int edge_y, int blk_in_x, int blk_in_y, struct cs_xyz *d_cp,
struct cube *cp )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int obxyz_size = cp[0].x * cp[0].y * cp[0].z ;
int nbxyz_size = (( cp[0].x - ( edge_x * 2 )) *
(( cp[0].y - ( edge_y * 2 ))) * cp[0].z ) ;
#ifdef CUDA_DBG
int i ;
#endif
struct cube temp_cube[ CUBE_INFO_CNT ] ;
memcpy ( &temp_cube, cp, sizeof ( *cp )) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d edge %d %d blk %d %d cubep %p\n",
__func__, fromp, top, tbl_size, edge_x, edge_y, blk_in_x,
blk_in_y, cp ) ;
fprintf(stderr, " nsize %d osize %d\n", nbxyz_size, obxyz_size ) ;
#endif
if ( tbl_size % obxyz_size )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, obxyz_size ) ;
return ( 0 ) ;
}
if ((( cp[2].x - ( edge_x * 2 )) < 0 ) ||
(( cp[2].y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cp[2].x, cp[2].y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box_v2 <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, edge_x, edge_y, obxyz_size, nbxyz_size,
d_cp, blk_in_x, blk_in_y ) ;
cudaThreadSynchronize() ;
#ifdef CUDA_DBG
for ( i = 0 ; i < CUBE_INFO_CNT ; i++ )
{
temp_cube[i].x -= edge_x * 2 ;
temp_cube[i].y -= edge_y * 2 ;
}
dbg_p_d_data_i_mn_v2("copy_box_v2 done", top, ( tbl_size / obxyz_size ) *
nbxyz_size, 100, temp_cube, blk_in_x, blk_in_y ) ;
#endif
return ( 1 ) ;
} | #include <hip/hip_runtime.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_copy_box.h"
// #define CUDA_DBG
// #define CUDA_DBG1
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
__global__ void d_do_copy_box ( int *fdp, int *tdp, int tbl_size,
int cx, int cy, int ex, int ey, int xy_size, int exy_size )
{
int *otdp, f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int block, i, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / xy_size ;
tdp += block * exy_size ;
i = f_idx % xy_size ;
y = i / cx ;
x = i % cx ;
if (( y >= ey ) && ( x >= ex ) && (( cy - y ) > ey ) && (( cx -x ) > ex ))
{
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
// edge_x/y are the distance from the cube_x/y to the embedded box ( defined
// by edge_x/y )
int
h_do_copy_box ( int *fromp, int *top, int tbl_size, int cube_x,
int cube_y, int edge_x, int edge_y )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int cube_xy = cube_y * cube_x ;
int edge_xy = (( cube_x - ( edge_x * 2 )) *
(( cube_y - ( edge_y * 2 )))) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d cube %d %d edge %d %d csize %d"
" esize %d\n",
__func__, fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
#endif
if ( tbl_size % cube_xy )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, cube_xy ) ;
return ( 0 ) ;
}
if ((( cube_x - ( edge_x * 2 )) < 0 ) ||
(( cube_y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cube_x, cube_y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_box", top, ( tbl_size / cube_xy ) * edge_xy ) ;
#endif
return ( 1 ) ;
}
__global__ void d_do_copy_vec ( int *fdp, int *tdp, int tbl_size,
int from_size, int to_size )
{
int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
int k ;
while ( t_idx < tbl_size )
{
k = ( t_idx / to_size ) * from_size + ( t_idx % to_size ) ;
tdp[ t_idx ] = fdp[ k ] ;
t_idx += CUDA_MAX_THREADS ;
}
}
// total_size is the size of the copy ... in element
// copy the first from_size elements from fromp to top for every frame
int
h_do_copy_vec ( int *fromp, int *top, int total_size, int from_size,
int to_size )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( total_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p total %d from %d to %d \n",
__func__, fromp, top, total_size, from_size, to_size ) ;
#endif
if (( total_size % to_size ) || ( to_size > from_size ))
{
fprintf( stderr, "%s: size %d %d %d\n", total_size, from_size, to_size ) ;
return ( 0 ) ;
}
h_block_adj ( total_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_vec <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, total_size, from_size, to_size ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_vec", top, total_size ) ;
#endif
return ( 1 ) ;
}
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
// obxyz_size is the old inner block size
// nbxyz_size is the new inner block size
// tbl_size is the old size
__global__ void d_do_copy_box_v2 ( int *fdp, int *tdp, int tbl_size,
int ex, int ey, int obxyz_size, int nbxyz_size, struct cs_xyz *d_xyzp,
int blk_in_x, int blk_in_y )
{
int f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int *otdp, cx, cy, cz, xy_size, exy_size, blk_idx, frame, block, i, j, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / obxyz_size ; // which block
i = block % blk_in_x ; // 0..blk_in_x-1
j = block / blk_in_x ; // 0..blk_in_y-1
if (( i == 0 ) || ( i == ( blk_in_x - 1 )))
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 2 ;
else
blk_idx = 1 ;
} else
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 1 ;
else
blk_idx = 0 ;
}
i = f_idx % obxyz_size ; // mea offset in the block
cx = d_xyzp[ blk_idx ].x ;
cy = d_xyzp[ blk_idx ].y ;
cz = d_xyzp[ blk_idx ].z ;
xy_size = cx * cy ;
exy_size = ( cx - ex * 2 ) * ( cy - ey * 2 ) ;
frame = i / xy_size ;
i = i % xy_size ;
y = i / cx ;
x = i % cx ;
if (( frame < cz ) && ( y >= ey ) && ( x >= ex ) &&
(( cy - y ) > ey ) && (( cx - x ) > ex ))
{
tdp += block * nbxyz_size + frame * exy_size ;
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
int
h_do_copy_box_v2 ( int *fromp, int *top, int tbl_size,
int edge_x, int edge_y, int blk_in_x, int blk_in_y, struct cs_xyz *d_cp,
struct cube *cp )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int obxyz_size = cp[0].x * cp[0].y * cp[0].z ;
int nbxyz_size = (( cp[0].x - ( edge_x * 2 )) *
(( cp[0].y - ( edge_y * 2 ))) * cp[0].z ) ;
#ifdef CUDA_DBG
int i ;
#endif
struct cube temp_cube[ CUBE_INFO_CNT ] ;
memcpy ( &temp_cube, cp, sizeof ( *cp )) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d edge %d %d blk %d %d cubep %p\n",
__func__, fromp, top, tbl_size, edge_x, edge_y, blk_in_x,
blk_in_y, cp ) ;
fprintf(stderr, " nsize %d osize %d\n", nbxyz_size, obxyz_size ) ;
#endif
if ( tbl_size % obxyz_size )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, obxyz_size ) ;
return ( 0 ) ;
}
if ((( cp[2].x - ( edge_x * 2 )) < 0 ) ||
(( cp[2].y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cp[2].x, cp[2].y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box_v2 <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, edge_x, edge_y, obxyz_size, nbxyz_size,
d_cp, blk_in_x, blk_in_y ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
for ( i = 0 ; i < CUBE_INFO_CNT ; i++ )
{
temp_cube[i].x -= edge_x * 2 ;
temp_cube[i].y -= edge_y * 2 ;
}
dbg_p_d_data_i_mn_v2("copy_box_v2 done", top, ( tbl_size / obxyz_size ) *
nbxyz_size, 100, temp_cube, blk_in_x, blk_in_y ) ;
#endif
return ( 1 ) ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_copy_box.h"
// #define CUDA_DBG
// #define CUDA_DBG1
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
__global__ void d_do_copy_box ( int *fdp, int *tdp, int tbl_size,
int cx, int cy, int ex, int ey, int xy_size, int exy_size )
{
int *otdp, f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int block, i, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / xy_size ;
tdp += block * exy_size ;
i = f_idx % xy_size ;
y = i / cx ;
x = i % cx ;
if (( y >= ey ) && ( x >= ex ) && (( cy - y ) > ey ) && (( cx -x ) > ex ))
{
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
// edge_x/y are the distance from the cube_x/y to the embedded box ( defined
// by edge_x/y )
int
h_do_copy_box ( int *fromp, int *top, int tbl_size, int cube_x,
int cube_y, int edge_x, int edge_y )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int cube_xy = cube_y * cube_x ;
int edge_xy = (( cube_x - ( edge_x * 2 )) *
(( cube_y - ( edge_y * 2 )))) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d cube %d %d edge %d %d csize %d"
" esize %d\n",
__func__, fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
#endif
if ( tbl_size % cube_xy )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, cube_xy ) ;
return ( 0 ) ;
}
if ((( cube_x - ( edge_x * 2 )) < 0 ) ||
(( cube_y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cube_x, cube_y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_box", top, ( tbl_size / cube_xy ) * edge_xy ) ;
#endif
return ( 1 ) ;
}
__global__ void d_do_copy_vec ( int *fdp, int *tdp, int tbl_size,
int from_size, int to_size )
{
int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
int k ;
while ( t_idx < tbl_size )
{
k = ( t_idx / to_size ) * from_size + ( t_idx % to_size ) ;
tdp[ t_idx ] = fdp[ k ] ;
t_idx += CUDA_MAX_THREADS ;
}
}
// total_size is the size of the copy ... in element
// copy the first from_size elements from fromp to top for every frame
int
h_do_copy_vec ( int *fromp, int *top, int total_size, int from_size,
int to_size )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( total_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p total %d from %d to %d \n",
__func__, fromp, top, total_size, from_size, to_size ) ;
#endif
if (( total_size % to_size ) || ( to_size > from_size ))
{
fprintf( stderr, "%s: size %d %d %d\n", total_size, from_size, to_size ) ;
return ( 0 ) ;
}
h_block_adj ( total_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_vec <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, total_size, from_size, to_size ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_vec", top, total_size ) ;
#endif
return ( 1 ) ;
}
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
// obxyz_size is the old inner block size
// nbxyz_size is the new inner block size
// tbl_size is the old size
__global__ void d_do_copy_box_v2 ( int *fdp, int *tdp, int tbl_size,
int ex, int ey, int obxyz_size, int nbxyz_size, struct cs_xyz *d_xyzp,
int blk_in_x, int blk_in_y )
{
int f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int *otdp, cx, cy, cz, xy_size, exy_size, blk_idx, frame, block, i, j, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / obxyz_size ; // which block
i = block % blk_in_x ; // 0..blk_in_x-1
j = block / blk_in_x ; // 0..blk_in_y-1
if (( i == 0 ) || ( i == ( blk_in_x - 1 )))
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 2 ;
else
blk_idx = 1 ;
} else
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 1 ;
else
blk_idx = 0 ;
}
i = f_idx % obxyz_size ; // mea offset in the block
cx = d_xyzp[ blk_idx ].x ;
cy = d_xyzp[ blk_idx ].y ;
cz = d_xyzp[ blk_idx ].z ;
xy_size = cx * cy ;
exy_size = ( cx - ex * 2 ) * ( cy - ey * 2 ) ;
frame = i / xy_size ;
i = i % xy_size ;
y = i / cx ;
x = i % cx ;
if (( frame < cz ) && ( y >= ey ) && ( x >= ex ) &&
(( cy - y ) > ey ) && (( cx - x ) > ex ))
{
tdp += block * nbxyz_size + frame * exy_size ;
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
int
h_do_copy_box_v2 ( int *fromp, int *top, int tbl_size,
int edge_x, int edge_y, int blk_in_x, int blk_in_y, struct cs_xyz *d_cp,
struct cube *cp )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int obxyz_size = cp[0].x * cp[0].y * cp[0].z ;
int nbxyz_size = (( cp[0].x - ( edge_x * 2 )) *
(( cp[0].y - ( edge_y * 2 ))) * cp[0].z ) ;
#ifdef CUDA_DBG
int i ;
#endif
struct cube temp_cube[ CUBE_INFO_CNT ] ;
memcpy ( &temp_cube, cp, sizeof ( *cp )) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d edge %d %d blk %d %d cubep %p\n",
__func__, fromp, top, tbl_size, edge_x, edge_y, blk_in_x,
blk_in_y, cp ) ;
fprintf(stderr, " nsize %d osize %d\n", nbxyz_size, obxyz_size ) ;
#endif
if ( tbl_size % obxyz_size )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, obxyz_size ) ;
return ( 0 ) ;
}
if ((( cp[2].x - ( edge_x * 2 )) < 0 ) ||
(( cp[2].y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cp[2].x, cp[2].y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box_v2 <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, edge_x, edge_y, obxyz_size, nbxyz_size,
d_cp, blk_in_x, blk_in_y ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
for ( i = 0 ; i < CUBE_INFO_CNT ; i++ )
{
temp_cube[i].x -= edge_x * 2 ;
temp_cube[i].y -= edge_y * 2 ;
}
dbg_p_d_data_i_mn_v2("copy_box_v2 done", top, ( tbl_size / obxyz_size ) *
nbxyz_size, 100, temp_cube, blk_in_x, blk_in_y ) ;
#endif
return ( 1 ) ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13d_do_copy_boxPiS_iiiiiii
.globl _Z13d_do_copy_boxPiS_iiiiiii
.p2align 8
.type _Z13d_do_copy_boxPiS_iiiiiii,@function
_Z13d_do_copy_boxPiS_iiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x14
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s14, s12, 31
s_ashr_i32 s15, s4, 31
s_add_i32 s2, s12, s14
s_add_i32 s8, s4, s15
s_xor_b32 s16, s2, s14
s_xor_b32 s17, s8, s15
v_cvt_f32_u32_e32 v0, s16
v_cvt_f32_u32_e32 v2, s17
s_sub_i32 s2, 0, s16
s_sub_i32 s8, 0, s17
s_sub_i32 s20, 0, s12
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_sub_i32 s21, 0, s4
s_sub_i32 s22, 0, s6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v3, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s2, v3
v_mul_lo_u32 v4, s8, v2
s_load_b128 s[8:11], s[0:1], 0x0
s_lshl_b32 s0, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_sub_i32 s19, s4, s0
v_mul_hi_u32 v5, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, v2, v4
v_sub_nc_u32_e32 v0, 0, v1
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v4, v2, v4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, 0x1fffe00, v1
v_add_nc_u32_e32 v0, 0xfe000200, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v1
s_or_b32 s18, vcc_lo, s18
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v1, v2
v_xor_b32_e32 v5, v5, v2
v_xor_b32_e32 v2, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v3
v_mul_lo_u32 v7, v6, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v7
v_add_nc_u32_e32 v7, 1, v6
v_subrev_nc_u32_e32 v8, s16, v5
v_cmp_le_u32_e32 vcc_lo, s16, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
v_add_nc_u32_e32 v7, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s16, v5
v_cndmask_b32_e32 v5, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v2
v_sub_nc_u32_e32 v5, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, s20, v5, v[1:2]
v_mul_lo_u32 v2, v5, s12
v_ashrrev_i32_e32 v6, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v6, v2
v_add_nc_u32_e32 v7, v1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v7, v7, v6
v_xor_b32_e32 v6, s15, v6
v_mul_hi_u32 v8, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v8, s17
v_sub_nc_u32_e32 v7, v7, v9
v_add_nc_u32_e32 v9, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s17, v7
v_cmp_le_u32_e32 vcc_lo, s17, v7
v_dual_cndmask_b32 v8, v8, v9 :: v_dual_cndmask_b32 v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, 1, v8
v_cmp_le_u32_e32 vcc_lo, s17, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_xor_b32_e32 v7, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v7, v6
v_mul_lo_u32 v6, s20, v5
v_mul_lo_u32 v7, s21, v8
v_mad_u64_u32 v[9:10], null, s4, v8, s[4:5]
v_sub_nc_u32_e32 v11, s5, v8
v_cmp_le_i32_e32 vcc_lo, s7, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add3_u32 v10, v1, v7, v6
v_add3_u32 v2, v9, v2, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_i32_e64 s1, s7, v11
v_cmp_le_i32_e64 s0, s6, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s2, s6, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v8, s7, v8
v_mul_lo_u32 v5, v5, s13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_mul_lo_u32 v8, v8, s19
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add3_u32 v8, s22, v1, v8
global_load_b32 v2, v[9:10], off
v_add3_u32 v7, v8, v7, v6
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v5, v7
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13d_do_copy_boxPiS_iiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13d_do_copy_boxPiS_iiiiiii, .Lfunc_end0-_Z13d_do_copy_boxPiS_iiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13d_do_copy_vecPiS_iii
.globl _Z13d_do_copy_vecPiS_iii
.p2align 8
.type _Z13d_do_copy_vecPiS_iii,@function
_Z13d_do_copy_vecPiS_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_3
s_load_b64 s[10:11], s[0:1], 0x14
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s11, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s11, s3
s_xor_b32 s8, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s4, 0, s8
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_load_b128 s[4:7], s[0:1], 0x0
s_sub_i32 s1, s10, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v2
v_xor_b32_e32 v3, v3, v2
v_xor_b32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v0
v_mul_lo_u32 v5, v4, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_subrev_nc_u32_e32 v5, s8, v3
v_cmp_le_u32_e32 vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v6, 1, v4
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v3
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
v_xor_b32_e32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v3, v2
v_mad_u64_u32 v[2:3], null, s1, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, 0x1fffe00, v1
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s6, v2
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13d_do_copy_vecPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13d_do_copy_vecPiS_iii, .Lfunc_end1-_Z13d_do_copy_vecPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.globl _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.p2align 8
.type _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii,@function
_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB2_9
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x14
s_load_b128 s[8:11], s[0:1], 0x28
s_mov_b32 s23, 0
s_mov_b32 s25, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s16, s6, 31
s_ashr_i32 s17, s10, 31
s_add_i32 s2, s6, s16
s_add_i32 s12, s10, s17
s_xor_b32 s18, s2, s16
s_xor_b32 s19, s12, s17
v_cvt_f32_u32_e32 v0, s18
v_cvt_f32_u32_e32 v1, s19
s_sub_i32 s2, 0, s18
s_sub_i32 s12, 0, s19
s_add_i32 s20, s10, -1
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v1, v1
s_add_i32 s11, s11, -1
s_lshl_b32 s21, s4, 1
s_lshl_b32 s22, s5, 1
s_sub_i32 s24, 0, s6
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s2, v0
v_mul_lo_u32 v4, s12, v1
s_load_b128 s[12:15], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
v_mul_hi_u32 v4, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v0, v2
v_add_nc_u32_e32 v7, v1, v4
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 0x1fffe00, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v3
s_or_b32 s25, vcc_lo, s25
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execz .LBB2_9
.LBB2_3:
v_ashrrev_i32_e32 v0, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v3, v0
v_xor_b32_e32 v1, v1, v0
v_xor_b32_e32 v0, s16, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v6
v_mul_lo_u32 v4, v2, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v4
v_subrev_nc_u32_e32 v8, s18, v1
v_cmp_le_u32_e32 vcc_lo, s18, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v8 :: v_dual_add_nc_u32 v4, 1, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s18, v1
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v2, v4, vcc_lo
v_xor_b32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v1, v0
v_ashrrev_i32_e32 v0, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v8, v0
v_xor_b32_e32 v1, v1, v0
v_xor_b32_e32 v0, s17, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v7
v_mul_lo_u32 v4, v2, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v4, 1, v2
v_subrev_nc_u32_e32 v9, s19, v1
v_cmp_le_u32_e32 vcc_lo, s19, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v9
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s19, v1
v_cndmask_b32_e32 v1, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v0
v_sub_nc_u32_e32 v2, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v2, s10
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_sub_nc_u32_e32 v0, v8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 0, v0
v_cmp_ne_u32_e64 s1, s20, v0
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s1, exec_lo, s1
v_cmp_eq_u32_e64 s0, s11, v2
v_mov_b32_e32 v1, s23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
v_cndmask_b32_e64 v0, 0, 1, s0
s_and_not1_saveexec_b32 s1, s1
v_cmp_eq_u32_e64 s0, s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
v_cndmask_b32_e64 v4, 1, 2, s0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v0, 12, s[8:9]
v_mul_lo_u32 v14, v8, s6
v_mov_b32_e32 v0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v1, 12, v[0:1]
global_load_b96 v[0:2], v[9:10], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v1, v0
v_ashrrev_i32_e32 v15, 31, v0
v_ashrrev_i32_e32 v11, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v4, v11
v_xor_b32_e32 v12, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v9, v12
v_rcp_iflag_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v13, 0x4f7ffffe, v9
v_mad_u64_u32 v[9:10], null, s24, v8, v[3:4]
v_sub_nc_u32_e32 v10, 0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v9
v_sub_nc_u32_e32 v14, v9, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v3, v14
v_cvt_u32_f32_e32 v13, v13
v_xor_b32_e32 v14, v14, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v10, v13
v_xor_b32_e32 v9, v9, v11
v_mul_hi_u32 v10, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, v13, v10
v_mul_hi_u32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v10, v12
v_sub_nc_u32_e32 v13, v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v16, v13, v12
v_cmp_ge_u32_e32 vcc_lo, v13, v12
v_dual_cndmask_b32 v13, v13, v16 :: v_dual_add_nc_u32 v14, 1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v10, v14, vcc_lo
v_add_nc_u32_e32 v14, v0, v15
v_cmp_ge_u32_e32 vcc_lo, v13, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v16, 1, v10
v_xor_b32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v10, v16, vcc_lo
v_cvt_f32_u32_e32 v11, v14
v_sub_nc_u32_e32 v13, 0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v10, v9
v_rcp_iflag_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v10, v9
v_mul_lo_u32 v4, v4, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, 0x4f7ffffe, v11
v_cmp_lt_i32_e64 s1, v9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v10, v10
v_sub_nc_u32_e32 v4, v3, v4
v_mad_u64_u32 v[11:12], null, s24, v8, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v13, v10
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v10, v4
v_add_nc_u32_e32 v13, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v10, v4
v_xor_b32_e32 v10, v13, v12
v_xor_b32_e32 v12, v12, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v10, v4
v_mul_lo_u32 v13, v4, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v10, v13
v_add_nc_u32_e32 v13, 1, v4
v_sub_nc_u32_e32 v16, v10, v14
v_cmp_ge_u32_e32 vcc_lo, v10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v13, vcc_lo
v_cndmask_b32_e32 v10, v10, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, 1, v4
v_cmp_ge_u32_e32 vcc_lo, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v13, vcc_lo
v_xor_b32_e32 v4, v4, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v4, v12
v_mul_lo_u32 v4, v10, v0
v_cmp_le_i32_e32 vcc_lo, s5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v11, v4
v_sub_nc_u32_e32 v4, v1, v10
v_cmp_le_i32_e64 s0, s4, v11
v_sub_nc_u32_e32 v12, v0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_i32_e64 s2, s5, v4
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, s4, v12
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[3:4]
v_subrev_nc_u32_e32 v4, s21, v0
v_subrev_nc_u32_e32 v0, s22, v1
v_subrev_nc_u32_e32 v1, s4, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s12, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
global_load_b32 v2, v[12:13], off
v_mul_lo_u32 v12, v0, v4
v_mul_lo_u32 v0, v8, s7
v_subrev_nc_u32_e32 v13, s5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, v9, v[0:1]
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v13, v4, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s14, v0
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v8
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
global_store_b32 v[0:1], v2, off
s_branch .LBB2_2
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, .Lfunc_end2-_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13d_do_copy_boxPiS_iiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z13d_do_copy_boxPiS_iiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13d_do_copy_vecPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13d_do_copy_vecPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <arpa/inet.h>
#include <math.h>
#include "cs_cuda.h"
#include "cs_dbg.h"
#include "cs_helper.h"
#include "cs_copy_box.h"
// #define CUDA_DBG
// #define CUDA_DBG1
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
__global__ void d_do_copy_box ( int *fdp, int *tdp, int tbl_size,
int cx, int cy, int ex, int ey, int xy_size, int exy_size )
{
int *otdp, f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int block, i, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / xy_size ;
tdp += block * exy_size ;
i = f_idx % xy_size ;
y = i / cx ;
x = i % cx ;
if (( y >= ey ) && ( x >= ex ) && (( cy - y ) > ey ) && (( cx -x ) > ex ))
{
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
// edge_x/y are the distance from the cube_x/y to the embedded box ( defined
// by edge_x/y )
int
h_do_copy_box ( int *fromp, int *top, int tbl_size, int cube_x,
int cube_y, int edge_x, int edge_y )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int cube_xy = cube_y * cube_x ;
int edge_xy = (( cube_x - ( edge_x * 2 )) *
(( cube_y - ( edge_y * 2 )))) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d cube %d %d edge %d %d csize %d"
" esize %d\n",
__func__, fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
#endif
if ( tbl_size % cube_xy )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, cube_xy ) ;
return ( 0 ) ;
}
if ((( cube_x - ( edge_x * 2 )) < 0 ) ||
(( cube_y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cube_x, cube_y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, cube_x, cube_y, edge_x, edge_y,
cube_xy, edge_xy ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_box", top, ( tbl_size / cube_xy ) * edge_xy ) ;
#endif
return ( 1 ) ;
}
__global__ void d_do_copy_vec ( int *fdp, int *tdp, int tbl_size,
int from_size, int to_size )
{
int t_idx = blockIdx.x * blockDim.x + threadIdx.x;
int k ;
while ( t_idx < tbl_size )
{
k = ( t_idx / to_size ) * from_size + ( t_idx % to_size ) ;
tdp[ t_idx ] = fdp[ k ] ;
t_idx += CUDA_MAX_THREADS ;
}
}
// total_size is the size of the copy ... in element
// copy the first from_size elements from fromp to top for every frame
int
h_do_copy_vec ( int *fromp, int *top, int total_size, int from_size,
int to_size )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( total_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p total %d from %d to %d \n",
__func__, fromp, top, total_size, from_size, to_size ) ;
#endif
if (( total_size % to_size ) || ( to_size > from_size ))
{
fprintf( stderr, "%s: size %d %d %d\n", total_size, from_size, to_size ) ;
return ( 0 ) ;
}
h_block_adj ( total_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_vec <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, total_size, from_size, to_size ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
dbg_p_d_data_i("copy_vec", top, total_size ) ;
#endif
return ( 1 ) ;
}
// ex, ey, and exy_size are the embedded dimensions/size
// ex/ey are from the point to the edge of the cx/cy
// obxyz_size is the old inner block size
// nbxyz_size is the new inner block size
// tbl_size is the old size
__global__ void d_do_copy_box_v2 ( int *fdp, int *tdp, int tbl_size,
int ex, int ey, int obxyz_size, int nbxyz_size, struct cs_xyz *d_xyzp,
int blk_in_x, int blk_in_y )
{
int f_idx = blockIdx.x * blockDim.x + threadIdx.x;
int *otdp, cx, cy, cz, xy_size, exy_size, blk_idx, frame, block, i, j, x, y ;
otdp = tdp ;
while ( f_idx < tbl_size )
{
tdp = otdp ;
block = f_idx / obxyz_size ; // which block
i = block % blk_in_x ; // 0..blk_in_x-1
j = block / blk_in_x ; // 0..blk_in_y-1
if (( i == 0 ) || ( i == ( blk_in_x - 1 )))
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 2 ;
else
blk_idx = 1 ;
} else
{
if (( j == 0 ) || ( j == ( blk_in_y - 1 )))
blk_idx = 1 ;
else
blk_idx = 0 ;
}
i = f_idx % obxyz_size ; // mea offset in the block
cx = d_xyzp[ blk_idx ].x ;
cy = d_xyzp[ blk_idx ].y ;
cz = d_xyzp[ blk_idx ].z ;
xy_size = cx * cy ;
exy_size = ( cx - ex * 2 ) * ( cy - ey * 2 ) ;
frame = i / xy_size ;
i = i % xy_size ;
y = i / cx ;
x = i % cx ;
if (( frame < cz ) && ( y >= ey ) && ( x >= ex ) &&
(( cy - y ) > ey ) && (( cx - x ) > ex ))
{
tdp += block * nbxyz_size + frame * exy_size ;
i = ( y - ey ) * ( cx - 2 * ex ) + ( x - ex ) ;
tdp [ i ] = fdp [ f_idx ] ;
}
f_idx += CUDA_MAX_THREADS ;
}
}
int
h_do_copy_box_v2 ( int *fromp, int *top, int tbl_size,
int edge_x, int edge_y, int blk_in_x, int blk_in_y, struct cs_xyz *d_cp,
struct cube *cp )
{
int nThreadsPerBlock = 512;
int nBlocks ; // = ( tbl_size + ( nThreadsPerBlock - 1 ))/nThreadsPerBlock ;
int obxyz_size = cp[0].x * cp[0].y * cp[0].z ;
int nbxyz_size = (( cp[0].x - ( edge_x * 2 )) *
(( cp[0].y - ( edge_y * 2 ))) * cp[0].z ) ;
#ifdef CUDA_DBG
int i ;
#endif
struct cube temp_cube[ CUBE_INFO_CNT ] ;
memcpy ( &temp_cube, cp, sizeof ( *cp )) ;
#ifdef CUDA_DBG1
fprintf(stderr, "%s: f %p t %p tblsize %d edge %d %d blk %d %d cubep %p\n",
__func__, fromp, top, tbl_size, edge_x, edge_y, blk_in_x,
blk_in_y, cp ) ;
fprintf(stderr, " nsize %d osize %d\n", nbxyz_size, obxyz_size ) ;
#endif
if ( tbl_size % obxyz_size )
{
fprintf(stderr, "%s: error size %d cube %d \n", __func__,
tbl_size, obxyz_size ) ;
return ( 0 ) ;
}
if ((( cp[2].x - ( edge_x * 2 )) < 0 ) ||
(( cp[2].y - ( edge_y * 2 )) < 0 ))
{
fprintf(stderr, "%s: error cube %d %d edge %d %d\n",
__func__, cp[2].x, cp[2].y, edge_x, edge_y ) ;
return ( 0 ) ;
}
h_block_adj ( tbl_size, nThreadsPerBlock, &nBlocks ) ;
d_do_copy_box_v2 <<< nBlocks, nThreadsPerBlock >>> (
fromp, top, tbl_size, edge_x, edge_y, obxyz_size, nbxyz_size,
d_cp, blk_in_x, blk_in_y ) ;
hipDeviceSynchronize() ;
#ifdef CUDA_DBG
for ( i = 0 ; i < CUBE_INFO_CNT ; i++ )
{
temp_cube[i].x -= edge_x * 2 ;
temp_cube[i].y -= edge_y * 2 ;
}
dbg_p_d_data_i_mn_v2("copy_box_v2 done", top, ( tbl_size / obxyz_size ) *
nbxyz_size, 100, temp_cube, blk_in_x, blk_in_y ) ;
#endif
return ( 1 ) ;
} | .text
.file "cs_copy_box.hip"
.globl _Z28__device_stub__d_do_copy_boxPiS_iiiiiii # -- Begin function _Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.p2align 4, 0x90
.type _Z28__device_stub__d_do_copy_boxPiS_iiiiiii,@function
_Z28__device_stub__d_do_copy_boxPiS_iiiiiii: # @_Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13d_do_copy_boxPiS_iiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__d_do_copy_boxPiS_iiiiiii, .Lfunc_end0-_Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.cfi_endproc
# -- End function
.globl _Z13h_do_copy_boxPiS_iiiii # -- Begin function _Z13h_do_copy_boxPiS_iiiii
.p2align 4, 0x90
.type _Z13h_do_copy_boxPiS_iiiii,@function
_Z13h_do_copy_boxPiS_iiiii: # @_Z13h_do_copy_boxPiS_iiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r9d killed $r9d def $r9
movl %edx, %r13d
movl %r8d, %r15d
imull %ecx, %r15d
movl %edx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .LBB1_1
# %bb.2:
movl %r8d, %ebx
movl %ecx, %r14d
movl 256(%rsp), %r10d
leal (%r9,%r9), %eax
movl %ecx, %r12d
subl %eax, %r12d
js .LBB1_4
# %bb.3:
leal (%r10,%r10), %eax
movl %ebx, %ebp
subl %eax, %ebp
js .LBB1_4
# %bb.5:
movq %rdi, 40(%rsp) # 8-byte Spill
movq %rsi, 48(%rsp) # 8-byte Spill
movq %r9, 56(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdx
movl %r13d, %edi
movl $512, %esi # imm = 0x200
callq _Z11h_block_adjiiPi
movl 8(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
imull %r12d, %ebp
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movq %rax, 112(%rsp)
movl %r13d, 36(%rsp)
movl %r14d, 32(%rsp)
movl %ebx, 28(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl 256(%rsp), %eax
movl %eax, 20(%rsp)
movl %r15d, 16(%rsp)
movl %ebp, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13d_do_copy_boxPiS_iiiiiii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
movl $1, %eax
.LBB1_8:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L__func__._Z13h_do_copy_boxPiS_iiiii, %edx
movl %r13d, %ecx
movl %r15d, %r8d
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
jmp .LBB1_8
.LBB1_4:
movq stderr(%rip), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.1, %esi
movl $.L__func__._Z13h_do_copy_boxPiS_iiiii, %edx
movl %r14d, %ecx
movl %ebx, %r8d
# kill: def $r9d killed $r9d killed $r9
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq fprintf
xorl %eax, %eax
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_8
.Lfunc_end1:
.size _Z13h_do_copy_boxPiS_iiiii, .Lfunc_end1-_Z13h_do_copy_boxPiS_iiiii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__d_do_copy_vecPiS_iii # -- Begin function _Z28__device_stub__d_do_copy_vecPiS_iii
.p2align 4, 0x90
.type _Z28__device_stub__d_do_copy_vecPiS_iii,@function
_Z28__device_stub__d_do_copy_vecPiS_iii: # @_Z28__device_stub__d_do_copy_vecPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13d_do_copy_vecPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__d_do_copy_vecPiS_iii, .Lfunc_end2-_Z28__device_stub__d_do_copy_vecPiS_iii
.cfi_endproc
# -- End function
.globl _Z13h_do_copy_vecPiS_iii # -- Begin function _Z13h_do_copy_vecPiS_iii
.p2align 4, 0x90
.type _Z13h_do_copy_vecPiS_iii,@function
_Z13h_do_copy_vecPiS_iii: # @_Z13h_do_copy_vecPiS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %edx, %eax
cltd
idivl %r8d
cmpl %ecx, %r8d
jg .LBB3_2
# %bb.1:
testl %edx, %edx
jne .LBB3_2
# %bb.3:
movq %rsi, %r12
movq %rdi, %r13
movq %rsp, %rdx
movl %r15d, %edi
movl $512, %esi # imm = 0x200
callq _Z11h_block_adjiiPi
movl (%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13d_do_copy_vecPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
callq hipDeviceSynchronize
.LBB3_6:
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str.2, %esi
movl %r15d, %edx
movl %r14d, %ecx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
jmp .LBB3_6
.Lfunc_end3:
.size _Z13h_do_copy_vecPiS_iii, .Lfunc_end3-_Z13h_do_copy_vecPiS_iii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii # -- Begin function _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.p2align 4, 0x90
.type _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii,@function
_Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii: # @_Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end4:
.size _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, .Lfunc_end4-_Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.cfi_endproc
# -- End function
.globl _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube # -- Begin function _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.p2align 4, 0x90
.type _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube,@function
_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube: # @_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r10d
movl %ecx, %r11d
movl %edx, %ebp
movq 304(%rsp), %r8
movl 8(%r8), %ebx
movl 12(%r8), %r13d
movl %r13d, %r12d
imull %ebx, %r12d
movl 16(%r8), %ecx
imull %ecx, %r12d
movl %edx, %eax
cltd
idivl %r12d
testl %edx, %edx
jne .LBB5_1
# %bb.2:
movl %ecx, 4(%rsp) # 4-byte Spill
leal (%r11,%r11), %r15d
movl 88(%r8), %ecx
cmpl %r15d, %ecx
jl .LBB5_4
# %bb.3:
leal (%r10,%r10), %r14d
cmpl %r14d, 92(%r8)
jl .LBB5_4
# %bb.5:
movq %rdi, 40(%rsp) # 8-byte Spill
movq %rsi, 48(%rsp) # 8-byte Spill
movl %r9d, (%rsp) # 4-byte Spill
movq %r11, 56(%rsp) # 8-byte Spill
movq %r10, 64(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdx
movl %ebp, %edi
movl $512, %esi # imm = 0x200
callq _Z11h_block_adjiiPi
movl 8(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6:
movq 296(%rsp), %rax
movl 288(%rsp), %ecx
subl %r15d, %ebx
subl %r14d, %r13d
imull %ebx, %r13d
imull 4(%rsp), %r13d # 4-byte Folded Reload
movq 40(%rsp), %rdx # 8-byte Reload
movq %rdx, 136(%rsp)
movq 48(%rsp), %rdx # 8-byte Reload
movq %rdx, 128(%rsp)
movl %ebp, 36(%rsp)
movq 56(%rsp), %rdx # 8-byte Reload
movl %edx, 32(%rsp)
movq 64(%rsp), %rdx # 8-byte Reload
movl %edx, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r13d, 20(%rsp)
movq %rax, 120(%rsp)
movl (%rsp), %eax # 4-byte Reload
movl %eax, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 28(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 20(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7:
callq hipDeviceSynchronize
movl $1, %eax
.LBB5_8:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_4:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rdi
movl 92(%r8), %r8d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.1, %esi
movl $.L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, %edx
movl %r11d, %r9d
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq fprintf
xorl %eax, %eax
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_8
.LBB5_1:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, %edx
movl %ebp, %ecx
movl %r12d, %r8d
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
jmp .LBB5_8
.Lfunc_end5:
.size _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, .Lfunc_end5-_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13d_do_copy_boxPiS_iiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13d_do_copy_vecPiS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13d_do_copy_boxPiS_iiiiiii,@object # @_Z13d_do_copy_boxPiS_iiiiiii
.section .rodata,"a",@progbits
.globl _Z13d_do_copy_boxPiS_iiiiiii
.p2align 3, 0x0
_Z13d_do_copy_boxPiS_iiiiiii:
.quad _Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.size _Z13d_do_copy_boxPiS_iiiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s: error size %d cube %d \n"
.size .L.str, 28
.type .L__func__._Z13h_do_copy_boxPiS_iiiii,@object # @__func__._Z13h_do_copy_boxPiS_iiiii
.L__func__._Z13h_do_copy_boxPiS_iiiii:
.asciz "h_do_copy_box"
.size .L__func__._Z13h_do_copy_boxPiS_iiiii, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s: error cube %d %d edge %d %d\n"
.size .L.str.1, 33
.type _Z13d_do_copy_vecPiS_iii,@object # @_Z13d_do_copy_vecPiS_iii
.section .rodata,"a",@progbits
.globl _Z13d_do_copy_vecPiS_iii
.p2align 3, 0x0
_Z13d_do_copy_vecPiS_iii:
.quad _Z28__device_stub__d_do_copy_vecPiS_iii
.size _Z13d_do_copy_vecPiS_iii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%s: size %d %d %d\n"
.size .L.str.2, 19
.type _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii,@object # @_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.section .rodata,"a",@progbits
.globl _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.p2align 3, 0x0
_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii:
.quad _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.size _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, 8
.type .L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube,@object # @__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.section .rodata.str1.1,"aMS",@progbits,1
.L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube:
.asciz "h_do_copy_box_v2"
.size .L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13d_do_copy_boxPiS_iiiiiii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13d_do_copy_vecPiS_iii"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii"
.size .L__unnamed_3, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.addrsig_sym _Z28__device_stub__d_do_copy_vecPiS_iii
.addrsig_sym _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13d_do_copy_boxPiS_iiiiiii
.addrsig_sym _Z13d_do_copy_vecPiS_iii
.addrsig_sym _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019b713_00000000-6_cs_copy_box.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
.type _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii, @function
_Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii:
.LFB2104:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13d_do_copy_boxPiS_iiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii, .-_Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
.globl _Z13d_do_copy_boxPiS_iiiiiii
.type _Z13d_do_copy_boxPiS_iiiiiii, @function
_Z13d_do_copy_boxPiS_iiiiiii:
.LFB2105:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z13d_do_copy_boxPiS_iiiiiii, .-_Z13d_do_copy_boxPiS_iiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_do_copy_box"
.LC1:
.string "%s: error size %d cube %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "%s: error cube %d %d edge %d %d\n"
.text
.globl _Z13h_do_copy_boxPiS_iiiii
.type _Z13h_do_copy_boxPiS_iiiii, @function
_Z13h_do_copy_boxPiS_iiiii:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %r8d, %r13d
imull %ecx, %r13d
leal (%r9,%r9), %eax
movl %ecx, %r15d
subl %eax, %r15d
movl 144(%rsp), %eax
addl %eax, %eax
movl %r8d, %r14d
subl %eax, %r14d
movl %edx, %eax
cltd
idivl %r13d
movl %edx, 8(%rsp)
testl %edx, %edx
jne .L18
movl %ecx, %ebx
movl %r8d, %ebp
movl %r9d, %r12d
movl %r15d, %eax
orl %r14d, %eax
jns .L14
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
pushq %r9
.cfi_def_cfa_offset 160
movl %r8d, %r9d
movl %ecx, %r8d
leaq .LC0(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl 8(%rsp), %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %r13d, %r9d
movl 12(%rsp), %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, 8(%rsp)
jmp .L11
.L14:
leaq 44(%rsp), %rdx
movl $512, %esi
movl 12(%rsp), %edi
call _Z11h_block_adjiiPi@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl 44(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
call cudaThreadSynchronize@PLT
movl $1, 8(%rsp)
jmp .L11
.L20:
subq $8, %rsp
.cfi_def_cfa_offset 152
imull %r14d, %r15d
pushq %r15
.cfi_def_cfa_offset 160
pushq %r13
.cfi_def_cfa_offset 168
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl %r12d, %r9d
movl %ebp, %r8d
movl %ebx, %ecx
movl 44(%rsp), %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z42__device_stub__Z13d_do_copy_boxPiS_iiiiiiiPiS_iiiiiii
addq $32, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z13h_do_copy_boxPiS_iiiii, .-_Z13h_do_copy_boxPiS_iiiii
.globl _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
.type _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii, @function
_Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii:
.LFB2106:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13d_do_copy_vecPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii, .-_Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
.globl _Z13d_do_copy_vecPiS_iii
.type _Z13d_do_copy_vecPiS_iii, @function
_Z13d_do_copy_vecPiS_iii:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z13d_do_copy_vecPiS_iii, .-_Z13d_do_copy_vecPiS_iii
.section .rodata.str1.1
.LC3:
.string "%s: size %d %d %d\n"
.text
.globl _Z13h_do_copy_vecPiS_iii
.type _Z13h_do_copy_vecPiS_iii, @function
_Z13h_do_copy_vecPiS_iii:
.LFB2078:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movl %edx, %ebp
movl %ecx, %r12d
movl %r8d, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %eax
cltd
idivl %r8d
testl %edx, %edx
jne .L35
movq %rdi, %r13
movq %rsi, %r14
cmpl %ecx, %r8d
jg .L35
leaq 12(%rsp), %rdx
movl $512, %esi
movl %ebp, %edi
call _Z11h_block_adjiiPi@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
call cudaThreadSynchronize@PLT
movl $1, %eax
jmp .L29
.L35:
movl %ebx, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
.L29:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl %ebx, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z38__device_stub__Z13d_do_copy_vecPiS_iiiPiS_iii
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2078:
.size _Z13h_do_copy_vecPiS_iii, .-_Z13h_do_copy_vecPiS_iii
.globl _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
.type _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii, @function
_Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii:
.LFB2108:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii, .-_Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
.globl _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.type _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, @function
_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, .-_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.section .rodata.str1.1
.LC4:
.string "h_do_copy_box_v2"
.text
.globl _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.type _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, @function
_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube:
.LFB2079:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
movl %ecx, %r12d
movl %r8d, 8(%rsp)
movl %r9d, 40(%rsp)
movq 280(%rsp), %rax
movq %rax, 32(%rsp)
movq 288(%rsp), %rcx
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl 8(%rcx), %ebp
movl 12(%rcx), %r13d
movl 16(%rcx), %r14d
movl %ebp, %ebx
imull %r13d, %ebx
imull %r14d, %ebx
movdqu (%rcx), %xmm0
movaps %xmm0, 80(%rsp)
movdqu 16(%rcx), %xmm1
movaps %xmm1, 96(%rsp)
movq 32(%rcx), %rax
movq %rax, 112(%rsp)
movl %edx, %eax
cltd
idivl %ebx
movl %edx, 4(%rsp)
testl %edx, %edx
jne .L55
leal (%r12,%r12), %r15d
movl 88(%rcx), %r8d
cmpl %r15d, %r8d
jl .L50
movl 8(%rsp), %eax
addl %eax, %eax
movl %eax, 44(%rsp)
cmpl %eax, 92(%rcx)
jl .L50
leaq 52(%rsp), %rdx
movl $512, %esi
movl 12(%rsp), %edi
call _Z11h_block_adjiiPi@PLT
movl $512, 68(%rsp)
movl $1, 72(%rsp)
movl 52(%rsp), %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
call cudaThreadSynchronize@PLT
movl $1, 4(%rsp)
jmp .L47
.L55:
movl %ebx, %r9d
movl 12(%rsp), %r8d
leaq .LC4(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, 4(%rsp)
jmp .L47
.L50:
movl 8(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 280
pushq %r12
.cfi_def_cfa_offset 288
movl 92(%rcx), %r9d
leaq .LC4(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
.L47:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl 4(%rsp), %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movl 272(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 280
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 288
pushq 48(%rsp)
.cfi_def_cfa_offset 296
subl %r15d, %ebp
movl 68(%rsp), %eax
subl %eax, %r13d
imull %r13d, %ebp
imull %r14d, %ebp
pushq %rbp
.cfi_def_cfa_offset 304
movl %ebx, %r9d
movl 40(%rsp), %r8d
movl %r12d, %ecx
movl 44(%rsp), %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z53__device_stub__Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyziiPiS_iiiiiP6cs_xyzii
addq $32, %rsp
.cfi_def_cfa_offset 272
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, .-_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii"
.section .rodata.str1.1
.LC6:
.string "_Z13d_do_copy_vecPiS_iii"
.LC7:
.string "_Z13d_do_copy_boxPiS_iiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2111:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13d_do_copy_vecPiS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13d_do_copy_boxPiS_iiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cs_copy_box.hip"
.globl _Z28__device_stub__d_do_copy_boxPiS_iiiiiii # -- Begin function _Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.p2align 4, 0x90
.type _Z28__device_stub__d_do_copy_boxPiS_iiiiiii,@function
_Z28__device_stub__d_do_copy_boxPiS_iiiiiii: # @_Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13d_do_copy_boxPiS_iiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__d_do_copy_boxPiS_iiiiiii, .Lfunc_end0-_Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.cfi_endproc
# -- End function
.globl _Z13h_do_copy_boxPiS_iiiii # -- Begin function _Z13h_do_copy_boxPiS_iiiii
.p2align 4, 0x90
.type _Z13h_do_copy_boxPiS_iiiii,@function
_Z13h_do_copy_boxPiS_iiiii: # @_Z13h_do_copy_boxPiS_iiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r9d killed $r9d def $r9
movl %edx, %r13d
movl %r8d, %r15d
imull %ecx, %r15d
movl %edx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .LBB1_1
# %bb.2:
movl %r8d, %ebx
movl %ecx, %r14d
movl 256(%rsp), %r10d
leal (%r9,%r9), %eax
movl %ecx, %r12d
subl %eax, %r12d
js .LBB1_4
# %bb.3:
leal (%r10,%r10), %eax
movl %ebx, %ebp
subl %eax, %ebp
js .LBB1_4
# %bb.5:
movq %rdi, 40(%rsp) # 8-byte Spill
movq %rsi, 48(%rsp) # 8-byte Spill
movq %r9, 56(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdx
movl %r13d, %edi
movl $512, %esi # imm = 0x200
callq _Z11h_block_adjiiPi
movl 8(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
imull %r12d, %ebp
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movq %rax, 112(%rsp)
movl %r13d, 36(%rsp)
movl %r14d, 32(%rsp)
movl %ebx, 28(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl 256(%rsp), %eax
movl %eax, 20(%rsp)
movl %r15d, 16(%rsp)
movl %ebp, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13d_do_copy_boxPiS_iiiiiii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
movl $1, %eax
.LBB1_8:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L__func__._Z13h_do_copy_boxPiS_iiiii, %edx
movl %r13d, %ecx
movl %r15d, %r8d
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
jmp .LBB1_8
.LBB1_4:
movq stderr(%rip), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.1, %esi
movl $.L__func__._Z13h_do_copy_boxPiS_iiiii, %edx
movl %r14d, %ecx
movl %ebx, %r8d
# kill: def $r9d killed $r9d killed $r9
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq fprintf
xorl %eax, %eax
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_8
.Lfunc_end1:
.size _Z13h_do_copy_boxPiS_iiiii, .Lfunc_end1-_Z13h_do_copy_boxPiS_iiiii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__d_do_copy_vecPiS_iii # -- Begin function _Z28__device_stub__d_do_copy_vecPiS_iii
.p2align 4, 0x90
.type _Z28__device_stub__d_do_copy_vecPiS_iii,@function
_Z28__device_stub__d_do_copy_vecPiS_iii: # @_Z28__device_stub__d_do_copy_vecPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13d_do_copy_vecPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__d_do_copy_vecPiS_iii, .Lfunc_end2-_Z28__device_stub__d_do_copy_vecPiS_iii
.cfi_endproc
# -- End function
.globl _Z13h_do_copy_vecPiS_iii # -- Begin function _Z13h_do_copy_vecPiS_iii
.p2align 4, 0x90
.type _Z13h_do_copy_vecPiS_iii,@function
_Z13h_do_copy_vecPiS_iii: # @_Z13h_do_copy_vecPiS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %edx, %eax
cltd
idivl %r8d
cmpl %ecx, %r8d
jg .LBB3_2
# %bb.1:
testl %edx, %edx
jne .LBB3_2
# %bb.3:
movq %rsi, %r12
movq %rdi, %r13
movq %rsp, %rdx
movl %r15d, %edi
movl $512, %esi # imm = 0x200
callq _Z11h_block_adjiiPi
movl (%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13d_do_copy_vecPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
callq hipDeviceSynchronize
.LBB3_6:
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str.2, %esi
movl %r15d, %edx
movl %r14d, %ecx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
jmp .LBB3_6
.Lfunc_end3:
.size _Z13h_do_copy_vecPiS_iii, .Lfunc_end3-_Z13h_do_copy_vecPiS_iii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii # -- Begin function _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.p2align 4, 0x90
.type _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii,@function
_Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii: # @_Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end4:
.size _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, .Lfunc_end4-_Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.cfi_endproc
# -- End function
.globl _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube # -- Begin function _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.p2align 4, 0x90
.type _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube,@function
_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube: # @_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r10d
movl %ecx, %r11d
movl %edx, %ebp
movq 304(%rsp), %r8
movl 8(%r8), %ebx
movl 12(%r8), %r13d
movl %r13d, %r12d
imull %ebx, %r12d
movl 16(%r8), %ecx
imull %ecx, %r12d
movl %edx, %eax
cltd
idivl %r12d
testl %edx, %edx
jne .LBB5_1
# %bb.2:
movl %ecx, 4(%rsp) # 4-byte Spill
leal (%r11,%r11), %r15d
movl 88(%r8), %ecx
cmpl %r15d, %ecx
jl .LBB5_4
# %bb.3:
leal (%r10,%r10), %r14d
cmpl %r14d, 92(%r8)
jl .LBB5_4
# %bb.5:
movq %rdi, 40(%rsp) # 8-byte Spill
movq %rsi, 48(%rsp) # 8-byte Spill
movl %r9d, (%rsp) # 4-byte Spill
movq %r11, 56(%rsp) # 8-byte Spill
movq %r10, 64(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdx
movl %ebp, %edi
movl $512, %esi # imm = 0x200
callq _Z11h_block_adjiiPi
movl 8(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6:
movq 296(%rsp), %rax
movl 288(%rsp), %ecx
subl %r15d, %ebx
subl %r14d, %r13d
imull %ebx, %r13d
imull 4(%rsp), %r13d # 4-byte Folded Reload
movq 40(%rsp), %rdx # 8-byte Reload
movq %rdx, 136(%rsp)
movq 48(%rsp), %rdx # 8-byte Reload
movq %rdx, 128(%rsp)
movl %ebp, 36(%rsp)
movq 56(%rsp), %rdx # 8-byte Reload
movl %edx, 32(%rsp)
movq 64(%rsp), %rdx # 8-byte Reload
movl %edx, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r13d, 20(%rsp)
movq %rax, 120(%rsp)
movl (%rsp), %eax # 4-byte Reload
movl %eax, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 28(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 20(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7:
callq hipDeviceSynchronize
movl $1, %eax
.LBB5_8:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_4:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rdi
movl 92(%r8), %r8d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.1, %esi
movl $.L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, %edx
movl %r11d, %r9d
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq fprintf
xorl %eax, %eax
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_8
.LBB5_1:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, %edx
movl %ebp, %ecx
movl %r12d, %r8d
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
jmp .LBB5_8
.Lfunc_end5:
.size _Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, .Lfunc_end5-_Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13d_do_copy_boxPiS_iiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13d_do_copy_vecPiS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13d_do_copy_boxPiS_iiiiiii,@object # @_Z13d_do_copy_boxPiS_iiiiiii
.section .rodata,"a",@progbits
.globl _Z13d_do_copy_boxPiS_iiiiiii
.p2align 3, 0x0
_Z13d_do_copy_boxPiS_iiiiiii:
.quad _Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.size _Z13d_do_copy_boxPiS_iiiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s: error size %d cube %d \n"
.size .L.str, 28
.type .L__func__._Z13h_do_copy_boxPiS_iiiii,@object # @__func__._Z13h_do_copy_boxPiS_iiiii
.L__func__._Z13h_do_copy_boxPiS_iiiii:
.asciz "h_do_copy_box"
.size .L__func__._Z13h_do_copy_boxPiS_iiiii, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s: error cube %d %d edge %d %d\n"
.size .L.str.1, 33
.type _Z13d_do_copy_vecPiS_iii,@object # @_Z13d_do_copy_vecPiS_iii
.section .rodata,"a",@progbits
.globl _Z13d_do_copy_vecPiS_iii
.p2align 3, 0x0
_Z13d_do_copy_vecPiS_iii:
.quad _Z28__device_stub__d_do_copy_vecPiS_iii
.size _Z13d_do_copy_vecPiS_iii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%s: size %d %d %d\n"
.size .L.str.2, 19
.type _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii,@object # @_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.section .rodata,"a",@progbits
.globl _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.p2align 3, 0x0
_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii:
.quad _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.size _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii, 8
.type .L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube,@object # @__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube
.section .rodata.str1.1,"aMS",@progbits,1
.L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube:
.asciz "h_do_copy_box_v2"
.size .L__func__._Z16h_do_copy_box_v2PiS_iiiiiP6cs_xyzP4cube, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13d_do_copy_boxPiS_iiiiiii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13d_do_copy_vecPiS_iii"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii"
.size .L__unnamed_3, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__d_do_copy_boxPiS_iiiiiii
.addrsig_sym _Z28__device_stub__d_do_copy_vecPiS_iii
.addrsig_sym _Z31__device_stub__d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13d_do_copy_boxPiS_iiiiiii
.addrsig_sym _Z13d_do_copy_vecPiS_iii
.addrsig_sym _Z16d_do_copy_box_v2PiS_iiiiiP6cs_xyzii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <cuda.h>
#define TILE_WIDTH 16
#define cudaCheckError() { \
cudaError_t e = cudaGetLastError(); \
if (e != cudaSuccess) { \
printf("CUDA error %s:%d: %s\n", __FILE__, __LINE__, \
cudaGetErrorString(e)); \
exit(1); \
} \
}
__global__ void MatrixMulKernel (float* Nd, float* Pd, int width, int height)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
float tempM, tempN;
if ((0*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(0*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((0*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(0*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int m=1; m <= (TILE_WIDTH + height - 1)/TILE_WIDTH; ++m)
{
Mds[ty][tx] = tempM;
Nds[tx][ty] = tempN;
__syncthreads();
if ((m*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(m*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((m*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(m*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int k=0; k<TILE_WIDTH; ++k)
Pvalue+=Mds[k][ty] * Nds[k][tx];
__syncthreads();
}
Pd[Row*width + Col] = Pvalue;
}
int main(int argc, char* argv[])
{
float *A_h, *C_h;
float *A_d, *C_d;
int i, width, height, size_A, size_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
srand(time(NULL));
if (argc != 3)
{
printf("Provide the problem size.\n");
return -1;
}
height = atoi(argv[1]);
width = atoi(argv[2]);
size_A = width * height * sizeof(float);
size_C = width* width * sizeof(float);
//memory allocation for host matrixes
A_h = (float *)malloc(size_A);
C_h = (float *)malloc(size_C);
if ((A_h == NULL) || (C_h == NULL))
{
printf("Could not allocate memory.\n");
return -2;
}
//initialization of matrixes
for (i = 0; i < width*height; i++) {
A_h[i] = (rand() % 100) / 100.00;
}
//memory allocation of device matrixes
cudaMalloc((void**) &A_d, size_A); cudaCheckError();
cudaMalloc((void**) &C_d, size_C); cudaCheckError();
//copy Host matrixes to Device matrixes
cudaMemcpy(A_d, A_h, size_A, cudaMemcpyHostToDevice); cudaCheckError();
//dimensions of device
dim3 dimGrid(((width-1)/TILE_WIDTH)+1, ((width-1)/TILE_WIDTH)+1, 1);
dim3 dimBLock(TILE_WIDTH,TILE_WIDTH,1);
cudaEventRecord(start);
//calculation of multiplication
MatrixMulKernel<<<dimGrid, dimBLock>>>(A_d, C_d, width, height);
cudaCheckError();
cudaEventRecord(stop);
//copy device results to host
cudaMemcpy(C_h, C_d, size_C, cudaMemcpyDeviceToHost); cudaCheckError();
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Milliseconds: %f\n", milliseconds);
//free device memory
cudaFree(A_d); cudaCheckError();
cudaFree(C_d); cudaCheckError();
//print results
// for (i = 0; i<width*height; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", A_h[i]);
// }
// printf("\n\n");
// printf("\n");
// for (i = 0; i<width*width; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", C_h[i]);
// }
// printf("\n\n");
// printf("\n");
} | code for sm_80
Function : _Z15MatrixMulKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fc600000001ff */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0080*/ LEA R3, R7, R0, 0x4 ; /* 0x0000000007037211 */
/* 0x001fc800078e20ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fc80003f06270 */
/*00a0*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fe40000746670 */
/*00b0*/ LEA R2, R5, R8, 0x4 ; /* 0x0000000805027211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fc80003f26270 */
/*00d0*/ ISETP.GE.OR P3, PT, R8, c[0x0][0x174], P1 ; /* 0x00005d0008007a0c */
/* 0x000fc60000f66670 */
/*00e0*/ @!P2 IMAD R12, R0, c[0x0][0x170], R2 ; /* 0x00005c00000caa24 */
/* 0x000fe400078e0202 */
/*00f0*/ @!P2 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0da424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R6, c[0x0][0x174] ; /* 0x00005d0000067a02 */
/* 0x000fc60000000f00 */
/*0110*/ @!P2 IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0ca625 */
/* 0x000fe200078e020d */
/*0120*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fc600000001ff */
/*0130*/ @!P3 MOV R15, 0x4 ; /* 0x00000004000fb802 */
/* 0x000fe20000000f00 */
/*0140*/ @!P2 LDG.E R9, [R12.64] ; /* 0x000000060c09a981 */
/* 0x000162000c1e1900 */
/*0150*/ ISETP.GE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f46270 */
/*0160*/ @!P3 IMAD R14, R8, c[0x0][0x170], R3 ; /* 0x00005c00080eba24 */
/* 0x000fc800078e0203 */
/*0170*/ @!P3 IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0eb625 */
/* 0x000fc800078e020f */
/*0180*/ IMAD R2, R3, c[0x0][0x170], R2 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0202 */
/*0190*/ @!P3 LDG.E R10, [R14.64] ; /* 0x000000060e0ab981 */
/* 0x000162000c1e1900 */
/*01a0*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe40000000f00 */
/*01b0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e020b */
/*01c0*/ @!P2 BRA 0x740 ; /* 0x000005700000a947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R11, R8, 0x10, RZ ; /* 0x00000010080b7810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R6, R6, 0xf, RZ ; /* 0x0000000f06067810 */
/* 0x000fe20007ffe0ff */
/*0200*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0210*/ IADD3 R13, R0, 0x10, RZ ; /* 0x00000010000d7810 */
/* 0x001fe20007ffe0ff */
/*0220*/ IMAD R16, R11, c[0x0][0x170], R0 ; /* 0x00005c000b107a24 */
/* 0x000fe200078e0200 */
/*0230*/ SHF.R.S32.HI R17, RZ, 0x1f, R6 ; /* 0x0000001fff117819 */
/* 0x000fc40000011406 */
/*0240*/ LEA R15, R8.reuse, 0x400, 0x6 ; /* 0x00000400080f7811 */
/* 0x040fe200078e30ff */
/*0250*/ IMAD R14, R13, c[0x0][0x170], R8 ; /* 0x00005c000d0e7a24 */
/* 0x000fe200078e0208 */
/*0260*/ LEA R16, R7, R16, 0x4 ; /* 0x0000001007107211 */
/* 0x000fe400078e20ff */
/*0270*/ SHF.L.U32 R7, R8, 0x2, RZ ; /* 0x0000000208077819 */
/* 0x000fe200000006ff */
/*0280*/ IMAD R14, R5, 0x10, R14 ; /* 0x00000010050e7824 */
/* 0x000fe200078e020e */
/*0290*/ LEA.HI R12, R17, R6, RZ, 0x4 ; /* 0x00000006110c7211 */
/* 0x000fe400078f20ff */
/*02a0*/ IADD3 R15, R15, R4, RZ ; /* 0x000000040f0f7210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fc40000000f00 */
/*02c0*/ LEA R18, R0, R7, 0x6 ; /* 0x0000000700127211 */
/* 0x000fe400078e30ff */
/*02d0*/ SHF.R.S32.HI R12, RZ, 0x4, R12 ; /* 0x00000004ff0c7819 */
/* 0x000fc6000001140c */
/*02e0*/ STS [R18], R9 ; /* 0x0000000912007388 */
/* 0x0201e20000000800 */
/*02f0*/ ISETP.GE.OR P2, PT, R13, c[0x0][0x174], P0 ; /* 0x00005d000d007a0c */
/* 0x000fe40000746670 */
/*0300*/ ISETP.GE.OR P3, PT, R11, c[0x0][0x174], P1 ; /* 0x00005d000b007a0c */
/* 0x000fe20000f66670 */
/*0310*/ STS [R15], R10 ; /* 0x0000000a0f007388 */
/* 0x0003e80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0330*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x001fca00000001ff */
/*0340*/ @!P2 MOV R5, 0x4 ; /* 0x000000040005a802 */
/* 0x000fe40000000f00 */
/*0350*/ @!P3 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff07b424 */
/* 0x000fe200078e00ff */
/*0360*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x002fe40000000f00 */
/*0370*/ @!P2 IMAD.WIDE R4, R14, R5, c[0x0][0x160] ; /* 0x000058000e04a625 */
/* 0x000fc800078e0205 */
/*0380*/ @!P3 IMAD.WIDE R6, R16, R7, c[0x0][0x160] ; /* 0x000058001006b625 */
/* 0x000fe200078e0207 */
/*0390*/ LDS R24, [R8.X4+0x400] ; /* 0x0004000008187984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e280000004800 */
/*03b0*/ LDS R28, [R8.X4+0x440] ; /* 0x00044000081c7984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R27, [R0.X4+0x40] ; /* 0x00004000001b7984 */
/* 0x000e680000004800 */
/*03d0*/ LDS R26, [R8.X4+0x480] ; /* 0x00048000081a7984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS R25, [R0.X4+0x80] ; /* 0x0000800000197984 */
/* 0x000ea80000004800 */
/*03f0*/ LDS R20, [R8.X4+0x4c0] ; /* 0x0004c00008147984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R23, [R0.X4+0xc0] ; /* 0x0000c00000177984 */
/* 0x000ee80000004800 */
/*0410*/ LDS R19, [R8.X4+0x500] ; /* 0x0005000008137984 */
/* 0x000fe80000004800 */
/*0420*/ LDS R22, [R0.X4+0x100] ; /* 0x0001000000167984 */
/* 0x000f280000004800 */
/*0430*/ @!P2 LDG.E R9, [R4.64] ; /* 0x000000060409a981 */
/* 0x000362000c1e1900 */
/*0440*/ FFMA R17, R24, R21, R17 ; /* 0x0000001518117223 */
/* 0x001fc60000000011 */
/*0450*/ @!P3 LDG.E R10, [R6.64] ; /* 0x00000006060ab981 */
/* 0x000162000c1e1900 */
/*0460*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0470*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LDS R21, [R8.X4+0x540] ; /* 0x0005400008157984 */
/* 0x000fe20000004800 */
/*0490*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ FFMA R17, R28, R27, R17 ; /* 0x0000001b1c117223 */
/* 0x002fe40000000011 */
/*04b0*/ LDS R24, [R0.X4+0x140] ; /* 0x0001400000187984 */
/* 0x000e620000004800 */
/*04c0*/ ISETP.LE.AND P2, PT, R12, UR4, PT ; /* 0x000000040c007c0c */
/* 0x000fc6000bf43270 */
/*04d0*/ LDS R4, [R8.X4+0x580] ; /* 0x0005800008047984 */
/* 0x000fe20000004800 */
/*04e0*/ FFMA R17, R26, R25, R17 ; /* 0x000000191a117223 */
/* 0x004fc60000000011 */
/*04f0*/ LDS R5, [R0.X4+0x180] ; /* 0x0001800000057984 */
/* 0x000ea80000004800 */
/*0500*/ LDS R6, [R8.X4+0x5c0] ; /* 0x0005c00008067984 */
/* 0x001fe20000004800 */
/*0510*/ FFMA R23, R20, R23, R17 ; /* 0x0000001714177223 */
/* 0x008fc60000000011 */
/*0520*/ LDS R7, [R0.X4+0x1c0] ; /* 0x0001c00000077984 */
/* 0x000e280000004800 */
/*0530*/ LDS R17, [R8.X4+0x600] ; /* 0x0006000008117984 */
/* 0x000fe20000004800 */
/*0540*/ FFMA R23, R19, R22, R23 ; /* 0x0000001613177223 */
/* 0x010fc60000000017 */
/*0550*/ LDS R20, [R0.X4+0x200] ; /* 0x0002000000147984 */
/* 0x000ee80000004800 */
/*0560*/ LDS R19, [R8.X4+0x640] ; /* 0x0006400008137984 */
/* 0x000fe80000004800 */
/*0570*/ LDS R22, [R0.X4+0x240] ; /* 0x0002400000167984 */
/* 0x000f220000004800 */
/*0580*/ FFMA R23, R21, R24, R23 ; /* 0x0000001815177223 */
/* 0x002fc60000000017 */
/*0590*/ LDS R21, [R8.X4+0x680] ; /* 0x0006800008157984 */
/* 0x000fe80000004800 */
/*05a0*/ LDS R24, [R0.X4+0x280] ; /* 0x0002800000187984 */
/* 0x000e620000004800 */
/*05b0*/ FFMA R23, R4, R5, R23 ; /* 0x0000000504177223 */
/* 0x004fc60000000017 */
/*05c0*/ LDS R4, [R8.X4+0x6c0] ; /* 0x0006c00008047984 */
/* 0x000fe80000004800 */
/*05d0*/ LDS R5, [R0.X4+0x2c0] ; /* 0x0002c00000057984 */
/* 0x000ea20000004800 */
/*05e0*/ FFMA R23, R6, R7, R23 ; /* 0x0000000706177223 */
/* 0x001fc60000000017 */
/*05f0*/ LDS R6, [R8.X4+0x700] ; /* 0x0007000008067984 */
/* 0x000fe80000004800 */
/*0600*/ LDS R7, [R0.X4+0x300] ; /* 0x0003000000077984 */
/* 0x000e220000004800 */
/*0610*/ FFMA R23, R17, R20, R23 ; /* 0x0000001411177223 */
/* 0x008fc60000000017 */
/*0620*/ LDS R17, [R8.X4+0x740] ; /* 0x0007400008117984 */
/* 0x000fe80000004800 */
/*0630*/ LDS R20, [R0.X4+0x340] ; /* 0x0003400000147984 */
/* 0x000ee20000004800 */
/*0640*/ FFMA R23, R19, R22, R23 ; /* 0x0000001613177223 */
/* 0x010fc60000000017 */
/*0650*/ LDS R22, [R8.X4+0x780] ; /* 0x0007800008167984 */
/* 0x000fe80000004800 */
/*0660*/ LDS R19, [R0.X4+0x380] ; /* 0x0003800000137984 */
/* 0x000f220000004800 */
/*0670*/ FFMA R21, R21, R24, R23 ; /* 0x0000001815157223 */
/* 0x002fc60000000017 */
/*0680*/ LDS R23, [R8.X4+0x7c0] ; /* 0x0007c00008177984 */
/* 0x000fe80000004800 */
/*0690*/ LDS R24, [R0.X4+0x3c0] ; /* 0x0003c00000187984 */
/* 0x000e620000004800 */
/*06a0*/ FFMA R4, R4, R5, R21 ; /* 0x0000000504047223 */
/* 0x004fe20000000015 */
/*06b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fc600000001ff */
/*06c0*/ FFMA R4, R6, R7, R4 ; /* 0x0000000706047223 */
/* 0x001fce0000000004 */
/*06d0*/ IMAD R16, R5.reuse, c[0x0][0x170], R16 ; /* 0x00005c0005107a24 */
/* 0x040fe400078e0210 */
/*06e0*/ IMAD R14, R5, c[0x0][0x170], R14 ; /* 0x00005c00050e7a24 */
/* 0x000fe400078e020e */
/*06f0*/ FFMA R4, R17, R20, R4 ; /* 0x0000001411047223 */
/* 0x008fc80000000004 */
/*0700*/ FFMA R4, R22, R19, R4 ; /* 0x0000001316047223 */
/* 0x010fc80000000004 */
/*0710*/ FFMA R17, R23, R24, R4 ; /* 0x0000001817117223 */
/* 0x002fe20000000004 */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ @!P2 BRA 0x2e0 ; /* 0xfffffba00000a947 */
/* 0x000fea000383ffff */
/*0740*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe2000c101906 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <cuda.h>
#define TILE_WIDTH 16
#define cudaCheckError() { \
cudaError_t e = cudaGetLastError(); \
if (e != cudaSuccess) { \
printf("CUDA error %s:%d: %s\n", __FILE__, __LINE__, \
cudaGetErrorString(e)); \
exit(1); \
} \
}
__global__ void MatrixMulKernel (float* Nd, float* Pd, int width, int height)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
float tempM, tempN;
if ((0*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(0*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((0*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(0*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int m=1; m <= (TILE_WIDTH + height - 1)/TILE_WIDTH; ++m)
{
Mds[ty][tx] = tempM;
Nds[tx][ty] = tempN;
__syncthreads();
if ((m*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(m*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((m*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(m*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int k=0; k<TILE_WIDTH; ++k)
Pvalue+=Mds[k][ty] * Nds[k][tx];
__syncthreads();
}
Pd[Row*width + Col] = Pvalue;
}
int main(int argc, char* argv[])
{
float *A_h, *C_h;
float *A_d, *C_d;
int i, width, height, size_A, size_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
srand(time(NULL));
if (argc != 3)
{
printf("Provide the problem size.\n");
return -1;
}
height = atoi(argv[1]);
width = atoi(argv[2]);
size_A = width * height * sizeof(float);
size_C = width* width * sizeof(float);
//memory allocation for host matrixes
A_h = (float *)malloc(size_A);
C_h = (float *)malloc(size_C);
if ((A_h == NULL) || (C_h == NULL))
{
printf("Could not allocate memory.\n");
return -2;
}
//initialization of matrixes
for (i = 0; i < width*height; i++) {
A_h[i] = (rand() % 100) / 100.00;
}
//memory allocation of device matrixes
cudaMalloc((void**) &A_d, size_A); cudaCheckError();
cudaMalloc((void**) &C_d, size_C); cudaCheckError();
//copy Host matrixes to Device matrixes
cudaMemcpy(A_d, A_h, size_A, cudaMemcpyHostToDevice); cudaCheckError();
//dimensions of device
dim3 dimGrid(((width-1)/TILE_WIDTH)+1, ((width-1)/TILE_WIDTH)+1, 1);
dim3 dimBLock(TILE_WIDTH,TILE_WIDTH,1);
cudaEventRecord(start);
//calculation of multiplication
MatrixMulKernel<<<dimGrid, dimBLock>>>(A_d, C_d, width, height);
cudaCheckError();
cudaEventRecord(stop);
//copy device results to host
cudaMemcpy(C_h, C_d, size_C, cudaMemcpyDeviceToHost); cudaCheckError();
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Milliseconds: %f\n", milliseconds);
//free device memory
cudaFree(A_d); cudaCheckError();
cudaFree(C_d); cudaCheckError();
//print results
// for (i = 0; i<width*height; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", A_h[i]);
// }
// printf("\n\n");
// printf("\n");
// for (i = 0; i<width*width; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", C_h[i]);
// }
// printf("\n\n");
// printf("\n");
} | .file "tmpxft_0016a229_00000000-6_MatrixMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
.type _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii, @function
_Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii, .-_Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
.globl _Z15MatrixMulKernelPfS_ii
.type _Z15MatrixMulKernelPfS_ii, @function
_Z15MatrixMulKernelPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15MatrixMulKernelPfS_ii, .-_Z15MatrixMulKernelPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Provide the problem size.\n"
.LC1:
.string "Could not allocate memory.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/nicklev/CUDA/master/MatrixMulKernel.cu"
.section .rodata.str1.1
.LC4:
.string "CUDA error %s:%d: %s\n"
.LC6:
.string "Milliseconds: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpl $3, %ebp
jne .L30
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 28(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 24(%rsp)
imull %eax, %r13d
movslq %r13d, %r12
leal 0(,%r13,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movl %ebp, %eax
imull %ebp, %eax
sall $2, %eax
cltq
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %r14, %r14
je .L14
testq %rax, %rax
je .L14
movq %r14, %rbx
leaq (%r14,%r12,4), %r12
testl %r13d, %r13d
jle .L16
.L17:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
.L16:
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
leaq 56(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L33
leal 14(%rbp), %eax
subl $1, %ebp
cmovns %ebp, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 80(%rsp)
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl $16, 92(%rsp)
movl $16, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 100(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
movq 56(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
movl $0, %eax
.L11:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L14:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-2, %eax
jmp .L11
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $104, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $105, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $108, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
jmp .L21
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $117, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $121, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $129, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $130, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z15MatrixMulKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <cuda.h>
#define TILE_WIDTH 16
#define cudaCheckError() { \
cudaError_t e = cudaGetLastError(); \
if (e != cudaSuccess) { \
printf("CUDA error %s:%d: %s\n", __FILE__, __LINE__, \
cudaGetErrorString(e)); \
exit(1); \
} \
}
__global__ void MatrixMulKernel (float* Nd, float* Pd, int width, int height)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
float tempM, tempN;
if ((0*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(0*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((0*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(0*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int m=1; m <= (TILE_WIDTH + height - 1)/TILE_WIDTH; ++m)
{
Mds[ty][tx] = tempM;
Nds[tx][ty] = tempN;
__syncthreads();
if ((m*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(m*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((m*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(m*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int k=0; k<TILE_WIDTH; ++k)
Pvalue+=Mds[k][ty] * Nds[k][tx];
__syncthreads();
}
Pd[Row*width + Col] = Pvalue;
}
int main(int argc, char* argv[])
{
float *A_h, *C_h;
float *A_d, *C_d;
int i, width, height, size_A, size_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
srand(time(NULL));
if (argc != 3)
{
printf("Provide the problem size.\n");
return -1;
}
height = atoi(argv[1]);
width = atoi(argv[2]);
size_A = width * height * sizeof(float);
size_C = width* width * sizeof(float);
//memory allocation for host matrixes
A_h = (float *)malloc(size_A);
C_h = (float *)malloc(size_C);
if ((A_h == NULL) || (C_h == NULL))
{
printf("Could not allocate memory.\n");
return -2;
}
//initialization of matrixes
for (i = 0; i < width*height; i++) {
A_h[i] = (rand() % 100) / 100.00;
}
//memory allocation of device matrixes
cudaMalloc((void**) &A_d, size_A); cudaCheckError();
cudaMalloc((void**) &C_d, size_C); cudaCheckError();
//copy Host matrixes to Device matrixes
cudaMemcpy(A_d, A_h, size_A, cudaMemcpyHostToDevice); cudaCheckError();
//dimensions of device
dim3 dimGrid(((width-1)/TILE_WIDTH)+1, ((width-1)/TILE_WIDTH)+1, 1);
dim3 dimBLock(TILE_WIDTH,TILE_WIDTH,1);
cudaEventRecord(start);
//calculation of multiplication
MatrixMulKernel<<<dimGrid, dimBLock>>>(A_d, C_d, width, height);
cudaCheckError();
cudaEventRecord(stop);
//copy device results to host
cudaMemcpy(C_h, C_d, size_C, cudaMemcpyDeviceToHost); cudaCheckError();
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Milliseconds: %f\n", milliseconds);
//free device memory
cudaFree(A_d); cudaCheckError();
cudaFree(C_d); cudaCheckError();
//print results
// for (i = 0; i<width*height; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", A_h[i]);
// }
// printf("\n\n");
// printf("\n");
// for (i = 0; i<width*width; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", C_h[i]);
// }
// printf("\n\n");
// printf("\n");
} | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define TILE_WIDTH 16
#define cudaCheckError() { \
hipError_t e = hipGetLastError(); \
if (e != hipSuccess) { \
printf("CUDA error %s:%d: %s\n", __FILE__, __LINE__, \
hipGetErrorString(e)); \
exit(1); \
} \
}
__global__ void MatrixMulKernel (float* Nd, float* Pd, int width, int height)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
float tempM, tempN;
if ((0*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(0*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((0*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(0*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int m=1; m <= (TILE_WIDTH + height - 1)/TILE_WIDTH; ++m)
{
Mds[ty][tx] = tempM;
Nds[tx][ty] = tempN;
__syncthreads();
if ((m*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(m*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((m*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(m*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int k=0; k<TILE_WIDTH; ++k)
Pvalue+=Mds[k][ty] * Nds[k][tx];
__syncthreads();
}
Pd[Row*width + Col] = Pvalue;
}
int main(int argc, char* argv[])
{
float *A_h, *C_h;
float *A_d, *C_d;
int i, width, height, size_A, size_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
srand(time(NULL));
if (argc != 3)
{
printf("Provide the problem size.\n");
return -1;
}
height = atoi(argv[1]);
width = atoi(argv[2]);
size_A = width * height * sizeof(float);
size_C = width* width * sizeof(float);
//memory allocation for host matrixes
A_h = (float *)malloc(size_A);
C_h = (float *)malloc(size_C);
if ((A_h == NULL) || (C_h == NULL))
{
printf("Could not allocate memory.\n");
return -2;
}
//initialization of matrixes
for (i = 0; i < width*height; i++) {
A_h[i] = (rand() % 100) / 100.00;
}
//memory allocation of device matrixes
hipMalloc((void**) &A_d, size_A); cudaCheckError();
hipMalloc((void**) &C_d, size_C); cudaCheckError();
//copy Host matrixes to Device matrixes
hipMemcpy(A_d, A_h, size_A, hipMemcpyHostToDevice); cudaCheckError();
//dimensions of device
dim3 dimGrid(((width-1)/TILE_WIDTH)+1, ((width-1)/TILE_WIDTH)+1, 1);
dim3 dimBLock(TILE_WIDTH,TILE_WIDTH,1);
hipEventRecord(start);
//calculation of multiplication
MatrixMulKernel<<<dimGrid, dimBLock>>>(A_d, C_d, width, height);
cudaCheckError();
hipEventRecord(stop);
//copy device results to host
hipMemcpy(C_h, C_d, size_C, hipMemcpyDeviceToHost); cudaCheckError();
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Milliseconds: %f\n", milliseconds);
//free device memory
hipFree(A_d); cudaCheckError();
hipFree(C_d); cudaCheckError();
//print results
// for (i = 0; i<width*height; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", A_h[i]);
// }
// printf("\n\n");
// printf("\n");
// for (i = 0; i<width*width; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", C_h[i]);
// }
// printf("\n\n");
// printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define TILE_WIDTH 16
#define cudaCheckError() { \
hipError_t e = hipGetLastError(); \
if (e != hipSuccess) { \
printf("CUDA error %s:%d: %s\n", __FILE__, __LINE__, \
hipGetErrorString(e)); \
exit(1); \
} \
}
__global__ void MatrixMulKernel (float* Nd, float* Pd, int width, int height)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
float tempM, tempN;
if ((0*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(0*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((0*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(0*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int m=1; m <= (TILE_WIDTH + height - 1)/TILE_WIDTH; ++m)
{
Mds[ty][tx] = tempM;
Nds[tx][ty] = tempN;
__syncthreads();
if ((m*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(m*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((m*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(m*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int k=0; k<TILE_WIDTH; ++k)
Pvalue+=Mds[k][ty] * Nds[k][tx];
__syncthreads();
}
Pd[Row*width + Col] = Pvalue;
}
int main(int argc, char* argv[])
{
float *A_h, *C_h;
float *A_d, *C_d;
int i, width, height, size_A, size_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
srand(time(NULL));
if (argc != 3)
{
printf("Provide the problem size.\n");
return -1;
}
height = atoi(argv[1]);
width = atoi(argv[2]);
size_A = width * height * sizeof(float);
size_C = width* width * sizeof(float);
//memory allocation for host matrixes
A_h = (float *)malloc(size_A);
C_h = (float *)malloc(size_C);
if ((A_h == NULL) || (C_h == NULL))
{
printf("Could not allocate memory.\n");
return -2;
}
//initialization of matrixes
for (i = 0; i < width*height; i++) {
A_h[i] = (rand() % 100) / 100.00;
}
//memory allocation of device matrixes
hipMalloc((void**) &A_d, size_A); cudaCheckError();
hipMalloc((void**) &C_d, size_C); cudaCheckError();
//copy Host matrixes to Device matrixes
hipMemcpy(A_d, A_h, size_A, hipMemcpyHostToDevice); cudaCheckError();
//dimensions of device
dim3 dimGrid(((width-1)/TILE_WIDTH)+1, ((width-1)/TILE_WIDTH)+1, 1);
dim3 dimBLock(TILE_WIDTH,TILE_WIDTH,1);
hipEventRecord(start);
//calculation of multiplication
MatrixMulKernel<<<dimGrid, dimBLock>>>(A_d, C_d, width, height);
cudaCheckError();
hipEventRecord(stop);
//copy device results to host
hipMemcpy(C_h, C_d, size_C, hipMemcpyDeviceToHost); cudaCheckError();
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Milliseconds: %f\n", milliseconds);
//free device memory
hipFree(A_d); cudaCheckError();
hipFree(C_d); cudaCheckError();
//print results
// for (i = 0; i<width*height; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", A_h[i]);
// }
// printf("\n\n");
// printf("\n");
// for (i = 0; i<width*width; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", C_h[i]);
// }
// printf("\n\n");
// printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_ii
.globl _Z15MatrixMulKernelPfS_ii
.p2align 8
.type _Z15MatrixMulKernelPfS_ii,@function
_Z15MatrixMulKernelPfS_ii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v3, 0x3ff, v0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s15, 4, v2
v_lshl_add_u32 v1, s14, 4, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[4:5], null, v2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s6, v4
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
global_load_b32 v4, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e64 s3, s5, v3
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_and_saveexec_b32 s8, s3
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[5:6], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s3, s6, v5
v_add_co_ci_u32_e64 v6, s3, s7, v6, s3
global_load_b32 v6, v[5:6], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v5, 0
s_cmp_lt_i32 s5, 1
s_mov_b32 s8, 1
s_cbranch_scc1 .LBB0_14
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b32_e32 v7, 2, v2
v_lshlrev_b32_e32 v9, 6, v3
s_add_i32 s3, s5, 15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_lshr_b32 s3, s3, 4
v_lshl_add_u32 v8, v2, 6, v5
v_add3_u32 v9, v9, v7, 0x400
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, 0x400, v5
s_max_i32 s9, s3, 1
.LBB0_6:
s_lshl_b32 s10, s8, 4
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
ds_store_b32 v9, v6
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v11, s10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e64 s3, s5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s11, s3
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[12:13], null, v11, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v4, v[11:12], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s11
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v11, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s5, v11
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s3
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v11, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v6, v[11:12], off
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s3, 0
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, s3, v7
v_add_nc_u32_e32 v12, s3, v10
s_add_i32 s3, s3, 64
ds_load_b32 v11, v11
ds_load_b32 v12, v12
s_cmpk_eq_i32 s3, 0x400
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v11, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s3, s8, 1
s_cmp_eq_u32 s8, s9
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
s_mov_b32 s8, s3
s_branch .LBB0_6
.LBB0_14:
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_ii, .Lfunc_end0-_Z15MatrixMulKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define TILE_WIDTH 16
#define cudaCheckError() { \
hipError_t e = hipGetLastError(); \
if (e != hipSuccess) { \
printf("CUDA error %s:%d: %s\n", __FILE__, __LINE__, \
hipGetErrorString(e)); \
exit(1); \
} \
}
__global__ void MatrixMulKernel (float* Nd, float* Pd, int width, int height)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
float tempM, tempN;
if ((0*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(0*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((0*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(0*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int m=1; m <= (TILE_WIDTH + height - 1)/TILE_WIDTH; ++m)
{
Mds[ty][tx] = tempM;
Nds[tx][ty] = tempN;
__syncthreads();
if ((m*TILE_WIDTH + ty) < height && Row < width)
tempM = Nd[(m*TILE_WIDTH + ty)*width + Col];
else
tempM = 0.0;
if ((m*TILE_WIDTH + tx) < height && Col < width)
tempN = Nd[(m*TILE_WIDTH + tx)*width + Row];
else
tempN = 0.0;
for (int k=0; k<TILE_WIDTH; ++k)
Pvalue+=Mds[k][ty] * Nds[k][tx];
__syncthreads();
}
Pd[Row*width + Col] = Pvalue;
}
int main(int argc, char* argv[])
{
float *A_h, *C_h;
float *A_d, *C_d;
int i, width, height, size_A, size_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
srand(time(NULL));
if (argc != 3)
{
printf("Provide the problem size.\n");
return -1;
}
height = atoi(argv[1]);
width = atoi(argv[2]);
size_A = width * height * sizeof(float);
size_C = width* width * sizeof(float);
//memory allocation for host matrixes
A_h = (float *)malloc(size_A);
C_h = (float *)malloc(size_C);
if ((A_h == NULL) || (C_h == NULL))
{
printf("Could not allocate memory.\n");
return -2;
}
//initialization of matrixes
for (i = 0; i < width*height; i++) {
A_h[i] = (rand() % 100) / 100.00;
}
//memory allocation of device matrixes
hipMalloc((void**) &A_d, size_A); cudaCheckError();
hipMalloc((void**) &C_d, size_C); cudaCheckError();
//copy Host matrixes to Device matrixes
hipMemcpy(A_d, A_h, size_A, hipMemcpyHostToDevice); cudaCheckError();
//dimensions of device
dim3 dimGrid(((width-1)/TILE_WIDTH)+1, ((width-1)/TILE_WIDTH)+1, 1);
dim3 dimBLock(TILE_WIDTH,TILE_WIDTH,1);
hipEventRecord(start);
//calculation of multiplication
MatrixMulKernel<<<dimGrid, dimBLock>>>(A_d, C_d, width, height);
cudaCheckError();
hipEventRecord(stop);
//copy device results to host
hipMemcpy(C_h, C_d, size_C, hipMemcpyDeviceToHost); cudaCheckError();
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Milliseconds: %f\n", milliseconds);
//free device memory
hipFree(A_d); cudaCheckError();
hipFree(C_d); cudaCheckError();
//print results
// for (i = 0; i<width*height; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", A_h[i]);
// }
// printf("\n\n");
// printf("\n");
// for (i = 0; i<width*width; i++)
// {
// if(i % width == 0)
// {
// printf("\n");
// }
// printf("%f, ", C_h[i]);
// }
// printf("\n\n");
// printf("\n");
} | .text
.file "MatrixMulKernel.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_ii # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_ii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_ii,@function
_Z30__device_stub__MatrixMulKernelPfS_ii: # @_Z30__device_stub__MatrixMulKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_ii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $3, %ebp
jne .LBB1_1
# %bb.2:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %r14d
imull %r15d, %r14d
leal (,%r14,4), %eax
movl %r12d, %ebx
imull %r12d, %ebx
shll $2, %ebx
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movslq %ebx, %rbx
movq %rbx, %rdi
callq malloc
testq %rbp, %rbp
je .LBB1_26
# %bb.3:
testq %rax, %rax
je .LBB1_26
# %bb.4: # %.preheader
movq %r15, 96(%rsp) # 8-byte Spill
movq %rax, 88(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
movl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_6
.LBB1_7: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.10:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 24(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
movq 96(%rsp), %r14 # 8-byte Reload
jne .LBB1_13
# %bb.14:
leal -1(%r12), %eax
leal 14(%r12), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
incl %ecx
movq %rcx, %r13
shlq $32, %r13
orq %rcx, %r13
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl %r12d, 36(%rsp)
movl %r14d, 32(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_19
# %bb.20:
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB1_21
# %bb.22:
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.24:
xorl %eax, %eax
jmp .LBB1_25
.LBB1_1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB1_25
.LBB1_26:
movl $.Lstr, %edi
callq puts@PLT
movl $-2, %eax
.LBB1_25:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 224
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $104, %edx
jmp .LBB1_9
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $105, %edx
jmp .LBB1_9
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $108, %edx
jmp .LBB1_9
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $117, %edx
jmp .LBB1_9
.LBB1_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $121, %edx
jmp .LBB1_9
.LBB1_21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $129, %edx
jmp .LBB1_9
.LBB1_23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $130, %edx
.LBB1_9:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_ii,@object # @_Z15MatrixMulKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_ii
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_ii:
.quad _Z30__device_stub__MatrixMulKernelPfS_ii
.size _Z15MatrixMulKernelPfS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CUDA error %s:%d: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/nicklev/CUDA/master/MatrixMulKernel.hip"
.size .L.str.3, 97
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Milliseconds: %f\n"
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Could not allocate memory."
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Provide the problem size."
.size .Lstr.1, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fc600000001ff */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0080*/ LEA R3, R7, R0, 0x4 ; /* 0x0000000007037211 */
/* 0x001fc800078e20ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fc80003f06270 */
/*00a0*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x174], P0 ; /* 0x00005d0000007a0c */
/* 0x000fe40000746670 */
/*00b0*/ LEA R2, R5, R8, 0x4 ; /* 0x0000000805027211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fc80003f26270 */
/*00d0*/ ISETP.GE.OR P3, PT, R8, c[0x0][0x174], P1 ; /* 0x00005d0008007a0c */
/* 0x000fc60000f66670 */
/*00e0*/ @!P2 IMAD R12, R0, c[0x0][0x170], R2 ; /* 0x00005c00000caa24 */
/* 0x000fe400078e0202 */
/*00f0*/ @!P2 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0da424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R6, c[0x0][0x174] ; /* 0x00005d0000067a02 */
/* 0x000fc60000000f00 */
/*0110*/ @!P2 IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0ca625 */
/* 0x000fe200078e020d */
/*0120*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fc600000001ff */
/*0130*/ @!P3 MOV R15, 0x4 ; /* 0x00000004000fb802 */
/* 0x000fe20000000f00 */
/*0140*/ @!P2 LDG.E R9, [R12.64] ; /* 0x000000060c09a981 */
/* 0x000162000c1e1900 */
/*0150*/ ISETP.GE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f46270 */
/*0160*/ @!P3 IMAD R14, R8, c[0x0][0x170], R3 ; /* 0x00005c00080eba24 */
/* 0x000fc800078e0203 */
/*0170*/ @!P3 IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0eb625 */
/* 0x000fc800078e020f */
/*0180*/ IMAD R2, R3, c[0x0][0x170], R2 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0202 */
/*0190*/ @!P3 LDG.E R10, [R14.64] ; /* 0x000000060e0ab981 */
/* 0x000162000c1e1900 */
/*01a0*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe40000000f00 */
/*01b0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e020b */
/*01c0*/ @!P2 BRA 0x740 ; /* 0x000005700000a947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R11, R8, 0x10, RZ ; /* 0x00000010080b7810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R6, R6, 0xf, RZ ; /* 0x0000000f06067810 */
/* 0x000fe20007ffe0ff */
/*0200*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0210*/ IADD3 R13, R0, 0x10, RZ ; /* 0x00000010000d7810 */
/* 0x001fe20007ffe0ff */
/*0220*/ IMAD R16, R11, c[0x0][0x170], R0 ; /* 0x00005c000b107a24 */
/* 0x000fe200078e0200 */
/*0230*/ SHF.R.S32.HI R17, RZ, 0x1f, R6 ; /* 0x0000001fff117819 */
/* 0x000fc40000011406 */
/*0240*/ LEA R15, R8.reuse, 0x400, 0x6 ; /* 0x00000400080f7811 */
/* 0x040fe200078e30ff */
/*0250*/ IMAD R14, R13, c[0x0][0x170], R8 ; /* 0x00005c000d0e7a24 */
/* 0x000fe200078e0208 */
/*0260*/ LEA R16, R7, R16, 0x4 ; /* 0x0000001007107211 */
/* 0x000fe400078e20ff */
/*0270*/ SHF.L.U32 R7, R8, 0x2, RZ ; /* 0x0000000208077819 */
/* 0x000fe200000006ff */
/*0280*/ IMAD R14, R5, 0x10, R14 ; /* 0x00000010050e7824 */
/* 0x000fe200078e020e */
/*0290*/ LEA.HI R12, R17, R6, RZ, 0x4 ; /* 0x00000006110c7211 */
/* 0x000fe400078f20ff */
/*02a0*/ IADD3 R15, R15, R4, RZ ; /* 0x000000040f0f7210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fc40000000f00 */
/*02c0*/ LEA R18, R0, R7, 0x6 ; /* 0x0000000700127211 */
/* 0x000fe400078e30ff */
/*02d0*/ SHF.R.S32.HI R12, RZ, 0x4, R12 ; /* 0x00000004ff0c7819 */
/* 0x000fc6000001140c */
/*02e0*/ STS [R18], R9 ; /* 0x0000000912007388 */
/* 0x0201e20000000800 */
/*02f0*/ ISETP.GE.OR P2, PT, R13, c[0x0][0x174], P0 ; /* 0x00005d000d007a0c */
/* 0x000fe40000746670 */
/*0300*/ ISETP.GE.OR P3, PT, R11, c[0x0][0x174], P1 ; /* 0x00005d000b007a0c */
/* 0x000fe20000f66670 */
/*0310*/ STS [R15], R10 ; /* 0x0000000a0f007388 */
/* 0x0003e80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0330*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x001fca00000001ff */
/*0340*/ @!P2 MOV R5, 0x4 ; /* 0x000000040005a802 */
/* 0x000fe40000000f00 */
/*0350*/ @!P3 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff07b424 */
/* 0x000fe200078e00ff */
/*0360*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x002fe40000000f00 */
/*0370*/ @!P2 IMAD.WIDE R4, R14, R5, c[0x0][0x160] ; /* 0x000058000e04a625 */
/* 0x000fc800078e0205 */
/*0380*/ @!P3 IMAD.WIDE R6, R16, R7, c[0x0][0x160] ; /* 0x000058001006b625 */
/* 0x000fe200078e0207 */
/*0390*/ LDS R24, [R8.X4+0x400] ; /* 0x0004000008187984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e280000004800 */
/*03b0*/ LDS R28, [R8.X4+0x440] ; /* 0x00044000081c7984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R27, [R0.X4+0x40] ; /* 0x00004000001b7984 */
/* 0x000e680000004800 */
/*03d0*/ LDS R26, [R8.X4+0x480] ; /* 0x00048000081a7984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS R25, [R0.X4+0x80] ; /* 0x0000800000197984 */
/* 0x000ea80000004800 */
/*03f0*/ LDS R20, [R8.X4+0x4c0] ; /* 0x0004c00008147984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R23, [R0.X4+0xc0] ; /* 0x0000c00000177984 */
/* 0x000ee80000004800 */
/*0410*/ LDS R19, [R8.X4+0x500] ; /* 0x0005000008137984 */
/* 0x000fe80000004800 */
/*0420*/ LDS R22, [R0.X4+0x100] ; /* 0x0001000000167984 */
/* 0x000f280000004800 */
/*0430*/ @!P2 LDG.E R9, [R4.64] ; /* 0x000000060409a981 */
/* 0x000362000c1e1900 */
/*0440*/ FFMA R17, R24, R21, R17 ; /* 0x0000001518117223 */
/* 0x001fc60000000011 */
/*0450*/ @!P3 LDG.E R10, [R6.64] ; /* 0x00000006060ab981 */
/* 0x000162000c1e1900 */
/*0460*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0470*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LDS R21, [R8.X4+0x540] ; /* 0x0005400008157984 */
/* 0x000fe20000004800 */
/*0490*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ FFMA R17, R28, R27, R17 ; /* 0x0000001b1c117223 */
/* 0x002fe40000000011 */
/*04b0*/ LDS R24, [R0.X4+0x140] ; /* 0x0001400000187984 */
/* 0x000e620000004800 */
/*04c0*/ ISETP.LE.AND P2, PT, R12, UR4, PT ; /* 0x000000040c007c0c */
/* 0x000fc6000bf43270 */
/*04d0*/ LDS R4, [R8.X4+0x580] ; /* 0x0005800008047984 */
/* 0x000fe20000004800 */
/*04e0*/ FFMA R17, R26, R25, R17 ; /* 0x000000191a117223 */
/* 0x004fc60000000011 */
/*04f0*/ LDS R5, [R0.X4+0x180] ; /* 0x0001800000057984 */
/* 0x000ea80000004800 */
/*0500*/ LDS R6, [R8.X4+0x5c0] ; /* 0x0005c00008067984 */
/* 0x001fe20000004800 */
/*0510*/ FFMA R23, R20, R23, R17 ; /* 0x0000001714177223 */
/* 0x008fc60000000011 */
/*0520*/ LDS R7, [R0.X4+0x1c0] ; /* 0x0001c00000077984 */
/* 0x000e280000004800 */
/*0530*/ LDS R17, [R8.X4+0x600] ; /* 0x0006000008117984 */
/* 0x000fe20000004800 */
/*0540*/ FFMA R23, R19, R22, R23 ; /* 0x0000001613177223 */
/* 0x010fc60000000017 */
/*0550*/ LDS R20, [R0.X4+0x200] ; /* 0x0002000000147984 */
/* 0x000ee80000004800 */
/*0560*/ LDS R19, [R8.X4+0x640] ; /* 0x0006400008137984 */
/* 0x000fe80000004800 */
/*0570*/ LDS R22, [R0.X4+0x240] ; /* 0x0002400000167984 */
/* 0x000f220000004800 */
/*0580*/ FFMA R23, R21, R24, R23 ; /* 0x0000001815177223 */
/* 0x002fc60000000017 */
/*0590*/ LDS R21, [R8.X4+0x680] ; /* 0x0006800008157984 */
/* 0x000fe80000004800 */
/*05a0*/ LDS R24, [R0.X4+0x280] ; /* 0x0002800000187984 */
/* 0x000e620000004800 */
/*05b0*/ FFMA R23, R4, R5, R23 ; /* 0x0000000504177223 */
/* 0x004fc60000000017 */
/*05c0*/ LDS R4, [R8.X4+0x6c0] ; /* 0x0006c00008047984 */
/* 0x000fe80000004800 */
/*05d0*/ LDS R5, [R0.X4+0x2c0] ; /* 0x0002c00000057984 */
/* 0x000ea20000004800 */
/*05e0*/ FFMA R23, R6, R7, R23 ; /* 0x0000000706177223 */
/* 0x001fc60000000017 */
/*05f0*/ LDS R6, [R8.X4+0x700] ; /* 0x0007000008067984 */
/* 0x000fe80000004800 */
/*0600*/ LDS R7, [R0.X4+0x300] ; /* 0x0003000000077984 */
/* 0x000e220000004800 */
/*0610*/ FFMA R23, R17, R20, R23 ; /* 0x0000001411177223 */
/* 0x008fc60000000017 */
/*0620*/ LDS R17, [R8.X4+0x740] ; /* 0x0007400008117984 */
/* 0x000fe80000004800 */
/*0630*/ LDS R20, [R0.X4+0x340] ; /* 0x0003400000147984 */
/* 0x000ee20000004800 */
/*0640*/ FFMA R23, R19, R22, R23 ; /* 0x0000001613177223 */
/* 0x010fc60000000017 */
/*0650*/ LDS R22, [R8.X4+0x780] ; /* 0x0007800008167984 */
/* 0x000fe80000004800 */
/*0660*/ LDS R19, [R0.X4+0x380] ; /* 0x0003800000137984 */
/* 0x000f220000004800 */
/*0670*/ FFMA R21, R21, R24, R23 ; /* 0x0000001815157223 */
/* 0x002fc60000000017 */
/*0680*/ LDS R23, [R8.X4+0x7c0] ; /* 0x0007c00008177984 */
/* 0x000fe80000004800 */
/*0690*/ LDS R24, [R0.X4+0x3c0] ; /* 0x0003c00000187984 */
/* 0x000e620000004800 */
/*06a0*/ FFMA R4, R4, R5, R21 ; /* 0x0000000504047223 */
/* 0x004fe20000000015 */
/*06b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fc600000001ff */
/*06c0*/ FFMA R4, R6, R7, R4 ; /* 0x0000000706047223 */
/* 0x001fce0000000004 */
/*06d0*/ IMAD R16, R5.reuse, c[0x0][0x170], R16 ; /* 0x00005c0005107a24 */
/* 0x040fe400078e0210 */
/*06e0*/ IMAD R14, R5, c[0x0][0x170], R14 ; /* 0x00005c00050e7a24 */
/* 0x000fe400078e020e */
/*06f0*/ FFMA R4, R17, R20, R4 ; /* 0x0000001411047223 */
/* 0x008fc80000000004 */
/*0700*/ FFMA R4, R22, R19, R4 ; /* 0x0000001316047223 */
/* 0x010fc80000000004 */
/*0710*/ FFMA R17, R23, R24, R4 ; /* 0x0000001817117223 */
/* 0x002fe20000000004 */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ @!P2 BRA 0x2e0 ; /* 0xfffffba00000a947 */
/* 0x000fea000383ffff */
/*0740*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe2000c101906 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_ii
.globl _Z15MatrixMulKernelPfS_ii
.p2align 8
.type _Z15MatrixMulKernelPfS_ii,@function
_Z15MatrixMulKernelPfS_ii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v3, 0x3ff, v0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s15, 4, v2
v_lshl_add_u32 v1, s14, 4, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[4:5], null, v2, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s2, s6, v4
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
global_load_b32 v4, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e64 s3, s5, v3
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_and_saveexec_b32 s8, s3
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[5:6], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s3, s6, v5
v_add_co_ci_u32_e64 v6, s3, s7, v6, s3
global_load_b32 v6, v[5:6], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v5, 0
s_cmp_lt_i32 s5, 1
s_mov_b32 s8, 1
s_cbranch_scc1 .LBB0_14
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b32_e32 v7, 2, v2
v_lshlrev_b32_e32 v9, 6, v3
s_add_i32 s3, s5, 15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_lshr_b32 s3, s3, 4
v_lshl_add_u32 v8, v2, 6, v5
v_add3_u32 v9, v9, v7, 0x400
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, 0x400, v5
s_max_i32 s9, s3, 1
.LBB0_6:
s_lshl_b32 s10, s8, 4
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
ds_store_b32 v9, v6
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v11, s10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e64 s3, s5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s11, s3
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[12:13], null, v11, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v4, v[11:12], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s11
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v11, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s5, v11
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s3
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v11, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v6, v[11:12], off
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s3, 0
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, s3, v7
v_add_nc_u32_e32 v12, s3, v10
s_add_i32 s3, s3, 64
ds_load_b32 v11, v11
ds_load_b32 v12, v12
s_cmpk_eq_i32 s3, 0x400
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v11, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s3, s8, 1
s_cmp_eq_u32 s8, s9
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
s_mov_b32 s8, s3
s_branch .LBB0_6
.LBB0_14:
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_ii, .Lfunc_end0-_Z15MatrixMulKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016a229_00000000-6_MatrixMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
.type _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii, @function
_Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii, .-_Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
.globl _Z15MatrixMulKernelPfS_ii
.type _Z15MatrixMulKernelPfS_ii, @function
_Z15MatrixMulKernelPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15MatrixMulKernelPfS_ii, .-_Z15MatrixMulKernelPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Provide the problem size.\n"
.LC1:
.string "Could not allocate memory.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/nicklev/CUDA/master/MatrixMulKernel.cu"
.section .rodata.str1.1
.LC4:
.string "CUDA error %s:%d: %s\n"
.LC6:
.string "Milliseconds: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpl $3, %ebp
jne .L30
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 28(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 24(%rsp)
imull %eax, %r13d
movslq %r13d, %r12
leal 0(,%r13,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movl %ebp, %eax
imull %ebp, %eax
sall $2, %eax
cltq
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %r14, %r14
je .L14
testq %rax, %rax
je .L14
movq %r14, %rbx
leaq (%r14,%r12,4), %r12
testl %r13d, %r13d
jle .L16
.L17:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
.L16:
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
leaq 56(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L33
leal 14(%rbp), %eax
subl $1, %ebp
cmovns %ebp, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 80(%rsp)
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl $16, 92(%rsp)
movl $16, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 100(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
movq 56(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
movl $0, %eax
.L11:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L14:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-2, %eax
jmp .L11
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $104, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $105, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $108, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z39__device_stub__Z15MatrixMulKernelPfS_iiPfS_ii
jmp .L21
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $117, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $121, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $129, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $130, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z15MatrixMulKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixMulKernel.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_ii # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_ii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_ii,@function
_Z30__device_stub__MatrixMulKernelPfS_ii: # @_Z30__device_stub__MatrixMulKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_ii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $3, %ebp
jne .LBB1_1
# %bb.2:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %r14d
imull %r15d, %r14d
leal (,%r14,4), %eax
movl %r12d, %ebx
imull %r12d, %ebx
shll $2, %ebx
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movslq %ebx, %rbx
movq %rbx, %rdi
callq malloc
testq %rbp, %rbp
je .LBB1_26
# %bb.3:
testq %rax, %rax
je .LBB1_26
# %bb.4: # %.preheader
movq %r15, 96(%rsp) # 8-byte Spill
movq %rax, 88(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
movl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_6
.LBB1_7: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.10:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 24(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
movq 96(%rsp), %r14 # 8-byte Reload
jne .LBB1_13
# %bb.14:
leal -1(%r12), %eax
leal 14(%r12), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
incl %ecx
movq %rcx, %r13
shlq $32, %r13
orq %rcx, %r13
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl %r12d, 36(%rsp)
movl %r14d, 32(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_19
# %bb.20:
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB1_21
# %bb.22:
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.24:
xorl %eax, %eax
jmp .LBB1_25
.LBB1_1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB1_25
.LBB1_26:
movl $.Lstr, %edi
callq puts@PLT
movl $-2, %eax
.LBB1_25:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 224
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $104, %edx
jmp .LBB1_9
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $105, %edx
jmp .LBB1_9
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $108, %edx
jmp .LBB1_9
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $117, %edx
jmp .LBB1_9
.LBB1_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $121, %edx
jmp .LBB1_9
.LBB1_21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $129, %edx
jmp .LBB1_9
.LBB1_23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.3, %esi
movl $130, %edx
.LBB1_9:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_ii,@object # @_Z15MatrixMulKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_ii
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_ii:
.quad _Z30__device_stub__MatrixMulKernelPfS_ii
.size _Z15MatrixMulKernelPfS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CUDA error %s:%d: %s\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/nicklev/CUDA/master/MatrixMulKernel.hip"
.size .L.str.3, 97
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Milliseconds: %f\n"
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Could not allocate memory."
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Provide the problem size."
.size .Lstr.1, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h> /* memcpy */
/* C99 syntax test (currently only a subset is parsed) */
/* @todo Also typedef struct */
typedef struct Car
{
const char *name;
int year;
float max_speed;
} Car; /* @todo Allow unnecessary ; */
int main()
{
int test_integer;
test_integer = -134;
int another_test_integer = 1;
/* @todo Make work */
/*char test_str[] = "foo"; */
/* @todo This parses, but needs conversion to C89 (because decl is separated from init) */
Car car;
/* @todo This parses, but need to make conversion from compound literals and designated initializers to C89 */
/*car = (Car) {
.year = 1,
.name = "bbb",
.max_speed = -2.0
};*/
/* @todo Rest of C99 */
/* @todo Make work */
/*(void)car; */
/*(void)test_integer; */
/*(void)another_test_integer; */
int x = car.year + test_integer + another_test_integer;
return x;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h> /* memcpy */
/* C99 syntax test (currently only a subset is parsed) */
/* @todo Also typedef struct */
typedef struct Car
{
const char *name;
int year;
float max_speed;
} Car; /* @todo Allow unnecessary ; */
int main()
{
int test_integer;
test_integer = -134;
int another_test_integer = 1;
/* @todo Make work */
/*char test_str[] = "foo"; */
/* @todo This parses, but needs conversion to C89 (because decl is separated from init) */
Car car;
/* @todo This parses, but need to make conversion from compound literals and designated initializers to C89 */
/*car = (Car) {
.year = 1,
.name = "bbb",
.max_speed = -2.0
};*/
/* @todo Rest of C99 */
/* @todo Make work */
/*(void)car; */
/*(void)test_integer; */
/*(void)another_test_integer; */
int x = car.year + test_integer + another_test_integer;
return x;
} | .file "tmpxft_0015078f_00000000-6_c_syntax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $-133, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h> /* memcpy */
/* C99 syntax test (currently only a subset is parsed) */
/* @todo Also typedef struct */
typedef struct Car
{
const char *name;
int year;
float max_speed;
} Car; /* @todo Allow unnecessary ; */
int main()
{
int test_integer;
test_integer = -134;
int another_test_integer = 1;
/* @todo Make work */
/*char test_str[] = "foo"; */
/* @todo This parses, but needs conversion to C89 (because decl is separated from init) */
Car car;
/* @todo This parses, but need to make conversion from compound literals and designated initializers to C89 */
/*car = (Car) {
.year = 1,
.name = "bbb",
.max_speed = -2.0
};*/
/* @todo Rest of C99 */
/* @todo Make work */
/*(void)car; */
/*(void)test_integer; */
/*(void)another_test_integer; */
int x = car.year + test_integer + another_test_integer;
return x;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* memcpy */
/* C99 syntax test (currently only a subset is parsed) */
/* @todo Also typedef struct */
typedef struct Car
{
const char *name;
int year;
float max_speed;
} Car; /* @todo Allow unnecessary ; */
int main()
{
int test_integer;
test_integer = -134;
int another_test_integer = 1;
/* @todo Make work */
/*char test_str[] = "foo"; */
/* @todo This parses, but needs conversion to C89 (because decl is separated from init) */
Car car;
/* @todo This parses, but need to make conversion from compound literals and designated initializers to C89 */
/*car = (Car) {
.year = 1,
.name = "bbb",
.max_speed = -2.0
};*/
/* @todo Rest of C99 */
/* @todo Make work */
/*(void)car; */
/*(void)test_integer; */
/*(void)another_test_integer; */
int x = car.year + test_integer + another_test_integer;
return x;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* memcpy */
/* C99 syntax test (currently only a subset is parsed) */
/* @todo Also typedef struct */
typedef struct Car
{
const char *name;
int year;
float max_speed;
} Car; /* @todo Allow unnecessary ; */
int main()
{
int test_integer;
test_integer = -134;
int another_test_integer = 1;
/* @todo Make work */
/*char test_str[] = "foo"; */
/* @todo This parses, but needs conversion to C89 (because decl is separated from init) */
Car car;
/* @todo This parses, but need to make conversion from compound literals and designated initializers to C89 */
/*car = (Car) {
.year = 1,
.name = "bbb",
.max_speed = -2.0
};*/
/* @todo Rest of C99 */
/* @todo Make work */
/*(void)car; */
/*(void)test_integer; */
/*(void)another_test_integer; */
int x = car.year + test_integer + another_test_integer;
return x;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* memcpy */
/* C99 syntax test (currently only a subset is parsed) */
/* @todo Also typedef struct */
typedef struct Car
{
const char *name;
int year;
float max_speed;
} Car; /* @todo Allow unnecessary ; */
int main()
{
int test_integer;
test_integer = -134;
int another_test_integer = 1;
/* @todo Make work */
/*char test_str[] = "foo"; */
/* @todo This parses, but needs conversion to C89 (because decl is separated from init) */
Car car;
/* @todo This parses, but need to make conversion from compound literals and designated initializers to C89 */
/*car = (Car) {
.year = 1,
.name = "bbb",
.max_speed = -2.0
};*/
/* @todo Rest of C99 */
/* @todo Make work */
/*(void)car; */
/*(void)test_integer; */
/*(void)another_test_integer; */
int x = car.year + test_integer + another_test_integer;
return x;
} | .text
.file "c_syntax.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015078f_00000000-6_c_syntax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $-133, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "c_syntax.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* An exercise on the different types of memory available in CUDA
*/
#include <iostream>
#include <cstdlib>
// Error checking macro function
#define myCudaCheck(result) { cudaErrorCheck((result), __FILE__, __LINE__); }
inline void cudaErrorCheck(cudaError_t err, const char* file, int line)
{
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << cudaGetErrorString(err) << " at " << file << ":" << line << std::endl;
exit(err);
}
}
// Array size
// HANDSON 2.1 Change the array size to a static __constant__ int
#define ARRAY_SIZE 65536
static __constant__ int arr_size;
// CUDA threads per block
#define nThreads 128
// Array reversing kernel
__global__
void reverse(float* devA, float* devB)
{
// HANDSON 2.3 Create a __shared__ temporary array of length nThreads for the swap
__shared__ float tmp_arr[nThreads];
// Get the index in this block
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// HANDSON 2.4 Fill the temporary array
tmp_arr[nThreads - (threadIdx.x+1)] = devA[idx];
// HANDSON 2.5 synchronize the threads
__syncthreads();
// HANDSON 2.6 Calculate the initial position of this block in the grid
int blockOffset = arr_size - (blockIdx.x + 1) * blockDim.x;
// Reverse the elements
// HANDSON 2.7 Fill the output array with the reversed elements from this block
devB[blockOffset + threadIdx.x] = tmp_arr[threadIdx.x];
}
// Main host function
int main( )
{
// HANDSON 2.2 Replace the host array size by a const int
// Here and elsewhere
// size of the array in char
const int host_size = 65536;
size_t sizeChar = host_size * sizeof(float);
// Allocate host memory
float* hostIn = (float*) malloc(sizeChar);
float* hostOut = (float*) malloc(sizeChar);
// Allocate device memory
float* devIn;
float* devOut;
myCudaCheck(
cudaMalloc(&devIn, sizeChar)
);
myCudaCheck(
cudaMalloc(&devOut, sizeChar)
);
// Initialize the arrays
for (int i = 0; i < host_size; i++) {
hostIn[i] = i;
hostOut[i] = 0;
}
myCudaCheck(
cudaMemcpyToSymbol( arr_size, &host_size, sizeof(int))
);
// Copy the input array from the host to the device
myCudaCheck(
cudaMemcpy(devIn, hostIn, sizeChar, cudaMemcpyHostToDevice)
);
// Define the size of the task
dim3 blocksPerGrid(host_size/nThreads);
dim3 threadsPerBlock(nThreads);
reverse<<<blocksPerGrid, threadsPerBlock>>>(devIn, devOut);
// Wait for all threads to complete
myCudaCheck(
cudaDeviceSynchronize()
);
// Copy the result array back to the host
myCudaCheck(
cudaMemcpy(hostOut, devOut, sizeChar, cudaMemcpyDeviceToHost)
);
// Check and print the result
int nCorrect = 0;
for (int i = 0; i < host_size; i++) {
nCorrect += (hostOut[i] == hostIn[host_size - (i+1)]) ? 1 : 0;
}
std::cout << ((nCorrect == host_size) ? "Success! " : "Failure: ");
std::cout << nCorrect << " elements were correctly swapped." << std::endl;
// Free device memory
myCudaCheck(
cudaFree(devIn)
);
myCudaCheck(
cudaFree(devOut)
);
// Free host memory
free(hostIn);
free(hostOut);
return 0;
} | code for sm_80
Function : _Z7reversePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R0, c[0x0][0x0], R11 ; /* 0x0000000000027a24 */
/* 0x001fca00078e020b */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IADD3 R7, -R11, 0x7f, RZ ; /* 0x0000007f0b077810 */
/* 0x000fe40007ffe1ff */
/*0090*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fca0000000f00 */
/*00a0*/ IMAD R0, R0, R13, c[0x0][0x0] ; /* 0x0000000000007624 */
/* 0x000fca00078e020d */
/*00b0*/ IADD3 R0, R11, c[0x3][0x0], -R0 ; /* 0x00c000000b007a10 */
/* 0x000fca0007ffe800 */
/*00c0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0005 */
/*00d0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x004fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000e280000004800 */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* An exercise on the different types of memory available in CUDA
*/
#include <iostream>
#include <cstdlib>
// Error checking macro function
#define myCudaCheck(result) { cudaErrorCheck((result), __FILE__, __LINE__); }
inline void cudaErrorCheck(cudaError_t err, const char* file, int line)
{
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << cudaGetErrorString(err) << " at " << file << ":" << line << std::endl;
exit(err);
}
}
// Array size
// HANDSON 2.1 Change the array size to a static __constant__ int
#define ARRAY_SIZE 65536
static __constant__ int arr_size;
// CUDA threads per block
#define nThreads 128
// Array reversing kernel
__global__
void reverse(float* devA, float* devB)
{
// HANDSON 2.3 Create a __shared__ temporary array of length nThreads for the swap
__shared__ float tmp_arr[nThreads];
// Get the index in this block
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// HANDSON 2.4 Fill the temporary array
tmp_arr[nThreads - (threadIdx.x+1)] = devA[idx];
// HANDSON 2.5 synchronize the threads
__syncthreads();
// HANDSON 2.6 Calculate the initial position of this block in the grid
int blockOffset = arr_size - (blockIdx.x + 1) * blockDim.x;
// Reverse the elements
// HANDSON 2.7 Fill the output array with the reversed elements from this block
devB[blockOffset + threadIdx.x] = tmp_arr[threadIdx.x];
}
// Main host function
int main( )
{
// HANDSON 2.2 Replace the host array size by a const int
// Here and elsewhere
// size of the array in char
const int host_size = 65536;
size_t sizeChar = host_size * sizeof(float);
// Allocate host memory
float* hostIn = (float*) malloc(sizeChar);
float* hostOut = (float*) malloc(sizeChar);
// Allocate device memory
float* devIn;
float* devOut;
myCudaCheck(
cudaMalloc(&devIn, sizeChar)
);
myCudaCheck(
cudaMalloc(&devOut, sizeChar)
);
// Initialize the arrays
for (int i = 0; i < host_size; i++) {
hostIn[i] = i;
hostOut[i] = 0;
}
myCudaCheck(
cudaMemcpyToSymbol( arr_size, &host_size, sizeof(int))
);
// Copy the input array from the host to the device
myCudaCheck(
cudaMemcpy(devIn, hostIn, sizeChar, cudaMemcpyHostToDevice)
);
// Define the size of the task
dim3 blocksPerGrid(host_size/nThreads);
dim3 threadsPerBlock(nThreads);
reverse<<<blocksPerGrid, threadsPerBlock>>>(devIn, devOut);
// Wait for all threads to complete
myCudaCheck(
cudaDeviceSynchronize()
);
// Copy the result array back to the host
myCudaCheck(
cudaMemcpy(hostOut, devOut, sizeChar, cudaMemcpyDeviceToHost)
);
// Check and print the result
int nCorrect = 0;
for (int i = 0; i < host_size; i++) {
nCorrect += (hostOut[i] == hostIn[host_size - (i+1)]) ? 1 : 0;
}
std::cout << ((nCorrect == host_size) ? "Success! " : "Failure: ");
std::cout << nCorrect << " elements were correctly swapped." << std::endl;
// Free device memory
myCudaCheck(
cudaFree(devIn)
);
myCudaCheck(
cudaFree(devOut)
);
// Free host memory
free(hostIn);
free(hostOut);
return 0;
} | .file "tmpxft_0013ccbf_00000000-6_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z14cudaErrorCheck9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " at "
.LC2:
.string ":"
.section .text._Z14cudaErrorCheck9cudaErrorPKci,"axG",@progbits,_Z14cudaErrorCheck9cudaErrorPKci,comdat
.weak _Z14cudaErrorCheck9cudaErrorPKci
.type _Z14cudaErrorCheck9cudaErrorPKci, @function
_Z14cudaErrorCheck9cudaErrorPKci:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %ebp
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z14cudaErrorCheck9cudaErrorPKci, .-_Z14cudaErrorCheck9cudaErrorPKci
.text
.globl _Z28__device_stub__Z7reversePfS_PfS_
.type _Z28__device_stub__Z7reversePfS_PfS_, @function
_Z28__device_stub__Z7reversePfS_PfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reversePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7reversePfS_PfS_, .-_Z28__device_stub__Z7reversePfS_PfS_
.globl _Z7reversePfS_
.type _Z7reversePfS_, @function
_Z7reversePfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reversePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7reversePfS_, .-_Z7reversePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Success! "
.LC4:
.string "Failure: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/nikoSchoinas/phas0100_cuda/main/memory/memory.cu"
.align 8
.LC7:
.string " elements were correctly swapped."
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $65536, 12(%rsp)
movl $262144, %edi
call malloc@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $66, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $69, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L18
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8arr_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
movl $79, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $84, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $95, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $2, %ecx
movl $262144, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $100, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movq %rbx, %rax
leaq 262140(%rbp), %rcx
leaq 262144(%rbx), %rdi
movl $0, %r12d
movl $0, %esi
.L20:
movss (%rax), %xmm0
ucomiss (%rcx), %xmm0
setnp %dl
movzbl %dl, %edx
cmovne %esi, %edx
addl %edx, %r12d
addq $4, %rax
subq $4, %rcx
cmpq %rdi, %rax
jne .L20
cmpl $65536, %r12d
leaq .LC4(%rip), %rsi
leaq .LC3(%rip), %rax
cmove %rax, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $113, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $116, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z7reversePfS_PfS_
jmp .L19
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7reversePfS_"
.LC9:
.string "arr_size"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reversePfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8arr_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8arr_size
.comm _ZL8arr_size,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* An exercise on the different types of memory available in CUDA
*/
#include <iostream>
#include <cstdlib>
// Error checking macro function
#define myCudaCheck(result) { cudaErrorCheck((result), __FILE__, __LINE__); }
inline void cudaErrorCheck(cudaError_t err, const char* file, int line)
{
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << cudaGetErrorString(err) << " at " << file << ":" << line << std::endl;
exit(err);
}
}
// Array size
// HANDSON 2.1 Change the array size to a static __constant__ int
#define ARRAY_SIZE 65536
static __constant__ int arr_size;
// CUDA threads per block
#define nThreads 128
// Array reversing kernel
__global__
void reverse(float* devA, float* devB)
{
// HANDSON 2.3 Create a __shared__ temporary array of length nThreads for the swap
__shared__ float tmp_arr[nThreads];
// Get the index in this block
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// HANDSON 2.4 Fill the temporary array
tmp_arr[nThreads - (threadIdx.x+1)] = devA[idx];
// HANDSON 2.5 synchronize the threads
__syncthreads();
// HANDSON 2.6 Calculate the initial position of this block in the grid
int blockOffset = arr_size - (blockIdx.x + 1) * blockDim.x;
// Reverse the elements
// HANDSON 2.7 Fill the output array with the reversed elements from this block
devB[blockOffset + threadIdx.x] = tmp_arr[threadIdx.x];
}
// Main host function
int main( )
{
// HANDSON 2.2 Replace the host array size by a const int
// Here and elsewhere
// size of the array in char
const int host_size = 65536;
size_t sizeChar = host_size * sizeof(float);
// Allocate host memory
float* hostIn = (float*) malloc(sizeChar);
float* hostOut = (float*) malloc(sizeChar);
// Allocate device memory
float* devIn;
float* devOut;
myCudaCheck(
cudaMalloc(&devIn, sizeChar)
);
myCudaCheck(
cudaMalloc(&devOut, sizeChar)
);
// Initialize the arrays
for (int i = 0; i < host_size; i++) {
hostIn[i] = i;
hostOut[i] = 0;
}
myCudaCheck(
cudaMemcpyToSymbol( arr_size, &host_size, sizeof(int))
);
// Copy the input array from the host to the device
myCudaCheck(
cudaMemcpy(devIn, hostIn, sizeChar, cudaMemcpyHostToDevice)
);
// Define the size of the task
dim3 blocksPerGrid(host_size/nThreads);
dim3 threadsPerBlock(nThreads);
reverse<<<blocksPerGrid, threadsPerBlock>>>(devIn, devOut);
// Wait for all threads to complete
myCudaCheck(
cudaDeviceSynchronize()
);
// Copy the result array back to the host
myCudaCheck(
cudaMemcpy(hostOut, devOut, sizeChar, cudaMemcpyDeviceToHost)
);
// Check and print the result
int nCorrect = 0;
for (int i = 0; i < host_size; i++) {
nCorrect += (hostOut[i] == hostIn[host_size - (i+1)]) ? 1 : 0;
}
std::cout << ((nCorrect == host_size) ? "Success! " : "Failure: ");
std::cout << nCorrect << " elements were correctly swapped." << std::endl;
// Free device memory
myCudaCheck(
cudaFree(devIn)
);
myCudaCheck(
cudaFree(devOut)
);
// Free host memory
free(hostIn);
free(hostOut);
return 0;
} | /*
* An exercise on the different types of memory available in CUDA
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
// Error checking macro function
#define myCudaCheck(result) { cudaErrorCheck((result), __FILE__, __LINE__); }
inline void cudaErrorCheck(hipError_t err, const char* file, int line)
{
if (err != hipSuccess) {
std::cerr << "CUDA error: " << hipGetErrorString(err) << " at " << file << ":" << line << std::endl;
exit(err);
}
}
// Array size
// HANDSON 2.1 Change the array size to a static __constant__ int
#define ARRAY_SIZE 65536
static __constant__ int arr_size;
// CUDA threads per block
#define nThreads 128
// Array reversing kernel
__global__
void reverse(float* devA, float* devB)
{
// HANDSON 2.3 Create a __shared__ temporary array of length nThreads for the swap
__shared__ float tmp_arr[nThreads];
// Get the index in this block
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// HANDSON 2.4 Fill the temporary array
tmp_arr[nThreads - (threadIdx.x+1)] = devA[idx];
// HANDSON 2.5 synchronize the threads
__syncthreads();
// HANDSON 2.6 Calculate the initial position of this block in the grid
int blockOffset = arr_size - (blockIdx.x + 1) * blockDim.x;
// Reverse the elements
// HANDSON 2.7 Fill the output array with the reversed elements from this block
devB[blockOffset + threadIdx.x] = tmp_arr[threadIdx.x];
}
// Main host function
int main( )
{
// HANDSON 2.2 Replace the host array size by a const int
// Here and elsewhere
// size of the array in char
const int host_size = 65536;
size_t sizeChar = host_size * sizeof(float);
// Allocate host memory
float* hostIn = (float*) malloc(sizeChar);
float* hostOut = (float*) malloc(sizeChar);
// Allocate device memory
float* devIn;
float* devOut;
myCudaCheck(
hipMalloc(&devIn, sizeChar)
);
myCudaCheck(
hipMalloc(&devOut, sizeChar)
);
// Initialize the arrays
for (int i = 0; i < host_size; i++) {
hostIn[i] = i;
hostOut[i] = 0;
}
myCudaCheck(
hipMemcpyToSymbol( HIP_SYMBOL(arr_size), &host_size, sizeof(int))
);
// Copy the input array from the host to the device
myCudaCheck(
hipMemcpy(devIn, hostIn, sizeChar, hipMemcpyHostToDevice)
);
// Define the size of the task
dim3 blocksPerGrid(host_size/nThreads);
dim3 threadsPerBlock(nThreads);
reverse<<<blocksPerGrid, threadsPerBlock>>>(devIn, devOut);
// Wait for all threads to complete
myCudaCheck(
hipDeviceSynchronize()
);
// Copy the result array back to the host
myCudaCheck(
hipMemcpy(hostOut, devOut, sizeChar, hipMemcpyDeviceToHost)
);
// Check and print the result
int nCorrect = 0;
for (int i = 0; i < host_size; i++) {
nCorrect += (hostOut[i] == hostIn[host_size - (i+1)]) ? 1 : 0;
}
std::cout << ((nCorrect == host_size) ? "Success! " : "Failure: ");
std::cout << nCorrect << " elements were correctly swapped." << std::endl;
// Free device memory
myCudaCheck(
hipFree(devIn)
);
myCudaCheck(
hipFree(devOut)
);
// Free host memory
free(hostIn);
free(hostOut);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* An exercise on the different types of memory available in CUDA
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
// Error checking macro function
#define myCudaCheck(result) { cudaErrorCheck((result), __FILE__, __LINE__); }
inline void cudaErrorCheck(hipError_t err, const char* file, int line)
{
if (err != hipSuccess) {
std::cerr << "CUDA error: " << hipGetErrorString(err) << " at " << file << ":" << line << std::endl;
exit(err);
}
}
// Array size
// HANDSON 2.1 Change the array size to a static __constant__ int
#define ARRAY_SIZE 65536
static __constant__ int arr_size;
// CUDA threads per block
#define nThreads 128
// Array reversing kernel
__global__
void reverse(float* devA, float* devB)
{
// HANDSON 2.3 Create a __shared__ temporary array of length nThreads for the swap
__shared__ float tmp_arr[nThreads];
// Get the index in this block
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// HANDSON 2.4 Fill the temporary array
tmp_arr[nThreads - (threadIdx.x+1)] = devA[idx];
// HANDSON 2.5 synchronize the threads
__syncthreads();
// HANDSON 2.6 Calculate the initial position of this block in the grid
int blockOffset = arr_size - (blockIdx.x + 1) * blockDim.x;
// Reverse the elements
// HANDSON 2.7 Fill the output array with the reversed elements from this block
devB[blockOffset + threadIdx.x] = tmp_arr[threadIdx.x];
}
// Main host function
int main( )
{
// HANDSON 2.2 Replace the host array size by a const int
// Here and elsewhere
// size of the array in char
const int host_size = 65536;
size_t sizeChar = host_size * sizeof(float);
// Allocate host memory
float* hostIn = (float*) malloc(sizeChar);
float* hostOut = (float*) malloc(sizeChar);
// Allocate device memory
float* devIn;
float* devOut;
myCudaCheck(
hipMalloc(&devIn, sizeChar)
);
myCudaCheck(
hipMalloc(&devOut, sizeChar)
);
// Initialize the arrays
for (int i = 0; i < host_size; i++) {
hostIn[i] = i;
hostOut[i] = 0;
}
myCudaCheck(
hipMemcpyToSymbol( HIP_SYMBOL(arr_size), &host_size, sizeof(int))
);
// Copy the input array from the host to the device
myCudaCheck(
hipMemcpy(devIn, hostIn, sizeChar, hipMemcpyHostToDevice)
);
// Define the size of the task
dim3 blocksPerGrid(host_size/nThreads);
dim3 threadsPerBlock(nThreads);
reverse<<<blocksPerGrid, threadsPerBlock>>>(devIn, devOut);
// Wait for all threads to complete
myCudaCheck(
hipDeviceSynchronize()
);
// Copy the result array back to the host
myCudaCheck(
hipMemcpy(hostOut, devOut, sizeChar, hipMemcpyDeviceToHost)
);
// Check and print the result
int nCorrect = 0;
for (int i = 0; i < host_size; i++) {
nCorrect += (hostOut[i] == hostIn[host_size - (i+1)]) ? 1 : 0;
}
std::cout << ((nCorrect == host_size) ? "Success! " : "Failure: ");
std::cout << nCorrect << " elements were correctly swapped." << std::endl;
// Free device memory
myCudaCheck(
hipFree(devIn)
);
myCudaCheck(
hipFree(devOut)
);
// Free host memory
free(hostIn);
free(hostOut);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reversePfS_
.globl _Z7reversePfS_
.p2align 8
.type _Z7reversePfS_,@function
_Z7reversePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL8arr_size@gotpcrel32@lo+4
s_addc_u32 s1, s1, _ZL8arr_size@gotpcrel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b32 v1, v[1:2], off
v_sub_nc_u32_e32 v2, 0x7f, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_not_b32 s1, s15
s_mul_i32 s4, s4, s1
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s0, s4, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v3
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reversePfS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reversePfS_, .Lfunc_end0-_Z7reversePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL8arr_size,@object
.section .bss,"aw",@nobits
.globl _ZL8arr_size
.p2align 2, 0x0
_ZL8arr_size:
.long 0
.size _ZL8arr_size, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL8arr_size
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reversePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reversePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* An exercise on the different types of memory available in CUDA
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
// Error checking macro function
#define myCudaCheck(result) { cudaErrorCheck((result), __FILE__, __LINE__); }
inline void cudaErrorCheck(hipError_t err, const char* file, int line)
{
if (err != hipSuccess) {
std::cerr << "CUDA error: " << hipGetErrorString(err) << " at " << file << ":" << line << std::endl;
exit(err);
}
}
// Array size
// HANDSON 2.1 Change the array size to a static __constant__ int
#define ARRAY_SIZE 65536
static __constant__ int arr_size;
// CUDA threads per block
#define nThreads 128
// Array reversing kernel
__global__
void reverse(float* devA, float* devB)
{
// HANDSON 2.3 Create a __shared__ temporary array of length nThreads for the swap
__shared__ float tmp_arr[nThreads];
// Get the index in this block
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// HANDSON 2.4 Fill the temporary array
tmp_arr[nThreads - (threadIdx.x+1)] = devA[idx];
// HANDSON 2.5 synchronize the threads
__syncthreads();
// HANDSON 2.6 Calculate the initial position of this block in the grid
int blockOffset = arr_size - (blockIdx.x + 1) * blockDim.x;
// Reverse the elements
// HANDSON 2.7 Fill the output array with the reversed elements from this block
devB[blockOffset + threadIdx.x] = tmp_arr[threadIdx.x];
}
// Main host function
int main( )
{
// HANDSON 2.2 Replace the host array size by a const int
// Here and elsewhere
// size of the array in char
const int host_size = 65536;
size_t sizeChar = host_size * sizeof(float);
// Allocate host memory
float* hostIn = (float*) malloc(sizeChar);
float* hostOut = (float*) malloc(sizeChar);
// Allocate device memory
float* devIn;
float* devOut;
myCudaCheck(
hipMalloc(&devIn, sizeChar)
);
myCudaCheck(
hipMalloc(&devOut, sizeChar)
);
// Initialize the arrays
for (int i = 0; i < host_size; i++) {
hostIn[i] = i;
hostOut[i] = 0;
}
myCudaCheck(
hipMemcpyToSymbol( HIP_SYMBOL(arr_size), &host_size, sizeof(int))
);
// Copy the input array from the host to the device
myCudaCheck(
hipMemcpy(devIn, hostIn, sizeChar, hipMemcpyHostToDevice)
);
// Define the size of the task
dim3 blocksPerGrid(host_size/nThreads);
dim3 threadsPerBlock(nThreads);
reverse<<<blocksPerGrid, threadsPerBlock>>>(devIn, devOut);
// Wait for all threads to complete
myCudaCheck(
hipDeviceSynchronize()
);
// Copy the result array back to the host
myCudaCheck(
hipMemcpy(hostOut, devOut, sizeChar, hipMemcpyDeviceToHost)
);
// Check and print the result
int nCorrect = 0;
for (int i = 0; i < host_size; i++) {
nCorrect += (hostOut[i] == hostIn[host_size - (i+1)]) ? 1 : 0;
}
std::cout << ((nCorrect == host_size) ? "Success! " : "Failure: ");
std::cout << nCorrect << " elements were correctly swapped." << std::endl;
// Free device memory
myCudaCheck(
hipFree(devIn)
);
myCudaCheck(
hipFree(devOut)
);
// Free host memory
free(hostIn);
free(hostOut);
return 0;
} | .text
.file "memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reversePfS_ # -- Begin function _Z22__device_stub__reversePfS_
.p2align 4, 0x90
.type _Z22__device_stub__reversePfS_,@function
_Z22__device_stub__reversePfS_: # @_Z22__device_stub__reversePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reversePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reversePfS_, .Lfunc_end0-_Z22__device_stub__reversePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $65536, 28(%rsp) # imm = 0x10000
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %rbx
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14cudaErrorCheck10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
jne .LBB1_27
# %bb.4: # %_Z14cudaErrorCheck10hipError_tPKci.exit34.preheader
xorl %r15d, %r15d
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_5: # %_Z14cudaErrorCheck10hipError_tPKci.exit34
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $65536, %r15 # imm = 0x10000
jne .LBB1_5
# %bb.6:
leaq 28(%rsp), %rsi
movl $_ZL8arr_size, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_7
# %bb.8: # %_Z14cudaErrorCheck10hipError_tPKci.exit36
movq 16(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_Z14cudaErrorCheck10hipError_tPKci.exit38
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 384(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7reversePfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_13
# %bb.14: # %_Z14cudaErrorCheck10hipError_tPKci.exit40
movq 8(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_28
# %bb.15: # %_Z14cudaErrorCheck10hipError_tPKci.exit42.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_16: # %_Z14cudaErrorCheck10hipError_tPKci.exit42
# =>This Inner Loop Header: Depth=1
movq %rax, %rcx
xorq $65535, %rcx # imm = 0xFFFF
movss (%rbx,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpeqss (%r14,%rax,4), %xmm0
leaq 1(%rax), %rcx
movd %xmm0, %eax
subl %eax, %ebp
movq %rcx, %rax
cmpq $65536, %rcx # imm = 0x10000
jne .LBB1_16
# %bb.17:
cmpl $65536, %ebp # imm = 0x10000
movl $.L.str.1, %eax
movl $.L.str.2, %esi
cmoveq %rax, %rsi
movl $_ZSt4cout, %edi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $33, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_26
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_20
# %bb.19:
movzbl 67(%r12), %eax
jmp .LBB1_21
.LBB1_20:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z14cudaErrorCheck10hipError_tPKci.exit45
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z14cudaErrorCheck10hipError_tPKci.exit47
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 160
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $70, %esi
jmp .LBB1_2
.LBB1_27:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $73, %esi
jmp .LBB1_2
.LBB1_7:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $83, %esi
jmp .LBB1_2
.LBB1_9:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $88, %esi
jmp .LBB1_2
.LBB1_13:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $99, %esi
jmp .LBB1_2
.LBB1_28:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $104, %esi
jmp .LBB1_2
.LBB1_26:
callq _ZSt16__throw_bad_castv
.LBB1_22:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $117, %esi
jmp .LBB1_2
.LBB1_24:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $120, %esi
.LBB1_2:
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl %ebx, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reversePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $_ZL8arr_size, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reversePfS_,@object # @_Z7reversePfS_
.section .rodata,"a",@progbits
.globl _Z7reversePfS_
.p2align 3, 0x0
_Z7reversePfS_:
.quad _Z22__device_stub__reversePfS_
.size _Z7reversePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/nikoSchoinas/phas0100_cuda/main/memory/memory.hip"
.size .L.str, 107
.type _ZL8arr_size,@object # @_ZL8arr_size
.local _ZL8arr_size
.comm _ZL8arr_size,4,4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Success! "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failure: "
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " elements were correctly swapped."
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA error: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " at "
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ":"
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reversePfS_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL8arr_size"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reversePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reversePfS_
.addrsig_sym _ZL8arr_size
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reversePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R0, c[0x0][0x0], R11 ; /* 0x0000000000027a24 */
/* 0x001fca00078e020b */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IADD3 R7, -R11, 0x7f, RZ ; /* 0x0000007f0b077810 */
/* 0x000fe40007ffe1ff */
/*0090*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fca0000000f00 */
/*00a0*/ IMAD R0, R0, R13, c[0x0][0x0] ; /* 0x0000000000007624 */
/* 0x000fca00078e020d */
/*00b0*/ IADD3 R0, R11, c[0x3][0x0], -R0 ; /* 0x00c000000b007a10 */
/* 0x000fca0007ffe800 */
/*00c0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0005 */
/*00d0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x004fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000e280000004800 */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reversePfS_
.globl _Z7reversePfS_
.p2align 8
.type _Z7reversePfS_,@function
_Z7reversePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL8arr_size@gotpcrel32@lo+4
s_addc_u32 s1, s1, _ZL8arr_size@gotpcrel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b32 v1, v[1:2], off
v_sub_nc_u32_e32 v2, 0x7f, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_not_b32 s1, s15
s_mul_i32 s4, s4, s1
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s0, s4, v0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v3
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reversePfS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reversePfS_, .Lfunc_end0-_Z7reversePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL8arr_size,@object
.section .bss,"aw",@nobits
.globl _ZL8arr_size
.p2align 2, 0x0
_ZL8arr_size:
.long 0
.size _ZL8arr_size, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL8arr_size
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reversePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reversePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013ccbf_00000000-6_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z14cudaErrorCheck9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " at "
.LC2:
.string ":"
.section .text._Z14cudaErrorCheck9cudaErrorPKci,"axG",@progbits,_Z14cudaErrorCheck9cudaErrorPKci,comdat
.weak _Z14cudaErrorCheck9cudaErrorPKci
.type _Z14cudaErrorCheck9cudaErrorPKci, @function
_Z14cudaErrorCheck9cudaErrorPKci:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %ebp
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z14cudaErrorCheck9cudaErrorPKci, .-_Z14cudaErrorCheck9cudaErrorPKci
.text
.globl _Z28__device_stub__Z7reversePfS_PfS_
.type _Z28__device_stub__Z7reversePfS_PfS_, @function
_Z28__device_stub__Z7reversePfS_PfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reversePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7reversePfS_PfS_, .-_Z28__device_stub__Z7reversePfS_PfS_
.globl _Z7reversePfS_
.type _Z7reversePfS_, @function
_Z7reversePfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reversePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7reversePfS_, .-_Z7reversePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Success! "
.LC4:
.string "Failure: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/nikoSchoinas/phas0100_cuda/main/memory/memory.cu"
.align 8
.LC7:
.string " elements were correctly swapped."
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $65536, 12(%rsp)
movl $262144, %edi
call malloc@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $66, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $69, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L18
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8arr_size(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
movl $79, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $84, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $95, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movl $2, %ecx
movl $262144, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $100, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movq %rbx, %rax
leaq 262140(%rbp), %rcx
leaq 262144(%rbx), %rdi
movl $0, %r12d
movl $0, %esi
.L20:
movss (%rax), %xmm0
ucomiss (%rcx), %xmm0
setnp %dl
movzbl %dl, %edx
cmovne %esi, %edx
addl %edx, %r12d
addq $4, %rax
subq $4, %rcx
cmpq %rdi, %rax
jne .L20
cmpl $65536, %r12d
leaq .LC4(%rip), %rsi
leaq .LC3(%rip), %rax
cmove %rax, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $113, %edx
leaq .LC5(%rip), %r12
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $116, %edx
movq %r12, %rsi
call _Z14cudaErrorCheck9cudaErrorPKci
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z7reversePfS_PfS_
jmp .L19
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7reversePfS_"
.LC9:
.string "arr_size"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reversePfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8arr_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8arr_size
.comm _ZL8arr_size,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reversePfS_ # -- Begin function _Z22__device_stub__reversePfS_
.p2align 4, 0x90
.type _Z22__device_stub__reversePfS_,@function
_Z22__device_stub__reversePfS_: # @_Z22__device_stub__reversePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reversePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reversePfS_, .Lfunc_end0-_Z22__device_stub__reversePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $65536, 28(%rsp) # imm = 0x10000
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %rbx
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14cudaErrorCheck10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
jne .LBB1_27
# %bb.4: # %_Z14cudaErrorCheck10hipError_tPKci.exit34.preheader
xorl %r15d, %r15d
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_5: # %_Z14cudaErrorCheck10hipError_tPKci.exit34
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $65536, %r15 # imm = 0x10000
jne .LBB1_5
# %bb.6:
leaq 28(%rsp), %rsi
movl $_ZL8arr_size, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_7
# %bb.8: # %_Z14cudaErrorCheck10hipError_tPKci.exit36
movq 16(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_Z14cudaErrorCheck10hipError_tPKci.exit38
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 384(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7reversePfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_13
# %bb.14: # %_Z14cudaErrorCheck10hipError_tPKci.exit40
movq 8(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_28
# %bb.15: # %_Z14cudaErrorCheck10hipError_tPKci.exit42.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_16: # %_Z14cudaErrorCheck10hipError_tPKci.exit42
# =>This Inner Loop Header: Depth=1
movq %rax, %rcx
xorq $65535, %rcx # imm = 0xFFFF
movss (%rbx,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpeqss (%r14,%rax,4), %xmm0
leaq 1(%rax), %rcx
movd %xmm0, %eax
subl %eax, %ebp
movq %rcx, %rax
cmpq $65536, %rcx # imm = 0x10000
jne .LBB1_16
# %bb.17:
cmpl $65536, %ebp # imm = 0x10000
movl $.L.str.1, %eax
movl $.L.str.2, %esi
cmoveq %rax, %rsi
movl $_ZSt4cout, %edi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $33, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_26
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_20
# %bb.19:
movzbl 67(%r12), %eax
jmp .LBB1_21
.LBB1_20:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z14cudaErrorCheck10hipError_tPKci.exit45
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z14cudaErrorCheck10hipError_tPKci.exit47
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 160
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $70, %esi
jmp .LBB1_2
.LBB1_27:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $73, %esi
jmp .LBB1_2
.LBB1_7:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $83, %esi
jmp .LBB1_2
.LBB1_9:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $88, %esi
jmp .LBB1_2
.LBB1_13:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $99, %esi
jmp .LBB1_2
.LBB1_28:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $104, %esi
jmp .LBB1_2
.LBB1_26:
callq _ZSt16__throw_bad_castv
.LBB1_22:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $117, %esi
jmp .LBB1_2
.LBB1_24:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $120, %esi
.LBB1_2:
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl %ebx, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reversePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $_ZL8arr_size, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reversePfS_,@object # @_Z7reversePfS_
.section .rodata,"a",@progbits
.globl _Z7reversePfS_
.p2align 3, 0x0
_Z7reversePfS_:
.quad _Z22__device_stub__reversePfS_
.size _Z7reversePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/nikoSchoinas/phas0100_cuda/main/memory/memory.hip"
.size .L.str, 107
.type _ZL8arr_size,@object # @_ZL8arr_size
.local _ZL8arr_size
.comm _ZL8arr_size,4,4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Success! "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failure: "
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " elements were correctly swapped."
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA error: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " at "
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ":"
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reversePfS_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL8arr_size"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reversePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reversePfS_
.addrsig_sym _ZL8arr_size
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
swap_reflect(float *A, int numElements)
{
int i=blockIdx.x;
int j=threadIdx.x;
float temp;
if ((i < numElements) && (j < numElements -1) && ((j)%2==0))
{
temp = A[i*numElements + j];
A[i*numElements + j] = A[i*numElements + j + 1];
A[i*numElements + j + 1] = temp;
}
__syncthreads();
if((i < numElements) && (j < numElements) && (i>j) && (i!=j))
{
A[j*numElements + i] = A[i*numElements + j];
//__syncthreads();
}
} | code for sm_80
Function : _Z12swap_reflectPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0060*/ BSSY B0, 0x160 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x041fe40003f06270 */
/*0080*/ LOP3.LUT R0, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109007812 */
/* 0x042fe200078ec0ff */
/*0090*/ IMAD R2, R4, c[0x0][0x168], R9 ; /* 0x00005a0004027a24 */
/* 0x000fe200078e0209 */
/*00a0*/ ISETP.GE.OR P1, PT, R9.reuse, UR4, P0 ; /* 0x0000000409007c0c */
/* 0x040fe20008726670 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x168], P0 ; /* 0x00005a0009007a0c */
/* 0x000fe20000706670 */
/*00d0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e020b */
/*00e0*/ ISETP.EQ.U32.OR P1, PT, R0, 0x1, P1 ; /* 0x000000010000780c */
/* 0x000fc40000f22470 */
/*00f0*/ ISETP.LE.OR P0, PT, R4, R9, P0 ; /* 0x000000090400720c */
/* 0x000fd60000703670 */
/*0100*/ @P1 BRA 0x150 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee8000c1e1900 */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101904 */
/*0140*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x0081e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*0190*/ IMAD R4, R9, c[0x0][0x168], R4 ; /* 0x00005a0009047a24 */
/* 0x000fc800078e0204 */
/*01a0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020b */
/*01b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
swap_reflect(float *A, int numElements)
{
int i=blockIdx.x;
int j=threadIdx.x;
float temp;
if ((i < numElements) && (j < numElements -1) && ((j)%2==0))
{
temp = A[i*numElements + j];
A[i*numElements + j] = A[i*numElements + j + 1];
A[i*numElements + j + 1] = temp;
}
__syncthreads();
if((i < numElements) && (j < numElements) && (i>j) && (i!=j))
{
A[j*numElements + i] = A[i*numElements + j];
//__syncthreads();
}
} | .file "tmpxft_000b152a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12swap_reflectPfiPfi
.type _Z33__device_stub__Z12swap_reflectPfiPfi, @function
_Z33__device_stub__Z12swap_reflectPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12swap_reflectPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z12swap_reflectPfiPfi, .-_Z33__device_stub__Z12swap_reflectPfiPfi
.globl _Z12swap_reflectPfi
.type _Z12swap_reflectPfi, @function
_Z12swap_reflectPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12swap_reflectPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12swap_reflectPfi, .-_Z12swap_reflectPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12swap_reflectPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12swap_reflectPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
swap_reflect(float *A, int numElements)
{
int i=blockIdx.x;
int j=threadIdx.x;
float temp;
if ((i < numElements) && (j < numElements -1) && ((j)%2==0))
{
temp = A[i*numElements + j];
A[i*numElements + j] = A[i*numElements + j + 1];
A[i*numElements + j + 1] = temp;
}
__syncthreads();
if((i < numElements) && (j < numElements) && (i>j) && (i!=j))
{
A[j*numElements + i] = A[i*numElements + j];
//__syncthreads();
}
} | #include <hip/hip_runtime.h>
__global__ void
swap_reflect(float *A, int numElements)
{
int i=blockIdx.x;
int j=threadIdx.x;
float temp;
if ((i < numElements) && (j < numElements -1) && ((j)%2==0))
{
temp = A[i*numElements + j];
A[i*numElements + j] = A[i*numElements + j + 1];
A[i*numElements + j + 1] = temp;
}
__syncthreads();
if((i < numElements) && (j < numElements) && (i>j) && (i!=j))
{
A[j*numElements + i] = A[i*numElements + j];
//__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
swap_reflect(float *A, int numElements)
{
int i=blockIdx.x;
int j=threadIdx.x;
float temp;
if ((i < numElements) && (j < numElements -1) && ((j)%2==0))
{
temp = A[i*numElements + j];
A[i*numElements + j] = A[i*numElements + j + 1];
A[i*numElements + j + 1] = temp;
}
__syncthreads();
if((i < numElements) && (j < numElements) && (i>j) && (i!=j))
{
A[j*numElements + i] = A[i*numElements + j];
//__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12swap_reflectPfi
.globl _Z12swap_reflectPfi
.p2align 8
.type _Z12swap_reflectPfi,@function
_Z12swap_reflectPfi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v1, 1, v0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s15, s5
s_cselect_b32 s1, -1, 0
s_add_i32 s0, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
v_cmp_eq_u32_e64 s0, 0, v1
s_and_b32 s6, s1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v3
global_store_b64 v[1:2], v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_min_i32 s0, s4, s5
s_waitcnt_vscnt null, 0x0
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_barrier
buffer_gl0_inv
s_and_b32 s0, s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, v0, s5, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12swap_reflectPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12swap_reflectPfi, .Lfunc_end0-_Z12swap_reflectPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12swap_reflectPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12swap_reflectPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
swap_reflect(float *A, int numElements)
{
int i=blockIdx.x;
int j=threadIdx.x;
float temp;
if ((i < numElements) && (j < numElements -1) && ((j)%2==0))
{
temp = A[i*numElements + j];
A[i*numElements + j] = A[i*numElements + j + 1];
A[i*numElements + j + 1] = temp;
}
__syncthreads();
if((i < numElements) && (j < numElements) && (i>j) && (i!=j))
{
A[j*numElements + i] = A[i*numElements + j];
//__syncthreads();
}
} | .text
.file "kernel.hip"
.globl _Z27__device_stub__swap_reflectPfi # -- Begin function _Z27__device_stub__swap_reflectPfi
.p2align 4, 0x90
.type _Z27__device_stub__swap_reflectPfi,@function
_Z27__device_stub__swap_reflectPfi: # @_Z27__device_stub__swap_reflectPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12swap_reflectPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__swap_reflectPfi, .Lfunc_end0-_Z27__device_stub__swap_reflectPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12swap_reflectPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12swap_reflectPfi,@object # @_Z12swap_reflectPfi
.section .rodata,"a",@progbits
.globl _Z12swap_reflectPfi
.p2align 3, 0x0
_Z12swap_reflectPfi:
.quad _Z27__device_stub__swap_reflectPfi
.size _Z12swap_reflectPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12swap_reflectPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__swap_reflectPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12swap_reflectPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12swap_reflectPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0060*/ BSSY B0, 0x160 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x041fe40003f06270 */
/*0080*/ LOP3.LUT R0, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109007812 */
/* 0x042fe200078ec0ff */
/*0090*/ IMAD R2, R4, c[0x0][0x168], R9 ; /* 0x00005a0004027a24 */
/* 0x000fe200078e0209 */
/*00a0*/ ISETP.GE.OR P1, PT, R9.reuse, UR4, P0 ; /* 0x0000000409007c0c */
/* 0x040fe20008726670 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x168], P0 ; /* 0x00005a0009007a0c */
/* 0x000fe20000706670 */
/*00d0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e020b */
/*00e0*/ ISETP.EQ.U32.OR P1, PT, R0, 0x1, P1 ; /* 0x000000010000780c */
/* 0x000fc40000f22470 */
/*00f0*/ ISETP.LE.OR P0, PT, R4, R9, P0 ; /* 0x000000090400720c */
/* 0x000fd60000703670 */
/*0100*/ @P1 BRA 0x150 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee8000c1e1900 */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101904 */
/*0140*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x0081e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*0190*/ IMAD R4, R9, c[0x0][0x168], R4 ; /* 0x00005a0009047a24 */
/* 0x000fc800078e0204 */
/*01a0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020b */
/*01b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12swap_reflectPfi
.globl _Z12swap_reflectPfi
.p2align 8
.type _Z12swap_reflectPfi,@function
_Z12swap_reflectPfi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v1, 1, v0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s15, s5
s_cselect_b32 s1, -1, 0
s_add_i32 s0, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
v_cmp_eq_u32_e64 s0, 0, v1
s_and_b32 s6, s1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v3
global_store_b64 v[1:2], v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_min_i32 s0, s4, s5
s_waitcnt_vscnt null, 0x0
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_barrier
buffer_gl0_inv
s_and_b32 s0, s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, v0, s5, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12swap_reflectPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12swap_reflectPfi, .Lfunc_end0-_Z12swap_reflectPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12swap_reflectPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12swap_reflectPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b152a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12swap_reflectPfiPfi
.type _Z33__device_stub__Z12swap_reflectPfiPfi, @function
_Z33__device_stub__Z12swap_reflectPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12swap_reflectPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z12swap_reflectPfiPfi, .-_Z33__device_stub__Z12swap_reflectPfiPfi
.globl _Z12swap_reflectPfi
.type _Z12swap_reflectPfi, @function
_Z12swap_reflectPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12swap_reflectPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12swap_reflectPfi, .-_Z12swap_reflectPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12swap_reflectPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12swap_reflectPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z27__device_stub__swap_reflectPfi # -- Begin function _Z27__device_stub__swap_reflectPfi
.p2align 4, 0x90
.type _Z27__device_stub__swap_reflectPfi,@function
_Z27__device_stub__swap_reflectPfi: # @_Z27__device_stub__swap_reflectPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12swap_reflectPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__swap_reflectPfi, .Lfunc_end0-_Z27__device_stub__swap_reflectPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12swap_reflectPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12swap_reflectPfi,@object # @_Z12swap_reflectPfi
.section .rodata,"a",@progbits
.globl _Z12swap_reflectPfi
.p2align 3, 0x0
_Z12swap_reflectPfi:
.quad _Z27__device_stub__swap_reflectPfi
.size _Z12swap_reflectPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12swap_reflectPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__swap_reflectPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12swap_reflectPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 1024
#define TIME 3600000
__global__ void initialize(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
if(ix==0)
{
a_d[ix]=200.0;
b_d[ix]=200.0;
}
else if (ix<arraySize)
{
a_d[ix]=0.0;
b_d[ix]=0.0;
}
}
__global__ void compute(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float temp;
if( ix > 0 && ix < arraySize-1){
temp = (a_d[ix+1]+a_d[ix-1])/2.0;
__syncthreads();
b_d[ix]=temp;
__syncthreads();
}
}
extern "C" void pointsource_pollution (float *a, float *b, int *c, int arraySize)
{
float *a_d, *b_d, *c_d;
cudaMalloc ((void**) &a_d, sizeof(float) * arraySize);
cudaMalloc ((void**) &b_d, sizeof(float) * arraySize);
cudaMalloc ((void**) &c_d, sizeof(float) * arraySize);
initialize<<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
for(int i=0;i<TIME;i++){
compute <<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
a_d=b_d;
}
cudaMemcpy (a, a_d, sizeof(float) * arraySize, cudaMemcpyDeviceToHost);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf ("CUDA error: %s\n", cudaGetErrorString(err));
cudaFree (a_d);
cudaFree (b_d);
cudaFree (c_d);
} | code for sm_80
Function : _Z7computePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fc8000bf06270 */
/*0070*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0207 */
/*00c0*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x004fe40000000000 */
/*0100*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0207 */
/*0110*/ FMUL R7, R0, 0.5 ; /* 0x3f00000000077820 */
/* 0x000fca0000400000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0060*/ @!P0 BRA 0xf0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*00c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x43480000 ; /* 0x43480000ff077424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fc600078e00ff */
/*0140*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 1024
#define TIME 3600000
__global__ void initialize(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
if(ix==0)
{
a_d[ix]=200.0;
b_d[ix]=200.0;
}
else if (ix<arraySize)
{
a_d[ix]=0.0;
b_d[ix]=0.0;
}
}
__global__ void compute(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float temp;
if( ix > 0 && ix < arraySize-1){
temp = (a_d[ix+1]+a_d[ix-1])/2.0;
__syncthreads();
b_d[ix]=temp;
__syncthreads();
}
}
extern "C" void pointsource_pollution (float *a, float *b, int *c, int arraySize)
{
float *a_d, *b_d, *c_d;
cudaMalloc ((void**) &a_d, sizeof(float) * arraySize);
cudaMalloc ((void**) &b_d, sizeof(float) * arraySize);
cudaMalloc ((void**) &c_d, sizeof(float) * arraySize);
initialize<<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
for(int i=0;i<TIME;i++){
compute <<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
a_d=b_d;
}
cudaMemcpy (a, a_d, sizeof(float) * arraySize, cudaMemcpyDeviceToHost);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf ("CUDA error: %s\n", cudaGetErrorString(err));
cudaFree (a_d);
cudaFree (b_d);
cudaFree (c_d);
} | .file "tmpxft_00163be4_00000000-6_pointsource_par.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10initializePfS_S_iPfS_S_i
.type _Z35__device_stub__Z10initializePfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10initializePfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10initializePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10initializePfS_S_iPfS_S_i, .-_Z35__device_stub__Z10initializePfS_S_iPfS_S_i
.globl _Z10initializePfS_S_i
.type _Z10initializePfS_S_i, @function
_Z10initializePfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10initializePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10initializePfS_S_i, .-_Z10initializePfS_S_i
.globl _Z31__device_stub__Z7computePfS_S_iPfS_S_i
.type _Z31__device_stub__Z7computePfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7computePfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z7computePfS_S_iPfS_S_i, .-_Z31__device_stub__Z7computePfS_S_iPfS_S_i
.globl _Z7computePfS_S_i
.type _Z7computePfS_S_i, @function
_Z7computePfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7computePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7computePfS_S_i, .-_Z7computePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CUDA error: %s\n"
.text
.globl pointsource_pollution
.type pointsource_pollution, @function
pointsource_pollution:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %ecx, %r13
salq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC5(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2siq %xmm3, %rax
movl %eax, %ebp
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
movl $3600000, %ebx
jmp .L23
.L28:
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10initializePfS_S_iPfS_S_i
jmp .L21
.L22:
movq 16(%rsp), %rsi
movq %rsi, 8(%rsp)
subl $1, %ebx
je .L29
.L23:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z7computePfS_S_iPfS_S_i
jmp .L22
.L29:
movl $2, %ecx
movq %r13, %rdx
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
.L24:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size pointsource_pollution, .-pointsource_pollution
.section .rodata.str1.1
.LC6:
.string "_Z7computePfS_S_i"
.LC7:
.string "_Z10initializePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC5:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 1024
#define TIME 3600000
__global__ void initialize(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
if(ix==0)
{
a_d[ix]=200.0;
b_d[ix]=200.0;
}
else if (ix<arraySize)
{
a_d[ix]=0.0;
b_d[ix]=0.0;
}
}
__global__ void compute(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float temp;
if( ix > 0 && ix < arraySize-1){
temp = (a_d[ix+1]+a_d[ix-1])/2.0;
__syncthreads();
b_d[ix]=temp;
__syncthreads();
}
}
extern "C" void pointsource_pollution (float *a, float *b, int *c, int arraySize)
{
float *a_d, *b_d, *c_d;
cudaMalloc ((void**) &a_d, sizeof(float) * arraySize);
cudaMalloc ((void**) &b_d, sizeof(float) * arraySize);
cudaMalloc ((void**) &c_d, sizeof(float) * arraySize);
initialize<<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
for(int i=0;i<TIME;i++){
compute <<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
a_d=b_d;
}
cudaMemcpy (a, a_d, sizeof(float) * arraySize, cudaMemcpyDeviceToHost);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf ("CUDA error: %s\n", cudaGetErrorString(err));
cudaFree (a_d);
cudaFree (b_d);
cudaFree (c_d);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 1024
#define TIME 3600000
__global__ void initialize(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
if(ix==0)
{
a_d[ix]=200.0;
b_d[ix]=200.0;
}
else if (ix<arraySize)
{
a_d[ix]=0.0;
b_d[ix]=0.0;
}
}
__global__ void compute(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float temp;
if( ix > 0 && ix < arraySize-1){
temp = (a_d[ix+1]+a_d[ix-1])/2.0;
__syncthreads();
b_d[ix]=temp;
__syncthreads();
}
}
extern "C" void pointsource_pollution (float *a, float *b, int *c, int arraySize)
{
float *a_d, *b_d, *c_d;
hipMalloc ((void**) &a_d, sizeof(float) * arraySize);
hipMalloc ((void**) &b_d, sizeof(float) * arraySize);
hipMalloc ((void**) &c_d, sizeof(float) * arraySize);
initialize<<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
for(int i=0;i<TIME;i++){
compute <<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
a_d=b_d;
}
hipMemcpy (a, a_d, sizeof(float) * arraySize, hipMemcpyDeviceToHost);
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf ("CUDA error: %s\n", hipGetErrorString(err));
hipFree (a_d);
hipFree (b_d);
hipFree (c_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 1024
#define TIME 3600000
__global__ void initialize(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
if(ix==0)
{
a_d[ix]=200.0;
b_d[ix]=200.0;
}
else if (ix<arraySize)
{
a_d[ix]=0.0;
b_d[ix]=0.0;
}
}
__global__ void compute(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float temp;
if( ix > 0 && ix < arraySize-1){
temp = (a_d[ix+1]+a_d[ix-1])/2.0;
__syncthreads();
b_d[ix]=temp;
__syncthreads();
}
}
extern "C" void pointsource_pollution (float *a, float *b, int *c, int arraySize)
{
float *a_d, *b_d, *c_d;
hipMalloc ((void**) &a_d, sizeof(float) * arraySize);
hipMalloc ((void**) &b_d, sizeof(float) * arraySize);
hipMalloc ((void**) &c_d, sizeof(float) * arraySize);
initialize<<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
for(int i=0;i<TIME;i++){
compute <<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
a_d=b_d;
}
hipMemcpy (a, a_d, sizeof(float) * arraySize, hipMemcpyDeviceToHost);
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf ("CUDA error: %s\n", hipGetErrorString(err));
hipFree (a_d);
hipFree (b_d);
hipFree (c_d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePfS_S_i
.globl _Z10initializePfS_S_i
.p2align 8
.type _Z10initializePfS_S_i,@function
_Z10initializePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execnz .LBB0_6
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x43480000
s_clause 0x1
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePfS_S_i, .Lfunc_end0-_Z10initializePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7computePfS_S_i
.globl _Z7computePfS_S_i
.p2align 8
.type _Z7computePfS_S_i,@function
_Z7computePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off offset:4
global_load_b32 v2, v[2:3], off offset:-4
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0.5, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7computePfS_S_i, .Lfunc_end1-_Z7computePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 1024
#define TIME 3600000
__global__ void initialize(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
if(ix==0)
{
a_d[ix]=200.0;
b_d[ix]=200.0;
}
else if (ix<arraySize)
{
a_d[ix]=0.0;
b_d[ix]=0.0;
}
}
__global__ void compute(float *a_d, float *b_d, float *c_d, int arraySize)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x;
float temp;
if( ix > 0 && ix < arraySize-1){
temp = (a_d[ix+1]+a_d[ix-1])/2.0;
__syncthreads();
b_d[ix]=temp;
__syncthreads();
}
}
extern "C" void pointsource_pollution (float *a, float *b, int *c, int arraySize)
{
float *a_d, *b_d, *c_d;
hipMalloc ((void**) &a_d, sizeof(float) * arraySize);
hipMalloc ((void**) &b_d, sizeof(float) * arraySize);
hipMalloc ((void**) &c_d, sizeof(float) * arraySize);
initialize<<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
for(int i=0;i<TIME;i++){
compute <<< ceil((float) arraySize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (a_d, b_d, c_d, arraySize);
a_d=b_d;
}
hipMemcpy (a, a_d, sizeof(float) * arraySize, hipMemcpyDeviceToHost);
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf ("CUDA error: %s\n", hipGetErrorString(err));
hipFree (a_d);
hipFree (b_d);
hipFree (c_d);
} | .text
.file "pointsource_par.hip"
.globl _Z25__device_stub__initializePfS_S_i # -- Begin function _Z25__device_stub__initializePfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__initializePfS_S_i,@function
_Z25__device_stub__initializePfS_S_i: # @_Z25__device_stub__initializePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10initializePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__initializePfS_S_i, .Lfunc_end0-_Z25__device_stub__initializePfS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfS_S_i # -- Begin function _Z22__device_stub__computePfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__computePfS_S_i,@function
_Z22__device_stub__computePfS_S_i: # @_Z22__device_stub__computePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__computePfS_S_i, .Lfunc_end1-_Z22__device_stub__computePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function pointsource_pollution
.LCPI2_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl pointsource_pollution
.p2align 4, 0x90
.type pointsource_pollution,@function
pointsource_pollution: # @pointsource_pollution
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 160(%rsp) # 8-byte Spill
movabsq $4294968320, %r15 # imm = 0x100000400
movl %ecx, 20(%rsp) # 4-byte Spill
movslq %ecx, %rbx
leaq (,%rbx,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, 152(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
cvtsi2ss %ebx, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %eax
leaq (%rax,%r15), %r12
addq $-1024, %r12 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10initializePfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl $3600000, %ebp # imm = 0x36EE80
leaq 48(%rsp), %r14
leaq 40(%rsp), %r13
leaq 112(%rsp), %rbx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
movq 24(%rsp), %rax
movq %rax, 8(%rsp)
decl %ebp
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
movq %r14, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z7computePfS_S_i, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.LBB2_6:
movq 8(%rsp), %rsi
movq 160(%rsp), %rdi # 8-byte Reload
movq 152(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_8:
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size pointsource_pollution, .Lfunc_end2-pointsource_pollution
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializePfS_S_i,@object # @_Z10initializePfS_S_i
.section .rodata,"a",@progbits
.globl _Z10initializePfS_S_i
.p2align 3, 0x0
_Z10initializePfS_S_i:
.quad _Z25__device_stub__initializePfS_S_i
.size _Z10initializePfS_S_i, 8
.type _Z7computePfS_S_i,@object # @_Z7computePfS_S_i
.globl _Z7computePfS_S_i
.p2align 3, 0x0
_Z7computePfS_S_i:
.quad _Z22__device_stub__computePfS_S_i
.size _Z7computePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePfS_S_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7computePfS_S_i"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePfS_S_i
.addrsig_sym _Z22__device_stub__computePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10initializePfS_S_i
.addrsig_sym _Z7computePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fc8000bf06270 */
/*0070*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0207 */
/*00c0*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x004fe40000000000 */
/*0100*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0207 */
/*0110*/ FMUL R7, R0, 0.5 ; /* 0x3f00000000077820 */
/* 0x000fca0000400000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0060*/ @!P0 BRA 0xf0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*00c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x43480000 ; /* 0x43480000ff077424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fc600078e00ff */
/*0140*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0150*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePfS_S_i
.globl _Z10initializePfS_S_i
.p2align 8
.type _Z10initializePfS_S_i,@function
_Z10initializePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execnz .LBB0_6
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x43480000
s_clause 0x1
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePfS_S_i, .Lfunc_end0-_Z10initializePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7computePfS_S_i
.globl _Z7computePfS_S_i
.p2align 8
.type _Z7computePfS_S_i,@function
_Z7computePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off offset:4
global_load_b32 v2, v[2:3], off offset:-4
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0.5, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7computePfS_S_i, .Lfunc_end1-_Z7computePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00163be4_00000000-6_pointsource_par.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10initializePfS_S_iPfS_S_i
.type _Z35__device_stub__Z10initializePfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10initializePfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10initializePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10initializePfS_S_iPfS_S_i, .-_Z35__device_stub__Z10initializePfS_S_iPfS_S_i
.globl _Z10initializePfS_S_i
.type _Z10initializePfS_S_i, @function
_Z10initializePfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10initializePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10initializePfS_S_i, .-_Z10initializePfS_S_i
.globl _Z31__device_stub__Z7computePfS_S_iPfS_S_i
.type _Z31__device_stub__Z7computePfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7computePfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z7computePfS_S_iPfS_S_i, .-_Z31__device_stub__Z7computePfS_S_iPfS_S_i
.globl _Z7computePfS_S_i
.type _Z7computePfS_S_i, @function
_Z7computePfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7computePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7computePfS_S_i, .-_Z7computePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CUDA error: %s\n"
.text
.globl pointsource_pollution
.type pointsource_pollution, @function
pointsource_pollution:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %ecx, %r13
salq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC5(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2siq %xmm3, %rax
movl %eax, %ebp
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
movl $3600000, %ebx
jmp .L23
.L28:
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10initializePfS_S_iPfS_S_i
jmp .L21
.L22:
movq 16(%rsp), %rsi
movq %rsi, 8(%rsp)
subl $1, %ebx
je .L29
.L23:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z7computePfS_S_iPfS_S_i
jmp .L22
.L29:
movl $2, %ecx
movq %r13, %rdx
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
.L24:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size pointsource_pollution, .-pointsource_pollution
.section .rodata.str1.1
.LC6:
.string "_Z7computePfS_S_i"
.LC7:
.string "_Z10initializePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC5:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pointsource_par.hip"
.globl _Z25__device_stub__initializePfS_S_i # -- Begin function _Z25__device_stub__initializePfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__initializePfS_S_i,@function
_Z25__device_stub__initializePfS_S_i: # @_Z25__device_stub__initializePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10initializePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__initializePfS_S_i, .Lfunc_end0-_Z25__device_stub__initializePfS_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfS_S_i # -- Begin function _Z22__device_stub__computePfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__computePfS_S_i,@function
_Z22__device_stub__computePfS_S_i: # @_Z22__device_stub__computePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__computePfS_S_i, .Lfunc_end1-_Z22__device_stub__computePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function pointsource_pollution
.LCPI2_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl pointsource_pollution
.p2align 4, 0x90
.type pointsource_pollution,@function
pointsource_pollution: # @pointsource_pollution
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 160(%rsp) # 8-byte Spill
movabsq $4294968320, %r15 # imm = 0x100000400
movl %ecx, 20(%rsp) # 4-byte Spill
movslq %ecx, %rbx
leaq (,%rbx,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, 152(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
cvtsi2ss %ebx, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %eax
leaq (%rax,%r15), %r12
addq $-1024, %r12 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10initializePfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl $3600000, %ebp # imm = 0x36EE80
leaq 48(%rsp), %r14
leaq 40(%rsp), %r13
leaq 112(%rsp), %rbx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
movq 24(%rsp), %rax
movq %rax, 8(%rsp)
decl %ebp
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
movq %r14, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z7computePfS_S_i, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.LBB2_6:
movq 8(%rsp), %rsi
movq 160(%rsp), %rdi # 8-byte Reload
movq 152(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_8:
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size pointsource_pollution, .Lfunc_end2-pointsource_pollution
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializePfS_S_i,@object # @_Z10initializePfS_S_i
.section .rodata,"a",@progbits
.globl _Z10initializePfS_S_i
.p2align 3, 0x0
_Z10initializePfS_S_i:
.quad _Z25__device_stub__initializePfS_S_i
.size _Z10initializePfS_S_i, 8
.type _Z7computePfS_S_i,@object # @_Z7computePfS_S_i
.globl _Z7computePfS_S_i
.p2align 3, 0x0
_Z7computePfS_S_i:
.quad _Z22__device_stub__computePfS_S_i
.size _Z7computePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePfS_S_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7computePfS_S_i"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePfS_S_i
.addrsig_sym _Z22__device_stub__computePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10initializePfS_S_i
.addrsig_sym _Z7computePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*#include "device_atomic_functions.h"
__global__
void inner_product1_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N_ln*N_ln; i++)
if (i < N_ln*N_ln)
temp[threadIdx.x] = a[i] * b[i];
__syncthreads();
//parallel reduction
//for (int j = threadIdx.x; j < N_ln*N_ln ; j += blockDim.x)
return;
}
__global__
void inner_product2_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j]
return;
}
*/
__global__
void laplacian_GPU(double *La, double *x, double dx, double dy, int N, int N_ln)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < N_ln && j < N_ln)
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) / (dx * dy);
return;
}
__global__
void YPEAX_GPU(double *y, double *x, double a, int N) // Y += a*X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N * N; i++)
if (i< N*N)
y[i] += a * x[i];
return;
}
__global__
void YEAYPX_GPU(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
return;
}
double inner_product(double *a, double *b, int type, int N, int N_ln)
{
double kk = 0.0;
int i, j;
if (type == 0)
{ // for N_ln^2 * N_ln^2
for ( i = 0; i < N_ln * N_ln; i++)
{
kk += a[i] * b[i];
}
}
else
{ // for N^2 * N_ln^2
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j];
}
}
}
return kk;
}
void laplacian(double *La, double *x, double dx, double dy, int N, int N_ln)
{
int i, j;
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) /
(dx * dy);
}
}
return;
}
void YEAYPX(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
// const int i = blockIdx.x*blockDim.x + threadIdx.x;
// const int j = blockIdx.y*blockDim.y + threadIdx.y;
int i,j;
for ( i = 0; i < N_ln; i++)
for ( j = 0; j < N_ln; j++)
{
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
}
return;
} | code for sm_80
Function : _Z10YEAYPX_GPUPdS_dii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x17c], P0 ; /* 0x00005f0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IADD3 R2, R0.reuse, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD R6, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000067a24 */
/* 0x000fe200078e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD R2, R2, c[0x0][0x178], R3 ; /* 0x00005e0002027a24 */
/* 0x000fc800078e0203 */
/*00f0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0205 */
/*0110*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x000ea4000c1e1b00 */
/*0130*/ DFMA R4, R4, c[0x0][0x170], R6 ; /* 0x00005c0004047a2b */
/* 0x004e0e0000000006 */
/*0140*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9YPEAX_GPUPdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00e0*/ DFMA R6, R2, c[0x0][0x170], R6 ; /* 0x00005c0002067a2b */
/* 0x004e0e0000000006 */
/*00f0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13laplacian_GPUPdS_ddii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x184], P0 ; /* 0x0000610000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R0, c[0x0][0x180], RZ ; /* 0x0000600000027a24 */
/* 0x000fe200078e02ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD R4, R5, 0x2, R2.reuse ; /* 0x0000000205047824 */
/* 0x100fe400078e0202 */
/*00f0*/ IMAD.IADD R12, R3.reuse, 0x1, R2 ; /* 0x00000001030c7824 */
/* 0x040fe400078e0202 */
/*0100*/ IMAD.IADD R14, R3.reuse, 0x1, R4.reuse ; /* 0x00000001030e7824 */
/* 0x140fe200078e0204 */
/*0110*/ IADD3 R16, R3, -c[0x0][0x180], R4 ; /* 0x8000600003107a10 */
/* 0x000fe20007ffe004 */
/*0120*/ IMAD.WIDE R12, R12, R17, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e0211 */
/*0130*/ IMAD.WIDE R14, R14, R17.reuse, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x080fe400078e0211 */
/*0140*/ LDG.E.64 R12, [R12.64+0x8] ; /* 0x000008040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0150*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fe400078e0211 */
/*0160*/ LDG.E.64 R14, [R14.64+0x8] ; /* 0x000008040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ee8000c1e1b00 */
/*0180*/ LDG.E.64 R4, [R16.64+0x10] ; /* 0x0000100410047981 */
/* 0x000f28000c1e1b00 */
/*0190*/ LDG.E.64 R6, [R16.64+0x8] ; /* 0x0000080410067981 */
/* 0x000f62000c1e1b00 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fe200078e00ff */
/*01b0*/ BSSY B0, 0x350 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fc400078e00ff */
/*01d0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fc800078e00ff */
/*01e0*/ DMUL R8, R8, c[0x0][0x178] ; /* 0x00005e0008087a28 */
/* 0x000e0c0000000000 */
/*01f0*/ MUFU.RCP64H R19, R9 ; /* 0x0000000900137308 */
/* 0x001e240000001800 */
/*0200*/ DFMA R20, -R8, R18, 1 ; /* 0x3ff000000814742b */
/* 0x001e0c0000000112 */
/*0210*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e0c0000000014 */
/*0220*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001fc80000000012 */
/*0230*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x004ecc000000000c */
/*0240*/ DADD R10, R12, R10 ; /* 0x000000000c0a7229 */
/* 0x008f08000000000a */
/*0250*/ DFMA R12, -R8, R20, 1 ; /* 0x3ff00000080c742b */
/* 0x000e080000000114 */
/*0260*/ DADD R4, R10, R4 ; /* 0x000000000a047229 */
/* 0x010f480000000004 */
/*0270*/ DFMA R12, R20, R12, R20 ; /* 0x0000000c140c722b */
/* 0x001fc80000000014 */
/*0280*/ DFMA R6, R6, -4, R4 ; /* 0xc01000000606782b */
/* 0x020e0c0000000004 */
/*0290*/ DMUL R4, R6, R12 ; /* 0x0000000c06047228 */
/* 0x001e080000000000 */
/*02a0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*02b0*/ DFMA R10, -R8, R4, R6 ; /* 0x00000004080a722b */
/* 0x001e0c0000000106 */
/*02c0*/ DFMA R4, R12, R10, R4 ; /* 0x0000000a0c04722b */
/* 0x001e140000000004 */
/*02d0*/ FFMA R2, RZ, R9, R5 ; /* 0x00000009ff027223 */
/* 0x001fca0000000005 */
/*02e0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fda0003f04200 */
/*02f0*/ @P0 BRA P1, 0x340 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0300*/ MOV R2, 0x320 ; /* 0x0000032000027802 */
/* 0x000fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0x3a0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD R3, R0, c[0x0][0x184], R3 ; /* 0x0000610000037a24 */
/* 0x000fc800078e0203 */
/*0370*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0380*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.GEU.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x000fe20003f0e200 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R8.reuse ; /* 0x000000ffff0a7224 */
/* 0x100fe200078e0008 */
/*03c0*/ FSETP.GEU.AND P2, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x000fe20003f4e200 */
/*03d0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*03e0*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*03f0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0400*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*0410*/ BSSY B1, 0x950 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*0420*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0440*/ LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009117812 */
/* 0x000fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0006 */
/*0460*/ @!P0 DMUL R4, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a048828 */
/* 0x000e220000000000 */
/*0470*/ ISETP.GE.U32.AND P1, PT, R12.reuse, R17, PT ; /* 0x000000110c00720c */
/* 0x040fe20003f26070 */
/*0480*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0490*/ @!P2 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0da812 */
/* 0x000fe200078ec0ff */
/*04a0*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*04b0*/ MUFU.RCP64H R15, R5 ; /* 0x00000005000f7308 */
/* 0x001e220000001800 */
/*04c0*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R13, PT ; /* 0x0000000d0c00a20c */
/* 0x000fe20003f66070 */
/*04d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe400078e00ff */
/*04e0*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fc600078ec0ff */
/*04f0*/ @!P2 SEL R21, R13.reuse, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x040fe40005800000 */
/*0500*/ SEL R9, R13, 0x63400000, !P1 ; /* 0x634000000d097807 */
/* 0x000fe40004800000 */
/*0510*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7.reuse, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x100fe400078ef807 */
/*0520*/ LOP3.LUT R9, R9, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fe400078ef807 */
/*0530*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0540*/ DFMA R18, R14, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x001e220000000804 */
/*0550*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc80007ffe0ff */
/*0560*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*0570*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0580*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0590*/ @!P2 LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000910a812 */
/* 0x000fc800078ec0ff */
/*05a0*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ DFMA R18, R14, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000804 */
/*05c0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*05d0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*05e0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*05f0*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0600*/ DFMA R20, R18, -R4, R8 ; /* 0x800000041214722b */
/* 0x001e0c0000000008 */
/*0610*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0620*/ @P0 BRA 0x7f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0630*/ LOP3.LUT R7, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b077812 */
/* 0x000fc800078ec0ff */
/*0640*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*0650*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*0660*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*0670*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0680*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0690*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*06a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*06b0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*06c0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x002e540000000000 */
/*06d0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*06e0*/ @P0 BRA 0x940 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*06f0*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e620000000008 */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0710*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x042fe40003f0d000 */
/*0720*/ LOP3.LUT R11, R5, 0x80000000, R11, 0x48, !PT ; /* 0x80000000050b7812 */
/* 0x000fc800078e480b */
/*0730*/ LOP3.LUT R7, R11, R7, RZ, 0xfc, !PT ; /* 0x000000070b077212 */
/* 0x000fce00078efcff */
/*0740*/ @!P0 BRA 0x940 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0760*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e620000008000 */
/*0770*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0780*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e86000000000e */
/*0790*/ LOP3.LUT R11, R7, R11, RZ, 0x3c, !PT ; /* 0x0000000b070b7212 */
/* 0x002fc600078e3cff */
/*07a0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x004fc80007ffe1ff */
/*07b0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*07c0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*07d0*/ FSEL R13, R11, R13, !P0 ; /* 0x0000000d0b0d7208 */
/* 0x000fe20004000000 */
/*07e0*/ BRA 0x940 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*07f0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0800*/ @P0 BRA 0x920 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0810*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*0820*/ @P0 BRA 0x8f0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0830*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0840*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0860*/ @!P0 BRA 0x940 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0880*/ LOP3.LUT R13, R7, 0x80000000, R11, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e480b */
/*0890*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*08a0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*08b0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*08c0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*08d0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*08e0*/ BRA 0x940 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0900*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000a */
/*0910*/ BRA 0x940 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0930*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff68004007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*#include "device_atomic_functions.h"
__global__
void inner_product1_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N_ln*N_ln; i++)
if (i < N_ln*N_ln)
temp[threadIdx.x] = a[i] * b[i];
__syncthreads();
//parallel reduction
//for (int j = threadIdx.x; j < N_ln*N_ln ; j += blockDim.x)
return;
}
__global__
void inner_product2_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j]
return;
}
*/
__global__
void laplacian_GPU(double *La, double *x, double dx, double dy, int N, int N_ln)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < N_ln && j < N_ln)
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) / (dx * dy);
return;
}
__global__
void YPEAX_GPU(double *y, double *x, double a, int N) // Y += a*X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N * N; i++)
if (i< N*N)
y[i] += a * x[i];
return;
}
__global__
void YEAYPX_GPU(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
return;
}
double inner_product(double *a, double *b, int type, int N, int N_ln)
{
double kk = 0.0;
int i, j;
if (type == 0)
{ // for N_ln^2 * N_ln^2
for ( i = 0; i < N_ln * N_ln; i++)
{
kk += a[i] * b[i];
}
}
else
{ // for N^2 * N_ln^2
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j];
}
}
}
return kk;
}
void laplacian(double *La, double *x, double dx, double dy, int N, int N_ln)
{
int i, j;
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) /
(dx * dy);
}
}
return;
}
void YEAYPX(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
// const int i = blockIdx.x*blockDim.x + threadIdx.x;
// const int j = blockIdx.y*blockDim.y + threadIdx.y;
int i,j;
for ( i = 0; i < N_ln; i++)
for ( j = 0; j < N_ln; j++)
{
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
}
return;
} | .file "tmpxft_00166577_00000000-6_operator.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13inner_productPdS_iii
.type _Z13inner_productPdS_iii, @function
_Z13inner_productPdS_iii:
.LFB2027:
.cfi_startproc
endbr64
movq %rdi, %rax
testl %edx, %edx
je .L4
testl %r8d, %r8d
jle .L9
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r9
leaq (%rdi,%r9), %rcx
movslq %r8d, %rdi
salq $3, %rdi
movq %rsi, %rdx
movl $0, %esi
pxor %xmm1, %xmm1
.L6:
movl $0, %eax
.L8:
movsd 8(%rcx,%rax), %xmm0
mulsd (%rdx,%rax), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rdi, %rax
jne .L8
addl $1, %esi
addq %r9, %rcx
addq %rdi, %rdx
cmpl %esi, %r8d
jne .L6
jmp .L3
.L4:
imull %r8d, %r8d
testl %r8d, %r8d
jle .L10
movslq %r8d, %r8
leaq 0(,%r8,8), %rcx
movl $0, %edx
pxor %xmm1, %xmm1
.L7:
movsd (%rax,%rdx), %xmm0
mulsd (%rsi,%rdx), %xmm0
addsd %xmm0, %xmm1
addq $8, %rdx
cmpq %rdx, %rcx
jne .L7
.L3:
movapd %xmm1, %xmm0
ret
.L9:
pxor %xmm1, %xmm1
jmp .L3
.L10:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z13inner_productPdS_iii, .-_Z13inner_productPdS_iii
.globl _Z9laplacianPdS_ddii
.type _Z9laplacianPdS_ddii, @function
_Z9laplacianPdS_ddii:
.LFB2028:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L19
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rax
movl %ecx, %r11d
mulsd %xmm1, %xmm0
movslq %edx, %r10
salq $3, %r10
movq %rsi, %r9
addl %edx, %edx
movslq %edx, %rdx
leaq (%rsi,%rdx,8), %rsi
movslq %ecx, %rdi
salq $3, %rdi
movq %rax, %rcx
movl $0, %ebx
movsd .LC1(%rip), %xmm3
.L15:
movq %r9, %r8
addq %r10, %r9
movq %r9, %rdx
movl $0, %eax
.L16:
movsd 8(%r8,%rax), %xmm1
addsd 8(%rsi,%rax), %xmm1
addsd (%rdx), %xmm1
addsd 16(%rdx), %xmm1
movapd %xmm3, %xmm2
mulsd 8(%rdx), %xmm2
subsd %xmm2, %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%rcx,%rax)
addq $8, %rdx
addq $8, %rax
cmpq %rdi, %rax
jne .L16
addl $1, %ebx
addq %r10, %rsi
addq %rdi, %rcx
cmpl %ebx, %r11d
jne .L15
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
ret
.cfi_endproc
.LFE2028:
.size _Z9laplacianPdS_ddii, .-_Z9laplacianPdS_ddii
.globl _Z6YEAYPXPdS_dii
.type _Z6YEAYPXPdS_dii, @function
_Z6YEAYPXPdS_dii:
.LFB2029:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L22
movslq %edx, %rdx
leaq 0(,%rdx,8), %r9
leaq (%rdi,%r9), %rdx
movslq %ecx, %rdi
salq $3, %rdi
movl $0, %r8d
.L24:
movl $0, %eax
.L25:
movapd %xmm0, %xmm1
mulsd 8(%rdx,%rax), %xmm1
addsd (%rsi,%rax), %xmm1
movsd %xmm1, 8(%rdx,%rax)
addq $8, %rax
cmpq %rdi, %rax
jne .L25
addl $1, %r8d
addq %r9, %rdx
addq %rdi, %rsi
cmpl %r8d, %ecx
jne .L24
.L22:
ret
.cfi_endproc
.LFE2029:
.size _Z6YEAYPXPdS_dii, .-_Z6YEAYPXPdS_dii
.globl _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii
.type _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii, @function
_Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13laplacian_GPUPdS_ddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii, .-_Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii
.globl _Z13laplacian_GPUPdS_ddii
.type _Z13laplacian_GPUPdS_ddii, @function
_Z13laplacian_GPUPdS_ddii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z13laplacian_GPUPdS_ddii, .-_Z13laplacian_GPUPdS_ddii
.globl _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di
.type _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di, @function
_Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di:
.LFB2056:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9YPEAX_GPUPdS_di(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di, .-_Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di
.globl _Z9YPEAX_GPUPdS_di
.type _Z9YPEAX_GPUPdS_di, @function
_Z9YPEAX_GPUPdS_di:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9YPEAX_GPUPdS_di, .-_Z9YPEAX_GPUPdS_di
.globl _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii
.type _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii, @function
_Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10YEAYPX_GPUPdS_dii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii, .-_Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii
.globl _Z10YEAYPX_GPUPdS_dii
.type _Z10YEAYPX_GPUPdS_dii, @function
_Z10YEAYPX_GPUPdS_dii:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10YEAYPX_GPUPdS_dii, .-_Z10YEAYPX_GPUPdS_dii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z10YEAYPX_GPUPdS_dii"
.LC3:
.string "_Z9YPEAX_GPUPdS_di"
.LC4:
.string "_Z13laplacian_GPUPdS_ddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10YEAYPX_GPUPdS_dii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9YPEAX_GPUPdS_di(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13laplacian_GPUPdS_ddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*#include "device_atomic_functions.h"
__global__
void inner_product1_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N_ln*N_ln; i++)
if (i < N_ln*N_ln)
temp[threadIdx.x] = a[i] * b[i];
__syncthreads();
//parallel reduction
//for (int j = threadIdx.x; j < N_ln*N_ln ; j += blockDim.x)
return;
}
__global__
void inner_product2_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j]
return;
}
*/
__global__
void laplacian_GPU(double *La, double *x, double dx, double dy, int N, int N_ln)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < N_ln && j < N_ln)
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) / (dx * dy);
return;
}
__global__
void YPEAX_GPU(double *y, double *x, double a, int N) // Y += a*X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N * N; i++)
if (i< N*N)
y[i] += a * x[i];
return;
}
__global__
void YEAYPX_GPU(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
return;
}
double inner_product(double *a, double *b, int type, int N, int N_ln)
{
double kk = 0.0;
int i, j;
if (type == 0)
{ // for N_ln^2 * N_ln^2
for ( i = 0; i < N_ln * N_ln; i++)
{
kk += a[i] * b[i];
}
}
else
{ // for N^2 * N_ln^2
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j];
}
}
}
return kk;
}
void laplacian(double *La, double *x, double dx, double dy, int N, int N_ln)
{
int i, j;
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) /
(dx * dy);
}
}
return;
}
void YEAYPX(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
// const int i = blockIdx.x*blockDim.x + threadIdx.x;
// const int j = blockIdx.y*blockDim.y + threadIdx.y;
int i,j;
for ( i = 0; i < N_ln; i++)
for ( j = 0; j < N_ln; j++)
{
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
}
return;
} | #include <hip/hip_runtime.h>
/*#include "device_atomic_functions.h"
__global__
void inner_product1_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N_ln*N_ln; i++)
if (i < N_ln*N_ln)
temp[threadIdx.x] = a[i] * b[i];
__syncthreads();
//parallel reduction
//for (int j = threadIdx.x; j < N_ln*N_ln ; j += blockDim.x)
return;
}
__global__
void inner_product2_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j]
return;
}
*/
__global__
void laplacian_GPU(double *La, double *x, double dx, double dy, int N, int N_ln)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < N_ln && j < N_ln)
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) / (dx * dy);
return;
}
__global__
void YPEAX_GPU(double *y, double *x, double a, int N) // Y += a*X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N * N; i++)
if (i< N*N)
y[i] += a * x[i];
return;
}
__global__
void YEAYPX_GPU(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
return;
}
double inner_product(double *a, double *b, int type, int N, int N_ln)
{
double kk = 0.0;
int i, j;
if (type == 0)
{ // for N_ln^2 * N_ln^2
for ( i = 0; i < N_ln * N_ln; i++)
{
kk += a[i] * b[i];
}
}
else
{ // for N^2 * N_ln^2
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j];
}
}
}
return kk;
}
void laplacian(double *La, double *x, double dx, double dy, int N, int N_ln)
{
int i, j;
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) /
(dx * dy);
}
}
return;
}
void YEAYPX(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
// const int i = blockIdx.x*blockDim.x + threadIdx.x;
// const int j = blockIdx.y*blockDim.y + threadIdx.y;
int i,j;
for ( i = 0; i < N_ln; i++)
for ( j = 0; j < N_ln; j++)
{
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*#include "device_atomic_functions.h"
__global__
void inner_product1_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N_ln*N_ln; i++)
if (i < N_ln*N_ln)
temp[threadIdx.x] = a[i] * b[i];
__syncthreads();
//parallel reduction
//for (int j = threadIdx.x; j < N_ln*N_ln ; j += blockDim.x)
return;
}
__global__
void inner_product2_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j]
return;
}
*/
__global__
void laplacian_GPU(double *La, double *x, double dx, double dy, int N, int N_ln)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < N_ln && j < N_ln)
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) / (dx * dy);
return;
}
__global__
void YPEAX_GPU(double *y, double *x, double a, int N) // Y += a*X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N * N; i++)
if (i< N*N)
y[i] += a * x[i];
return;
}
__global__
void YEAYPX_GPU(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
return;
}
double inner_product(double *a, double *b, int type, int N, int N_ln)
{
double kk = 0.0;
int i, j;
if (type == 0)
{ // for N_ln^2 * N_ln^2
for ( i = 0; i < N_ln * N_ln; i++)
{
kk += a[i] * b[i];
}
}
else
{ // for N^2 * N_ln^2
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j];
}
}
}
return kk;
}
void laplacian(double *La, double *x, double dx, double dy, int N, int N_ln)
{
int i, j;
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) /
(dx * dy);
}
}
return;
}
void YEAYPX(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
// const int i = blockIdx.x*blockDim.x + threadIdx.x;
// const int j = blockIdx.y*blockDim.y + threadIdx.y;
int i,j;
for ( i = 0; i < N_ln; i++)
for ( j = 0; j < N_ln; j++)
{
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13laplacian_GPUPdS_ddii
.globl _Z13laplacian_GPUPdS_ddii
.p2align 8
.type _Z13laplacian_GPUPdS_ddii,@function
_Z13laplacian_GPUPdS_ddii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB0_2
s_load_b32 s9, s[0:1], 0x20
v_add_nc_u32_e32 v2, 1, v1
v_add_nc_u32_e32 v4, 2, v0
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v7, v0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v2, v7
v_add_nc_u32_e32 v12, s9, v7
v_mad_u64_u32 v[5:6], null, v4, s9, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, v12, v1
v_add_nc_u32_e32 v12, v12, v2
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v10, 2, v7
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_u32 v3, vcc_lo, s2, v3
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_lshlrev_b64 v[8:9], 3, v[7:8]
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_lshlrev_b64 v[10:11], 3, v[10:11]
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[3:4], v[5:6]
v_mul_f64 v[4:5], s[4:5], s[6:7]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[10:11]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[12:13], -4.0, v[2:3]
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s8, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13laplacian_GPUPdS_ddii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13laplacian_GPUPdS_ddii, .Lfunc_end0-_Z13laplacian_GPUPdS_ddii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9YPEAX_GPUPdS_di
.globl _Z9YPEAX_GPUPdS_di
.p2align 8
.type _Z9YPEAX_GPUPdS_di,@function
_Z9YPEAX_GPUPdS_di:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s3, s3
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9YPEAX_GPUPdS_di
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9YPEAX_GPUPdS_di, .Lfunc_end1-_Z9YPEAX_GPUPdS_di
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10YEAYPX_GPUPdS_dii
.globl _Z10YEAYPX_GPUPdS_dii
.p2align 8
.type _Z10YEAYPX_GPUPdS_dii,@function
_Z10YEAYPX_GPUPdS_dii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB2_2
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s4, v0, s[4:5]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v1, v2, 1
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[4:5], v[0:1], off
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], s[0:1], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10YEAYPX_GPUPdS_dii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10YEAYPX_GPUPdS_dii, .Lfunc_end2-_Z10YEAYPX_GPUPdS_dii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13laplacian_GPUPdS_ddii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13laplacian_GPUPdS_ddii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9YPEAX_GPUPdS_di
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9YPEAX_GPUPdS_di.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10YEAYPX_GPUPdS_dii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10YEAYPX_GPUPdS_dii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*#include "device_atomic_functions.h"
__global__
void inner_product1_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N_ln*N_ln; i++)
if (i < N_ln*N_ln)
temp[threadIdx.x] = a[i] * b[i];
__syncthreads();
//parallel reduction
//for (int j = threadIdx.x; j < N_ln*N_ln ; j += blockDim.x)
return;
}
__global__
void inner_product2_GPU(double kk, double *a, double *b, int N, int N_ln)
{
kk = 0.0;
__shared__ double temp[128];
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j]
return;
}
*/
__global__
void laplacian_GPU(double *La, double *x, double dx, double dy, int N, int N_ln)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < N_ln && j < N_ln)
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) / (dx * dy);
return;
}
__global__
void YPEAX_GPU(double *y, double *x, double a, int N) // Y += a*X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
//for ( i = 0; i < N * N; i++)
if (i< N*N)
y[i] += a * x[i];
return;
}
__global__
void YEAYPX_GPU(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const int j = blockIdx.y*blockDim.y + threadIdx.y;
//for ( i = 0; i < N_ln; i++)
//for ( j = 0; j < N_ln; j++)
if (i < N_ln && j < N_ln)
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
return;
}
double inner_product(double *a, double *b, int type, int N, int N_ln)
{
double kk = 0.0;
int i, j;
if (type == 0)
{ // for N_ln^2 * N_ln^2
for ( i = 0; i < N_ln * N_ln; i++)
{
kk += a[i] * b[i];
}
}
else
{ // for N^2 * N_ln^2
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
kk += a[N * (i + 1) + (j + 1)] * b[N_ln * i + j];
}
}
}
return kk;
}
void laplacian(double *La, double *x, double dx, double dy, int N, int N_ln)
{
int i, j;
for ( i = 0; i < N_ln; i++)
{
for ( j = 0; j < N_ln; j++)
{
La[N_ln * i + j] = (x[N * i + (j + 1)] + x[N * (i + 2) + (j + 1)] + x[N * (i + 1) + j] +
x[N * (i + 1) + (j + 2)] - 4.0 * x[N * (i + 1) + (j + 1)]) /
(dx * dy);
}
}
return;
}
void YEAYPX(double *y, double *x, double a, int N, int N_ln) // Y = a*Y + X
{
// const int i = blockIdx.x*blockDim.x + threadIdx.x;
// const int j = blockIdx.y*blockDim.y + threadIdx.y;
int i,j;
for ( i = 0; i < N_ln; i++)
for ( j = 0; j < N_ln; j++)
{
y[N * (i + 1) + (j + 1)] = a * y[N * (i + 1) + (j + 1)] + x[N_ln * i + j];
}
return;
} | .text
.file "operator.hip"
.globl _Z28__device_stub__laplacian_GPUPdS_ddii # -- Begin function _Z28__device_stub__laplacian_GPUPdS_ddii
.p2align 4, 0x90
.type _Z28__device_stub__laplacian_GPUPdS_ddii,@function
_Z28__device_stub__laplacian_GPUPdS_ddii: # @_Z28__device_stub__laplacian_GPUPdS_ddii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13laplacian_GPUPdS_ddii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__laplacian_GPUPdS_ddii, .Lfunc_end0-_Z28__device_stub__laplacian_GPUPdS_ddii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__YPEAX_GPUPdS_di # -- Begin function _Z24__device_stub__YPEAX_GPUPdS_di
.p2align 4, 0x90
.type _Z24__device_stub__YPEAX_GPUPdS_di,@function
_Z24__device_stub__YPEAX_GPUPdS_di: # @_Z24__device_stub__YPEAX_GPUPdS_di
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9YPEAX_GPUPdS_di, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__YPEAX_GPUPdS_di, .Lfunc_end1-_Z24__device_stub__YPEAX_GPUPdS_di
.cfi_endproc
# -- End function
.globl _Z25__device_stub__YEAYPX_GPUPdS_dii # -- Begin function _Z25__device_stub__YEAYPX_GPUPdS_dii
.p2align 4, 0x90
.type _Z25__device_stub__YEAYPX_GPUPdS_dii,@function
_Z25__device_stub__YEAYPX_GPUPdS_dii: # @_Z25__device_stub__YEAYPX_GPUPdS_dii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10YEAYPX_GPUPdS_dii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__YEAYPX_GPUPdS_dii, .Lfunc_end2-_Z25__device_stub__YEAYPX_GPUPdS_dii
.cfi_endproc
# -- End function
.globl _Z13inner_productPdS_iii # -- Begin function _Z13inner_productPdS_iii
.p2align 4, 0x90
.type _Z13inner_productPdS_iii,@function
_Z13inner_productPdS_iii: # @_Z13inner_productPdS_iii
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
testl %edx, %edx
je .LBB3_6
# %bb.1: # %.preheader30
testl %r8d, %r8d
jle .LBB3_11
# %bb.2: # %.preheader29.lr.ph
movslq %ecx, %rax
movl %r8d, %ecx
leaq (,%rcx,8), %rdx
leaq (%rdi,%rax,8), %rdi
addq $8, %rdi
shlq $3, %rax
xorpd %xmm0, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_3: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rsi,%r9,8), %xmm1
leaq 1(%r9), %r10
addsd %xmm1, %xmm0
movq %r10, %r9
cmpq %r10, %rcx
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incq %r8
addq %rdx, %rsi
addq %rax, %rdi
cmpq %rcx, %r8
jne .LBB3_3
jmp .LBB3_9
.LBB3_6: # %.preheader
testl %r8d, %r8d
je .LBB3_11
# %bb.7: # %.lr.ph39.preheader
imull %r8d, %r8d
cmpl $1, %r8d
adcl $0, %r8d
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_8: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rsi,%rax,8), %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq %rax, %r8
jne .LBB3_8
.LBB3_9: # %.loopexit
retq
.LBB3_11:
xorps %xmm0, %xmm0
retq
.Lfunc_end3:
.size _Z13inner_productPdS_iii, .Lfunc_end3-_Z13inner_productPdS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9laplacianPdS_ddii
.LCPI4_0:
.quad 0xc010000000000000 # double -4
.text
.globl _Z9laplacianPdS_ddii
.p2align 4, 0x90
.type _Z9laplacianPdS_ddii,@function
_Z9laplacianPdS_ddii: # @_Z9laplacianPdS_ddii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
mulsd %xmm1, %xmm0
movslq %edx, %r11
movl %ecx, %eax
leaq (,%rax,8), %rcx
leaq (,%r11,8), %rdx
leaq (%rsi,%r11,8), %r8
addq $8, %r8
movq %r11, %r9
shlq $32, %r9
movabsq $8589934592, %r10 # imm = 0x200000000
addq %r9, %r10
shlq $4, %r11
addq %rsi, %r11
addq $8, %r11
leaq 8(%rsi), %rbx
xorl %r14d, %r14d
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
movabsq $4294967296, %r15 # imm = 0x100000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %r10, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r13), %xmm2 # xmm2 = mem[0],zero
addsd (%r11,%r13), %xmm2
addsd -8(%r8,%r13), %xmm2
movq %r12, %rbp
sarq $29, %rbp
addsd (%rsi,%rbp), %xmm2
movsd (%r8,%r13), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm1, %xmm3
addsd %xmm2, %xmm3
divsd %xmm0, %xmm3
movsd %xmm3, (%rdi,%r13)
addq $8, %r13
addq %r15, %r12
cmpq %r13, %rcx
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r14
addq %rcx, %rdi
addq %rdx, %r8
addq %r9, %r10
addq %rdx, %r11
addq %rdx, %rbx
cmpq %rax, %r14
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge35
retq
.Lfunc_end4:
.size _Z9laplacianPdS_ddii, .Lfunc_end4-_Z9laplacianPdS_ddii
.cfi_endproc
# -- End function
.globl _Z6YEAYPXPdS_dii # -- Begin function _Z6YEAYPXPdS_dii
.p2align 4, 0x90
.type _Z6YEAYPXPdS_dii,@function
_Z6YEAYPXPdS_dii: # @_Z6YEAYPXPdS_dii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB5_5
# %bb.1: # %.preheader.lr.ph
movslq %edx, %rax
movl %ecx, %ecx
leaq (,%rcx,8), %rdx
leaq (%rdi,%rax,8), %rdi
addq $8, %rdi
shlq $3, %rax
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%rsi,%r9,8), %xmm1
movsd %xmm1, (%rdi,%r9,8)
leaq 1(%r9), %r10
movq %r10, %r9
cmpq %r10, %rcx
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r8
addq %rdx, %rsi
addq %rax, %rdi
cmpq %rcx, %r8
jne .LBB5_2
.LBB5_5: # %._crit_edge22
retq
.Lfunc_end5:
.size _Z6YEAYPXPdS_dii, .Lfunc_end5-_Z6YEAYPXPdS_dii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13laplacian_GPUPdS_ddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9YPEAX_GPUPdS_di, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10YEAYPX_GPUPdS_dii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13laplacian_GPUPdS_ddii,@object # @_Z13laplacian_GPUPdS_ddii
.section .rodata,"a",@progbits
.globl _Z13laplacian_GPUPdS_ddii
.p2align 3, 0x0
_Z13laplacian_GPUPdS_ddii:
.quad _Z28__device_stub__laplacian_GPUPdS_ddii
.size _Z13laplacian_GPUPdS_ddii, 8
.type _Z9YPEAX_GPUPdS_di,@object # @_Z9YPEAX_GPUPdS_di
.globl _Z9YPEAX_GPUPdS_di
.p2align 3, 0x0
_Z9YPEAX_GPUPdS_di:
.quad _Z24__device_stub__YPEAX_GPUPdS_di
.size _Z9YPEAX_GPUPdS_di, 8
.type _Z10YEAYPX_GPUPdS_dii,@object # @_Z10YEAYPX_GPUPdS_dii
.globl _Z10YEAYPX_GPUPdS_dii
.p2align 3, 0x0
_Z10YEAYPX_GPUPdS_dii:
.quad _Z25__device_stub__YEAYPX_GPUPdS_dii
.size _Z10YEAYPX_GPUPdS_dii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13laplacian_GPUPdS_ddii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9YPEAX_GPUPdS_di"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10YEAYPX_GPUPdS_dii"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__laplacian_GPUPdS_ddii
.addrsig_sym _Z24__device_stub__YPEAX_GPUPdS_di
.addrsig_sym _Z25__device_stub__YEAYPX_GPUPdS_dii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13laplacian_GPUPdS_ddii
.addrsig_sym _Z9YPEAX_GPUPdS_di
.addrsig_sym _Z10YEAYPX_GPUPdS_dii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00166577_00000000-6_operator.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13inner_productPdS_iii
.type _Z13inner_productPdS_iii, @function
_Z13inner_productPdS_iii:
.LFB2027:
.cfi_startproc
endbr64
movq %rdi, %rax
testl %edx, %edx
je .L4
testl %r8d, %r8d
jle .L9
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r9
leaq (%rdi,%r9), %rcx
movslq %r8d, %rdi
salq $3, %rdi
movq %rsi, %rdx
movl $0, %esi
pxor %xmm1, %xmm1
.L6:
movl $0, %eax
.L8:
movsd 8(%rcx,%rax), %xmm0
mulsd (%rdx,%rax), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rdi, %rax
jne .L8
addl $1, %esi
addq %r9, %rcx
addq %rdi, %rdx
cmpl %esi, %r8d
jne .L6
jmp .L3
.L4:
imull %r8d, %r8d
testl %r8d, %r8d
jle .L10
movslq %r8d, %r8
leaq 0(,%r8,8), %rcx
movl $0, %edx
pxor %xmm1, %xmm1
.L7:
movsd (%rax,%rdx), %xmm0
mulsd (%rsi,%rdx), %xmm0
addsd %xmm0, %xmm1
addq $8, %rdx
cmpq %rdx, %rcx
jne .L7
.L3:
movapd %xmm1, %xmm0
ret
.L9:
pxor %xmm1, %xmm1
jmp .L3
.L10:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z13inner_productPdS_iii, .-_Z13inner_productPdS_iii
.globl _Z9laplacianPdS_ddii
.type _Z9laplacianPdS_ddii, @function
_Z9laplacianPdS_ddii:
.LFB2028:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L19
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rax
movl %ecx, %r11d
mulsd %xmm1, %xmm0
movslq %edx, %r10
salq $3, %r10
movq %rsi, %r9
addl %edx, %edx
movslq %edx, %rdx
leaq (%rsi,%rdx,8), %rsi
movslq %ecx, %rdi
salq $3, %rdi
movq %rax, %rcx
movl $0, %ebx
movsd .LC1(%rip), %xmm3
.L15:
movq %r9, %r8
addq %r10, %r9
movq %r9, %rdx
movl $0, %eax
.L16:
movsd 8(%r8,%rax), %xmm1
addsd 8(%rsi,%rax), %xmm1
addsd (%rdx), %xmm1
addsd 16(%rdx), %xmm1
movapd %xmm3, %xmm2
mulsd 8(%rdx), %xmm2
subsd %xmm2, %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%rcx,%rax)
addq $8, %rdx
addq $8, %rax
cmpq %rdi, %rax
jne .L16
addl $1, %ebx
addq %r10, %rsi
addq %rdi, %rcx
cmpl %ebx, %r11d
jne .L15
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
ret
.cfi_endproc
.LFE2028:
.size _Z9laplacianPdS_ddii, .-_Z9laplacianPdS_ddii
.globl _Z6YEAYPXPdS_dii
.type _Z6YEAYPXPdS_dii, @function
_Z6YEAYPXPdS_dii:
.LFB2029:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L22
movslq %edx, %rdx
leaq 0(,%rdx,8), %r9
leaq (%rdi,%r9), %rdx
movslq %ecx, %rdi
salq $3, %rdi
movl $0, %r8d
.L24:
movl $0, %eax
.L25:
movapd %xmm0, %xmm1
mulsd 8(%rdx,%rax), %xmm1
addsd (%rsi,%rax), %xmm1
movsd %xmm1, 8(%rdx,%rax)
addq $8, %rax
cmpq %rdi, %rax
jne .L25
addl $1, %r8d
addq %r9, %rdx
addq %rdi, %rsi
cmpl %r8d, %ecx
jne .L24
.L22:
ret
.cfi_endproc
.LFE2029:
.size _Z6YEAYPXPdS_dii, .-_Z6YEAYPXPdS_dii
.globl _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii
.type _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii, @function
_Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13laplacian_GPUPdS_ddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii, .-_Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii
.globl _Z13laplacian_GPUPdS_ddii
.type _Z13laplacian_GPUPdS_ddii, @function
_Z13laplacian_GPUPdS_ddii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13laplacian_GPUPdS_ddiiPdS_ddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z13laplacian_GPUPdS_ddii, .-_Z13laplacian_GPUPdS_ddii
.globl _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di
.type _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di, @function
_Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di:
.LFB2056:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9YPEAX_GPUPdS_di(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di, .-_Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di
.globl _Z9YPEAX_GPUPdS_di
.type _Z9YPEAX_GPUPdS_di, @function
_Z9YPEAX_GPUPdS_di:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9YPEAX_GPUPdS_diPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9YPEAX_GPUPdS_di, .-_Z9YPEAX_GPUPdS_di
.globl _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii
.type _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii, @function
_Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10YEAYPX_GPUPdS_dii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii, .-_Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii
.globl _Z10YEAYPX_GPUPdS_dii
.type _Z10YEAYPX_GPUPdS_dii, @function
_Z10YEAYPX_GPUPdS_dii:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10YEAYPX_GPUPdS_diiPdS_dii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10YEAYPX_GPUPdS_dii, .-_Z10YEAYPX_GPUPdS_dii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z10YEAYPX_GPUPdS_dii"
.LC3:
.string "_Z9YPEAX_GPUPdS_di"
.LC4:
.string "_Z13laplacian_GPUPdS_ddii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10YEAYPX_GPUPdS_dii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9YPEAX_GPUPdS_di(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13laplacian_GPUPdS_ddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "operator.hip"
.globl _Z28__device_stub__laplacian_GPUPdS_ddii # -- Begin function _Z28__device_stub__laplacian_GPUPdS_ddii
.p2align 4, 0x90
.type _Z28__device_stub__laplacian_GPUPdS_ddii,@function
_Z28__device_stub__laplacian_GPUPdS_ddii: # @_Z28__device_stub__laplacian_GPUPdS_ddii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13laplacian_GPUPdS_ddii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__laplacian_GPUPdS_ddii, .Lfunc_end0-_Z28__device_stub__laplacian_GPUPdS_ddii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__YPEAX_GPUPdS_di # -- Begin function _Z24__device_stub__YPEAX_GPUPdS_di
.p2align 4, 0x90
.type _Z24__device_stub__YPEAX_GPUPdS_di,@function
_Z24__device_stub__YPEAX_GPUPdS_di: # @_Z24__device_stub__YPEAX_GPUPdS_di
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9YPEAX_GPUPdS_di, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__YPEAX_GPUPdS_di, .Lfunc_end1-_Z24__device_stub__YPEAX_GPUPdS_di
.cfi_endproc
# -- End function
.globl _Z25__device_stub__YEAYPX_GPUPdS_dii # -- Begin function _Z25__device_stub__YEAYPX_GPUPdS_dii
.p2align 4, 0x90
.type _Z25__device_stub__YEAYPX_GPUPdS_dii,@function
_Z25__device_stub__YEAYPX_GPUPdS_dii: # @_Z25__device_stub__YEAYPX_GPUPdS_dii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10YEAYPX_GPUPdS_dii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__YEAYPX_GPUPdS_dii, .Lfunc_end2-_Z25__device_stub__YEAYPX_GPUPdS_dii
.cfi_endproc
# -- End function
.globl _Z13inner_productPdS_iii # -- Begin function _Z13inner_productPdS_iii
.p2align 4, 0x90
.type _Z13inner_productPdS_iii,@function
_Z13inner_productPdS_iii: # @_Z13inner_productPdS_iii
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
testl %edx, %edx
je .LBB3_6
# %bb.1: # %.preheader30
testl %r8d, %r8d
jle .LBB3_11
# %bb.2: # %.preheader29.lr.ph
movslq %ecx, %rax
movl %r8d, %ecx
leaq (,%rcx,8), %rdx
leaq (%rdi,%rax,8), %rdi
addq $8, %rdi
shlq $3, %rax
xorpd %xmm0, %xmm0
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_3: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rsi,%r9,8), %xmm1
leaq 1(%r9), %r10
addsd %xmm1, %xmm0
movq %r10, %r9
cmpq %r10, %rcx
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incq %r8
addq %rdx, %rsi
addq %rax, %rdi
cmpq %rcx, %r8
jne .LBB3_3
jmp .LBB3_9
.LBB3_6: # %.preheader
testl %r8d, %r8d
je .LBB3_11
# %bb.7: # %.lr.ph39.preheader
imull %r8d, %r8d
cmpl $1, %r8d
adcl $0, %r8d
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_8: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rsi,%rax,8), %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq %rax, %r8
jne .LBB3_8
.LBB3_9: # %.loopexit
retq
.LBB3_11:
xorps %xmm0, %xmm0
retq
.Lfunc_end3:
.size _Z13inner_productPdS_iii, .Lfunc_end3-_Z13inner_productPdS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9laplacianPdS_ddii
.LCPI4_0:
.quad 0xc010000000000000 # double -4
.text
.globl _Z9laplacianPdS_ddii
.p2align 4, 0x90
.type _Z9laplacianPdS_ddii,@function
_Z9laplacianPdS_ddii: # @_Z9laplacianPdS_ddii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
mulsd %xmm1, %xmm0
movslq %edx, %r11
movl %ecx, %eax
leaq (,%rax,8), %rcx
leaq (,%r11,8), %rdx
leaq (%rsi,%r11,8), %r8
addq $8, %r8
movq %r11, %r9
shlq $32, %r9
movabsq $8589934592, %r10 # imm = 0x200000000
addq %r9, %r10
shlq $4, %r11
addq %rsi, %r11
addq $8, %r11
leaq 8(%rsi), %rbx
xorl %r14d, %r14d
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
movabsq $4294967296, %r15 # imm = 0x100000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %r10, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r13), %xmm2 # xmm2 = mem[0],zero
addsd (%r11,%r13), %xmm2
addsd -8(%r8,%r13), %xmm2
movq %r12, %rbp
sarq $29, %rbp
addsd (%rsi,%rbp), %xmm2
movsd (%r8,%r13), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm1, %xmm3
addsd %xmm2, %xmm3
divsd %xmm0, %xmm3
movsd %xmm3, (%rdi,%r13)
addq $8, %r13
addq %r15, %r12
cmpq %r13, %rcx
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r14
addq %rcx, %rdi
addq %rdx, %r8
addq %r9, %r10
addq %rdx, %r11
addq %rdx, %rbx
cmpq %rax, %r14
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge35
retq
.Lfunc_end4:
.size _Z9laplacianPdS_ddii, .Lfunc_end4-_Z9laplacianPdS_ddii
.cfi_endproc
# -- End function
.globl _Z6YEAYPXPdS_dii # -- Begin function _Z6YEAYPXPdS_dii
.p2align 4, 0x90
.type _Z6YEAYPXPdS_dii,@function
_Z6YEAYPXPdS_dii: # @_Z6YEAYPXPdS_dii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB5_5
# %bb.1: # %.preheader.lr.ph
movslq %edx, %rax
movl %ecx, %ecx
leaq (,%rcx,8), %rdx
leaq (%rdi,%rax,8), %rdi
addq $8, %rdi
shlq $3, %rax
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%rsi,%r9,8), %xmm1
movsd %xmm1, (%rdi,%r9,8)
leaq 1(%r9), %r10
movq %r10, %r9
cmpq %r10, %rcx
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r8
addq %rdx, %rsi
addq %rax, %rdi
cmpq %rcx, %r8
jne .LBB5_2
.LBB5_5: # %._crit_edge22
retq
.Lfunc_end5:
.size _Z6YEAYPXPdS_dii, .Lfunc_end5-_Z6YEAYPXPdS_dii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13laplacian_GPUPdS_ddii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9YPEAX_GPUPdS_di, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10YEAYPX_GPUPdS_dii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13laplacian_GPUPdS_ddii,@object # @_Z13laplacian_GPUPdS_ddii
.section .rodata,"a",@progbits
.globl _Z13laplacian_GPUPdS_ddii
.p2align 3, 0x0
_Z13laplacian_GPUPdS_ddii:
.quad _Z28__device_stub__laplacian_GPUPdS_ddii
.size _Z13laplacian_GPUPdS_ddii, 8
.type _Z9YPEAX_GPUPdS_di,@object # @_Z9YPEAX_GPUPdS_di
.globl _Z9YPEAX_GPUPdS_di
.p2align 3, 0x0
_Z9YPEAX_GPUPdS_di:
.quad _Z24__device_stub__YPEAX_GPUPdS_di
.size _Z9YPEAX_GPUPdS_di, 8
.type _Z10YEAYPX_GPUPdS_dii,@object # @_Z10YEAYPX_GPUPdS_dii
.globl _Z10YEAYPX_GPUPdS_dii
.p2align 3, 0x0
_Z10YEAYPX_GPUPdS_dii:
.quad _Z25__device_stub__YEAYPX_GPUPdS_dii
.size _Z10YEAYPX_GPUPdS_dii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13laplacian_GPUPdS_ddii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9YPEAX_GPUPdS_di"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10YEAYPX_GPUPdS_dii"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__laplacian_GPUPdS_ddii
.addrsig_sym _Z24__device_stub__YPEAX_GPUPdS_di
.addrsig_sym _Z25__device_stub__YEAYPX_GPUPdS_dii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13laplacian_GPUPdS_ddii
.addrsig_sym _Z9YPEAX_GPUPdS_di
.addrsig_sym _Z10YEAYPX_GPUPdS_dii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <stdio.h>
//#include <stdlib.h>
//#include <time.h>
//
//#include "common.h"
//#include "cuda_common.cuh"
//
//#include "cuda.h"
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#define c0 1
//#define c1 2
//#define c2 3
//#define c3 4
//#define c4 5
//
//#define RADIUS 4
//
//#define BDIM 128
//
////constant memory declaration
//__constant__ int coef[9];
//
//void host_const_calculation(int * in, int * out, int size)
//{
// for (int i = 0; i < size; i++)
// {
//
// if (i < RADIUS)
// {
// out[i] = in[i + 4] * c0
// + in[i + 3] * c1
// + in[i + 2] * c2
// + in[i + 1] * c3
// + in[i] * c4;
//
// if (i == 3)
// {
// out[i] += in[2] * c3;
// out[i] += in[1] * c2;
// out[i] += in[0] * c1;
// }
// else if (i == 2)
// {
// out[i] += in[1] * c3;
// out[i] += in[0] * c2;
// }
// else if (i == 1)
// {
// out[i] += in[0] * c3;
// }
// }
// else if ((i + RADIUS) >= size)
// {
// out[i] = in[i - 4] * c0
// + in[i - 3] * c1
// + in[i - 2] * c2
// + in[i - 1] * c3
// + in[i] * c4;
//
// if (i == size - 4)
// {
// out[i] += in[size - 3] * c3;
// out[i] += in[size - 2] * c2;
// out[i] += in[size - 1] * c1;
// }
// else if (i == size - 3)
// {
// out[i] += in[size - 2] * c3;
// out[i] += in[size - 1] * c2;
// }
// else if (i == size - 2)
// {
// out[i] += in[size - 1] * c3;
// }
// }
// else
// {
// out[i] = (in[i - 4] + in[i + 4])*c0
// + (in[i - 3] + in[i + 3])*c1
// + (in[i - 2] + in[i + 2])*c2
// + (in[i - 1] + in[i + 1])*c3
// + in[i] * c4;
// }
// }
//}
//
////setting up constant memory from host
//void setup_coef_1()
//{
// const int h_coef[] = { c0,c1,c2,c3,c4,c3,c2,c1,c0 };
// cudaMemcpyToSymbol(coef, h_coef, (9) * sizeof(float));
//}
//
//__global__ void constant_stencil_smem_test(int * in,
// int *out, int size)
//{
// __shared__ int smem[BDIM + 2 * RADIUS];
//
// int gid = blockDim.x * blockIdx.x + threadIdx.x;
// int bid = blockIdx.x;
// int num_of_blocks = gridDim.x;
//
// int value = 0;
//
// if (gid < size)
// {
// int sidx = threadIdx.x + RADIUS;
//
// // Read data from global memory into shared memory
// smem[sidx] = in[gid];
//
// if (bid != 0 && bid != (num_of_blocks - 1))
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else if (bid == 0)
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = 0;
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = 0;
// }
// }
//
// __syncthreads();
//
// value += smem[sidx - 4] * coef[0];
// value += smem[sidx - 3] * coef[1];
// value += smem[sidx - 2] * coef[2];
// value += smem[sidx - 1] * coef[3];
// value += smem[sidx - 0] * coef[4];
// value += smem[sidx + 1] * coef[5];
// value += smem[sidx + 2] * coef[6];
// value += smem[sidx + 3] * coef[7];
// value += smem[sidx + 4] * coef[8];
//
// out[gid] = value;
// }
//}
//
//
//int main(int argc, char ** argv)
//{
// int size = 1 << 22;
// int byte_size = sizeof(int) * size;
// int block_size = BDIM;
//
// int * h_in, *h_out, *h_ref;
//
// h_in = (int*)malloc(byte_size);
// h_out = (int*)malloc(byte_size);
// h_ref = (int*)malloc(byte_size);
//
// initialize(h_in, size, INIT_ONE);
//
// int * d_in, *d_out;
// cudaMalloc((void**)&d_in, byte_size);
// cudaMalloc((void**)&d_out, byte_size);
//
// cudaMemcpy(d_in, h_in, byte_size, cudaMemcpyHostToDevice);
// cudaMemset(d_out, 0, byte_size);
//
// setup_coef_1();
//
// dim3 blocks(block_size);
// dim3 grid(size / blocks.x);
//
// constant_stencil_smem_test << < grid, blocks >> > (d_in, d_out, size);
// cudaDeviceSynchronize();
//
// cudaMemcpy(h_ref, d_out, byte_size, cudaMemcpyDeviceToHost);
//
// host_const_calculation(h_in, h_out, size);
//
// compare_arrays(h_ref, h_out, size);
//
// cudaFree(d_out);
// cudaFree(d_in);
// free(h_ref);
// free(h_out);
// free(h_in);
//
// return 0;
//}//#include <stdio.h>
////#include <stdlib.h>
////#include <time.h>
////
////#include "common.h"
////#include "cuda_common.cuh"
////
////#include "cuda.h"
////#include "cuda_runtime.h"
////#include "device_launch_parameters.h"
////
////#define BDIMX 64
////#define BDIMY 8
////#define IPAD 2
////
////__global__ void transpose_read_raw_write_column_benchmark(int * mat,
//// int* transpose, int nx, int ny)
////{
//// int ix = blockDim.x * blockIdx.x + threadIdx.x;
//// int iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// if (ix < nx && iy < ny)
//// {
//// //read by row, write by col
//// transpose[ix * ny + iy] = mat[iy * nx + ix];
//// }
////}
////
////__global__ void transpose_smem(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX + IPAD];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad_unrolling(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY*(2 * BDIMX + IPAD)];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = 2 * blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = 2 * blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// unsigned int row_idx = threadIdx.y * (blockDim.x * 2 + IPAD) + threadIdx.x;
//// tile[row_idx] = in[in_index];
//// tile[row_idx + BDIMX] = in[in_index + BDIMX];
////
//// // thread synchronization
//// __syncthreads();
////
//// // store two rows to global memory from two columns of shared memory
//// unsigned int col_idx = i_col*(blockDim.x * 2 + IPAD) + i_row;
//// out[out_index] = tile[col_idx];
//// out[out_index + ny*BDIMX] = tile[col_idx + BDIMX];
//// }
////}
////
////int main(int argc, char** argv)
////{
//// //default values for variabless
//// int nx = 1024;
//// int ny = 1024;
//// int block_x = BDIMX;
//// int block_y = BDIMY;
//// int kernel_num = 0;
////
//// //set the variable based on arguments
//// if (argc > 1)
//// nx = 1 << atoi(argv[1]);
//// if (argc > 2)
//// ny = 1 << atoi(argv[2]);
//// if (argc > 3)
//// block_x = 1 << atoi(argv[3]);
//// if (argc > 4)
//// block_y = 1 << atoi(argv[4]);
////
//// int size = nx * ny;
//// int byte_size = sizeof(int*) * size;
////
//// printf("Matrix transpose for %d X % d matrix with block size %d X %d \n", nx, ny, block_x, block_y);
////
//// int * h_mat_array = (int*)malloc(byte_size);
//// int * h_trans_array = (int*)malloc(byte_size);
//// int * h_ref = (int*)malloc(byte_size);
////
//// initialize(h_mat_array, size, INIT_ONE_TO_TEN);
////
//// //matirx transpose in CPU
//// mat_transpose_cpu(h_mat_array, h_trans_array, nx, ny);
////
//// int * d_mat_array, *d_trans_array;
////
//// gpuErrchk(cudaMalloc((void**)&d_mat_array, byte_size));
//// gpuErrchk(cudaMalloc((void**)&d_trans_array, byte_size));
////
//// gpuErrchk(cudaMemcpy(d_mat_array, h_mat_array, byte_size, cudaMemcpyHostToDevice));
//// gpuErrchk(cudaMemset(d_trans_array, 0, byte_size));
////
//// dim3 blocks(block_x, block_y);
//// dim3 grid(nx / block_x, ny / block_y);
////
//// printf("Launching smem kernel \n");
//// transpose_smem << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching benchmark kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_read_raw_write_column_benchmark << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_smem_pad << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding and unrolling kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
////
//// grid.x = grid.x / 2;
////
//// transpose_smem_pad_unrolling << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// cudaFree(d_trans_array);
//// cudaFree(d_mat_array);
//// free(h_ref);
//// free(h_trans_array);
//// free(h_mat_array);
////
//// gpuErrchk(cudaDeviceReset());
//// return EXIT_SUCCESS;
////} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <stdio.h>
//#include <stdlib.h>
//#include <time.h>
//
//#include "common.h"
//#include "cuda_common.cuh"
//
//#include "cuda.h"
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#define c0 1
//#define c1 2
//#define c2 3
//#define c3 4
//#define c4 5
//
//#define RADIUS 4
//
//#define BDIM 128
//
////constant memory declaration
//__constant__ int coef[9];
//
//void host_const_calculation(int * in, int * out, int size)
//{
// for (int i = 0; i < size; i++)
// {
//
// if (i < RADIUS)
// {
// out[i] = in[i + 4] * c0
// + in[i + 3] * c1
// + in[i + 2] * c2
// + in[i + 1] * c3
// + in[i] * c4;
//
// if (i == 3)
// {
// out[i] += in[2] * c3;
// out[i] += in[1] * c2;
// out[i] += in[0] * c1;
// }
// else if (i == 2)
// {
// out[i] += in[1] * c3;
// out[i] += in[0] * c2;
// }
// else if (i == 1)
// {
// out[i] += in[0] * c3;
// }
// }
// else if ((i + RADIUS) >= size)
// {
// out[i] = in[i - 4] * c0
// + in[i - 3] * c1
// + in[i - 2] * c2
// + in[i - 1] * c3
// + in[i] * c4;
//
// if (i == size - 4)
// {
// out[i] += in[size - 3] * c3;
// out[i] += in[size - 2] * c2;
// out[i] += in[size - 1] * c1;
// }
// else if (i == size - 3)
// {
// out[i] += in[size - 2] * c3;
// out[i] += in[size - 1] * c2;
// }
// else if (i == size - 2)
// {
// out[i] += in[size - 1] * c3;
// }
// }
// else
// {
// out[i] = (in[i - 4] + in[i + 4])*c0
// + (in[i - 3] + in[i + 3])*c1
// + (in[i - 2] + in[i + 2])*c2
// + (in[i - 1] + in[i + 1])*c3
// + in[i] * c4;
// }
// }
//}
//
////setting up constant memory from host
//void setup_coef_1()
//{
// const int h_coef[] = { c0,c1,c2,c3,c4,c3,c2,c1,c0 };
// cudaMemcpyToSymbol(coef, h_coef, (9) * sizeof(float));
//}
//
//__global__ void constant_stencil_smem_test(int * in,
// int *out, int size)
//{
// __shared__ int smem[BDIM + 2 * RADIUS];
//
// int gid = blockDim.x * blockIdx.x + threadIdx.x;
// int bid = blockIdx.x;
// int num_of_blocks = gridDim.x;
//
// int value = 0;
//
// if (gid < size)
// {
// int sidx = threadIdx.x + RADIUS;
//
// // Read data from global memory into shared memory
// smem[sidx] = in[gid];
//
// if (bid != 0 && bid != (num_of_blocks - 1))
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else if (bid == 0)
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = 0;
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = 0;
// }
// }
//
// __syncthreads();
//
// value += smem[sidx - 4] * coef[0];
// value += smem[sidx - 3] * coef[1];
// value += smem[sidx - 2] * coef[2];
// value += smem[sidx - 1] * coef[3];
// value += smem[sidx - 0] * coef[4];
// value += smem[sidx + 1] * coef[5];
// value += smem[sidx + 2] * coef[6];
// value += smem[sidx + 3] * coef[7];
// value += smem[sidx + 4] * coef[8];
//
// out[gid] = value;
// }
//}
//
//
//int main(int argc, char ** argv)
//{
// int size = 1 << 22;
// int byte_size = sizeof(int) * size;
// int block_size = BDIM;
//
// int * h_in, *h_out, *h_ref;
//
// h_in = (int*)malloc(byte_size);
// h_out = (int*)malloc(byte_size);
// h_ref = (int*)malloc(byte_size);
//
// initialize(h_in, size, INIT_ONE);
//
// int * d_in, *d_out;
// cudaMalloc((void**)&d_in, byte_size);
// cudaMalloc((void**)&d_out, byte_size);
//
// cudaMemcpy(d_in, h_in, byte_size, cudaMemcpyHostToDevice);
// cudaMemset(d_out, 0, byte_size);
//
// setup_coef_1();
//
// dim3 blocks(block_size);
// dim3 grid(size / blocks.x);
//
// constant_stencil_smem_test << < grid, blocks >> > (d_in, d_out, size);
// cudaDeviceSynchronize();
//
// cudaMemcpy(h_ref, d_out, byte_size, cudaMemcpyDeviceToHost);
//
// host_const_calculation(h_in, h_out, size);
//
// compare_arrays(h_ref, h_out, size);
//
// cudaFree(d_out);
// cudaFree(d_in);
// free(h_ref);
// free(h_out);
// free(h_in);
//
// return 0;
//}//#include <stdio.h>
////#include <stdlib.h>
////#include <time.h>
////
////#include "common.h"
////#include "cuda_common.cuh"
////
////#include "cuda.h"
////#include "cuda_runtime.h"
////#include "device_launch_parameters.h"
////
////#define BDIMX 64
////#define BDIMY 8
////#define IPAD 2
////
////__global__ void transpose_read_raw_write_column_benchmark(int * mat,
//// int* transpose, int nx, int ny)
////{
//// int ix = blockDim.x * blockIdx.x + threadIdx.x;
//// int iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// if (ix < nx && iy < ny)
//// {
//// //read by row, write by col
//// transpose[ix * ny + iy] = mat[iy * nx + ix];
//// }
////}
////
////__global__ void transpose_smem(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX + IPAD];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad_unrolling(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY*(2 * BDIMX + IPAD)];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = 2 * blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = 2 * blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// unsigned int row_idx = threadIdx.y * (blockDim.x * 2 + IPAD) + threadIdx.x;
//// tile[row_idx] = in[in_index];
//// tile[row_idx + BDIMX] = in[in_index + BDIMX];
////
//// // thread synchronization
//// __syncthreads();
////
//// // store two rows to global memory from two columns of shared memory
//// unsigned int col_idx = i_col*(blockDim.x * 2 + IPAD) + i_row;
//// out[out_index] = tile[col_idx];
//// out[out_index + ny*BDIMX] = tile[col_idx + BDIMX];
//// }
////}
////
////int main(int argc, char** argv)
////{
//// //default values for variabless
//// int nx = 1024;
//// int ny = 1024;
//// int block_x = BDIMX;
//// int block_y = BDIMY;
//// int kernel_num = 0;
////
//// //set the variable based on arguments
//// if (argc > 1)
//// nx = 1 << atoi(argv[1]);
//// if (argc > 2)
//// ny = 1 << atoi(argv[2]);
//// if (argc > 3)
//// block_x = 1 << atoi(argv[3]);
//// if (argc > 4)
//// block_y = 1 << atoi(argv[4]);
////
//// int size = nx * ny;
//// int byte_size = sizeof(int*) * size;
////
//// printf("Matrix transpose for %d X % d matrix with block size %d X %d \n", nx, ny, block_x, block_y);
////
//// int * h_mat_array = (int*)malloc(byte_size);
//// int * h_trans_array = (int*)malloc(byte_size);
//// int * h_ref = (int*)malloc(byte_size);
////
//// initialize(h_mat_array, size, INIT_ONE_TO_TEN);
////
//// //matirx transpose in CPU
//// mat_transpose_cpu(h_mat_array, h_trans_array, nx, ny);
////
//// int * d_mat_array, *d_trans_array;
////
//// gpuErrchk(cudaMalloc((void**)&d_mat_array, byte_size));
//// gpuErrchk(cudaMalloc((void**)&d_trans_array, byte_size));
////
//// gpuErrchk(cudaMemcpy(d_mat_array, h_mat_array, byte_size, cudaMemcpyHostToDevice));
//// gpuErrchk(cudaMemset(d_trans_array, 0, byte_size));
////
//// dim3 blocks(block_x, block_y);
//// dim3 grid(nx / block_x, ny / block_y);
////
//// printf("Launching smem kernel \n");
//// transpose_smem << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching benchmark kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_read_raw_write_column_benchmark << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_smem_pad << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding and unrolling kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
////
//// grid.x = grid.x / 2;
////
//// transpose_smem_pad_unrolling << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// cudaFree(d_trans_array);
//// cudaFree(d_mat_array);
//// free(h_ref);
//// free(h_trans_array);
//// free(h_mat_array);
////
//// gpuErrchk(cudaDeviceReset());
//// return EXIT_SUCCESS;
////} | .file "tmpxft_000695a7_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <stdio.h>
//#include <stdlib.h>
//#include <time.h>
//
//#include "common.h"
//#include "cuda_common.cuh"
//
//#include "cuda.h"
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#define c0 1
//#define c1 2
//#define c2 3
//#define c3 4
//#define c4 5
//
//#define RADIUS 4
//
//#define BDIM 128
//
////constant memory declaration
//__constant__ int coef[9];
//
//void host_const_calculation(int * in, int * out, int size)
//{
// for (int i = 0; i < size; i++)
// {
//
// if (i < RADIUS)
// {
// out[i] = in[i + 4] * c0
// + in[i + 3] * c1
// + in[i + 2] * c2
// + in[i + 1] * c3
// + in[i] * c4;
//
// if (i == 3)
// {
// out[i] += in[2] * c3;
// out[i] += in[1] * c2;
// out[i] += in[0] * c1;
// }
// else if (i == 2)
// {
// out[i] += in[1] * c3;
// out[i] += in[0] * c2;
// }
// else if (i == 1)
// {
// out[i] += in[0] * c3;
// }
// }
// else if ((i + RADIUS) >= size)
// {
// out[i] = in[i - 4] * c0
// + in[i - 3] * c1
// + in[i - 2] * c2
// + in[i - 1] * c3
// + in[i] * c4;
//
// if (i == size - 4)
// {
// out[i] += in[size - 3] * c3;
// out[i] += in[size - 2] * c2;
// out[i] += in[size - 1] * c1;
// }
// else if (i == size - 3)
// {
// out[i] += in[size - 2] * c3;
// out[i] += in[size - 1] * c2;
// }
// else if (i == size - 2)
// {
// out[i] += in[size - 1] * c3;
// }
// }
// else
// {
// out[i] = (in[i - 4] + in[i + 4])*c0
// + (in[i - 3] + in[i + 3])*c1
// + (in[i - 2] + in[i + 2])*c2
// + (in[i - 1] + in[i + 1])*c3
// + in[i] * c4;
// }
// }
//}
//
////setting up constant memory from host
//void setup_coef_1()
//{
// const int h_coef[] = { c0,c1,c2,c3,c4,c3,c2,c1,c0 };
// cudaMemcpyToSymbol(coef, h_coef, (9) * sizeof(float));
//}
//
//__global__ void constant_stencil_smem_test(int * in,
// int *out, int size)
//{
// __shared__ int smem[BDIM + 2 * RADIUS];
//
// int gid = blockDim.x * blockIdx.x + threadIdx.x;
// int bid = blockIdx.x;
// int num_of_blocks = gridDim.x;
//
// int value = 0;
//
// if (gid < size)
// {
// int sidx = threadIdx.x + RADIUS;
//
// // Read data from global memory into shared memory
// smem[sidx] = in[gid];
//
// if (bid != 0 && bid != (num_of_blocks - 1))
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else if (bid == 0)
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = 0;
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = 0;
// }
// }
//
// __syncthreads();
//
// value += smem[sidx - 4] * coef[0];
// value += smem[sidx - 3] * coef[1];
// value += smem[sidx - 2] * coef[2];
// value += smem[sidx - 1] * coef[3];
// value += smem[sidx - 0] * coef[4];
// value += smem[sidx + 1] * coef[5];
// value += smem[sidx + 2] * coef[6];
// value += smem[sidx + 3] * coef[7];
// value += smem[sidx + 4] * coef[8];
//
// out[gid] = value;
// }
//}
//
//
//int main(int argc, char ** argv)
//{
// int size = 1 << 22;
// int byte_size = sizeof(int) * size;
// int block_size = BDIM;
//
// int * h_in, *h_out, *h_ref;
//
// h_in = (int*)malloc(byte_size);
// h_out = (int*)malloc(byte_size);
// h_ref = (int*)malloc(byte_size);
//
// initialize(h_in, size, INIT_ONE);
//
// int * d_in, *d_out;
// cudaMalloc((void**)&d_in, byte_size);
// cudaMalloc((void**)&d_out, byte_size);
//
// cudaMemcpy(d_in, h_in, byte_size, cudaMemcpyHostToDevice);
// cudaMemset(d_out, 0, byte_size);
//
// setup_coef_1();
//
// dim3 blocks(block_size);
// dim3 grid(size / blocks.x);
//
// constant_stencil_smem_test << < grid, blocks >> > (d_in, d_out, size);
// cudaDeviceSynchronize();
//
// cudaMemcpy(h_ref, d_out, byte_size, cudaMemcpyDeviceToHost);
//
// host_const_calculation(h_in, h_out, size);
//
// compare_arrays(h_ref, h_out, size);
//
// cudaFree(d_out);
// cudaFree(d_in);
// free(h_ref);
// free(h_out);
// free(h_in);
//
// return 0;
//}//#include <stdio.h>
////#include <stdlib.h>
////#include <time.h>
////
////#include "common.h"
////#include "cuda_common.cuh"
////
////#include "cuda.h"
////#include "cuda_runtime.h"
////#include "device_launch_parameters.h"
////
////#define BDIMX 64
////#define BDIMY 8
////#define IPAD 2
////
////__global__ void transpose_read_raw_write_column_benchmark(int * mat,
//// int* transpose, int nx, int ny)
////{
//// int ix = blockDim.x * blockIdx.x + threadIdx.x;
//// int iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// if (ix < nx && iy < ny)
//// {
//// //read by row, write by col
//// transpose[ix * ny + iy] = mat[iy * nx + ix];
//// }
////}
////
////__global__ void transpose_smem(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX + IPAD];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad_unrolling(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY*(2 * BDIMX + IPAD)];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = 2 * blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = 2 * blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// unsigned int row_idx = threadIdx.y * (blockDim.x * 2 + IPAD) + threadIdx.x;
//// tile[row_idx] = in[in_index];
//// tile[row_idx + BDIMX] = in[in_index + BDIMX];
////
//// // thread synchronization
//// __syncthreads();
////
//// // store two rows to global memory from two columns of shared memory
//// unsigned int col_idx = i_col*(blockDim.x * 2 + IPAD) + i_row;
//// out[out_index] = tile[col_idx];
//// out[out_index + ny*BDIMX] = tile[col_idx + BDIMX];
//// }
////}
////
////int main(int argc, char** argv)
////{
//// //default values for variabless
//// int nx = 1024;
//// int ny = 1024;
//// int block_x = BDIMX;
//// int block_y = BDIMY;
//// int kernel_num = 0;
////
//// //set the variable based on arguments
//// if (argc > 1)
//// nx = 1 << atoi(argv[1]);
//// if (argc > 2)
//// ny = 1 << atoi(argv[2]);
//// if (argc > 3)
//// block_x = 1 << atoi(argv[3]);
//// if (argc > 4)
//// block_y = 1 << atoi(argv[4]);
////
//// int size = nx * ny;
//// int byte_size = sizeof(int*) * size;
////
//// printf("Matrix transpose for %d X % d matrix with block size %d X %d \n", nx, ny, block_x, block_y);
////
//// int * h_mat_array = (int*)malloc(byte_size);
//// int * h_trans_array = (int*)malloc(byte_size);
//// int * h_ref = (int*)malloc(byte_size);
////
//// initialize(h_mat_array, size, INIT_ONE_TO_TEN);
////
//// //matirx transpose in CPU
//// mat_transpose_cpu(h_mat_array, h_trans_array, nx, ny);
////
//// int * d_mat_array, *d_trans_array;
////
//// gpuErrchk(cudaMalloc((void**)&d_mat_array, byte_size));
//// gpuErrchk(cudaMalloc((void**)&d_trans_array, byte_size));
////
//// gpuErrchk(cudaMemcpy(d_mat_array, h_mat_array, byte_size, cudaMemcpyHostToDevice));
//// gpuErrchk(cudaMemset(d_trans_array, 0, byte_size));
////
//// dim3 blocks(block_x, block_y);
//// dim3 grid(nx / block_x, ny / block_y);
////
//// printf("Launching smem kernel \n");
//// transpose_smem << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching benchmark kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_read_raw_write_column_benchmark << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_smem_pad << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding and unrolling kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
////
//// grid.x = grid.x / 2;
////
//// transpose_smem_pad_unrolling << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// cudaFree(d_trans_array);
//// cudaFree(d_mat_array);
//// free(h_ref);
//// free(h_trans_array);
//// free(h_mat_array);
////
//// gpuErrchk(cudaDeviceReset());
//// return EXIT_SUCCESS;
////} | #include <hip/hip_runtime.h>
//#include <stdio.h>
//#include <stdlib.h>
//#include <time.h>
//
//#include "common.h"
//#include "cuda_common.cuh"
//
//#include "cuda.h"
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#define c0 1
//#define c1 2
//#define c2 3
//#define c3 4
//#define c4 5
//
//#define RADIUS 4
//
//#define BDIM 128
//
////constant memory declaration
//__constant__ int coef[9];
//
//void host_const_calculation(int * in, int * out, int size)
//{
// for (int i = 0; i < size; i++)
// {
//
// if (i < RADIUS)
// {
// out[i] = in[i + 4] * c0
// + in[i + 3] * c1
// + in[i + 2] * c2
// + in[i + 1] * c3
// + in[i] * c4;
//
// if (i == 3)
// {
// out[i] += in[2] * c3;
// out[i] += in[1] * c2;
// out[i] += in[0] * c1;
// }
// else if (i == 2)
// {
// out[i] += in[1] * c3;
// out[i] += in[0] * c2;
// }
// else if (i == 1)
// {
// out[i] += in[0] * c3;
// }
// }
// else if ((i + RADIUS) >= size)
// {
// out[i] = in[i - 4] * c0
// + in[i - 3] * c1
// + in[i - 2] * c2
// + in[i - 1] * c3
// + in[i] * c4;
//
// if (i == size - 4)
// {
// out[i] += in[size - 3] * c3;
// out[i] += in[size - 2] * c2;
// out[i] += in[size - 1] * c1;
// }
// else if (i == size - 3)
// {
// out[i] += in[size - 2] * c3;
// out[i] += in[size - 1] * c2;
// }
// else if (i == size - 2)
// {
// out[i] += in[size - 1] * c3;
// }
// }
// else
// {
// out[i] = (in[i - 4] + in[i + 4])*c0
// + (in[i - 3] + in[i + 3])*c1
// + (in[i - 2] + in[i + 2])*c2
// + (in[i - 1] + in[i + 1])*c3
// + in[i] * c4;
// }
// }
//}
//
////setting up constant memory from host
//void setup_coef_1()
//{
// const int h_coef[] = { c0,c1,c2,c3,c4,c3,c2,c1,c0 };
// cudaMemcpyToSymbol(coef, h_coef, (9) * sizeof(float));
//}
//
//__global__ void constant_stencil_smem_test(int * in,
// int *out, int size)
//{
// __shared__ int smem[BDIM + 2 * RADIUS];
//
// int gid = blockDim.x * blockIdx.x + threadIdx.x;
// int bid = blockIdx.x;
// int num_of_blocks = gridDim.x;
//
// int value = 0;
//
// if (gid < size)
// {
// int sidx = threadIdx.x + RADIUS;
//
// // Read data from global memory into shared memory
// smem[sidx] = in[gid];
//
// if (bid != 0 && bid != (num_of_blocks - 1))
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else if (bid == 0)
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = 0;
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = 0;
// }
// }
//
// __syncthreads();
//
// value += smem[sidx - 4] * coef[0];
// value += smem[sidx - 3] * coef[1];
// value += smem[sidx - 2] * coef[2];
// value += smem[sidx - 1] * coef[3];
// value += smem[sidx - 0] * coef[4];
// value += smem[sidx + 1] * coef[5];
// value += smem[sidx + 2] * coef[6];
// value += smem[sidx + 3] * coef[7];
// value += smem[sidx + 4] * coef[8];
//
// out[gid] = value;
// }
//}
//
//
//int main(int argc, char ** argv)
//{
// int size = 1 << 22;
// int byte_size = sizeof(int) * size;
// int block_size = BDIM;
//
// int * h_in, *h_out, *h_ref;
//
// h_in = (int*)malloc(byte_size);
// h_out = (int*)malloc(byte_size);
// h_ref = (int*)malloc(byte_size);
//
// initialize(h_in, size, INIT_ONE);
//
// int * d_in, *d_out;
// cudaMalloc((void**)&d_in, byte_size);
// cudaMalloc((void**)&d_out, byte_size);
//
// cudaMemcpy(d_in, h_in, byte_size, cudaMemcpyHostToDevice);
// cudaMemset(d_out, 0, byte_size);
//
// setup_coef_1();
//
// dim3 blocks(block_size);
// dim3 grid(size / blocks.x);
//
// constant_stencil_smem_test << < grid, blocks >> > (d_in, d_out, size);
// cudaDeviceSynchronize();
//
// cudaMemcpy(h_ref, d_out, byte_size, cudaMemcpyDeviceToHost);
//
// host_const_calculation(h_in, h_out, size);
//
// compare_arrays(h_ref, h_out, size);
//
// cudaFree(d_out);
// cudaFree(d_in);
// free(h_ref);
// free(h_out);
// free(h_in);
//
// return 0;
//}//#include <stdio.h>
////#include <stdlib.h>
////#include <time.h>
////
////#include "common.h"
////#include "cuda_common.cuh"
////
////#include "cuda.h"
////#include "cuda_runtime.h"
////#include "device_launch_parameters.h"
////
////#define BDIMX 64
////#define BDIMY 8
////#define IPAD 2
////
////__global__ void transpose_read_raw_write_column_benchmark(int * mat,
//// int* transpose, int nx, int ny)
////{
//// int ix = blockDim.x * blockIdx.x + threadIdx.x;
//// int iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// if (ix < nx && iy < ny)
//// {
//// //read by row, write by col
//// transpose[ix * ny + iy] = mat[iy * nx + ix];
//// }
////}
////
////__global__ void transpose_smem(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX + IPAD];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad_unrolling(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY*(2 * BDIMX + IPAD)];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = 2 * blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = 2 * blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// unsigned int row_idx = threadIdx.y * (blockDim.x * 2 + IPAD) + threadIdx.x;
//// tile[row_idx] = in[in_index];
//// tile[row_idx + BDIMX] = in[in_index + BDIMX];
////
//// // thread synchronization
//// __syncthreads();
////
//// // store two rows to global memory from two columns of shared memory
//// unsigned int col_idx = i_col*(blockDim.x * 2 + IPAD) + i_row;
//// out[out_index] = tile[col_idx];
//// out[out_index + ny*BDIMX] = tile[col_idx + BDIMX];
//// }
////}
////
////int main(int argc, char** argv)
////{
//// //default values for variabless
//// int nx = 1024;
//// int ny = 1024;
//// int block_x = BDIMX;
//// int block_y = BDIMY;
//// int kernel_num = 0;
////
//// //set the variable based on arguments
//// if (argc > 1)
//// nx = 1 << atoi(argv[1]);
//// if (argc > 2)
//// ny = 1 << atoi(argv[2]);
//// if (argc > 3)
//// block_x = 1 << atoi(argv[3]);
//// if (argc > 4)
//// block_y = 1 << atoi(argv[4]);
////
//// int size = nx * ny;
//// int byte_size = sizeof(int*) * size;
////
//// printf("Matrix transpose for %d X % d matrix with block size %d X %d \n", nx, ny, block_x, block_y);
////
//// int * h_mat_array = (int*)malloc(byte_size);
//// int * h_trans_array = (int*)malloc(byte_size);
//// int * h_ref = (int*)malloc(byte_size);
////
//// initialize(h_mat_array, size, INIT_ONE_TO_TEN);
////
//// //matirx transpose in CPU
//// mat_transpose_cpu(h_mat_array, h_trans_array, nx, ny);
////
//// int * d_mat_array, *d_trans_array;
////
//// gpuErrchk(cudaMalloc((void**)&d_mat_array, byte_size));
//// gpuErrchk(cudaMalloc((void**)&d_trans_array, byte_size));
////
//// gpuErrchk(cudaMemcpy(d_mat_array, h_mat_array, byte_size, cudaMemcpyHostToDevice));
//// gpuErrchk(cudaMemset(d_trans_array, 0, byte_size));
////
//// dim3 blocks(block_x, block_y);
//// dim3 grid(nx / block_x, ny / block_y);
////
//// printf("Launching smem kernel \n");
//// transpose_smem << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching benchmark kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_read_raw_write_column_benchmark << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_smem_pad << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding and unrolling kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
////
//// grid.x = grid.x / 2;
////
//// transpose_smem_pad_unrolling << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// cudaFree(d_trans_array);
//// cudaFree(d_mat_array);
//// free(h_ref);
//// free(h_trans_array);
//// free(h_mat_array);
////
//// gpuErrchk(cudaDeviceReset());
//// return EXIT_SUCCESS;
////} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <stdio.h>
//#include <stdlib.h>
//#include <time.h>
//
//#include "common.h"
//#include "cuda_common.cuh"
//
//#include "cuda.h"
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#define c0 1
//#define c1 2
//#define c2 3
//#define c3 4
//#define c4 5
//
//#define RADIUS 4
//
//#define BDIM 128
//
////constant memory declaration
//__constant__ int coef[9];
//
//void host_const_calculation(int * in, int * out, int size)
//{
// for (int i = 0; i < size; i++)
// {
//
// if (i < RADIUS)
// {
// out[i] = in[i + 4] * c0
// + in[i + 3] * c1
// + in[i + 2] * c2
// + in[i + 1] * c3
// + in[i] * c4;
//
// if (i == 3)
// {
// out[i] += in[2] * c3;
// out[i] += in[1] * c2;
// out[i] += in[0] * c1;
// }
// else if (i == 2)
// {
// out[i] += in[1] * c3;
// out[i] += in[0] * c2;
// }
// else if (i == 1)
// {
// out[i] += in[0] * c3;
// }
// }
// else if ((i + RADIUS) >= size)
// {
// out[i] = in[i - 4] * c0
// + in[i - 3] * c1
// + in[i - 2] * c2
// + in[i - 1] * c3
// + in[i] * c4;
//
// if (i == size - 4)
// {
// out[i] += in[size - 3] * c3;
// out[i] += in[size - 2] * c2;
// out[i] += in[size - 1] * c1;
// }
// else if (i == size - 3)
// {
// out[i] += in[size - 2] * c3;
// out[i] += in[size - 1] * c2;
// }
// else if (i == size - 2)
// {
// out[i] += in[size - 1] * c3;
// }
// }
// else
// {
// out[i] = (in[i - 4] + in[i + 4])*c0
// + (in[i - 3] + in[i + 3])*c1
// + (in[i - 2] + in[i + 2])*c2
// + (in[i - 1] + in[i + 1])*c3
// + in[i] * c4;
// }
// }
//}
//
////setting up constant memory from host
//void setup_coef_1()
//{
// const int h_coef[] = { c0,c1,c2,c3,c4,c3,c2,c1,c0 };
// cudaMemcpyToSymbol(coef, h_coef, (9) * sizeof(float));
//}
//
//__global__ void constant_stencil_smem_test(int * in,
// int *out, int size)
//{
// __shared__ int smem[BDIM + 2 * RADIUS];
//
// int gid = blockDim.x * blockIdx.x + threadIdx.x;
// int bid = blockIdx.x;
// int num_of_blocks = gridDim.x;
//
// int value = 0;
//
// if (gid < size)
// {
// int sidx = threadIdx.x + RADIUS;
//
// // Read data from global memory into shared memory
// smem[sidx] = in[gid];
//
// if (bid != 0 && bid != (num_of_blocks - 1))
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else if (bid == 0)
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = 0;
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = 0;
// }
// }
//
// __syncthreads();
//
// value += smem[sidx - 4] * coef[0];
// value += smem[sidx - 3] * coef[1];
// value += smem[sidx - 2] * coef[2];
// value += smem[sidx - 1] * coef[3];
// value += smem[sidx - 0] * coef[4];
// value += smem[sidx + 1] * coef[5];
// value += smem[sidx + 2] * coef[6];
// value += smem[sidx + 3] * coef[7];
// value += smem[sidx + 4] * coef[8];
//
// out[gid] = value;
// }
//}
//
//
//int main(int argc, char ** argv)
//{
// int size = 1 << 22;
// int byte_size = sizeof(int) * size;
// int block_size = BDIM;
//
// int * h_in, *h_out, *h_ref;
//
// h_in = (int*)malloc(byte_size);
// h_out = (int*)malloc(byte_size);
// h_ref = (int*)malloc(byte_size);
//
// initialize(h_in, size, INIT_ONE);
//
// int * d_in, *d_out;
// cudaMalloc((void**)&d_in, byte_size);
// cudaMalloc((void**)&d_out, byte_size);
//
// cudaMemcpy(d_in, h_in, byte_size, cudaMemcpyHostToDevice);
// cudaMemset(d_out, 0, byte_size);
//
// setup_coef_1();
//
// dim3 blocks(block_size);
// dim3 grid(size / blocks.x);
//
// constant_stencil_smem_test << < grid, blocks >> > (d_in, d_out, size);
// cudaDeviceSynchronize();
//
// cudaMemcpy(h_ref, d_out, byte_size, cudaMemcpyDeviceToHost);
//
// host_const_calculation(h_in, h_out, size);
//
// compare_arrays(h_ref, h_out, size);
//
// cudaFree(d_out);
// cudaFree(d_in);
// free(h_ref);
// free(h_out);
// free(h_in);
//
// return 0;
//}//#include <stdio.h>
////#include <stdlib.h>
////#include <time.h>
////
////#include "common.h"
////#include "cuda_common.cuh"
////
////#include "cuda.h"
////#include "cuda_runtime.h"
////#include "device_launch_parameters.h"
////
////#define BDIMX 64
////#define BDIMY 8
////#define IPAD 2
////
////__global__ void transpose_read_raw_write_column_benchmark(int * mat,
//// int* transpose, int nx, int ny)
////{
//// int ix = blockDim.x * blockIdx.x + threadIdx.x;
//// int iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// if (ix < nx && iy < ny)
//// {
//// //read by row, write by col
//// transpose[ix * ny + iy] = mat[iy * nx + ix];
//// }
////}
////
////__global__ void transpose_smem(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX + IPAD];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad_unrolling(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY*(2 * BDIMX + IPAD)];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = 2 * blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = 2 * blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// unsigned int row_idx = threadIdx.y * (blockDim.x * 2 + IPAD) + threadIdx.x;
//// tile[row_idx] = in[in_index];
//// tile[row_idx + BDIMX] = in[in_index + BDIMX];
////
//// // thread synchronization
//// __syncthreads();
////
//// // store two rows to global memory from two columns of shared memory
//// unsigned int col_idx = i_col*(blockDim.x * 2 + IPAD) + i_row;
//// out[out_index] = tile[col_idx];
//// out[out_index + ny*BDIMX] = tile[col_idx + BDIMX];
//// }
////}
////
////int main(int argc, char** argv)
////{
//// //default values for variabless
//// int nx = 1024;
//// int ny = 1024;
//// int block_x = BDIMX;
//// int block_y = BDIMY;
//// int kernel_num = 0;
////
//// //set the variable based on arguments
//// if (argc > 1)
//// nx = 1 << atoi(argv[1]);
//// if (argc > 2)
//// ny = 1 << atoi(argv[2]);
//// if (argc > 3)
//// block_x = 1 << atoi(argv[3]);
//// if (argc > 4)
//// block_y = 1 << atoi(argv[4]);
////
//// int size = nx * ny;
//// int byte_size = sizeof(int*) * size;
////
//// printf("Matrix transpose for %d X % d matrix with block size %d X %d \n", nx, ny, block_x, block_y);
////
//// int * h_mat_array = (int*)malloc(byte_size);
//// int * h_trans_array = (int*)malloc(byte_size);
//// int * h_ref = (int*)malloc(byte_size);
////
//// initialize(h_mat_array, size, INIT_ONE_TO_TEN);
////
//// //matirx transpose in CPU
//// mat_transpose_cpu(h_mat_array, h_trans_array, nx, ny);
////
//// int * d_mat_array, *d_trans_array;
////
//// gpuErrchk(cudaMalloc((void**)&d_mat_array, byte_size));
//// gpuErrchk(cudaMalloc((void**)&d_trans_array, byte_size));
////
//// gpuErrchk(cudaMemcpy(d_mat_array, h_mat_array, byte_size, cudaMemcpyHostToDevice));
//// gpuErrchk(cudaMemset(d_trans_array, 0, byte_size));
////
//// dim3 blocks(block_x, block_y);
//// dim3 grid(nx / block_x, ny / block_y);
////
//// printf("Launching smem kernel \n");
//// transpose_smem << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching benchmark kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_read_raw_write_column_benchmark << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_smem_pad << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding and unrolling kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
////
//// grid.x = grid.x / 2;
////
//// transpose_smem_pad_unrolling << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// cudaFree(d_trans_array);
//// cudaFree(d_mat_array);
//// free(h_ref);
//// free(h_trans_array);
//// free(h_mat_array);
////
//// gpuErrchk(cudaDeviceReset());
//// return EXIT_SUCCESS;
////} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <stdio.h>
//#include <stdlib.h>
//#include <time.h>
//
//#include "common.h"
//#include "cuda_common.cuh"
//
//#include "cuda.h"
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
//#define c0 1
//#define c1 2
//#define c2 3
//#define c3 4
//#define c4 5
//
//#define RADIUS 4
//
//#define BDIM 128
//
////constant memory declaration
//__constant__ int coef[9];
//
//void host_const_calculation(int * in, int * out, int size)
//{
// for (int i = 0; i < size; i++)
// {
//
// if (i < RADIUS)
// {
// out[i] = in[i + 4] * c0
// + in[i + 3] * c1
// + in[i + 2] * c2
// + in[i + 1] * c3
// + in[i] * c4;
//
// if (i == 3)
// {
// out[i] += in[2] * c3;
// out[i] += in[1] * c2;
// out[i] += in[0] * c1;
// }
// else if (i == 2)
// {
// out[i] += in[1] * c3;
// out[i] += in[0] * c2;
// }
// else if (i == 1)
// {
// out[i] += in[0] * c3;
// }
// }
// else if ((i + RADIUS) >= size)
// {
// out[i] = in[i - 4] * c0
// + in[i - 3] * c1
// + in[i - 2] * c2
// + in[i - 1] * c3
// + in[i] * c4;
//
// if (i == size - 4)
// {
// out[i] += in[size - 3] * c3;
// out[i] += in[size - 2] * c2;
// out[i] += in[size - 1] * c1;
// }
// else if (i == size - 3)
// {
// out[i] += in[size - 2] * c3;
// out[i] += in[size - 1] * c2;
// }
// else if (i == size - 2)
// {
// out[i] += in[size - 1] * c3;
// }
// }
// else
// {
// out[i] = (in[i - 4] + in[i + 4])*c0
// + (in[i - 3] + in[i + 3])*c1
// + (in[i - 2] + in[i + 2])*c2
// + (in[i - 1] + in[i + 1])*c3
// + in[i] * c4;
// }
// }
//}
//
////setting up constant memory from host
//void setup_coef_1()
//{
// const int h_coef[] = { c0,c1,c2,c3,c4,c3,c2,c1,c0 };
// cudaMemcpyToSymbol(coef, h_coef, (9) * sizeof(float));
//}
//
//__global__ void constant_stencil_smem_test(int * in,
// int *out, int size)
//{
// __shared__ int smem[BDIM + 2 * RADIUS];
//
// int gid = blockDim.x * blockIdx.x + threadIdx.x;
// int bid = blockIdx.x;
// int num_of_blocks = gridDim.x;
//
// int value = 0;
//
// if (gid < size)
// {
// int sidx = threadIdx.x + RADIUS;
//
// // Read data from global memory into shared memory
// smem[sidx] = in[gid];
//
// if (bid != 0 && bid != (num_of_blocks - 1))
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else if (bid == 0)
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = 0;
// smem[sidx + BDIM] = in[gid + BDIM];
// }
// }
// else
// {
// if (threadIdx.x < RADIUS)
// {
// smem[sidx - RADIUS] = in[gid - RADIUS];
// smem[sidx + BDIM] = 0;
// }
// }
//
// __syncthreads();
//
// value += smem[sidx - 4] * coef[0];
// value += smem[sidx - 3] * coef[1];
// value += smem[sidx - 2] * coef[2];
// value += smem[sidx - 1] * coef[3];
// value += smem[sidx - 0] * coef[4];
// value += smem[sidx + 1] * coef[5];
// value += smem[sidx + 2] * coef[6];
// value += smem[sidx + 3] * coef[7];
// value += smem[sidx + 4] * coef[8];
//
// out[gid] = value;
// }
//}
//
//
//int main(int argc, char ** argv)
//{
// int size = 1 << 22;
// int byte_size = sizeof(int) * size;
// int block_size = BDIM;
//
// int * h_in, *h_out, *h_ref;
//
// h_in = (int*)malloc(byte_size);
// h_out = (int*)malloc(byte_size);
// h_ref = (int*)malloc(byte_size);
//
// initialize(h_in, size, INIT_ONE);
//
// int * d_in, *d_out;
// cudaMalloc((void**)&d_in, byte_size);
// cudaMalloc((void**)&d_out, byte_size);
//
// cudaMemcpy(d_in, h_in, byte_size, cudaMemcpyHostToDevice);
// cudaMemset(d_out, 0, byte_size);
//
// setup_coef_1();
//
// dim3 blocks(block_size);
// dim3 grid(size / blocks.x);
//
// constant_stencil_smem_test << < grid, blocks >> > (d_in, d_out, size);
// cudaDeviceSynchronize();
//
// cudaMemcpy(h_ref, d_out, byte_size, cudaMemcpyDeviceToHost);
//
// host_const_calculation(h_in, h_out, size);
//
// compare_arrays(h_ref, h_out, size);
//
// cudaFree(d_out);
// cudaFree(d_in);
// free(h_ref);
// free(h_out);
// free(h_in);
//
// return 0;
//}//#include <stdio.h>
////#include <stdlib.h>
////#include <time.h>
////
////#include "common.h"
////#include "cuda_common.cuh"
////
////#include "cuda.h"
////#include "cuda_runtime.h"
////#include "device_launch_parameters.h"
////
////#define BDIMX 64
////#define BDIMY 8
////#define IPAD 2
////
////__global__ void transpose_read_raw_write_column_benchmark(int * mat,
//// int* transpose, int nx, int ny)
////{
//// int ix = blockDim.x * blockIdx.x + threadIdx.x;
//// int iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// if (ix < nx && iy < ny)
//// {
//// //read by row, write by col
//// transpose[ix * ny + iy] = mat[iy * nx + ix];
//// }
////}
////
////__global__ void transpose_smem(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY][BDIMX + IPAD];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// //load from in array in row major and store to shared memory in row major
//// tile[threadIdx.y][threadIdx.x] = in[in_index];
////
//// //wait untill all the threads load the values
//// __syncthreads();
////
//// out[out_index] = tile[i_col][i_row];
//// }
////}
////
////__global__ void transpose_smem_pad_unrolling(int * in, int* out, int nx, int ny)
////{
//// __shared__ int tile[BDIMY*(2 * BDIMX + IPAD)];
////
//// //input index
//// int ix, iy, in_index;
////
//// //output index
//// int i_row, i_col, _1d_index, out_ix, out_iy, out_index;
////
//// //ix and iy calculation for input index
//// ix = 2 * blockDim.x * blockIdx.x + threadIdx.x;
//// iy = blockDim.y * blockIdx.y + threadIdx.y;
////
//// //input index
//// in_index = iy * nx + ix;
////
//// //1D index calculation fro shared memory
//// _1d_index = threadIdx.y * blockDim.x + threadIdx.x;
////
//// //col major row and col index calcuation
//// i_row = _1d_index / blockDim.y;
//// i_col = _1d_index % blockDim.y;
////
//// //coordinate for transpose matrix
//// out_ix = blockIdx.y * blockDim.y + i_col;
//// out_iy = 2 * blockIdx.x * blockDim.x + i_row;
////
//// //output array access in row major format
//// out_index = out_iy * ny + out_ix;
////
//// if (ix < nx && iy < ny)
//// {
//// unsigned int row_idx = threadIdx.y * (blockDim.x * 2 + IPAD) + threadIdx.x;
//// tile[row_idx] = in[in_index];
//// tile[row_idx + BDIMX] = in[in_index + BDIMX];
////
//// // thread synchronization
//// __syncthreads();
////
//// // store two rows to global memory from two columns of shared memory
//// unsigned int col_idx = i_col*(blockDim.x * 2 + IPAD) + i_row;
//// out[out_index] = tile[col_idx];
//// out[out_index + ny*BDIMX] = tile[col_idx + BDIMX];
//// }
////}
////
////int main(int argc, char** argv)
////{
//// //default values for variabless
//// int nx = 1024;
//// int ny = 1024;
//// int block_x = BDIMX;
//// int block_y = BDIMY;
//// int kernel_num = 0;
////
//// //set the variable based on arguments
//// if (argc > 1)
//// nx = 1 << atoi(argv[1]);
//// if (argc > 2)
//// ny = 1 << atoi(argv[2]);
//// if (argc > 3)
//// block_x = 1 << atoi(argv[3]);
//// if (argc > 4)
//// block_y = 1 << atoi(argv[4]);
////
//// int size = nx * ny;
//// int byte_size = sizeof(int*) * size;
////
//// printf("Matrix transpose for %d X % d matrix with block size %d X %d \n", nx, ny, block_x, block_y);
////
//// int * h_mat_array = (int*)malloc(byte_size);
//// int * h_trans_array = (int*)malloc(byte_size);
//// int * h_ref = (int*)malloc(byte_size);
////
//// initialize(h_mat_array, size, INIT_ONE_TO_TEN);
////
//// //matirx transpose in CPU
//// mat_transpose_cpu(h_mat_array, h_trans_array, nx, ny);
////
//// int * d_mat_array, *d_trans_array;
////
//// gpuErrchk(cudaMalloc((void**)&d_mat_array, byte_size));
//// gpuErrchk(cudaMalloc((void**)&d_trans_array, byte_size));
////
//// gpuErrchk(cudaMemcpy(d_mat_array, h_mat_array, byte_size, cudaMemcpyHostToDevice));
//// gpuErrchk(cudaMemset(d_trans_array, 0, byte_size));
////
//// dim3 blocks(block_x, block_y);
//// dim3 grid(nx / block_x, ny / block_y);
////
//// printf("Launching smem kernel \n");
//// transpose_smem << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching benchmark kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_read_raw_write_column_benchmark << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
//// transpose_smem_pad << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// printf("Launching smem padding and unrolling kernel \n");
//// cudaMemset(d_trans_array, 0, byte_size);
////
//// grid.x = grid.x / 2;
////
//// transpose_smem_pad_unrolling << < grid, blocks >> > (d_mat_array, d_trans_array, nx, ny);
//// gpuErrchk(cudaDeviceSynchronize());
////
//// gpuErrchk(cudaMemcpy(h_ref, d_trans_array, byte_size, cudaMemcpyDeviceToHost));
//// compare_arrays(h_ref, h_trans_array, size);
////
//// cudaFree(d_trans_array);
//// cudaFree(d_mat_array);
//// free(h_ref);
//// free(h_trans_array);
//// free(h_mat_array);
////
//// gpuErrchk(cudaDeviceReset());
//// return EXIT_SUCCESS;
////} | .text
.file "test.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000695a7_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void onesc(int *A, int *B){
int ele = threadIdx.x, row=blockIdx.x, no_eles = blockDim.x, no_rows = gridDim.x;
if(row!=0 && ele!=0 && row!=no_rows-1 && ele != no_eles-1){
int cur = A[row*no_eles + ele];
int binaryNum[32], bin=0;
int i = 0;
while (cur > 0) { //find binary equivalent
binaryNum[i] = cur % 2;
cur = cur / 2;
i++;
}
for(int k=0;k<i;k++){ //find ones complement
if(binaryNum[k]==1){
binaryNum[k] = 0;
}
else{
binaryNum[k] = 1;
}
}
for (int j = i - 1; j >= 0; j--) //put to integer element
bin = bin*10 + binaryNum[j];
B[row*no_eles + ele] = bin;
}
else{
B[row*no_eles + ele] = A[row*no_eles + ele];
}
}
int main(){
int *a, *t, m, n;
int *d_a, *d_t;
printf("Enter the value of m: "); scanf("%d",&m);
printf("Enter the value of n: "); scanf("%d",&n);
int size = sizeof(int)*m*n;
a=(int*)malloc(size);
t=(int*)malloc(size);
printf("Enter input matrix: \n");
for(int i=0; i<m*n; i++)
scanf("%d",&a[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
onesc<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("Resultant matrix:\n");
for(int i=0; i<m; i++){
for(int j=0; j<n; j++){
printf("%d ",t[i*n+j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | code for sm_80
Function : _Z5onescPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x80, RZ ; /* 0xffffff8001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R23, R2, c[0x0][0x0], R3 ; /* 0x0000000002177a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.WIDE R4, R23, R4, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x000fca00078e0204 */
/*0080*/ LDG.E R0, [R4.64] ; /* 0x0000000804007981 */
/* 0x000162000c1e1900 */
/*0090*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*00a0*/ ISETP.NE.AND P0, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe20003f05270 */
/*00b0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ BSSY B0, 0x1160 ; /* 0x0000109000007945 */
/* 0x000fe20003800000 */
/*00d0*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe13f */
/*00e0*/ ISETP.EQ.OR P0, PT, R3, RZ, !P0 ; /* 0x000000ff0300720c */
/* 0x000fe20004702670 */
/*00f0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe40000000800 */
/*0100*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe4000fffe13f */
/*0110*/ ISETP.EQ.OR P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fc40008702670 */
/*0120*/ SHF.R.S32.HI R2, RZ, 0x1f, R23 ; /* 0x0000001fff027819 */
/* 0x000fe40000011417 */
/*0130*/ ISETP.EQ.OR P0, PT, R3, UR5, P0 ; /* 0x0000000503007c0c */
/* 0x000fda0008702670 */
/*0140*/ @P0 BRA 0x1150 ; /* 0x0000100000000947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x021fe20003f06270 */
/*0160*/ BSSY B1, 0x220 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fd600078e00ff */
/*0180*/ @!P0 BRA 0x210 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R3, R22, 0x4, R1 ; /* 0x0000000416037824 */
/* 0x000fe200078e0201 */
/*01b0*/ LOP3.LUT R4, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100047812 */
/* 0x000fe400078ec0ff */
/*01c0*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe40000011600 */
/*01d0*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ STL [R3], R4 ; /* 0x0000000403007387 */
/* 0x0001e20000100800 */
/*01f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0200*/ @P0 BRA 0x1a0 ; /* 0xffffff9000000947 */
/* 0x001fea000383ffff */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*0230*/ BSSY B3, 0xa00 ; /* 0x000007c000037945 */
/* 0x000fd80003800000 */
/*0240*/ @!P0 BRA 0x9f0 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R0, R22.reuse, -0x1, RZ ; /* 0xffffffff16007810 */
/* 0x040fe20007ffe0ff */
/*0260*/ BSSY B2, 0x940 ; /* 0x000006d000027945 */
/* 0x000fe20003800000 */
/*0270*/ LOP3.LUT R21, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316157812 */
/* 0x000fe200078ec0ff */
/*0280*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*02a0*/ @!P0 BRA 0x930 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.IADD R3, R22, 0x1, -R21 ; /* 0x0000000116037824 */
/* 0x000fe200078e0a15 */
/*02c0*/ BSSY B1, 0x840 ; /* 0x0000057000017945 */
/* 0x000fe20003800000 */
/*02d0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0001 */
/*02f0*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0300*/ @!P0 BRA 0x830 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0320*/ BSSY B4, 0x640 ; /* 0x0000031000047945 */
/* 0x000fe20003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0340*/ @!P1 BRA 0x630 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ LDL.128 R4, [R0] ; /* 0x0000000000047983 */
/* 0x000ea80000100c00 */
/*0370*/ LDL.128 R16, [R0+0x10] ; /* 0x0000100000107983 */
/* 0x000ee80000100c00 */
/*0380*/ LDL.128 R12, [R0+0x30] ; /* 0x00003000000c7983 */
/* 0x000f280000100c00 */
/*0390*/ LDL.128 R8, [R0+0x20] ; /* 0x0000200000087983 */
/* 0x000f620000100c00 */
/*03a0*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc40007ffe0ff */
/*03b0*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.NE.AND P3, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x004fe40003f65270 */
/*03d0*/ ISETP.NE.AND P6, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003fc5270 */
/*03e0*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x008fe40003f25270 */
/*03f0*/ SEL R7, RZ, 0x1, !P3 ; /* 0x00000001ff077807 */
/* 0x000fe40005800000 */
/*0400*/ SEL R6, RZ, 0x1, !P6 ; /* 0x00000001ff067807 */
/* 0x000fc40007000000 */
/*0410*/ SEL R16, RZ, 0x1, !P1 ; /* 0x00000001ff107807 */
/* 0x000fe40004800000 */
/*0420*/ ISETP.NE.AND P3, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fe40003f65270 */
/*0430*/ ISETP.NE.AND P6, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe40003fc5270 */
/*0440*/ ISETP.NE.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x010fe40003f25270 */
/*0450*/ SEL R19, RZ, 0x1, !P6 ; /* 0x00000001ff137807 */
/* 0x000fe40007000000 */
/*0460*/ SEL R18, RZ, 0x1, !P3 ; /* 0x00000001ff127807 */
/* 0x000fc40005800000 */
/*0470*/ SEL R13, RZ, 0x1, !P1 ; /* 0x00000001ff0d7807 */
/* 0x000fe40004800000 */
/*0480*/ ISETP.NE.AND P5, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003fa5270 */
/*0490*/ ISETP.NE.AND P4, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f85270 */
/*04a0*/ ISETP.NE.AND P2, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fe40003f45270 */
/*04b0*/ ISETP.NE.AND P6, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fe40003fc5270 */
/*04c0*/ ISETP.NE.AND P3, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc40003f65270 */
/*04d0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*04e0*/ SEL R5, RZ, 0x1, !P4 ; /* 0x00000001ff057807 */
/* 0x000fe40006000000 */
/*04f0*/ SEL R4, RZ, 0x1, !P5 ; /* 0x00000001ff047807 */
/* 0x000fe40006800000 */
/*0500*/ SEL R17, RZ, 0x1, !P2 ; /* 0x00000001ff117807 */
/* 0x000fe40005000000 */
/*0510*/ SEL R11, RZ, 0x1, !P3 ; /* 0x00000001ff0b7807 */
/* 0x000fe40005800000 */
/*0520*/ SEL R10, RZ, 0x1, !P6 ; /* 0x00000001ff0a7807 */
/* 0x000fc40007000000 */
/*0530*/ ISETP.NE.AND P4, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f85270 */
/*0540*/ ISETP.NE.AND P5, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003fa5270 */
/*0550*/ ISETP.NE.AND P2, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f45270 */
/*0560*/ ISETP.NE.AND P3, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe40003f65270 */
/*0570*/ ISETP.NE.AND P6, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003fc5270 */
/*0580*/ SEL R9, RZ, 0x1, !P5 ; /* 0x00000001ff097807 */
/* 0x000fc40006800000 */
/*0590*/ SEL R8, RZ, 0x1, !P4 ; /* 0x00000001ff087807 */
/* 0x000fe40006000000 */
/*05a0*/ SEL R15, RZ, 0x1, !P3 ; /* 0x00000001ff0f7807 */
/* 0x000fe40005800000 */
/*05b0*/ SEL R14, RZ, 0x1, !P6 ; /* 0x00000001ff0e7807 */
/* 0x000fe40007000000 */
/*05c0*/ SEL R12, RZ, 0x1, !P2 ; /* 0x00000001ff0c7807 */
/* 0x000fe20005000000 */
/*05d0*/ STL.128 [R0], R4 ; /* 0x0000000400007387 */
/* 0x000fe80000100c00 */
/*05e0*/ STL.128 [R0+0x10], R16 ; /* 0x0000101000007387 */
/* 0x000fe80000100c00 */
/*05f0*/ STL.128 [R0+0x20], R8 ; /* 0x0000200800007387 */
/* 0x000fe80000100c00 */
/*0600*/ STL.128 [R0+0x30], R12 ; /* 0x0000300c00007387 */
/* 0x0001e40000100c00 */
/*0610*/ IADD3 R0, R0, 0x40, RZ ; /* 0x0000004000007810 */
/* 0x001fe20007ffe0ff */
/*0620*/ @P1 BRA 0x360 ; /* 0xfffffd3000001947 */
/* 0x000fea000383ffff */
/*0630*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fe20003f24270 */
/*0650*/ BSSY B4, 0x800 ; /* 0x000001a000047945 */
/* 0x000fd80003800000 */
/*0660*/ @!P1 BRA 0x7f0 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*0670*/ LDL.128 R8, [R0] ; /* 0x0000000000087983 */
/* 0x000ea80000100c00 */
/*0680*/ LDL.128 R4, [R0+0x10] ; /* 0x0000100000047983 */
/* 0x000ee20000100c00 */
/*0690*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.NE.AND P6, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fe40003fc5270 */
/*06c0*/ ISETP.NE.AND P3, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc40003f65270 */
/*06d0*/ SEL R11, RZ, 0x1, !P6 ; /* 0x00000001ff0b7807 */
/* 0x000fe40007000000 */
/*06e0*/ ISETP.NE.AND P4, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f85270 */
/*06f0*/ ISETP.NE.AND P5, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003fa5270 */
/*0700*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x008fe40003f05270 */
/*0710*/ ISETP.NE.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f25270 */
/*0720*/ ISETP.NE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc40003f45270 */
/*0730*/ ISETP.NE.AND P6, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003fc5270 */
/*0740*/ SEL R10, RZ, 0x1, !P5 ; /* 0x00000001ff0a7807 */
/* 0x000fe40006800000 */
/*0750*/ SEL R9, RZ, 0x1, !P4 ; /* 0x00000001ff097807 */
/* 0x000fe40006000000 */
/*0760*/ SEL R8, RZ, 0x1, !P3 ; /* 0x00000001ff087807 */
/* 0x000fe40005800000 */
/*0770*/ SEL R7, RZ, 0x1, !P6 ; /* 0x00000001ff077807 */
/* 0x000fe40007000000 */
/*0780*/ SEL R6, RZ, 0x1, !P2 ; /* 0x00000001ff067807 */
/* 0x000fe20005000000 */
/*0790*/ STL.128 [R0], R8 ; /* 0x0000000800007387 */
/* 0x000fe20000100c00 */
/*07a0*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fc40004800000 */
/*07b0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe40004000000 */
/*07c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*07d0*/ STL.128 [R0+0x10], R4 ; /* 0x0000100400007387 */
/* 0x0001e40000100c00 */
/*07e0*/ IADD3 R0, R0, 0x20, RZ ; /* 0x0000002000007810 */
/* 0x001fc60007ffe0ff */
/*07f0*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0810*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*0820*/ @!P0 BRA 0x930 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ LDL.128 R4, [R0] ; /* 0x0000000000047983 */
/* 0x000ea20000100c00 */
/*0850*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*0870*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fe40003f05270 */
/*0880*/ ISETP.NE.AND P3, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f65270 */
/*0890*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc40004000000 */
/*08a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*08b0*/ ISETP.NE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f45270 */
/*08c0*/ ISETP.NE.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f25270 */
/*08d0*/ SEL R7, RZ, 0x1, !P3 ; /* 0x00000001ff077807 */
/* 0x000fe40005800000 */
/*08e0*/ SEL R6, RZ, 0x1, !P2 ; /* 0x00000001ff067807 */
/* 0x000fe40005000000 */
/*08f0*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fca0004800000 */
/*0900*/ STL.128 [R0], R4 ; /* 0x0000000400007387 */
/* 0x0001e40000100c00 */
/*0910*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x001fe20007ffe0ff */
/*0920*/ @P0 BRA 0x840 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0930*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0940*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*0950*/ @!P0 BRA 0x9f0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0960*/ IMAD R3, R20, 0x4, R1 ; /* 0x0000000414037824 */
/* 0x000fca00078e0201 */
/*0970*/ LDL R0, [R3] ; /* 0x0000000003007983 */
/* 0x000ea20000100800 */
/*0980*/ IADD3 R21, R21, -0x1, RZ ; /* 0xffffffff15157810 */
/* 0x000fe40007ffe0ff */
/*0990*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fc80003f05270 */
/*09a0*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fe40004000000 */
/*09b0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003f05270 */
/*09c0*/ STL [R3], R0 ; /* 0x0000000003007387 */
/* 0x0001e40000100800 */
/*09d0*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x001fd00007ffe0ff */
/*09e0*/ @P0 BRA 0x970 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*09f0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f06270 */
/*0a10*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*0a20*/ @!P0 BRA 0x1150 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0a30*/ LOP3.LUT R0, RZ, R22, RZ, 0x33, !PT ; /* 0x00000016ff007212 */
/* 0x000fe200078e33ff */
/*0a40*/ BSSY B1, 0x10b0 ; /* 0x0000066000017945 */
/* 0x000fe60003800000 */
/*0a50*/ IMNMX R3, R0, -0x2, !PT ; /* 0xfffffffe00037817 */
/* 0x000fca0007800200 */
/*0a60*/ IMAD.IADD R4, R22, 0x1, R3 ; /* 0x0000000116047824 */
/* 0x000fca00078e0203 */
/*0a70*/ IADD3 R0, R4.reuse, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x040fe40007ffe0ff */
/*0a80*/ IADD3 R3, R4, 0x2, RZ ; /* 0x0000000204037810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0aa0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0ab0*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fd600078ec0ff */
/*0ac0*/ @!P0 BRA 0x10a0 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.IADD R5, R4, 0x1, -R3 ; /* 0x0000000104057824 */
/* 0x000fe200078e0a03 */
/*0ae0*/ IADD3 R4, R22, -0x1, RZ ; /* 0xffffffff16047810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ BSSY B2, 0xfd0 ; /* 0x000004d000027945 */
/* 0x000fe20003800000 */
/*0b00*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0b10*/ ISETP.GT.AND P0, PT, R5, -0x2, PT ; /* 0xfffffffe0500780c */
/* 0x000fe20003f04270 */
/*0b20*/ IMAD R4, R4, 0x4, R1 ; /* 0x0000000404047824 */
/* 0x000fd800078e0201 */
/*0b30*/ @!P0 BRA 0xfc0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0b40*/ IADD3 R6, R5, 0x2, RZ ; /* 0x0000000205067810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ BSSY B3, 0xe00 ; /* 0x000002a000037945 */
/* 0x000fe20003800000 */
/*0b60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0b70*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fda0003f24270 */
/*0b80*/ @!P1 BRA 0xdf0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0b90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0ba0*/ LDL R17, [R4] ; /* 0x0000000004117983 */
/* 0x0000a80000100800 */
/*0bb0*/ LDL R16, [R4+-0x4] ; /* 0xfffffc0004107983 */
/* 0x0000e80000100800 */
/*0bc0*/ LDL R19, [R4+-0x8] ; /* 0xfffff80004137983 */
/* 0x0001280000100800 */
/*0bd0*/ LDL R21, [R4+-0xc] ; /* 0xfffff40004157983 */
/* 0x0001680000100800 */
/*0be0*/ LDL R25, [R4+-0x10] ; /* 0xfffff00004197983 */
/* 0x0001680000100800 */
/*0bf0*/ LDL R27, [R4+-0x14] ; /* 0xffffec00041b7983 */
/* 0x0001680000100800 */
/*0c00*/ LDL R15, [R4+-0x18] ; /* 0xffffe800040f7983 */
/* 0x0001680000100800 */
/*0c10*/ LDL R14, [R4+-0x1c] ; /* 0xffffe400040e7983 */
/* 0x0001680000100800 */
/*0c20*/ LDL R13, [R4+-0x20] ; /* 0xffffe000040d7983 */
/* 0x0001680000100800 */
/*0c30*/ LDL R12, [R4+-0x24] ; /* 0xffffdc00040c7983 */
/* 0x0001680000100800 */
/*0c40*/ LDL R11, [R4+-0x28] ; /* 0xffffd800040b7983 */
/* 0x0001680000100800 */
/*0c50*/ LDL R10, [R4+-0x2c] ; /* 0xffffd400040a7983 */
/* 0x0001680000100800 */
/*0c60*/ LDL R9, [R4+-0x30] ; /* 0xffffd00004097983 */
/* 0x0001680000100800 */
/*0c70*/ LDL R7, [R4+-0x34] ; /* 0xffffcc0004077983 */
/* 0x0001680000100800 */
/*0c80*/ LDL R8, [R4+-0x38] ; /* 0xffffc80004087983 */
/* 0x0001680000100800 */
/*0c90*/ LDL R6, [R4+-0x3c] ; /* 0xffffc40004067983 */
/* 0x0001620000100800 */
/*0ca0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc40007ffe0ff */
/*0cb0*/ IADD3 R22, R22, -0x10, RZ ; /* 0xfffffff016167810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ ISETP.GT.AND P1, PT, R5, 0xa, PT ; /* 0x0000000a0500780c */
/* 0x000fe40003f24270 */
/*0cd0*/ IADD3 R4, R4, -0x40, RZ ; /* 0xffffffc004047810 */
/* 0x001fe20007ffe0ff */
/*0ce0*/ IMAD R17, R0, 0xa, R17 ; /* 0x0000000a00117824 */
/* 0x004fc800078e0211 */
/*0cf0*/ IMAD R16, R17, 0xa, R16 ; /* 0x0000000a11107824 */
/* 0x008fc800078e0210 */
/*0d00*/ IMAD R16, R16, 0xa, R19 ; /* 0x0000000a10107824 */
/* 0x010fc800078e0213 */
/*0d10*/ IMAD R16, R16, 0xa, R21 ; /* 0x0000000a10107824 */
/* 0x020fc800078e0215 */
/*0d20*/ IMAD R16, R16, 0xa, R25 ; /* 0x0000000a10107824 */
/* 0x000fc800078e0219 */
/*0d30*/ IMAD R16, R16, 0xa, R27 ; /* 0x0000000a10107824 */
/* 0x000fc800078e021b */
/*0d40*/ IMAD R15, R16, 0xa, R15 ; /* 0x0000000a100f7824 */
/* 0x000fc800078e020f */
/*0d50*/ IMAD R14, R15, 0xa, R14 ; /* 0x0000000a0f0e7824 */
/* 0x000fc800078e020e */
/*0d60*/ IMAD R13, R14, 0xa, R13 ; /* 0x0000000a0e0d7824 */
/* 0x000fc800078e020d */
/*0d70*/ IMAD R12, R13, 0xa, R12 ; /* 0x0000000a0d0c7824 */
/* 0x000fc800078e020c */
/*0d80*/ IMAD R11, R12, 0xa, R11 ; /* 0x0000000a0c0b7824 */
/* 0x000fc800078e020b */
/*0d90*/ IMAD R10, R11, 0xa, R10 ; /* 0x0000000a0b0a7824 */
/* 0x000fc800078e020a */
/*0da0*/ IMAD R10, R10, 0xa, R9 ; /* 0x0000000a0a0a7824 */
/* 0x000fc800078e0209 */
/*0db0*/ IMAD R7, R10, 0xa, R7 ; /* 0x0000000a0a077824 */
/* 0x000fc800078e0207 */
/*0dc0*/ IMAD R7, R7, 0xa, R8 ; /* 0x0000000a07077824 */
/* 0x000fc800078e0208 */
/*0dd0*/ IMAD R0, R7, 0xa, R6 ; /* 0x0000000a07007824 */
/* 0x000fe200078e0206 */
/*0de0*/ @P1 BRA 0xba0 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*0df0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0e00*/ IADD3 R6, R5, 0x2, RZ ; /* 0x0000000205067810 */
/* 0x000fe20007ffe0ff */
/*0e10*/ BSSY B3, 0xf90 ; /* 0x0000017000037945 */
/* 0x000fe60003800000 */
/*0e20*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0e30*/ @!P1 BRA 0xf80 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0e40*/ LDL R7, [R4] ; /* 0x0000000004077983 */
/* 0x0000a80000100800 */
/*0e50*/ LDL R6, [R4+-0x4] ; /* 0xfffffc0004067983 */
/* 0x0000e80000100800 */
/*0e60*/ LDL R9, [R4+-0x8] ; /* 0xfffff80004097983 */
/* 0x0001280000100800 */
/*0e70*/ LDL R11, [R4+-0xc] ; /* 0xfffff400040b7983 */
/* 0x0001680000100800 */
/*0e80*/ LDL R13, [R4+-0x10] ; /* 0xfffff000040d7983 */
/* 0x0001680000100800 */
/*0e90*/ LDL R15, [R4+-0x14] ; /* 0xffffec00040f7983 */
/* 0x0001680000100800 */
/*0ea0*/ LDL R17, [R4+-0x18] ; /* 0xffffe80004117983 */
/* 0x0001680000100800 */
/*0eb0*/ LDL R19, [R4+-0x1c] ; /* 0xffffe40004137983 */
/* 0x0001620000100800 */
/*0ec0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0ed0*/ IADD3 R22, R22, -0x8, RZ ; /* 0xfffffff816167810 */
/* 0x000fe40007ffe0ff */
/*0ee0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0ef0*/ IADD3 R4, R4, -0x20, RZ ; /* 0xffffffe004047810 */
/* 0x001fe20007ffe0ff */
/*0f00*/ IMAD R7, R0, 0xa, R7 ; /* 0x0000000a00077824 */
/* 0x004fc800078e0207 */
/*0f10*/ IMAD R6, R7, 0xa, R6 ; /* 0x0000000a07067824 */
/* 0x008fc800078e0206 */
/*0f20*/ IMAD R6, R6, 0xa, R9 ; /* 0x0000000a06067824 */
/* 0x010fc800078e0209 */
/*0f30*/ IMAD R6, R6, 0xa, R11 ; /* 0x0000000a06067824 */
/* 0x020fc800078e020b */
/*0f40*/ IMAD R6, R6, 0xa, R13 ; /* 0x0000000a06067824 */
/* 0x000fc800078e020d */
/*0f50*/ IMAD R6, R6, 0xa, R15 ; /* 0x0000000a06067824 */
/* 0x000fc800078e020f */
/*0f60*/ IMAD R6, R6, 0xa, R17 ; /* 0x0000000a06067824 */
/* 0x000fc800078e0211 */
/*0f70*/ IMAD R0, R6, 0xa, R19 ; /* 0x0000000a06007824 */
/* 0x000fe400078e0213 */
/*0f80*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0f90*/ ISETP.NE.OR P0, PT, R5, -0x2, P0 ; /* 0xfffffffe0500780c */
/* 0x000fda0000705670 */
/*0fa0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0fb0*/ @!P0 BRA 0x10a0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0fc0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fd0*/ LDL R7, [R4] ; /* 0x0000000004077983 */
/* 0x0000a80000100800 */
/*0fe0*/ LDL R6, [R4+-0x4] ; /* 0xfffffc0004067983 */
/* 0x0000e80000100800 */
/*0ff0*/ LDL R9, [R4+-0x8] ; /* 0xfffff80004097983 */
/* 0x0001280000100800 */
/*1000*/ LDL R11, [R4+-0xc] ; /* 0xfffff400040b7983 */
/* 0x0001620000100800 */
/*1010*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc40007ffe0ff */
/*1020*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x000fe40007ffe0ff */
/*1030*/ ISETP.NE.AND P0, PT, R5, -0x2, PT ; /* 0xfffffffe0500780c */
/* 0x000fe40003f05270 */
/*1040*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x001fe20007ffe0ff */
/*1050*/ IMAD R7, R0, 0xa, R7 ; /* 0x0000000a00077824 */
/* 0x004fc800078e0207 */
/*1060*/ IMAD R6, R7, 0xa, R6 ; /* 0x0000000a07067824 */
/* 0x008fc800078e0206 */
/*1070*/ IMAD R6, R6, 0xa, R9 ; /* 0x0000000a06067824 */
/* 0x010fc800078e0209 */
/*1080*/ IMAD R0, R6, 0xa, R11 ; /* 0x0000000a06007824 */
/* 0x020fe200078e020b */
/*1090*/ @P0 BRA 0xfd0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*10a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*10c0*/ @!P0 BRA 0x1150 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*10d0*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fca0007ffe0ff */
/*10e0*/ IMAD R22, R22, 0x4, R1 ; /* 0x0000000416167824 */
/* 0x000fca00078e0201 */
/*10f0*/ LDL R5, [R22] ; /* 0x0000000016057983 */
/* 0x0000a20000100800 */
/*1100*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fc80007ffe0ff */
/*1110*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*1120*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x001fe20007ffe0ff */
/*1130*/ IMAD R0, R0, 0xa, R5 ; /* 0x0000000a00007824 */
/* 0x004fd400078e0205 */
/*1140*/ @P0 BRA 0x10f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*1150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*1160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*1170*/ LEA R4, P0, R23, c[0x0][0x168], 0x2 ; /* 0x00005a0017047a11 */
/* 0x000fc800078010ff */
/*1180*/ LEA.HI.X R5, R23, c[0x0][0x16c], R2, 0x2, P0 ; /* 0x00005b0017057a11 */
/* 0x000fca00000f1402 */
/*1190*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x020fe2000c101908 */
/*11a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*11b0*/ BRA 0x11b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void onesc(int *A, int *B){
int ele = threadIdx.x, row=blockIdx.x, no_eles = blockDim.x, no_rows = gridDim.x;
if(row!=0 && ele!=0 && row!=no_rows-1 && ele != no_eles-1){
int cur = A[row*no_eles + ele];
int binaryNum[32], bin=0;
int i = 0;
while (cur > 0) { //find binary equivalent
binaryNum[i] = cur % 2;
cur = cur / 2;
i++;
}
for(int k=0;k<i;k++){ //find ones complement
if(binaryNum[k]==1){
binaryNum[k] = 0;
}
else{
binaryNum[k] = 1;
}
}
for (int j = i - 1; j >= 0; j--) //put to integer element
bin = bin*10 + binaryNum[j];
B[row*no_eles + ele] = bin;
}
else{
B[row*no_eles + ele] = A[row*no_eles + ele];
}
}
int main(){
int *a, *t, m, n;
int *d_a, *d_t;
printf("Enter the value of m: "); scanf("%d",&m);
printf("Enter the value of n: "); scanf("%d",&n);
int size = sizeof(int)*m*n;
a=(int*)malloc(size);
t=(int*)malloc(size);
printf("Enter input matrix: \n");
for(int i=0; i<m*n; i++)
scanf("%d",&a[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
onesc<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("Resultant matrix:\n");
for(int i=0; i<m; i++){
for(int j=0; j<n; j++){
printf("%d ",t[i*n+j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | .file "tmpxft_000b1a41_00000000-6_CUDA_MatrixOnesComplement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5onescPiS_PiS_
.type _Z26__device_stub__Z5onescPiS_PiS_, @function
_Z26__device_stub__Z5onescPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5onescPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5onescPiS_PiS_, .-_Z26__device_stub__Z5onescPiS_PiS_
.globl _Z5onescPiS_
.type _Z5onescPiS_, @function
_Z5onescPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5onescPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5onescPiS_, .-_Z5onescPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the value of m: "
.LC1:
.string "%d"
.LC2:
.string "Enter the value of n: "
.LC3:
.string "Enter input matrix: \n"
.LC4:
.string "Resultant matrix:\n"
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %r13d
imull 8(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .L12
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r14
.L13:
movq %rbp, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cmpl %ebx, %eax
jg .L13
.L12:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L14:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r14
cmpl $0, 8(%rsp)
jg .L15
.L16:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z5onescPiS_PiS_
jmp .L14
.L17:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 12(%rsp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jle .L16
.L15:
movl 12(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5onescPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5onescPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void onesc(int *A, int *B){
int ele = threadIdx.x, row=blockIdx.x, no_eles = blockDim.x, no_rows = gridDim.x;
if(row!=0 && ele!=0 && row!=no_rows-1 && ele != no_eles-1){
int cur = A[row*no_eles + ele];
int binaryNum[32], bin=0;
int i = 0;
while (cur > 0) { //find binary equivalent
binaryNum[i] = cur % 2;
cur = cur / 2;
i++;
}
for(int k=0;k<i;k++){ //find ones complement
if(binaryNum[k]==1){
binaryNum[k] = 0;
}
else{
binaryNum[k] = 1;
}
}
for (int j = i - 1; j >= 0; j--) //put to integer element
bin = bin*10 + binaryNum[j];
B[row*no_eles + ele] = bin;
}
else{
B[row*no_eles + ele] = A[row*no_eles + ele];
}
}
int main(){
int *a, *t, m, n;
int *d_a, *d_t;
printf("Enter the value of m: "); scanf("%d",&m);
printf("Enter the value of n: "); scanf("%d",&n);
int size = sizeof(int)*m*n;
a=(int*)malloc(size);
t=(int*)malloc(size);
printf("Enter input matrix: \n");
for(int i=0; i<m*n; i++)
scanf("%d",&a[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
onesc<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("Resultant matrix:\n");
for(int i=0; i<m; i++){
for(int j=0; j<n; j++){
printf("%d ",t[i*n+j]);
}
printf("\n");
}
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void onesc(int *A, int *B){
int ele = threadIdx.x, row=blockIdx.x, no_eles = blockDim.x, no_rows = gridDim.x;
if(row!=0 && ele!=0 && row!=no_rows-1 && ele != no_eles-1){
int cur = A[row*no_eles + ele];
int binaryNum[32], bin=0;
int i = 0;
while (cur > 0) { //find binary equivalent
binaryNum[i] = cur % 2;
cur = cur / 2;
i++;
}
for(int k=0;k<i;k++){ //find ones complement
if(binaryNum[k]==1){
binaryNum[k] = 0;
}
else{
binaryNum[k] = 1;
}
}
for (int j = i - 1; j >= 0; j--) //put to integer element
bin = bin*10 + binaryNum[j];
B[row*no_eles + ele] = bin;
}
else{
B[row*no_eles + ele] = A[row*no_eles + ele];
}
}
int main(){
int *a, *t, m, n;
int *d_a, *d_t;
printf("Enter the value of m: "); scanf("%d",&m);
printf("Enter the value of n: "); scanf("%d",&n);
int size = sizeof(int)*m*n;
a=(int*)malloc(size);
t=(int*)malloc(size);
printf("Enter input matrix: \n");
for(int i=0; i<m*n; i++)
scanf("%d",&a[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
onesc<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("Resultant matrix:\n");
for(int i=0; i<m; i++){
for(int j=0; j<n; j++){
printf("%d ",t[i*n+j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void onesc(int *A, int *B){
int ele = threadIdx.x, row=blockIdx.x, no_eles = blockDim.x, no_rows = gridDim.x;
if(row!=0 && ele!=0 && row!=no_rows-1 && ele != no_eles-1){
int cur = A[row*no_eles + ele];
int binaryNum[32], bin=0;
int i = 0;
while (cur > 0) { //find binary equivalent
binaryNum[i] = cur % 2;
cur = cur / 2;
i++;
}
for(int k=0;k<i;k++){ //find ones complement
if(binaryNum[k]==1){
binaryNum[k] = 0;
}
else{
binaryNum[k] = 1;
}
}
for (int j = i - 1; j >= 0; j--) //put to integer element
bin = bin*10 + binaryNum[j];
B[row*no_eles + ele] = bin;
}
else{
B[row*no_eles + ele] = A[row*no_eles + ele];
}
}
int main(){
int *a, *t, m, n;
int *d_a, *d_t;
printf("Enter the value of m: "); scanf("%d",&m);
printf("Enter the value of n: "); scanf("%d",&n);
int size = sizeof(int)*m*n;
a=(int*)malloc(size);
t=(int*)malloc(size);
printf("Enter input matrix: \n");
for(int i=0; i<m*n; i++)
scanf("%d",&a[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
onesc<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("Resultant matrix:\n");
for(int i=0; i<m; i++){
for(int j=0; j<n; j++){
printf("%d ",t[i*n+j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5onescPiS_
.globl _Z5onescPiS_
.p2align 8
.type _Z5onescPiS_,@function
_Z5onescPiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lg_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cselect_b32 s1, -1, 0
s_add_i32 s0, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v0
global_load_b32 v3, v[3:4], off
s_and_b32 s1, s1, vcc_lo
s_cmp_lg_u32 s15, s0
s_cselect_b32 s0, -1, 0
s_add_i32 s2, s2, -1
s_and_b32 s0, s1, s0
v_cmp_ne_u32_e32 vcc_lo, s2, v0
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s0, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execnz .LBB0_15
.LBB0_2:
s_endpgm
.LBB0_3:
v_mov_b32_e32 v0, 0
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v4, 16
s_mov_b32 s2, 0
s_mov_b32 s3, 0
.LBB0_5:
v_lshrrev_b32_e32 v5, 1, v3
v_and_b32_e32 v0, 1, v3
s_add_i32 s3, s3, 1
v_cmp_gt_u32_e32 vcc_lo, 2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v3, v5
scratch_store_b32 v4, v0, off
v_add_nc_u32_e32 v4, 4, v4
v_mov_b32_e32 v0, s3
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s2
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s2, 0
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v3, 16 :: v_dual_mov_b32 v4, v0
.LBB0_9:
scratch_load_b32 v5, v3, off
v_add_nc_u32_e32 v4, -1, v4
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v5
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
scratch_store_b32 v3, v5, off
v_add_nc_u32_e32 v3, 4, v3
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_9
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v3, 0
s_mov_b32 s2, 0
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v3, 2, v0
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v3, 16, -4
v_mov_b32_e32 v3, 0
.LBB0_12:
scratch_load_b32 v5, v4, off
v_add_nc_u32_e32 v4, -4, v4
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v3, 10, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, v6 :: v_dual_add_nc_u32 v0, -1, v0
v_cmp_gt_i32_e32 vcc_lo, 2, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s2
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
.LBB0_15:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5onescPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 144
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5onescPiS_, .Lfunc_end0-_Z5onescPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5onescPiS_
.private_segment_fixed_size: 144
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5onescPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void onesc(int *A, int *B){
int ele = threadIdx.x, row=blockIdx.x, no_eles = blockDim.x, no_rows = gridDim.x;
if(row!=0 && ele!=0 && row!=no_rows-1 && ele != no_eles-1){
int cur = A[row*no_eles + ele];
int binaryNum[32], bin=0;
int i = 0;
while (cur > 0) { //find binary equivalent
binaryNum[i] = cur % 2;
cur = cur / 2;
i++;
}
for(int k=0;k<i;k++){ //find ones complement
if(binaryNum[k]==1){
binaryNum[k] = 0;
}
else{
binaryNum[k] = 1;
}
}
for (int j = i - 1; j >= 0; j--) //put to integer element
bin = bin*10 + binaryNum[j];
B[row*no_eles + ele] = bin;
}
else{
B[row*no_eles + ele] = A[row*no_eles + ele];
}
}
int main(){
int *a, *t, m, n;
int *d_a, *d_t;
printf("Enter the value of m: "); scanf("%d",&m);
printf("Enter the value of n: "); scanf("%d",&n);
int size = sizeof(int)*m*n;
a=(int*)malloc(size);
t=(int*)malloc(size);
printf("Enter input matrix: \n");
for(int i=0; i<m*n; i++)
scanf("%d",&a[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
onesc<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("Resultant matrix:\n");
for(int i=0; i<m; i++){
for(int j=0; j<n; j++){
printf("%d ",t[i*n+j]);
}
printf("\n");
}
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.file "CUDA_MatrixOnesComplement.hip"
.globl _Z20__device_stub__onescPiS_ # -- Begin function _Z20__device_stub__onescPiS_
.p2align 4, 0x90
.type _Z20__device_stub__onescPiS_,@function
_Z20__device_stub__onescPiS_: # @_Z20__device_stub__onescPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5onescPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__onescPiS_, .Lfunc_end0-_Z20__device_stub__onescPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r12
cmpq %rcx, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5onescPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.6: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge31
# in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_11
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_10
# %bb.8: # %.lr.ph30.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph30
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_9
jmp .LBB1_10
.LBB1_11: # %._crit_edge33
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5onescPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5onescPiS_,@object # @_Z5onescPiS_
.section .rodata,"a",@progbits
.globl _Z5onescPiS_
.p2align 3, 0x0
_Z5onescPiS_:
.quad _Z20__device_stub__onescPiS_
.size _Z5onescPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the value of m: "
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter the value of n: "
.size .L.str.2, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5onescPiS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter input matrix: "
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Resultant matrix:"
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__onescPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5onescPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5onescPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x80, RZ ; /* 0xffffff8001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R23, R2, c[0x0][0x0], R3 ; /* 0x0000000002177a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.WIDE R4, R23, R4, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x000fca00078e0204 */
/*0080*/ LDG.E R0, [R4.64] ; /* 0x0000000804007981 */
/* 0x000162000c1e1900 */
/*0090*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*00a0*/ ISETP.NE.AND P0, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe20003f05270 */
/*00b0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ BSSY B0, 0x1160 ; /* 0x0000109000007945 */
/* 0x000fe20003800000 */
/*00d0*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe13f */
/*00e0*/ ISETP.EQ.OR P0, PT, R3, RZ, !P0 ; /* 0x000000ff0300720c */
/* 0x000fe20004702670 */
/*00f0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe40000000800 */
/*0100*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe4000fffe13f */
/*0110*/ ISETP.EQ.OR P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fc40008702670 */
/*0120*/ SHF.R.S32.HI R2, RZ, 0x1f, R23 ; /* 0x0000001fff027819 */
/* 0x000fe40000011417 */
/*0130*/ ISETP.EQ.OR P0, PT, R3, UR5, P0 ; /* 0x0000000503007c0c */
/* 0x000fda0008702670 */
/*0140*/ @P0 BRA 0x1150 ; /* 0x0000100000000947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x021fe20003f06270 */
/*0160*/ BSSY B1, 0x220 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fd600078e00ff */
/*0180*/ @!P0 BRA 0x210 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R3, R22, 0x4, R1 ; /* 0x0000000416037824 */
/* 0x000fe200078e0201 */
/*01b0*/ LOP3.LUT R4, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100047812 */
/* 0x000fe400078ec0ff */
/*01c0*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe40000011600 */
/*01d0*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ STL [R3], R4 ; /* 0x0000000403007387 */
/* 0x0001e20000100800 */
/*01f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0200*/ @P0 BRA 0x1a0 ; /* 0xffffff9000000947 */
/* 0x001fea000383ffff */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*0230*/ BSSY B3, 0xa00 ; /* 0x000007c000037945 */
/* 0x000fd80003800000 */
/*0240*/ @!P0 BRA 0x9f0 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R0, R22.reuse, -0x1, RZ ; /* 0xffffffff16007810 */
/* 0x040fe20007ffe0ff */
/*0260*/ BSSY B2, 0x940 ; /* 0x000006d000027945 */
/* 0x000fe20003800000 */
/*0270*/ LOP3.LUT R21, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316157812 */
/* 0x000fe200078ec0ff */
/*0280*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*02a0*/ @!P0 BRA 0x930 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.IADD R3, R22, 0x1, -R21 ; /* 0x0000000116037824 */
/* 0x000fe200078e0a15 */
/*02c0*/ BSSY B1, 0x840 ; /* 0x0000057000017945 */
/* 0x000fe20003800000 */
/*02d0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0001 */
/*02f0*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0300*/ @!P0 BRA 0x830 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0320*/ BSSY B4, 0x640 ; /* 0x0000031000047945 */
/* 0x000fe20003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0340*/ @!P1 BRA 0x630 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ LDL.128 R4, [R0] ; /* 0x0000000000047983 */
/* 0x000ea80000100c00 */
/*0370*/ LDL.128 R16, [R0+0x10] ; /* 0x0000100000107983 */
/* 0x000ee80000100c00 */
/*0380*/ LDL.128 R12, [R0+0x30] ; /* 0x00003000000c7983 */
/* 0x000f280000100c00 */
/*0390*/ LDL.128 R8, [R0+0x20] ; /* 0x0000200000087983 */
/* 0x000f620000100c00 */
/*03a0*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc40007ffe0ff */
/*03b0*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.NE.AND P3, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x004fe40003f65270 */
/*03d0*/ ISETP.NE.AND P6, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003fc5270 */
/*03e0*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x008fe40003f25270 */
/*03f0*/ SEL R7, RZ, 0x1, !P3 ; /* 0x00000001ff077807 */
/* 0x000fe40005800000 */
/*0400*/ SEL R6, RZ, 0x1, !P6 ; /* 0x00000001ff067807 */
/* 0x000fc40007000000 */
/*0410*/ SEL R16, RZ, 0x1, !P1 ; /* 0x00000001ff107807 */
/* 0x000fe40004800000 */
/*0420*/ ISETP.NE.AND P3, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fe40003f65270 */
/*0430*/ ISETP.NE.AND P6, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe40003fc5270 */
/*0440*/ ISETP.NE.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x010fe40003f25270 */
/*0450*/ SEL R19, RZ, 0x1, !P6 ; /* 0x00000001ff137807 */
/* 0x000fe40007000000 */
/*0460*/ SEL R18, RZ, 0x1, !P3 ; /* 0x00000001ff127807 */
/* 0x000fc40005800000 */
/*0470*/ SEL R13, RZ, 0x1, !P1 ; /* 0x00000001ff0d7807 */
/* 0x000fe40004800000 */
/*0480*/ ISETP.NE.AND P5, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003fa5270 */
/*0490*/ ISETP.NE.AND P4, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f85270 */
/*04a0*/ ISETP.NE.AND P2, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fe40003f45270 */
/*04b0*/ ISETP.NE.AND P6, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fe40003fc5270 */
/*04c0*/ ISETP.NE.AND P3, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc40003f65270 */
/*04d0*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*04e0*/ SEL R5, RZ, 0x1, !P4 ; /* 0x00000001ff057807 */
/* 0x000fe40006000000 */
/*04f0*/ SEL R4, RZ, 0x1, !P5 ; /* 0x00000001ff047807 */
/* 0x000fe40006800000 */
/*0500*/ SEL R17, RZ, 0x1, !P2 ; /* 0x00000001ff117807 */
/* 0x000fe40005000000 */
/*0510*/ SEL R11, RZ, 0x1, !P3 ; /* 0x00000001ff0b7807 */
/* 0x000fe40005800000 */
/*0520*/ SEL R10, RZ, 0x1, !P6 ; /* 0x00000001ff0a7807 */
/* 0x000fc40007000000 */
/*0530*/ ISETP.NE.AND P4, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f85270 */
/*0540*/ ISETP.NE.AND P5, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003fa5270 */
/*0550*/ ISETP.NE.AND P2, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f45270 */
/*0560*/ ISETP.NE.AND P3, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe40003f65270 */
/*0570*/ ISETP.NE.AND P6, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003fc5270 */
/*0580*/ SEL R9, RZ, 0x1, !P5 ; /* 0x00000001ff097807 */
/* 0x000fc40006800000 */
/*0590*/ SEL R8, RZ, 0x1, !P4 ; /* 0x00000001ff087807 */
/* 0x000fe40006000000 */
/*05a0*/ SEL R15, RZ, 0x1, !P3 ; /* 0x00000001ff0f7807 */
/* 0x000fe40005800000 */
/*05b0*/ SEL R14, RZ, 0x1, !P6 ; /* 0x00000001ff0e7807 */
/* 0x000fe40007000000 */
/*05c0*/ SEL R12, RZ, 0x1, !P2 ; /* 0x00000001ff0c7807 */
/* 0x000fe20005000000 */
/*05d0*/ STL.128 [R0], R4 ; /* 0x0000000400007387 */
/* 0x000fe80000100c00 */
/*05e0*/ STL.128 [R0+0x10], R16 ; /* 0x0000101000007387 */
/* 0x000fe80000100c00 */
/*05f0*/ STL.128 [R0+0x20], R8 ; /* 0x0000200800007387 */
/* 0x000fe80000100c00 */
/*0600*/ STL.128 [R0+0x30], R12 ; /* 0x0000300c00007387 */
/* 0x0001e40000100c00 */
/*0610*/ IADD3 R0, R0, 0x40, RZ ; /* 0x0000004000007810 */
/* 0x001fe20007ffe0ff */
/*0620*/ @P1 BRA 0x360 ; /* 0xfffffd3000001947 */
/* 0x000fea000383ffff */
/*0630*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fe20003f24270 */
/*0650*/ BSSY B4, 0x800 ; /* 0x000001a000047945 */
/* 0x000fd80003800000 */
/*0660*/ @!P1 BRA 0x7f0 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*0670*/ LDL.128 R8, [R0] ; /* 0x0000000000087983 */
/* 0x000ea80000100c00 */
/*0680*/ LDL.128 R4, [R0+0x10] ; /* 0x0000100000047983 */
/* 0x000ee20000100c00 */
/*0690*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.NE.AND P6, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fe40003fc5270 */
/*06c0*/ ISETP.NE.AND P3, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc40003f65270 */
/*06d0*/ SEL R11, RZ, 0x1, !P6 ; /* 0x00000001ff0b7807 */
/* 0x000fe40007000000 */
/*06e0*/ ISETP.NE.AND P4, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f85270 */
/*06f0*/ ISETP.NE.AND P5, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003fa5270 */
/*0700*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x008fe40003f05270 */
/*0710*/ ISETP.NE.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f25270 */
/*0720*/ ISETP.NE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc40003f45270 */
/*0730*/ ISETP.NE.AND P6, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003fc5270 */
/*0740*/ SEL R10, RZ, 0x1, !P5 ; /* 0x00000001ff0a7807 */
/* 0x000fe40006800000 */
/*0750*/ SEL R9, RZ, 0x1, !P4 ; /* 0x00000001ff097807 */
/* 0x000fe40006000000 */
/*0760*/ SEL R8, RZ, 0x1, !P3 ; /* 0x00000001ff087807 */
/* 0x000fe40005800000 */
/*0770*/ SEL R7, RZ, 0x1, !P6 ; /* 0x00000001ff077807 */
/* 0x000fe40007000000 */
/*0780*/ SEL R6, RZ, 0x1, !P2 ; /* 0x00000001ff067807 */
/* 0x000fe20005000000 */
/*0790*/ STL.128 [R0], R8 ; /* 0x0000000800007387 */
/* 0x000fe20000100c00 */
/*07a0*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fc40004800000 */
/*07b0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe40004000000 */
/*07c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*07d0*/ STL.128 [R0+0x10], R4 ; /* 0x0000100400007387 */
/* 0x0001e40000100c00 */
/*07e0*/ IADD3 R0, R0, 0x20, RZ ; /* 0x0000002000007810 */
/* 0x001fc60007ffe0ff */
/*07f0*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0810*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*0820*/ @!P0 BRA 0x930 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ LDL.128 R4, [R0] ; /* 0x0000000000047983 */
/* 0x000ea20000100c00 */
/*0850*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*0870*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fe40003f05270 */
/*0880*/ ISETP.NE.AND P3, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f65270 */
/*0890*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc40004000000 */
/*08a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*08b0*/ ISETP.NE.AND P2, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f45270 */
/*08c0*/ ISETP.NE.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f25270 */
/*08d0*/ SEL R7, RZ, 0x1, !P3 ; /* 0x00000001ff077807 */
/* 0x000fe40005800000 */
/*08e0*/ SEL R6, RZ, 0x1, !P2 ; /* 0x00000001ff067807 */
/* 0x000fe40005000000 */
/*08f0*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fca0004800000 */
/*0900*/ STL.128 [R0], R4 ; /* 0x0000000400007387 */
/* 0x0001e40000100c00 */
/*0910*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x001fe20007ffe0ff */
/*0920*/ @P0 BRA 0x840 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0930*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0940*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*0950*/ @!P0 BRA 0x9f0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0960*/ IMAD R3, R20, 0x4, R1 ; /* 0x0000000414037824 */
/* 0x000fca00078e0201 */
/*0970*/ LDL R0, [R3] ; /* 0x0000000003007983 */
/* 0x000ea20000100800 */
/*0980*/ IADD3 R21, R21, -0x1, RZ ; /* 0xffffffff15157810 */
/* 0x000fe40007ffe0ff */
/*0990*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fc80003f05270 */
/*09a0*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fe40004000000 */
/*09b0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003f05270 */
/*09c0*/ STL [R3], R0 ; /* 0x0000000003007387 */
/* 0x0001e40000100800 */
/*09d0*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x001fd00007ffe0ff */
/*09e0*/ @P0 BRA 0x970 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*09f0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f06270 */
/*0a10*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*0a20*/ @!P0 BRA 0x1150 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0a30*/ LOP3.LUT R0, RZ, R22, RZ, 0x33, !PT ; /* 0x00000016ff007212 */
/* 0x000fe200078e33ff */
/*0a40*/ BSSY B1, 0x10b0 ; /* 0x0000066000017945 */
/* 0x000fe60003800000 */
/*0a50*/ IMNMX R3, R0, -0x2, !PT ; /* 0xfffffffe00037817 */
/* 0x000fca0007800200 */
/*0a60*/ IMAD.IADD R4, R22, 0x1, R3 ; /* 0x0000000116047824 */
/* 0x000fca00078e0203 */
/*0a70*/ IADD3 R0, R4.reuse, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x040fe40007ffe0ff */
/*0a80*/ IADD3 R3, R4, 0x2, RZ ; /* 0x0000000204037810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0aa0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0ab0*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fd600078ec0ff */
/*0ac0*/ @!P0 BRA 0x10a0 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.IADD R5, R4, 0x1, -R3 ; /* 0x0000000104057824 */
/* 0x000fe200078e0a03 */
/*0ae0*/ IADD3 R4, R22, -0x1, RZ ; /* 0xffffffff16047810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ BSSY B2, 0xfd0 ; /* 0x000004d000027945 */
/* 0x000fe20003800000 */
/*0b00*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0b10*/ ISETP.GT.AND P0, PT, R5, -0x2, PT ; /* 0xfffffffe0500780c */
/* 0x000fe20003f04270 */
/*0b20*/ IMAD R4, R4, 0x4, R1 ; /* 0x0000000404047824 */
/* 0x000fd800078e0201 */
/*0b30*/ @!P0 BRA 0xfc0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0b40*/ IADD3 R6, R5, 0x2, RZ ; /* 0x0000000205067810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ BSSY B3, 0xe00 ; /* 0x000002a000037945 */
/* 0x000fe20003800000 */
/*0b60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0b70*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fda0003f24270 */
/*0b80*/ @!P1 BRA 0xdf0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0b90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0ba0*/ LDL R17, [R4] ; /* 0x0000000004117983 */
/* 0x0000a80000100800 */
/*0bb0*/ LDL R16, [R4+-0x4] ; /* 0xfffffc0004107983 */
/* 0x0000e80000100800 */
/*0bc0*/ LDL R19, [R4+-0x8] ; /* 0xfffff80004137983 */
/* 0x0001280000100800 */
/*0bd0*/ LDL R21, [R4+-0xc] ; /* 0xfffff40004157983 */
/* 0x0001680000100800 */
/*0be0*/ LDL R25, [R4+-0x10] ; /* 0xfffff00004197983 */
/* 0x0001680000100800 */
/*0bf0*/ LDL R27, [R4+-0x14] ; /* 0xffffec00041b7983 */
/* 0x0001680000100800 */
/*0c00*/ LDL R15, [R4+-0x18] ; /* 0xffffe800040f7983 */
/* 0x0001680000100800 */
/*0c10*/ LDL R14, [R4+-0x1c] ; /* 0xffffe400040e7983 */
/* 0x0001680000100800 */
/*0c20*/ LDL R13, [R4+-0x20] ; /* 0xffffe000040d7983 */
/* 0x0001680000100800 */
/*0c30*/ LDL R12, [R4+-0x24] ; /* 0xffffdc00040c7983 */
/* 0x0001680000100800 */
/*0c40*/ LDL R11, [R4+-0x28] ; /* 0xffffd800040b7983 */
/* 0x0001680000100800 */
/*0c50*/ LDL R10, [R4+-0x2c] ; /* 0xffffd400040a7983 */
/* 0x0001680000100800 */
/*0c60*/ LDL R9, [R4+-0x30] ; /* 0xffffd00004097983 */
/* 0x0001680000100800 */
/*0c70*/ LDL R7, [R4+-0x34] ; /* 0xffffcc0004077983 */
/* 0x0001680000100800 */
/*0c80*/ LDL R8, [R4+-0x38] ; /* 0xffffc80004087983 */
/* 0x0001680000100800 */
/*0c90*/ LDL R6, [R4+-0x3c] ; /* 0xffffc40004067983 */
/* 0x0001620000100800 */
/*0ca0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc40007ffe0ff */
/*0cb0*/ IADD3 R22, R22, -0x10, RZ ; /* 0xfffffff016167810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ ISETP.GT.AND P1, PT, R5, 0xa, PT ; /* 0x0000000a0500780c */
/* 0x000fe40003f24270 */
/*0cd0*/ IADD3 R4, R4, -0x40, RZ ; /* 0xffffffc004047810 */
/* 0x001fe20007ffe0ff */
/*0ce0*/ IMAD R17, R0, 0xa, R17 ; /* 0x0000000a00117824 */
/* 0x004fc800078e0211 */
/*0cf0*/ IMAD R16, R17, 0xa, R16 ; /* 0x0000000a11107824 */
/* 0x008fc800078e0210 */
/*0d00*/ IMAD R16, R16, 0xa, R19 ; /* 0x0000000a10107824 */
/* 0x010fc800078e0213 */
/*0d10*/ IMAD R16, R16, 0xa, R21 ; /* 0x0000000a10107824 */
/* 0x020fc800078e0215 */
/*0d20*/ IMAD R16, R16, 0xa, R25 ; /* 0x0000000a10107824 */
/* 0x000fc800078e0219 */
/*0d30*/ IMAD R16, R16, 0xa, R27 ; /* 0x0000000a10107824 */
/* 0x000fc800078e021b */
/*0d40*/ IMAD R15, R16, 0xa, R15 ; /* 0x0000000a100f7824 */
/* 0x000fc800078e020f */
/*0d50*/ IMAD R14, R15, 0xa, R14 ; /* 0x0000000a0f0e7824 */
/* 0x000fc800078e020e */
/*0d60*/ IMAD R13, R14, 0xa, R13 ; /* 0x0000000a0e0d7824 */
/* 0x000fc800078e020d */
/*0d70*/ IMAD R12, R13, 0xa, R12 ; /* 0x0000000a0d0c7824 */
/* 0x000fc800078e020c */
/*0d80*/ IMAD R11, R12, 0xa, R11 ; /* 0x0000000a0c0b7824 */
/* 0x000fc800078e020b */
/*0d90*/ IMAD R10, R11, 0xa, R10 ; /* 0x0000000a0b0a7824 */
/* 0x000fc800078e020a */
/*0da0*/ IMAD R10, R10, 0xa, R9 ; /* 0x0000000a0a0a7824 */
/* 0x000fc800078e0209 */
/*0db0*/ IMAD R7, R10, 0xa, R7 ; /* 0x0000000a0a077824 */
/* 0x000fc800078e0207 */
/*0dc0*/ IMAD R7, R7, 0xa, R8 ; /* 0x0000000a07077824 */
/* 0x000fc800078e0208 */
/*0dd0*/ IMAD R0, R7, 0xa, R6 ; /* 0x0000000a07007824 */
/* 0x000fe200078e0206 */
/*0de0*/ @P1 BRA 0xba0 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*0df0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0e00*/ IADD3 R6, R5, 0x2, RZ ; /* 0x0000000205067810 */
/* 0x000fe20007ffe0ff */
/*0e10*/ BSSY B3, 0xf90 ; /* 0x0000017000037945 */
/* 0x000fe60003800000 */
/*0e20*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0e30*/ @!P1 BRA 0xf80 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0e40*/ LDL R7, [R4] ; /* 0x0000000004077983 */
/* 0x0000a80000100800 */
/*0e50*/ LDL R6, [R4+-0x4] ; /* 0xfffffc0004067983 */
/* 0x0000e80000100800 */
/*0e60*/ LDL R9, [R4+-0x8] ; /* 0xfffff80004097983 */
/* 0x0001280000100800 */
/*0e70*/ LDL R11, [R4+-0xc] ; /* 0xfffff400040b7983 */
/* 0x0001680000100800 */
/*0e80*/ LDL R13, [R4+-0x10] ; /* 0xfffff000040d7983 */
/* 0x0001680000100800 */
/*0e90*/ LDL R15, [R4+-0x14] ; /* 0xffffec00040f7983 */
/* 0x0001680000100800 */
/*0ea0*/ LDL R17, [R4+-0x18] ; /* 0xffffe80004117983 */
/* 0x0001680000100800 */
/*0eb0*/ LDL R19, [R4+-0x1c] ; /* 0xffffe40004137983 */
/* 0x0001620000100800 */
/*0ec0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0ed0*/ IADD3 R22, R22, -0x8, RZ ; /* 0xfffffff816167810 */
/* 0x000fe40007ffe0ff */
/*0ee0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0ef0*/ IADD3 R4, R4, -0x20, RZ ; /* 0xffffffe004047810 */
/* 0x001fe20007ffe0ff */
/*0f00*/ IMAD R7, R0, 0xa, R7 ; /* 0x0000000a00077824 */
/* 0x004fc800078e0207 */
/*0f10*/ IMAD R6, R7, 0xa, R6 ; /* 0x0000000a07067824 */
/* 0x008fc800078e0206 */
/*0f20*/ IMAD R6, R6, 0xa, R9 ; /* 0x0000000a06067824 */
/* 0x010fc800078e0209 */
/*0f30*/ IMAD R6, R6, 0xa, R11 ; /* 0x0000000a06067824 */
/* 0x020fc800078e020b */
/*0f40*/ IMAD R6, R6, 0xa, R13 ; /* 0x0000000a06067824 */
/* 0x000fc800078e020d */
/*0f50*/ IMAD R6, R6, 0xa, R15 ; /* 0x0000000a06067824 */
/* 0x000fc800078e020f */
/*0f60*/ IMAD R6, R6, 0xa, R17 ; /* 0x0000000a06067824 */
/* 0x000fc800078e0211 */
/*0f70*/ IMAD R0, R6, 0xa, R19 ; /* 0x0000000a06007824 */
/* 0x000fe400078e0213 */
/*0f80*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0f90*/ ISETP.NE.OR P0, PT, R5, -0x2, P0 ; /* 0xfffffffe0500780c */
/* 0x000fda0000705670 */
/*0fa0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0fb0*/ @!P0 BRA 0x10a0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0fc0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fd0*/ LDL R7, [R4] ; /* 0x0000000004077983 */
/* 0x0000a80000100800 */
/*0fe0*/ LDL R6, [R4+-0x4] ; /* 0xfffffc0004067983 */
/* 0x0000e80000100800 */
/*0ff0*/ LDL R9, [R4+-0x8] ; /* 0xfffff80004097983 */
/* 0x0001280000100800 */
/*1000*/ LDL R11, [R4+-0xc] ; /* 0xfffff400040b7983 */
/* 0x0001620000100800 */
/*1010*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc40007ffe0ff */
/*1020*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x000fe40007ffe0ff */
/*1030*/ ISETP.NE.AND P0, PT, R5, -0x2, PT ; /* 0xfffffffe0500780c */
/* 0x000fe40003f05270 */
/*1040*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x001fe20007ffe0ff */
/*1050*/ IMAD R7, R0, 0xa, R7 ; /* 0x0000000a00077824 */
/* 0x004fc800078e0207 */
/*1060*/ IMAD R6, R7, 0xa, R6 ; /* 0x0000000a07067824 */
/* 0x008fc800078e0206 */
/*1070*/ IMAD R6, R6, 0xa, R9 ; /* 0x0000000a06067824 */
/* 0x010fc800078e0209 */
/*1080*/ IMAD R0, R6, 0xa, R11 ; /* 0x0000000a06007824 */
/* 0x020fe200078e020b */
/*1090*/ @P0 BRA 0xfd0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*10a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*10c0*/ @!P0 BRA 0x1150 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*10d0*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fca0007ffe0ff */
/*10e0*/ IMAD R22, R22, 0x4, R1 ; /* 0x0000000416167824 */
/* 0x000fca00078e0201 */
/*10f0*/ LDL R5, [R22] ; /* 0x0000000016057983 */
/* 0x0000a20000100800 */
/*1100*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fc80007ffe0ff */
/*1110*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*1120*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x001fe20007ffe0ff */
/*1130*/ IMAD R0, R0, 0xa, R5 ; /* 0x0000000a00007824 */
/* 0x004fd400078e0205 */
/*1140*/ @P0 BRA 0x10f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*1150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*1160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*1170*/ LEA R4, P0, R23, c[0x0][0x168], 0x2 ; /* 0x00005a0017047a11 */
/* 0x000fc800078010ff */
/*1180*/ LEA.HI.X R5, R23, c[0x0][0x16c], R2, 0x2, P0 ; /* 0x00005b0017057a11 */
/* 0x000fca00000f1402 */
/*1190*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x020fe2000c101908 */
/*11a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*11b0*/ BRA 0x11b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5onescPiS_
.globl _Z5onescPiS_
.p2align 8
.type _Z5onescPiS_,@function
_Z5onescPiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lg_u32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cselect_b32 s1, -1, 0
s_add_i32 s0, s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v0
global_load_b32 v3, v[3:4], off
s_and_b32 s1, s1, vcc_lo
s_cmp_lg_u32 s15, s0
s_cselect_b32 s0, -1, 0
s_add_i32 s2, s2, -1
s_and_b32 s0, s1, s0
v_cmp_ne_u32_e32 vcc_lo, s2, v0
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s0, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execnz .LBB0_15
.LBB0_2:
s_endpgm
.LBB0_3:
v_mov_b32_e32 v0, 0
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v4, 16
s_mov_b32 s2, 0
s_mov_b32 s3, 0
.LBB0_5:
v_lshrrev_b32_e32 v5, 1, v3
v_and_b32_e32 v0, 1, v3
s_add_i32 s3, s3, 1
v_cmp_gt_u32_e32 vcc_lo, 2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v3, v5
scratch_store_b32 v4, v0, off
v_add_nc_u32_e32 v4, 4, v4
v_mov_b32_e32 v0, s3
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s2
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s2, 0
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v3, 16 :: v_dual_mov_b32 v4, v0
.LBB0_9:
scratch_load_b32 v5, v3, off
v_add_nc_u32_e32 v4, -1, v4
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v5
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
scratch_store_b32 v3, v5, off
v_add_nc_u32_e32 v3, 4, v3
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_9
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v3, 0
s_mov_b32 s2, 0
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v3, 2, v0
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v3, 16, -4
v_mov_b32_e32 v3, 0
.LBB0_12:
scratch_load_b32 v5, v4, off
v_add_nc_u32_e32 v4, -4, v4
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v3, 10, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, v6 :: v_dual_add_nc_u32 v0, -1, v0
v_cmp_gt_i32_e32 vcc_lo, 2, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s2
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
.LBB0_15:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5onescPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 144
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5onescPiS_, .Lfunc_end0-_Z5onescPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5onescPiS_
.private_segment_fixed_size: 144
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5onescPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b1a41_00000000-6_CUDA_MatrixOnesComplement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5onescPiS_PiS_
.type _Z26__device_stub__Z5onescPiS_PiS_, @function
_Z26__device_stub__Z5onescPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5onescPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5onescPiS_PiS_, .-_Z26__device_stub__Z5onescPiS_PiS_
.globl _Z5onescPiS_
.type _Z5onescPiS_, @function
_Z5onescPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5onescPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5onescPiS_, .-_Z5onescPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the value of m: "
.LC1:
.string "%d"
.LC2:
.string "Enter the value of n: "
.LC3:
.string "Enter input matrix: \n"
.LC4:
.string "Resultant matrix:\n"
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %r13d
imull 8(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .L12
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r14
.L13:
movq %rbp, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cmpl %ebx, %eax
jg .L13
.L12:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L14:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r14
cmpl $0, 8(%rsp)
jg .L15
.L16:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z5onescPiS_PiS_
jmp .L14
.L17:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 12(%rsp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jle .L16
.L15:
movl 12(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5onescPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5onescPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_MatrixOnesComplement.hip"
.globl _Z20__device_stub__onescPiS_ # -- Begin function _Z20__device_stub__onescPiS_
.p2align 4, 0x90
.type _Z20__device_stub__onescPiS_,@function
_Z20__device_stub__onescPiS_: # @_Z20__device_stub__onescPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5onescPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__onescPiS_, .Lfunc_end0-_Z20__device_stub__onescPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r12
cmpq %rcx, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5onescPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.6: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge31
# in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_11
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_10
# %bb.8: # %.lr.ph30.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph30
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_9
jmp .LBB1_10
.LBB1_11: # %._crit_edge33
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5onescPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5onescPiS_,@object # @_Z5onescPiS_
.section .rodata,"a",@progbits
.globl _Z5onescPiS_
.p2align 3, 0x0
_Z5onescPiS_:
.quad _Z20__device_stub__onescPiS_
.size _Z5onescPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the value of m: "
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter the value of n: "
.size .L.str.2, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5onescPiS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter input matrix: "
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Resultant matrix:"
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__onescPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5onescPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <tuple>
#include <random>
#include <functional>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ bool getCell( bool* input, int x, int y, int* size ) {
if ( x < 0 ) { x = x + size[1]; }
else if ( x >= size[1] ) { x = x - size[1]; }
if ( y < 0 ) { y = y + size[0]; }
else if ( y >= size[0] ) { y = y - size[0]; }
return input[ y * size[0] + x ];
}
__device__ int getNeighbourCount( bool* input, int x, int y, int* size ) {
int count = 0;
if ( getCell( input, x - 1 , y - 1, size )) { count++; }
if ( getCell( input, x , y - 1, size )) { count++; }
if ( getCell( input, x + 1 , y - 1, size )) { count++; }
if ( getCell( input, x - 1 , y, size )) { count++; }
if ( getCell( input, x + 1 , y, size )) { count++; }
if ( getCell( input, x - 1 , y + 1, size )) { count++; }
if ( getCell( input, x , y + 1, size )) { count++; }
if ( getCell( input, x + 1 , y + 1, size )) { count++; }
return count;
}
__global__ void simulate( bool* input, bool* output, int width, int height, int steps ) {
int index = threadIdx.x;
int stride = blockDim.x;
if ( index >= ( width * height )) {
// Index out of range
printf("Out of range: %d\n", index);
return;
}
// Find X and Y
int y = index / width;
int x = index % width;
int size[2] = {width, height};
//printf("X: %d, Y: %d\n", x, y);
int count = getNeighbourCount( input, x, y, size );
if ( input[ index ] ) {
//printf("alive");
// Cell is alive
if ( count == 2 || count == 3 ) {
// Cell has 2 or 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
} else {
//printf("dead");
// Cell is dead
if ( count == 3 ) {
// Cell has exactly 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
}
}
/*
Clears screen and moves cursor to home pos on POSIX systems
*/
void clear() {
std::cout << "\033[2J;" << "\033[1;1H";
}
/*
*/
void printGrid( bool* grid, int* size ) {
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
if ( grid[ y * size[1] + x ] == true ) {
std::cout << "0";
}
else {
std::cout << ".";
}
}
std::cout << std::endl;
}
}
static void show_usage(std::string name)
{
std::cerr << "Usage: " << name << " [-i input.txt]/[-r] [-o output.txt] [-s 10]\n"
<< "Options:" << std::endl
<< "\t-h, --help\t\tShow this help message and exit" << std::endl
<< "\t-i, --input\t\tProvide an input file for the starting state" << std::endl
<< "\t-r, --random\t\tInstead start with a randomized starting state, provide a seed, 0 will set a random seed" << std::endl
<< "\t-o, --output\t\tOptionally save the final state as a file" << std::endl
<< "\t-s, --steps\t\tThe number of simulation step to take" << std::endl
<< "\t-p, --play\t\tOptionally play the simulation in the console" << std::endl
<< std::endl;
}
int main( int argc, char* argv[] ) {
int opt;
char* input;
char* output;
bool isRandom = false;
std::ofstream outfile;
bool play = false;
int seed;
int steps = 0;
int size[2] = {10, 10}; // x, y
int width, height;
int gridSize = size[1] * size[0] * sizeof(bool*);
bool* grid;
bool* d_in; // The read-only input array for kernel
bool* d_out; // The write-only output for kernel
if ( argc < 2 ) {
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
while (( opt = getopt(argc, argv, "hi:o:r:s:p" )) != -1 ) {
switch ( opt ) {
case 'h':
show_usage( argv[0] );
exit( EXIT_FAILURE );
break;
case 'i':
input = optarg;
break;
case 'o':
output = optarg;
break;
case 'r':
isRandom = true;
seed = atoi(optarg);
break;
case 's':
steps = atoi(optarg);
break;
case 'p':
play = true;
break;
default: /* '?' */
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
}
// Init empty grid
grid = (bool*) malloc( gridSize );
gpuErrchk( cudaMalloc( &d_in, gridSize ) );
gpuErrchk( cudaMalloc( &d_out, gridSize ) );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = false; // Init host grid to empty
}
}
if ( isRandom ) {
if ( ! seed ) {
seed = std::chrono::steady_clock::now().time_since_epoch().count();
}
std::default_random_engine engine(seed);
std::uniform_int_distribution<> boolGen( 0, 1 );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = boolGen( engine );
}
}
} else {
// File is assumed to have {width} {height} on the first line
std::ifstream infile( input );
std::string size_string;
std::string delimiter = " ";
// parsing string into two ints for width and height
std::getline( infile, size_string );
std::string str1 = size_string.substr( 0, size_string.find( delimiter ));
size_string.erase( 0, size_string.find( delimiter ) + delimiter.length() );
std::string str2 = size_string;
int width = stoi( str1 );
int height = stoi( str2 );
std::string line;
int count = 0; // current line count
while ( std::getline( infile, line )) {
for ( int x = 0; x < width; x++ ) {
if ( line[x] == '0' ) {
grid[ count * width + x ] = true;
} else {
grid[ count * width + x ] = false;
}
}
count++;
}
}
if ( play ) {
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( cudaMemcpy ( d_in, grid, gridSize, cudaMemcpyHostToDevice ) );
for (int step = 0; step < steps; step++) {
simulate<<< 1, 100 >>>( d_in, d_out, size[0], size[1], steps );
if ( play ) {
gpuErrchk( cudaMemcpy ( grid, d_out, gridSize, cudaMemcpyDeviceToHost ) );
gpuErrchk( cudaDeviceSynchronize() );
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( cudaMemcpy ( d_in, d_out, gridSize, cudaMemcpyHostToHost ) );
}
if ( !play ) {
// Wait for GPU to finish before accessing on host
gpuErrchk( cudaMemcpy ( grid, d_out, gridSize, cudaMemcpyDeviceToHost ) );
gpuErrchk( cudaDeviceSynchronize() );
printGrid( grid, size );
}
// Clean up memory allocations
free( grid );
cudaFree( d_in );
cudaFree( d_out );
exit( EXIT_SUCCESS );
} | code for sm_80
Function : _Z8simulatePbS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fc6000f8e023f */
/*0050*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0060*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fda000bf06270 */
/*0080*/ @!P0 BRA 0x170 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00a0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e20000100800 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00d0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e6a0000000a00 */
/*00e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0140*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0150*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ IABS R5, c[0x0][0x170] ; /* 0x00005c0000057a13 */
/* 0x000fe20000000000 */
/*0180*/ IMAD.MOV R9, RZ, RZ, -c[0x0][0x174] ; /* 0x80005d00ff097624 */
/* 0x000fe200078e02ff */
/*0190*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*01b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*01f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0200*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0210*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0220*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0230*/ LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000027a12 */
/* 0x000fc800078e3cff */
/*0240*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0250*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0270*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fe400078e0206 */
/*0280*/ IMAD.MOV R6, RZ, RZ, -c[0x0][0x170] ; /* 0x80005c00ff067624 */
/* 0x000fc600078e02ff */
/*0290*/ ISETP.GT.U32.AND P1, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f24070 */
/*02a0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a05 */
/*02b0*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0003 */
/*0300*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*0310*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff049a12 */
/* 0x000fc800078e33ff */
/*0320*/ ISETP.GT.AND P1, PT, R4.reuse, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x040fe20003f24270 */
/*0330*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a04 */
/*0340*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f06270 */
/*0350*/ SEL R5, R6, RZ, P1 ; /* 0x000000ff06057207 */
/* 0x000fe20000800000 */
/*0360*/ IMAD R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0200 */
/*0370*/ IADD3 R17, R4, 0x1, RZ ; /* 0x0000000104117810 */
/* 0x000fe40007ffe0ff */
/*0380*/ SEL R5, R5, c[0x0][0x170], P0 ; /* 0x00005c0005057a07 */
/* 0x000fe40000000000 */
/*0390*/ ISETP.GT.AND P3, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fc40003f64270 */
/*03a0*/ ISETP.GE.AND P4, PT, R2.reuse, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x040fe40003f86270 */
/*03b0*/ ISETP.GE.AND P1, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe40003f26270 */
/*03c0*/ ISETP.GE.AND P2, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe40003f46270 */
/*03d0*/ SEL R3, R9.reuse, RZ, P3 ; /* 0x000000ff09037207 */
/* 0x040fe40001800000 */
/*03e0*/ SEL R7, R9, RZ, P4 ; /* 0x000000ff09077207 */
/* 0x000fe40002000000 */
/*03f0*/ IADD3 R8, R2, 0x1, RZ ; /* 0x0000000102087810 */
/* 0x000fc40007ffe0ff */
/*0400*/ SEL R3, R3, c[0x0][0x174], P1 ; /* 0x00005d0003037a07 */
/* 0x000fe40000800000 */
/*0410*/ SEL R7, R7, c[0x0][0x174], P2 ; /* 0x00005d0007077a07 */
/* 0x000fe40001000000 */
/*0420*/ ISETP.GE.AND P1, PT, R8, c[0x0][0x174], PT ; /* 0x00005d0008007a0c */
/* 0x000fe40003f26270 */
/*0430*/ ISETP.GE.AND P3, PT, R2.reuse, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x040fe40003f66270 */
/*0440*/ IADD3 R3, R2.reuse, -0x1, R3 ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe003 */
/*0450*/ IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102027824 */
/* 0x000fe200078e0207 */
/*0460*/ IADD3 R10, R4, -0x1, R5 ; /* 0xffffffff040a7810 */
/* 0x000fc40007ffe005 */
/*0470*/ SEL R7, R9, RZ, P1 ; /* 0x000000ff09077207 */
/* 0x000fe40000800000 */
/*0480*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f26270 */
/*0490*/ IMAD R11, R10.reuse, c[0x0][0x170], R2 ; /* 0x00005c000a0b7a24 */
/* 0x040fe200078e0202 */
/*04a0*/ SEL R5, R7, c[0x0][0x174], P3 ; /* 0x00005d0007057a07 */
/* 0x000fe20001800000 */
/*04b0*/ IMAD R9, R10, c[0x0][0x170], R3 ; /* 0x00005c000a097a24 */
/* 0x000fe200078e0203 */
/*04c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f06270 */
/*04d0*/ SEL R7, R6, RZ, P1 ; /* 0x000000ff06077207 */
/* 0x000fe20000800000 */
/*04e0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fe200078e0205 */
/*04f0*/ IADD3 R12, P1, R11, c[0x0][0x160], RZ ; /* 0x000058000b0c7a10 */
/* 0x000fc40007f3e0ff */
/*0500*/ SEL R7, R7, c[0x0][0x170], P0 ; /* 0x00005c0007077a07 */
/* 0x000fe40000000000 */
/*0510*/ LEA.HI.X.SX32 R13, R11, c[0x0][0x164], 0x1, P1 ; /* 0x000059000b0d7a11 */
/* 0x000fe400008f0eff */
/*0520*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x170], PT ; /* 0x00005c0011007a0c */
/* 0x000fe20003f26270 */
/*0530*/ IMAD.IADD R14, R4.reuse, 0x1, R7 ; /* 0x00000001040e7824 */
/* 0x040fe200078e0207 */
/*0540*/ ISETP.GE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fe20003f06270 */
/*0550*/ IMAD R7, R10, c[0x0][0x170], R5 ; /* 0x00005c000a077a24 */
/* 0x000fe200078e0205 */
/*0560*/ IADD3 R8, P2, R9.reuse, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x040fe20007f5e0ff */
/*0570*/ LDG.E.U8 R4, [R12.64] ; /* 0x000000040c047981 */
/* 0x0000a2000c1e1100 */
/*0580*/ SEL R6, R6, RZ, P1 ; /* 0x000000ff06067207 */
/* 0x000fe20000800000 */
/*0590*/ IMAD R15, R14, c[0x0][0x170], R3 ; /* 0x00005c000e0f7a24 */
/* 0x000fe200078e0203 */
/*05a0*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P2 ; /* 0x0000590009097a11 */
/* 0x000fc400010f0eff */
/*05b0*/ IADD3 R10, P1, R7, c[0x0][0x160], RZ ; /* 0x00005800070a7a10 */
/* 0x000fe40007f3e0ff */
/*05c0*/ SEL R18, R6, c[0x0][0x170], P0 ; /* 0x00005c0006127a07 */
/* 0x000fe20000000000 */
/*05d0*/ IMAD R16, R14, c[0x0][0x170], R5 ; /* 0x00005c000e107a24 */
/* 0x000fe200078e0205 */
/*05e0*/ IADD3 R6, P0, R15, c[0x0][0x160], RZ ; /* 0x000058000f067a10 */
/* 0x000fe20007f1e0ff */
/*05f0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0002e2000c1e1100 */
/*0600*/ LEA.HI.X.SX32 R11, R7, c[0x0][0x164], 0x1, P1 ; /* 0x00005900070b7a11 */
/* 0x000fe200008f0eff */
/*0610*/ IMAD.IADD R18, R17, 0x1, R18 ; /* 0x0000000111127824 */
/* 0x000fe200078e0212 */
/*0620*/ LEA.HI.X.SX32 R7, R15, c[0x0][0x164], 0x1, P0 ; /* 0x000059000f077a11 */
/* 0x000fe400000f0eff */
/*0630*/ IADD3 R14, P0, R16, c[0x0][0x160], RZ ; /* 0x00005800100e7a10 */
/* 0x000fe20007f1e0ff */
/*0640*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1100 */
/*0650*/ IMAD R3, R18, c[0x0][0x170], R3 ; /* 0x00005c0012037a24 */
/* 0x000fc400078e0203 */
/*0660*/ LEA.HI.X.SX32 R15, R16, c[0x0][0x164], 0x1, P0 ; /* 0x00005900100f7a11 */
/* 0x000fe200000f0eff */
/*0670*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000b22000c1e1100 */
/*0680*/ IMAD R16, R18, c[0x0][0x170], R2 ; /* 0x00005c0012107a24 */
/* 0x000fe200078e0202 */
/*0690*/ IADD3 R12, P0, R3.reuse, c[0x0][0x160], RZ ; /* 0x00005800030c7a10 */
/* 0x041fe40007f1e0ff */
/*06a0*/ LDG.E.U8 R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x002124000c1e1100 */
/*06b0*/ LEA.HI.X.SX32 R13, R3, c[0x0][0x164], 0x1, P0 ; /* 0x00005900030d7a11 */
/* 0x000fe400000f0eff */
/*06c0*/ IADD3 R2, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010027a10 */
/* 0x000fe20007f1e0ff */
/*06d0*/ IMAD R5, R18, c[0x0][0x170], R5 ; /* 0x00005c0012057a24 */
/* 0x000fc400078e0205 */
/*06e0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1100 */
/*06f0*/ LEA.HI.X.SX32 R3, R16, c[0x0][0x164], 0x1, P0 ; /* 0x0000590010037a11 */
/* 0x000fe400000f0eff */
/*0700*/ IADD3 R16, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005107a10 */
/* 0x000fc60007f1e0ff */
/*0710*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000322000c1e1100 */
/*0720*/ LEA.HI.X.SX32 R17, R5, c[0x0][0x164], 0x1, P0 ; /* 0x0000590005117a11 */
/* 0x000fe400000f0eff */
/*0730*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0740*/ IADD3 R14, P0, R0, c[0x0][0x160], RZ ; /* 0x00005800000e7a10 */
/* 0x001fe20007f1e0ff */
/*0750*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f26000c1e1100 */
/*0760*/ IADD3.X R15, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900050f7a10 */
/* 0x000fca00007fe4ff */
/*0770*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1100 */
/*0780*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x020fe200078e00ff */
/*0790*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fe40003f45270 */
/*07a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x008fc80003f05270 */
/*07b0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fe40004000000 */
/*07c0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x010fca0003f25270 */
/*07d0*/ @P2 SEL R4, R7, 0x2, !P0 ; /* 0x0000000207042807 */
/* 0x000fe40004000000 */
/*07e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*07f0*/ SEL R3, RZ, 0x1, !P1 ; /* 0x00000001ff037807 */
/* 0x002fe40004800000 */
/*0800*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f25270 */
/*0810*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x000fca00078e0203 */
/*0820*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*0830*/ @!P0 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0203 */
/*0840*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05270 */
/*0850*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fe20007ffe0ff */
/*0860*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*0870*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f25270 */
/*0880*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fc60007ffe0ff */
/*0890*/ @!P0 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0203 */
/*08a0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc80003f05270 */
/*08b0*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ @!P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0204 */
/*08d0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f25270 */
/*08e0*/ IADD3 R2, P2, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fe40007f5e0ff */
/*08f0*/ IADD3 R0, R6, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3.X R3, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005037a10 */
/* 0x000fe200017fe4ff */
/*0910*/ @!P0 IMAD.MOV R0, RZ, RZ, R6 ; /* 0x000000ffff008224 */
/* 0x000fcc00078e0206 */
/*0920*/ @!P1 BRA 0x9c0 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*0930*/ LOP3.LUT R0, R0, 0x1, RZ, 0xfc, !PT ; /* 0x0000000100007812 */
/* 0x000fe200078efcff */
/*0940*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0950*/ ISETP.NE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f05270 */
/*0960*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101104 */
/*0970*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0990*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*09a0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ ISETP.NE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f05270 */
/*09d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*09e0*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101104 */
/*09f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0a10*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0a20*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*0a30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a40*/ BRA 0xa40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <tuple>
#include <random>
#include <functional>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ bool getCell( bool* input, int x, int y, int* size ) {
if ( x < 0 ) { x = x + size[1]; }
else if ( x >= size[1] ) { x = x - size[1]; }
if ( y < 0 ) { y = y + size[0]; }
else if ( y >= size[0] ) { y = y - size[0]; }
return input[ y * size[0] + x ];
}
__device__ int getNeighbourCount( bool* input, int x, int y, int* size ) {
int count = 0;
if ( getCell( input, x - 1 , y - 1, size )) { count++; }
if ( getCell( input, x , y - 1, size )) { count++; }
if ( getCell( input, x + 1 , y - 1, size )) { count++; }
if ( getCell( input, x - 1 , y, size )) { count++; }
if ( getCell( input, x + 1 , y, size )) { count++; }
if ( getCell( input, x - 1 , y + 1, size )) { count++; }
if ( getCell( input, x , y + 1, size )) { count++; }
if ( getCell( input, x + 1 , y + 1, size )) { count++; }
return count;
}
__global__ void simulate( bool* input, bool* output, int width, int height, int steps ) {
int index = threadIdx.x;
int stride = blockDim.x;
if ( index >= ( width * height )) {
// Index out of range
printf("Out of range: %d\n", index);
return;
}
// Find X and Y
int y = index / width;
int x = index % width;
int size[2] = {width, height};
//printf("X: %d, Y: %d\n", x, y);
int count = getNeighbourCount( input, x, y, size );
if ( input[ index ] ) {
//printf("alive");
// Cell is alive
if ( count == 2 || count == 3 ) {
// Cell has 2 or 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
} else {
//printf("dead");
// Cell is dead
if ( count == 3 ) {
// Cell has exactly 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
}
}
/*
Clears screen and moves cursor to home pos on POSIX systems
*/
void clear() {
std::cout << "\033[2J;" << "\033[1;1H";
}
/*
*/
void printGrid( bool* grid, int* size ) {
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
if ( grid[ y * size[1] + x ] == true ) {
std::cout << "0";
}
else {
std::cout << ".";
}
}
std::cout << std::endl;
}
}
static void show_usage(std::string name)
{
std::cerr << "Usage: " << name << " [-i input.txt]/[-r] [-o output.txt] [-s 10]\n"
<< "Options:" << std::endl
<< "\t-h, --help\t\tShow this help message and exit" << std::endl
<< "\t-i, --input\t\tProvide an input file for the starting state" << std::endl
<< "\t-r, --random\t\tInstead start with a randomized starting state, provide a seed, 0 will set a random seed" << std::endl
<< "\t-o, --output\t\tOptionally save the final state as a file" << std::endl
<< "\t-s, --steps\t\tThe number of simulation step to take" << std::endl
<< "\t-p, --play\t\tOptionally play the simulation in the console" << std::endl
<< std::endl;
}
int main( int argc, char* argv[] ) {
int opt;
char* input;
char* output;
bool isRandom = false;
std::ofstream outfile;
bool play = false;
int seed;
int steps = 0;
int size[2] = {10, 10}; // x, y
int width, height;
int gridSize = size[1] * size[0] * sizeof(bool*);
bool* grid;
bool* d_in; // The read-only input array for kernel
bool* d_out; // The write-only output for kernel
if ( argc < 2 ) {
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
while (( opt = getopt(argc, argv, "hi:o:r:s:p" )) != -1 ) {
switch ( opt ) {
case 'h':
show_usage( argv[0] );
exit( EXIT_FAILURE );
break;
case 'i':
input = optarg;
break;
case 'o':
output = optarg;
break;
case 'r':
isRandom = true;
seed = atoi(optarg);
break;
case 's':
steps = atoi(optarg);
break;
case 'p':
play = true;
break;
default: /* '?' */
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
}
// Init empty grid
grid = (bool*) malloc( gridSize );
gpuErrchk( cudaMalloc( &d_in, gridSize ) );
gpuErrchk( cudaMalloc( &d_out, gridSize ) );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = false; // Init host grid to empty
}
}
if ( isRandom ) {
if ( ! seed ) {
seed = std::chrono::steady_clock::now().time_since_epoch().count();
}
std::default_random_engine engine(seed);
std::uniform_int_distribution<> boolGen( 0, 1 );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = boolGen( engine );
}
}
} else {
// File is assumed to have {width} {height} on the first line
std::ifstream infile( input );
std::string size_string;
std::string delimiter = " ";
// parsing string into two ints for width and height
std::getline( infile, size_string );
std::string str1 = size_string.substr( 0, size_string.find( delimiter ));
size_string.erase( 0, size_string.find( delimiter ) + delimiter.length() );
std::string str2 = size_string;
int width = stoi( str1 );
int height = stoi( str2 );
std::string line;
int count = 0; // current line count
while ( std::getline( infile, line )) {
for ( int x = 0; x < width; x++ ) {
if ( line[x] == '0' ) {
grid[ count * width + x ] = true;
} else {
grid[ count * width + x ] = false;
}
}
count++;
}
}
if ( play ) {
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( cudaMemcpy ( d_in, grid, gridSize, cudaMemcpyHostToDevice ) );
for (int step = 0; step < steps; step++) {
simulate<<< 1, 100 >>>( d_in, d_out, size[0], size[1], steps );
if ( play ) {
gpuErrchk( cudaMemcpy ( grid, d_out, gridSize, cudaMemcpyDeviceToHost ) );
gpuErrchk( cudaDeviceSynchronize() );
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( cudaMemcpy ( d_in, d_out, gridSize, cudaMemcpyHostToHost ) );
}
if ( !play ) {
// Wait for GPU to finish before accessing on host
gpuErrchk( cudaMemcpy ( grid, d_out, gridSize, cudaMemcpyDeviceToHost ) );
gpuErrchk( cudaDeviceSynchronize() );
printGrid( grid, size );
}
// Clean up memory allocations
free( grid );
cudaFree( d_in );
cudaFree( d_out );
exit( EXIT_SUCCESS );
} | .file "tmpxft_00104713_00000000-6_gol.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " [-i input.txt]/[-r] [-o output.txt] [-s 10]\n"
.section .rodata.str1.1
.LC2:
.string "Options:"
.section .rodata.str1.8
.align 8
.LC3:
.string "\t-h, --help\t\tShow this help message and exit"
.align 8
.LC4:
.string "\t-i, --input\t\tProvide an input file for the starting state"
.align 8
.LC5:
.string "\t-r, --random\t\tInstead start with a randomized starting state, provide a seed, 0 will set a random seed"
.align 8
.LC6:
.string "\t-o, --output\t\tOptionally save the final state as a file"
.align 8
.LC7:
.string "\t-s, --steps\t\tThe number of simulation step to take"
.align 8
.LC8:
.string "\t-p, --play\t\tOptionally play the simulation in the console"
#NO_APP
.text
.type _ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB5851:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rbx), %rdx
movq (%rbx), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5851:
.size _ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5856:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5856:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC9:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB5846:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L11
ret
.L11:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L12
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE5846:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z7getCellPbiiPi
.type _Z7getCellPbiiPi, @function
_Z7getCellPbiiPi:
.LFB5847:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE5847:
.size _Z7getCellPbiiPi, .-_Z7getCellPbiiPi
.globl _Z17getNeighbourCountPbiiPi
.type _Z17getNeighbourCountPbiiPi, @function
_Z17getNeighbourCountPbiiPi:
.LFB5848:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE5848:
.size _Z17getNeighbourCountPbiiPi, .-_Z17getNeighbourCountPbiiPi
.section .rodata.str1.1
.LC10:
.string "\033[2J;"
.LC11:
.string "\033[1;1H"
.text
.globl _Z5clearv
.type _Z5clearv, @function
_Z5clearv:
.LFB5849:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $5, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $6, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5849:
.size _Z5clearv, .-_Z5clearv
.section .rodata.str1.1
.LC12:
.string "0"
.LC13:
.string "."
.text
.globl _Z9printGridPbPi
.type _Z9printGridPbPi, @function
_Z9printGridPbPi:
.LFB5850:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movq %rsi, %rbp
movl $0, %r13d
leaq .LC13(%rip), %r15
leaq _ZSt4cout(%rip), %r12
cmpl $0, 4(%rsi)
jg .L20
.L19:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl $1, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L23:
addl $1, %ebx
cmpl %ebx, 0(%rbp)
jle .L28
.L24:
movl %r13d, %eax
imull 4(%rbp), %eax
addl %ebx, %eax
cltq
cmpb $0, (%r14,%rax)
je .L22
movl $1, %edx
leaq .LC12(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L23
.L28:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L26
movzbl 67(%rbx), %esi
.L27:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
cmpl %r13d, 4(%rbp)
jle .L19
.L20:
movl $0, %ebx
cmpl $0, 0(%rbp)
jg .L24
jmp .L28
.L35:
call _ZSt16__throw_bad_castv@PLT
.L26:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.cfi_endproc
.LFE5850:
.size _Z9printGridPbPi, .-_Z9printGridPbPi
.globl _Z32__device_stub__Z8simulatePbS_iiiPbS_iii
.type _Z32__device_stub__Z8simulatePbS_iiiPbS_iii, @function
_Z32__device_stub__Z8simulatePbS_iiiPbS_iii:
.LFB5878:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8simulatePbS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5878:
.size _Z32__device_stub__Z8simulatePbS_iiiPbS_iii, .-_Z32__device_stub__Z8simulatePbS_iiiPbS_iii
.globl _Z8simulatePbS_iii
.type _Z8simulatePbS_iii, @function
_Z8simulatePbS_iii:
.LFB5879:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8simulatePbS_iiiPbS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5879:
.size _Z8simulatePbS_iii, .-_Z8simulatePbS_iii
.section .rodata.str1.1
.LC14:
.string "_Z8simulatePbS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5881:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z8simulatePbS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5881:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB5955:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5955
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rcx
cmpq %rbp, %rcx
je .L60
cmpl $34, (%rbx)
je .L49
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L49
testq %r12, %r12
je .L52
subq %rbp, %rcx
movq %rcx, (%r12)
.L52:
cmpl $0, (%rbx)
jne .L46
movl %r15d, (%rbx)
.L46:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L62
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L62:
call __stack_chk_fail@PLT
.L49:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L63
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L58:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L55
movl %r15d, (%rbx)
.L55:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L56
call __stack_chk_fail@PLT
.L63:
call __stack_chk_fail@PLT
.L56:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5955:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA5955:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5955-.LLSDACSB5955
.LLSDACSB5955:
.uleb128 .LEHB0-.LFB5955
.uleb128 .LEHE0-.LEHB0
.uleb128 .L58-.LFB5955
.uleb128 0
.uleb128 .LEHB1-.LFB5955
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE5955:
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC15:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB6198:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L73
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L74
cmpq $1, %rax
jne .L69
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L70:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L76
leaq .LC15(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L76:
call __stack_chk_fail@PLT
.L74:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L68:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L70
.L69:
testq %rax, %rax
je .L70
jmp .L68
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6198:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .text._ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE:
.LFB6480:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %r12
movslq (%rdx), %rax
subq %rax, %r12
cmpq $2147483644, %r12
ja .L78
addq $1, %r12
movl $2147483645, %eax
movl $0, %edx
divq %r12
movq %rax, %r8
imulq %rax, %r12
movq (%rsi), %rdx
movabsq $8589934597, %rdi
.L79:
imulq $16807, %rdx, %rsi
movq %rsi, %rax
mulq %rdi
movq %rsi, %rcx
subq %rdx, %rcx
shrq %rcx
addq %rcx, %rdx
shrq $30, %rdx
movq %rdx, %rcx
salq $31, %rcx
subq %rdx, %rcx
subq %rcx, %rsi
movq %rsi, %rdx
leaq -1(%rsi), %rax
cmpq %r12, %rax
jnb .L79
movq %rsi, (%rbx)
movl $0, %edx
divq %r8
.L80:
addl 0(%rbp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L87
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
movq %rdi, %r13
cmpq $2147483645, %r12
jbe .L81
movq %r12, %rdx
shrq %rdx
movabsq $-9223372028264841207, %rcx
movq %rdx, %rax
mulq %rcx
shrq $29, %rdx
movl %edx, %r14d
movabsq $8589934597, %r15
.L85:
movl $0, (%rsp)
movl %r14d, 4(%rsp)
movq %rsp, %rdx
movq %rbx, %rsi
movq %r13, %rdi
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
cltq
movq %rax, %rcx
salq $30, %rcx
subq %rax, %rcx
addq %rcx, %rcx
imulq $16807, (%rbx), %rsi
movq %rsi, %rax
mulq %r15
movq %rsi, %rax
subq %rdx, %rax
shrq %rax
addq %rax, %rdx
shrq $30, %rdx
movq %rdx, %rax
salq $31, %rax
subq %rdx, %rax
subq %rax, %rsi
movq %rsi, (%rbx)
leaq -1(%rsi,%rcx), %rax
cmpq %rax, %r12
jb .L85
cmpq %rcx, %rax
jb .L85
jmp .L80
.L81:
imulq $16807, (%rsi), %rcx
movabsq $8589934597, %rdx
movq %rcx, %rax
mulq %rdx
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $30, %rax
movq %rax, %rdx
salq $31, %rdx
subq %rax, %rdx
movq %rcx, %rax
subq %rdx, %rax
movq %rax, (%rsi)
subq $1, %rax
jmp .L80
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6480:
.size _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
.section .rodata.str1.1
.LC16:
.string "hi:o:r:s:p"
.section .rodata.str1.8
.align 8
.LC17:
.string "/home/ubuntu/Datasets/stackv2/train-structured/paddypolson/cuda-game-of-life/master/gol.cu"
.section .rodata.str1.1
.LC18:
.string " "
.LC19:
.string "stoi"
.text
.globl main
.type main, @function
main:
.LFB5852:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5852
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1288, %rsp
.cfi_def_cfa_offset 1344
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 1272(%rsp)
xorl %eax, %eax
leaq 240(%rsp), %rdi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE2:
movl $10, 72(%rsp)
movl $10, 76(%rsp)
cmpl $1, %ebx
jle .L147
movl $0, %r14d
movl $0, %r15d
movb $0, 8(%rsp)
leaq .LC16(%rip), %r13
leaq .L92(%rip), %r12
.L89:
movq %r13, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call getopt@PLT
cmpl $-1, %eax
je .L148
subl $104, %eax
cmpl $11, %eax
ja .L90
movl %eax, %eax
movslq (%r12,%rax,4), %rax
addq %r12, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L92:
.long .L97-.L92
.long .L96-.L92
.long .L90-.L92
.long .L90-.L92
.long .L90-.L92
.long .L90-.L92
.long .L90-.L92
.long .L89-.L92
.long .L94-.L92
.long .L90-.L92
.long .L93-.L92
.long .L91-.L92
.text
.L147:
leaq 60(%rsp), %rdx
leaq 752(%rsp), %rdi
movq 0(%rbp), %rsi
.LEHB3:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE3:
leaq 752(%rsp), %rdi
.LEHB4:
call _ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE4:
leaq 752(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %edi
call exit@PLT
.L97:
leaq 60(%rsp), %rdx
leaq 752(%rsp), %rdi
movq 0(%rbp), %rsi
.LEHB5:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE5:
leaq 752(%rsp), %rdi
.LEHB6:
call _ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE6:
leaq 752(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %edi
call exit@PLT
.L96:
movq optarg(%rip), %rax
movq %rax, 24(%rsp)
jmp .L89
.L93:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 20(%rsp)
movb $1, 8(%rsp)
jmp .L89
.L91:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L89
.L90:
leaq 60(%rsp), %rdx
leaq 752(%rsp), %rdi
movq 0(%rbp), %rsi
.LEHB7:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE7:
leaq 752(%rsp), %rdi
.LEHB8:
call _ZL10show_usageNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE8:
leaq 752(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %edi
call exit@PLT
.L94:
movl $1, %r15d
jmp .L89
.L148:
movl $800, %edi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $800, %esi
.LEHB9:
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $180, %edx
leaq .LC17(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $181, %edx
leaq .LC17(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %r13, %r12
leaq 10(%r13), %rdx
leaq 110(%r13), %rcx
.L99:
leaq -10(%rdx), %rax
.L100:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L100
addq $10, %rdx
cmpq %rcx, %rdx
jne .L99
cmpb $0, 8(%rsp)
je .L102
cmpl $0, 20(%rsp)
je .L149
.L103:
movslq 20(%rsp), %rax
movl $2147483647, %ecx
movl $0, %edx
divq %rcx
testq %rdx, %rdx
movl $1, %eax
cmove %rax, %rdx
movq %rdx, 48(%rsp)
movl $0, 60(%rsp)
movl $1, 64(%rsp)
leaq 100(%r13), %rax
movq %rax, 8(%rsp)
leaq 60(%rsp), %rbp
.L104:
movq %r12, %rbx
.L105:
leaq 48(%rsp), %rsi
movq %rbp, %rdx
movq %rbp, %rdi
call _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
testl %eax, %eax
setne (%rbx)
addq $1, %rbx
leaq 10(%r12), %rax
cmpq %rax, %rbx
jne .L105
cmpq %rax, 8(%rsp)
je .L107
movq %rax, %r12
jmp .L104
.L149:
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movl %eax, 20(%rsp)
jmp .L103
.L102:
leaq 752(%rsp), %rdi
movl $8, %edx
movq 24(%rsp), %rsi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE9:
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $0, 88(%rsp)
movb $0, 96(%rsp)
leaq 60(%rsp), %rdx
leaq 112(%rsp), %rdi
leaq .LC18(%rip), %rsi
.LEHB10:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE10:
leaq 80(%rsp), %rsi
leaq 752(%rsp), %rdi
.LEHB11:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
leaq 80(%rsp), %rbx
movq 120(%rsp), %rcx
movl $0, %edx
movq 112(%rsp), %rsi
movq %rbx, %rdi
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@PLT
movq %rax, %rcx
leaq 144(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm@PLT
.LEHE11:
movq 120(%rsp), %rcx
movl $0, %edx
movq 112(%rsp), %rsi
movq %rbx, %rdi
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@PLT
addq 120(%rsp), %rax
movq %rax, %rdx
movl $0, %esi
movq %rbx, %rdi
.LEHB12:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE5eraseEmm@PLT
movq %rbx, %rsi
leaq 176(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_@PLT
.LEHE12:
movl $10, %r8d
movl $0, %ecx
movq 144(%rsp), %rdx
leaq .LC19(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB13:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
movl %eax, %ebp
movl $10, %r8d
movl $0, %ecx
movq 176(%rsp), %rdx
leaq .LC19(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE13:
leaq 224(%rsp), %rax
movq %rax, 208(%rsp)
movq $0, 216(%rsp)
movb $0, 224(%rsp)
movl $0, %ebx
movslq %ebp, %r12
jmp .L108
.L150:
leal (%rsi,%rax), %edx
movslq %edx, %rdx
movb $1, 0(%r13,%rdx)
.L110:
addq $1, %rax
cmpq %rcx, %rax
je .L114
.L111:
cmpb $48, (%rax)
je .L150
leal (%rsi,%rax), %edx
movslq %edx, %rdx
movb $0, 0(%r13,%rdx)
jmp .L110
.L114:
addl %ebp, %ebx
.L108:
leaq 208(%rsp), %rsi
leaq 752(%rsp), %rdi
.LEHB14:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE14:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L112
testl %ebp, %ebp
jle .L114
movq 208(%rsp), %rdx
leaq (%r12,%rdx), %rcx
movq %rdx, %rax
movl %ebx, %esi
subl %edx, %esi
jmp .L111
.L112:
leaq 208(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 176(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 752(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L107:
testb %r15b, %r15b
je .L115
.LEHB15:
call _Z5clearv
leaq 72(%rsp), %rsi
movq %r13, %rdi
call _Z9printGridPbPi
movl $1, %edi
call sleep@PLT
.L115:
movl $1, %ecx
movl $800, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $236, %edx
leaq .LC17(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
testl %r14d, %r14d
jle .L116
movl $0, %ebx
leaq .LC17(%rip), %rbp
jmp .L119
.L153:
testl %eax, %eax
je .L151
.L117:
testb %r15b, %r15b
je .L118
movl $2, %ecx
movl $800, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
jmp .L152
.L151:
movl %r14d, %r8d
movl $10, %ecx
movl $10, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z8simulatePbS_iiiPbS_iii
jmp .L117
.L152:
movl %eax, %edi
movl $1, %ecx
movl $243, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $244, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call _Z5clearv
leaq 72(%rsp), %rsi
movq %r13, %rdi
call _Z9printGridPbPi
movl $1, %edi
call sleep@PLT
.L118:
movl $0, %ecx
movl $800, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $250, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
addl $1, %ebx
cmpl %ebx, %r14d
je .L116
.L119:
movl $100, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L153
.L116:
testb %r15b, %r15b
jne .L120
movl $2, %ecx
movl $800, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $255, %edx
leaq .LC17(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $256, %edx
leaq .LC17(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 72(%rsp), %rsi
movq %r13, %rdi
call _Z9printGridPbPi
.L120:
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.LEHE15:
movl $0, %edi
call exit@PLT
.L133:
endbr64
movq %rax, %rbx
leaq 752(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L122:
leaq 240(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1272(%rsp), %rax
subq %fs:40, %rax
je .L130
call __stack_chk_fail@PLT
.L135:
endbr64
movq %rax, %rbx
leaq 752(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L122
.L136:
endbr64
movq %rax, %rbx
leaq 752(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L122
.L141:
endbr64
movq %rax, %rbx
leaq 208(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L126:
leaq 176(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L127:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L128:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L129:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 752(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L122
.L140:
endbr64
movq %rax, %rbx
jmp .L126
.L139:
endbr64
movq %rax, %rbx
jmp .L127
.L138:
endbr64
movq %rax, %rbx
jmp .L128
.L137:
endbr64
movq %rax, %rbx
jmp .L129
.L134:
endbr64
movq %rax, %rbx
jmp .L122
.L130:
movq %rbx, %rdi
.LEHB16:
call _Unwind_Resume@PLT
.LEHE16:
.cfi_endproc
.LFE5852:
.section .gcc_except_table,"a",@progbits
.LLSDA5852:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5852-.LLSDACSB5852
.LLSDACSB5852:
.uleb128 .LEHB2-.LFB5852
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB5852
.uleb128 .LEHE3-.LEHB3
.uleb128 .L134-.LFB5852
.uleb128 0
.uleb128 .LEHB4-.LFB5852
.uleb128 .LEHE4-.LEHB4
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.LLSDACSE5852:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <tuple>
#include <random>
#include <functional>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ bool getCell( bool* input, int x, int y, int* size ) {
if ( x < 0 ) { x = x + size[1]; }
else if ( x >= size[1] ) { x = x - size[1]; }
if ( y < 0 ) { y = y + size[0]; }
else if ( y >= size[0] ) { y = y - size[0]; }
return input[ y * size[0] + x ];
}
__device__ int getNeighbourCount( bool* input, int x, int y, int* size ) {
int count = 0;
if ( getCell( input, x - 1 , y - 1, size )) { count++; }
if ( getCell( input, x , y - 1, size )) { count++; }
if ( getCell( input, x + 1 , y - 1, size )) { count++; }
if ( getCell( input, x - 1 , y, size )) { count++; }
if ( getCell( input, x + 1 , y, size )) { count++; }
if ( getCell( input, x - 1 , y + 1, size )) { count++; }
if ( getCell( input, x , y + 1, size )) { count++; }
if ( getCell( input, x + 1 , y + 1, size )) { count++; }
return count;
}
__global__ void simulate( bool* input, bool* output, int width, int height, int steps ) {
int index = threadIdx.x;
int stride = blockDim.x;
if ( index >= ( width * height )) {
// Index out of range
printf("Out of range: %d\n", index);
return;
}
// Find X and Y
int y = index / width;
int x = index % width;
int size[2] = {width, height};
//printf("X: %d, Y: %d\n", x, y);
int count = getNeighbourCount( input, x, y, size );
if ( input[ index ] ) {
//printf("alive");
// Cell is alive
if ( count == 2 || count == 3 ) {
// Cell has 2 or 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
} else {
//printf("dead");
// Cell is dead
if ( count == 3 ) {
// Cell has exactly 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
}
}
/*
Clears screen and moves cursor to home pos on POSIX systems
*/
void clear() {
std::cout << "\033[2J;" << "\033[1;1H";
}
/*
*/
void printGrid( bool* grid, int* size ) {
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
if ( grid[ y * size[1] + x ] == true ) {
std::cout << "0";
}
else {
std::cout << ".";
}
}
std::cout << std::endl;
}
}
static void show_usage(std::string name)
{
std::cerr << "Usage: " << name << " [-i input.txt]/[-r] [-o output.txt] [-s 10]\n"
<< "Options:" << std::endl
<< "\t-h, --help\t\tShow this help message and exit" << std::endl
<< "\t-i, --input\t\tProvide an input file for the starting state" << std::endl
<< "\t-r, --random\t\tInstead start with a randomized starting state, provide a seed, 0 will set a random seed" << std::endl
<< "\t-o, --output\t\tOptionally save the final state as a file" << std::endl
<< "\t-s, --steps\t\tThe number of simulation step to take" << std::endl
<< "\t-p, --play\t\tOptionally play the simulation in the console" << std::endl
<< std::endl;
}
int main( int argc, char* argv[] ) {
int opt;
char* input;
char* output;
bool isRandom = false;
std::ofstream outfile;
bool play = false;
int seed;
int steps = 0;
int size[2] = {10, 10}; // x, y
int width, height;
int gridSize = size[1] * size[0] * sizeof(bool*);
bool* grid;
bool* d_in; // The read-only input array for kernel
bool* d_out; // The write-only output for kernel
if ( argc < 2 ) {
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
while (( opt = getopt(argc, argv, "hi:o:r:s:p" )) != -1 ) {
switch ( opt ) {
case 'h':
show_usage( argv[0] );
exit( EXIT_FAILURE );
break;
case 'i':
input = optarg;
break;
case 'o':
output = optarg;
break;
case 'r':
isRandom = true;
seed = atoi(optarg);
break;
case 's':
steps = atoi(optarg);
break;
case 'p':
play = true;
break;
default: /* '?' */
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
}
// Init empty grid
grid = (bool*) malloc( gridSize );
gpuErrchk( cudaMalloc( &d_in, gridSize ) );
gpuErrchk( cudaMalloc( &d_out, gridSize ) );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = false; // Init host grid to empty
}
}
if ( isRandom ) {
if ( ! seed ) {
seed = std::chrono::steady_clock::now().time_since_epoch().count();
}
std::default_random_engine engine(seed);
std::uniform_int_distribution<> boolGen( 0, 1 );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = boolGen( engine );
}
}
} else {
// File is assumed to have {width} {height} on the first line
std::ifstream infile( input );
std::string size_string;
std::string delimiter = " ";
// parsing string into two ints for width and height
std::getline( infile, size_string );
std::string str1 = size_string.substr( 0, size_string.find( delimiter ));
size_string.erase( 0, size_string.find( delimiter ) + delimiter.length() );
std::string str2 = size_string;
int width = stoi( str1 );
int height = stoi( str2 );
std::string line;
int count = 0; // current line count
while ( std::getline( infile, line )) {
for ( int x = 0; x < width; x++ ) {
if ( line[x] == '0' ) {
grid[ count * width + x ] = true;
} else {
grid[ count * width + x ] = false;
}
}
count++;
}
}
if ( play ) {
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( cudaMemcpy ( d_in, grid, gridSize, cudaMemcpyHostToDevice ) );
for (int step = 0; step < steps; step++) {
simulate<<< 1, 100 >>>( d_in, d_out, size[0], size[1], steps );
if ( play ) {
gpuErrchk( cudaMemcpy ( grid, d_out, gridSize, cudaMemcpyDeviceToHost ) );
gpuErrchk( cudaDeviceSynchronize() );
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( cudaMemcpy ( d_in, d_out, gridSize, cudaMemcpyHostToHost ) );
}
if ( !play ) {
// Wait for GPU to finish before accessing on host
gpuErrchk( cudaMemcpy ( grid, d_out, gridSize, cudaMemcpyDeviceToHost ) );
gpuErrchk( cudaDeviceSynchronize() );
printGrid( grid, size );
}
// Clean up memory allocations
free( grid );
cudaFree( d_in );
cudaFree( d_out );
exit( EXIT_SUCCESS );
} | #include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <tuple>
#include <random>
#include <functional>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ bool getCell( bool* input, int x, int y, int* size ) {
if ( x < 0 ) { x = x + size[1]; }
else if ( x >= size[1] ) { x = x - size[1]; }
if ( y < 0 ) { y = y + size[0]; }
else if ( y >= size[0] ) { y = y - size[0]; }
return input[ y * size[0] + x ];
}
__device__ int getNeighbourCount( bool* input, int x, int y, int* size ) {
int count = 0;
if ( getCell( input, x - 1 , y - 1, size )) { count++; }
if ( getCell( input, x , y - 1, size )) { count++; }
if ( getCell( input, x + 1 , y - 1, size )) { count++; }
if ( getCell( input, x - 1 , y, size )) { count++; }
if ( getCell( input, x + 1 , y, size )) { count++; }
if ( getCell( input, x - 1 , y + 1, size )) { count++; }
if ( getCell( input, x , y + 1, size )) { count++; }
if ( getCell( input, x + 1 , y + 1, size )) { count++; }
return count;
}
__global__ void simulate( bool* input, bool* output, int width, int height, int steps ) {
int index = threadIdx.x;
int stride = blockDim.x;
if ( index >= ( width * height )) {
// Index out of range
printf("Out of range: %d\n", index);
return;
}
// Find X and Y
int y = index / width;
int x = index % width;
int size[2] = {width, height};
//printf("X: %d, Y: %d\n", x, y);
int count = getNeighbourCount( input, x, y, size );
if ( input[ index ] ) {
//printf("alive");
// Cell is alive
if ( count == 2 || count == 3 ) {
// Cell has 2 or 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
} else {
//printf("dead");
// Cell is dead
if ( count == 3 ) {
// Cell has exactly 3 neighbours
output[ index ] = true;
} else {
output[ index ] = false;
}
}
}
/*
Clears screen and moves cursor to home pos on POSIX systems
*/
void clear() {
std::cout << "\033[2J;" << "\033[1;1H";
}
/*
*/
void printGrid( bool* grid, int* size ) {
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
if ( grid[ y * size[1] + x ] == true ) {
std::cout << "0";
}
else {
std::cout << ".";
}
}
std::cout << std::endl;
}
}
static void show_usage(std::string name)
{
std::cerr << "Usage: " << name << " [-i input.txt]/[-r] [-o output.txt] [-s 10]\n"
<< "Options:" << std::endl
<< "\t-h, --help\t\tShow this help message and exit" << std::endl
<< "\t-i, --input\t\tProvide an input file for the starting state" << std::endl
<< "\t-r, --random\t\tInstead start with a randomized starting state, provide a seed, 0 will set a random seed" << std::endl
<< "\t-o, --output\t\tOptionally save the final state as a file" << std::endl
<< "\t-s, --steps\t\tThe number of simulation step to take" << std::endl
<< "\t-p, --play\t\tOptionally play the simulation in the console" << std::endl
<< std::endl;
}
int main( int argc, char* argv[] ) {
int opt;
char* input;
char* output;
bool isRandom = false;
std::ofstream outfile;
bool play = false;
int seed;
int steps = 0;
int size[2] = {10, 10}; // x, y
int width, height;
int gridSize = size[1] * size[0] * sizeof(bool*);
bool* grid;
bool* d_in; // The read-only input array for kernel
bool* d_out; // The write-only output for kernel
if ( argc < 2 ) {
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
while (( opt = getopt(argc, argv, "hi:o:r:s:p" )) != -1 ) {
switch ( opt ) {
case 'h':
show_usage( argv[0] );
exit( EXIT_FAILURE );
break;
case 'i':
input = optarg;
break;
case 'o':
output = optarg;
break;
case 'r':
isRandom = true;
seed = atoi(optarg);
break;
case 's':
steps = atoi(optarg);
break;
case 'p':
play = true;
break;
default: /* '?' */
show_usage( argv[0] );
exit( EXIT_FAILURE );
}
}
// Init empty grid
grid = (bool*) malloc( gridSize );
gpuErrchk( hipMalloc( &d_in, gridSize ) );
gpuErrchk( hipMalloc( &d_out, gridSize ) );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = false; // Init host grid to empty
}
}
if ( isRandom ) {
if ( ! seed ) {
seed = std::chrono::steady_clock::now().time_since_epoch().count();
}
std::default_random_engine engine(seed);
std::uniform_int_distribution<> boolGen( 0, 1 );
for ( int y = 0; y < size[1]; y++ ) {
for ( int x = 0; x < size[0]; x++ ) {
grid[ y * size[1] + x ] = boolGen( engine );
}
}
} else {
// File is assumed to have {width} {height} on the first line
std::ifstream infile( input );
std::string size_string;
std::string delimiter = " ";
// parsing string into two ints for width and height
std::getline( infile, size_string );
std::string str1 = size_string.substr( 0, size_string.find( delimiter ));
size_string.erase( 0, size_string.find( delimiter ) + delimiter.length() );
std::string str2 = size_string;
int width = stoi( str1 );
int height = stoi( str2 );
std::string line;
int count = 0; // current line count
while ( std::getline( infile, line )) {
for ( int x = 0; x < width; x++ ) {
if ( line[x] == '0' ) {
grid[ count * width + x ] = true;
} else {
grid[ count * width + x ] = false;
}
}
count++;
}
}
if ( play ) {
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( hipMemcpy ( d_in, grid, gridSize, hipMemcpyHostToDevice ) );
for (int step = 0; step < steps; step++) {
simulate<<< 1, 100 >>>( d_in, d_out, size[0], size[1], steps );
if ( play ) {
gpuErrchk( hipMemcpy ( grid, d_out, gridSize, hipMemcpyDeviceToHost ) );
gpuErrchk( hipDeviceSynchronize() );
clear();
printGrid( grid, size );
sleep( 1 );
}
gpuErrchk( hipMemcpy ( d_in, d_out, gridSize, hipMemcpyHostToHost ) );
}
if ( !play ) {
// Wait for GPU to finish before accessing on host
gpuErrchk( hipMemcpy ( grid, d_out, gridSize, hipMemcpyDeviceToHost ) );
gpuErrchk( hipDeviceSynchronize() );
printGrid( grid, size );
}
// Clean up memory allocations
free( grid );
hipFree( d_in );
hipFree( d_out );
exit( EXIT_SUCCESS );
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void partialSumKernel(int *X, int N)
{
__shared__ int partialSum[2 * BLOCK_SIZE];
int tx = threadIdx.x;
int i = blockIdx.x * blockDim.x + tx;
partialSum[tx] = (i < N) ? X[i] : 0;
partialSum[tx + blockDim.x] = 0;
for (int stride = blockDim.x; stride > 0; stride = stride/2)
{
__syncthreads();
if (tx <= stride) {
partialSum[tx] += partialSum[tx + stride];
//printf("tx[%d], bx[%d]: %d + %d\n", tx, blockIdx.x, partialSum[tx], partialSum[tx + stride]);
}
}
if (tx == 0)
X[blockIdx.x] = partialSum[tx];
} | code for sm_80
Function : _Z16partialSumKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fca00078e0203 */
/*0090*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ SHF.L.U32 R5, R7.reuse, 0x2, RZ ; /* 0x0000000207057819 */
/* 0x040fe400000006ff */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*00d0*/ ISETP.GE.AND P1, PT, R4.reuse, 0x1, PT ; /* 0x000000010400780c */
/* 0x040fe20003f26270 */
/*00e0*/ IMAD R4, R4, 0x4, R5 ; /* 0x0000000404047824 */
/* 0x000fe200078e0205 */
/*00f0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*0100*/ STS [R4], RZ ; /* 0x000000ff04007388 */
/* 0x0001ee0000000800 */
/*0110*/ @!P1 BRA 0x1d0 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x001fc60000000f00 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GT.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24270 */
/*0150*/ @!P1 IMAD R2, R0, 0x4, R5 ; /* 0x0000000400029824 */
/* 0x000fe200078e0205 */
/*0160*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*0170*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe80000004800 */
/*0180*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0190*/ @!P1 IADD3 R3, R3, R2, RZ ; /* 0x0000000203039210 */
/* 0x001fca0007ffe0ff */
/*01a0*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e20000004800 */
/*01b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void partialSumKernel(int *X, int N)
{
__shared__ int partialSum[2 * BLOCK_SIZE];
int tx = threadIdx.x;
int i = blockIdx.x * blockDim.x + tx;
partialSum[tx] = (i < N) ? X[i] : 0;
partialSum[tx + blockDim.x] = 0;
for (int stride = blockDim.x; stride > 0; stride = stride/2)
{
__syncthreads();
if (tx <= stride) {
partialSum[tx] += partialSum[tx + stride];
//printf("tx[%d], bx[%d]: %d + %d\n", tx, blockIdx.x, partialSum[tx], partialSum[tx + stride]);
}
}
if (tx == 0)
X[blockIdx.x] = partialSum[tx];
} | .file "tmpxft_0012834c_00000000-6_partialSumKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16partialSumKernelPiiPii
.type _Z37__device_stub__Z16partialSumKernelPiiPii, @function
_Z37__device_stub__Z16partialSumKernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16partialSumKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16partialSumKernelPiiPii, .-_Z37__device_stub__Z16partialSumKernelPiiPii
.globl _Z16partialSumKernelPii
.type _Z16partialSumKernelPii, @function
_Z16partialSumKernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16partialSumKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16partialSumKernelPii, .-_Z16partialSumKernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16partialSumKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16partialSumKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void partialSumKernel(int *X, int N)
{
__shared__ int partialSum[2 * BLOCK_SIZE];
int tx = threadIdx.x;
int i = blockIdx.x * blockDim.x + tx;
partialSum[tx] = (i < N) ? X[i] : 0;
partialSum[tx + blockDim.x] = 0;
for (int stride = blockDim.x; stride > 0; stride = stride/2)
{
__syncthreads();
if (tx <= stride) {
partialSum[tx] += partialSum[tx + stride];
//printf("tx[%d], bx[%d]: %d + %d\n", tx, blockIdx.x, partialSum[tx], partialSum[tx + stride]);
}
}
if (tx == 0)
X[blockIdx.x] = partialSum[tx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void partialSumKernel(int *X, int N)
{
__shared__ int partialSum[2 * BLOCK_SIZE];
int tx = threadIdx.x;
int i = blockIdx.x * blockDim.x + tx;
partialSum[tx] = (i < N) ? X[i] : 0;
partialSum[tx + blockDim.x] = 0;
for (int stride = blockDim.x; stride > 0; stride = stride/2)
{
__syncthreads();
if (tx <= stride) {
partialSum[tx] += partialSum[tx + stride];
//printf("tx[%d], bx[%d]: %d + %d\n", tx, blockIdx.x, partialSum[tx], partialSum[tx + stride]);
}
}
if (tx == 0)
X[blockIdx.x] = partialSum[tx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void partialSumKernel(int *X, int N)
{
__shared__ int partialSum[2 * BLOCK_SIZE];
int tx = threadIdx.x;
int i = blockIdx.x * blockDim.x + tx;
partialSum[tx] = (i < N) ? X[i] : 0;
partialSum[tx + blockDim.x] = 0;
for (int stride = blockDim.x; stride > 0; stride = stride/2)
{
__syncthreads();
if (tx <= stride) {
partialSum[tx] += partialSum[tx + stride];
//printf("tx[%d], bx[%d]: %d + %d\n", tx, blockIdx.x, partialSum[tx], partialSum[tx + stride]);
}
}
if (tx == 0)
X[blockIdx.x] = partialSum[tx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16partialSumKernelPii
.globl _Z16partialSumKernelPii
.p2align 8
.type _Z16partialSumKernelPii,@function
_Z16partialSumKernelPii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v1, 2, v0
v_add_lshl_u32 v3, v0, s3, 2
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
ds_store_b32 v3, v4
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
ds_load_b32 v0, v1
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_3
.LBB0_7:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16partialSumKernelPii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16partialSumKernelPii, .Lfunc_end0-_Z16partialSumKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16partialSumKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16partialSumKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void partialSumKernel(int *X, int N)
{
__shared__ int partialSum[2 * BLOCK_SIZE];
int tx = threadIdx.x;
int i = blockIdx.x * blockDim.x + tx;
partialSum[tx] = (i < N) ? X[i] : 0;
partialSum[tx + blockDim.x] = 0;
for (int stride = blockDim.x; stride > 0; stride = stride/2)
{
__syncthreads();
if (tx <= stride) {
partialSum[tx] += partialSum[tx + stride];
//printf("tx[%d], bx[%d]: %d + %d\n", tx, blockIdx.x, partialSum[tx], partialSum[tx + stride]);
}
}
if (tx == 0)
X[blockIdx.x] = partialSum[tx];
} | .text
.file "partialSumKernel.hip"
.globl _Z31__device_stub__partialSumKernelPii # -- Begin function _Z31__device_stub__partialSumKernelPii
.p2align 4, 0x90
.type _Z31__device_stub__partialSumKernelPii,@function
_Z31__device_stub__partialSumKernelPii: # @_Z31__device_stub__partialSumKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16partialSumKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__partialSumKernelPii, .Lfunc_end0-_Z31__device_stub__partialSumKernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16partialSumKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16partialSumKernelPii,@object # @_Z16partialSumKernelPii
.section .rodata,"a",@progbits
.globl _Z16partialSumKernelPii
.p2align 3, 0x0
_Z16partialSumKernelPii:
.quad _Z31__device_stub__partialSumKernelPii
.size _Z16partialSumKernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16partialSumKernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__partialSumKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16partialSumKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16partialSumKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fca00078e0203 */
/*0090*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ SHF.L.U32 R5, R7.reuse, 0x2, RZ ; /* 0x0000000207057819 */
/* 0x040fe400000006ff */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*00d0*/ ISETP.GE.AND P1, PT, R4.reuse, 0x1, PT ; /* 0x000000010400780c */
/* 0x040fe20003f26270 */
/*00e0*/ IMAD R4, R4, 0x4, R5 ; /* 0x0000000404047824 */
/* 0x000fe200078e0205 */
/*00f0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*0100*/ STS [R4], RZ ; /* 0x000000ff04007388 */
/* 0x0001ee0000000800 */
/*0110*/ @!P1 BRA 0x1d0 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x001fc60000000f00 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GT.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24270 */
/*0150*/ @!P1 IMAD R2, R0, 0x4, R5 ; /* 0x0000000400029824 */
/* 0x000fe200078e0205 */
/*0160*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*0170*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe80000004800 */
/*0180*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0190*/ @!P1 IADD3 R3, R3, R2, RZ ; /* 0x0000000203039210 */
/* 0x001fca0007ffe0ff */
/*01a0*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e20000004800 */
/*01b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16partialSumKernelPii
.globl _Z16partialSumKernelPii
.p2align 8
.type _Z16partialSumKernelPii,@function
_Z16partialSumKernelPii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v1, 2, v0
v_add_lshl_u32 v3, v0, s3, 2
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
ds_store_b32 v3, v4
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
ds_load_b32 v0, v1
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_3
.LBB0_7:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_ge_u32_e64 s3, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16partialSumKernelPii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16partialSumKernelPii, .Lfunc_end0-_Z16partialSumKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16partialSumKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16partialSumKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012834c_00000000-6_partialSumKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16partialSumKernelPiiPii
.type _Z37__device_stub__Z16partialSumKernelPiiPii, @function
_Z37__device_stub__Z16partialSumKernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16partialSumKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16partialSumKernelPiiPii, .-_Z37__device_stub__Z16partialSumKernelPiiPii
.globl _Z16partialSumKernelPii
.type _Z16partialSumKernelPii, @function
_Z16partialSumKernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16partialSumKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16partialSumKernelPii, .-_Z16partialSumKernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16partialSumKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16partialSumKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "partialSumKernel.hip"
.globl _Z31__device_stub__partialSumKernelPii # -- Begin function _Z31__device_stub__partialSumKernelPii
.p2align 4, 0x90
.type _Z31__device_stub__partialSumKernelPii,@function
_Z31__device_stub__partialSumKernelPii: # @_Z31__device_stub__partialSumKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16partialSumKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__partialSumKernelPii, .Lfunc_end0-_Z31__device_stub__partialSumKernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16partialSumKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16partialSumKernelPii,@object # @_Z16partialSumKernelPii
.section .rodata,"a",@progbits
.globl _Z16partialSumKernelPii
.p2align 3, 0x0
_Z16partialSumKernelPii:
.quad _Z31__device_stub__partialSumKernelPii
.size _Z16partialSumKernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16partialSumKernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__partialSumKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16partialSumKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addRows(double *matrix, int *d_i){
int i=*d_i;
int n=blockDim.x+i;
int id= n*(blockIdx.x+i+1) + threadIdx.x+i;
__shared__ double multiplier;
if(threadIdx.x==0){
multiplier=matrix[n*(blockIdx.x+1+i)+i]/matrix[n*i+i];
}
__syncthreads();
matrix[id]-=matrix[n*i+threadIdx.x+i]*multiplier;
} | code for sm_80
Function : _Z7addRowsPdPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0050*/ BSSY B0, 0x280 ; /* 0x0000022000007945 */
/* 0x000fe60003800000 */
/*0060*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e280000002100 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002500 */
/*0080*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x001fe40003f05270 */
/*0090*/ IADD3 R5, R0, 0x1, R15 ; /* 0x0000000100057810 */
/* 0x004fc40007ffe00f */
/*00a0*/ IADD3 R12, R15, c[0x0][0x0], RZ ; /* 0x000000000f0c7a10 */
/* 0x000fca0007ffe0ff */
/*00b0*/ IMAD R0, R12, R5, RZ ; /* 0x000000050c007224 */
/* 0x000fc800078e02ff */
/*00c0*/ @P0 BRA 0x270 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD R4, R15, R12, R15 ; /* 0x0000000c0f047224 */
/* 0x000fc800078e020f */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0209 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.IADD R8, R15, 0x1, R0 ; /* 0x000000010f087824 */
/* 0x000fc800078e0200 */
/*0120*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0009 */
/*0130*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1b00 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0150*/ MUFU.RCP64H R3, R5 ; /* 0x0000000500037308 */
/* 0x004e220000001800 */
/*0160*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x008fc80003f2e200 */
/*0170*/ DFMA R6, -R4, R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000102 */
/*0180*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0190*/ DFMA R6, R2, R6, R2 ; /* 0x000000060206722b */
/* 0x001e0c0000000002 */
/*01a0*/ DFMA R2, -R4, R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000106 */
/*01b0*/ DFMA R2, R6, R2, R6 ; /* 0x000000020602722b */
/* 0x001e0c0000000006 */
/*01c0*/ DMUL R6, R8, R2 ; /* 0x0000000208067228 */
/* 0x001e0c0000000000 */
/*01d0*/ DFMA R10, -R4, R6, R8 ; /* 0x00000006040a722b */
/* 0x001e0c0000000108 */
/*01e0*/ DFMA R2, R2, R10, R6 ; /* 0x0000000a0202722b */
/* 0x001e140000000006 */
/*01f0*/ FFMA R6, RZ, R5, R3 ; /* 0x00000005ff067223 */
/* 0x001fca0000000003 */
/*0200*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0210*/ @P0 BRA P1, 0x260 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0220*/ MOV R14, 0x240 ; /* 0x00000240000e7802 */
/* 0x000fe40000000f00 */
/*0230*/ CALL.REL.NOINC 0x350 ; /* 0x0000011000007944 */
/* 0x000fea0003c00000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000b */
/*0260*/ STS.64 [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0001e40000000a00 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ IMAD.IADD R13, R15.reuse, 0x1, R13 ; /* 0x000000010f0d7824 */
/* 0x040fe400078e020d */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD R2, R15, R12, R13.reuse ; /* 0x0000000c0f027224 */
/* 0x101fe400078e020d */
/*02c0*/ IMAD.IADD R6, R0, 0x1, R13 ; /* 0x0000000100067824 */
/* 0x000fe400078e020d */
/*02d0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0007 */
/*02e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0207 */
/*02f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0310*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000ea40000000a00 */
/*0320*/ DFMA R4, R4, -R2, R8 ; /* 0x800000020404722b */
/* 0x004e0e0000000008 */
/*0330*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0370*/ LOP3.LUT R2, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05027812 */
/* 0x040fe200078ec0ff */
/*0380*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff157424 */
/* 0x000fe200078e00ff */
/*0390*/ LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005167812 */
/* 0x000fe400078ec0ff */
/*03a0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*03c0*/ LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009147812 */
/* 0x000fc800078ec0ff */
/*03d0*/ ISETP.GE.U32.AND P1, PT, R20, R22, PT ; /* 0x000000161400720c */
/* 0x000fe20003f26070 */
/*03e0*/ @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004028828 */
/* 0x000e220000000000 */
/*03f0*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0014 */
/*0400*/ SEL R17, R21, 0x63400000, !P1 ; /* 0x6340000015117807 */
/* 0x000fe40004800000 */
/*0410*/ FSETP.GEU.AND P1, PT, |R9|, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x000fe20003f2e200 */
/*0420*/ MUFU.RCP64H R7, R3 ; /* 0x0000000300077308 */
/* 0x001e280000001800 */
/*0430*/ @!P0 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003168812 */
/* 0x000fe200078ec0ff */
/*0440*/ DFMA R10, R6, -R2, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000802 */
/*0450*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0460*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*0470*/ DFMA R6, R10, -R2, 1 ; /* 0x3ff000000a06742b */
/* 0x001e0c0000000802 */
/*0480*/ DFMA R10, R10, R6, R10 ; /* 0x000000060a0a722b */
/* 0x001064000000000a */
/*0490*/ LOP3.LUT R7, R17, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff11077812 */
/* 0x001fe200078ef809 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*04b0*/ @P1 BRA 0x540 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005117812 */
/* 0x002fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R20, R17, PT ; /* 0x000000111400720c */
/* 0x000fc80003f06070 */
/*04f0*/ SEL R17, R21, 0x63400000, !P0 ; /* 0x6340000015117807 */
/* 0x000fc80004000000 */
/*0500*/ LOP3.LUT R17, R17, 0x80000000, R9, 0xf8, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ef809 */
/*0510*/ LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000011117812 */
/* 0x000fcc00078efcff */
/*0520*/ DFMA R6, R6, 2, -R16 ; /* 0x400000000606782b */
/* 0x000e140000000810 */
/*0530*/ LOP3.LUT R23, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007177812 */
/* 0x001fc800078ec0ff */
/*0540*/ IADD3 R18, R23, -0x1, RZ ; /* 0xffffffff17127810 */
/* 0x002fe20007ffe0ff */
/*0550*/ DMUL R16, R10, R6 ; /* 0x000000060a107228 */
/* 0x000e220000000000 */
/*0560*/ IADD3 R24, R22, -0x1, RZ ; /* 0xffffffff16187810 */
/* 0x000fe40007ffe0ff */
/*0570*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*0580*/ DFMA R18, R16, -R2, R6 ; /* 0x800000021012722b */
/* 0x001e220000000006 */
/*0590*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fca0000704470 */
/*05a0*/ DFMA R18, R10, R18, R16 ; /* 0x000000120a12722b */
/* 0x0010500000000010 */
/*05b0*/ @P0 BRA 0x780 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*05c0*/ LOP3.LUT R9, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005097812 */
/* 0x003fc800078ec0ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R20.reuse, R9, PT ; /* 0x000000091400720c */
/* 0x040fe20003f06070 */
/*05e0*/ IMAD.IADD R8, R20, 0x1, -R9 ; /* 0x0000000114087824 */
/* 0x000fc600078e0a09 */
/*05f0*/ SEL R21, R21, 0x63400000, !P0 ; /* 0x6340000015157807 */
/* 0x000fe40004000000 */
/*0600*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*0610*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0620*/ IMAD.IADD R16, R8, 0x1, -R21 ; /* 0x0000000108107824 */
/* 0x000fe400078e0a15 */
/*0630*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0640*/ IADD3 R9, R16, 0x7fe00000, RZ ; /* 0x7fe0000010097810 */
/* 0x000fcc0007ffe0ff */
/*0650*/ DMUL R10, R18, R8 ; /* 0x00000008120a7228 */
/* 0x000e140000000000 */
/*0660*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*0670*/ @P0 BRA 0x8d0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0680*/ DFMA R2, R18, -R2, R6 ; /* 0x800000021202722b */
/* 0x000e220000000006 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*06a0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*06b0*/ LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003057812 */
/* 0x000fc800078e4805 */
/*06c0*/ LOP3.LUT R9, R5, R9, RZ, 0xfc, !PT ; /* 0x0000000905097212 */
/* 0x000fce00078efcff */
/*06d0*/ @!P0 BRA 0x8d0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV R3, RZ, RZ, -R16 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a10 */
/*06f0*/ DMUL.RP R8, R18, R8 ; /* 0x0000000812087228 */
/* 0x000e220000008000 */
/*0700*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0710*/ DFMA R2, R10, -R2, R18 ; /* 0x800000020a02722b */
/* 0x000e460000000012 */
/*0720*/ LOP3.LUT R5, R9, R5, RZ, 0x3c, !PT ; /* 0x0000000509057212 */
/* 0x001fc600078e3cff */
/*0730*/ IADD3 R2, -R16, -0x43300000, RZ ; /* 0xbcd0000010027810 */
/* 0x002fc80007ffe1ff */
/*0740*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0750*/ FSEL R10, R8, R10, !P0 ; /* 0x0000000a080a7208 */
/* 0x000fe40004000000 */
/*0760*/ FSEL R11, R5, R11, !P0 ; /* 0x0000000b050b7208 */
/* 0x000fe20004000000 */
/*0770*/ BRA 0x8d0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0780*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*0790*/ @P0 BRA 0x8b0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*07a0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*07b0*/ @P0 BRA 0x880 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, R23, R22, PT ; /* 0x000000161700720c */
/* 0x000fe20003f05270 */
/*07d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*07e0*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fd400078e00ff */
/*07f0*/ @!P0 BRA 0x8d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.NE.AND P0, PT, R23, 0x7ff00000, PT ; /* 0x7ff000001700780c */
/* 0x000fe40003f05270 */
/*0810*/ LOP3.LUT R11, R9, 0x80000000, R5, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fe400078e4805 */
/*0820*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0830*/ @P0 LOP3.LUT R2, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b020812 */
/* 0x000fe200078efcff */
/*0840*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*0850*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0860*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0002 */
/*0870*/ BRA 0x8d0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050b7812 */
/* 0x000fe200078efcff */
/*0890*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*08a0*/ BRA 0x8d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R11, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090b7812 */
/* 0x000fe200078efcff */
/*08c0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000e */
/*08e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff70002007950 */
/* 0x000fea0003c3ffff */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addRows(double *matrix, int *d_i){
int i=*d_i;
int n=blockDim.x+i;
int id= n*(blockIdx.x+i+1) + threadIdx.x+i;
__shared__ double multiplier;
if(threadIdx.x==0){
multiplier=matrix[n*(blockIdx.x+1+i)+i]/matrix[n*i+i];
}
__syncthreads();
matrix[id]-=matrix[n*i+threadIdx.x+i]*multiplier;
} | .file "tmpxft_000ae33a_00000000-6_addRows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7addRowsPdPiPdPi
.type _Z28__device_stub__Z7addRowsPdPiPdPi, @function
_Z28__device_stub__Z7addRowsPdPiPdPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7addRowsPdPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7addRowsPdPiPdPi, .-_Z28__device_stub__Z7addRowsPdPiPdPi
.globl _Z7addRowsPdPi
.type _Z7addRowsPdPi, @function
_Z7addRowsPdPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7addRowsPdPiPdPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7addRowsPdPi, .-_Z7addRowsPdPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7addRowsPdPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7addRowsPdPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addRows(double *matrix, int *d_i){
int i=*d_i;
int n=blockDim.x+i;
int id= n*(blockIdx.x+i+1) + threadIdx.x+i;
__shared__ double multiplier;
if(threadIdx.x==0){
multiplier=matrix[n*(blockIdx.x+1+i)+i]/matrix[n*i+i];
}
__syncthreads();
matrix[id]-=matrix[n*i+threadIdx.x+i]*multiplier;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addRows(double *matrix, int *d_i){
int i=*d_i;
int n=blockDim.x+i;
int id= n*(blockIdx.x+i+1) + threadIdx.x+i;
__shared__ double multiplier;
if(threadIdx.x==0){
multiplier=matrix[n*(blockIdx.x+1+i)+i]/matrix[n*i+i];
}
__syncthreads();
matrix[id]-=matrix[n*i+threadIdx.x+i]*multiplier;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addRows(double *matrix, int *d_i){
int i=*d_i;
int n=blockDim.x+i;
int id= n*(blockIdx.x+i+1) + threadIdx.x+i;
__shared__ double multiplier;
if(threadIdx.x==0){
multiplier=matrix[n*(blockIdx.x+1+i)+i]/matrix[n*i+i];
}
__syncthreads();
matrix[id]-=matrix[n*i+threadIdx.x+i]*multiplier;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7addRowsPdPi
.globl _Z7addRowsPdPi
.p2align 8
.type _Z7addRowsPdPi,@function
_Z7addRowsPdPi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x1c
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[6:7], 0x0
s_and_b32 s0, s0, 0xffff
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, s0
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_add_i32 s0, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, 1
s_mul_i32 s0, s3, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s2
s_lshl_b64 s[0:1], s[0:1], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_i32 s7, s3, 1
s_mul_i32 s8, s7, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_clause 0x1
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[1:2], null, s[8:9], s[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[3:4], v[1:2]
s_waitcnt_depctr 0xfff
v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
v_div_scale_f64 v[5:6], vcc_lo, s[0:1], s[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[5:6], v[3:4]
v_fma_f64 v[1:2], -v[1:2], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[1:2], v[1:2], v[3:4], v[7:8]
v_mov_b32_e32 v3, 0
v_div_fixup_f64 v[1:2], v[1:2], s[8:9], s[0:1]
ds_store_b64 v3, v[1:2]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v0, s2, v0
s_add_i32 s0, s15, s2
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, 1
s_barrier
v_mad_u64_u32 v[1:2], null, s3, s0, v[0:1]
buffer_gl0_inv
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_lshlrev_b64 v[5:6], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[5:6], v[0:1], off
ds_load_b64 v[7:8], v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[2:3], -v[2:3], v[7:8], v[5:6]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7addRowsPdPi
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7addRowsPdPi, .Lfunc_end0-_Z7addRowsPdPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7addRowsPdPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7addRowsPdPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addRows(double *matrix, int *d_i){
int i=*d_i;
int n=blockDim.x+i;
int id= n*(blockIdx.x+i+1) + threadIdx.x+i;
__shared__ double multiplier;
if(threadIdx.x==0){
multiplier=matrix[n*(blockIdx.x+1+i)+i]/matrix[n*i+i];
}
__syncthreads();
matrix[id]-=matrix[n*i+threadIdx.x+i]*multiplier;
} | .text
.file "addRows.hip"
.globl _Z22__device_stub__addRowsPdPi # -- Begin function _Z22__device_stub__addRowsPdPi
.p2align 4, 0x90
.type _Z22__device_stub__addRowsPdPi,@function
_Z22__device_stub__addRowsPdPi: # @_Z22__device_stub__addRowsPdPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7addRowsPdPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__addRowsPdPi, .Lfunc_end0-_Z22__device_stub__addRowsPdPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7addRowsPdPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7addRowsPdPi,@object # @_Z7addRowsPdPi
.section .rodata,"a",@progbits
.globl _Z7addRowsPdPi
.p2align 3, 0x0
_Z7addRowsPdPi:
.quad _Z22__device_stub__addRowsPdPi
.size _Z7addRowsPdPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7addRowsPdPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__addRowsPdPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7addRowsPdPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7addRowsPdPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0050*/ BSSY B0, 0x280 ; /* 0x0000022000007945 */
/* 0x000fe60003800000 */
/*0060*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e280000002100 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002500 */
/*0080*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x001fe40003f05270 */
/*0090*/ IADD3 R5, R0, 0x1, R15 ; /* 0x0000000100057810 */
/* 0x004fc40007ffe00f */
/*00a0*/ IADD3 R12, R15, c[0x0][0x0], RZ ; /* 0x000000000f0c7a10 */
/* 0x000fca0007ffe0ff */
/*00b0*/ IMAD R0, R12, R5, RZ ; /* 0x000000050c007224 */
/* 0x000fc800078e02ff */
/*00c0*/ @P0 BRA 0x270 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD R4, R15, R12, R15 ; /* 0x0000000c0f047224 */
/* 0x000fc800078e020f */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0209 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.IADD R8, R15, 0x1, R0 ; /* 0x000000010f087824 */
/* 0x000fc800078e0200 */
/*0120*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0009 */
/*0130*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1b00 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0150*/ MUFU.RCP64H R3, R5 ; /* 0x0000000500037308 */
/* 0x004e220000001800 */
/*0160*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x008fc80003f2e200 */
/*0170*/ DFMA R6, -R4, R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000102 */
/*0180*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0190*/ DFMA R6, R2, R6, R2 ; /* 0x000000060206722b */
/* 0x001e0c0000000002 */
/*01a0*/ DFMA R2, -R4, R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000106 */
/*01b0*/ DFMA R2, R6, R2, R6 ; /* 0x000000020602722b */
/* 0x001e0c0000000006 */
/*01c0*/ DMUL R6, R8, R2 ; /* 0x0000000208067228 */
/* 0x001e0c0000000000 */
/*01d0*/ DFMA R10, -R4, R6, R8 ; /* 0x00000006040a722b */
/* 0x001e0c0000000108 */
/*01e0*/ DFMA R2, R2, R10, R6 ; /* 0x0000000a0202722b */
/* 0x001e140000000006 */
/*01f0*/ FFMA R6, RZ, R5, R3 ; /* 0x00000005ff067223 */
/* 0x001fca0000000003 */
/*0200*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0210*/ @P0 BRA P1, 0x260 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0220*/ MOV R14, 0x240 ; /* 0x00000240000e7802 */
/* 0x000fe40000000f00 */
/*0230*/ CALL.REL.NOINC 0x350 ; /* 0x0000011000007944 */
/* 0x000fea0003c00000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000b */
/*0260*/ STS.64 [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0001e40000000a00 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ IMAD.IADD R13, R15.reuse, 0x1, R13 ; /* 0x000000010f0d7824 */
/* 0x040fe400078e020d */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD R2, R15, R12, R13.reuse ; /* 0x0000000c0f027224 */
/* 0x101fe400078e020d */
/*02c0*/ IMAD.IADD R6, R0, 0x1, R13 ; /* 0x0000000100067824 */
/* 0x000fe400078e020d */
/*02d0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0007 */
/*02e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e0207 */
/*02f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0310*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000ea40000000a00 */
/*0320*/ DFMA R4, R4, -R2, R8 ; /* 0x800000020404722b */
/* 0x004e0e0000000008 */
/*0330*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0370*/ LOP3.LUT R2, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05027812 */
/* 0x040fe200078ec0ff */
/*0380*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff157424 */
/* 0x000fe200078e00ff */
/*0390*/ LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005167812 */
/* 0x000fe400078ec0ff */
/*03a0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*03c0*/ LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009147812 */
/* 0x000fc800078ec0ff */
/*03d0*/ ISETP.GE.U32.AND P1, PT, R20, R22, PT ; /* 0x000000161400720c */
/* 0x000fe20003f26070 */
/*03e0*/ @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004028828 */
/* 0x000e220000000000 */
/*03f0*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0014 */
/*0400*/ SEL R17, R21, 0x63400000, !P1 ; /* 0x6340000015117807 */
/* 0x000fe40004800000 */
/*0410*/ FSETP.GEU.AND P1, PT, |R9|, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x000fe20003f2e200 */
/*0420*/ MUFU.RCP64H R7, R3 ; /* 0x0000000300077308 */
/* 0x001e280000001800 */
/*0430*/ @!P0 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003168812 */
/* 0x000fe200078ec0ff */
/*0440*/ DFMA R10, R6, -R2, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000802 */
/*0450*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0460*/ DFMA R10, R6, R10, R6 ; /* 0x0000000a060a722b */
/* 0x001e0c0000000006 */
/*0470*/ DFMA R6, R10, -R2, 1 ; /* 0x3ff000000a06742b */
/* 0x001e0c0000000802 */
/*0480*/ DFMA R10, R10, R6, R10 ; /* 0x000000060a0a722b */
/* 0x001064000000000a */
/*0490*/ LOP3.LUT R7, R17, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff11077812 */
/* 0x001fe200078ef809 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*04b0*/ @P1 BRA 0x540 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005117812 */
/* 0x002fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R20, R17, PT ; /* 0x000000111400720c */
/* 0x000fc80003f06070 */
/*04f0*/ SEL R17, R21, 0x63400000, !P0 ; /* 0x6340000015117807 */
/* 0x000fc80004000000 */
/*0500*/ LOP3.LUT R17, R17, 0x80000000, R9, 0xf8, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ef809 */
/*0510*/ LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000011117812 */
/* 0x000fcc00078efcff */
/*0520*/ DFMA R6, R6, 2, -R16 ; /* 0x400000000606782b */
/* 0x000e140000000810 */
/*0530*/ LOP3.LUT R23, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007177812 */
/* 0x001fc800078ec0ff */
/*0540*/ IADD3 R18, R23, -0x1, RZ ; /* 0xffffffff17127810 */
/* 0x002fe20007ffe0ff */
/*0550*/ DMUL R16, R10, R6 ; /* 0x000000060a107228 */
/* 0x000e220000000000 */
/*0560*/ IADD3 R24, R22, -0x1, RZ ; /* 0xffffffff16187810 */
/* 0x000fe40007ffe0ff */
/*0570*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*0580*/ DFMA R18, R16, -R2, R6 ; /* 0x800000021012722b */
/* 0x001e220000000006 */
/*0590*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fca0000704470 */
/*05a0*/ DFMA R18, R10, R18, R16 ; /* 0x000000120a12722b */
/* 0x0010500000000010 */
/*05b0*/ @P0 BRA 0x780 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*05c0*/ LOP3.LUT R9, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005097812 */
/* 0x003fc800078ec0ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R20.reuse, R9, PT ; /* 0x000000091400720c */
/* 0x040fe20003f06070 */
/*05e0*/ IMAD.IADD R8, R20, 0x1, -R9 ; /* 0x0000000114087824 */
/* 0x000fc600078e0a09 */
/*05f0*/ SEL R21, R21, 0x63400000, !P0 ; /* 0x6340000015157807 */
/* 0x000fe40004000000 */
/*0600*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*0610*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0620*/ IMAD.IADD R16, R8, 0x1, -R21 ; /* 0x0000000108107824 */
/* 0x000fe400078e0a15 */
/*0630*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0640*/ IADD3 R9, R16, 0x7fe00000, RZ ; /* 0x7fe0000010097810 */
/* 0x000fcc0007ffe0ff */
/*0650*/ DMUL R10, R18, R8 ; /* 0x00000008120a7228 */
/* 0x000e140000000000 */
/*0660*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*0670*/ @P0 BRA 0x8d0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0680*/ DFMA R2, R18, -R2, R6 ; /* 0x800000021202722b */
/* 0x000e220000000006 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*06a0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*06b0*/ LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003057812 */
/* 0x000fc800078e4805 */
/*06c0*/ LOP3.LUT R9, R5, R9, RZ, 0xfc, !PT ; /* 0x0000000905097212 */
/* 0x000fce00078efcff */
/*06d0*/ @!P0 BRA 0x8d0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV R3, RZ, RZ, -R16 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a10 */
/*06f0*/ DMUL.RP R8, R18, R8 ; /* 0x0000000812087228 */
/* 0x000e220000008000 */
/*0700*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0710*/ DFMA R2, R10, -R2, R18 ; /* 0x800000020a02722b */
/* 0x000e460000000012 */
/*0720*/ LOP3.LUT R5, R9, R5, RZ, 0x3c, !PT ; /* 0x0000000509057212 */
/* 0x001fc600078e3cff */
/*0730*/ IADD3 R2, -R16, -0x43300000, RZ ; /* 0xbcd0000010027810 */
/* 0x002fc80007ffe1ff */
/*0740*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0750*/ FSEL R10, R8, R10, !P0 ; /* 0x0000000a080a7208 */
/* 0x000fe40004000000 */
/*0760*/ FSEL R11, R5, R11, !P0 ; /* 0x0000000b050b7208 */
/* 0x000fe20004000000 */
/*0770*/ BRA 0x8d0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0780*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*0790*/ @P0 BRA 0x8b0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*07a0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*07b0*/ @P0 BRA 0x880 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, R23, R22, PT ; /* 0x000000161700720c */
/* 0x000fe20003f05270 */
/*07d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*07e0*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fd400078e00ff */
/*07f0*/ @!P0 BRA 0x8d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.NE.AND P0, PT, R23, 0x7ff00000, PT ; /* 0x7ff000001700780c */
/* 0x000fe40003f05270 */
/*0810*/ LOP3.LUT R11, R9, 0x80000000, R5, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fe400078e4805 */
/*0820*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0830*/ @P0 LOP3.LUT R2, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b020812 */
/* 0x000fe200078efcff */
/*0840*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*0850*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0860*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0002 */
/*0870*/ BRA 0x8d0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050b7812 */
/* 0x000fe200078efcff */
/*0890*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*08a0*/ BRA 0x8d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R11, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090b7812 */
/* 0x000fe200078efcff */
/*08c0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000e */
/*08e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff70002007950 */
/* 0x000fea0003c3ffff */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7addRowsPdPi
.globl _Z7addRowsPdPi
.p2align 8
.type _Z7addRowsPdPi,@function
_Z7addRowsPdPi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x1c
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[6:7], 0x0
s_and_b32 s0, s0, 0xffff
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, s0
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_add_i32 s0, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, 1
s_mul_i32 s0, s3, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s2
s_lshl_b64 s[0:1], s[0:1], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_i32 s7, s3, 1
s_mul_i32 s8, s7, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_clause 0x1
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[1:2], null, s[8:9], s[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[3:4], v[1:2]
s_waitcnt_depctr 0xfff
v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
v_div_scale_f64 v[5:6], vcc_lo, s[0:1], s[8:9], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[5:6], v[3:4]
v_fma_f64 v[1:2], -v[1:2], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[1:2], v[1:2], v[3:4], v[7:8]
v_mov_b32_e32 v3, 0
v_div_fixup_f64 v[1:2], v[1:2], s[8:9], s[0:1]
ds_store_b64 v3, v[1:2]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v0, s2, v0
s_add_i32 s0, s15, s2
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, 1
s_barrier
v_mad_u64_u32 v[1:2], null, s3, s0, v[0:1]
buffer_gl0_inv
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_lshlrev_b64 v[5:6], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[5:6], v[0:1], off
ds_load_b64 v[7:8], v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[2:3], -v[2:3], v[7:8], v[5:6]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7addRowsPdPi
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7addRowsPdPi, .Lfunc_end0-_Z7addRowsPdPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7addRowsPdPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7addRowsPdPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ae33a_00000000-6_addRows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7addRowsPdPiPdPi
.type _Z28__device_stub__Z7addRowsPdPiPdPi, @function
_Z28__device_stub__Z7addRowsPdPiPdPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7addRowsPdPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7addRowsPdPiPdPi, .-_Z28__device_stub__Z7addRowsPdPiPdPi
.globl _Z7addRowsPdPi
.type _Z7addRowsPdPi, @function
_Z7addRowsPdPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7addRowsPdPiPdPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7addRowsPdPi, .-_Z7addRowsPdPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7addRowsPdPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7addRowsPdPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addRows.hip"
.globl _Z22__device_stub__addRowsPdPi # -- Begin function _Z22__device_stub__addRowsPdPi
.p2align 4, 0x90
.type _Z22__device_stub__addRowsPdPi,@function
_Z22__device_stub__addRowsPdPi: # @_Z22__device_stub__addRowsPdPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7addRowsPdPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__addRowsPdPi, .Lfunc_end0-_Z22__device_stub__addRowsPdPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7addRowsPdPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7addRowsPdPi,@object # @_Z7addRowsPdPi
.section .rodata,"a",@progbits
.globl _Z7addRowsPdPi
.p2align 3, 0x0
_Z7addRowsPdPi:
.quad _Z22__device_stub__addRowsPdPi
.size _Z7addRowsPdPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7addRowsPdPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__addRowsPdPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7addRowsPdPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
int main(){
cudaDeviceProp Props;
cudaGetDeviceProperties(&Props,0);
printf("shared mem: %d\n",Props.sharedMemPerBlock);
printf("max threads per block : %d\n",Props.maxThreadsPerBlock);
printf("max blocks: %d\n",Props.maxGridSize[0]);
printf("total Const mem: %d\n",Props.totalConstMem);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
int main(){
cudaDeviceProp Props;
cudaGetDeviceProperties(&Props,0);
printf("shared mem: %d\n",Props.sharedMemPerBlock);
printf("max threads per block : %d\n",Props.maxThreadsPerBlock);
printf("max blocks: %d\n",Props.maxGridSize[0]);
printf("total Const mem: %d\n",Props.totalConstMem);
} | .file "tmpxft_0018bfa1_00000000-6_devProp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "shared mem: %d\n"
.LC1:
.string "max threads per block : %d\n"
.LC2:
.string "max blocks: %d\n"
.LC3:
.string "total Const mem: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movq 296(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rsp), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
int main(){
cudaDeviceProp Props;
cudaGetDeviceProperties(&Props,0);
printf("shared mem: %d\n",Props.sharedMemPerBlock);
printf("max threads per block : %d\n",Props.maxThreadsPerBlock);
printf("max blocks: %d\n",Props.maxGridSize[0]);
printf("total Const mem: %d\n",Props.totalConstMem);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
hipDeviceProp_t Props;
hipGetDeviceProperties(&Props,0);
printf("shared mem: %d\n",Props.sharedMemPerBlock);
printf("max threads per block : %d\n",Props.maxThreadsPerBlock);
printf("max blocks: %d\n",Props.maxGridSize[0]);
printf("total Const mem: %d\n",Props.totalConstMem);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
hipDeviceProp_t Props;
hipGetDeviceProperties(&Props,0);
printf("shared mem: %d\n",Props.sharedMemPerBlock);
printf("max threads per block : %d\n",Props.maxThreadsPerBlock);
printf("max blocks: %d\n",Props.maxGridSize[0]);
printf("total Const mem: %d\n",Props.totalConstMem);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(){
hipDeviceProp_t Props;
hipGetDeviceProperties(&Props,0);
printf("shared mem: %d\n",Props.sharedMemPerBlock);
printf("max threads per block : %d\n",Props.maxThreadsPerBlock);
printf("max blocks: %d\n",Props.maxGridSize[0]);
printf("total Const mem: %d\n",Props.totalConstMem);
} | .text
.file "devProp.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq 304(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "shared mem: %d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "max threads per block : %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "max blocks: %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total Const mem: %d\n"
.size .L.str.3, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018bfa1_00000000-6_devProp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "shared mem: %d\n"
.LC1:
.string "max threads per block : %d\n"
.LC2:
.string "max blocks: %d\n"
.LC3:
.string "total Const mem: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movq 296(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rsp), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "devProp.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq 304(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "shared mem: %d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "max threads per block : %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "max blocks: %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total Const mem: %d\n"
.size .L.str.3, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
const int N = 5;
//data on device
float * dev_matA;
float * dev_matB;
float * dev_res;
//data on host
float * matA = (float *)malloc(N*N*sizeof(float));
float * matB = (float *)malloc(N*N*sizeof(float));
float * res = (float *)malloc(N*N*sizeof(float));
void initMat(float * mat)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
mat[i + j*N] = i + j * N;
}
void printRes()
{
for(int j =0; j <N; j++)
{
cout << endl;
for(int i=0;i<N;i++)
cout << res[j*N + i] << " ";
}
}
__global__ void mat_add(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] + B[x + y*N];
}
__global__ void mat_sub(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] - B[x + y*N];
}
__global__ void mat_mult(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
float result = 0;
for(int i = 0; i < N; i++)
{
result += A[y * N + i] * B[x + i * N];
}
res[x + y*N] = result;
}
void mat_add_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] + B[i];
}
}
void mat_sub_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] - B[i];
}
}
void mat_mult_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
{
float result = 0;
for(int k = 0; k < N; k++)
{
result += A[i*N + k] * B[k*N + j];
}
res[i*N + j] = result;
}
}
int main(int argc, char** argv)
{
dim3 threadsPerBlock(16,16);
dim3 numBlocks((int)ceil((float)N / threadsPerBlock.x), (int)ceil((float)N/threadsPerBlock.y));
cudaMalloc((void**)&dev_matA, N*N*sizeof(float));
cudaMalloc((void**)&dev_matB, N*N*sizeof(float));
cudaMalloc((void**)&dev_res, N*N*sizeof(float));
initMat(matA);
initMat(matB);
cudaMemcpy(dev_matA, matA, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_matB, matB, N*N*sizeof(float), cudaMemcpyHostToDevice);
mat_add<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_sub<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_mult<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_mul test######## ";
printRes();
mat_add_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_sub_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_mult_serial(matA, matB, res);
cout<< endl << "###########serial mat_mul test######## ";
printRes();
int in;
cin >> in;
} | code for sm_80
Function : _Z8mat_multPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R2, R5, c[0x0][0x4], R2 ; /* 0x0000010005027a24 */
/* 0x001fca00078e0202 */
/*0080*/ LEA R7, R2, R2, 0x2 ; /* 0x0000000202077211 */
/* 0x000fe200078e10ff */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R7, R16, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0210 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R16, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0210 */
/*00c0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140404087981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000f28000c1e1900 */
/*0120*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000f68000c1e1900 */
/*0130*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R14, [R4.64+0x50] ; /* 0x00005004040e7981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000f62000c1e1900 */
/*0160*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x000fe20007ffe0ff */
/*0170*/ FFMA R6, R6, R9, RZ ; /* 0x0000000906067223 */
/* 0x004fc800000000ff */
/*0180*/ FFMA R6, R11, R8, R6 ; /* 0x000000080b067223 */
/* 0x008fc80000000006 */
/*0190*/ FFMA R6, R13, R10, R6 ; /* 0x0000000a0d067223 */
/* 0x010fc80000000006 */
/*01a0*/ FFMA R12, R15, R12, R6 ; /* 0x0000000c0f0c7223 */
/* 0x020fe40000000006 */
/*01b0*/ IMAD.WIDE R6, R7, R16, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fc800078e0210 */
/*01c0*/ FFMA R17, R17, R14, R12 ; /* 0x0000000e11117223 */
/* 0x000fca000000000c */
/*01d0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R0, R3, 0x5, R0 ; /* 0x0000000503007824 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
const int N = 5;
//data on device
float * dev_matA;
float * dev_matB;
float * dev_res;
//data on host
float * matA = (float *)malloc(N*N*sizeof(float));
float * matB = (float *)malloc(N*N*sizeof(float));
float * res = (float *)malloc(N*N*sizeof(float));
void initMat(float * mat)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
mat[i + j*N] = i + j * N;
}
void printRes()
{
for(int j =0; j <N; j++)
{
cout << endl;
for(int i=0;i<N;i++)
cout << res[j*N + i] << " ";
}
}
__global__ void mat_add(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] + B[x + y*N];
}
__global__ void mat_sub(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] - B[x + y*N];
}
__global__ void mat_mult(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
float result = 0;
for(int i = 0; i < N; i++)
{
result += A[y * N + i] * B[x + i * N];
}
res[x + y*N] = result;
}
void mat_add_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] + B[i];
}
}
void mat_sub_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] - B[i];
}
}
void mat_mult_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
{
float result = 0;
for(int k = 0; k < N; k++)
{
result += A[i*N + k] * B[k*N + j];
}
res[i*N + j] = result;
}
}
int main(int argc, char** argv)
{
dim3 threadsPerBlock(16,16);
dim3 numBlocks((int)ceil((float)N / threadsPerBlock.x), (int)ceil((float)N/threadsPerBlock.y));
cudaMalloc((void**)&dev_matA, N*N*sizeof(float));
cudaMalloc((void**)&dev_matB, N*N*sizeof(float));
cudaMalloc((void**)&dev_res, N*N*sizeof(float));
initMat(matA);
initMat(matB);
cudaMemcpy(dev_matA, matA, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_matB, matB, N*N*sizeof(float), cudaMemcpyHostToDevice);
mat_add<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_sub<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_mult<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_mul test######## ";
printRes();
mat_add_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_sub_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_mult_serial(matA, matB, res);
cout<< endl << "###########serial mat_mul test######## ";
printRes();
int in;
cin >> in;
} | .file "tmpxft_00002f99_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7initMatPf
.type _Z7initMatPf, @function
_Z7initMatPf:
.LFB3669:
.cfi_startproc
endbr64
movl $25, %ecx
.L4:
leal -25(%rcx), %eax
movq %rdi, %rdx
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addl $5, %eax
addq $20, %rdx
cmpl %ecx, %eax
jne .L5
addq $4, %rdi
addl $1, %ecx
cmpl $30, %ecx
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z7initMatPf, .-_Z7initMatPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z8printResv
.type _Z8printResv, @function
_Z8printResv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $20, %ebp
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %r13
jmp .L13
.L18:
call _ZSt16__throw_bad_castv@PLT
.L10:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L11:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq -20(%rbp), %rbx
.L12:
movq res(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addq $20, %rbp
cmpq $120, %rbp
je .L17
.L13:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L18
cmpb $0, 56(%rbx)
je .L10
movzbl 67(%rbx), %esi
jmp .L11
.L17:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z8printResv, .-_Z8printResv
.globl _Z14mat_add_serialPfS_S_
.type _Z14mat_add_serialPfS_S_, @function
_Z14mat_add_serialPfS_S_:
.LFB3671:
.cfi_startproc
endbr64
movl $0, %eax
.L20:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L20
ret
.cfi_endproc
.LFE3671:
.size _Z14mat_add_serialPfS_S_, .-_Z14mat_add_serialPfS_S_
.globl _Z14mat_sub_serialPfS_S_
.type _Z14mat_sub_serialPfS_S_, @function
_Z14mat_sub_serialPfS_S_:
.LFB3672:
.cfi_startproc
endbr64
movl $0, %eax
.L23:
movss (%rdi,%rax), %xmm0
subss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $100, %rax
jne .L23
ret
.cfi_endproc
.LFE3672:
.size _Z14mat_sub_serialPfS_S_, .-_Z14mat_sub_serialPfS_S_
.globl _Z15mat_mult_serialPfS_S_
.type _Z15mat_mult_serialPfS_S_, @function
_Z15mat_mult_serialPfS_S_:
.LFB3673:
.cfi_startproc
endbr64
leaq 100(%rdx), %r10
.L26:
leaq 100(%rsi), %r8
movl $0, %r9d
.L30:
leaq -100(%r8), %rax
movq %rdi, %rcx
pxor %xmm1, %xmm1
.L27:
movss (%rcx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq $20, %rax
cmpq %r8, %rax
jne .L27
movss %xmm1, (%rdx,%r9,4)
addq $1, %r9
addq $4, %r8
cmpq $5, %r9
jne .L30
addq $20, %rdx
addq $20, %rdi
cmpq %r10, %rdx
jne .L26
ret
.cfi_endproc
.LFE3673:
.size _Z15mat_mult_serialPfS_S_, .-_Z15mat_mult_serialPfS_S_
.globl _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_addPfS_S_PfS_S_:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z30__device_stub__Z7mat_addPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_addPfS_S_PfS_S_
.globl _Z7mat_addPfS_S_
.type _Z7mat_addPfS_S_, @function
_Z7mat_addPfS_S_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7mat_addPfS_S_, .-_Z7mat_addPfS_S_
.globl _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.type _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, @function
_Z30__device_stub__Z7mat_subPfS_S_PfS_S_:
.LFB3701:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z30__device_stub__Z7mat_subPfS_S_PfS_S_, .-_Z30__device_stub__Z7mat_subPfS_S_PfS_S_
.globl _Z7mat_subPfS_S_
.type _Z7mat_subPfS_S_, @function
_Z7mat_subPfS_S_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z7mat_subPfS_S_, .-_Z7mat_subPfS_S_
.globl _Z31__device_stub__Z8mat_multPfS_S_PfS_S_
.type _Z31__device_stub__Z8mat_multPfS_S_PfS_S_, @function
_Z31__device_stub__Z8mat_multPfS_S_PfS_S_:
.LFB3703:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z31__device_stub__Z8mat_multPfS_S_PfS_S_, .-_Z31__device_stub__Z8mat_multPfS_S_PfS_S_
.globl _Z8mat_multPfS_S_
.type _Z8mat_multPfS_S_, @function
_Z8mat_multPfS_S_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8mat_multPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z8mat_multPfS_S_, .-_Z8mat_multPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "###########parallel mat_add test######## "
.align 8
.LC3:
.string "###########parallel mat_mul test######## "
.align 8
.LC4:
.string "###########serial mat_add test######## "
.align 8
.LC5:
.string "###########serial mat_mul test######## "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $100, %esi
leaq dev_matA(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq dev_matB(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq dev_res(%rip), %rdi
call cudaMalloc@PLT
movq matA(%rip), %rdi
call _Z7initMatPf
movq matB(%rip), %rdi
call _Z7initMatPf
movl $1, %ecx
movl $100, %edx
movq matA(%rip), %rsi
movq dev_matA(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq matB(%rip), %rsi
movq dev_matB(%rip), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $16, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L57:
movl $2, %ecx
movl $100, %edx
movq dev_res(%rip), %rsi
movq res(%rip), %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L58:
movl $2, %ecx
movl $100, %edx
movq dev_res(%rip), %rsi
movq res(%rip), %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L59:
movl $2, %ecx
movl $100, %edx
movq dev_res(%rip), %rsi
movq res(%rip), %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movq res(%rip), %rdx
movq matB(%rip), %rsi
movq matA(%rip), %rdi
call _Z14mat_add_serialPfS_S_
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movq res(%rip), %rdx
movq matB(%rip), %rsi
movq matA(%rip), %rdi
call _Z14mat_sub_serialPfS_S_
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
movq res(%rip), %rdx
movq matB(%rip), %rsi
movq matA(%rip), %rdi
call _Z15mat_mult_serialPfS_S_
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z8printResv
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq dev_res(%rip), %rdx
movq dev_matB(%rip), %rsi
movq dev_matA(%rip), %rdi
call _Z30__device_stub__Z7mat_addPfS_S_PfS_S_
jmp .L57
.L63:
movq dev_res(%rip), %rdx
movq dev_matB(%rip), %rsi
movq dev_matA(%rip), %rdi
call _Z30__device_stub__Z7mat_subPfS_S_PfS_S_
jmp .L58
.L64:
movq dev_res(%rip), %rdx
movq dev_matB(%rip), %rsi
movq dev_matA(%rip), %rdi
call _Z31__device_stub__Z8mat_multPfS_S_PfS_S_
jmp .L59
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8mat_multPfS_S_"
.LC7:
.string "_Z7mat_subPfS_S_"
.LC8:
.string "_Z7mat_addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_dev_matA, @function
_GLOBAL__sub_I_dev_matA:
.LFB4335:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %edi
call malloc@PLT
movq %rax, matA(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, matB(%rip)
movl $100, %edi
call malloc@PLT
movq %rax, res(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4335:
.size _GLOBAL__sub_I_dev_matA, .-_GLOBAL__sub_I_dev_matA
.section .init_array
.align 8
.quad _GLOBAL__sub_I_dev_matA
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res
.bss
.align 8
.type res, @object
.size res, 8
res:
.zero 8
.globl matB
.align 8
.type matB, @object
.size matB, 8
matB:
.zero 8
.globl matA
.align 8
.type matA, @object
.size matA, 8
matA:
.zero 8
.globl dev_res
.align 8
.type dev_res, @object
.size dev_res, 8
dev_res:
.zero 8
.globl dev_matB
.align 8
.type dev_matB, @object
.size dev_matB, 8
dev_matB:
.zero 8
.globl dev_matA
.align 8
.type dev_matA, @object
.size dev_matA, 8
dev_matA:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
const int N = 5;
//data on device
float * dev_matA;
float * dev_matB;
float * dev_res;
//data on host
float * matA = (float *)malloc(N*N*sizeof(float));
float * matB = (float *)malloc(N*N*sizeof(float));
float * res = (float *)malloc(N*N*sizeof(float));
void initMat(float * mat)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
mat[i + j*N] = i + j * N;
}
void printRes()
{
for(int j =0; j <N; j++)
{
cout << endl;
for(int i=0;i<N;i++)
cout << res[j*N + i] << " ";
}
}
__global__ void mat_add(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] + B[x + y*N];
}
__global__ void mat_sub(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] - B[x + y*N];
}
__global__ void mat_mult(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
float result = 0;
for(int i = 0; i < N; i++)
{
result += A[y * N + i] * B[x + i * N];
}
res[x + y*N] = result;
}
void mat_add_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] + B[i];
}
}
void mat_sub_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] - B[i];
}
}
void mat_mult_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
{
float result = 0;
for(int k = 0; k < N; k++)
{
result += A[i*N + k] * B[k*N + j];
}
res[i*N + j] = result;
}
}
int main(int argc, char** argv)
{
dim3 threadsPerBlock(16,16);
dim3 numBlocks((int)ceil((float)N / threadsPerBlock.x), (int)ceil((float)N/threadsPerBlock.y));
cudaMalloc((void**)&dev_matA, N*N*sizeof(float));
cudaMalloc((void**)&dev_matB, N*N*sizeof(float));
cudaMalloc((void**)&dev_res, N*N*sizeof(float));
initMat(matA);
initMat(matB);
cudaMemcpy(dev_matA, matA, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_matB, matB, N*N*sizeof(float), cudaMemcpyHostToDevice);
mat_add<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_sub<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_mult<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
cudaMemcpy(res, dev_res, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_mul test######## ";
printRes();
mat_add_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_sub_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_mult_serial(matA, matB, res);
cout<< endl << "###########serial mat_mul test######## ";
printRes();
int in;
cin >> in;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
const int N = 5;
//data on device
float * dev_matA;
float * dev_matB;
float * dev_res;
//data on host
float * matA = (float *)malloc(N*N*sizeof(float));
float * matB = (float *)malloc(N*N*sizeof(float));
float * res = (float *)malloc(N*N*sizeof(float));
void initMat(float * mat)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
mat[i + j*N] = i + j * N;
}
void printRes()
{
for(int j =0; j <N; j++)
{
cout << endl;
for(int i=0;i<N;i++)
cout << res[j*N + i] << " ";
}
}
__global__ void mat_add(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] + B[x + y*N];
}
__global__ void mat_sub(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] - B[x + y*N];
}
__global__ void mat_mult(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
float result = 0;
for(int i = 0; i < N; i++)
{
result += A[y * N + i] * B[x + i * N];
}
res[x + y*N] = result;
}
void mat_add_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] + B[i];
}
}
void mat_sub_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] - B[i];
}
}
void mat_mult_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
{
float result = 0;
for(int k = 0; k < N; k++)
{
result += A[i*N + k] * B[k*N + j];
}
res[i*N + j] = result;
}
}
int main(int argc, char** argv)
{
dim3 threadsPerBlock(16,16);
dim3 numBlocks((int)ceil((float)N / threadsPerBlock.x), (int)ceil((float)N/threadsPerBlock.y));
hipMalloc((void**)&dev_matA, N*N*sizeof(float));
hipMalloc((void**)&dev_matB, N*N*sizeof(float));
hipMalloc((void**)&dev_res, N*N*sizeof(float));
initMat(matA);
initMat(matB);
hipMemcpy(dev_matA, matA, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_matB, matB, N*N*sizeof(float), hipMemcpyHostToDevice);
mat_add<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_sub<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_mult<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_mul test######## ";
printRes();
mat_add_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_sub_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_mult_serial(matA, matB, res);
cout<< endl << "###########serial mat_mul test######## ";
printRes();
int in;
cin >> in;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
const int N = 5;
//data on device
float * dev_matA;
float * dev_matB;
float * dev_res;
//data on host
float * matA = (float *)malloc(N*N*sizeof(float));
float * matB = (float *)malloc(N*N*sizeof(float));
float * res = (float *)malloc(N*N*sizeof(float));
void initMat(float * mat)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
mat[i + j*N] = i + j * N;
}
void printRes()
{
for(int j =0; j <N; j++)
{
cout << endl;
for(int i=0;i<N;i++)
cout << res[j*N + i] << " ";
}
}
__global__ void mat_add(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] + B[x + y*N];
}
__global__ void mat_sub(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] - B[x + y*N];
}
__global__ void mat_mult(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
float result = 0;
for(int i = 0; i < N; i++)
{
result += A[y * N + i] * B[x + i * N];
}
res[x + y*N] = result;
}
void mat_add_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] + B[i];
}
}
void mat_sub_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] - B[i];
}
}
void mat_mult_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
{
float result = 0;
for(int k = 0; k < N; k++)
{
result += A[i*N + k] * B[k*N + j];
}
res[i*N + j] = result;
}
}
int main(int argc, char** argv)
{
dim3 threadsPerBlock(16,16);
dim3 numBlocks((int)ceil((float)N / threadsPerBlock.x), (int)ceil((float)N/threadsPerBlock.y));
hipMalloc((void**)&dev_matA, N*N*sizeof(float));
hipMalloc((void**)&dev_matB, N*N*sizeof(float));
hipMalloc((void**)&dev_res, N*N*sizeof(float));
initMat(matA);
initMat(matB);
hipMemcpy(dev_matA, matA, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_matB, matB, N*N*sizeof(float), hipMemcpyHostToDevice);
mat_add<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_sub<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_mult<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_mul test######## ";
printRes();
mat_add_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_sub_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_mult_serial(matA, matB, res);
cout<< endl << "###########serial mat_mul test######## ";
printRes();
int in;
cin >> in;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_
.globl _Z7mat_addPfS_S_
.p2align 8
.type _Z7mat_addPfS_S_,@function
_Z7mat_addPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v2, 2, v2
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_, .Lfunc_end0-_Z7mat_addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 8
.type _Z7mat_subPfS_S_,@function
_Z7mat_subPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v2, 2, v2
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_, .Lfunc_end1-_Z7mat_subPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8mat_multPfS_S_
.globl _Z8mat_multPfS_S_
.p2align 8
.type _Z8mat_multPfS_S_,@function
_Z8mat_multPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v1, 2, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
v_add_co_u32 v3, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_1:
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s2, v2
s_add_i32 s2, s2, 5
s_cmp_eq_u32 s2, 25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v7, v5
s_cbranch_scc0 .LBB2_1
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, 5, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8mat_multPfS_S_, .Lfunc_end2-_Z8mat_multPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8mat_multPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
const int N = 5;
//data on device
float * dev_matA;
float * dev_matB;
float * dev_res;
//data on host
float * matA = (float *)malloc(N*N*sizeof(float));
float * matB = (float *)malloc(N*N*sizeof(float));
float * res = (float *)malloc(N*N*sizeof(float));
void initMat(float * mat)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
mat[i + j*N] = i + j * N;
}
void printRes()
{
for(int j =0; j <N; j++)
{
cout << endl;
for(int i=0;i<N;i++)
cout << res[j*N + i] << " ";
}
}
__global__ void mat_add(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] + B[x + y*N];
}
__global__ void mat_sub(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
res[x + y*N] = A[x + y*N] - B[x + y*N];
}
__global__ void mat_mult(float * A, float * B, float * res)
{
int x = threadIdx.x + blockIdx.x *blockDim.x;
int y = threadIdx.y + blockIdx.y *blockDim.y;
float result = 0;
for(int i = 0; i < N; i++)
{
result += A[y * N + i] * B[x + i * N];
}
res[x + y*N] = result;
}
void mat_add_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] + B[i];
}
}
void mat_sub_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N * N; i++)
{
res[i] = A[i] - B[i];
}
}
void mat_mult_serial(float * A, float * B, float * res)
{
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
{
float result = 0;
for(int k = 0; k < N; k++)
{
result += A[i*N + k] * B[k*N + j];
}
res[i*N + j] = result;
}
}
int main(int argc, char** argv)
{
dim3 threadsPerBlock(16,16);
dim3 numBlocks((int)ceil((float)N / threadsPerBlock.x), (int)ceil((float)N/threadsPerBlock.y));
hipMalloc((void**)&dev_matA, N*N*sizeof(float));
hipMalloc((void**)&dev_matB, N*N*sizeof(float));
hipMalloc((void**)&dev_res, N*N*sizeof(float));
initMat(matA);
initMat(matB);
hipMemcpy(dev_matA, matA, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_matB, matB, N*N*sizeof(float), hipMemcpyHostToDevice);
mat_add<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_sub<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_add test######## ";
printRes();
mat_mult<<<numBlocks, threadsPerBlock>>>(dev_matA, dev_matB, dev_res);
hipMemcpy(res, dev_res, N*N*sizeof(float), hipMemcpyDeviceToHost);
cout<< endl << "###########parallel mat_mul test######## ";
printRes();
mat_add_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_sub_serial(matA, matB, res);
cout<< endl << "###########serial mat_add test######## ";
printRes();
mat_mult_serial(matA, matB, res);
cout<< endl << "###########serial mat_mul test######## ";
printRes();
int in;
cin >> in;
} | .text
.file "matrix_math.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7initMatPf # -- Begin function _Z7initMatPf
.p2align 4, 0x90
.type _Z7initMatPf,@function
_Z7initMatPf: # @_Z7initMatPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rcx), %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
addq $5, %rcx
cmpq $25, %rcx
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $4, %rdi
cmpq $5, %rax
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z7initMatPf, .Lfunc_end0-_Z7initMatPf
.cfi_endproc
# -- End function
.globl _Z8printResv # -- Begin function _Z8printResv
.p2align 4, 0x90
.type _Z8printResv,@function
_Z8printResv: # @_Z8printResv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_9
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movq res(%rip), %rax
addq %r14, %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $5, %rbx
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $20, %r14
cmpq $5, %r15
jne .LBB1_1
# %bb.8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z8printResv, .Lfunc_end1-_Z8printResv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_addPfS_S_ # -- Begin function _Z22__device_stub__mat_addPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_,@function
_Z22__device_stub__mat_addPfS_S_: # @_Z22__device_stub__mat_addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__mat_addPfS_S_, .Lfunc_end2-_Z22__device_stub__mat_addPfS_S_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_subPfS_S_ # -- Begin function _Z22__device_stub__mat_subPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mat_subPfS_S_,@function
_Z22__device_stub__mat_subPfS_S_: # @_Z22__device_stub__mat_subPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__mat_subPfS_S_, .Lfunc_end3-_Z22__device_stub__mat_subPfS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__mat_multPfS_S_ # -- Begin function _Z23__device_stub__mat_multPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__mat_multPfS_S_,@function
_Z23__device_stub__mat_multPfS_S_: # @_Z23__device_stub__mat_multPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z23__device_stub__mat_multPfS_S_, .Lfunc_end4-_Z23__device_stub__mat_multPfS_S_
.cfi_endproc
# -- End function
.globl _Z14mat_add_serialPfS_S_ # -- Begin function _Z14mat_add_serialPfS_S_
.p2align 4, 0x90
.type _Z14mat_add_serialPfS_S_,@function
_Z14mat_add_serialPfS_S_: # @_Z14mat_add_serialPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB5_1
# %bb.2:
retq
.Lfunc_end5:
.size _Z14mat_add_serialPfS_S_, .Lfunc_end5-_Z14mat_add_serialPfS_S_
.cfi_endproc
# -- End function
.globl _Z14mat_sub_serialPfS_S_ # -- Begin function _Z14mat_sub_serialPfS_S_
.p2align 4, 0x90
.type _Z14mat_sub_serialPfS_S_,@function
_Z14mat_sub_serialPfS_S_: # @_Z14mat_sub_serialPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB6_1
# %bb.2:
retq
.Lfunc_end6:
.size _Z14mat_sub_serialPfS_S_, .Lfunc_end6-_Z14mat_sub_serialPfS_S_
.cfi_endproc
# -- End function
.globl _Z15mat_mult_serialPfS_S_ # -- Begin function _Z15mat_mult_serialPfS_S_
.p2align 4, 0x90
.type _Z15mat_mult_serialPfS_S_,@function
_Z15mat_mult_serialPfS_S_: # @_Z15mat_mult_serialPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
# Child Loop BB7_3 Depth 3
leaq (%rax,%rax,4), %rcx
leaq (%rdx,%rcx,4), %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB7_2: # %.preheader
# Parent Loop BB7_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_3 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_1 Depth=1
# Parent Loop BB7_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $20, %r10
cmpq $5, %r11
jne .LBB7_3
# %bb.4: # in Loop: Header=BB7_2 Depth=2
movss %xmm0, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $5, %r9
jne .LBB7_2
# %bb.5: # in Loop: Header=BB7_1 Depth=1
incq %rax
addq $20, %rdi
cmpq $5, %rax
jne .LBB7_1
# %bb.6:
retq
.Lfunc_end7:
.size _Z15mat_mult_serialPfS_S_, .Lfunc_end7-_Z15mat_mult_serialPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $dev_matA, %edi
movl $100, %esi
callq hipMalloc
movl $dev_matB, %edi
movl $100, %esi
callq hipMalloc
movl $dev_res, %edi
movl $100, %esi
callq hipMalloc
xorl %eax, %eax
movq matA(%rip), %rsi
movq %rsi, %rcx
.p2align 4, 0x90
.LBB8_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_2: # Parent Loop BB8_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rcx,%rdx,4)
addq $5, %rdx
cmpq $25, %rdx
jne .LBB8_2
# %bb.3: # in Loop: Header=BB8_1 Depth=1
incq %rax
addq $4, %rcx
cmpq $5, %rax
jne .LBB8_1
# %bb.4: # %_Z7initMatPf.exit
movq matB(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_5: # %.preheader.i25
# =>This Loop Header: Depth=1
# Child Loop BB8_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_6: # Parent Loop BB8_5 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $5, %rdx
cmpq $25, %rdx
jne .LBB8_6
# %bb.7: # in Loop: Header=BB8_5 Depth=1
incq %rcx
addq $4, %rax
cmpq $5, %rcx
jne .LBB8_5
# %bb.8: # %_Z7initMatPf.exit32
movabsq $68719476752, %rbx # imm = 0x1000000010
movabsq $4294967297, %r14 # imm = 0x100000001
movq dev_matA(%rip), %rdi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_matB(%rip), %rdi
movq matB(%rip), %rsi
movl $100, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_10
# %bb.9:
movq dev_matA(%rip), %rax
movq dev_matB(%rip), %rcx
movq dev_res(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_10:
movq res(%rip), %rdi
movq dev_res(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB8_49
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB8_13
# %bb.12:
movzbl 67(%r15), %eax
jmp .LBB8_14
.LBB8_13:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.3, %esi
movl $41, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_16
# %bb.15:
movq dev_matA(%rip), %rax
movq dev_matB(%rip), %rcx
movq dev_res(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mat_subPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_16:
movq res(%rip), %rdi
movq dev_res(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB8_49
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB8_19
# %bb.18:
movzbl 67(%r15), %eax
jmp .LBB8_20
.LBB8_19:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.3, %esi
movl $41, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_22
# %bb.21:
movq dev_matA(%rip), %rax
movq dev_matB(%rip), %rcx
movq dev_res(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_22:
movq res(%rip), %rdi
movq dev_res(%rip), %rsi
movl $100, %edx
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbx)
je .LBB8_25
# %bb.24:
movzbl 67(%rbx), %eax
jmp .LBB8_26
.LBB8_25:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.4, %esi
movl $41, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq matA(%rip), %rax
movq matB(%rip), %rcx
xorl %edx, %edx
movq res(%rip), %rsi
.p2align 4, 0x90
.LBB8_27: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%rdx,4), %xmm0
movss %xmm0, (%rsi,%rdx,4)
incq %rdx
cmpq $25, %rdx
jne .LBB8_27
# %bb.28: # %_Z14mat_add_serialPfS_S_.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%rbx)
je .LBB8_31
# %bb.30:
movzbl 67(%rbx), %eax
jmp .LBB8_32
.LBB8_31:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.5, %esi
movl $39, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq matA(%rip), %rax
movq matB(%rip), %rcx
xorl %edx, %edx
movq res(%rip), %rsi
.p2align 4, 0x90
.LBB8_33: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rcx,%rdx,4), %xmm0
movss %xmm0, (%rsi,%rdx,4)
incq %rdx
cmpq $25, %rdx
jne .LBB8_33
# %bb.34: # %_Z14mat_sub_serialPfS_S_.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%rbx)
je .LBB8_37
# %bb.36:
movzbl 67(%rbx), %eax
jmp .LBB8_38
.LBB8_37:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.5, %esi
movl $39, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
movq matA(%rip), %rax
movq matB(%rip), %rcx
xorl %edx, %edx
movq res(%rip), %rsi
.p2align 4, 0x90
.LBB8_39: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB8_40 Depth 2
# Child Loop BB8_41 Depth 3
leaq (%rdx,%rdx,4), %rdi
leaq (%rsi,%rdi,4), %rdi
movq %rcx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB8_40: # %.preheader.i51
# Parent Loop BB8_39 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_41 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB8_41: # Parent Loop BB8_39 Depth=1
# Parent Loop BB8_40 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $20, %r10
cmpq $5, %r11
jne .LBB8_41
# %bb.42: # in Loop: Header=BB8_40 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq $5, %r9
jne .LBB8_40
# %bb.43: # in Loop: Header=BB8_39 Depth=1
incq %rdx
addq $20, %rax
cmpq $5, %rdx
jne .LBB8_39
# %bb.44: # %_Z15mat_mult_serialPfS_S_.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_49
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB8_47
# %bb.46:
movzbl 67(%rbx), %eax
jmp .LBB8_48
.LBB8_47:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.6, %esi
movl $39, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z8printResv
leaq 80(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB8_49:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_matrix_math.hip
.type _GLOBAL__sub_I_matrix_math.hip,@function
_GLOBAL__sub_I_matrix_math.hip: # @_GLOBAL__sub_I_matrix_math.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $100, %edi
callq malloc
movq %rax, matA(%rip)
movl $100, %edi
callq malloc
movq %rax, matB(%rip)
movl $100, %edi
callq malloc
movq %rax, res(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _GLOBAL__sub_I_matrix_math.hip, .Lfunc_end9-_GLOBAL__sub_I_matrix_math.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_subPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mat_multPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_matA,@object # @dev_matA
.bss
.globl dev_matA
.p2align 3, 0x0
dev_matA:
.quad 0
.size dev_matA, 8
.type dev_matB,@object # @dev_matB
.globl dev_matB
.p2align 3, 0x0
dev_matB:
.quad 0
.size dev_matB, 8
.type dev_res,@object # @dev_res
.globl dev_res
.p2align 3, 0x0
dev_res:
.quad 0
.size dev_res, 8
.type matA,@object # @matA
.globl matA
.p2align 3, 0x0
matA:
.quad 0
.size matA, 8
.type matB,@object # @matB
.globl matB
.p2align 3, 0x0
matB:
.quad 0
.size matB, 8
.type res,@object # @res
.globl res
.p2align 3, 0x0
res:
.quad 0
.size res, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z7mat_addPfS_S_,@object # @_Z7mat_addPfS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_addPfS_S_
.p2align 3, 0x0
_Z7mat_addPfS_S_:
.quad _Z22__device_stub__mat_addPfS_S_
.size _Z7mat_addPfS_S_, 8
.type _Z7mat_subPfS_S_,@object # @_Z7mat_subPfS_S_
.globl _Z7mat_subPfS_S_
.p2align 3, 0x0
_Z7mat_subPfS_S_:
.quad _Z22__device_stub__mat_subPfS_S_
.size _Z7mat_subPfS_S_, 8
.type _Z8mat_multPfS_S_,@object # @_Z8mat_multPfS_S_
.globl _Z8mat_multPfS_S_
.p2align 3, 0x0
_Z8mat_multPfS_S_:
.quad _Z23__device_stub__mat_multPfS_S_
.size _Z8mat_multPfS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "###########parallel mat_add test######## "
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "###########parallel mat_mul test######## "
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "###########serial mat_add test######## "
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "###########serial mat_mul test######## "
.size .L.str.6, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_addPfS_S_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mat_subPfS_S_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8mat_multPfS_S_"
.size .L__unnamed_3, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_matrix_math.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_addPfS_S_
.addrsig_sym _Z22__device_stub__mat_subPfS_S_
.addrsig_sym _Z23__device_stub__mat_multPfS_S_
.addrsig_sym _GLOBAL__sub_I_matrix_math.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_matA
.addrsig_sym dev_matB
.addrsig_sym dev_res
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7mat_addPfS_S_
.addrsig_sym _Z7mat_subPfS_S_
.addrsig_sym _Z8mat_multPfS_S_
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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